drivers/infiniband/hw/mlx5/qp.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <rdma/ib_umem.h>
  35 #include <rdma/ib_cache.h>
  36 #include <rdma/ib_user_verbs.h>
  37 #include "mlx5_ib.h"
  38
  39 /* not supported currently */
  40 static int wq_signature;
  41
  42 enum {
  43         MLX5_IB_ACK_REQ_FREQ    = 8,
  44 };
  45
  46 enum {
  47         MLX5_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  48         MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  49         MLX5_IB_LINK_TYPE_IB            = 0,
  50         MLX5_IB_LINK_TYPE_ETH           = 1
  51 };
  52
  53 enum {
  54         MLX5_IB_SQ_STRIDE       = 6,
  55         MLX5_IB_CACHE_LINE_SIZE = 64,
  56 };
  57
  58 static const u32 mlx5_ib_opcode[] = {
  59         [IB_WR_SEND]                            = MLX5_OPCODE_SEND,
  60         [IB_WR_LSO]                             = MLX5_OPCODE_LSO,
  61         [IB_WR_SEND_WITH_IMM]                   = MLX5_OPCODE_SEND_IMM,
  62         [IB_WR_RDMA_WRITE]                      = MLX5_OPCODE_RDMA_WRITE,
  63         [IB_WR_RDMA_WRITE_WITH_IMM]             = MLX5_OPCODE_RDMA_WRITE_IMM,
  64         [IB_WR_RDMA_READ]                       = MLX5_OPCODE_RDMA_READ,
  65         [IB_WR_ATOMIC_CMP_AND_SWP]              = MLX5_OPCODE_ATOMIC_CS,
  66         [IB_WR_ATOMIC_FETCH_AND_ADD]            = MLX5_OPCODE_ATOMIC_FA,
  67         [IB_WR_SEND_WITH_INV]                   = MLX5_OPCODE_SEND_INVAL,
  68         [IB_WR_LOCAL_INV]                       = MLX5_OPCODE_UMR,
  69         [IB_WR_REG_MR]                          = MLX5_OPCODE_UMR,
  70         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = MLX5_OPCODE_ATOMIC_MASKED_CS,
  71         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = MLX5_OPCODE_ATOMIC_MASKED_FA,
  72         [MLX5_IB_WR_UMR]                        = MLX5_OPCODE_UMR,
  73 };
  74
  75 struct mlx5_wqe_eth_pad {
  76         u8 rsvd0[16];
  77 };
  78
  79 enum raw_qp_set_mask_map {
  80         MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID         = 1UL << 0,
  81 };
  82
  83 struct mlx5_modify_raw_qp_param {
  84         u16 operation;
  85
  86         u32 set_mask; /* raw_qp_set_mask_map */
  87         u8 rq_q_ctr_id;
  88 };
  89
  90 static void get_cqs(enum ib_qp_type qp_type,
  91                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
  92                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
  93
  94 static int is_qp0(enum ib_qp_type qp_type)
  95 {
  96         return qp_type == IB_QPT_SMI;
  97 }
  98
  99 static int is_sqp(enum ib_qp_type qp_type)
 100 {
 101         return is_qp0(qp_type) || is_qp1(qp_type);
 102 }
 103
 104 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
 105 {
 106         return mlx5_buf_offset(&qp->buf, offset);
 107 }
 108
 109 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
 110 {
 111         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 112 }
 113
 114 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
 115 {
 116         return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
 117 }
 118
 119 /**
 120  * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
 121  *
 122  * @qp: QP to copy from.
 123  * @send: copy from the send queue when non-zero, use the receive queue
 124  *        otherwise.
 125  * @wqe_index:  index to start copying from. For send work queues, the
 126  *              wqe_index is in units of MLX5_SEND_WQE_BB.
 127  *              For receive work queue, it is the number of work queue
 128  *              element in the queue.
 129  * @buffer: destination buffer.
 130  * @length: maximum number of bytes to copy.
 131  *
 132  * Copies at least a single WQE, but may copy more data.
 133  *
 134  * Return: the number of bytes copied, or an error code.
 135  */
 136 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
 137                           void *buffer, u32 length,
 138                           struct mlx5_ib_qp_base *base)
 139 {
 140         struct ib_device *ibdev = qp->ibqp.device;
 141         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 142         struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
 143         size_t offset;
 144         size_t wq_end;
 145         struct ib_umem *umem = base->ubuffer.umem;
 146         u32 first_copy_length;
 147         int wqe_length;
 148         int ret;
 149
 150         if (wq->wqe_cnt == 0) {
 151                 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
 152                             qp->ibqp.qp_type);
 153                 return -EINVAL;
 154         }
 155
 156         offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
 157         wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
 158
 159         if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
 160                 return -EINVAL;
 161
 162         if (offset > umem->length ||
 163             (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
 164                 return -EINVAL;
 165
 166         first_copy_length = min_t(u32, offset + length, wq_end) - offset;
 167         ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
 168         if (ret)
 169                 return ret;
 170
 171         if (send) {
 172                 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
 173                 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 174
 175                 wqe_length = ds * MLX5_WQE_DS_UNITS;
 176         } else {
 177                 wqe_length = 1 << wq->wqe_shift;
 178         }
 179
 180         if (wqe_length <= first_copy_length)
 181                 return first_copy_length;
 182
 183         ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
 184                                 wqe_length - first_copy_length);
 185         if (ret)
 186                 return ret;
 187
 188         return wqe_length;
 189 }
 190
 191 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
 192 {
 193         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 194         struct ib_event event;
 195
 196         if (type == MLX5_EVENT_TYPE_PATH_MIG) {
 197                 /* This event is only valid for trans_qps */
 198                 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
 199         }
 200
 201         if (ibqp->event_handler) {
 202                 event.device     = ibqp->device;
 203                 event.element.qp = ibqp;
 204                 switch (type) {
 205                 case MLX5_EVENT_TYPE_PATH_MIG:
 206                         event.event = IB_EVENT_PATH_MIG;
 207                         break;
 208                 case MLX5_EVENT_TYPE_COMM_EST:
 209                         event.event = IB_EVENT_COMM_EST;
 210                         break;
 211                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 212                         event.event = IB_EVENT_SQ_DRAINED;
 213                         break;
 214                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 215                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 216                         break;
 217                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 218                         event.event = IB_EVENT_QP_FATAL;
 219                         break;
 220                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 221                         event.event = IB_EVENT_PATH_MIG_ERR;
 222                         break;
 223                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 224                         event.event = IB_EVENT_QP_REQ_ERR;
 225                         break;
 226                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 227                         event.event = IB_EVENT_QP_ACCESS_ERR;
 228                         break;
 229                 default:
 230                         pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
 231                         return;
 232                 }
 233
 234                 ibqp->event_handler(&event, ibqp->qp_context);
 235         }
 236 }
 237
 238 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
 239                        int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
 240 {
 241         int wqe_size;
 242         int wq_size;
 243
 244         /* Sanity check RQ size before proceeding */
 245         if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
 246                 return -EINVAL;
 247
 248         if (!has_rq) {
 249                 qp->rq.max_gs = 0;
 250                 qp->rq.wqe_cnt = 0;
 251                 qp->rq.wqe_shift = 0;
 252                 cap->max_recv_wr = 0;
 253                 cap->max_recv_sge = 0;
 254         } else {
 255                 if (ucmd) {
 256                         qp->rq.wqe_cnt = ucmd->rq_wqe_count;
 257                         qp->rq.wqe_shift = ucmd->rq_wqe_shift;
 258                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 259                         qp->rq.max_post = qp->rq.wqe_cnt;
 260                 } else {
 261                         wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
 262                         wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
 263                         wqe_size = roundup_pow_of_two(wqe_size);
 264                         wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
 265                         wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
 266                         qp->rq.wqe_cnt = wq_size / wqe_size;
 267                         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
 268                                 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
 269                                             wqe_size,
 270                                             MLX5_CAP_GEN(dev->mdev,
 271                                                          max_wqe_sz_rq));
 272                                 return -EINVAL;
 273                         }
 274                         qp->rq.wqe_shift = ilog2(wqe_size);
 275                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 276                         qp->rq.max_post = qp->rq.wqe_cnt;
 277                 }
 278         }
 279
 280         return 0;
 281 }
 282
 283 static int sq_overhead(struct ib_qp_init_attr *attr)
 284 {
 285         int size = 0;
 286
 287         switch (attr->qp_type) {
 288         case IB_QPT_XRC_INI:
 289                 size += sizeof(struct mlx5_wqe_xrc_seg);
 290                 /* fall through */
 291         case IB_QPT_RC:
 292                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 293                         max(sizeof(struct mlx5_wqe_atomic_seg) +
 294                             sizeof(struct mlx5_wqe_raddr_seg),
 295                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 296                             sizeof(struct mlx5_mkey_seg));
 297                 break;
 298
 299         case IB_QPT_XRC_TGT:
 300                 return 0;
 301
 302         case IB_QPT_UC:
 303                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 304                         max(sizeof(struct mlx5_wqe_raddr_seg),
 305                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 306                             sizeof(struct mlx5_mkey_seg));
 307                 break;
 308
 309         case IB_QPT_UD:
 310                 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 311                         size += sizeof(struct mlx5_wqe_eth_pad) +
 312                                 sizeof(struct mlx5_wqe_eth_seg);
 313                 /* fall through */
 314         case IB_QPT_SMI:
 315         case MLX5_IB_QPT_HW_GSI:
 316                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 317                         sizeof(struct mlx5_wqe_datagram_seg);
 318                 break;
 319
 320         case MLX5_IB_QPT_REG_UMR:
 321                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 322                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 323                         sizeof(struct mlx5_mkey_seg);
 324                 break;
 325
 326         default:
 327                 return -EINVAL;
 328         }
 329
 330         return size;
 331 }
 332
 333 static int calc_send_wqe(struct ib_qp_init_attr *attr)
 334 {
 335         int inl_size = 0;
 336         int size;
 337
 338         size = sq_overhead(attr);
 339         if (size < 0)
 340                 return size;
 341
 342         if (attr->cap.max_inline_data) {
 343                 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
 344                         attr->cap.max_inline_data;
 345         }
 346
 347         size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
 348         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
 349             ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
 350                         return MLX5_SIG_WQE_SIZE;
 351         else
 352                 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
 353 }
 354
 355 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
 356                         struct mlx5_ib_qp *qp)
 357 {
 358         int wqe_size;
 359         int wq_size;
 360
 361         if (!attr->cap.max_send_wr)
 362                 return 0;
 363
 364         wqe_size = calc_send_wqe(attr);
 365         mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
 366         if (wqe_size < 0)
 367                 return wqe_size;
 368
 369         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 370                 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
 371                             wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 372                 return -EINVAL;
 373         }
 374
 375         qp->max_inline_data = wqe_size - sq_overhead(attr) -
 376                               sizeof(struct mlx5_wqe_inline_seg);
 377         attr->cap.max_inline_data = qp->max_inline_data;
 378
 379         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
 380                 qp->signature_en = true;
 381
 382         wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
 383         qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
 384         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 385                 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n",
 386                             qp->sq.wqe_cnt,
 387                             1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 388                 return -ENOMEM;
 389         }
 390         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 391         qp->sq.max_gs = attr->cap.max_send_sge;
 392         qp->sq.max_post = wq_size / wqe_size;
 393         attr->cap.max_send_wr = qp->sq.max_post;
 394
 395         return wq_size;
 396 }
 397
 398 static int set_user_buf_size(struct mlx5_ib_dev *dev,
 399                             struct mlx5_ib_qp *qp,
 400                             struct mlx5_ib_create_qp *ucmd,
 401                             struct mlx5_ib_qp_base *base,
 402                             struct ib_qp_init_attr *attr)
 403 {
 404         int desc_sz = 1 << qp->sq.wqe_shift;
 405
 406         if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 407                 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
 408                              desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 409                 return -EINVAL;
 410         }
 411
 412         if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
 413                 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
 414                              ucmd->sq_wqe_count, ucmd->sq_wqe_count);
 415                 return -EINVAL;
 416         }
 417
 418         qp->sq.wqe_cnt = ucmd->sq_wqe_count;
 419
 420         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 421                 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
 422                              qp->sq.wqe_cnt,
 423                              1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 424                 return -EINVAL;
 425         }
 426
 427         if (attr->qp_type == IB_QPT_RAW_PACKET) {
 428                 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 429                 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
 430         } else {
 431                 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 432                                          (qp->sq.wqe_cnt << 6);
 433         }
 434
 435         return 0;
 436 }
 437
 438 static int qp_has_rq(struct ib_qp_init_attr *attr)
 439 {
 440         if (attr->qp_type == IB_QPT_XRC_INI ||
 441             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
 442             attr->qp_type == MLX5_IB_QPT_REG_UMR ||
 443             !attr->cap.max_recv_wr)
 444                 return 0;
 445
 446         return 1;
 447 }
 448
 449 static int first_med_uuar(void)
 450 {
 451         return 1;
 452 }
 453
 454 static int next_uuar(int n)
 455 {
 456         n++;
 457
 458         while (((n % 4) & 2))
 459                 n++;
 460
 461         return n;
 462 }
 463
 464 static int num_med_uuar(struct mlx5_uuar_info *uuari)
 465 {
 466         int n;
 467
 468         n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE -
 469                 uuari->num_low_latency_uuars - 1;
 470
 471         return n >= 0 ? n : 0;
 472 }
 473
 474 static int max_uuari(struct mlx5_uuar_info *uuari)
 475 {
 476         return uuari->num_uars * 4;
 477 }
 478
 479 static int first_hi_uuar(struct mlx5_uuar_info *uuari)
 480 {
 481         int med;
 482         int i;
 483         int t;
 484
 485         med = num_med_uuar(uuari);
 486         for (t = 0, i = first_med_uuar();; i = next_uuar(i)) {
 487                 t++;
 488                 if (t == med)
 489                         return next_uuar(i);
 490         }
 491
 492         return 0;
 493 }
 494
 495 static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari)
 496 {
 497         int i;
 498
 499         for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) {
 500                 if (!test_bit(i, uuari->bitmap)) {
 501                         set_bit(i, uuari->bitmap);
 502                         uuari->count[i]++;
 503                         return i;
 504                 }
 505         }
 506
 507         return -ENOMEM;
 508 }
 509
 510 static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari)
 511 {
 512         int minidx = first_med_uuar();
 513         int i;
 514
 515         for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) {
 516                 if (uuari->count[i] < uuari->count[minidx])
 517                         minidx = i;
 518         }
 519
 520         uuari->count[minidx]++;
 521         return minidx;
 522 }
 523
 524 static int alloc_uuar(struct mlx5_uuar_info *uuari,
 525                       enum mlx5_ib_latency_class lat)
 526 {
 527         int uuarn = -EINVAL;
 528
 529         mutex_lock(&uuari->lock);
 530         switch (lat) {
 531         case MLX5_IB_LATENCY_CLASS_LOW:
 532                 uuarn = 0;
 533                 uuari->count[uuarn]++;
 534                 break;
 535
 536         case MLX5_IB_LATENCY_CLASS_MEDIUM:
 537                 if (uuari->ver < 2)
 538                         uuarn = -ENOMEM;
 539                 else
 540                         uuarn = alloc_med_class_uuar(uuari);
 541                 break;
 542
 543         case MLX5_IB_LATENCY_CLASS_HIGH:
 544                 if (uuari->ver < 2)
 545                         uuarn = -ENOMEM;
 546                 else
 547                         uuarn = alloc_high_class_uuar(uuari);
 548                 break;
 549
 550         case MLX5_IB_LATENCY_CLASS_FAST_PATH:
 551                 uuarn = 2;
 552                 break;
 553         }
 554         mutex_unlock(&uuari->lock);
 555
 556         return uuarn;
 557 }
 558
 559 static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 560 {
 561         clear_bit(uuarn, uuari->bitmap);
 562         --uuari->count[uuarn];
 563 }
 564
 565 static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 566 {
 567         clear_bit(uuarn, uuari->bitmap);
 568         --uuari->count[uuarn];
 569 }
 570
 571 static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 572 {
 573         int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
 574         int high_uuar = nuuars - uuari->num_low_latency_uuars;
 575
 576         mutex_lock(&uuari->lock);
 577         if (uuarn == 0) {
 578                 --uuari->count[uuarn];
 579                 goto out;
 580         }
 581
 582         if (uuarn < high_uuar) {
 583                 free_med_class_uuar(uuari, uuarn);
 584                 goto out;
 585         }
 586
 587         free_high_class_uuar(uuari, uuarn);
 588
 589 out:
 590         mutex_unlock(&uuari->lock);
 591 }
 592
 593 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
 594 {
 595         switch (state) {
 596         case IB_QPS_RESET:      return MLX5_QP_STATE_RST;
 597         case IB_QPS_INIT:       return MLX5_QP_STATE_INIT;
 598         case IB_QPS_RTR:        return MLX5_QP_STATE_RTR;
 599         case IB_QPS_RTS:        return MLX5_QP_STATE_RTS;
 600         case IB_QPS_SQD:        return MLX5_QP_STATE_SQD;
 601         case IB_QPS_SQE:        return MLX5_QP_STATE_SQER;
 602         case IB_QPS_ERR:        return MLX5_QP_STATE_ERR;
 603         default:                return -1;
 604         }
 605 }
 606
 607 static int to_mlx5_st(enum ib_qp_type type)
 608 {
 609         switch (type) {
 610         case IB_QPT_RC:                 return MLX5_QP_ST_RC;
 611         case IB_QPT_UC:                 return MLX5_QP_ST_UC;
 612         case IB_QPT_UD:                 return MLX5_QP_ST_UD;
 613         case MLX5_IB_QPT_REG_UMR:       return MLX5_QP_ST_REG_UMR;
 614         case IB_QPT_XRC_INI:
 615         case IB_QPT_XRC_TGT:            return MLX5_QP_ST_XRC;
 616         case IB_QPT_SMI:                return MLX5_QP_ST_QP0;
 617         case MLX5_IB_QPT_HW_GSI:        return MLX5_QP_ST_QP1;
 618         case IB_QPT_RAW_IPV6:           return MLX5_QP_ST_RAW_IPV6;
 619         case IB_QPT_RAW_PACKET:
 620         case IB_QPT_RAW_ETHERTYPE:      return MLX5_QP_ST_RAW_ETHERTYPE;
 621         case IB_QPT_MAX:
 622         default:                return -EINVAL;
 623         }
 624 }
 625
 626 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
 627                              struct mlx5_ib_cq *recv_cq);
 628 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
 629                                struct mlx5_ib_cq *recv_cq);
 630
 631 static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn)
 632 {
 633         return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index;
 634 }
 635
 636 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
 637                             struct ib_pd *pd,
 638                             unsigned long addr, size_t size,
 639                             struct ib_umem **umem,
 640                             int *npages, int *page_shift, int *ncont,
 641                             u32 *offset)
 642 {
 643         int err;
 644
 645         *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
 646         if (IS_ERR(*umem)) {
 647                 mlx5_ib_dbg(dev, "umem_get failed\n");
 648                 return PTR_ERR(*umem);
 649         }
 650
 651         mlx5_ib_cont_pages(*umem, addr, npages, page_shift, ncont, NULL);
 652
 653         err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
 654         if (err) {
 655                 mlx5_ib_warn(dev, "bad offset\n");
 656                 goto err_umem;
 657         }
 658
 659         mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
 660                     addr, size, *npages, *page_shift, *ncont, *offset);
 661
 662         return 0;
 663
 664 err_umem:
 665         ib_umem_release(*umem);
 666         *umem = NULL;
 667
 668         return err;
 669 }
 670
 671 static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq)
 672 {
 673         struct mlx5_ib_ucontext *context;
 674
 675         context = to_mucontext(pd->uobject->context);
 676         mlx5_ib_db_unmap_user(context, &rwq->db);
 677         if (rwq->umem)
 678                 ib_umem_release(rwq->umem);
 679 }
 680
 681 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 682                           struct mlx5_ib_rwq *rwq,
 683                           struct mlx5_ib_create_wq *ucmd)
 684 {
 685         struct mlx5_ib_ucontext *context;
 686         int page_shift = 0;
 687         int npages;
 688         u32 offset = 0;
 689         int ncont = 0;
 690         int err;
 691
 692         if (!ucmd->buf_addr)
 693                 return -EINVAL;
 694
 695         context = to_mucontext(pd->uobject->context);
 696         rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
 697                                rwq->buf_size, 0, 0);
 698         if (IS_ERR(rwq->umem)) {
 699                 mlx5_ib_dbg(dev, "umem_get failed\n");
 700                 err = PTR_ERR(rwq->umem);
 701                 return err;
 702         }
 703
 704         mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, &npages, &page_shift,
 705                            &ncont, NULL);
 706         err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
 707                                      &rwq->rq_page_offset);
 708         if (err) {
 709                 mlx5_ib_warn(dev, "bad offset\n");
 710                 goto err_umem;
 711         }
 712
 713         rwq->rq_num_pas = ncont;
 714         rwq->page_shift = page_shift;
 715         rwq->log_page_size =  page_shift - MLX5_ADAPTER_PAGE_SHIFT;
 716         rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
 717
 718         mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
 719                     (unsigned long long)ucmd->buf_addr, rwq->buf_size,
 720                     npages, page_shift, ncont, offset);
 721
 722         err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
 723         if (err) {
 724                 mlx5_ib_dbg(dev, "map failed\n");
 725                 goto err_umem;
 726         }
 727
 728         rwq->create_type = MLX5_WQ_USER;
 729         return 0;
 730
 731 err_umem:
 732         ib_umem_release(rwq->umem);
 733         return err;
 734 }
 735
 736 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 737                           struct mlx5_ib_qp *qp, struct ib_udata *udata,
 738                           struct ib_qp_init_attr *attr,
 739                           u32 **in,
 740                           struct mlx5_ib_create_qp_resp *resp, int *inlen,
 741                           struct mlx5_ib_qp_base *base)
 742 {
 743         struct mlx5_ib_ucontext *context;
 744         struct mlx5_ib_create_qp ucmd;
 745         struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
 746         int page_shift = 0;
 747         int uar_index;
 748         int npages;
 749         u32 offset = 0;
 750         int uuarn;
 751         int ncont = 0;
 752         __be64 *pas;
 753         void *qpc;
 754         int err;
 755
 756         err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
 757         if (err) {
 758                 mlx5_ib_dbg(dev, "copy failed\n");
 759                 return err;
 760         }
 761
 762         context = to_mucontext(pd->uobject->context);
 763         /*
 764          * TBD: should come from the verbs when we have the API
 765          */
 766         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
 767                 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
 768                 uuarn = MLX5_CROSS_CHANNEL_UUAR;
 769         else {
 770                 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH);
 771                 if (uuarn < 0) {
 772                         mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n");
 773                         mlx5_ib_dbg(dev, "reverting to medium latency\n");
 774                         uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM);
 775                         if (uuarn < 0) {
 776                                 mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n");
 777                                 mlx5_ib_dbg(dev, "reverting to high latency\n");
 778                                 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW);
 779                                 if (uuarn < 0) {
 780                                         mlx5_ib_warn(dev, "uuar allocation failed\n");
 781                                         return uuarn;
 782                                 }
 783                         }
 784                 }
 785         }
 786
 787         uar_index = uuarn_to_uar_index(&context->uuari, uuarn);
 788         mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index);
 789
 790         qp->rq.offset = 0;
 791         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 792         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 793
 794         err = set_user_buf_size(dev, qp, &ucmd, base, attr);
 795         if (err)
 796                 goto err_uuar;
 797
 798         if (ucmd.buf_addr && ubuffer->buf_size) {
 799                 ubuffer->buf_addr = ucmd.buf_addr;
 800                 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
 801                                        ubuffer->buf_size,
 802                                        &ubuffer->umem, &npages, &page_shift,
 803                                        &ncont, &offset);
 804                 if (err)
 805                         goto err_uuar;
 806         } else {
 807                 ubuffer->umem = NULL;
 808         }
 809
 810         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 811                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
 812         *in = mlx5_vzalloc(*inlen);
 813         if (!*in) {
 814                 err = -ENOMEM;
 815                 goto err_umem;
 816         }
 817
 818         pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
 819         if (ubuffer->umem)
 820                 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
 821
 822         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
 823
 824         MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 825         MLX5_SET(qpc, qpc, page_offset, offset);
 826
 827         MLX5_SET(qpc, qpc, uar_page, uar_index);
 828         resp->uuar_index = uuarn;
 829         qp->uuarn = uuarn;
 830
 831         err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
 832         if (err) {
 833                 mlx5_ib_dbg(dev, "map failed\n");
 834                 goto err_free;
 835         }
 836
 837         err = ib_copy_to_udata(udata, resp, sizeof(*resp));
 838         if (err) {
 839                 mlx5_ib_dbg(dev, "copy failed\n");
 840                 goto err_unmap;
 841         }
 842         qp->create_type = MLX5_QP_USER;
 843
 844         return 0;
 845
 846 err_unmap:
 847         mlx5_ib_db_unmap_user(context, &qp->db);
 848
 849 err_free:
 850         kvfree(*in);
 851
 852 err_umem:
 853         if (ubuffer->umem)
 854                 ib_umem_release(ubuffer->umem);
 855
 856 err_uuar:
 857         free_uuar(&context->uuari, uuarn);
 858         return err;
 859 }
 860
 861 static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp,
 862                             struct mlx5_ib_qp_base *base)
 863 {
 864         struct mlx5_ib_ucontext *context;
 865
 866         context = to_mucontext(pd->uobject->context);
 867         mlx5_ib_db_unmap_user(context, &qp->db);
 868         if (base->ubuffer.umem)
 869                 ib_umem_release(base->ubuffer.umem);
 870         free_uuar(&context->uuari, qp->uuarn);
 871 }
 872
 873 static int create_kernel_qp(struct mlx5_ib_dev *dev,
 874                             struct ib_qp_init_attr *init_attr,
 875                             struct mlx5_ib_qp *qp,
 876                             u32 **in, int *inlen,
 877                             struct mlx5_ib_qp_base *base)
 878 {
 879         enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW;
 880         struct mlx5_uuar_info *uuari;
 881         int uar_index;
 882         void *qpc;
 883         int uuarn;
 884         int err;
 885
 886         uuari = &dev->mdev->priv.uuari;
 887         if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
 888                                         IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
 889                                         IB_QP_CREATE_IPOIB_UD_LSO |
 890                                         mlx5_ib_create_qp_sqpn_qp1()))
 891                 return -EINVAL;
 892
 893         if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
 894                 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH;
 895
 896         uuarn = alloc_uuar(uuari, lc);
 897         if (uuarn < 0) {
 898                 mlx5_ib_dbg(dev, "\n");
 899                 return -ENOMEM;
 900         }
 901
 902         qp->bf = &uuari->bfs[uuarn];
 903         uar_index = qp->bf->uar->index;
 904
 905         err = calc_sq_size(dev, init_attr, qp);
 906         if (err < 0) {
 907                 mlx5_ib_dbg(dev, "err %d\n", err);
 908                 goto err_uuar;
 909         }
 910
 911         qp->rq.offset = 0;
 912         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 913         base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
 914
 915         err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
 916         if (err) {
 917                 mlx5_ib_dbg(dev, "err %d\n", err);
 918                 goto err_uuar;
 919         }
 920
 921         qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
 922         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 923                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
 924         *in = mlx5_vzalloc(*inlen);
 925         if (!*in) {
 926                 err = -ENOMEM;
 927                 goto err_buf;
 928         }
 929
 930         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
 931         MLX5_SET(qpc, qpc, uar_page, uar_index);
 932         MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 933
 934         /* Set "fast registration enabled" for all kernel QPs */
 935         MLX5_SET(qpc, qpc, fre, 1);
 936         MLX5_SET(qpc, qpc, rlky, 1);
 937
 938         if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
 939                 MLX5_SET(qpc, qpc, deth_sqpn, 1);
 940                 qp->flags |= MLX5_IB_QP_SQPN_QP1;
 941         }
 942
 943         mlx5_fill_page_array(&qp->buf,
 944                              (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
 945
 946         err = mlx5_db_alloc(dev->mdev, &qp->db);
 947         if (err) {
 948                 mlx5_ib_dbg(dev, "err %d\n", err);
 949                 goto err_free;
 950         }
 951
 952         qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
 953         qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
 954         qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
 955         qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
 956         qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
 957
 958         if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
 959             !qp->sq.w_list || !qp->sq.wqe_head) {
 960                 err = -ENOMEM;
 961                 goto err_wrid;
 962         }
 963         qp->create_type = MLX5_QP_KERNEL;
 964
 965         return 0;
 966
 967 err_wrid:
 968         mlx5_db_free(dev->mdev, &qp->db);
 969         kfree(qp->sq.wqe_head);
 970         kfree(qp->sq.w_list);
 971         kfree(qp->sq.wrid);
 972         kfree(qp->sq.wr_data);
 973         kfree(qp->rq.wrid);
 974
 975 err_free:
 976         kvfree(*in);
 977
 978 err_buf:
 979         mlx5_buf_free(dev->mdev, &qp->buf);
 980
 981 err_uuar:
 982         free_uuar(&dev->mdev->priv.uuari, uuarn);
 983         return err;
 984 }
 985
 986 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
 987 {
 988         mlx5_db_free(dev->mdev, &qp->db);
 989         kfree(qp->sq.wqe_head);
 990         kfree(qp->sq.w_list);
 991         kfree(qp->sq.wrid);
 992         kfree(qp->sq.wr_data);
 993         kfree(qp->rq.wrid);
 994         mlx5_buf_free(dev->mdev, &qp->buf);
 995         free_uuar(&dev->mdev->priv.uuari, qp->bf->uuarn);
 996 }
 997
 998 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
 999 {
1000         if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1001             (attr->qp_type == IB_QPT_XRC_INI))
1002                 return MLX5_SRQ_RQ;
1003         else if (!qp->has_rq)
1004                 return MLX5_ZERO_LEN_RQ;
1005         else
1006                 return MLX5_NON_ZERO_RQ;
1007 }
1008
1009 static int is_connected(enum ib_qp_type qp_type)
1010 {
1011         if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1012                 return 1;
1013
1014         return 0;
1015 }
1016
1017 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1018                                     struct mlx5_ib_sq *sq, u32 tdn)
1019 {
1020         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1021         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1022
1023         MLX5_SET(tisc, tisc, transport_domain, tdn);
1024         return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1025 }
1026
1027 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1028                                       struct mlx5_ib_sq *sq)
1029 {
1030         mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1031 }
1032
1033 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1034                                    struct mlx5_ib_sq *sq, void *qpin,
1035                                    struct ib_pd *pd)
1036 {
1037         struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1038         __be64 *pas;
1039         void *in;
1040         void *sqc;
1041         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1042         void *wq;
1043         int inlen;
1044         int err;
1045         int page_shift = 0;
1046         int npages;
1047         int ncont = 0;
1048         u32 offset = 0;
1049
1050         err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1051                                &sq->ubuffer.umem, &npages, &page_shift,
1052                                &ncont, &offset);
1053         if (err)
1054                 return err;
1055
1056         inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1057         in = mlx5_vzalloc(inlen);
1058         if (!in) {
1059                 err = -ENOMEM;
1060                 goto err_umem;
1061         }
1062
1063         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1064         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1065         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1066         MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1067         MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1068         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1069         MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1070
1071         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1072         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1073         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1074         MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1075         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1076         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1077         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1078         MLX5_SET(wq, wq, log_wq_pg_sz,  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1079         MLX5_SET(wq, wq, page_offset, offset);
1080
1081         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1082         mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1083
1084         err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1085
1086         kvfree(in);
1087
1088         if (err)
1089                 goto err_umem;
1090
1091         return 0;
1092
1093 err_umem:
1094         ib_umem_release(sq->ubuffer.umem);
1095         sq->ubuffer.umem = NULL;
1096
1097         return err;
1098 }
1099
1100 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1101                                      struct mlx5_ib_sq *sq)
1102 {
1103         mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1104         ib_umem_release(sq->ubuffer.umem);
1105 }
1106
1107 static int get_rq_pas_size(void *qpc)
1108 {
1109         u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1110         u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1111         u32 log_rq_size   = MLX5_GET(qpc, qpc, log_rq_size);
1112         u32 page_offset   = MLX5_GET(qpc, qpc, page_offset);
1113         u32 po_quanta     = 1 << (log_page_size - 6);
1114         u32 rq_sz         = 1 << (log_rq_size + 4 + log_rq_stride);
1115         u32 page_size     = 1 << log_page_size;
1116         u32 rq_sz_po      = rq_sz + (page_offset * po_quanta);
1117         u32 rq_num_pas    = (rq_sz_po + page_size - 1) / page_size;
1118
1119         return rq_num_pas * sizeof(u64);
1120 }
1121
1122 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1123                                    struct mlx5_ib_rq *rq, void *qpin)
1124 {
1125         struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1126         __be64 *pas;
1127         __be64 *qp_pas;
1128         void *in;
1129         void *rqc;
1130         void *wq;
1131         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1132         int inlen;
1133         int err;
1134         u32 rq_pas_size = get_rq_pas_size(qpc);
1135
1136         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1137         in = mlx5_vzalloc(inlen);
1138         if (!in)
1139                 return -ENOMEM;
1140
1141         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1142         MLX5_SET(rqc, rqc, vsd, 1);
1143         MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1144         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1145         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1146         MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1147         MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1148
1149         if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1150                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1151
1152         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1153         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1154         MLX5_SET(wq, wq, end_padding_mode,
1155                  MLX5_GET(qpc, qpc, end_padding_mode));
1156         MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1157         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1158         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1159         MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1160         MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1161         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1162
1163         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1164         qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1165         memcpy(pas, qp_pas, rq_pas_size);
1166
1167         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1168
1169         kvfree(in);
1170
1171         return err;
1172 }
1173
1174 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1175                                      struct mlx5_ib_rq *rq)
1176 {
1177         mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1178 }
1179
1180 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1181                                     struct mlx5_ib_rq *rq, u32 tdn)
1182 {
1183         u32 *in;
1184         void *tirc;
1185         int inlen;
1186         int err;
1187
1188         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1189         in = mlx5_vzalloc(inlen);
1190         if (!in)
1191                 return -ENOMEM;
1192
1193         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1194         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1195         MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1196         MLX5_SET(tirc, tirc, transport_domain, tdn);
1197
1198         err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1199
1200         kvfree(in);
1201
1202         return err;
1203 }
1204
1205 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1206                                       struct mlx5_ib_rq *rq)
1207 {
1208         mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1209 }
1210
1211 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1212                                 u32 *in,
1213                                 struct ib_pd *pd)
1214 {
1215         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1216         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1217         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1218         struct ib_uobject *uobj = pd->uobject;
1219         struct ib_ucontext *ucontext = uobj->context;
1220         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1221         int err;
1222         u32 tdn = mucontext->tdn;
1223
1224         if (qp->sq.wqe_cnt) {
1225                 err = create_raw_packet_qp_tis(dev, sq, tdn);
1226                 if (err)
1227                         return err;
1228
1229                 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1230                 if (err)
1231                         goto err_destroy_tis;
1232
1233                 sq->base.container_mibqp = qp;
1234         }
1235
1236         if (qp->rq.wqe_cnt) {
1237                 rq->base.container_mibqp = qp;
1238
1239                 err = create_raw_packet_qp_rq(dev, rq, in);
1240                 if (err)
1241                         goto err_destroy_sq;
1242
1243
1244                 err = create_raw_packet_qp_tir(dev, rq, tdn);
1245                 if (err)
1246                         goto err_destroy_rq;
1247         }
1248
1249         qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1250                                                      rq->base.mqp.qpn;
1251
1252         return 0;
1253
1254 err_destroy_rq:
1255         destroy_raw_packet_qp_rq(dev, rq);
1256 err_destroy_sq:
1257         if (!qp->sq.wqe_cnt)
1258                 return err;
1259         destroy_raw_packet_qp_sq(dev, sq);
1260 err_destroy_tis:
1261         destroy_raw_packet_qp_tis(dev, sq);
1262
1263         return err;
1264 }
1265
1266 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1267                                   struct mlx5_ib_qp *qp)
1268 {
1269         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1270         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1271         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1272
1273         if (qp->rq.wqe_cnt) {
1274                 destroy_raw_packet_qp_tir(dev, rq);
1275                 destroy_raw_packet_qp_rq(dev, rq);
1276         }
1277
1278         if (qp->sq.wqe_cnt) {
1279                 destroy_raw_packet_qp_sq(dev, sq);
1280                 destroy_raw_packet_qp_tis(dev, sq);
1281         }
1282 }
1283
1284 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1285                                     struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1286 {
1287         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1288         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1289
1290         sq->sq = &qp->sq;
1291         rq->rq = &qp->rq;
1292         sq->doorbell = &qp->db;
1293         rq->doorbell = &qp->db;
1294 }
1295
1296 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1297 {
1298         mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1299 }
1300
1301 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1302                                  struct ib_pd *pd,
1303                                  struct ib_qp_init_attr *init_attr,
1304                                  struct ib_udata *udata)
1305 {
1306         struct ib_uobject *uobj = pd->uobject;
1307         struct ib_ucontext *ucontext = uobj->context;
1308         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1309         struct mlx5_ib_create_qp_resp resp = {};
1310         int inlen;
1311         int err;
1312         u32 *in;
1313         void *tirc;
1314         void *hfso;
1315         u32 selected_fields = 0;
1316         size_t min_resp_len;
1317         u32 tdn = mucontext->tdn;
1318         struct mlx5_ib_create_qp_rss ucmd = {};
1319         size_t required_cmd_sz;
1320
1321         if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1322                 return -EOPNOTSUPP;
1323
1324         if (init_attr->create_flags || init_attr->send_cq)
1325                 return -EINVAL;
1326
1327         min_resp_len = offsetof(typeof(resp), uuar_index) + sizeof(resp.uuar_index);
1328         if (udata->outlen < min_resp_len)
1329                 return -EINVAL;
1330
1331         required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1);
1332         if (udata->inlen < required_cmd_sz) {
1333                 mlx5_ib_dbg(dev, "invalid inlen\n");
1334                 return -EINVAL;
1335         }
1336
1337         if (udata->inlen > sizeof(ucmd) &&
1338             !ib_is_udata_cleared(udata, sizeof(ucmd),
1339                                  udata->inlen - sizeof(ucmd))) {
1340                 mlx5_ib_dbg(dev, "inlen is not supported\n");
1341                 return -EOPNOTSUPP;
1342         }
1343
1344         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1345                 mlx5_ib_dbg(dev, "copy failed\n");
1346                 return -EFAULT;
1347         }
1348
1349         if (ucmd.comp_mask) {
1350                 mlx5_ib_dbg(dev, "invalid comp mask\n");
1351                 return -EOPNOTSUPP;
1352         }
1353
1354         if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) {
1355                 mlx5_ib_dbg(dev, "invalid reserved\n");
1356                 return -EOPNOTSUPP;
1357         }
1358
1359         err = ib_copy_to_udata(udata, &resp, min_resp_len);
1360         if (err) {
1361                 mlx5_ib_dbg(dev, "copy failed\n");
1362                 return -EINVAL;
1363         }
1364
1365         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1366         in = mlx5_vzalloc(inlen);
1367         if (!in)
1368                 return -ENOMEM;
1369
1370         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1371         MLX5_SET(tirc, tirc, disp_type,
1372                  MLX5_TIRC_DISP_TYPE_INDIRECT);
1373         MLX5_SET(tirc, tirc, indirect_table,
1374                  init_attr->rwq_ind_tbl->ind_tbl_num);
1375         MLX5_SET(tirc, tirc, transport_domain, tdn);
1376
1377         hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1378         switch (ucmd.rx_hash_function) {
1379         case MLX5_RX_HASH_FUNC_TOEPLITZ:
1380         {
1381                 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1382                 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1383
1384                 if (len != ucmd.rx_key_len) {
1385                         err = -EINVAL;
1386                         goto err;
1387                 }
1388
1389                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1390                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1391                 memcpy(rss_key, ucmd.rx_hash_key, len);
1392                 break;
1393         }
1394         default:
1395                 err = -EOPNOTSUPP;
1396                 goto err;
1397         }
1398
1399         if (!ucmd.rx_hash_fields_mask) {
1400                 /* special case when this TIR serves as steering entry without hashing */
1401                 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1402                         goto create_tir;
1403                 err = -EINVAL;
1404                 goto err;
1405         }
1406
1407         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1408              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1409              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1410              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1411                 err = -EINVAL;
1412                 goto err;
1413         }
1414
1415         /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1416         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1417             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1418                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1419                          MLX5_L3_PROT_TYPE_IPV4);
1420         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1421                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1422                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1423                          MLX5_L3_PROT_TYPE_IPV6);
1424
1425         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1426              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1427              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1428              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1429                 err = -EINVAL;
1430                 goto err;
1431         }
1432
1433         /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1434         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1435             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1436                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1437                          MLX5_L4_PROT_TYPE_TCP);
1438         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1439                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1440                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1441                          MLX5_L4_PROT_TYPE_UDP);
1442
1443         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1444             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1445                 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1446
1447         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1448             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1449                 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1450
1451         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1452             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1453                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1454
1455         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1456             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1457                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1458
1459         MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1460
1461 create_tir:
1462         err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1463
1464         if (err)
1465                 goto err;
1466
1467         kvfree(in);
1468         /* qpn is reserved for that QP */
1469         qp->trans_qp.base.mqp.qpn = 0;
1470         return 0;
1471
1472 err:
1473         kvfree(in);
1474         return err;
1475 }
1476
1477 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1478                             struct ib_qp_init_attr *init_attr,
1479                             struct ib_udata *udata, struct mlx5_ib_qp *qp)
1480 {
1481         struct mlx5_ib_resources *devr = &dev->devr;
1482         int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1483         struct mlx5_core_dev *mdev = dev->mdev;
1484         struct mlx5_ib_create_qp_resp resp;
1485         struct mlx5_ib_cq *send_cq;
1486         struct mlx5_ib_cq *recv_cq;
1487         unsigned long flags;
1488         u32 uidx = MLX5_IB_DEFAULT_UIDX;
1489         struct mlx5_ib_create_qp ucmd;
1490         struct mlx5_ib_qp_base *base;
1491         void *qpc;
1492         u32 *in;
1493         int err;
1494
1495         base = init_attr->qp_type == IB_QPT_RAW_PACKET ?
1496                &qp->raw_packet_qp.rq.base :
1497                &qp->trans_qp.base;
1498
1499         if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1500                 mlx5_ib_odp_create_qp(qp);
1501
1502         mutex_init(&qp->mutex);
1503         spin_lock_init(&qp->sq.lock);
1504         spin_lock_init(&qp->rq.lock);
1505
1506         if (init_attr->rwq_ind_tbl) {
1507                 if (!udata)
1508                         return -ENOSYS;
1509
1510                 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1511                 return err;
1512         }
1513
1514         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1515                 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1516                         mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1517                         return -EINVAL;
1518                 } else {
1519                         qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1520                 }
1521         }
1522
1523         if (init_attr->create_flags &
1524                         (IB_QP_CREATE_CROSS_CHANNEL |
1525                          IB_QP_CREATE_MANAGED_SEND |
1526                          IB_QP_CREATE_MANAGED_RECV)) {
1527                 if (!MLX5_CAP_GEN(mdev, cd)) {
1528                         mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1529                         return -EINVAL;
1530                 }
1531                 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1532                         qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1533                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1534                         qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1535                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1536                         qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1537         }
1538
1539         if (init_attr->qp_type == IB_QPT_UD &&
1540             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1541                 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1542                         mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1543                         return -EOPNOTSUPP;
1544                 }
1545
1546         if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1547                 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1548                         mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1549                         return -EOPNOTSUPP;
1550                 }
1551                 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1552                     !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1553                         mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1554                         return -EOPNOTSUPP;
1555                 }
1556                 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1557         }
1558
1559         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1560                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1561
1562         if (pd && pd->uobject) {
1563                 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1564                         mlx5_ib_dbg(dev, "copy failed\n");
1565                         return -EFAULT;
1566                 }
1567
1568                 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1569                                         &ucmd, udata->inlen, &uidx);
1570                 if (err)
1571                         return err;
1572
1573                 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1574                 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1575         } else {
1576                 qp->wq_sig = !!wq_signature;
1577         }
1578
1579         qp->has_rq = qp_has_rq(init_attr);
1580         err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1581                           qp, (pd && pd->uobject) ? &ucmd : NULL);
1582         if (err) {
1583                 mlx5_ib_dbg(dev, "err %d\n", err);
1584                 return err;
1585         }
1586
1587         if (pd) {
1588                 if (pd->uobject) {
1589                         __u32 max_wqes =
1590                                 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1591                         mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1592                         if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1593                             ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1594                                 mlx5_ib_dbg(dev, "invalid rq params\n");
1595                                 return -EINVAL;
1596                         }
1597                         if (ucmd.sq_wqe_count > max_wqes) {
1598                                 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1599                                             ucmd.sq_wqe_count, max_wqes);
1600                                 return -EINVAL;
1601                         }
1602                         if (init_attr->create_flags &
1603                             mlx5_ib_create_qp_sqpn_qp1()) {
1604                                 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1605                                 return -EINVAL;
1606                         }
1607                         err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1608                                              &resp, &inlen, base);
1609                         if (err)
1610                                 mlx5_ib_dbg(dev, "err %d\n", err);
1611                 } else {
1612                         err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1613                                                base);
1614                         if (err)
1615                                 mlx5_ib_dbg(dev, "err %d\n", err);
1616                 }
1617
1618                 if (err)
1619                         return err;
1620         } else {
1621                 in = mlx5_vzalloc(inlen);
1622                 if (!in)
1623                         return -ENOMEM;
1624
1625                 qp->create_type = MLX5_QP_EMPTY;
1626         }
1627
1628         if (is_sqp(init_attr->qp_type))
1629                 qp->port = init_attr->port_num;
1630
1631         qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1632
1633         MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type));
1634         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1635
1636         if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1637                 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
1638         else
1639                 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1640
1641
1642         if (qp->wq_sig)
1643                 MLX5_SET(qpc, qpc, wq_signature, 1);
1644
1645         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1646                 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1647
1648         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1649                 MLX5_SET(qpc, qpc, cd_master, 1);
1650         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1651                 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1652         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1653                 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1654
1655         if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1656                 int rcqe_sz;
1657                 int scqe_sz;
1658
1659                 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1660                 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1661
1662                 if (rcqe_sz == 128)
1663                         MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1664                 else
1665                         MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1666
1667                 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1668                         if (scqe_sz == 128)
1669                                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1670                         else
1671                                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1672                 }
1673         }
1674
1675         if (qp->rq.wqe_cnt) {
1676                 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1677                 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
1678         }
1679
1680         MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
1681
1682         if (qp->sq.wqe_cnt)
1683                 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
1684         else
1685                 MLX5_SET(qpc, qpc, no_sq, 1);
1686
1687         /* Set default resources */
1688         switch (init_attr->qp_type) {
1689         case IB_QPT_XRC_TGT:
1690                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1691                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1692                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1693                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
1694                 break;
1695         case IB_QPT_XRC_INI:
1696                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1697                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1698                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1699                 break;
1700         default:
1701                 if (init_attr->srq) {
1702                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1703                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
1704                 } else {
1705                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1706                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
1707                 }
1708         }
1709
1710         if (init_attr->send_cq)
1711                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
1712
1713         if (init_attr->recv_cq)
1714                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
1715
1716         MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1717
1718         /* 0xffffff means we ask to work with cqe version 0 */
1719         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1720                 MLX5_SET(qpc, qpc, user_index, uidx);
1721
1722         /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1723         if (init_attr->qp_type == IB_QPT_UD &&
1724             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1725                 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1726                 qp->flags |= MLX5_IB_QP_LSO;
1727         }
1728
1729         if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1730                 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1731                 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1732                 err = create_raw_packet_qp(dev, qp, in, pd);
1733         } else {
1734                 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1735         }
1736
1737         if (err) {
1738                 mlx5_ib_dbg(dev, "create qp failed\n");
1739                 goto err_create;
1740         }
1741
1742         kvfree(in);
1743
1744         base->container_mibqp = qp;
1745         base->mqp.event = mlx5_ib_qp_event;
1746
1747         get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1748                 &send_cq, &recv_cq);
1749         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1750         mlx5_ib_lock_cqs(send_cq, recv_cq);
1751         /* Maintain device to QPs access, needed for further handling via reset
1752          * flow
1753          */
1754         list_add_tail(&qp->qps_list, &dev->qp_list);
1755         /* Maintain CQ to QPs access, needed for further handling via reset flow
1756          */
1757         if (send_cq)
1758                 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1759         if (recv_cq)
1760                 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1761         mlx5_ib_unlock_cqs(send_cq, recv_cq);
1762         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1763
1764         return 0;
1765
1766 err_create:
1767         if (qp->create_type == MLX5_QP_USER)
1768                 destroy_qp_user(pd, qp, base);
1769         else if (qp->create_type == MLX5_QP_KERNEL)
1770                 destroy_qp_kernel(dev, qp);
1771
1772         kvfree(in);
1773         return err;
1774 }
1775
1776 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1777         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1778 {
1779         if (send_cq) {
1780                 if (recv_cq) {
1781                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1782                                 spin_lock(&send_cq->lock);
1783                                 spin_lock_nested(&recv_cq->lock,
1784                                                  SINGLE_DEPTH_NESTING);
1785                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1786                                 spin_lock(&send_cq->lock);
1787                                 __acquire(&recv_cq->lock);
1788                         } else {
1789                                 spin_lock(&recv_cq->lock);
1790                                 spin_lock_nested(&send_cq->lock,
1791                                                  SINGLE_DEPTH_NESTING);
1792                         }
1793                 } else {
1794                         spin_lock(&send_cq->lock);
1795                         __acquire(&recv_cq->lock);
1796                 }
1797         } else if (recv_cq) {
1798                 spin_lock(&recv_cq->lock);
1799                 __acquire(&send_cq->lock);
1800         } else {
1801                 __acquire(&send_cq->lock);
1802                 __acquire(&recv_cq->lock);
1803         }
1804 }
1805
1806 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1807         __releases(&send_cq->lock) __releases(&recv_cq->lock)
1808 {
1809         if (send_cq) {
1810                 if (recv_cq) {
1811                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1812                                 spin_unlock(&recv_cq->lock);
1813                                 spin_unlock(&send_cq->lock);
1814                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1815                                 __release(&recv_cq->lock);
1816                                 spin_unlock(&send_cq->lock);
1817                         } else {
1818                                 spin_unlock(&send_cq->lock);
1819                                 spin_unlock(&recv_cq->lock);
1820                         }
1821                 } else {
1822                         __release(&recv_cq->lock);
1823                         spin_unlock(&send_cq->lock);
1824                 }
1825         } else if (recv_cq) {
1826                 __release(&send_cq->lock);
1827                 spin_unlock(&recv_cq->lock);
1828         } else {
1829                 __release(&recv_cq->lock);
1830                 __release(&send_cq->lock);
1831         }
1832 }
1833
1834 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1835 {
1836         return to_mpd(qp->ibqp.pd);
1837 }
1838
1839 static void get_cqs(enum ib_qp_type qp_type,
1840                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
1841                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1842 {
1843         switch (qp_type) {
1844         case IB_QPT_XRC_TGT:
1845                 *send_cq = NULL;
1846                 *recv_cq = NULL;
1847                 break;
1848         case MLX5_IB_QPT_REG_UMR:
1849         case IB_QPT_XRC_INI:
1850                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1851                 *recv_cq = NULL;
1852                 break;
1853
1854         case IB_QPT_SMI:
1855         case MLX5_IB_QPT_HW_GSI:
1856         case IB_QPT_RC:
1857         case IB_QPT_UC:
1858         case IB_QPT_UD:
1859         case IB_QPT_RAW_IPV6:
1860         case IB_QPT_RAW_ETHERTYPE:
1861         case IB_QPT_RAW_PACKET:
1862                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1863                 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
1864                 break;
1865
1866         case IB_QPT_MAX:
1867         default:
1868                 *send_cq = NULL;
1869                 *recv_cq = NULL;
1870                 break;
1871         }
1872 }
1873
1874 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1875                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
1876                                 u8 lag_tx_affinity);
1877
1878 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1879 {
1880         struct mlx5_ib_cq *send_cq, *recv_cq;
1881         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
1882         unsigned long flags;
1883         int err;
1884
1885         if (qp->ibqp.rwq_ind_tbl) {
1886                 destroy_rss_raw_qp_tir(dev, qp);
1887                 return;
1888         }
1889
1890         base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ?
1891                &qp->raw_packet_qp.rq.base :
1892                &qp->trans_qp.base;
1893
1894         if (qp->state != IB_QPS_RESET) {
1895                 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) {
1896                         mlx5_ib_qp_disable_pagefaults(qp);
1897                         err = mlx5_core_qp_modify(dev->mdev,
1898                                                   MLX5_CMD_OP_2RST_QP, 0,
1899                                                   NULL, &base->mqp);
1900                 } else {
1901                         struct mlx5_modify_raw_qp_param raw_qp_param = {
1902                                 .operation = MLX5_CMD_OP_2RST_QP
1903                         };
1904
1905                         err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
1906                 }
1907                 if (err)
1908                         mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
1909                                      base->mqp.qpn);
1910         }
1911
1912         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
1913                 &send_cq, &recv_cq);
1914
1915         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1916         mlx5_ib_lock_cqs(send_cq, recv_cq);
1917         /* del from lists under both locks above to protect reset flow paths */
1918         list_del(&qp->qps_list);
1919         if (send_cq)
1920                 list_del(&qp->cq_send_list);
1921
1922         if (recv_cq)
1923                 list_del(&qp->cq_recv_list);
1924
1925         if (qp->create_type == MLX5_QP_KERNEL) {
1926                 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
1927                                    qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1928                 if (send_cq != recv_cq)
1929                         __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
1930                                            NULL);
1931         }
1932         mlx5_ib_unlock_cqs(send_cq, recv_cq);
1933         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1934
1935         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1936                 destroy_raw_packet_qp(dev, qp);
1937         } else {
1938                 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
1939                 if (err)
1940                         mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
1941                                      base->mqp.qpn);
1942         }
1943
1944         if (qp->create_type == MLX5_QP_KERNEL)
1945                 destroy_qp_kernel(dev, qp);
1946         else if (qp->create_type == MLX5_QP_USER)
1947                 destroy_qp_user(&get_pd(qp)->ibpd, qp, base);
1948 }
1949
1950 static const char *ib_qp_type_str(enum ib_qp_type type)
1951 {
1952         switch (type) {
1953         case IB_QPT_SMI:
1954                 return "IB_QPT_SMI";
1955         case IB_QPT_GSI:
1956                 return "IB_QPT_GSI";
1957         case IB_QPT_RC:
1958                 return "IB_QPT_RC";
1959         case IB_QPT_UC:
1960                 return "IB_QPT_UC";
1961         case IB_QPT_UD:
1962                 return "IB_QPT_UD";
1963         case IB_QPT_RAW_IPV6:
1964                 return "IB_QPT_RAW_IPV6";
1965         case IB_QPT_RAW_ETHERTYPE:
1966                 return "IB_QPT_RAW_ETHERTYPE";
1967         case IB_QPT_XRC_INI:
1968                 return "IB_QPT_XRC_INI";
1969         case IB_QPT_XRC_TGT:
1970                 return "IB_QPT_XRC_TGT";
1971         case IB_QPT_RAW_PACKET:
1972                 return "IB_QPT_RAW_PACKET";
1973         case MLX5_IB_QPT_REG_UMR:
1974                 return "MLX5_IB_QPT_REG_UMR";
1975         case IB_QPT_MAX:
1976         default:
1977                 return "Invalid QP type";
1978         }
1979 }
1980
1981 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1982                                 struct ib_qp_init_attr *init_attr,
1983                                 struct ib_udata *udata)
1984 {
1985         struct mlx5_ib_dev *dev;
1986         struct mlx5_ib_qp *qp;
1987         u16 xrcdn = 0;
1988         int err;
1989
1990         if (pd) {
1991                 dev = to_mdev(pd->device);
1992
1993                 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1994                         if (!pd->uobject) {
1995                                 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
1996                                 return ERR_PTR(-EINVAL);
1997                         } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
1998                                 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
1999                                 return ERR_PTR(-EINVAL);
2000                         }
2001                 }
2002         } else {
2003                 /* being cautious here */
2004                 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2005                     init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2006                         pr_warn("%s: no PD for transport %s\n", __func__,
2007                                 ib_qp_type_str(init_attr->qp_type));
2008                         return ERR_PTR(-EINVAL);
2009                 }
2010                 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2011         }
2012
2013         switch (init_attr->qp_type) {
2014         case IB_QPT_XRC_TGT:
2015         case IB_QPT_XRC_INI:
2016                 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2017                         mlx5_ib_dbg(dev, "XRC not supported\n");
2018                         return ERR_PTR(-ENOSYS);
2019                 }
2020                 init_attr->recv_cq = NULL;
2021                 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2022                         xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2023                         init_attr->send_cq = NULL;
2024                 }
2025
2026                 /* fall through */
2027         case IB_QPT_RAW_PACKET:
2028         case IB_QPT_RC:
2029         case IB_QPT_UC:
2030         case IB_QPT_UD:
2031         case IB_QPT_SMI:
2032         case MLX5_IB_QPT_HW_GSI:
2033         case MLX5_IB_QPT_REG_UMR:
2034                 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2035                 if (!qp)
2036                         return ERR_PTR(-ENOMEM);
2037
2038                 err = create_qp_common(dev, pd, init_attr, udata, qp);
2039                 if (err) {
2040                         mlx5_ib_dbg(dev, "create_qp_common failed\n");
2041                         kfree(qp);
2042                         return ERR_PTR(err);
2043                 }
2044
2045                 if (is_qp0(init_attr->qp_type))
2046                         qp->ibqp.qp_num = 0;
2047                 else if (is_qp1(init_attr->qp_type))
2048                         qp->ibqp.qp_num = 1;
2049                 else
2050                         qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2051
2052                 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2053                             qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2054                             to_mcq(init_attr->recv_cq)->mcq.cqn,
2055                             to_mcq(init_attr->send_cq)->mcq.cqn);
2056
2057                 qp->trans_qp.xrcdn = xrcdn;
2058
2059                 break;
2060
2061         case IB_QPT_GSI:
2062                 return mlx5_ib_gsi_create_qp(pd, init_attr);
2063
2064         case IB_QPT_RAW_IPV6:
2065         case IB_QPT_RAW_ETHERTYPE:
2066         case IB_QPT_MAX:
2067         default:
2068                 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2069                             init_attr->qp_type);
2070                 /* Don't support raw QPs */
2071                 return ERR_PTR(-EINVAL);
2072         }
2073
2074         return &qp->ibqp;
2075 }
2076
2077 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2078 {
2079         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2080         struct mlx5_ib_qp *mqp = to_mqp(qp);
2081
2082         if (unlikely(qp->qp_type == IB_QPT_GSI))
2083                 return mlx5_ib_gsi_destroy_qp(qp);
2084
2085         destroy_qp_common(dev, mqp);
2086
2087         kfree(mqp);
2088
2089         return 0;
2090 }
2091
2092 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2093                                    int attr_mask)
2094 {
2095         u32 hw_access_flags = 0;
2096         u8 dest_rd_atomic;
2097         u32 access_flags;
2098
2099         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2100                 dest_rd_atomic = attr->max_dest_rd_atomic;
2101         else
2102                 dest_rd_atomic = qp->trans_qp.resp_depth;
2103
2104         if (attr_mask & IB_QP_ACCESS_FLAGS)
2105                 access_flags = attr->qp_access_flags;
2106         else
2107                 access_flags = qp->trans_qp.atomic_rd_en;
2108
2109         if (!dest_rd_atomic)
2110                 access_flags &= IB_ACCESS_REMOTE_WRITE;
2111
2112         if (access_flags & IB_ACCESS_REMOTE_READ)
2113                 hw_access_flags |= MLX5_QP_BIT_RRE;
2114         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2115                 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2116         if (access_flags & IB_ACCESS_REMOTE_WRITE)
2117                 hw_access_flags |= MLX5_QP_BIT_RWE;
2118
2119         return cpu_to_be32(hw_access_flags);
2120 }
2121
2122 enum {
2123         MLX5_PATH_FLAG_FL       = 1 << 0,
2124         MLX5_PATH_FLAG_FREE_AR  = 1 << 1,
2125         MLX5_PATH_FLAG_COUNTER  = 1 << 2,
2126 };
2127
2128 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2129 {
2130         if (rate == IB_RATE_PORT_CURRENT) {
2131                 return 0;
2132         } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
2133                 return -EINVAL;
2134         } else {
2135                 while (rate != IB_RATE_2_5_GBPS &&
2136                        !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2137                          MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2138                         --rate;
2139         }
2140
2141         return rate + MLX5_STAT_RATE_OFFSET;
2142 }
2143
2144 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2145                                       struct mlx5_ib_sq *sq, u8 sl)
2146 {
2147         void *in;
2148         void *tisc;
2149         int inlen;
2150         int err;
2151
2152         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2153         in = mlx5_vzalloc(inlen);
2154         if (!in)
2155                 return -ENOMEM;
2156
2157         MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2158
2159         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2160         MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2161
2162         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2163
2164         kvfree(in);
2165
2166         return err;
2167 }
2168
2169 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2170                                          struct mlx5_ib_sq *sq, u8 tx_affinity)
2171 {
2172         void *in;
2173         void *tisc;
2174         int inlen;
2175         int err;
2176
2177         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2178         in = mlx5_vzalloc(inlen);
2179         if (!in)
2180                 return -ENOMEM;
2181
2182         MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2183
2184         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2185         MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2186
2187         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2188
2189         kvfree(in);
2190
2191         return err;
2192 }
2193
2194 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2195                          const struct ib_ah_attr *ah,
2196                          struct mlx5_qp_path *path, u8 port, int attr_mask,
2197                          u32 path_flags, const struct ib_qp_attr *attr,
2198                          bool alt)
2199 {
2200         enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2201         int err;
2202
2203         if (attr_mask & IB_QP_PKEY_INDEX)
2204                 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2205                                                      attr->pkey_index);
2206
2207         if (ah->ah_flags & IB_AH_GRH) {
2208                 if (ah->grh.sgid_index >=
2209                     dev->mdev->port_caps[port - 1].gid_table_len) {
2210                         pr_err("sgid_index (%u) too large. max is %d\n",
2211                                ah->grh.sgid_index,
2212                                dev->mdev->port_caps[port - 1].gid_table_len);
2213                         return -EINVAL;
2214                 }
2215         }
2216
2217         if (ll == IB_LINK_LAYER_ETHERNET) {
2218                 if (!(ah->ah_flags & IB_AH_GRH))
2219                         return -EINVAL;
2220                 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac));
2221                 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2222                                                           ah->grh.sgid_index);
2223                 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4;
2224         } else {
2225                 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2226                 path->fl_free_ar |=
2227                         (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2228                 path->rlid = cpu_to_be16(ah->dlid);
2229                 path->grh_mlid = ah->src_path_bits & 0x7f;
2230                 if (ah->ah_flags & IB_AH_GRH)
2231                         path->grh_mlid  |= 1 << 7;
2232                 path->dci_cfi_prio_sl = ah->sl & 0xf;
2233         }
2234
2235         if (ah->ah_flags & IB_AH_GRH) {
2236                 path->mgid_index = ah->grh.sgid_index;
2237                 path->hop_limit  = ah->grh.hop_limit;
2238                 path->tclass_flowlabel =
2239                         cpu_to_be32((ah->grh.traffic_class << 20) |
2240                                     (ah->grh.flow_label));
2241                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
2242         }
2243
2244         err = ib_rate_to_mlx5(dev, ah->static_rate);
2245         if (err < 0)
2246                 return err;
2247         path->static_rate = err;
2248         path->port = port;
2249
2250         if (attr_mask & IB_QP_TIMEOUT)
2251                 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2252
2253         if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2254                 return modify_raw_packet_eth_prio(dev->mdev,
2255                                                   &qp->raw_packet_qp.sq,
2256                                                   ah->sl & 0xf);
2257
2258         return 0;
2259 }
2260
2261 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2262         [MLX5_QP_STATE_INIT] = {
2263                 [MLX5_QP_STATE_INIT] = {
2264                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2265                                           MLX5_QP_OPTPAR_RAE            |
2266                                           MLX5_QP_OPTPAR_RWE            |
2267                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2268                                           MLX5_QP_OPTPAR_PRI_PORT,
2269                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2270                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2271                                           MLX5_QP_OPTPAR_PRI_PORT,
2272                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2273                                           MLX5_QP_OPTPAR_Q_KEY          |
2274                                           MLX5_QP_OPTPAR_PRI_PORT,
2275                 },
2276                 [MLX5_QP_STATE_RTR] = {
2277                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2278                                           MLX5_QP_OPTPAR_RRE            |
2279                                           MLX5_QP_OPTPAR_RAE            |
2280                                           MLX5_QP_OPTPAR_RWE            |
2281                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2282                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2283                                           MLX5_QP_OPTPAR_RWE            |
2284                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2285                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2286                                           MLX5_QP_OPTPAR_Q_KEY,
2287                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX    |
2288                                            MLX5_QP_OPTPAR_Q_KEY,
2289                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2290                                           MLX5_QP_OPTPAR_RRE            |
2291                                           MLX5_QP_OPTPAR_RAE            |
2292                                           MLX5_QP_OPTPAR_RWE            |
2293                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2294                 },
2295         },
2296         [MLX5_QP_STATE_RTR] = {
2297                 [MLX5_QP_STATE_RTS] = {
2298                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2299                                           MLX5_QP_OPTPAR_RRE            |
2300                                           MLX5_QP_OPTPAR_RAE            |
2301                                           MLX5_QP_OPTPAR_RWE            |
2302                                           MLX5_QP_OPTPAR_PM_STATE       |
2303                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
2304                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2305                                           MLX5_QP_OPTPAR_RWE            |
2306                                           MLX5_QP_OPTPAR_PM_STATE,
2307                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2308                 },
2309         },
2310         [MLX5_QP_STATE_RTS] = {
2311                 [MLX5_QP_STATE_RTS] = {
2312                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2313                                           MLX5_QP_OPTPAR_RAE            |
2314                                           MLX5_QP_OPTPAR_RWE            |
2315                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
2316                                           MLX5_QP_OPTPAR_PM_STATE       |
2317                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2318                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2319                                           MLX5_QP_OPTPAR_PM_STATE       |
2320                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2321                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY          |
2322                                           MLX5_QP_OPTPAR_SRQN           |
2323                                           MLX5_QP_OPTPAR_CQN_RCV,
2324                 },
2325         },
2326         [MLX5_QP_STATE_SQER] = {
2327                 [MLX5_QP_STATE_RTS] = {
2328                         [MLX5_QP_ST_UD]  = MLX5_QP_OPTPAR_Q_KEY,
2329                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2330                         [MLX5_QP_ST_UC]  = MLX5_QP_OPTPAR_RWE,
2331                         [MLX5_QP_ST_RC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT   |
2332                                            MLX5_QP_OPTPAR_RWE           |
2333                                            MLX5_QP_OPTPAR_RAE           |
2334                                            MLX5_QP_OPTPAR_RRE,
2335                 },
2336         },
2337 };
2338
2339 static int ib_nr_to_mlx5_nr(int ib_mask)
2340 {
2341         switch (ib_mask) {
2342         case IB_QP_STATE:
2343                 return 0;
2344         case IB_QP_CUR_STATE:
2345                 return 0;
2346         case IB_QP_EN_SQD_ASYNC_NOTIFY:
2347                 return 0;
2348         case IB_QP_ACCESS_FLAGS:
2349                 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2350                         MLX5_QP_OPTPAR_RAE;
2351         case IB_QP_PKEY_INDEX:
2352                 return MLX5_QP_OPTPAR_PKEY_INDEX;
2353         case IB_QP_PORT:
2354                 return MLX5_QP_OPTPAR_PRI_PORT;
2355         case IB_QP_QKEY:
2356                 return MLX5_QP_OPTPAR_Q_KEY;
2357         case IB_QP_AV:
2358                 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2359                         MLX5_QP_OPTPAR_PRI_PORT;
2360         case IB_QP_PATH_MTU:
2361                 return 0;
2362         case IB_QP_TIMEOUT:
2363                 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2364         case IB_QP_RETRY_CNT:
2365                 return MLX5_QP_OPTPAR_RETRY_COUNT;
2366         case IB_QP_RNR_RETRY:
2367                 return MLX5_QP_OPTPAR_RNR_RETRY;
2368         case IB_QP_RQ_PSN:
2369                 return 0;
2370         case IB_QP_MAX_QP_RD_ATOMIC:
2371                 return MLX5_QP_OPTPAR_SRA_MAX;
2372         case IB_QP_ALT_PATH:
2373                 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2374         case IB_QP_MIN_RNR_TIMER:
2375                 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2376         case IB_QP_SQ_PSN:
2377                 return 0;
2378         case IB_QP_MAX_DEST_RD_ATOMIC:
2379                 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2380                         MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2381         case IB_QP_PATH_MIG_STATE:
2382                 return MLX5_QP_OPTPAR_PM_STATE;
2383         case IB_QP_CAP:
2384                 return 0;
2385         case IB_QP_DEST_QPN:
2386                 return 0;
2387         }
2388         return 0;
2389 }
2390
2391 static int ib_mask_to_mlx5_opt(int ib_mask)
2392 {
2393         int result = 0;
2394         int i;
2395
2396         for (i = 0; i < 8 * sizeof(int); i++) {
2397                 if ((1 << i) & ib_mask)
2398                         result |= ib_nr_to_mlx5_nr(1 << i);
2399         }
2400
2401         return result;
2402 }
2403
2404 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2405                                    struct mlx5_ib_rq *rq, int new_state,
2406                                    const struct mlx5_modify_raw_qp_param *raw_qp_param)
2407 {
2408         void *in;
2409         void *rqc;
2410         int inlen;
2411         int err;
2412
2413         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2414         in = mlx5_vzalloc(inlen);
2415         if (!in)
2416                 return -ENOMEM;
2417
2418         MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2419
2420         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2421         MLX5_SET(rqc, rqc, state, new_state);
2422
2423         if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2424                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2425                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
2426                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID);
2427                         MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2428                 } else
2429                         pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2430                                      dev->ib_dev.name);
2431         }
2432
2433         err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
2434         if (err)
2435                 goto out;
2436
2437         rq->state = new_state;
2438
2439 out:
2440         kvfree(in);
2441         return err;
2442 }
2443
2444 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2445                                    struct mlx5_ib_sq *sq, int new_state)
2446 {
2447         void *in;
2448         void *sqc;
2449         int inlen;
2450         int err;
2451
2452         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2453         in = mlx5_vzalloc(inlen);
2454         if (!in)
2455                 return -ENOMEM;
2456
2457         MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2458
2459         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2460         MLX5_SET(sqc, sqc, state, new_state);
2461
2462         err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2463         if (err)
2464                 goto out;
2465
2466         sq->state = new_state;
2467
2468 out:
2469         kvfree(in);
2470         return err;
2471 }
2472
2473 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2474                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2475                                 u8 tx_affinity)
2476 {
2477         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2478         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2479         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2480         int rq_state;
2481         int sq_state;
2482         int err;
2483
2484         switch (raw_qp_param->operation) {
2485         case MLX5_CMD_OP_RST2INIT_QP:
2486                 rq_state = MLX5_RQC_STATE_RDY;
2487                 sq_state = MLX5_SQC_STATE_RDY;
2488                 break;
2489         case MLX5_CMD_OP_2ERR_QP:
2490                 rq_state = MLX5_RQC_STATE_ERR;
2491                 sq_state = MLX5_SQC_STATE_ERR;
2492                 break;
2493         case MLX5_CMD_OP_2RST_QP:
2494                 rq_state = MLX5_RQC_STATE_RST;
2495                 sq_state = MLX5_SQC_STATE_RST;
2496                 break;
2497         case MLX5_CMD_OP_INIT2INIT_QP:
2498         case MLX5_CMD_OP_INIT2RTR_QP:
2499         case MLX5_CMD_OP_RTR2RTS_QP:
2500         case MLX5_CMD_OP_RTS2RTS_QP:
2501                 if (raw_qp_param->set_mask)
2502                         return -EINVAL;
2503                 else
2504                         return 0;
2505         default:
2506                 WARN_ON(1);
2507                 return -EINVAL;
2508         }
2509
2510         if (qp->rq.wqe_cnt) {
2511                 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
2512                 if (err)
2513                         return err;
2514         }
2515
2516         if (qp->sq.wqe_cnt) {
2517                 if (tx_affinity) {
2518                         err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2519                                                             tx_affinity);
2520                         if (err)
2521                                 return err;
2522                 }
2523
2524                 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state);
2525         }
2526
2527         return 0;
2528 }
2529
2530 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2531                                const struct ib_qp_attr *attr, int attr_mask,
2532                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
2533 {
2534         static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2535                 [MLX5_QP_STATE_RST] = {
2536                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2537                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2538                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_RST2INIT_QP,
2539                 },
2540                 [MLX5_QP_STATE_INIT]  = {
2541                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2542                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2543                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_INIT2INIT_QP,
2544                         [MLX5_QP_STATE_RTR]     = MLX5_CMD_OP_INIT2RTR_QP,
2545                 },
2546                 [MLX5_QP_STATE_RTR]   = {
2547                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2548                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2549                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTR2RTS_QP,
2550                 },
2551                 [MLX5_QP_STATE_RTS]   = {
2552                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2553                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2554                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTS2RTS_QP,
2555                 },
2556                 [MLX5_QP_STATE_SQD] = {
2557                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2558                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2559                 },
2560                 [MLX5_QP_STATE_SQER] = {
2561                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2562                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2563                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_SQERR2RTS_QP,
2564                 },
2565                 [MLX5_QP_STATE_ERR] = {
2566                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2567                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2568                 }
2569         };
2570
2571         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2572         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2573         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
2574         struct mlx5_ib_cq *send_cq, *recv_cq;
2575         struct mlx5_qp_context *context;
2576         struct mlx5_ib_pd *pd;
2577         struct mlx5_ib_port *mibport = NULL;
2578         enum mlx5_qp_state mlx5_cur, mlx5_new;
2579         enum mlx5_qp_optpar optpar;
2580         int sqd_event;
2581         int mlx5_st;
2582         int err;
2583         u16 op;
2584         u8 tx_affinity = 0;
2585
2586         context = kzalloc(sizeof(*context), GFP_KERNEL);
2587         if (!context)
2588                 return -ENOMEM;
2589
2590         err = to_mlx5_st(ibqp->qp_type);
2591         if (err < 0) {
2592                 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
2593                 goto out;
2594         }
2595
2596         context->flags = cpu_to_be32(err << 16);
2597
2598         if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2599                 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2600         } else {
2601                 switch (attr->path_mig_state) {
2602                 case IB_MIG_MIGRATED:
2603                         context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2604                         break;
2605                 case IB_MIG_REARM:
2606                         context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2607                         break;
2608                 case IB_MIG_ARMED:
2609                         context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2610                         break;
2611                 }
2612         }
2613
2614         if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2615                 if ((ibqp->qp_type == IB_QPT_RC) ||
2616                     (ibqp->qp_type == IB_QPT_UD &&
2617                      !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
2618                     (ibqp->qp_type == IB_QPT_UC) ||
2619                     (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2620                     (ibqp->qp_type == IB_QPT_XRC_INI) ||
2621                     (ibqp->qp_type == IB_QPT_XRC_TGT)) {
2622                         if (mlx5_lag_is_active(dev->mdev)) {
2623                                 tx_affinity = (unsigned int)atomic_add_return(1,
2624                                                 &dev->roce.next_port) %
2625                                                 MLX5_MAX_PORTS + 1;
2626                                 context->flags |= cpu_to_be32(tx_affinity << 24);
2627                         }
2628                 }
2629         }
2630
2631         if (is_sqp(ibqp->qp_type)) {
2632                 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2633         } else if (ibqp->qp_type == IB_QPT_UD ||
2634                    ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2635                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2636         } else if (attr_mask & IB_QP_PATH_MTU) {
2637                 if (attr->path_mtu < IB_MTU_256 ||
2638                     attr->path_mtu > IB_MTU_4096) {
2639                         mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2640                         err = -EINVAL;
2641                         goto out;
2642                 }
2643                 context->mtu_msgmax = (attr->path_mtu << 5) |
2644                                       (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
2645         }
2646
2647         if (attr_mask & IB_QP_DEST_QPN)
2648                 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2649
2650         if (attr_mask & IB_QP_PKEY_INDEX)
2651                 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
2652
2653         /* todo implement counter_index functionality */
2654
2655         if (is_sqp(ibqp->qp_type))
2656                 context->pri_path.port = qp->port;
2657
2658         if (attr_mask & IB_QP_PORT)
2659                 context->pri_path.port = attr->port_num;
2660
2661         if (attr_mask & IB_QP_AV) {
2662                 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
2663                                     attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
2664                                     attr_mask, 0, attr, false);
2665                 if (err)
2666                         goto out;
2667         }
2668
2669         if (attr_mask & IB_QP_TIMEOUT)
2670                 context->pri_path.ackto_lt |= attr->timeout << 3;
2671
2672         if (attr_mask & IB_QP_ALT_PATH) {
2673                 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2674                                     &context->alt_path,
2675                                     attr->alt_port_num,
2676                                     attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2677                                     0, attr, true);
2678                 if (err)
2679                         goto out;
2680         }
2681
2682         pd = get_pd(qp);
2683         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2684                 &send_cq, &recv_cq);
2685
2686         context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2687         context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2688         context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2689         context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2690
2691         if (attr_mask & IB_QP_RNR_RETRY)
2692                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2693
2694         if (attr_mask & IB_QP_RETRY_CNT)
2695                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2696
2697         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2698                 if (attr->max_rd_atomic)
2699                         context->params1 |=
2700                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2701         }
2702
2703         if (attr_mask & IB_QP_SQ_PSN)
2704                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2705
2706         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2707                 if (attr->max_dest_rd_atomic)
2708                         context->params2 |=
2709                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2710         }
2711
2712         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2713                 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2714
2715         if (attr_mask & IB_QP_MIN_RNR_TIMER)
2716                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2717
2718         if (attr_mask & IB_QP_RQ_PSN)
2719                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2720
2721         if (attr_mask & IB_QP_QKEY)
2722                 context->qkey = cpu_to_be32(attr->qkey);
2723
2724         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2725                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2726
2727         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
2728             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2729                 sqd_event = 1;
2730         else
2731                 sqd_event = 0;
2732
2733         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2734                 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
2735                                qp->port) - 1;
2736                 mibport = &dev->port[port_num];
2737                 context->qp_counter_set_usr_page |=
2738                         cpu_to_be32((u32)(mibport->q_cnt_id) << 24);
2739         }
2740
2741         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2742                 context->sq_crq_size |= cpu_to_be16(1 << 4);
2743
2744         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2745                 context->deth_sqpn = cpu_to_be32(1);
2746
2747         mlx5_cur = to_mlx5_state(cur_state);
2748         mlx5_new = to_mlx5_state(new_state);
2749         mlx5_st = to_mlx5_st(ibqp->qp_type);
2750         if (mlx5_st < 0)
2751                 goto out;
2752
2753         /* If moving to a reset or error state, we must disable page faults on
2754          * this QP and flush all current page faults. Otherwise a stale page
2755          * fault may attempt to work on this QP after it is reset and moved
2756          * again to RTS, and may cause the driver and the device to get out of
2757          * sync. */
2758         if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2759             (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR) &&
2760             (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
2761                 mlx5_ib_qp_disable_pagefaults(qp);
2762
2763         if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2764             !optab[mlx5_cur][mlx5_new])
2765                 goto out;
2766
2767         op = optab[mlx5_cur][mlx5_new];
2768         optpar = ib_mask_to_mlx5_opt(attr_mask);
2769         optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
2770
2771         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
2772                 struct mlx5_modify_raw_qp_param raw_qp_param = {};
2773
2774                 raw_qp_param.operation = op;
2775                 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2776                         raw_qp_param.rq_q_ctr_id = mibport->q_cnt_id;
2777                         raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
2778                 }
2779                 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
2780         } else {
2781                 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
2782                                           &base->mqp);
2783         }
2784
2785         if (err)
2786                 goto out;
2787
2788         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT &&
2789             (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
2790                 mlx5_ib_qp_enable_pagefaults(qp);
2791
2792         qp->state = new_state;
2793
2794         if (attr_mask & IB_QP_ACCESS_FLAGS)
2795                 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
2796         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2797                 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
2798         if (attr_mask & IB_QP_PORT)
2799                 qp->port = attr->port_num;
2800         if (attr_mask & IB_QP_ALT_PATH)
2801                 qp->trans_qp.alt_port = attr->alt_port_num;
2802
2803         /*
2804          * If we moved a kernel QP to RESET, clean up all old CQ
2805          * entries and reinitialize the QP.
2806          */
2807         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
2808                 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2809                                  ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2810                 if (send_cq != recv_cq)
2811                         mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
2812
2813                 qp->rq.head = 0;
2814                 qp->rq.tail = 0;
2815                 qp->sq.head = 0;
2816                 qp->sq.tail = 0;
2817                 qp->sq.cur_post = 0;
2818                 qp->sq.last_poll = 0;
2819                 qp->db.db[MLX5_RCV_DBR] = 0;
2820                 qp->db.db[MLX5_SND_DBR] = 0;
2821         }
2822
2823 out:
2824         kfree(context);
2825         return err;
2826 }
2827
2828 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2829                       int attr_mask, struct ib_udata *udata)
2830 {
2831         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2832         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2833         enum ib_qp_type qp_type;
2834         enum ib_qp_state cur_state, new_state;
2835         int err = -EINVAL;
2836         int port;
2837         enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
2838
2839         if (ibqp->rwq_ind_tbl)
2840                 return -ENOSYS;
2841
2842         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
2843                 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
2844
2845         qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
2846                 IB_QPT_GSI : ibqp->qp_type;
2847
2848         mutex_lock(&qp->mutex);
2849
2850         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2851         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2852
2853         if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
2854                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2855                 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
2856         }
2857
2858         if (qp_type != MLX5_IB_QPT_REG_UMR &&
2859             !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
2860                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
2861                             cur_state, new_state, ibqp->qp_type, attr_mask);
2862                 goto out;
2863         }
2864
2865         if ((attr_mask & IB_QP_PORT) &&
2866             (attr->port_num == 0 ||
2867              attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
2868                 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
2869                             attr->port_num, dev->num_ports);
2870                 goto out;
2871         }
2872
2873         if (attr_mask & IB_QP_PKEY_INDEX) {
2874                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2875                 if (attr->pkey_index >=
2876                     dev->mdev->port_caps[port - 1].pkey_table_len) {
2877                         mlx5_ib_dbg(dev, "invalid pkey index %d\n",
2878                                     attr->pkey_index);
2879                         goto out;
2880                 }
2881         }
2882
2883         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2884             attr->max_rd_atomic >
2885             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
2886                 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
2887                             attr->max_rd_atomic);
2888                 goto out;
2889         }
2890
2891         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2892             attr->max_dest_rd_atomic >
2893             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
2894                 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
2895                             attr->max_dest_rd_atomic);
2896                 goto out;
2897         }
2898
2899         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2900                 err = 0;
2901                 goto out;
2902         }
2903
2904         err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2905
2906 out:
2907         mutex_unlock(&qp->mutex);
2908         return err;
2909 }
2910
2911 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2912 {
2913         struct mlx5_ib_cq *cq;
2914         unsigned cur;
2915
2916         cur = wq->head - wq->tail;
2917         if (likely(cur + nreq < wq->max_post))
2918                 return 0;
2919
2920         cq = to_mcq(ib_cq);
2921         spin_lock(&cq->lock);
2922         cur = wq->head - wq->tail;
2923         spin_unlock(&cq->lock);
2924
2925         return cur + nreq >= wq->max_post;
2926 }
2927
2928 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
2929                                           u64 remote_addr, u32 rkey)
2930 {
2931         rseg->raddr    = cpu_to_be64(remote_addr);
2932         rseg->rkey     = cpu_to_be32(rkey);
2933         rseg->reserved = 0;
2934 }
2935
2936 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
2937                          struct ib_send_wr *wr, void *qend,
2938                          struct mlx5_ib_qp *qp, int *size)
2939 {
2940         void *seg = eseg;
2941
2942         memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
2943
2944         if (wr->send_flags & IB_SEND_IP_CSUM)
2945                 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
2946                                  MLX5_ETH_WQE_L4_CSUM;
2947
2948         seg += sizeof(struct mlx5_wqe_eth_seg);
2949         *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
2950
2951         if (wr->opcode == IB_WR_LSO) {
2952                 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
2953                 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start);
2954                 u64 left, leftlen, copysz;
2955                 void *pdata = ud_wr->header;
2956
2957                 left = ud_wr->hlen;
2958                 eseg->mss = cpu_to_be16(ud_wr->mss);
2959                 eseg->inline_hdr_sz = cpu_to_be16(left);
2960
2961                 /*
2962                  * check if there is space till the end of queue, if yes,
2963                  * copy all in one shot, otherwise copy till the end of queue,
2964                  * rollback and than the copy the left
2965                  */
2966                 leftlen = qend - (void *)eseg->inline_hdr_start;
2967                 copysz = min_t(u64, leftlen, left);
2968
2969                 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
2970
2971                 if (likely(copysz > size_of_inl_hdr_start)) {
2972                         seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
2973                         *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
2974                 }
2975
2976                 if (unlikely(copysz < left)) { /* the last wqe in the queue */
2977                         seg = mlx5_get_send_wqe(qp, 0);
2978                         left -= copysz;
2979                         pdata += copysz;
2980                         memcpy(seg, pdata, left);
2981                         seg += ALIGN(left, 16);
2982                         *size += ALIGN(left, 16) / 16;
2983                 }
2984         }
2985
2986         return seg;
2987 }
2988
2989 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
2990                              struct ib_send_wr *wr)
2991 {
2992         memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
2993         dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
2994         dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
2995 }
2996
2997 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
2998 {
2999         dseg->byte_count = cpu_to_be32(sg->length);
3000         dseg->lkey       = cpu_to_be32(sg->lkey);
3001         dseg->addr       = cpu_to_be64(sg->addr);
3002 }
3003
3004 static __be16 get_klm_octo(int npages)
3005 {
3006         return cpu_to_be16(ALIGN(npages, 8) / 2);
3007 }
3008
3009 static __be64 frwr_mkey_mask(void)
3010 {
3011         u64 result;
3012
3013         result = MLX5_MKEY_MASK_LEN             |
3014                 MLX5_MKEY_MASK_PAGE_SIZE        |
3015                 MLX5_MKEY_MASK_START_ADDR       |
3016                 MLX5_MKEY_MASK_EN_RINVAL        |
3017                 MLX5_MKEY_MASK_KEY              |
3018                 MLX5_MKEY_MASK_LR               |
3019                 MLX5_MKEY_MASK_LW               |
3020                 MLX5_MKEY_MASK_RR               |
3021                 MLX5_MKEY_MASK_RW               |
3022                 MLX5_MKEY_MASK_A                |
3023                 MLX5_MKEY_MASK_SMALL_FENCE      |
3024                 MLX5_MKEY_MASK_FREE;
3025
3026         return cpu_to_be64(result);
3027 }
3028
3029 static __be64 sig_mkey_mask(void)
3030 {
3031         u64 result;
3032
3033         result = MLX5_MKEY_MASK_LEN             |
3034                 MLX5_MKEY_MASK_PAGE_SIZE        |
3035                 MLX5_MKEY_MASK_START_ADDR       |
3036                 MLX5_MKEY_MASK_EN_SIGERR        |
3037                 MLX5_MKEY_MASK_EN_RINVAL        |
3038                 MLX5_MKEY_MASK_KEY              |
3039                 MLX5_MKEY_MASK_LR               |
3040                 MLX5_MKEY_MASK_LW               |
3041                 MLX5_MKEY_MASK_RR               |
3042                 MLX5_MKEY_MASK_RW               |
3043                 MLX5_MKEY_MASK_SMALL_FENCE      |
3044                 MLX5_MKEY_MASK_FREE             |
3045                 MLX5_MKEY_MASK_BSF_EN;
3046
3047         return cpu_to_be64(result);
3048 }
3049
3050 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
3051                                 struct mlx5_ib_mr *mr)
3052 {
3053         int ndescs = mr->ndescs;
3054
3055         memset(umr, 0, sizeof(*umr));
3056
3057         if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
3058                 /* KLMs take twice the size of MTTs */
3059                 ndescs *= 2;
3060
3061         umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3062         umr->klm_octowords = get_klm_octo(ndescs);
3063         umr->mkey_mask = frwr_mkey_mask();
3064 }
3065
3066 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
3067 {
3068         memset(umr, 0, sizeof(*umr));
3069         umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
3070         umr->flags = 1 << 7;
3071 }
3072
3073 static __be64 get_umr_reg_mr_mask(void)
3074 {
3075         u64 result;
3076
3077         result = MLX5_MKEY_MASK_LEN             |
3078                  MLX5_MKEY_MASK_PAGE_SIZE       |
3079                  MLX5_MKEY_MASK_START_ADDR      |
3080                  MLX5_MKEY_MASK_PD              |
3081                  MLX5_MKEY_MASK_LR              |
3082                  MLX5_MKEY_MASK_LW              |
3083                  MLX5_MKEY_MASK_KEY             |
3084                  MLX5_MKEY_MASK_RR              |
3085                  MLX5_MKEY_MASK_RW              |
3086                  MLX5_MKEY_MASK_A               |
3087                  MLX5_MKEY_MASK_FREE;
3088
3089         return cpu_to_be64(result);
3090 }
3091
3092 static __be64 get_umr_unreg_mr_mask(void)
3093 {
3094         u64 result;
3095
3096         result = MLX5_MKEY_MASK_FREE;
3097
3098         return cpu_to_be64(result);
3099 }
3100
3101 static __be64 get_umr_update_mtt_mask(void)
3102 {
3103         u64 result;
3104
3105         result = MLX5_MKEY_MASK_FREE;
3106
3107         return cpu_to_be64(result);
3108 }
3109
3110 static __be64 get_umr_update_translation_mask(void)
3111 {
3112         u64 result;
3113
3114         result = MLX5_MKEY_MASK_LEN |
3115                  MLX5_MKEY_MASK_PAGE_SIZE |
3116                  MLX5_MKEY_MASK_START_ADDR |
3117                  MLX5_MKEY_MASK_KEY |
3118                  MLX5_MKEY_MASK_FREE;
3119
3120         return cpu_to_be64(result);
3121 }
3122
3123 static __be64 get_umr_update_access_mask(void)
3124 {
3125         u64 result;
3126
3127         result = MLX5_MKEY_MASK_LW |
3128                  MLX5_MKEY_MASK_RR |
3129                  MLX5_MKEY_MASK_RW |
3130                  MLX5_MKEY_MASK_A |
3131                  MLX5_MKEY_MASK_KEY |
3132                  MLX5_MKEY_MASK_FREE;
3133
3134         return cpu_to_be64(result);
3135 }
3136
3137 static __be64 get_umr_update_pd_mask(void)
3138 {
3139         u64 result;
3140
3141         result = MLX5_MKEY_MASK_PD |
3142                  MLX5_MKEY_MASK_KEY |
3143                  MLX5_MKEY_MASK_FREE;
3144
3145         return cpu_to_be64(result);
3146 }
3147
3148 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3149                                 struct ib_send_wr *wr)
3150 {
3151         struct mlx5_umr_wr *umrwr = umr_wr(wr);
3152
3153         memset(umr, 0, sizeof(*umr));
3154
3155         if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3156                 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3157         else
3158                 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3159
3160         if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) {
3161                 umr->klm_octowords = get_klm_octo(umrwr->npages);
3162                 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) {
3163                         umr->mkey_mask = get_umr_update_mtt_mask();
3164                         umr->bsf_octowords = get_klm_octo(umrwr->target.offset);
3165                         umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
3166                 }
3167                 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3168                         umr->mkey_mask |= get_umr_update_translation_mask();
3169                 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_ACCESS)
3170                         umr->mkey_mask |= get_umr_update_access_mask();
3171                 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD)
3172                         umr->mkey_mask |= get_umr_update_pd_mask();
3173                 if (!umr->mkey_mask)
3174                         umr->mkey_mask = get_umr_reg_mr_mask();
3175         } else {
3176                 umr->mkey_mask = get_umr_unreg_mr_mask();
3177         }
3178
3179         if (!wr->num_sge)
3180                 umr->flags |= MLX5_UMR_INLINE;
3181 }
3182
3183 static u8 get_umr_flags(int acc)
3184 {
3185         return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
3186                (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
3187                (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
3188                (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
3189                 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
3190 }
3191
3192 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3193                              struct mlx5_ib_mr *mr,
3194                              u32 key, int access)
3195 {
3196         int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3197
3198         memset(seg, 0, sizeof(*seg));
3199
3200         if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
3201                 seg->log2_page_size = ilog2(mr->ibmr.page_size);
3202         else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
3203                 /* KLMs take twice the size of MTTs */
3204                 ndescs *= 2;
3205
3206         seg->flags = get_umr_flags(access) | mr->access_mode;
3207         seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3208         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3209         seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3210         seg->len = cpu_to_be64(mr->ibmr.length);
3211         seg->xlt_oct_size = cpu_to_be32(ndescs);
3212 }
3213
3214 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
3215 {
3216         memset(seg, 0, sizeof(*seg));
3217         seg->status = MLX5_MKEY_STATUS_FREE;
3218 }
3219
3220 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3221 {
3222         struct mlx5_umr_wr *umrwr = umr_wr(wr);
3223
3224         memset(seg, 0, sizeof(*seg));
3225         if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) {
3226                 seg->status = MLX5_MKEY_STATUS_FREE;
3227                 return;
3228         }
3229
3230         seg->flags = convert_access(umrwr->access_flags);
3231         if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) {
3232                 if (umrwr->pd)
3233                         seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3234                 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr);
3235         }
3236         seg->len = cpu_to_be64(umrwr->length);
3237         seg->log2_page_size = umrwr->page_shift;
3238         seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
3239                                        mlx5_mkey_variant(umrwr->mkey));
3240 }
3241
3242 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3243                              struct mlx5_ib_mr *mr,
3244                              struct mlx5_ib_pd *pd)
3245 {
3246         int bcount = mr->desc_size * mr->ndescs;
3247
3248         dseg->addr = cpu_to_be64(mr->desc_map);
3249         dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3250         dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3251 }
3252
3253 static __be32 send_ieth(struct ib_send_wr *wr)
3254 {
3255         switch (wr->opcode) {
3256         case IB_WR_SEND_WITH_IMM:
3257         case IB_WR_RDMA_WRITE_WITH_IMM:
3258                 return wr->ex.imm_data;
3259
3260         case IB_WR_SEND_WITH_INV:
3261                 return cpu_to_be32(wr->ex.invalidate_rkey);
3262
3263         default:
3264                 return 0;
3265         }
3266 }
3267
3268 static u8 calc_sig(void *wqe, int size)
3269 {
3270         u8 *p = wqe;
3271         u8 res = 0;
3272         int i;
3273
3274         for (i = 0; i < size; i++)
3275                 res ^= p[i];
3276
3277         return ~res;
3278 }
3279
3280 static u8 wq_sig(void *wqe)
3281 {
3282         return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3283 }
3284
3285 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3286                             void *wqe, int *sz)
3287 {
3288         struct mlx5_wqe_inline_seg *seg;
3289         void *qend = qp->sq.qend;
3290         void *addr;
3291         int inl = 0;
3292         int copy;
3293         int len;
3294         int i;
3295
3296         seg = wqe;
3297         wqe += sizeof(*seg);
3298         for (i = 0; i < wr->num_sge; i++) {
3299                 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3300                 len  = wr->sg_list[i].length;
3301                 inl += len;
3302
3303                 if (unlikely(inl > qp->max_inline_data))
3304                         return -ENOMEM;
3305
3306                 if (unlikely(wqe + len > qend)) {
3307                         copy = qend - wqe;
3308                         memcpy(wqe, addr, copy);
3309                         addr += copy;
3310                         len -= copy;
3311                         wqe = mlx5_get_send_wqe(qp, 0);
3312                 }
3313                 memcpy(wqe, addr, len);
3314                 wqe += len;
3315         }
3316
3317         seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3318
3319         *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3320
3321         return 0;
3322 }
3323
3324 static u16 prot_field_size(enum ib_signature_type type)
3325 {
3326         switch (type) {
3327         case IB_SIG_TYPE_T10_DIF:
3328                 return MLX5_DIF_SIZE;
3329         default:
3330                 return 0;
3331         }
3332 }
3333
3334 static u8 bs_selector(int block_size)
3335 {
3336         switch (block_size) {
3337         case 512:           return 0x1;
3338         case 520:           return 0x2;
3339         case 4096:          return 0x3;
3340         case 4160:          return 0x4;
3341         case 1073741824:    return 0x5;
3342         default:            return 0;
3343         }
3344 }
3345
3346 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3347                               struct mlx5_bsf_inl *inl)
3348 {
3349         /* Valid inline section and allow BSF refresh */
3350         inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3351                                        MLX5_BSF_REFRESH_DIF);
3352         inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3353         inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
3354         /* repeating block */
3355         inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3356         inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3357                         MLX5_DIF_CRC : MLX5_DIF_IPCS;
3358
3359         if (domain->sig.dif.ref_remap)
3360                 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
3361
3362         if (domain->sig.dif.app_escape) {
3363                 if (domain->sig.dif.ref_escape)
3364                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3365                 else
3366                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
3367         }
3368
3369         inl->dif_app_bitmask_check =
3370                 cpu_to_be16(domain->sig.dif.apptag_check_mask);
3371 }
3372
3373 static int mlx5_set_bsf(struct ib_mr *sig_mr,
3374                         struct ib_sig_attrs *sig_attrs,
3375                         struct mlx5_bsf *bsf, u32 data_size)
3376 {
3377         struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3378         struct mlx5_bsf_basic *basic = &bsf->basic;
3379         struct ib_sig_domain *mem = &sig_attrs->mem;
3380         struct ib_sig_domain *wire = &sig_attrs->wire;
3381
3382         memset(bsf, 0, sizeof(*bsf));
3383
3384         /* Basic + Extended + Inline */
3385         basic->bsf_size_sbs = 1 << 7;
3386         /* Input domain check byte mask */
3387         basic->check_byte_mask = sig_attrs->check_mask;
3388         basic->raw_data_size = cpu_to_be32(data_size);
3389
3390         /* Memory domain */
3391         switch (sig_attrs->mem.sig_type) {
3392         case IB_SIG_TYPE_NONE:
3393                 break;
3394         case IB_SIG_TYPE_T10_DIF:
3395                 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3396                 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3397                 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3398                 break;
3399         default:
3400                 return -EINVAL;
3401         }
3402
3403         /* Wire domain */
3404         switch (sig_attrs->wire.sig_type) {
3405         case IB_SIG_TYPE_NONE:
3406                 break;
3407         case IB_SIG_TYPE_T10_DIF:
3408                 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
3409                     mem->sig_type == wire->sig_type) {
3410                         /* Same block structure */
3411                         basic->bsf_size_sbs |= 1 << 4;
3412                         if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
3413                                 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
3414                         if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
3415                                 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
3416                         if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
3417                                 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
3418                 } else
3419                         basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3420
3421                 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
3422                 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
3423                 break;
3424         default:
3425                 return -EINVAL;
3426         }
3427
3428         return 0;
3429 }
3430
3431 static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3432                                 struct mlx5_ib_qp *qp, void **seg, int *size)
3433 {
3434         struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3435         struct ib_mr *sig_mr = wr->sig_mr;
3436         struct mlx5_bsf *bsf;
3437         u32 data_len = wr->wr.sg_list->length;
3438         u32 data_key = wr->wr.sg_list->lkey;
3439         u64 data_va = wr->wr.sg_list->addr;
3440         int ret;
3441         int wqe_size;
3442
3443         if (!wr->prot ||
3444             (data_key == wr->prot->lkey &&
3445              data_va == wr->prot->addr &&
3446              data_len == wr->prot->length)) {
3447                 /**
3448                  * Source domain doesn't contain signature information
3449                  * or data and protection are interleaved in memory.
3450                  * So need construct:
3451                  *                  ------------------
3452                  *                 |     data_klm     |
3453                  *                  ------------------
3454                  *                 |       BSF        |
3455                  *                  ------------------
3456                  **/
3457                 struct mlx5_klm *data_klm = *seg;
3458
3459                 data_klm->bcount = cpu_to_be32(data_len);
3460                 data_klm->key = cpu_to_be32(data_key);
3461                 data_klm->va = cpu_to_be64(data_va);
3462                 wqe_size = ALIGN(sizeof(*data_klm), 64);
3463         } else {
3464                 /**
3465                  * Source domain contains signature information
3466                  * So need construct a strided block format:
3467                  *               ---------------------------
3468                  *              |     stride_block_ctrl     |
3469                  *               ---------------------------
3470                  *              |          data_klm         |
3471                  *               ---------------------------
3472                  *              |          prot_klm         |
3473                  *               ---------------------------
3474                  *              |             BSF           |
3475                  *               ---------------------------
3476                  **/
3477                 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3478                 struct mlx5_stride_block_entry *data_sentry;
3479                 struct mlx5_stride_block_entry *prot_sentry;
3480                 u32 prot_key = wr->prot->lkey;
3481                 u64 prot_va = wr->prot->addr;
3482                 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3483                 int prot_size;
3484
3485                 sblock_ctrl = *seg;
3486                 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3487                 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3488
3489                 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3490                 if (!prot_size) {
3491                         pr_err("Bad block size given: %u\n", block_size);
3492                         return -EINVAL;
3493                 }
3494                 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3495                                                             prot_size);
3496                 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3497                 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3498                 sblock_ctrl->num_entries = cpu_to_be16(2);
3499
3500                 data_sentry->bcount = cpu_to_be16(block_size);
3501                 data_sentry->key = cpu_to_be32(data_key);
3502                 data_sentry->va = cpu_to_be64(data_va);
3503                 data_sentry->stride = cpu_to_be16(block_size);
3504
3505                 prot_sentry->bcount = cpu_to_be16(prot_size);
3506                 prot_sentry->key = cpu_to_be32(prot_key);
3507                 prot_sentry->va = cpu_to_be64(prot_va);
3508                 prot_sentry->stride = cpu_to_be16(prot_size);
3509
3510                 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3511                                  sizeof(*prot_sentry), 64);
3512         }
3513
3514         *seg += wqe_size;
3515         *size += wqe_size / 16;
3516         if (unlikely((*seg == qp->sq.qend)))
3517                 *seg = mlx5_get_send_wqe(qp, 0);
3518
3519         bsf = *seg;
3520         ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3521         if (ret)
3522                 return -EINVAL;
3523
3524         *seg += sizeof(*bsf);
3525         *size += sizeof(*bsf) / 16;
3526         if (unlikely((*seg == qp->sq.qend)))
3527                 *seg = mlx5_get_send_wqe(qp, 0);
3528
3529         return 0;
3530 }
3531
3532 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
3533                                  struct ib_sig_handover_wr *wr, u32 nelements,
3534                                  u32 length, u32 pdn)
3535 {
3536         struct ib_mr *sig_mr = wr->sig_mr;
3537         u32 sig_key = sig_mr->rkey;
3538         u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
3539
3540         memset(seg, 0, sizeof(*seg));
3541
3542         seg->flags = get_umr_flags(wr->access_flags) |
3543                                    MLX5_MKC_ACCESS_MODE_KLMS;
3544         seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
3545         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
3546                                     MLX5_MKEY_BSF_EN | pdn);
3547         seg->len = cpu_to_be64(length);
3548         seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements)));
3549         seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3550 }
3551
3552 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3553                                 u32 nelements)
3554 {
3555         memset(umr, 0, sizeof(*umr));
3556
3557         umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
3558         umr->klm_octowords = get_klm_octo(nelements);
3559         umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3560         umr->mkey_mask = sig_mkey_mask();
3561 }
3562
3563
3564 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
3565                           void **seg, int *size)
3566 {
3567         struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3568         struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
3569         u32 pdn = get_pd(qp)->pdn;
3570         u32 klm_oct_size;
3571         int region_len, ret;
3572
3573         if (unlikely(wr->wr.num_sge != 1) ||
3574             unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
3575             unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3576             unlikely(!sig_mr->sig->sig_status_checked))
3577                 return -EINVAL;
3578
3579         /* length of the protected region, data + protection */
3580         region_len = wr->wr.sg_list->length;
3581         if (wr->prot &&
3582             (wr->prot->lkey != wr->wr.sg_list->lkey  ||
3583              wr->prot->addr != wr->wr.sg_list->addr  ||
3584              wr->prot->length != wr->wr.sg_list->length))
3585                 region_len += wr->prot->length;
3586
3587         /**
3588          * KLM octoword size - if protection was provided
3589          * then we use strided block format (3 octowords),
3590          * else we use single KLM (1 octoword)
3591          **/
3592         klm_oct_size = wr->prot ? 3 : 1;
3593
3594         set_sig_umr_segment(*seg, klm_oct_size);
3595         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3596         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3597         if (unlikely((*seg == qp->sq.qend)))
3598                 *seg = mlx5_get_send_wqe(qp, 0);
3599
3600         set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn);
3601         *seg += sizeof(struct mlx5_mkey_seg);
3602         *size += sizeof(struct mlx5_mkey_seg) / 16;
3603         if (unlikely((*seg == qp->sq.qend)))
3604                 *seg = mlx5_get_send_wqe(qp, 0);
3605
3606         ret = set_sig_data_segment(wr, qp, seg, size);
3607         if (ret)
3608                 return ret;
3609
3610         sig_mr->sig->sig_status_checked = false;
3611         return 0;
3612 }
3613
3614 static int set_psv_wr(struct ib_sig_domain *domain,
3615                       u32 psv_idx, void **seg, int *size)
3616 {
3617         struct mlx5_seg_set_psv *psv_seg = *seg;
3618
3619         memset(psv_seg, 0, sizeof(*psv_seg));
3620         psv_seg->psv_num = cpu_to_be32(psv_idx);
3621         switch (domain->sig_type) {
3622         case IB_SIG_TYPE_NONE:
3623                 break;
3624         case IB_SIG_TYPE_T10_DIF:
3625                 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3626                                                      domain->sig.dif.app_tag);
3627                 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
3628                 break;
3629         default:
3630                 pr_err("Bad signature type given.\n");
3631                 return 1;
3632         }
3633
3634         *seg += sizeof(*psv_seg);
3635         *size += sizeof(*psv_seg) / 16;
3636
3637         return 0;
3638 }
3639
3640 static int set_reg_wr(struct mlx5_ib_qp *qp,
3641                       struct ib_reg_wr *wr,
3642                       void **seg, int *size)
3643 {
3644         struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3645         struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3646
3647         if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3648                 mlx5_ib_warn(to_mdev(qp->ibqp.device),
3649                              "Invalid IB_SEND_INLINE send flag\n");
3650                 return -EINVAL;
3651         }
3652
3653         set_reg_umr_seg(*seg, mr);
3654         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3655         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3656         if (unlikely((*seg == qp->sq.qend)))
3657                 *seg = mlx5_get_send_wqe(qp, 0);
3658
3659         set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3660         *seg += sizeof(struct mlx5_mkey_seg);
3661         *size += sizeof(struct mlx5_mkey_seg) / 16;
3662         if (unlikely((*seg == qp->sq.qend)))
3663                 *seg = mlx5_get_send_wqe(qp, 0);
3664
3665         set_reg_data_seg(*seg, mr, pd);
3666         *seg += sizeof(struct mlx5_wqe_data_seg);
3667         *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3668
3669         return 0;
3670 }
3671
3672 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
3673 {
3674         set_linv_umr_seg(*seg);
3675         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3676         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3677         if (unlikely((*seg == qp->sq.qend)))
3678                 *seg = mlx5_get_send_wqe(qp, 0);
3679         set_linv_mkey_seg(*seg);
3680         *seg += sizeof(struct mlx5_mkey_seg);
3681         *size += sizeof(struct mlx5_mkey_seg) / 16;
3682         if (unlikely((*seg == qp->sq.qend)))
3683                 *seg = mlx5_get_send_wqe(qp, 0);
3684 }
3685
3686 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3687 {
3688         __be32 *p = NULL;
3689         int tidx = idx;
3690         int i, j;
3691
3692         pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3693         for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3694                 if ((i & 0xf) == 0) {
3695                         void *buf = mlx5_get_send_wqe(qp, tidx);
3696                         tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3697                         p = buf;
3698                         j = 0;
3699                 }
3700                 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3701                          be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3702                          be32_to_cpu(p[j + 3]));
3703         }
3704 }
3705
3706 static void mlx5_bf_copy(u64 __iomem *dst, u64 *src,
3707                          unsigned bytecnt, struct mlx5_ib_qp *qp)
3708 {
3709         while (bytecnt > 0) {
3710                 __iowrite64_copy(dst++, src++, 8);
3711                 __iowrite64_copy(dst++, src++, 8);
3712                 __iowrite64_copy(dst++, src++, 8);
3713                 __iowrite64_copy(dst++, src++, 8);
3714                 __iowrite64_copy(dst++, src++, 8);
3715                 __iowrite64_copy(dst++, src++, 8);
3716                 __iowrite64_copy(dst++, src++, 8);
3717                 __iowrite64_copy(dst++, src++, 8);
3718                 bytecnt -= 64;
3719                 if (unlikely(src == qp->sq.qend))
3720                         src = mlx5_get_send_wqe(qp, 0);
3721         }
3722 }
3723
3724 static u8 get_fence(u8 fence, struct ib_send_wr *wr)
3725 {
3726         if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
3727                      wr->send_flags & IB_SEND_FENCE))
3728                 return MLX5_FENCE_MODE_STRONG_ORDERING;
3729
3730         if (unlikely(fence)) {
3731                 if (wr->send_flags & IB_SEND_FENCE)
3732                         return MLX5_FENCE_MODE_SMALL_AND_FENCE;
3733                 else
3734                         return fence;
3735         } else if (unlikely(wr->send_flags & IB_SEND_FENCE)) {
3736                 return MLX5_FENCE_MODE_FENCE;
3737         }
3738
3739         return 0;
3740 }
3741
3742 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3743                      struct mlx5_wqe_ctrl_seg **ctrl,
3744                      struct ib_send_wr *wr, unsigned *idx,
3745                      int *size, int nreq)
3746 {
3747         int err = 0;
3748
3749         if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) {
3750                 err = -ENOMEM;
3751                 return err;
3752         }
3753
3754         *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3755         *seg = mlx5_get_send_wqe(qp, *idx);
3756         *ctrl = *seg;
3757         *(uint32_t *)(*seg + 8) = 0;
3758         (*ctrl)->imm = send_ieth(wr);
3759         (*ctrl)->fm_ce_se = qp->sq_signal_bits |
3760                 (wr->send_flags & IB_SEND_SIGNALED ?
3761                  MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3762                 (wr->send_flags & IB_SEND_SOLICITED ?
3763                  MLX5_WQE_CTRL_SOLICITED : 0);
3764
3765         *seg += sizeof(**ctrl);
3766         *size = sizeof(**ctrl) / 16;
3767
3768         return err;
3769 }
3770
3771 static void finish_wqe(struct mlx5_ib_qp *qp,
3772                        struct mlx5_wqe_ctrl_seg *ctrl,
3773                        u8 size, unsigned idx, u64 wr_id,
3774                        int nreq, u8 fence, u8 next_fence,
3775                        u32 mlx5_opcode)
3776 {
3777         u8 opmod = 0;
3778
3779         ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3780                                              mlx5_opcode | ((u32)opmod << 24));
3781         ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
3782         ctrl->fm_ce_se |= fence;
3783         qp->fm_cache = next_fence;
3784         if (unlikely(qp->wq_sig))
3785                 ctrl->signature = wq_sig(ctrl);
3786
3787         qp->sq.wrid[idx] = wr_id;
3788         qp->sq.w_list[idx].opcode = mlx5_opcode;
3789         qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3790         qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3791         qp->sq.w_list[idx].next = qp->sq.cur_post;
3792 }
3793
3794
3795 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3796                       struct ib_send_wr **bad_wr)
3797 {
3798         struct mlx5_wqe_ctrl_seg *ctrl = NULL;  /* compiler warning */
3799         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3800         struct mlx5_core_dev *mdev = dev->mdev;
3801         struct mlx5_ib_qp *qp;
3802         struct mlx5_ib_mr *mr;
3803         struct mlx5_wqe_data_seg *dpseg;
3804         struct mlx5_wqe_xrc_seg *xrc;
3805         struct mlx5_bf *bf;
3806         int uninitialized_var(size);
3807         void *qend;
3808         unsigned long flags;
3809         unsigned idx;
3810         int err = 0;
3811         int inl = 0;
3812         int num_sge;
3813         void *seg;
3814         int nreq;
3815         int i;
3816         u8 next_fence = 0;
3817         u8 fence;
3818
3819         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3820                 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
3821
3822         qp = to_mqp(ibqp);
3823         bf = qp->bf;
3824         qend = qp->sq.qend;
3825
3826         spin_lock_irqsave(&qp->sq.lock, flags);
3827
3828         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
3829                 err = -EIO;
3830                 *bad_wr = wr;
3831                 nreq = 0;
3832                 goto out;
3833         }
3834
3835         for (nreq = 0; wr; nreq++, wr = wr->next) {
3836                 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
3837                         mlx5_ib_warn(dev, "\n");
3838                         err = -EINVAL;
3839                         *bad_wr = wr;
3840                         goto out;
3841                 }
3842
3843                 fence = qp->fm_cache;
3844                 num_sge = wr->num_sge;
3845                 if (unlikely(num_sge > qp->sq.max_gs)) {
3846                         mlx5_ib_warn(dev, "\n");
3847                         err = -ENOMEM;
3848                         *bad_wr = wr;
3849                         goto out;
3850                 }
3851
3852                 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3853                 if (err) {
3854                         mlx5_ib_warn(dev, "\n");
3855                         err = -ENOMEM;
3856                         *bad_wr = wr;
3857                         goto out;
3858                 }
3859
3860                 switch (ibqp->qp_type) {
3861                 case IB_QPT_XRC_INI:
3862                         xrc = seg;
3863                         seg += sizeof(*xrc);
3864                         size += sizeof(*xrc) / 16;
3865                         /* fall through */
3866                 case IB_QPT_RC:
3867                         switch (wr->opcode) {
3868                         case IB_WR_RDMA_READ:
3869                         case IB_WR_RDMA_WRITE:
3870                         case IB_WR_RDMA_WRITE_WITH_IMM:
3871                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3872                                               rdma_wr(wr)->rkey);
3873                                 seg += sizeof(struct mlx5_wqe_raddr_seg);
3874                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3875                                 break;
3876
3877                         case IB_WR_ATOMIC_CMP_AND_SWP:
3878                         case IB_WR_ATOMIC_FETCH_AND_ADD:
3879                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
3880                                 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
3881                                 err = -ENOSYS;
3882                                 *bad_wr = wr;
3883                                 goto out;
3884
3885                         case IB_WR_LOCAL_INV:
3886                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3887                                 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
3888                                 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
3889                                 set_linv_wr(qp, &seg, &size);
3890                                 num_sge = 0;
3891                                 break;
3892
3893                         case IB_WR_REG_MR:
3894                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3895                                 qp->sq.wr_data[idx] = IB_WR_REG_MR;
3896                                 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
3897                                 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
3898                                 if (err) {
3899                                         *bad_wr = wr;
3900                                         goto out;
3901                                 }
3902                                 num_sge = 0;
3903                                 break;
3904
3905                         case IB_WR_REG_SIG_MR:
3906                                 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
3907                                 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
3908
3909                                 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
3910                                 err = set_sig_umr_wr(wr, qp, &seg, &size);
3911                                 if (err) {
3912                                         mlx5_ib_warn(dev, "\n");
3913                                         *bad_wr = wr;
3914                                         goto out;
3915                                 }
3916
3917                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3918                                            nreq, get_fence(fence, wr),
3919                                            next_fence, MLX5_OPCODE_UMR);
3920                                 /*
3921                                  * SET_PSV WQEs are not signaled and solicited
3922                                  * on error
3923                                  */
3924                                 wr->send_flags &= ~IB_SEND_SIGNALED;
3925                                 wr->send_flags |= IB_SEND_SOLICITED;
3926                                 err = begin_wqe(qp, &seg, &ctrl, wr,
3927                                                 &idx, &size, nreq);
3928                                 if (err) {
3929                                         mlx5_ib_warn(dev, "\n");
3930                                         err = -ENOMEM;
3931                                         *bad_wr = wr;
3932                                         goto out;
3933                                 }
3934
3935                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
3936                                                  mr->sig->psv_memory.psv_idx, &seg,
3937                                                  &size);
3938                                 if (err) {
3939                                         mlx5_ib_warn(dev, "\n");
3940                                         *bad_wr = wr;
3941                                         goto out;
3942                                 }
3943
3944                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3945                                            nreq, get_fence(fence, wr),
3946                                            next_fence, MLX5_OPCODE_SET_PSV);
3947                                 err = begin_wqe(qp, &seg, &ctrl, wr,
3948                                                 &idx, &size, nreq);
3949                                 if (err) {
3950                                         mlx5_ib_warn(dev, "\n");
3951                                         err = -ENOMEM;
3952                                         *bad_wr = wr;
3953                                         goto out;
3954                                 }
3955
3956                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3957                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
3958                                                  mr->sig->psv_wire.psv_idx, &seg,
3959                                                  &size);
3960                                 if (err) {
3961                                         mlx5_ib_warn(dev, "\n");
3962                                         *bad_wr = wr;
3963                                         goto out;
3964                                 }
3965
3966                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3967                                            nreq, get_fence(fence, wr),
3968                                            next_fence, MLX5_OPCODE_SET_PSV);
3969                                 num_sge = 0;
3970                                 goto skip_psv;
3971
3972                         default:
3973                                 break;
3974                         }
3975                         break;
3976
3977                 case IB_QPT_UC:
3978                         switch (wr->opcode) {
3979                         case IB_WR_RDMA_WRITE:
3980                         case IB_WR_RDMA_WRITE_WITH_IMM:
3981                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3982                                               rdma_wr(wr)->rkey);
3983                                 seg  += sizeof(struct mlx5_wqe_raddr_seg);
3984                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3985                                 break;
3986
3987                         default:
3988                                 break;
3989                         }
3990                         break;
3991
3992                 case IB_QPT_SMI:
3993                 case MLX5_IB_QPT_HW_GSI:
3994                         set_datagram_seg(seg, wr);
3995                         seg += sizeof(struct mlx5_wqe_datagram_seg);
3996                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
3997                         if (unlikely((seg == qend)))
3998                                 seg = mlx5_get_send_wqe(qp, 0);
3999                         break;
4000                 case IB_QPT_UD:
4001                         set_datagram_seg(seg, wr);
4002                         seg += sizeof(struct mlx5_wqe_datagram_seg);
4003                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4004
4005                         if (unlikely((seg == qend)))
4006                                 seg = mlx5_get_send_wqe(qp, 0);
4007
4008                         /* handle qp that supports ud offload */
4009                         if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4010                                 struct mlx5_wqe_eth_pad *pad;
4011
4012                                 pad = seg;
4013                                 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4014                                 seg += sizeof(struct mlx5_wqe_eth_pad);
4015                                 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4016
4017                                 seg = set_eth_seg(seg, wr, qend, qp, &size);
4018
4019                                 if (unlikely((seg == qend)))
4020                                         seg = mlx5_get_send_wqe(qp, 0);
4021                         }
4022                         break;
4023                 case MLX5_IB_QPT_REG_UMR:
4024                         if (wr->opcode != MLX5_IB_WR_UMR) {
4025                                 err = -EINVAL;
4026                                 mlx5_ib_warn(dev, "bad opcode\n");
4027                                 goto out;
4028                         }
4029                         qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
4030                         ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
4031                         set_reg_umr_segment(seg, wr);
4032                         seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4033                         size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4034                         if (unlikely((seg == qend)))
4035                                 seg = mlx5_get_send_wqe(qp, 0);
4036                         set_reg_mkey_segment(seg, wr);
4037                         seg += sizeof(struct mlx5_mkey_seg);
4038                         size += sizeof(struct mlx5_mkey_seg) / 16;
4039                         if (unlikely((seg == qend)))
4040                                 seg = mlx5_get_send_wqe(qp, 0);
4041                         break;
4042
4043                 default:
4044                         break;
4045                 }
4046
4047                 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4048                         int uninitialized_var(sz);
4049
4050                         err = set_data_inl_seg(qp, wr, seg, &sz);
4051                         if (unlikely(err)) {
4052                                 mlx5_ib_warn(dev, "\n");
4053                                 *bad_wr = wr;
4054                                 goto out;
4055                         }
4056                         inl = 1;
4057                         size += sz;
4058                 } else {
4059                         dpseg = seg;
4060                         for (i = 0; i < num_sge; i++) {
4061                                 if (unlikely(dpseg == qend)) {
4062                                         seg = mlx5_get_send_wqe(qp, 0);
4063                                         dpseg = seg;
4064                                 }
4065                                 if (likely(wr->sg_list[i].length)) {
4066                                         set_data_ptr_seg(dpseg, wr->sg_list + i);
4067                                         size += sizeof(struct mlx5_wqe_data_seg) / 16;
4068                                         dpseg++;
4069                                 }
4070                         }
4071                 }
4072
4073                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4074                            get_fence(fence, wr), next_fence,
4075                            mlx5_ib_opcode[wr->opcode]);
4076 skip_psv:
4077                 if (0)
4078                         dump_wqe(qp, idx, size);
4079         }
4080
4081 out:
4082         if (likely(nreq)) {
4083                 qp->sq.head += nreq;
4084
4085                 /* Make sure that descriptors are written before
4086                  * updating doorbell record and ringing the doorbell
4087                  */
4088                 wmb();
4089
4090                 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4091
4092                 /* Make sure doorbell record is visible to the HCA before
4093                  * we hit doorbell */
4094                 wmb();
4095
4096                 if (bf->need_lock)
4097                         spin_lock(&bf->lock);
4098                 else
4099                         __acquire(&bf->lock);
4100
4101                 /* TBD enable WC */
4102                 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) {
4103                         mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp);
4104                         /* wc_wmb(); */
4105                 } else {
4106                         mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset,
4107                                      MLX5_GET_DOORBELL_LOCK(&bf->lock32));
4108                         /* Make sure doorbells don't leak out of SQ spinlock
4109                          * and reach the HCA out of order.
4110                          */
4111                         mmiowb();
4112                 }
4113                 bf->offset ^= bf->buf_size;
4114                 if (bf->need_lock)
4115                         spin_unlock(&bf->lock);
4116                 else
4117                         __release(&bf->lock);
4118         }
4119
4120         spin_unlock_irqrestore(&qp->sq.lock, flags);
4121
4122         return err;
4123 }
4124
4125 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4126 {
4127         sig->signature = calc_sig(sig, size);
4128 }
4129
4130 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4131                       struct ib_recv_wr **bad_wr)
4132 {
4133         struct mlx5_ib_qp *qp = to_mqp(ibqp);
4134         struct mlx5_wqe_data_seg *scat;
4135         struct mlx5_rwqe_sig *sig;
4136         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4137         struct mlx5_core_dev *mdev = dev->mdev;
4138         unsigned long flags;
4139         int err = 0;
4140         int nreq;
4141         int ind;
4142         int i;
4143
4144         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4145                 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4146
4147         spin_lock_irqsave(&qp->rq.lock, flags);
4148
4149         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4150                 err = -EIO;
4151                 *bad_wr = wr;
4152                 nreq = 0;
4153                 goto out;
4154         }
4155
4156         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4157
4158         for (nreq = 0; wr; nreq++, wr = wr->next) {
4159                 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4160                         err = -ENOMEM;
4161                         *bad_wr = wr;
4162                         goto out;
4163                 }
4164
4165                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4166                         err = -EINVAL;
4167                         *bad_wr = wr;
4168                         goto out;
4169                 }
4170
4171                 scat = get_recv_wqe(qp, ind);
4172                 if (qp->wq_sig)
4173                         scat++;
4174
4175                 for (i = 0; i < wr->num_sge; i++)
4176                         set_data_ptr_seg(scat + i, wr->sg_list + i);
4177
4178                 if (i < qp->rq.max_gs) {
4179                         scat[i].byte_count = 0;
4180                         scat[i].lkey       = cpu_to_be32(MLX5_INVALID_LKEY);
4181                         scat[i].addr       = 0;
4182                 }
4183
4184                 if (qp->wq_sig) {
4185                         sig = (struct mlx5_rwqe_sig *)scat;
4186                         set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4187                 }
4188
4189                 qp->rq.wrid[ind] = wr->wr_id;
4190
4191                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4192         }
4193
4194 out:
4195         if (likely(nreq)) {
4196                 qp->rq.head += nreq;
4197
4198                 /* Make sure that descriptors are written before
4199                  * doorbell record.
4200                  */
4201                 wmb();
4202
4203                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4204         }
4205
4206         spin_unlock_irqrestore(&qp->rq.lock, flags);
4207
4208         return err;
4209 }
4210
4211 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4212 {
4213         switch (mlx5_state) {
4214         case MLX5_QP_STATE_RST:      return IB_QPS_RESET;
4215         case MLX5_QP_STATE_INIT:     return IB_QPS_INIT;
4216         case MLX5_QP_STATE_RTR:      return IB_QPS_RTR;
4217         case MLX5_QP_STATE_RTS:      return IB_QPS_RTS;
4218         case MLX5_QP_STATE_SQ_DRAINING:
4219         case MLX5_QP_STATE_SQD:      return IB_QPS_SQD;
4220         case MLX5_QP_STATE_SQER:     return IB_QPS_SQE;
4221         case MLX5_QP_STATE_ERR:      return IB_QPS_ERR;
4222         default:                     return -1;
4223         }
4224 }
4225
4226 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4227 {
4228         switch (mlx5_mig_state) {
4229         case MLX5_QP_PM_ARMED:          return IB_MIG_ARMED;
4230         case MLX5_QP_PM_REARM:          return IB_MIG_REARM;
4231         case MLX5_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
4232         default: return -1;
4233         }
4234 }
4235
4236 static int to_ib_qp_access_flags(int mlx5_flags)
4237 {
4238         int ib_flags = 0;
4239
4240         if (mlx5_flags & MLX5_QP_BIT_RRE)
4241                 ib_flags |= IB_ACCESS_REMOTE_READ;
4242         if (mlx5_flags & MLX5_QP_BIT_RWE)
4243                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4244         if (mlx5_flags & MLX5_QP_BIT_RAE)
4245                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4246
4247         return ib_flags;
4248 }
4249
4250 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
4251                                 struct mlx5_qp_path *path)
4252 {
4253         struct mlx5_core_dev *dev = ibdev->mdev;
4254
4255         memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
4256         ib_ah_attr->port_num      = path->port;
4257
4258         if (ib_ah_attr->port_num == 0 ||
4259             ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports))
4260                 return;
4261
4262         ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf;
4263
4264         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
4265         ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
4266         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
4267         ib_ah_attr->ah_flags      = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
4268         if (ib_ah_attr->ah_flags) {
4269                 ib_ah_attr->grh.sgid_index = path->mgid_index;
4270                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
4271                 ib_ah_attr->grh.traffic_class =
4272                         (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
4273                 ib_ah_attr->grh.flow_label =
4274                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
4275                 memcpy(ib_ah_attr->grh.dgid.raw,
4276                        path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
4277         }
4278 }
4279
4280 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4281                                         struct mlx5_ib_sq *sq,
4282                                         u8 *sq_state)
4283 {
4284         void *out;
4285         void *sqc;
4286         int inlen;
4287         int err;
4288
4289         inlen = MLX5_ST_SZ_BYTES(query_sq_out);
4290         out = mlx5_vzalloc(inlen);
4291         if (!out)
4292                 return -ENOMEM;
4293
4294         err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4295         if (err)
4296                 goto out;
4297
4298         sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4299         *sq_state = MLX5_GET(sqc, sqc, state);
4300         sq->state = *sq_state;
4301
4302 out:
4303         kvfree(out);
4304         return err;
4305 }
4306
4307 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4308                                         struct mlx5_ib_rq *rq,
4309                                         u8 *rq_state)
4310 {
4311         void *out;
4312         void *rqc;
4313         int inlen;
4314         int err;
4315
4316         inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4317         out = mlx5_vzalloc(inlen);
4318         if (!out)
4319                 return -ENOMEM;
4320
4321         err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4322         if (err)
4323                 goto out;
4324
4325         rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4326         *rq_state = MLX5_GET(rqc, rqc, state);
4327         rq->state = *rq_state;
4328
4329 out:
4330         kvfree(out);
4331         return err;
4332 }
4333
4334 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4335                                   struct mlx5_ib_qp *qp, u8 *qp_state)
4336 {
4337         static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4338                 [MLX5_RQC_STATE_RST] = {
4339                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
4340                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
4341                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE_BAD,
4342                         [MLX5_SQ_STATE_NA]      = IB_QPS_RESET,
4343                 },
4344                 [MLX5_RQC_STATE_RDY] = {
4345                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
4346                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
4347                         [MLX5_SQC_STATE_ERR]    = IB_QPS_SQE,
4348                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE,
4349                 },
4350                 [MLX5_RQC_STATE_ERR] = {
4351                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
4352                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
4353                         [MLX5_SQC_STATE_ERR]    = IB_QPS_ERR,
4354                         [MLX5_SQ_STATE_NA]      = IB_QPS_ERR,
4355                 },
4356                 [MLX5_RQ_STATE_NA] = {
4357                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
4358                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
4359                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE,
4360                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE_BAD,
4361                 },
4362         };
4363
4364         *qp_state = sqrq_trans[rq_state][sq_state];
4365
4366         if (*qp_state == MLX5_QP_STATE_BAD) {
4367                 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4368                      qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4369                      qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4370                 return -EINVAL;
4371         }
4372
4373         if (*qp_state == MLX5_QP_STATE)
4374                 *qp_state = qp->state;
4375
4376         return 0;
4377 }
4378
4379 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4380                                      struct mlx5_ib_qp *qp,
4381                                      u8 *raw_packet_qp_state)
4382 {
4383         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4384         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4385         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4386         int err;
4387         u8 sq_state = MLX5_SQ_STATE_NA;
4388         u8 rq_state = MLX5_RQ_STATE_NA;
4389
4390         if (qp->sq.wqe_cnt) {
4391                 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4392                 if (err)
4393                         return err;
4394         }
4395
4396         if (qp->rq.wqe_cnt) {
4397                 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4398                 if (err)
4399                         return err;
4400         }
4401
4402         return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4403                                       raw_packet_qp_state);
4404 }
4405
4406 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4407                          struct ib_qp_attr *qp_attr)
4408 {
4409         int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
4410         struct mlx5_qp_context *context;
4411         int mlx5_state;
4412         u32 *outb;
4413         int err = 0;
4414
4415         outb = kzalloc(outlen, GFP_KERNEL);
4416         if (!outb)
4417                 return -ENOMEM;
4418
4419         err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
4420                                  outlen);
4421         if (err)
4422                 goto out;
4423
4424         /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4425         context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4426
4427         mlx5_state = be32_to_cpu(context->flags) >> 28;
4428
4429         qp->state                    = to_ib_qp_state(mlx5_state);
4430         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
4431         qp_attr->path_mig_state      =
4432                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4433         qp_attr->qkey                = be32_to_cpu(context->qkey);
4434         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4435         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
4436         qp_attr->dest_qp_num         = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4437         qp_attr->qp_access_flags     =
4438                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4439
4440         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4441                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4442                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
4443                 qp_attr->alt_pkey_index =
4444                         be16_to_cpu(context->alt_path.pkey_index);
4445                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
4446         }
4447
4448         qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
4449         qp_attr->port_num = context->pri_path.port;
4450
4451         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4452         qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4453
4454         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4455
4456         qp_attr->max_dest_rd_atomic =
4457                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4458         qp_attr->min_rnr_timer      =
4459                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4460         qp_attr->timeout            = context->pri_path.ackto_lt >> 3;
4461         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
4462         qp_attr->rnr_retry          = (be32_to_cpu(context->params1) >> 13) & 0x7;
4463         qp_attr->alt_timeout        = context->alt_path.ackto_lt >> 3;
4464
4465 out:
4466         kfree(outb);
4467         return err;
4468 }
4469
4470 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4471                      int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4472 {
4473         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4474         struct mlx5_ib_qp *qp = to_mqp(ibqp);
4475         int err = 0;
4476         u8 raw_packet_qp_state;
4477
4478         if (ibqp->rwq_ind_tbl)
4479                 return -ENOSYS;
4480
4481         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4482                 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4483                                             qp_init_attr);
4484
4485 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4486         /*
4487          * Wait for any outstanding page faults, in case the user frees memory
4488          * based upon this query's result.
4489          */
4490         flush_workqueue(mlx5_ib_page_fault_wq);
4491 #endif
4492
4493         mutex_lock(&qp->mutex);
4494
4495         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
4496                 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4497                 if (err)
4498                         goto out;
4499                 qp->state = raw_packet_qp_state;
4500                 qp_attr->port_num = 1;
4501         } else {
4502                 err = query_qp_attr(dev, qp, qp_attr);
4503                 if (err)
4504                         goto out;
4505         }
4506
4507         qp_attr->qp_state            = qp->state;
4508         qp_attr->cur_qp_state        = qp_attr->qp_state;
4509         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
4510         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
4511
4512         if (!ibqp->uobject) {
4513                 qp_attr->cap.max_send_wr  = qp->sq.max_post;
4514                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4515                 qp_init_attr->qp_context = ibqp->qp_context;
4516         } else {
4517                 qp_attr->cap.max_send_wr  = 0;
4518                 qp_attr->cap.max_send_sge = 0;
4519         }
4520
4521         qp_init_attr->qp_type = ibqp->qp_type;
4522         qp_init_attr->recv_cq = ibqp->recv_cq;
4523         qp_init_attr->send_cq = ibqp->send_cq;
4524         qp_init_attr->srq = ibqp->srq;
4525         qp_attr->cap.max_inline_data = qp->max_inline_data;
4526
4527         qp_init_attr->cap            = qp_attr->cap;
4528
4529         qp_init_attr->create_flags = 0;
4530         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4531                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4532
4533         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4534                 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4535         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4536                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4537         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4538                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
4539         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4540                 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
4541
4542         qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4543                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4544
4545 out:
4546         mutex_unlock(&qp->mutex);
4547         return err;
4548 }
4549
4550 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4551                                           struct ib_ucontext *context,
4552                                           struct ib_udata *udata)
4553 {
4554         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4555         struct mlx5_ib_xrcd *xrcd;
4556         int err;
4557
4558         if (!MLX5_CAP_GEN(dev->mdev, xrc))
4559                 return ERR_PTR(-ENOSYS);
4560
4561         xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4562         if (!xrcd)
4563                 return ERR_PTR(-ENOMEM);
4564
4565         err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
4566         if (err) {
4567                 kfree(xrcd);
4568                 return ERR_PTR(-ENOMEM);
4569         }
4570
4571         return &xrcd->ibxrcd;
4572 }
4573
4574 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
4575 {
4576         struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4577         u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4578         int err;
4579
4580         err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
4581         if (err) {
4582                 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4583                 return err;
4584         }
4585
4586         kfree(xrcd);
4587
4588         return 0;
4589 }
4590
4591 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
4592 {
4593         struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
4594         struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
4595         struct ib_event event;
4596
4597         if (rwq->ibwq.event_handler) {
4598                 event.device     = rwq->ibwq.device;
4599                 event.element.wq = &rwq->ibwq;
4600                 switch (type) {
4601                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
4602                         event.event = IB_EVENT_WQ_FATAL;
4603                         break;
4604                 default:
4605                         mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
4606                         return;
4607                 }
4608
4609                 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
4610         }
4611 }
4612
4613 static int  create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4614                       struct ib_wq_init_attr *init_attr)
4615 {
4616         struct mlx5_ib_dev *dev;
4617         __be64 *rq_pas0;
4618         void *in;
4619         void *rqc;
4620         void *wq;
4621         int inlen;
4622         int err;
4623
4624         dev = to_mdev(pd->device);
4625
4626         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
4627         in = mlx5_vzalloc(inlen);
4628         if (!in)
4629                 return -ENOMEM;
4630
4631         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4632         MLX5_SET(rqc,  rqc, mem_rq_type,
4633                  MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4634         MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4635         MLX5_SET(rqc,  rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4636         MLX5_SET(rqc,  rqc, state, MLX5_RQC_STATE_RST);
4637         MLX5_SET(rqc,  rqc, flush_in_error_en, 1);
4638         wq = MLX5_ADDR_OF(rqc, rqc, wq);
4639         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
4640         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4641         MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4642         MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4643         MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4644         MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4645         MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4646         MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4647         MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4648         rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4649         mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
4650         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
4651         kvfree(in);
4652         return err;
4653 }
4654
4655 static int set_user_rq_size(struct mlx5_ib_dev *dev,
4656                             struct ib_wq_init_attr *wq_init_attr,
4657                             struct mlx5_ib_create_wq *ucmd,
4658                             struct mlx5_ib_rwq *rwq)
4659 {
4660         /* Sanity check RQ size before proceeding */
4661         if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4662                 return -EINVAL;
4663
4664         if (!ucmd->rq_wqe_count)
4665                 return -EINVAL;
4666
4667         rwq->wqe_count = ucmd->rq_wqe_count;
4668         rwq->wqe_shift = ucmd->rq_wqe_shift;
4669         rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
4670         rwq->log_rq_stride = rwq->wqe_shift;
4671         rwq->log_rq_size = ilog2(rwq->wqe_count);
4672         return 0;
4673 }
4674
4675 static int prepare_user_rq(struct ib_pd *pd,
4676                            struct ib_wq_init_attr *init_attr,
4677                            struct ib_udata *udata,
4678                            struct mlx5_ib_rwq *rwq)
4679 {
4680         struct mlx5_ib_dev *dev = to_mdev(pd->device);
4681         struct mlx5_ib_create_wq ucmd = {};
4682         int err;
4683         size_t required_cmd_sz;
4684
4685         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4686         if (udata->inlen < required_cmd_sz) {
4687                 mlx5_ib_dbg(dev, "invalid inlen\n");
4688                 return -EINVAL;
4689         }
4690
4691         if (udata->inlen > sizeof(ucmd) &&
4692             !ib_is_udata_cleared(udata, sizeof(ucmd),
4693                                  udata->inlen - sizeof(ucmd))) {
4694                 mlx5_ib_dbg(dev, "inlen is not supported\n");
4695                 return -EOPNOTSUPP;
4696         }
4697
4698         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4699                 mlx5_ib_dbg(dev, "copy failed\n");
4700                 return -EFAULT;
4701         }
4702
4703         if (ucmd.comp_mask) {
4704                 mlx5_ib_dbg(dev, "invalid comp mask\n");
4705                 return -EOPNOTSUPP;
4706         }
4707
4708         if (ucmd.reserved) {
4709                 mlx5_ib_dbg(dev, "invalid reserved\n");
4710                 return -EOPNOTSUPP;
4711         }
4712
4713         err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4714         if (err) {
4715                 mlx5_ib_dbg(dev, "err %d\n", err);
4716                 return err;
4717         }
4718
4719         err = create_user_rq(dev, pd, rwq, &ucmd);
4720         if (err) {
4721                 mlx5_ib_dbg(dev, "err %d\n", err);
4722                 if (err)
4723                         return err;
4724         }
4725
4726         rwq->user_index = ucmd.user_index;
4727         return 0;
4728 }
4729
4730 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4731                                 struct ib_wq_init_attr *init_attr,
4732                                 struct ib_udata *udata)
4733 {
4734         struct mlx5_ib_dev *dev;
4735         struct mlx5_ib_rwq *rwq;
4736         struct mlx5_ib_create_wq_resp resp = {};
4737         size_t min_resp_len;
4738         int err;
4739
4740         if (!udata)
4741                 return ERR_PTR(-ENOSYS);
4742
4743         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4744         if (udata->outlen && udata->outlen < min_resp_len)
4745                 return ERR_PTR(-EINVAL);
4746
4747         dev = to_mdev(pd->device);
4748         switch (init_attr->wq_type) {
4749         case IB_WQT_RQ:
4750                 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
4751                 if (!rwq)
4752                         return ERR_PTR(-ENOMEM);
4753                 err = prepare_user_rq(pd, init_attr, udata, rwq);
4754                 if (err)
4755                         goto err;
4756                 err = create_rq(rwq, pd, init_attr);
4757                 if (err)
4758                         goto err_user_rq;
4759                 break;
4760         default:
4761                 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
4762                             init_attr->wq_type);
4763                 return ERR_PTR(-EINVAL);
4764         }
4765
4766         rwq->ibwq.wq_num = rwq->core_qp.qpn;
4767         rwq->ibwq.state = IB_WQS_RESET;
4768         if (udata->outlen) {
4769                 resp.response_length = offsetof(typeof(resp), response_length) +
4770                                 sizeof(resp.response_length);
4771                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4772                 if (err)
4773                         goto err_copy;
4774         }
4775
4776         rwq->core_qp.event = mlx5_ib_wq_event;
4777         rwq->ibwq.event_handler = init_attr->event_handler;
4778         return &rwq->ibwq;
4779
4780 err_copy:
4781         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4782 err_user_rq:
4783         destroy_user_rq(pd, rwq);
4784 err:
4785         kfree(rwq);
4786         return ERR_PTR(err);
4787 }
4788
4789 int mlx5_ib_destroy_wq(struct ib_wq *wq)
4790 {
4791         struct mlx5_ib_dev *dev = to_mdev(wq->device);
4792         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4793
4794         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4795         destroy_user_rq(wq->pd, rwq);
4796         kfree(rwq);
4797
4798         return 0;
4799 }
4800
4801 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
4802                                                       struct ib_rwq_ind_table_init_attr *init_attr,
4803                                                       struct ib_udata *udata)
4804 {
4805         struct mlx5_ib_dev *dev = to_mdev(device);
4806         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
4807         int sz = 1 << init_attr->log_ind_tbl_size;
4808         struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
4809         size_t min_resp_len;
4810         int inlen;
4811         int err;
4812         int i;
4813         u32 *in;
4814         void *rqtc;
4815
4816         if (udata->inlen > 0 &&
4817             !ib_is_udata_cleared(udata, 0,
4818                                  udata->inlen))
4819                 return ERR_PTR(-EOPNOTSUPP);
4820
4821         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4822         if (udata->outlen && udata->outlen < min_resp_len)
4823                 return ERR_PTR(-EINVAL);
4824
4825         rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
4826         if (!rwq_ind_tbl)
4827                 return ERR_PTR(-ENOMEM);
4828
4829         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
4830         in = mlx5_vzalloc(inlen);
4831         if (!in) {
4832                 err = -ENOMEM;
4833                 goto err;
4834         }
4835
4836         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
4837
4838         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
4839         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
4840
4841         for (i = 0; i < sz; i++)
4842                 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
4843
4844         err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
4845         kvfree(in);
4846
4847         if (err)
4848                 goto err;
4849
4850         rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
4851         if (udata->outlen) {
4852                 resp.response_length = offsetof(typeof(resp), response_length) +
4853                                         sizeof(resp.response_length);
4854                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4855                 if (err)
4856                         goto err_copy;
4857         }
4858
4859         return &rwq_ind_tbl->ib_rwq_ind_tbl;
4860
4861 err_copy:
4862         mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4863 err:
4864         kfree(rwq_ind_tbl);
4865         return ERR_PTR(err);
4866 }
4867
4868 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4869 {
4870         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
4871         struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
4872
4873         mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4874
4875         kfree(rwq_ind_tbl);
4876         return 0;
4877 }
4878
4879 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
4880                       u32 wq_attr_mask, struct ib_udata *udata)
4881 {
4882         struct mlx5_ib_dev *dev = to_mdev(wq->device);
4883         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4884         struct mlx5_ib_modify_wq ucmd = {};
4885         size_t required_cmd_sz;
4886         int curr_wq_state;
4887         int wq_state;
4888         int inlen;
4889         int err;
4890         void *rqc;
4891         void *in;
4892
4893         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4894         if (udata->inlen < required_cmd_sz)
4895                 return -EINVAL;
4896
4897         if (udata->inlen > sizeof(ucmd) &&
4898             !ib_is_udata_cleared(udata, sizeof(ucmd),
4899                                  udata->inlen - sizeof(ucmd)))
4900                 return -EOPNOTSUPP;
4901
4902         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4903                 return -EFAULT;
4904
4905         if (ucmd.comp_mask || ucmd.reserved)
4906                 return -EOPNOTSUPP;
4907
4908         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
4909         in = mlx5_vzalloc(inlen);
4910         if (!in)
4911                 return -ENOMEM;
4912
4913         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
4914
4915         curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
4916                 wq_attr->curr_wq_state : wq->state;
4917         wq_state = (wq_attr_mask & IB_WQ_STATE) ?
4918                 wq_attr->wq_state : curr_wq_state;
4919         if (curr_wq_state == IB_WQS_ERR)
4920                 curr_wq_state = MLX5_RQC_STATE_ERR;
4921         if (wq_state == IB_WQS_ERR)
4922                 wq_state = MLX5_RQC_STATE_ERR;
4923         MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
4924         MLX5_SET(rqc, rqc, state, wq_state);
4925
4926         err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
4927         kvfree(in);
4928         if (!err)
4929                 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
4930
4931         return err;
4932 }