drivers/infiniband/hw/mlx5/qp.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <rdma/ib_umem.h>
  35 #include <rdma/ib_cache.h>
  36 #include <rdma/ib_user_verbs.h>
  37 #include "mlx5_ib.h"
  38 #include "user.h"
  39
  40 /* not supported currently */
  41 static int wq_signature;
  42
  43 enum {
  44         MLX5_IB_ACK_REQ_FREQ    = 8,
  45 };
  46
  47 enum {
  48         MLX5_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  49         MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  50         MLX5_IB_LINK_TYPE_IB            = 0,
  51         MLX5_IB_LINK_TYPE_ETH           = 1
  52 };
  53
  54 enum {
  55         MLX5_IB_SQ_STRIDE       = 6,
  56         MLX5_IB_CACHE_LINE_SIZE = 64,
  57 };
  58
  59 static const u32 mlx5_ib_opcode[] = {
  60         [IB_WR_SEND]                            = MLX5_OPCODE_SEND,
  61         [IB_WR_LSO]                             = MLX5_OPCODE_LSO,
  62         [IB_WR_SEND_WITH_IMM]                   = MLX5_OPCODE_SEND_IMM,
  63         [IB_WR_RDMA_WRITE]                      = MLX5_OPCODE_RDMA_WRITE,
  64         [IB_WR_RDMA_WRITE_WITH_IMM]             = MLX5_OPCODE_RDMA_WRITE_IMM,
  65         [IB_WR_RDMA_READ]                       = MLX5_OPCODE_RDMA_READ,
  66         [IB_WR_ATOMIC_CMP_AND_SWP]              = MLX5_OPCODE_ATOMIC_CS,
  67         [IB_WR_ATOMIC_FETCH_AND_ADD]            = MLX5_OPCODE_ATOMIC_FA,
  68         [IB_WR_SEND_WITH_INV]                   = MLX5_OPCODE_SEND_INVAL,
  69         [IB_WR_LOCAL_INV]                       = MLX5_OPCODE_UMR,
  70         [IB_WR_REG_MR]                          = MLX5_OPCODE_UMR,
  71         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = MLX5_OPCODE_ATOMIC_MASKED_CS,
  72         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = MLX5_OPCODE_ATOMIC_MASKED_FA,
  73         [MLX5_IB_WR_UMR]                        = MLX5_OPCODE_UMR,
  74 };
  75
  76 struct mlx5_wqe_eth_pad {
  77         u8 rsvd0[16];
  78 };
  79
  80 static void get_cqs(enum ib_qp_type qp_type,
  81                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
  82                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
  83
  84 static int is_qp0(enum ib_qp_type qp_type)
  85 {
  86         return qp_type == IB_QPT_SMI;
  87 }
  88
  89 static int is_sqp(enum ib_qp_type qp_type)
  90 {
  91         return is_qp0(qp_type) || is_qp1(qp_type);
  92 }
  93
  94 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
  95 {
  96         return mlx5_buf_offset(&qp->buf, offset);
  97 }
  98
  99 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
 100 {
 101         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 102 }
 103
 104 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
 105 {
 106         return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
 107 }
 108
 109 /**
 110  * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
 111  *
 112  * @qp: QP to copy from.
 113  * @send: copy from the send queue when non-zero, use the receive queue
 114  *        otherwise.
 115  * @wqe_index:  index to start copying from. For send work queues, the
 116  *              wqe_index is in units of MLX5_SEND_WQE_BB.
 117  *              For receive work queue, it is the number of work queue
 118  *              element in the queue.
 119  * @buffer: destination buffer.
 120  * @length: maximum number of bytes to copy.
 121  *
 122  * Copies at least a single WQE, but may copy more data.
 123  *
 124  * Return: the number of bytes copied, or an error code.
 125  */
 126 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
 127                           void *buffer, u32 length,
 128                           struct mlx5_ib_qp_base *base)
 129 {
 130         struct ib_device *ibdev = qp->ibqp.device;
 131         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 132         struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
 133         size_t offset;
 134         size_t wq_end;
 135         struct ib_umem *umem = base->ubuffer.umem;
 136         u32 first_copy_length;
 137         int wqe_length;
 138         int ret;
 139
 140         if (wq->wqe_cnt == 0) {
 141                 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
 142                             qp->ibqp.qp_type);
 143                 return -EINVAL;
 144         }
 145
 146         offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
 147         wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
 148
 149         if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
 150                 return -EINVAL;
 151
 152         if (offset > umem->length ||
 153             (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
 154                 return -EINVAL;
 155
 156         first_copy_length = min_t(u32, offset + length, wq_end) - offset;
 157         ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
 158         if (ret)
 159                 return ret;
 160
 161         if (send) {
 162                 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
 163                 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 164
 165                 wqe_length = ds * MLX5_WQE_DS_UNITS;
 166         } else {
 167                 wqe_length = 1 << wq->wqe_shift;
 168         }
 169
 170         if (wqe_length <= first_copy_length)
 171                 return first_copy_length;
 172
 173         ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
 174                                 wqe_length - first_copy_length);
 175         if (ret)
 176                 return ret;
 177
 178         return wqe_length;
 179 }
 180
 181 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
 182 {
 183         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 184         struct ib_event event;
 185
 186         if (type == MLX5_EVENT_TYPE_PATH_MIG) {
 187                 /* This event is only valid for trans_qps */
 188                 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
 189         }
 190
 191         if (ibqp->event_handler) {
 192                 event.device     = ibqp->device;
 193                 event.element.qp = ibqp;
 194                 switch (type) {
 195                 case MLX5_EVENT_TYPE_PATH_MIG:
 196                         event.event = IB_EVENT_PATH_MIG;
 197                         break;
 198                 case MLX5_EVENT_TYPE_COMM_EST:
 199                         event.event = IB_EVENT_COMM_EST;
 200                         break;
 201                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 202                         event.event = IB_EVENT_SQ_DRAINED;
 203                         break;
 204                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 205                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 206                         break;
 207                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 208                         event.event = IB_EVENT_QP_FATAL;
 209                         break;
 210                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 211                         event.event = IB_EVENT_PATH_MIG_ERR;
 212                         break;
 213                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 214                         event.event = IB_EVENT_QP_REQ_ERR;
 215                         break;
 216                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 217                         event.event = IB_EVENT_QP_ACCESS_ERR;
 218                         break;
 219                 default:
 220                         pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
 221                         return;
 222                 }
 223
 224                 ibqp->event_handler(&event, ibqp->qp_context);
 225         }
 226 }
 227
 228 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
 229                        int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
 230 {
 231         int wqe_size;
 232         int wq_size;
 233
 234         /* Sanity check RQ size before proceeding */
 235         if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
 236                 return -EINVAL;
 237
 238         if (!has_rq) {
 239                 qp->rq.max_gs = 0;
 240                 qp->rq.wqe_cnt = 0;
 241                 qp->rq.wqe_shift = 0;
 242                 cap->max_recv_wr = 0;
 243                 cap->max_recv_sge = 0;
 244         } else {
 245                 if (ucmd) {
 246                         qp->rq.wqe_cnt = ucmd->rq_wqe_count;
 247                         qp->rq.wqe_shift = ucmd->rq_wqe_shift;
 248                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 249                         qp->rq.max_post = qp->rq.wqe_cnt;
 250                 } else {
 251                         wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
 252                         wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
 253                         wqe_size = roundup_pow_of_two(wqe_size);
 254                         wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
 255                         wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
 256                         qp->rq.wqe_cnt = wq_size / wqe_size;
 257                         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
 258                                 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
 259                                             wqe_size,
 260                                             MLX5_CAP_GEN(dev->mdev,
 261                                                          max_wqe_sz_rq));
 262                                 return -EINVAL;
 263                         }
 264                         qp->rq.wqe_shift = ilog2(wqe_size);
 265                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 266                         qp->rq.max_post = qp->rq.wqe_cnt;
 267                 }
 268         }
 269
 270         return 0;
 271 }
 272
 273 static int sq_overhead(struct ib_qp_init_attr *attr)
 274 {
 275         int size = 0;
 276
 277         switch (attr->qp_type) {
 278         case IB_QPT_XRC_INI:
 279                 size += sizeof(struct mlx5_wqe_xrc_seg);
 280                 /* fall through */
 281         case IB_QPT_RC:
 282                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 283                         max(sizeof(struct mlx5_wqe_atomic_seg) +
 284                             sizeof(struct mlx5_wqe_raddr_seg),
 285                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 286                             sizeof(struct mlx5_mkey_seg));
 287                 break;
 288
 289         case IB_QPT_XRC_TGT:
 290                 return 0;
 291
 292         case IB_QPT_UC:
 293                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 294                         max(sizeof(struct mlx5_wqe_raddr_seg),
 295                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 296                             sizeof(struct mlx5_mkey_seg));
 297                 break;
 298
 299         case IB_QPT_UD:
 300                 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 301                         size += sizeof(struct mlx5_wqe_eth_pad) +
 302                                 sizeof(struct mlx5_wqe_eth_seg);
 303                 /* fall through */
 304         case IB_QPT_SMI:
 305         case MLX5_IB_QPT_HW_GSI:
 306                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 307                         sizeof(struct mlx5_wqe_datagram_seg);
 308                 break;
 309
 310         case MLX5_IB_QPT_REG_UMR:
 311                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 312                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 313                         sizeof(struct mlx5_mkey_seg);
 314                 break;
 315
 316         default:
 317                 return -EINVAL;
 318         }
 319
 320         return size;
 321 }
 322
 323 static int calc_send_wqe(struct ib_qp_init_attr *attr)
 324 {
 325         int inl_size = 0;
 326         int size;
 327
 328         size = sq_overhead(attr);
 329         if (size < 0)
 330                 return size;
 331
 332         if (attr->cap.max_inline_data) {
 333                 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
 334                         attr->cap.max_inline_data;
 335         }
 336
 337         size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
 338         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
 339             ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
 340                         return MLX5_SIG_WQE_SIZE;
 341         else
 342                 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
 343 }
 344
 345 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
 346                         struct mlx5_ib_qp *qp)
 347 {
 348         int wqe_size;
 349         int wq_size;
 350
 351         if (!attr->cap.max_send_wr)
 352                 return 0;
 353
 354         wqe_size = calc_send_wqe(attr);
 355         mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
 356         if (wqe_size < 0)
 357                 return wqe_size;
 358
 359         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 360                 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
 361                             wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 362                 return -EINVAL;
 363         }
 364
 365         qp->max_inline_data = wqe_size - sq_overhead(attr) -
 366                               sizeof(struct mlx5_wqe_inline_seg);
 367         attr->cap.max_inline_data = qp->max_inline_data;
 368
 369         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
 370                 qp->signature_en = true;
 371
 372         wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
 373         qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
 374         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 375                 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n",
 376                             qp->sq.wqe_cnt,
 377                             1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 378                 return -ENOMEM;
 379         }
 380         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 381         qp->sq.max_gs = attr->cap.max_send_sge;
 382         qp->sq.max_post = wq_size / wqe_size;
 383         attr->cap.max_send_wr = qp->sq.max_post;
 384
 385         return wq_size;
 386 }
 387
 388 static int set_user_buf_size(struct mlx5_ib_dev *dev,
 389                             struct mlx5_ib_qp *qp,
 390                             struct mlx5_ib_create_qp *ucmd,
 391                             struct mlx5_ib_qp_base *base,
 392                             struct ib_qp_init_attr *attr)
 393 {
 394         int desc_sz = 1 << qp->sq.wqe_shift;
 395
 396         if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 397                 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
 398                              desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 399                 return -EINVAL;
 400         }
 401
 402         if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
 403                 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
 404                              ucmd->sq_wqe_count, ucmd->sq_wqe_count);
 405                 return -EINVAL;
 406         }
 407
 408         qp->sq.wqe_cnt = ucmd->sq_wqe_count;
 409
 410         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 411                 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
 412                              qp->sq.wqe_cnt,
 413                              1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 414                 return -EINVAL;
 415         }
 416
 417         if (attr->qp_type == IB_QPT_RAW_PACKET) {
 418                 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 419                 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
 420         } else {
 421                 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 422                                          (qp->sq.wqe_cnt << 6);
 423         }
 424
 425         return 0;
 426 }
 427
 428 static int qp_has_rq(struct ib_qp_init_attr *attr)
 429 {
 430         if (attr->qp_type == IB_QPT_XRC_INI ||
 431             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
 432             attr->qp_type == MLX5_IB_QPT_REG_UMR ||
 433             !attr->cap.max_recv_wr)
 434                 return 0;
 435
 436         return 1;
 437 }
 438
 439 static int first_med_uuar(void)
 440 {
 441         return 1;
 442 }
 443
 444 static int next_uuar(int n)
 445 {
 446         n++;
 447
 448         while (((n % 4) & 2))
 449                 n++;
 450
 451         return n;
 452 }
 453
 454 static int num_med_uuar(struct mlx5_uuar_info *uuari)
 455 {
 456         int n;
 457
 458         n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE -
 459                 uuari->num_low_latency_uuars - 1;
 460
 461         return n >= 0 ? n : 0;
 462 }
 463
 464 static int max_uuari(struct mlx5_uuar_info *uuari)
 465 {
 466         return uuari->num_uars * 4;
 467 }
 468
 469 static int first_hi_uuar(struct mlx5_uuar_info *uuari)
 470 {
 471         int med;
 472         int i;
 473         int t;
 474
 475         med = num_med_uuar(uuari);
 476         for (t = 0, i = first_med_uuar();; i = next_uuar(i)) {
 477                 t++;
 478                 if (t == med)
 479                         return next_uuar(i);
 480         }
 481
 482         return 0;
 483 }
 484
 485 static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari)
 486 {
 487         int i;
 488
 489         for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) {
 490                 if (!test_bit(i, uuari->bitmap)) {
 491                         set_bit(i, uuari->bitmap);
 492                         uuari->count[i]++;
 493                         return i;
 494                 }
 495         }
 496
 497         return -ENOMEM;
 498 }
 499
 500 static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari)
 501 {
 502         int minidx = first_med_uuar();
 503         int i;
 504
 505         for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) {
 506                 if (uuari->count[i] < uuari->count[minidx])
 507                         minidx = i;
 508         }
 509
 510         uuari->count[minidx]++;
 511         return minidx;
 512 }
 513
 514 static int alloc_uuar(struct mlx5_uuar_info *uuari,
 515                       enum mlx5_ib_latency_class lat)
 516 {
 517         int uuarn = -EINVAL;
 518
 519         mutex_lock(&uuari->lock);
 520         switch (lat) {
 521         case MLX5_IB_LATENCY_CLASS_LOW:
 522                 uuarn = 0;
 523                 uuari->count[uuarn]++;
 524                 break;
 525
 526         case MLX5_IB_LATENCY_CLASS_MEDIUM:
 527                 if (uuari->ver < 2)
 528                         uuarn = -ENOMEM;
 529                 else
 530                         uuarn = alloc_med_class_uuar(uuari);
 531                 break;
 532
 533         case MLX5_IB_LATENCY_CLASS_HIGH:
 534                 if (uuari->ver < 2)
 535                         uuarn = -ENOMEM;
 536                 else
 537                         uuarn = alloc_high_class_uuar(uuari);
 538                 break;
 539
 540         case MLX5_IB_LATENCY_CLASS_FAST_PATH:
 541                 uuarn = 2;
 542                 break;
 543         }
 544         mutex_unlock(&uuari->lock);
 545
 546         return uuarn;
 547 }
 548
 549 static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 550 {
 551         clear_bit(uuarn, uuari->bitmap);
 552         --uuari->count[uuarn];
 553 }
 554
 555 static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 556 {
 557         clear_bit(uuarn, uuari->bitmap);
 558         --uuari->count[uuarn];
 559 }
 560
 561 static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 562 {
 563         int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
 564         int high_uuar = nuuars - uuari->num_low_latency_uuars;
 565
 566         mutex_lock(&uuari->lock);
 567         if (uuarn == 0) {
 568                 --uuari->count[uuarn];
 569                 goto out;
 570         }
 571
 572         if (uuarn < high_uuar) {
 573                 free_med_class_uuar(uuari, uuarn);
 574                 goto out;
 575         }
 576
 577         free_high_class_uuar(uuari, uuarn);
 578
 579 out:
 580         mutex_unlock(&uuari->lock);
 581 }
 582
 583 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
 584 {
 585         switch (state) {
 586         case IB_QPS_RESET:      return MLX5_QP_STATE_RST;
 587         case IB_QPS_INIT:       return MLX5_QP_STATE_INIT;
 588         case IB_QPS_RTR:        return MLX5_QP_STATE_RTR;
 589         case IB_QPS_RTS:        return MLX5_QP_STATE_RTS;
 590         case IB_QPS_SQD:        return MLX5_QP_STATE_SQD;
 591         case IB_QPS_SQE:        return MLX5_QP_STATE_SQER;
 592         case IB_QPS_ERR:        return MLX5_QP_STATE_ERR;
 593         default:                return -1;
 594         }
 595 }
 596
 597 static int to_mlx5_st(enum ib_qp_type type)
 598 {
 599         switch (type) {
 600         case IB_QPT_RC:                 return MLX5_QP_ST_RC;
 601         case IB_QPT_UC:                 return MLX5_QP_ST_UC;
 602         case IB_QPT_UD:                 return MLX5_QP_ST_UD;
 603         case MLX5_IB_QPT_REG_UMR:       return MLX5_QP_ST_REG_UMR;
 604         case IB_QPT_XRC_INI:
 605         case IB_QPT_XRC_TGT:            return MLX5_QP_ST_XRC;
 606         case IB_QPT_SMI:                return MLX5_QP_ST_QP0;
 607         case MLX5_IB_QPT_HW_GSI:        return MLX5_QP_ST_QP1;
 608         case IB_QPT_RAW_IPV6:           return MLX5_QP_ST_RAW_IPV6;
 609         case IB_QPT_RAW_PACKET:
 610         case IB_QPT_RAW_ETHERTYPE:      return MLX5_QP_ST_RAW_ETHERTYPE;
 611         case IB_QPT_MAX:
 612         default:                return -EINVAL;
 613         }
 614 }
 615
 616 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
 617                              struct mlx5_ib_cq *recv_cq);
 618 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
 619                                struct mlx5_ib_cq *recv_cq);
 620
 621 static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn)
 622 {
 623         return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index;
 624 }
 625
 626 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
 627                             struct ib_pd *pd,
 628                             unsigned long addr, size_t size,
 629                             struct ib_umem **umem,
 630                             int *npages, int *page_shift, int *ncont,
 631                             u32 *offset)
 632 {
 633         int err;
 634
 635         *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
 636         if (IS_ERR(*umem)) {
 637                 mlx5_ib_dbg(dev, "umem_get failed\n");
 638                 return PTR_ERR(*umem);
 639         }
 640
 641         mlx5_ib_cont_pages(*umem, addr, npages, page_shift, ncont, NULL);
 642
 643         err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
 644         if (err) {
 645                 mlx5_ib_warn(dev, "bad offset\n");
 646                 goto err_umem;
 647         }
 648
 649         mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
 650                     addr, size, *npages, *page_shift, *ncont, *offset);
 651
 652         return 0;
 653
 654 err_umem:
 655         ib_umem_release(*umem);
 656         *umem = NULL;
 657
 658         return err;
 659 }
 660
 661 static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq)
 662 {
 663         struct mlx5_ib_ucontext *context;
 664
 665         context = to_mucontext(pd->uobject->context);
 666         mlx5_ib_db_unmap_user(context, &rwq->db);
 667         if (rwq->umem)
 668                 ib_umem_release(rwq->umem);
 669 }
 670
 671 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 672                           struct mlx5_ib_rwq *rwq,
 673                           struct mlx5_ib_create_wq *ucmd)
 674 {
 675         struct mlx5_ib_ucontext *context;
 676         int page_shift = 0;
 677         int npages;
 678         u32 offset = 0;
 679         int ncont = 0;
 680         int err;
 681
 682         if (!ucmd->buf_addr)
 683                 return -EINVAL;
 684
 685         context = to_mucontext(pd->uobject->context);
 686         rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
 687                                rwq->buf_size, 0, 0);
 688         if (IS_ERR(rwq->umem)) {
 689                 mlx5_ib_dbg(dev, "umem_get failed\n");
 690                 err = PTR_ERR(rwq->umem);
 691                 return err;
 692         }
 693
 694         mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, &npages, &page_shift,
 695                            &ncont, NULL);
 696         err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
 697                                      &rwq->rq_page_offset);
 698         if (err) {
 699                 mlx5_ib_warn(dev, "bad offset\n");
 700                 goto err_umem;
 701         }
 702
 703         rwq->rq_num_pas = ncont;
 704         rwq->page_shift = page_shift;
 705         rwq->log_page_size =  page_shift - MLX5_ADAPTER_PAGE_SHIFT;
 706         rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
 707
 708         mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
 709                     (unsigned long long)ucmd->buf_addr, rwq->buf_size,
 710                     npages, page_shift, ncont, offset);
 711
 712         err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
 713         if (err) {
 714                 mlx5_ib_dbg(dev, "map failed\n");
 715                 goto err_umem;
 716         }
 717
 718         rwq->create_type = MLX5_WQ_USER;
 719         return 0;
 720
 721 err_umem:
 722         ib_umem_release(rwq->umem);
 723         return err;
 724 }
 725
 726 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 727                           struct mlx5_ib_qp *qp, struct ib_udata *udata,
 728                           struct ib_qp_init_attr *attr,
 729                           struct mlx5_create_qp_mbox_in **in,
 730                           struct mlx5_ib_create_qp_resp *resp, int *inlen,
 731                           struct mlx5_ib_qp_base *base)
 732 {
 733         struct mlx5_ib_ucontext *context;
 734         struct mlx5_ib_create_qp ucmd;
 735         struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
 736         int page_shift = 0;
 737         int uar_index;
 738         int npages;
 739         u32 offset = 0;
 740         int uuarn;
 741         int ncont = 0;
 742         int err;
 743
 744         err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
 745         if (err) {
 746                 mlx5_ib_dbg(dev, "copy failed\n");
 747                 return err;
 748         }
 749
 750         context = to_mucontext(pd->uobject->context);
 751         /*
 752          * TBD: should come from the verbs when we have the API
 753          */
 754         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
 755                 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
 756                 uuarn = MLX5_CROSS_CHANNEL_UUAR;
 757         else {
 758                 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH);
 759                 if (uuarn < 0) {
 760                         mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n");
 761                         mlx5_ib_dbg(dev, "reverting to medium latency\n");
 762                         uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM);
 763                         if (uuarn < 0) {
 764                                 mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n");
 765                                 mlx5_ib_dbg(dev, "reverting to high latency\n");
 766                                 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW);
 767                                 if (uuarn < 0) {
 768                                         mlx5_ib_warn(dev, "uuar allocation failed\n");
 769                                         return uuarn;
 770                                 }
 771                         }
 772                 }
 773         }
 774
 775         uar_index = uuarn_to_uar_index(&context->uuari, uuarn);
 776         mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index);
 777
 778         qp->rq.offset = 0;
 779         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 780         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 781
 782         err = set_user_buf_size(dev, qp, &ucmd, base, attr);
 783         if (err)
 784                 goto err_uuar;
 785
 786         if (ucmd.buf_addr && ubuffer->buf_size) {
 787                 ubuffer->buf_addr = ucmd.buf_addr;
 788                 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
 789                                        ubuffer->buf_size,
 790                                        &ubuffer->umem, &npages, &page_shift,
 791                                        &ncont, &offset);
 792                 if (err)
 793                         goto err_uuar;
 794         } else {
 795                 ubuffer->umem = NULL;
 796         }
 797
 798         *inlen = sizeof(**in) + sizeof(*(*in)->pas) * ncont;
 799         *in = mlx5_vzalloc(*inlen);
 800         if (!*in) {
 801                 err = -ENOMEM;
 802                 goto err_umem;
 803         }
 804         if (ubuffer->umem)
 805                 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift,
 806                                      (*in)->pas, 0);
 807         (*in)->ctx.log_pg_sz_remote_qpn =
 808                 cpu_to_be32((page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
 809         (*in)->ctx.params2 = cpu_to_be32(offset << 6);
 810
 811         (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
 812         resp->uuar_index = uuarn;
 813         qp->uuarn = uuarn;
 814
 815         err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
 816         if (err) {
 817                 mlx5_ib_dbg(dev, "map failed\n");
 818                 goto err_free;
 819         }
 820
 821         err = ib_copy_to_udata(udata, resp, sizeof(*resp));
 822         if (err) {
 823                 mlx5_ib_dbg(dev, "copy failed\n");
 824                 goto err_unmap;
 825         }
 826         qp->create_type = MLX5_QP_USER;
 827
 828         return 0;
 829
 830 err_unmap:
 831         mlx5_ib_db_unmap_user(context, &qp->db);
 832
 833 err_free:
 834         kvfree(*in);
 835
 836 err_umem:
 837         if (ubuffer->umem)
 838                 ib_umem_release(ubuffer->umem);
 839
 840 err_uuar:
 841         free_uuar(&context->uuari, uuarn);
 842         return err;
 843 }
 844
 845 static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp,
 846                             struct mlx5_ib_qp_base *base)
 847 {
 848         struct mlx5_ib_ucontext *context;
 849
 850         context = to_mucontext(pd->uobject->context);
 851         mlx5_ib_db_unmap_user(context, &qp->db);
 852         if (base->ubuffer.umem)
 853                 ib_umem_release(base->ubuffer.umem);
 854         free_uuar(&context->uuari, qp->uuarn);
 855 }
 856
 857 static int create_kernel_qp(struct mlx5_ib_dev *dev,
 858                             struct ib_qp_init_attr *init_attr,
 859                             struct mlx5_ib_qp *qp,
 860                             struct mlx5_create_qp_mbox_in **in, int *inlen,
 861                             struct mlx5_ib_qp_base *base)
 862 {
 863         enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW;
 864         struct mlx5_uuar_info *uuari;
 865         int uar_index;
 866         int uuarn;
 867         int err;
 868
 869         uuari = &dev->mdev->priv.uuari;
 870         if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
 871                                         IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
 872                                         IB_QP_CREATE_IPOIB_UD_LSO |
 873                                         mlx5_ib_create_qp_sqpn_qp1()))
 874                 return -EINVAL;
 875
 876         if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
 877                 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH;
 878
 879         uuarn = alloc_uuar(uuari, lc);
 880         if (uuarn < 0) {
 881                 mlx5_ib_dbg(dev, "\n");
 882                 return -ENOMEM;
 883         }
 884
 885         qp->bf = &uuari->bfs[uuarn];
 886         uar_index = qp->bf->uar->index;
 887
 888         err = calc_sq_size(dev, init_attr, qp);
 889         if (err < 0) {
 890                 mlx5_ib_dbg(dev, "err %d\n", err);
 891                 goto err_uuar;
 892         }
 893
 894         qp->rq.offset = 0;
 895         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 896         base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
 897
 898         err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
 899         if (err) {
 900                 mlx5_ib_dbg(dev, "err %d\n", err);
 901                 goto err_uuar;
 902         }
 903
 904         qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
 905         *inlen = sizeof(**in) + sizeof(*(*in)->pas) * qp->buf.npages;
 906         *in = mlx5_vzalloc(*inlen);
 907         if (!*in) {
 908                 err = -ENOMEM;
 909                 goto err_buf;
 910         }
 911         (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
 912         (*in)->ctx.log_pg_sz_remote_qpn =
 913                 cpu_to_be32((qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
 914         /* Set "fast registration enabled" for all kernel QPs */
 915         (*in)->ctx.params1 |= cpu_to_be32(1 << 11);
 916         (*in)->ctx.sq_crq_size |= cpu_to_be16(1 << 4);
 917
 918         if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
 919                 (*in)->ctx.deth_sqpn = cpu_to_be32(1);
 920                 qp->flags |= MLX5_IB_QP_SQPN_QP1;
 921         }
 922
 923         mlx5_fill_page_array(&qp->buf, (*in)->pas);
 924
 925         err = mlx5_db_alloc(dev->mdev, &qp->db);
 926         if (err) {
 927                 mlx5_ib_dbg(dev, "err %d\n", err);
 928                 goto err_free;
 929         }
 930
 931         qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
 932         qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
 933         qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
 934         qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
 935         qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
 936
 937         if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
 938             !qp->sq.w_list || !qp->sq.wqe_head) {
 939                 err = -ENOMEM;
 940                 goto err_wrid;
 941         }
 942         qp->create_type = MLX5_QP_KERNEL;
 943
 944         return 0;
 945
 946 err_wrid:
 947         mlx5_db_free(dev->mdev, &qp->db);
 948         kfree(qp->sq.wqe_head);
 949         kfree(qp->sq.w_list);
 950         kfree(qp->sq.wrid);
 951         kfree(qp->sq.wr_data);
 952         kfree(qp->rq.wrid);
 953
 954 err_free:
 955         kvfree(*in);
 956
 957 err_buf:
 958         mlx5_buf_free(dev->mdev, &qp->buf);
 959
 960 err_uuar:
 961         free_uuar(&dev->mdev->priv.uuari, uuarn);
 962         return err;
 963 }
 964
 965 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
 966 {
 967         mlx5_db_free(dev->mdev, &qp->db);
 968         kfree(qp->sq.wqe_head);
 969         kfree(qp->sq.w_list);
 970         kfree(qp->sq.wrid);
 971         kfree(qp->sq.wr_data);
 972         kfree(qp->rq.wrid);
 973         mlx5_buf_free(dev->mdev, &qp->buf);
 974         free_uuar(&dev->mdev->priv.uuari, qp->bf->uuarn);
 975 }
 976
 977 static __be32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
 978 {
 979         if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
 980             (attr->qp_type == IB_QPT_XRC_INI))
 981                 return cpu_to_be32(MLX5_SRQ_RQ);
 982         else if (!qp->has_rq)
 983                 return cpu_to_be32(MLX5_ZERO_LEN_RQ);
 984         else
 985                 return cpu_to_be32(MLX5_NON_ZERO_RQ);
 986 }
 987
 988 static int is_connected(enum ib_qp_type qp_type)
 989 {
 990         if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
 991                 return 1;
 992
 993         return 0;
 994 }
 995
 996 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
 997                                     struct mlx5_ib_sq *sq, u32 tdn)
 998 {
 999         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1000         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1001
1002         memset(in, 0, sizeof(in));
1003
1004         MLX5_SET(tisc, tisc, transport_domain, tdn);
1005
1006         return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1007 }
1008
1009 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1010                                       struct mlx5_ib_sq *sq)
1011 {
1012         mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1013 }
1014
1015 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1016                                    struct mlx5_ib_sq *sq, void *qpin,
1017                                    struct ib_pd *pd)
1018 {
1019         struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1020         __be64 *pas;
1021         void *in;
1022         void *sqc;
1023         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1024         void *wq;
1025         int inlen;
1026         int err;
1027         int page_shift = 0;
1028         int npages;
1029         int ncont = 0;
1030         u32 offset = 0;
1031
1032         err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1033                                &sq->ubuffer.umem, &npages, &page_shift,
1034                                &ncont, &offset);
1035         if (err)
1036                 return err;
1037
1038         inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1039         in = mlx5_vzalloc(inlen);
1040         if (!in) {
1041                 err = -ENOMEM;
1042                 goto err_umem;
1043         }
1044
1045         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1046         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1047         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1048         MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1049         MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1050         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1051         MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1052
1053         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1054         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1055         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1056         MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1057         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1058         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1059         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1060         MLX5_SET(wq, wq, log_wq_pg_sz,  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1061         MLX5_SET(wq, wq, page_offset, offset);
1062
1063         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1064         mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1065
1066         err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1067
1068         kvfree(in);
1069
1070         if (err)
1071                 goto err_umem;
1072
1073         return 0;
1074
1075 err_umem:
1076         ib_umem_release(sq->ubuffer.umem);
1077         sq->ubuffer.umem = NULL;
1078
1079         return err;
1080 }
1081
1082 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1083                                      struct mlx5_ib_sq *sq)
1084 {
1085         mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1086         ib_umem_release(sq->ubuffer.umem);
1087 }
1088
1089 static int get_rq_pas_size(void *qpc)
1090 {
1091         u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1092         u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1093         u32 log_rq_size   = MLX5_GET(qpc, qpc, log_rq_size);
1094         u32 page_offset   = MLX5_GET(qpc, qpc, page_offset);
1095         u32 po_quanta     = 1 << (log_page_size - 6);
1096         u32 rq_sz         = 1 << (log_rq_size + 4 + log_rq_stride);
1097         u32 page_size     = 1 << log_page_size;
1098         u32 rq_sz_po      = rq_sz + (page_offset * po_quanta);
1099         u32 rq_num_pas    = (rq_sz_po + page_size - 1) / page_size;
1100
1101         return rq_num_pas * sizeof(u64);
1102 }
1103
1104 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1105                                    struct mlx5_ib_rq *rq, void *qpin)
1106 {
1107         struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1108         __be64 *pas;
1109         __be64 *qp_pas;
1110         void *in;
1111         void *rqc;
1112         void *wq;
1113         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1114         int inlen;
1115         int err;
1116         u32 rq_pas_size = get_rq_pas_size(qpc);
1117
1118         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1119         in = mlx5_vzalloc(inlen);
1120         if (!in)
1121                 return -ENOMEM;
1122
1123         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1124         MLX5_SET(rqc, rqc, vsd, 1);
1125         MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1126         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1127         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1128         MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1129         MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1130
1131         if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1132                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1133
1134         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1135         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1136         MLX5_SET(wq, wq, end_padding_mode,
1137                  MLX5_GET(qpc, qpc, end_padding_mode));
1138         MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1139         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1140         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1141         MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1142         MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1143         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1144
1145         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1146         qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1147         memcpy(pas, qp_pas, rq_pas_size);
1148
1149         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1150
1151         kvfree(in);
1152
1153         return err;
1154 }
1155
1156 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1157                                      struct mlx5_ib_rq *rq)
1158 {
1159         mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1160 }
1161
1162 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1163                                     struct mlx5_ib_rq *rq, u32 tdn)
1164 {
1165         u32 *in;
1166         void *tirc;
1167         int inlen;
1168         int err;
1169
1170         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1171         in = mlx5_vzalloc(inlen);
1172         if (!in)
1173                 return -ENOMEM;
1174
1175         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1176         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1177         MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1178         MLX5_SET(tirc, tirc, transport_domain, tdn);
1179
1180         err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1181
1182         kvfree(in);
1183
1184         return err;
1185 }
1186
1187 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1188                                       struct mlx5_ib_rq *rq)
1189 {
1190         mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1191 }
1192
1193 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1194                                 struct mlx5_create_qp_mbox_in *in,
1195                                 struct ib_pd *pd)
1196 {
1197         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1198         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1199         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1200         struct ib_uobject *uobj = pd->uobject;
1201         struct ib_ucontext *ucontext = uobj->context;
1202         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1203         int err;
1204         u32 tdn = mucontext->tdn;
1205
1206         if (qp->sq.wqe_cnt) {
1207                 err = create_raw_packet_qp_tis(dev, sq, tdn);
1208                 if (err)
1209                         return err;
1210
1211                 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1212                 if (err)
1213                         goto err_destroy_tis;
1214
1215                 sq->base.container_mibqp = qp;
1216         }
1217
1218         if (qp->rq.wqe_cnt) {
1219                 rq->base.container_mibqp = qp;
1220
1221                 err = create_raw_packet_qp_rq(dev, rq, in);
1222                 if (err)
1223                         goto err_destroy_sq;
1224
1225
1226                 err = create_raw_packet_qp_tir(dev, rq, tdn);
1227                 if (err)
1228                         goto err_destroy_rq;
1229         }
1230
1231         qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1232                                                      rq->base.mqp.qpn;
1233
1234         return 0;
1235
1236 err_destroy_rq:
1237         destroy_raw_packet_qp_rq(dev, rq);
1238 err_destroy_sq:
1239         if (!qp->sq.wqe_cnt)
1240                 return err;
1241         destroy_raw_packet_qp_sq(dev, sq);
1242 err_destroy_tis:
1243         destroy_raw_packet_qp_tis(dev, sq);
1244
1245         return err;
1246 }
1247
1248 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1249                                   struct mlx5_ib_qp *qp)
1250 {
1251         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1252         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1253         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1254
1255         if (qp->rq.wqe_cnt) {
1256                 destroy_raw_packet_qp_tir(dev, rq);
1257                 destroy_raw_packet_qp_rq(dev, rq);
1258         }
1259
1260         if (qp->sq.wqe_cnt) {
1261                 destroy_raw_packet_qp_sq(dev, sq);
1262                 destroy_raw_packet_qp_tis(dev, sq);
1263         }
1264 }
1265
1266 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1267                                     struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1268 {
1269         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1270         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1271
1272         sq->sq = &qp->sq;
1273         rq->rq = &qp->rq;
1274         sq->doorbell = &qp->db;
1275         rq->doorbell = &qp->db;
1276 }
1277
1278 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1279 {
1280         mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1281 }
1282
1283 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1284                                  struct ib_pd *pd,
1285                                  struct ib_qp_init_attr *init_attr,
1286                                  struct ib_udata *udata)
1287 {
1288         struct ib_uobject *uobj = pd->uobject;
1289         struct ib_ucontext *ucontext = uobj->context;
1290         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1291         struct mlx5_ib_create_qp_resp resp = {};
1292         int inlen;
1293         int err;
1294         u32 *in;
1295         void *tirc;
1296         void *hfso;
1297         u32 selected_fields = 0;
1298         size_t min_resp_len;
1299         u32 tdn = mucontext->tdn;
1300         struct mlx5_ib_create_qp_rss ucmd = {};
1301         size_t required_cmd_sz;
1302
1303         if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1304                 return -EOPNOTSUPP;
1305
1306         if (init_attr->create_flags || init_attr->send_cq)
1307                 return -EINVAL;
1308
1309         min_resp_len = offsetof(typeof(resp), uuar_index) + sizeof(resp.uuar_index);
1310         if (udata->outlen < min_resp_len)
1311                 return -EINVAL;
1312
1313         required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1);
1314         if (udata->inlen < required_cmd_sz) {
1315                 mlx5_ib_dbg(dev, "invalid inlen\n");
1316                 return -EINVAL;
1317         }
1318
1319         if (udata->inlen > sizeof(ucmd) &&
1320             !ib_is_udata_cleared(udata, sizeof(ucmd),
1321                                  udata->inlen - sizeof(ucmd))) {
1322                 mlx5_ib_dbg(dev, "inlen is not supported\n");
1323                 return -EOPNOTSUPP;
1324         }
1325
1326         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1327                 mlx5_ib_dbg(dev, "copy failed\n");
1328                 return -EFAULT;
1329         }
1330
1331         if (ucmd.comp_mask) {
1332                 mlx5_ib_dbg(dev, "invalid comp mask\n");
1333                 return -EOPNOTSUPP;
1334         }
1335
1336         if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) {
1337                 mlx5_ib_dbg(dev, "invalid reserved\n");
1338                 return -EOPNOTSUPP;
1339         }
1340
1341         err = ib_copy_to_udata(udata, &resp, min_resp_len);
1342         if (err) {
1343                 mlx5_ib_dbg(dev, "copy failed\n");
1344                 return -EINVAL;
1345         }
1346
1347         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1348         in = mlx5_vzalloc(inlen);
1349         if (!in)
1350                 return -ENOMEM;
1351
1352         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1353         MLX5_SET(tirc, tirc, disp_type,
1354                  MLX5_TIRC_DISP_TYPE_INDIRECT);
1355         MLX5_SET(tirc, tirc, indirect_table,
1356                  init_attr->rwq_ind_tbl->ind_tbl_num);
1357         MLX5_SET(tirc, tirc, transport_domain, tdn);
1358
1359         hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1360         switch (ucmd.rx_hash_function) {
1361         case MLX5_RX_HASH_FUNC_TOEPLITZ:
1362         {
1363                 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1364                 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1365
1366                 if (len != ucmd.rx_key_len) {
1367                         err = -EINVAL;
1368                         goto err;
1369                 }
1370
1371                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1372                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1373                 memcpy(rss_key, ucmd.rx_hash_key, len);
1374                 break;
1375         }
1376         default:
1377                 err = -EOPNOTSUPP;
1378                 goto err;
1379         }
1380
1381         if (!ucmd.rx_hash_fields_mask) {
1382                 /* special case when this TIR serves as steering entry without hashing */
1383                 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1384                         goto create_tir;
1385                 err = -EINVAL;
1386                 goto err;
1387         }
1388
1389         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1390              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1391              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1392              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1393                 err = -EINVAL;
1394                 goto err;
1395         }
1396
1397         /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1398         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1399             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1400                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1401                          MLX5_L3_PROT_TYPE_IPV4);
1402         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1403                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1404                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1405                          MLX5_L3_PROT_TYPE_IPV6);
1406
1407         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1408              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1409              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1410              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1411                 err = -EINVAL;
1412                 goto err;
1413         }
1414
1415         /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1416         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1417             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1418                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1419                          MLX5_L4_PROT_TYPE_TCP);
1420         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1421                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1422                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1423                          MLX5_L4_PROT_TYPE_UDP);
1424
1425         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1426             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1427                 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1428
1429         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1430             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1431                 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1432
1433         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1434             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1435                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1436
1437         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1438             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1439                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1440
1441         MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1442
1443 create_tir:
1444         err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1445
1446         if (err)
1447                 goto err;
1448
1449         kvfree(in);
1450         /* qpn is reserved for that QP */
1451         qp->trans_qp.base.mqp.qpn = 0;
1452         qp->flags |= MLX5_IB_QP_RSS;
1453         return 0;
1454
1455 err:
1456         kvfree(in);
1457         return err;
1458 }
1459
1460 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1461                             struct ib_qp_init_attr *init_attr,
1462                             struct ib_udata *udata, struct mlx5_ib_qp *qp)
1463 {
1464         struct mlx5_ib_resources *devr = &dev->devr;
1465         struct mlx5_core_dev *mdev = dev->mdev;
1466         struct mlx5_ib_qp_base *base;
1467         struct mlx5_ib_create_qp_resp resp;
1468         struct mlx5_create_qp_mbox_in *in;
1469         struct mlx5_ib_create_qp ucmd;
1470         struct mlx5_ib_cq *send_cq;
1471         struct mlx5_ib_cq *recv_cq;
1472         unsigned long flags;
1473         int inlen = sizeof(*in);
1474         int err;
1475         u32 uidx = MLX5_IB_DEFAULT_UIDX;
1476         void *qpc;
1477
1478         base = init_attr->qp_type == IB_QPT_RAW_PACKET ?
1479                &qp->raw_packet_qp.rq.base :
1480                &qp->trans_qp.base;
1481
1482         if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1483                 mlx5_ib_odp_create_qp(qp);
1484
1485         mutex_init(&qp->mutex);
1486         spin_lock_init(&qp->sq.lock);
1487         spin_lock_init(&qp->rq.lock);
1488
1489         if (init_attr->rwq_ind_tbl) {
1490                 if (!udata)
1491                         return -ENOSYS;
1492
1493                 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1494                 return err;
1495         }
1496
1497         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1498                 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1499                         mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1500                         return -EINVAL;
1501                 } else {
1502                         qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1503                 }
1504         }
1505
1506         if (init_attr->create_flags &
1507                         (IB_QP_CREATE_CROSS_CHANNEL |
1508                          IB_QP_CREATE_MANAGED_SEND |
1509                          IB_QP_CREATE_MANAGED_RECV)) {
1510                 if (!MLX5_CAP_GEN(mdev, cd)) {
1511                         mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1512                         return -EINVAL;
1513                 }
1514                 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1515                         qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1516                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1517                         qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1518                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1519                         qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1520         }
1521
1522         if (init_attr->qp_type == IB_QPT_UD &&
1523             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1524                 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1525                         mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1526                         return -EOPNOTSUPP;
1527                 }
1528
1529         if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1530                 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1531                         mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1532                         return -EOPNOTSUPP;
1533                 }
1534                 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1535                     !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1536                         mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1537                         return -EOPNOTSUPP;
1538                 }
1539                 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1540         }
1541
1542         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1543                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1544
1545         if (pd && pd->uobject) {
1546                 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1547                         mlx5_ib_dbg(dev, "copy failed\n");
1548                         return -EFAULT;
1549                 }
1550
1551                 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1552                                         &ucmd, udata->inlen, &uidx);
1553                 if (err)
1554                         return err;
1555
1556                 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1557                 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1558         } else {
1559                 qp->wq_sig = !!wq_signature;
1560         }
1561
1562         qp->has_rq = qp_has_rq(init_attr);
1563         err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1564                           qp, (pd && pd->uobject) ? &ucmd : NULL);
1565         if (err) {
1566                 mlx5_ib_dbg(dev, "err %d\n", err);
1567                 return err;
1568         }
1569
1570         if (pd) {
1571                 if (pd->uobject) {
1572                         __u32 max_wqes =
1573                                 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1574                         mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1575                         if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1576                             ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1577                                 mlx5_ib_dbg(dev, "invalid rq params\n");
1578                                 return -EINVAL;
1579                         }
1580                         if (ucmd.sq_wqe_count > max_wqes) {
1581                                 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1582                                             ucmd.sq_wqe_count, max_wqes);
1583                                 return -EINVAL;
1584                         }
1585                         if (init_attr->create_flags &
1586                             mlx5_ib_create_qp_sqpn_qp1()) {
1587                                 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1588                                 return -EINVAL;
1589                         }
1590                         err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1591                                              &resp, &inlen, base);
1592                         if (err)
1593                                 mlx5_ib_dbg(dev, "err %d\n", err);
1594                 } else {
1595                         err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1596                                                base);
1597                         if (err)
1598                                 mlx5_ib_dbg(dev, "err %d\n", err);
1599                 }
1600
1601                 if (err)
1602                         return err;
1603         } else {
1604                 in = mlx5_vzalloc(sizeof(*in));
1605                 if (!in)
1606                         return -ENOMEM;
1607
1608                 qp->create_type = MLX5_QP_EMPTY;
1609         }
1610
1611         if (is_sqp(init_attr->qp_type))
1612                 qp->port = init_attr->port_num;
1613
1614         in->ctx.flags = cpu_to_be32(to_mlx5_st(init_attr->qp_type) << 16 |
1615                                     MLX5_QP_PM_MIGRATED << 11);
1616
1617         if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1618                 in->ctx.flags_pd = cpu_to_be32(to_mpd(pd ? pd : devr->p0)->pdn);
1619         else
1620                 in->ctx.flags_pd = cpu_to_be32(MLX5_QP_LAT_SENSITIVE);
1621
1622         if (qp->wq_sig)
1623                 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_ENABLE_SIG);
1624
1625         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1626                 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_BLOCK_MCAST);
1627
1628         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1629                 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_MASTER);
1630         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1631                 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_SLAVE_SEND);
1632         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1633                 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_SLAVE_RECV);
1634
1635         if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1636                 int rcqe_sz;
1637                 int scqe_sz;
1638
1639                 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1640                 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1641
1642                 if (rcqe_sz == 128)
1643                         in->ctx.cs_res = MLX5_RES_SCAT_DATA64_CQE;
1644                 else
1645                         in->ctx.cs_res = MLX5_RES_SCAT_DATA32_CQE;
1646
1647                 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1648                         if (scqe_sz == 128)
1649                                 in->ctx.cs_req = MLX5_REQ_SCAT_DATA64_CQE;
1650                         else
1651                                 in->ctx.cs_req = MLX5_REQ_SCAT_DATA32_CQE;
1652                 }
1653         }
1654
1655         if (qp->rq.wqe_cnt) {
1656                 in->ctx.rq_size_stride = (qp->rq.wqe_shift - 4);
1657                 in->ctx.rq_size_stride |= ilog2(qp->rq.wqe_cnt) << 3;
1658         }
1659
1660         in->ctx.rq_type_srqn = get_rx_type(qp, init_attr);
1661
1662         if (qp->sq.wqe_cnt)
1663                 in->ctx.sq_crq_size |= cpu_to_be16(ilog2(qp->sq.wqe_cnt) << 11);
1664         else
1665                 in->ctx.sq_crq_size |= cpu_to_be16(0x8000);
1666
1667         /* Set default resources */
1668         switch (init_attr->qp_type) {
1669         case IB_QPT_XRC_TGT:
1670                 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
1671                 in->ctx.cqn_send = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
1672                 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
1673                 in->ctx.xrcd = cpu_to_be32(to_mxrcd(init_attr->xrcd)->xrcdn);
1674                 break;
1675         case IB_QPT_XRC_INI:
1676                 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
1677                 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
1678                 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
1679                 break;
1680         default:
1681                 if (init_attr->srq) {
1682                         in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x0)->xrcdn);
1683                         in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(init_attr->srq)->msrq.srqn);
1684                 } else {
1685                         in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
1686                         in->ctx.rq_type_srqn |=
1687                                 cpu_to_be32(to_msrq(devr->s1)->msrq.srqn);
1688                 }
1689         }
1690
1691         if (init_attr->send_cq)
1692                 in->ctx.cqn_send = cpu_to_be32(to_mcq(init_attr->send_cq)->mcq.cqn);
1693
1694         if (init_attr->recv_cq)
1695                 in->ctx.cqn_recv = cpu_to_be32(to_mcq(init_attr->recv_cq)->mcq.cqn);
1696
1697         in->ctx.db_rec_addr = cpu_to_be64(qp->db.dma);
1698
1699         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) {
1700                 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1701                 /* 0xffffff means we ask to work with cqe version 0 */
1702                 MLX5_SET(qpc, qpc, user_index, uidx);
1703         }
1704         /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1705         if (init_attr->qp_type == IB_QPT_UD &&
1706             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1707                 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1708                 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1709                 qp->flags |= MLX5_IB_QP_LSO;
1710         }
1711
1712         if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1713                 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1714                 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1715                 err = create_raw_packet_qp(dev, qp, in, pd);
1716         } else {
1717                 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1718         }
1719
1720         if (err) {
1721                 mlx5_ib_dbg(dev, "create qp failed\n");
1722                 goto err_create;
1723         }
1724
1725         kvfree(in);
1726
1727         base->container_mibqp = qp;
1728         base->mqp.event = mlx5_ib_qp_event;
1729
1730         get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1731                 &send_cq, &recv_cq);
1732         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1733         mlx5_ib_lock_cqs(send_cq, recv_cq);
1734         /* Maintain device to QPs access, needed for further handling via reset
1735          * flow
1736          */
1737         list_add_tail(&qp->qps_list, &dev->qp_list);
1738         /* Maintain CQ to QPs access, needed for further handling via reset flow
1739          */
1740         if (send_cq)
1741                 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1742         if (recv_cq)
1743                 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1744         mlx5_ib_unlock_cqs(send_cq, recv_cq);
1745         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1746
1747         return 0;
1748
1749 err_create:
1750         if (qp->create_type == MLX5_QP_USER)
1751                 destroy_qp_user(pd, qp, base);
1752         else if (qp->create_type == MLX5_QP_KERNEL)
1753                 destroy_qp_kernel(dev, qp);
1754
1755         kvfree(in);
1756         return err;
1757 }
1758
1759 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1760         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1761 {
1762         if (send_cq) {
1763                 if (recv_cq) {
1764                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1765                                 spin_lock(&send_cq->lock);
1766                                 spin_lock_nested(&recv_cq->lock,
1767                                                  SINGLE_DEPTH_NESTING);
1768                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1769                                 spin_lock(&send_cq->lock);
1770                                 __acquire(&recv_cq->lock);
1771                         } else {
1772                                 spin_lock(&recv_cq->lock);
1773                                 spin_lock_nested(&send_cq->lock,
1774                                                  SINGLE_DEPTH_NESTING);
1775                         }
1776                 } else {
1777                         spin_lock(&send_cq->lock);
1778                         __acquire(&recv_cq->lock);
1779                 }
1780         } else if (recv_cq) {
1781                 spin_lock(&recv_cq->lock);
1782                 __acquire(&send_cq->lock);
1783         } else {
1784                 __acquire(&send_cq->lock);
1785                 __acquire(&recv_cq->lock);
1786         }
1787 }
1788
1789 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1790         __releases(&send_cq->lock) __releases(&recv_cq->lock)
1791 {
1792         if (send_cq) {
1793                 if (recv_cq) {
1794                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1795                                 spin_unlock(&recv_cq->lock);
1796                                 spin_unlock(&send_cq->lock);
1797                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1798                                 __release(&recv_cq->lock);
1799                                 spin_unlock(&send_cq->lock);
1800                         } else {
1801                                 spin_unlock(&send_cq->lock);
1802                                 spin_unlock(&recv_cq->lock);
1803                         }
1804                 } else {
1805                         __release(&recv_cq->lock);
1806                         spin_unlock(&send_cq->lock);
1807                 }
1808         } else if (recv_cq) {
1809                 __release(&send_cq->lock);
1810                 spin_unlock(&recv_cq->lock);
1811         } else {
1812                 __release(&recv_cq->lock);
1813                 __release(&send_cq->lock);
1814         }
1815 }
1816
1817 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1818 {
1819         return to_mpd(qp->ibqp.pd);
1820 }
1821
1822 static void get_cqs(enum ib_qp_type qp_type,
1823                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
1824                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1825 {
1826         switch (qp_type) {
1827         case IB_QPT_XRC_TGT:
1828                 *send_cq = NULL;
1829                 *recv_cq = NULL;
1830                 break;
1831         case MLX5_IB_QPT_REG_UMR:
1832         case IB_QPT_XRC_INI:
1833                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1834                 *recv_cq = NULL;
1835                 break;
1836
1837         case IB_QPT_SMI:
1838         case MLX5_IB_QPT_HW_GSI:
1839         case IB_QPT_RC:
1840         case IB_QPT_UC:
1841         case IB_QPT_UD:
1842         case IB_QPT_RAW_IPV6:
1843         case IB_QPT_RAW_ETHERTYPE:
1844         case IB_QPT_RAW_PACKET:
1845                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1846                 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
1847                 break;
1848
1849         case IB_QPT_MAX:
1850         default:
1851                 *send_cq = NULL;
1852                 *recv_cq = NULL;
1853                 break;
1854         }
1855 }
1856
1857 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1858                                 u16 operation);
1859
1860 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1861 {
1862         struct mlx5_ib_cq *send_cq, *recv_cq;
1863         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
1864         struct mlx5_modify_qp_mbox_in *in;
1865         unsigned long flags;
1866         int err;
1867
1868         if (qp->ibqp.rwq_ind_tbl) {
1869                 destroy_rss_raw_qp_tir(dev, qp);
1870                 return;
1871         }
1872
1873         base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ?
1874                &qp->raw_packet_qp.rq.base :
1875                &qp->trans_qp.base;
1876
1877         in = kzalloc(sizeof(*in), GFP_KERNEL);
1878         if (!in)
1879                 return;
1880
1881         if (qp->state != IB_QPS_RESET) {
1882                 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) {
1883                         mlx5_ib_qp_disable_pagefaults(qp);
1884                         err = mlx5_core_qp_modify(dev->mdev,
1885                                                   MLX5_CMD_OP_2RST_QP, in, 0,
1886                                                   &base->mqp);
1887                 } else {
1888                         err = modify_raw_packet_qp(dev, qp,
1889                                                    MLX5_CMD_OP_2RST_QP);
1890                 }
1891                 if (err)
1892                         mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
1893                                      base->mqp.qpn);
1894         }
1895
1896         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
1897                 &send_cq, &recv_cq);
1898
1899         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1900         mlx5_ib_lock_cqs(send_cq, recv_cq);
1901         /* del from lists under both locks above to protect reset flow paths */
1902         list_del(&qp->qps_list);
1903         if (send_cq)
1904                 list_del(&qp->cq_send_list);
1905
1906         if (recv_cq)
1907                 list_del(&qp->cq_recv_list);
1908
1909         if (qp->create_type == MLX5_QP_KERNEL) {
1910                 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
1911                                    qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1912                 if (send_cq != recv_cq)
1913                         __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
1914                                            NULL);
1915         }
1916         mlx5_ib_unlock_cqs(send_cq, recv_cq);
1917         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1918
1919         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1920                 destroy_raw_packet_qp(dev, qp);
1921         } else {
1922                 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
1923                 if (err)
1924                         mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
1925                                      base->mqp.qpn);
1926         }
1927
1928         kfree(in);
1929
1930         if (qp->create_type == MLX5_QP_KERNEL)
1931                 destroy_qp_kernel(dev, qp);
1932         else if (qp->create_type == MLX5_QP_USER)
1933                 destroy_qp_user(&get_pd(qp)->ibpd, qp, base);
1934 }
1935
1936 static const char *ib_qp_type_str(enum ib_qp_type type)
1937 {
1938         switch (type) {
1939         case IB_QPT_SMI:
1940                 return "IB_QPT_SMI";
1941         case IB_QPT_GSI:
1942                 return "IB_QPT_GSI";
1943         case IB_QPT_RC:
1944                 return "IB_QPT_RC";
1945         case IB_QPT_UC:
1946                 return "IB_QPT_UC";
1947         case IB_QPT_UD:
1948                 return "IB_QPT_UD";
1949         case IB_QPT_RAW_IPV6:
1950                 return "IB_QPT_RAW_IPV6";
1951         case IB_QPT_RAW_ETHERTYPE:
1952                 return "IB_QPT_RAW_ETHERTYPE";
1953         case IB_QPT_XRC_INI:
1954                 return "IB_QPT_XRC_INI";
1955         case IB_QPT_XRC_TGT:
1956                 return "IB_QPT_XRC_TGT";
1957         case IB_QPT_RAW_PACKET:
1958                 return "IB_QPT_RAW_PACKET";
1959         case MLX5_IB_QPT_REG_UMR:
1960                 return "MLX5_IB_QPT_REG_UMR";
1961         case IB_QPT_MAX:
1962         default:
1963                 return "Invalid QP type";
1964         }
1965 }
1966
1967 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1968                                 struct ib_qp_init_attr *init_attr,
1969                                 struct ib_udata *udata)
1970 {
1971         struct mlx5_ib_dev *dev;
1972         struct mlx5_ib_qp *qp;
1973         u16 xrcdn = 0;
1974         int err;
1975
1976         if (pd) {
1977                 dev = to_mdev(pd->device);
1978
1979                 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1980                         if (!pd->uobject) {
1981                                 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
1982                                 return ERR_PTR(-EINVAL);
1983                         } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
1984                                 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
1985                                 return ERR_PTR(-EINVAL);
1986                         }
1987                 }
1988         } else {
1989                 /* being cautious here */
1990                 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
1991                     init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
1992                         pr_warn("%s: no PD for transport %s\n", __func__,
1993                                 ib_qp_type_str(init_attr->qp_type));
1994                         return ERR_PTR(-EINVAL);
1995                 }
1996                 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
1997         }
1998
1999         switch (init_attr->qp_type) {
2000         case IB_QPT_XRC_TGT:
2001         case IB_QPT_XRC_INI:
2002                 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2003                         mlx5_ib_dbg(dev, "XRC not supported\n");
2004                         return ERR_PTR(-ENOSYS);
2005                 }
2006                 init_attr->recv_cq = NULL;
2007                 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2008                         xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2009                         init_attr->send_cq = NULL;
2010                 }
2011
2012                 /* fall through */
2013         case IB_QPT_RAW_PACKET:
2014         case IB_QPT_RC:
2015         case IB_QPT_UC:
2016         case IB_QPT_UD:
2017         case IB_QPT_SMI:
2018         case MLX5_IB_QPT_HW_GSI:
2019         case MLX5_IB_QPT_REG_UMR:
2020                 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2021                 if (!qp)
2022                         return ERR_PTR(-ENOMEM);
2023
2024                 err = create_qp_common(dev, pd, init_attr, udata, qp);
2025                 if (err) {
2026                         mlx5_ib_dbg(dev, "create_qp_common failed\n");
2027                         kfree(qp);
2028                         return ERR_PTR(err);
2029                 }
2030
2031                 if (is_qp0(init_attr->qp_type))
2032                         qp->ibqp.qp_num = 0;
2033                 else if (is_qp1(init_attr->qp_type))
2034                         qp->ibqp.qp_num = 1;
2035                 else
2036                         qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2037
2038                 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2039                             qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2040                             to_mcq(init_attr->recv_cq)->mcq.cqn,
2041                             to_mcq(init_attr->send_cq)->mcq.cqn);
2042
2043                 qp->trans_qp.xrcdn = xrcdn;
2044
2045                 break;
2046
2047         case IB_QPT_GSI:
2048                 return mlx5_ib_gsi_create_qp(pd, init_attr);
2049
2050         case IB_QPT_RAW_IPV6:
2051         case IB_QPT_RAW_ETHERTYPE:
2052         case IB_QPT_MAX:
2053         default:
2054                 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2055                             init_attr->qp_type);
2056                 /* Don't support raw QPs */
2057                 return ERR_PTR(-EINVAL);
2058         }
2059
2060         return &qp->ibqp;
2061 }
2062
2063 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2064 {
2065         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2066         struct mlx5_ib_qp *mqp = to_mqp(qp);
2067
2068         if (unlikely(qp->qp_type == IB_QPT_GSI))
2069                 return mlx5_ib_gsi_destroy_qp(qp);
2070
2071         destroy_qp_common(dev, mqp);
2072
2073         kfree(mqp);
2074
2075         return 0;
2076 }
2077
2078 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2079                                    int attr_mask)
2080 {
2081         u32 hw_access_flags = 0;
2082         u8 dest_rd_atomic;
2083         u32 access_flags;
2084
2085         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2086                 dest_rd_atomic = attr->max_dest_rd_atomic;
2087         else
2088                 dest_rd_atomic = qp->trans_qp.resp_depth;
2089
2090         if (attr_mask & IB_QP_ACCESS_FLAGS)
2091                 access_flags = attr->qp_access_flags;
2092         else
2093                 access_flags = qp->trans_qp.atomic_rd_en;
2094
2095         if (!dest_rd_atomic)
2096                 access_flags &= IB_ACCESS_REMOTE_WRITE;
2097
2098         if (access_flags & IB_ACCESS_REMOTE_READ)
2099                 hw_access_flags |= MLX5_QP_BIT_RRE;
2100         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2101                 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2102         if (access_flags & IB_ACCESS_REMOTE_WRITE)
2103                 hw_access_flags |= MLX5_QP_BIT_RWE;
2104
2105         return cpu_to_be32(hw_access_flags);
2106 }
2107
2108 enum {
2109         MLX5_PATH_FLAG_FL       = 1 << 0,
2110         MLX5_PATH_FLAG_FREE_AR  = 1 << 1,
2111         MLX5_PATH_FLAG_COUNTER  = 1 << 2,
2112 };
2113
2114 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2115 {
2116         if (rate == IB_RATE_PORT_CURRENT) {
2117                 return 0;
2118         } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
2119                 return -EINVAL;
2120         } else {
2121                 while (rate != IB_RATE_2_5_GBPS &&
2122                        !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2123                          MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2124                         --rate;
2125         }
2126
2127         return rate + MLX5_STAT_RATE_OFFSET;
2128 }
2129
2130 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2131                                       struct mlx5_ib_sq *sq, u8 sl)
2132 {
2133         void *in;
2134         void *tisc;
2135         int inlen;
2136         int err;
2137
2138         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2139         in = mlx5_vzalloc(inlen);
2140         if (!in)
2141                 return -ENOMEM;
2142
2143         MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2144
2145         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2146         MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2147
2148         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2149
2150         kvfree(in);
2151
2152         return err;
2153 }
2154
2155 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2156                          const struct ib_ah_attr *ah,
2157                          struct mlx5_qp_path *path, u8 port, int attr_mask,
2158                          u32 path_flags, const struct ib_qp_attr *attr,
2159                          bool alt)
2160 {
2161         enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2162         int err;
2163
2164         if (attr_mask & IB_QP_PKEY_INDEX)
2165                 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2166                                                      attr->pkey_index);
2167
2168         if (ah->ah_flags & IB_AH_GRH) {
2169                 if (ah->grh.sgid_index >=
2170                     dev->mdev->port_caps[port - 1].gid_table_len) {
2171                         pr_err("sgid_index (%u) too large. max is %d\n",
2172                                ah->grh.sgid_index,
2173                                dev->mdev->port_caps[port - 1].gid_table_len);
2174                         return -EINVAL;
2175                 }
2176         }
2177
2178         if (ll == IB_LINK_LAYER_ETHERNET) {
2179                 if (!(ah->ah_flags & IB_AH_GRH))
2180                         return -EINVAL;
2181                 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac));
2182                 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2183                                                           ah->grh.sgid_index);
2184                 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4;
2185         } else {
2186                 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2187                 path->fl_free_ar |=
2188                         (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2189                 path->rlid = cpu_to_be16(ah->dlid);
2190                 path->grh_mlid = ah->src_path_bits & 0x7f;
2191                 if (ah->ah_flags & IB_AH_GRH)
2192                         path->grh_mlid  |= 1 << 7;
2193                 path->dci_cfi_prio_sl = ah->sl & 0xf;
2194         }
2195
2196         if (ah->ah_flags & IB_AH_GRH) {
2197                 path->mgid_index = ah->grh.sgid_index;
2198                 path->hop_limit  = ah->grh.hop_limit;
2199                 path->tclass_flowlabel =
2200                         cpu_to_be32((ah->grh.traffic_class << 20) |
2201                                     (ah->grh.flow_label));
2202                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
2203         }
2204
2205         err = ib_rate_to_mlx5(dev, ah->static_rate);
2206         if (err < 0)
2207                 return err;
2208         path->static_rate = err;
2209         path->port = port;
2210
2211         if (attr_mask & IB_QP_TIMEOUT)
2212                 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2213
2214         if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2215                 return modify_raw_packet_eth_prio(dev->mdev,
2216                                                   &qp->raw_packet_qp.sq,
2217                                                   ah->sl & 0xf);
2218
2219         return 0;
2220 }
2221
2222 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2223         [MLX5_QP_STATE_INIT] = {
2224                 [MLX5_QP_STATE_INIT] = {
2225                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2226                                           MLX5_QP_OPTPAR_RAE            |
2227                                           MLX5_QP_OPTPAR_RWE            |
2228                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2229                                           MLX5_QP_OPTPAR_PRI_PORT,
2230                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2231                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2232                                           MLX5_QP_OPTPAR_PRI_PORT,
2233                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2234                                           MLX5_QP_OPTPAR_Q_KEY          |
2235                                           MLX5_QP_OPTPAR_PRI_PORT,
2236                 },
2237                 [MLX5_QP_STATE_RTR] = {
2238                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2239                                           MLX5_QP_OPTPAR_RRE            |
2240                                           MLX5_QP_OPTPAR_RAE            |
2241                                           MLX5_QP_OPTPAR_RWE            |
2242                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2243                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2244                                           MLX5_QP_OPTPAR_RWE            |
2245                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2246                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2247                                           MLX5_QP_OPTPAR_Q_KEY,
2248                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX    |
2249                                            MLX5_QP_OPTPAR_Q_KEY,
2250                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2251                                           MLX5_QP_OPTPAR_RRE            |
2252                                           MLX5_QP_OPTPAR_RAE            |
2253                                           MLX5_QP_OPTPAR_RWE            |
2254                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2255                 },
2256         },
2257         [MLX5_QP_STATE_RTR] = {
2258                 [MLX5_QP_STATE_RTS] = {
2259                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2260                                           MLX5_QP_OPTPAR_RRE            |
2261                                           MLX5_QP_OPTPAR_RAE            |
2262                                           MLX5_QP_OPTPAR_RWE            |
2263                                           MLX5_QP_OPTPAR_PM_STATE       |
2264                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
2265                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2266                                           MLX5_QP_OPTPAR_RWE            |
2267                                           MLX5_QP_OPTPAR_PM_STATE,
2268                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2269                 },
2270         },
2271         [MLX5_QP_STATE_RTS] = {
2272                 [MLX5_QP_STATE_RTS] = {
2273                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2274                                           MLX5_QP_OPTPAR_RAE            |
2275                                           MLX5_QP_OPTPAR_RWE            |
2276                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
2277                                           MLX5_QP_OPTPAR_PM_STATE       |
2278                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2279                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2280                                           MLX5_QP_OPTPAR_PM_STATE       |
2281                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2282                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY          |
2283                                           MLX5_QP_OPTPAR_SRQN           |
2284                                           MLX5_QP_OPTPAR_CQN_RCV,
2285                 },
2286         },
2287         [MLX5_QP_STATE_SQER] = {
2288                 [MLX5_QP_STATE_RTS] = {
2289                         [MLX5_QP_ST_UD]  = MLX5_QP_OPTPAR_Q_KEY,
2290                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2291                         [MLX5_QP_ST_UC]  = MLX5_QP_OPTPAR_RWE,
2292                         [MLX5_QP_ST_RC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT   |
2293                                            MLX5_QP_OPTPAR_RWE           |
2294                                            MLX5_QP_OPTPAR_RAE           |
2295                                            MLX5_QP_OPTPAR_RRE,
2296                 },
2297         },
2298 };
2299
2300 static int ib_nr_to_mlx5_nr(int ib_mask)
2301 {
2302         switch (ib_mask) {
2303         case IB_QP_STATE:
2304                 return 0;
2305         case IB_QP_CUR_STATE:
2306                 return 0;
2307         case IB_QP_EN_SQD_ASYNC_NOTIFY:
2308                 return 0;
2309         case IB_QP_ACCESS_FLAGS:
2310                 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2311                         MLX5_QP_OPTPAR_RAE;
2312         case IB_QP_PKEY_INDEX:
2313                 return MLX5_QP_OPTPAR_PKEY_INDEX;
2314         case IB_QP_PORT:
2315                 return MLX5_QP_OPTPAR_PRI_PORT;
2316         case IB_QP_QKEY:
2317                 return MLX5_QP_OPTPAR_Q_KEY;
2318         case IB_QP_AV:
2319                 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2320                         MLX5_QP_OPTPAR_PRI_PORT;
2321         case IB_QP_PATH_MTU:
2322                 return 0;
2323         case IB_QP_TIMEOUT:
2324                 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2325         case IB_QP_RETRY_CNT:
2326                 return MLX5_QP_OPTPAR_RETRY_COUNT;
2327         case IB_QP_RNR_RETRY:
2328                 return MLX5_QP_OPTPAR_RNR_RETRY;
2329         case IB_QP_RQ_PSN:
2330                 return 0;
2331         case IB_QP_MAX_QP_RD_ATOMIC:
2332                 return MLX5_QP_OPTPAR_SRA_MAX;
2333         case IB_QP_ALT_PATH:
2334                 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2335         case IB_QP_MIN_RNR_TIMER:
2336                 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2337         case IB_QP_SQ_PSN:
2338                 return 0;
2339         case IB_QP_MAX_DEST_RD_ATOMIC:
2340                 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2341                         MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2342         case IB_QP_PATH_MIG_STATE:
2343                 return MLX5_QP_OPTPAR_PM_STATE;
2344         case IB_QP_CAP:
2345                 return 0;
2346         case IB_QP_DEST_QPN:
2347                 return 0;
2348         }
2349         return 0;
2350 }
2351
2352 static int ib_mask_to_mlx5_opt(int ib_mask)
2353 {
2354         int result = 0;
2355         int i;
2356
2357         for (i = 0; i < 8 * sizeof(int); i++) {
2358                 if ((1 << i) & ib_mask)
2359                         result |= ib_nr_to_mlx5_nr(1 << i);
2360         }
2361
2362         return result;
2363 }
2364
2365 static int modify_raw_packet_qp_rq(struct mlx5_core_dev *dev,
2366                                    struct mlx5_ib_rq *rq, int new_state)
2367 {
2368         void *in;
2369         void *rqc;
2370         int inlen;
2371         int err;
2372
2373         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2374         in = mlx5_vzalloc(inlen);
2375         if (!in)
2376                 return -ENOMEM;
2377
2378         MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2379
2380         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2381         MLX5_SET(rqc, rqc, state, new_state);
2382
2383         err = mlx5_core_modify_rq(dev, rq->base.mqp.qpn, in, inlen);
2384         if (err)
2385                 goto out;
2386
2387         rq->state = new_state;
2388
2389 out:
2390         kvfree(in);
2391         return err;
2392 }
2393
2394 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2395                                    struct mlx5_ib_sq *sq, int new_state)
2396 {
2397         void *in;
2398         void *sqc;
2399         int inlen;
2400         int err;
2401
2402         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2403         in = mlx5_vzalloc(inlen);
2404         if (!in)
2405                 return -ENOMEM;
2406
2407         MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2408
2409         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2410         MLX5_SET(sqc, sqc, state, new_state);
2411
2412         err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2413         if (err)
2414                 goto out;
2415
2416         sq->state = new_state;
2417
2418 out:
2419         kvfree(in);
2420         return err;
2421 }
2422
2423 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2424                                 u16 operation)
2425 {
2426         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2427         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2428         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2429         int rq_state;
2430         int sq_state;
2431         int err;
2432
2433         switch (operation) {
2434         case MLX5_CMD_OP_RST2INIT_QP:
2435                 rq_state = MLX5_RQC_STATE_RDY;
2436                 sq_state = MLX5_SQC_STATE_RDY;
2437                 break;
2438         case MLX5_CMD_OP_2ERR_QP:
2439                 rq_state = MLX5_RQC_STATE_ERR;
2440                 sq_state = MLX5_SQC_STATE_ERR;
2441                 break;
2442         case MLX5_CMD_OP_2RST_QP:
2443                 rq_state = MLX5_RQC_STATE_RST;
2444                 sq_state = MLX5_SQC_STATE_RST;
2445                 break;
2446         case MLX5_CMD_OP_INIT2INIT_QP:
2447         case MLX5_CMD_OP_INIT2RTR_QP:
2448         case MLX5_CMD_OP_RTR2RTS_QP:
2449         case MLX5_CMD_OP_RTS2RTS_QP:
2450                 /* Nothing to do here... */
2451                 return 0;
2452         default:
2453                 WARN_ON(1);
2454                 return -EINVAL;
2455         }
2456
2457         if (qp->rq.wqe_cnt) {
2458                 err =  modify_raw_packet_qp_rq(dev->mdev, rq, rq_state);
2459                 if (err)
2460                         return err;
2461         }
2462
2463         if (qp->sq.wqe_cnt)
2464                 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state);
2465
2466         return 0;
2467 }
2468
2469 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2470                                const struct ib_qp_attr *attr, int attr_mask,
2471                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
2472 {
2473         static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2474                 [MLX5_QP_STATE_RST] = {
2475                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2476                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2477                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_RST2INIT_QP,
2478                 },
2479                 [MLX5_QP_STATE_INIT]  = {
2480                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2481                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2482                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_INIT2INIT_QP,
2483                         [MLX5_QP_STATE_RTR]     = MLX5_CMD_OP_INIT2RTR_QP,
2484                 },
2485                 [MLX5_QP_STATE_RTR]   = {
2486                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2487                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2488                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTR2RTS_QP,
2489                 },
2490                 [MLX5_QP_STATE_RTS]   = {
2491                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2492                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2493                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTS2RTS_QP,
2494                 },
2495                 [MLX5_QP_STATE_SQD] = {
2496                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2497                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2498                 },
2499                 [MLX5_QP_STATE_SQER] = {
2500                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2501                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2502                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_SQERR2RTS_QP,
2503                 },
2504                 [MLX5_QP_STATE_ERR] = {
2505                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2506                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2507                 }
2508         };
2509
2510         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2511         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2512         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
2513         struct mlx5_ib_cq *send_cq, *recv_cq;
2514         struct mlx5_qp_context *context;
2515         struct mlx5_modify_qp_mbox_in *in;
2516         struct mlx5_ib_pd *pd;
2517         enum mlx5_qp_state mlx5_cur, mlx5_new;
2518         enum mlx5_qp_optpar optpar;
2519         int sqd_event;
2520         int mlx5_st;
2521         int err;
2522         u16 op;
2523
2524         in = kzalloc(sizeof(*in), GFP_KERNEL);
2525         if (!in)
2526                 return -ENOMEM;
2527
2528         context = &in->ctx;
2529         err = to_mlx5_st(ibqp->qp_type);
2530         if (err < 0) {
2531                 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
2532                 goto out;
2533         }
2534
2535         context->flags = cpu_to_be32(err << 16);
2536
2537         if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2538                 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2539         } else {
2540                 switch (attr->path_mig_state) {
2541                 case IB_MIG_MIGRATED:
2542                         context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2543                         break;
2544                 case IB_MIG_REARM:
2545                         context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2546                         break;
2547                 case IB_MIG_ARMED:
2548                         context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2549                         break;
2550                 }
2551         }
2552
2553         if (is_sqp(ibqp->qp_type)) {
2554                 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2555         } else if (ibqp->qp_type == IB_QPT_UD ||
2556                    ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2557                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2558         } else if (attr_mask & IB_QP_PATH_MTU) {
2559                 if (attr->path_mtu < IB_MTU_256 ||
2560                     attr->path_mtu > IB_MTU_4096) {
2561                         mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2562                         err = -EINVAL;
2563                         goto out;
2564                 }
2565                 context->mtu_msgmax = (attr->path_mtu << 5) |
2566                                       (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
2567         }
2568
2569         if (attr_mask & IB_QP_DEST_QPN)
2570                 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2571
2572         if (attr_mask & IB_QP_PKEY_INDEX)
2573                 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
2574
2575         /* todo implement counter_index functionality */
2576
2577         if (is_sqp(ibqp->qp_type))
2578                 context->pri_path.port = qp->port;
2579
2580         if (attr_mask & IB_QP_PORT)
2581                 context->pri_path.port = attr->port_num;
2582
2583         if (attr_mask & IB_QP_AV) {
2584                 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
2585                                     attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
2586                                     attr_mask, 0, attr, false);
2587                 if (err)
2588                         goto out;
2589         }
2590
2591         if (attr_mask & IB_QP_TIMEOUT)
2592                 context->pri_path.ackto_lt |= attr->timeout << 3;
2593
2594         if (attr_mask & IB_QP_ALT_PATH) {
2595                 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2596                                     &context->alt_path,
2597                                     attr->alt_port_num,
2598                                     attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2599                                     0, attr, true);
2600                 if (err)
2601                         goto out;
2602         }
2603
2604         pd = get_pd(qp);
2605         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2606                 &send_cq, &recv_cq);
2607
2608         context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2609         context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2610         context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2611         context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2612
2613         if (attr_mask & IB_QP_RNR_RETRY)
2614                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2615
2616         if (attr_mask & IB_QP_RETRY_CNT)
2617                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2618
2619         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2620                 if (attr->max_rd_atomic)
2621                         context->params1 |=
2622                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2623         }
2624
2625         if (attr_mask & IB_QP_SQ_PSN)
2626                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2627
2628         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2629                 if (attr->max_dest_rd_atomic)
2630                         context->params2 |=
2631                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2632         }
2633
2634         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2635                 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2636
2637         if (attr_mask & IB_QP_MIN_RNR_TIMER)
2638                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2639
2640         if (attr_mask & IB_QP_RQ_PSN)
2641                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2642
2643         if (attr_mask & IB_QP_QKEY)
2644                 context->qkey = cpu_to_be32(attr->qkey);
2645
2646         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2647                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2648
2649         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
2650             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2651                 sqd_event = 1;
2652         else
2653                 sqd_event = 0;
2654
2655         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2656                 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
2657                                qp->port) - 1;
2658                 struct mlx5_ib_port *mibport = &dev->port[port_num];
2659
2660                 context->qp_counter_set_usr_page |=
2661                         cpu_to_be32((u32)(mibport->q_cnt_id) << 24);
2662         }
2663
2664         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2665                 context->sq_crq_size |= cpu_to_be16(1 << 4);
2666
2667         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2668                 context->deth_sqpn = cpu_to_be32(1);
2669
2670         mlx5_cur = to_mlx5_state(cur_state);
2671         mlx5_new = to_mlx5_state(new_state);
2672         mlx5_st = to_mlx5_st(ibqp->qp_type);
2673         if (mlx5_st < 0)
2674                 goto out;
2675
2676         /* If moving to a reset or error state, we must disable page faults on
2677          * this QP and flush all current page faults. Otherwise a stale page
2678          * fault may attempt to work on this QP after it is reset and moved
2679          * again to RTS, and may cause the driver and the device to get out of
2680          * sync. */
2681         if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2682             (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR) &&
2683             (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
2684                 mlx5_ib_qp_disable_pagefaults(qp);
2685
2686         if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2687             !optab[mlx5_cur][mlx5_new])
2688                 goto out;
2689
2690         op = optab[mlx5_cur][mlx5_new];
2691         optpar = ib_mask_to_mlx5_opt(attr_mask);
2692         optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
2693         in->optparam = cpu_to_be32(optpar);
2694
2695         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET)
2696                 err = modify_raw_packet_qp(dev, qp, op);
2697         else
2698                 err = mlx5_core_qp_modify(dev->mdev, op, in, sqd_event,
2699                                           &base->mqp);
2700         if (err)
2701                 goto out;
2702
2703         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT &&
2704             (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
2705                 mlx5_ib_qp_enable_pagefaults(qp);
2706
2707         qp->state = new_state;
2708
2709         if (attr_mask & IB_QP_ACCESS_FLAGS)
2710                 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
2711         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2712                 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
2713         if (attr_mask & IB_QP_PORT)
2714                 qp->port = attr->port_num;
2715         if (attr_mask & IB_QP_ALT_PATH)
2716                 qp->trans_qp.alt_port = attr->alt_port_num;
2717
2718         /*
2719          * If we moved a kernel QP to RESET, clean up all old CQ
2720          * entries and reinitialize the QP.
2721          */
2722         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
2723                 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2724                                  ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2725                 if (send_cq != recv_cq)
2726                         mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
2727
2728                 qp->rq.head = 0;
2729                 qp->rq.tail = 0;
2730                 qp->sq.head = 0;
2731                 qp->sq.tail = 0;
2732                 qp->sq.cur_post = 0;
2733                 qp->sq.last_poll = 0;
2734                 qp->db.db[MLX5_RCV_DBR] = 0;
2735                 qp->db.db[MLX5_SND_DBR] = 0;
2736         }
2737
2738 out:
2739         kfree(in);
2740         return err;
2741 }
2742
2743 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2744                       int attr_mask, struct ib_udata *udata)
2745 {
2746         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2747         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2748         enum ib_qp_type qp_type;
2749         enum ib_qp_state cur_state, new_state;
2750         int err = -EINVAL;
2751         int port;
2752         enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
2753
2754         if (ibqp->rwq_ind_tbl)
2755                 return -ENOSYS;
2756
2757         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
2758                 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
2759
2760         qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
2761                 IB_QPT_GSI : ibqp->qp_type;
2762
2763         mutex_lock(&qp->mutex);
2764
2765         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2766         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2767
2768         if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
2769                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2770                 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
2771         }
2772
2773         if (qp_type != MLX5_IB_QPT_REG_UMR &&
2774             !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
2775                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
2776                             cur_state, new_state, ibqp->qp_type, attr_mask);
2777                 goto out;
2778         }
2779
2780         if ((attr_mask & IB_QP_PORT) &&
2781             (attr->port_num == 0 ||
2782              attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
2783                 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
2784                             attr->port_num, dev->num_ports);
2785                 goto out;
2786         }
2787
2788         if (attr_mask & IB_QP_PKEY_INDEX) {
2789                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2790                 if (attr->pkey_index >=
2791                     dev->mdev->port_caps[port - 1].pkey_table_len) {
2792                         mlx5_ib_dbg(dev, "invalid pkey index %d\n",
2793                                     attr->pkey_index);
2794                         goto out;
2795                 }
2796         }
2797
2798         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2799             attr->max_rd_atomic >
2800             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
2801                 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
2802                             attr->max_rd_atomic);
2803                 goto out;
2804         }
2805
2806         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2807             attr->max_dest_rd_atomic >
2808             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
2809                 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
2810                             attr->max_dest_rd_atomic);
2811                 goto out;
2812         }
2813
2814         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2815                 err = 0;
2816                 goto out;
2817         }
2818
2819         err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2820
2821 out:
2822         mutex_unlock(&qp->mutex);
2823         return err;
2824 }
2825
2826 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2827 {
2828         struct mlx5_ib_cq *cq;
2829         unsigned cur;
2830
2831         cur = wq->head - wq->tail;
2832         if (likely(cur + nreq < wq->max_post))
2833                 return 0;
2834
2835         cq = to_mcq(ib_cq);
2836         spin_lock(&cq->lock);
2837         cur = wq->head - wq->tail;
2838         spin_unlock(&cq->lock);
2839
2840         return cur + nreq >= wq->max_post;
2841 }
2842
2843 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
2844                                           u64 remote_addr, u32 rkey)
2845 {
2846         rseg->raddr    = cpu_to_be64(remote_addr);
2847         rseg->rkey     = cpu_to_be32(rkey);
2848         rseg->reserved = 0;
2849 }
2850
2851 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
2852                          struct ib_send_wr *wr, void *qend,
2853                          struct mlx5_ib_qp *qp, int *size)
2854 {
2855         void *seg = eseg;
2856
2857         memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
2858
2859         if (wr->send_flags & IB_SEND_IP_CSUM)
2860                 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
2861                                  MLX5_ETH_WQE_L4_CSUM;
2862
2863         seg += sizeof(struct mlx5_wqe_eth_seg);
2864         *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
2865
2866         if (wr->opcode == IB_WR_LSO) {
2867                 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
2868                 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start);
2869                 u64 left, leftlen, copysz;
2870                 void *pdata = ud_wr->header;
2871
2872                 left = ud_wr->hlen;
2873                 eseg->mss = cpu_to_be16(ud_wr->mss);
2874                 eseg->inline_hdr_sz = cpu_to_be16(left);
2875
2876                 /*
2877                  * check if there is space till the end of queue, if yes,
2878                  * copy all in one shot, otherwise copy till the end of queue,
2879                  * rollback and than the copy the left
2880                  */
2881                 leftlen = qend - (void *)eseg->inline_hdr_start;
2882                 copysz = min_t(u64, leftlen, left);
2883
2884                 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
2885
2886                 if (likely(copysz > size_of_inl_hdr_start)) {
2887                         seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
2888                         *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
2889                 }
2890
2891                 if (unlikely(copysz < left)) { /* the last wqe in the queue */
2892                         seg = mlx5_get_send_wqe(qp, 0);
2893                         left -= copysz;
2894                         pdata += copysz;
2895                         memcpy(seg, pdata, left);
2896                         seg += ALIGN(left, 16);
2897                         *size += ALIGN(left, 16) / 16;
2898                 }
2899         }
2900
2901         return seg;
2902 }
2903
2904 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
2905                              struct ib_send_wr *wr)
2906 {
2907         memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
2908         dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
2909         dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
2910 }
2911
2912 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
2913 {
2914         dseg->byte_count = cpu_to_be32(sg->length);
2915         dseg->lkey       = cpu_to_be32(sg->lkey);
2916         dseg->addr       = cpu_to_be64(sg->addr);
2917 }
2918
2919 static __be16 get_klm_octo(int npages)
2920 {
2921         return cpu_to_be16(ALIGN(npages, 8) / 2);
2922 }
2923
2924 static __be64 frwr_mkey_mask(void)
2925 {
2926         u64 result;
2927
2928         result = MLX5_MKEY_MASK_LEN             |
2929                 MLX5_MKEY_MASK_PAGE_SIZE        |
2930                 MLX5_MKEY_MASK_START_ADDR       |
2931                 MLX5_MKEY_MASK_EN_RINVAL        |
2932                 MLX5_MKEY_MASK_KEY              |
2933                 MLX5_MKEY_MASK_LR               |
2934                 MLX5_MKEY_MASK_LW               |
2935                 MLX5_MKEY_MASK_RR               |
2936                 MLX5_MKEY_MASK_RW               |
2937                 MLX5_MKEY_MASK_A                |
2938                 MLX5_MKEY_MASK_SMALL_FENCE      |
2939                 MLX5_MKEY_MASK_FREE;
2940
2941         return cpu_to_be64(result);
2942 }
2943
2944 static __be64 sig_mkey_mask(void)
2945 {
2946         u64 result;
2947
2948         result = MLX5_MKEY_MASK_LEN             |
2949                 MLX5_MKEY_MASK_PAGE_SIZE        |
2950                 MLX5_MKEY_MASK_START_ADDR       |
2951                 MLX5_MKEY_MASK_EN_SIGERR        |
2952                 MLX5_MKEY_MASK_EN_RINVAL        |
2953                 MLX5_MKEY_MASK_KEY              |
2954                 MLX5_MKEY_MASK_LR               |
2955                 MLX5_MKEY_MASK_LW               |
2956                 MLX5_MKEY_MASK_RR               |
2957                 MLX5_MKEY_MASK_RW               |
2958                 MLX5_MKEY_MASK_SMALL_FENCE      |
2959                 MLX5_MKEY_MASK_FREE             |
2960                 MLX5_MKEY_MASK_BSF_EN;
2961
2962         return cpu_to_be64(result);
2963 }
2964
2965 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
2966                                 struct mlx5_ib_mr *mr)
2967 {
2968         int ndescs = mr->ndescs;
2969
2970         memset(umr, 0, sizeof(*umr));
2971
2972         if (mr->access_mode == MLX5_ACCESS_MODE_KLM)
2973                 /* KLMs take twice the size of MTTs */
2974                 ndescs *= 2;
2975
2976         umr->flags = MLX5_UMR_CHECK_NOT_FREE;
2977         umr->klm_octowords = get_klm_octo(ndescs);
2978         umr->mkey_mask = frwr_mkey_mask();
2979 }
2980
2981 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
2982 {
2983         memset(umr, 0, sizeof(*umr));
2984         umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
2985         umr->flags = 1 << 7;
2986 }
2987
2988 static __be64 get_umr_reg_mr_mask(void)
2989 {
2990         u64 result;
2991
2992         result = MLX5_MKEY_MASK_LEN             |
2993                  MLX5_MKEY_MASK_PAGE_SIZE       |
2994                  MLX5_MKEY_MASK_START_ADDR      |
2995                  MLX5_MKEY_MASK_PD              |
2996                  MLX5_MKEY_MASK_LR              |
2997                  MLX5_MKEY_MASK_LW              |
2998                  MLX5_MKEY_MASK_KEY             |
2999                  MLX5_MKEY_MASK_RR              |
3000                  MLX5_MKEY_MASK_RW              |
3001                  MLX5_MKEY_MASK_A               |
3002                  MLX5_MKEY_MASK_FREE;
3003
3004         return cpu_to_be64(result);
3005 }
3006
3007 static __be64 get_umr_unreg_mr_mask(void)
3008 {
3009         u64 result;
3010
3011         result = MLX5_MKEY_MASK_FREE;
3012
3013         return cpu_to_be64(result);
3014 }
3015
3016 static __be64 get_umr_update_mtt_mask(void)
3017 {
3018         u64 result;
3019
3020         result = MLX5_MKEY_MASK_FREE;
3021
3022         return cpu_to_be64(result);
3023 }
3024
3025 static __be64 get_umr_update_translation_mask(void)
3026 {
3027         u64 result;
3028
3029         result = MLX5_MKEY_MASK_LEN |
3030                  MLX5_MKEY_MASK_PAGE_SIZE |
3031                  MLX5_MKEY_MASK_START_ADDR |
3032                  MLX5_MKEY_MASK_KEY |
3033                  MLX5_MKEY_MASK_FREE;
3034
3035         return cpu_to_be64(result);
3036 }
3037
3038 static __be64 get_umr_update_access_mask(void)
3039 {
3040         u64 result;
3041
3042         result = MLX5_MKEY_MASK_LW |
3043                  MLX5_MKEY_MASK_RR |
3044                  MLX5_MKEY_MASK_RW |
3045                  MLX5_MKEY_MASK_A |
3046                  MLX5_MKEY_MASK_KEY |
3047                  MLX5_MKEY_MASK_FREE;
3048
3049         return cpu_to_be64(result);
3050 }
3051
3052 static __be64 get_umr_update_pd_mask(void)
3053 {
3054         u64 result;
3055
3056         result = MLX5_MKEY_MASK_PD |
3057                  MLX5_MKEY_MASK_KEY |
3058                  MLX5_MKEY_MASK_FREE;
3059
3060         return cpu_to_be64(result);
3061 }
3062
3063 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3064                                 struct ib_send_wr *wr)
3065 {
3066         struct mlx5_umr_wr *umrwr = umr_wr(wr);
3067
3068         memset(umr, 0, sizeof(*umr));
3069
3070         if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3071                 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3072         else
3073                 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3074
3075         if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) {
3076                 umr->klm_octowords = get_klm_octo(umrwr->npages);
3077                 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) {
3078                         umr->mkey_mask = get_umr_update_mtt_mask();
3079                         umr->bsf_octowords = get_klm_octo(umrwr->target.offset);
3080                         umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
3081                 }
3082                 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3083                         umr->mkey_mask |= get_umr_update_translation_mask();
3084                 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_ACCESS)
3085                         umr->mkey_mask |= get_umr_update_access_mask();
3086                 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD)
3087                         umr->mkey_mask |= get_umr_update_pd_mask();
3088                 if (!umr->mkey_mask)
3089                         umr->mkey_mask = get_umr_reg_mr_mask();
3090         } else {
3091                 umr->mkey_mask = get_umr_unreg_mr_mask();
3092         }
3093
3094         if (!wr->num_sge)
3095                 umr->flags |= MLX5_UMR_INLINE;
3096 }
3097
3098 static u8 get_umr_flags(int acc)
3099 {
3100         return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
3101                (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
3102                (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
3103                (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
3104                 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
3105 }
3106
3107 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3108                              struct mlx5_ib_mr *mr,
3109                              u32 key, int access)
3110 {
3111         int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3112
3113         memset(seg, 0, sizeof(*seg));
3114
3115         if (mr->access_mode == MLX5_ACCESS_MODE_MTT)
3116                 seg->log2_page_size = ilog2(mr->ibmr.page_size);
3117         else if (mr->access_mode == MLX5_ACCESS_MODE_KLM)
3118                 /* KLMs take twice the size of MTTs */
3119                 ndescs *= 2;
3120
3121         seg->flags = get_umr_flags(access) | mr->access_mode;
3122         seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3123         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3124         seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3125         seg->len = cpu_to_be64(mr->ibmr.length);
3126         seg->xlt_oct_size = cpu_to_be32(ndescs);
3127 }
3128
3129 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
3130 {
3131         memset(seg, 0, sizeof(*seg));
3132         seg->status = MLX5_MKEY_STATUS_FREE;
3133 }
3134
3135 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3136 {
3137         struct mlx5_umr_wr *umrwr = umr_wr(wr);
3138
3139         memset(seg, 0, sizeof(*seg));
3140         if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) {
3141                 seg->status = MLX5_MKEY_STATUS_FREE;
3142                 return;
3143         }
3144
3145         seg->flags = convert_access(umrwr->access_flags);
3146         if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) {
3147                 if (umrwr->pd)
3148                         seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3149                 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr);
3150         }
3151         seg->len = cpu_to_be64(umrwr->length);
3152         seg->log2_page_size = umrwr->page_shift;
3153         seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
3154                                        mlx5_mkey_variant(umrwr->mkey));
3155 }
3156
3157 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3158                              struct mlx5_ib_mr *mr,
3159                              struct mlx5_ib_pd *pd)
3160 {
3161         int bcount = mr->desc_size * mr->ndescs;
3162
3163         dseg->addr = cpu_to_be64(mr->desc_map);
3164         dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3165         dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3166 }
3167
3168 static __be32 send_ieth(struct ib_send_wr *wr)
3169 {
3170         switch (wr->opcode) {
3171         case IB_WR_SEND_WITH_IMM:
3172         case IB_WR_RDMA_WRITE_WITH_IMM:
3173                 return wr->ex.imm_data;
3174
3175         case IB_WR_SEND_WITH_INV:
3176                 return cpu_to_be32(wr->ex.invalidate_rkey);
3177
3178         default:
3179                 return 0;
3180         }
3181 }
3182
3183 static u8 calc_sig(void *wqe, int size)
3184 {
3185         u8 *p = wqe;
3186         u8 res = 0;
3187         int i;
3188
3189         for (i = 0; i < size; i++)
3190                 res ^= p[i];
3191
3192         return ~res;
3193 }
3194
3195 static u8 wq_sig(void *wqe)
3196 {
3197         return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3198 }
3199
3200 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3201                             void *wqe, int *sz)
3202 {
3203         struct mlx5_wqe_inline_seg *seg;
3204         void *qend = qp->sq.qend;
3205         void *addr;
3206         int inl = 0;
3207         int copy;
3208         int len;
3209         int i;
3210
3211         seg = wqe;
3212         wqe += sizeof(*seg);
3213         for (i = 0; i < wr->num_sge; i++) {
3214                 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3215                 len  = wr->sg_list[i].length;
3216                 inl += len;
3217
3218                 if (unlikely(inl > qp->max_inline_data))
3219                         return -ENOMEM;
3220
3221                 if (unlikely(wqe + len > qend)) {
3222                         copy = qend - wqe;
3223                         memcpy(wqe, addr, copy);
3224                         addr += copy;
3225                         len -= copy;
3226                         wqe = mlx5_get_send_wqe(qp, 0);
3227                 }
3228                 memcpy(wqe, addr, len);
3229                 wqe += len;
3230         }
3231
3232         seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3233
3234         *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3235
3236         return 0;
3237 }
3238
3239 static u16 prot_field_size(enum ib_signature_type type)
3240 {
3241         switch (type) {
3242         case IB_SIG_TYPE_T10_DIF:
3243                 return MLX5_DIF_SIZE;
3244         default:
3245                 return 0;
3246         }
3247 }
3248
3249 static u8 bs_selector(int block_size)
3250 {
3251         switch (block_size) {
3252         case 512:           return 0x1;
3253         case 520:           return 0x2;
3254         case 4096:          return 0x3;
3255         case 4160:          return 0x4;
3256         case 1073741824:    return 0x5;
3257         default:            return 0;
3258         }
3259 }
3260
3261 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3262                               struct mlx5_bsf_inl *inl)
3263 {
3264         /* Valid inline section and allow BSF refresh */
3265         inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3266                                        MLX5_BSF_REFRESH_DIF);
3267         inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3268         inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
3269         /* repeating block */
3270         inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3271         inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3272                         MLX5_DIF_CRC : MLX5_DIF_IPCS;
3273
3274         if (domain->sig.dif.ref_remap)
3275                 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
3276
3277         if (domain->sig.dif.app_escape) {
3278                 if (domain->sig.dif.ref_escape)
3279                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3280                 else
3281                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
3282         }
3283
3284         inl->dif_app_bitmask_check =
3285                 cpu_to_be16(domain->sig.dif.apptag_check_mask);
3286 }
3287
3288 static int mlx5_set_bsf(struct ib_mr *sig_mr,
3289                         struct ib_sig_attrs *sig_attrs,
3290                         struct mlx5_bsf *bsf, u32 data_size)
3291 {
3292         struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3293         struct mlx5_bsf_basic *basic = &bsf->basic;
3294         struct ib_sig_domain *mem = &sig_attrs->mem;
3295         struct ib_sig_domain *wire = &sig_attrs->wire;
3296
3297         memset(bsf, 0, sizeof(*bsf));
3298
3299         /* Basic + Extended + Inline */
3300         basic->bsf_size_sbs = 1 << 7;
3301         /* Input domain check byte mask */
3302         basic->check_byte_mask = sig_attrs->check_mask;
3303         basic->raw_data_size = cpu_to_be32(data_size);
3304
3305         /* Memory domain */
3306         switch (sig_attrs->mem.sig_type) {
3307         case IB_SIG_TYPE_NONE:
3308                 break;
3309         case IB_SIG_TYPE_T10_DIF:
3310                 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3311                 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3312                 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3313                 break;
3314         default:
3315                 return -EINVAL;
3316         }
3317
3318         /* Wire domain */
3319         switch (sig_attrs->wire.sig_type) {
3320         case IB_SIG_TYPE_NONE:
3321                 break;
3322         case IB_SIG_TYPE_T10_DIF:
3323                 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
3324                     mem->sig_type == wire->sig_type) {
3325                         /* Same block structure */
3326                         basic->bsf_size_sbs |= 1 << 4;
3327                         if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
3328                                 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
3329                         if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
3330                                 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
3331                         if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
3332                                 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
3333                 } else
3334                         basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3335
3336                 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
3337                 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
3338                 break;
3339         default:
3340                 return -EINVAL;
3341         }
3342
3343         return 0;
3344 }
3345
3346 static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3347                                 struct mlx5_ib_qp *qp, void **seg, int *size)
3348 {
3349         struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3350         struct ib_mr *sig_mr = wr->sig_mr;
3351         struct mlx5_bsf *bsf;
3352         u32 data_len = wr->wr.sg_list->length;
3353         u32 data_key = wr->wr.sg_list->lkey;
3354         u64 data_va = wr->wr.sg_list->addr;
3355         int ret;
3356         int wqe_size;
3357
3358         if (!wr->prot ||
3359             (data_key == wr->prot->lkey &&
3360              data_va == wr->prot->addr &&
3361              data_len == wr->prot->length)) {
3362                 /**
3363                  * Source domain doesn't contain signature information
3364                  * or data and protection are interleaved in memory.
3365                  * So need construct:
3366                  *                  ------------------
3367                  *                 |     data_klm     |
3368                  *                  ------------------
3369                  *                 |       BSF        |
3370                  *                  ------------------
3371                  **/
3372                 struct mlx5_klm *data_klm = *seg;
3373
3374                 data_klm->bcount = cpu_to_be32(data_len);
3375                 data_klm->key = cpu_to_be32(data_key);
3376                 data_klm->va = cpu_to_be64(data_va);
3377                 wqe_size = ALIGN(sizeof(*data_klm), 64);
3378         } else {
3379                 /**
3380                  * Source domain contains signature information
3381                  * So need construct a strided block format:
3382                  *               ---------------------------
3383                  *              |     stride_block_ctrl     |
3384                  *               ---------------------------
3385                  *              |          data_klm         |
3386                  *               ---------------------------
3387                  *              |          prot_klm         |
3388                  *               ---------------------------
3389                  *              |             BSF           |
3390                  *               ---------------------------
3391                  **/
3392                 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3393                 struct mlx5_stride_block_entry *data_sentry;
3394                 struct mlx5_stride_block_entry *prot_sentry;
3395                 u32 prot_key = wr->prot->lkey;
3396                 u64 prot_va = wr->prot->addr;
3397                 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3398                 int prot_size;
3399
3400                 sblock_ctrl = *seg;
3401                 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3402                 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3403
3404                 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3405                 if (!prot_size) {
3406                         pr_err("Bad block size given: %u\n", block_size);
3407                         return -EINVAL;
3408                 }
3409                 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3410                                                             prot_size);
3411                 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3412                 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3413                 sblock_ctrl->num_entries = cpu_to_be16(2);
3414
3415                 data_sentry->bcount = cpu_to_be16(block_size);
3416                 data_sentry->key = cpu_to_be32(data_key);
3417                 data_sentry->va = cpu_to_be64(data_va);
3418                 data_sentry->stride = cpu_to_be16(block_size);
3419
3420                 prot_sentry->bcount = cpu_to_be16(prot_size);
3421                 prot_sentry->key = cpu_to_be32(prot_key);
3422                 prot_sentry->va = cpu_to_be64(prot_va);
3423                 prot_sentry->stride = cpu_to_be16(prot_size);
3424
3425                 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3426                                  sizeof(*prot_sentry), 64);
3427         }
3428
3429         *seg += wqe_size;
3430         *size += wqe_size / 16;
3431         if (unlikely((*seg == qp->sq.qend)))
3432                 *seg = mlx5_get_send_wqe(qp, 0);
3433
3434         bsf = *seg;
3435         ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3436         if (ret)
3437                 return -EINVAL;
3438
3439         *seg += sizeof(*bsf);
3440         *size += sizeof(*bsf) / 16;
3441         if (unlikely((*seg == qp->sq.qend)))
3442                 *seg = mlx5_get_send_wqe(qp, 0);
3443
3444         return 0;
3445 }
3446
3447 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
3448                                  struct ib_sig_handover_wr *wr, u32 nelements,
3449                                  u32 length, u32 pdn)
3450 {
3451         struct ib_mr *sig_mr = wr->sig_mr;
3452         u32 sig_key = sig_mr->rkey;
3453         u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
3454
3455         memset(seg, 0, sizeof(*seg));
3456
3457         seg->flags = get_umr_flags(wr->access_flags) |
3458                                    MLX5_ACCESS_MODE_KLM;
3459         seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
3460         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
3461                                     MLX5_MKEY_BSF_EN | pdn);
3462         seg->len = cpu_to_be64(length);
3463         seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements)));
3464         seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3465 }
3466
3467 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3468                                 u32 nelements)
3469 {
3470         memset(umr, 0, sizeof(*umr));
3471
3472         umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
3473         umr->klm_octowords = get_klm_octo(nelements);
3474         umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3475         umr->mkey_mask = sig_mkey_mask();
3476 }
3477
3478
3479 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
3480                           void **seg, int *size)
3481 {
3482         struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3483         struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
3484         u32 pdn = get_pd(qp)->pdn;
3485         u32 klm_oct_size;
3486         int region_len, ret;
3487
3488         if (unlikely(wr->wr.num_sge != 1) ||
3489             unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
3490             unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3491             unlikely(!sig_mr->sig->sig_status_checked))
3492                 return -EINVAL;
3493
3494         /* length of the protected region, data + protection */
3495         region_len = wr->wr.sg_list->length;
3496         if (wr->prot &&
3497             (wr->prot->lkey != wr->wr.sg_list->lkey  ||
3498              wr->prot->addr != wr->wr.sg_list->addr  ||
3499              wr->prot->length != wr->wr.sg_list->length))
3500                 region_len += wr->prot->length;
3501
3502         /**
3503          * KLM octoword size - if protection was provided
3504          * then we use strided block format (3 octowords),
3505          * else we use single KLM (1 octoword)
3506          **/
3507         klm_oct_size = wr->prot ? 3 : 1;
3508
3509         set_sig_umr_segment(*seg, klm_oct_size);
3510         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3511         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3512         if (unlikely((*seg == qp->sq.qend)))
3513                 *seg = mlx5_get_send_wqe(qp, 0);
3514
3515         set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn);
3516         *seg += sizeof(struct mlx5_mkey_seg);
3517         *size += sizeof(struct mlx5_mkey_seg) / 16;
3518         if (unlikely((*seg == qp->sq.qend)))
3519                 *seg = mlx5_get_send_wqe(qp, 0);
3520
3521         ret = set_sig_data_segment(wr, qp, seg, size);
3522         if (ret)
3523                 return ret;
3524
3525         sig_mr->sig->sig_status_checked = false;
3526         return 0;
3527 }
3528
3529 static int set_psv_wr(struct ib_sig_domain *domain,
3530                       u32 psv_idx, void **seg, int *size)
3531 {
3532         struct mlx5_seg_set_psv *psv_seg = *seg;
3533
3534         memset(psv_seg, 0, sizeof(*psv_seg));
3535         psv_seg->psv_num = cpu_to_be32(psv_idx);
3536         switch (domain->sig_type) {
3537         case IB_SIG_TYPE_NONE:
3538                 break;
3539         case IB_SIG_TYPE_T10_DIF:
3540                 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3541                                                      domain->sig.dif.app_tag);
3542                 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
3543                 break;
3544         default:
3545                 pr_err("Bad signature type given.\n");
3546                 return 1;
3547         }
3548
3549         *seg += sizeof(*psv_seg);
3550         *size += sizeof(*psv_seg) / 16;
3551
3552         return 0;
3553 }
3554
3555 static int set_reg_wr(struct mlx5_ib_qp *qp,
3556                       struct ib_reg_wr *wr,
3557                       void **seg, int *size)
3558 {
3559         struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3560         struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3561
3562         if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3563                 mlx5_ib_warn(to_mdev(qp->ibqp.device),
3564                              "Invalid IB_SEND_INLINE send flag\n");
3565                 return -EINVAL;
3566         }
3567
3568         set_reg_umr_seg(*seg, mr);
3569         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3570         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3571         if (unlikely((*seg == qp->sq.qend)))
3572                 *seg = mlx5_get_send_wqe(qp, 0);
3573
3574         set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3575         *seg += sizeof(struct mlx5_mkey_seg);
3576         *size += sizeof(struct mlx5_mkey_seg) / 16;
3577         if (unlikely((*seg == qp->sq.qend)))
3578                 *seg = mlx5_get_send_wqe(qp, 0);
3579
3580         set_reg_data_seg(*seg, mr, pd);
3581         *seg += sizeof(struct mlx5_wqe_data_seg);
3582         *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3583
3584         return 0;
3585 }
3586
3587 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
3588 {
3589         set_linv_umr_seg(*seg);
3590         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3591         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3592         if (unlikely((*seg == qp->sq.qend)))
3593                 *seg = mlx5_get_send_wqe(qp, 0);
3594         set_linv_mkey_seg(*seg);
3595         *seg += sizeof(struct mlx5_mkey_seg);
3596         *size += sizeof(struct mlx5_mkey_seg) / 16;
3597         if (unlikely((*seg == qp->sq.qend)))
3598                 *seg = mlx5_get_send_wqe(qp, 0);
3599 }
3600
3601 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3602 {
3603         __be32 *p = NULL;
3604         int tidx = idx;
3605         int i, j;
3606
3607         pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3608         for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3609                 if ((i & 0xf) == 0) {
3610                         void *buf = mlx5_get_send_wqe(qp, tidx);
3611                         tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3612                         p = buf;
3613                         j = 0;
3614                 }
3615                 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3616                          be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3617                          be32_to_cpu(p[j + 3]));
3618         }
3619 }
3620
3621 static void mlx5_bf_copy(u64 __iomem *dst, u64 *src,
3622                          unsigned bytecnt, struct mlx5_ib_qp *qp)
3623 {
3624         while (bytecnt > 0) {
3625                 __iowrite64_copy(dst++, src++, 8);
3626                 __iowrite64_copy(dst++, src++, 8);
3627                 __iowrite64_copy(dst++, src++, 8);
3628                 __iowrite64_copy(dst++, src++, 8);
3629                 __iowrite64_copy(dst++, src++, 8);
3630                 __iowrite64_copy(dst++, src++, 8);
3631                 __iowrite64_copy(dst++, src++, 8);
3632                 __iowrite64_copy(dst++, src++, 8);
3633                 bytecnt -= 64;
3634                 if (unlikely(src == qp->sq.qend))
3635                         src = mlx5_get_send_wqe(qp, 0);
3636         }
3637 }
3638
3639 static u8 get_fence(u8 fence, struct ib_send_wr *wr)
3640 {
3641         if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
3642                      wr->send_flags & IB_SEND_FENCE))
3643                 return MLX5_FENCE_MODE_STRONG_ORDERING;
3644
3645         if (unlikely(fence)) {
3646                 if (wr->send_flags & IB_SEND_FENCE)
3647                         return MLX5_FENCE_MODE_SMALL_AND_FENCE;
3648                 else
3649                         return fence;
3650         } else if (unlikely(wr->send_flags & IB_SEND_FENCE)) {
3651                 return MLX5_FENCE_MODE_FENCE;
3652         }
3653
3654         return 0;
3655 }
3656
3657 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3658                      struct mlx5_wqe_ctrl_seg **ctrl,
3659                      struct ib_send_wr *wr, unsigned *idx,
3660                      int *size, int nreq)
3661 {
3662         if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
3663                 return -ENOMEM;
3664
3665         *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3666         *seg = mlx5_get_send_wqe(qp, *idx);
3667         *ctrl = *seg;
3668         *(uint32_t *)(*seg + 8) = 0;
3669         (*ctrl)->imm = send_ieth(wr);
3670         (*ctrl)->fm_ce_se = qp->sq_signal_bits |
3671                 (wr->send_flags & IB_SEND_SIGNALED ?
3672                  MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3673                 (wr->send_flags & IB_SEND_SOLICITED ?
3674                  MLX5_WQE_CTRL_SOLICITED : 0);
3675
3676         *seg += sizeof(**ctrl);
3677         *size = sizeof(**ctrl) / 16;
3678
3679         return 0;
3680 }
3681
3682 static void finish_wqe(struct mlx5_ib_qp *qp,
3683                        struct mlx5_wqe_ctrl_seg *ctrl,
3684                        u8 size, unsigned idx, u64 wr_id,
3685                        int nreq, u8 fence, u8 next_fence,
3686                        u32 mlx5_opcode)
3687 {
3688         u8 opmod = 0;
3689
3690         ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3691                                              mlx5_opcode | ((u32)opmod << 24));
3692         ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
3693         ctrl->fm_ce_se |= fence;
3694         qp->fm_cache = next_fence;
3695         if (unlikely(qp->wq_sig))
3696                 ctrl->signature = wq_sig(ctrl);
3697
3698         qp->sq.wrid[idx] = wr_id;
3699         qp->sq.w_list[idx].opcode = mlx5_opcode;
3700         qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3701         qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3702         qp->sq.w_list[idx].next = qp->sq.cur_post;
3703 }
3704
3705
3706 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3707                       struct ib_send_wr **bad_wr)
3708 {
3709         struct mlx5_wqe_ctrl_seg *ctrl = NULL;  /* compiler warning */
3710         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3711         struct mlx5_core_dev *mdev = dev->mdev;
3712         struct mlx5_ib_qp *qp;
3713         struct mlx5_ib_mr *mr;
3714         struct mlx5_wqe_data_seg *dpseg;
3715         struct mlx5_wqe_xrc_seg *xrc;
3716         struct mlx5_bf *bf;
3717         int uninitialized_var(size);
3718         void *qend;
3719         unsigned long flags;
3720         unsigned idx;
3721         int err = 0;
3722         int inl = 0;
3723         int num_sge;
3724         void *seg;
3725         int nreq;
3726         int i;
3727         u8 next_fence = 0;
3728         u8 fence;
3729
3730         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3731                 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
3732
3733         qp = to_mqp(ibqp);
3734         bf = qp->bf;
3735         qend = qp->sq.qend;
3736
3737         spin_lock_irqsave(&qp->sq.lock, flags);
3738
3739         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
3740                 err = -EIO;
3741                 *bad_wr = wr;
3742                 nreq = 0;
3743                 goto out;
3744         }
3745
3746         for (nreq = 0; wr; nreq++, wr = wr->next) {
3747                 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
3748                         mlx5_ib_warn(dev, "\n");
3749                         err = -EINVAL;
3750                         *bad_wr = wr;
3751                         goto out;
3752                 }
3753
3754                 fence = qp->fm_cache;
3755                 num_sge = wr->num_sge;
3756                 if (unlikely(num_sge > qp->sq.max_gs)) {
3757                         mlx5_ib_warn(dev, "\n");
3758                         err = -EINVAL;
3759                         *bad_wr = wr;
3760                         goto out;
3761                 }
3762
3763                 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3764                 if (err) {
3765                         mlx5_ib_warn(dev, "\n");
3766                         err = -ENOMEM;
3767                         *bad_wr = wr;
3768                         goto out;
3769                 }
3770
3771                 switch (ibqp->qp_type) {
3772                 case IB_QPT_XRC_INI:
3773                         xrc = seg;
3774                         seg += sizeof(*xrc);
3775                         size += sizeof(*xrc) / 16;
3776                         /* fall through */
3777                 case IB_QPT_RC:
3778                         switch (wr->opcode) {
3779                         case IB_WR_RDMA_READ:
3780                         case IB_WR_RDMA_WRITE:
3781                         case IB_WR_RDMA_WRITE_WITH_IMM:
3782                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3783                                               rdma_wr(wr)->rkey);
3784                                 seg += sizeof(struct mlx5_wqe_raddr_seg);
3785                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3786                                 break;
3787
3788                         case IB_WR_ATOMIC_CMP_AND_SWP:
3789                         case IB_WR_ATOMIC_FETCH_AND_ADD:
3790                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
3791                                 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
3792                                 err = -ENOSYS;
3793                                 *bad_wr = wr;
3794                                 goto out;
3795
3796                         case IB_WR_LOCAL_INV:
3797                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3798                                 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
3799                                 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
3800                                 set_linv_wr(qp, &seg, &size);
3801                                 num_sge = 0;
3802                                 break;
3803
3804                         case IB_WR_REG_MR:
3805                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3806                                 qp->sq.wr_data[idx] = IB_WR_REG_MR;
3807                                 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
3808                                 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
3809                                 if (err) {
3810                                         *bad_wr = wr;
3811                                         goto out;
3812                                 }
3813                                 num_sge = 0;
3814                                 break;
3815
3816                         case IB_WR_REG_SIG_MR:
3817                                 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
3818                                 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
3819
3820                                 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
3821                                 err = set_sig_umr_wr(wr, qp, &seg, &size);
3822                                 if (err) {
3823                                         mlx5_ib_warn(dev, "\n");
3824                                         *bad_wr = wr;
3825                                         goto out;
3826                                 }
3827
3828                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3829                                            nreq, get_fence(fence, wr),
3830                                            next_fence, MLX5_OPCODE_UMR);
3831                                 /*
3832                                  * SET_PSV WQEs are not signaled and solicited
3833                                  * on error
3834                                  */
3835                                 wr->send_flags &= ~IB_SEND_SIGNALED;
3836                                 wr->send_flags |= IB_SEND_SOLICITED;
3837                                 err = begin_wqe(qp, &seg, &ctrl, wr,
3838                                                 &idx, &size, nreq);
3839                                 if (err) {
3840                                         mlx5_ib_warn(dev, "\n");
3841                                         err = -ENOMEM;
3842                                         *bad_wr = wr;
3843                                         goto out;
3844                                 }
3845
3846                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
3847                                                  mr->sig->psv_memory.psv_idx, &seg,
3848                                                  &size);
3849                                 if (err) {
3850                                         mlx5_ib_warn(dev, "\n");
3851                                         *bad_wr = wr;
3852                                         goto out;
3853                                 }
3854
3855                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3856                                            nreq, get_fence(fence, wr),
3857                                            next_fence, MLX5_OPCODE_SET_PSV);
3858                                 err = begin_wqe(qp, &seg, &ctrl, wr,
3859                                                 &idx, &size, nreq);
3860                                 if (err) {
3861                                         mlx5_ib_warn(dev, "\n");
3862                                         err = -ENOMEM;
3863                                         *bad_wr = wr;
3864                                         goto out;
3865                                 }
3866
3867                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3868                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
3869                                                  mr->sig->psv_wire.psv_idx, &seg,
3870                                                  &size);
3871                                 if (err) {
3872                                         mlx5_ib_warn(dev, "\n");
3873                                         *bad_wr = wr;
3874                                         goto out;
3875                                 }
3876
3877                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3878                                            nreq, get_fence(fence, wr),
3879                                            next_fence, MLX5_OPCODE_SET_PSV);
3880                                 num_sge = 0;
3881                                 goto skip_psv;
3882
3883                         default:
3884                                 break;
3885                         }
3886                         break;
3887
3888                 case IB_QPT_UC:
3889                         switch (wr->opcode) {
3890                         case IB_WR_RDMA_WRITE:
3891                         case IB_WR_RDMA_WRITE_WITH_IMM:
3892                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3893                                               rdma_wr(wr)->rkey);
3894                                 seg  += sizeof(struct mlx5_wqe_raddr_seg);
3895                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3896                                 break;
3897
3898                         default:
3899                                 break;
3900                         }
3901                         break;
3902
3903                 case IB_QPT_SMI:
3904                 case MLX5_IB_QPT_HW_GSI:
3905                         set_datagram_seg(seg, wr);
3906                         seg += sizeof(struct mlx5_wqe_datagram_seg);
3907                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
3908                         if (unlikely((seg == qend)))
3909                                 seg = mlx5_get_send_wqe(qp, 0);
3910                         break;
3911                 case IB_QPT_UD:
3912                         set_datagram_seg(seg, wr);
3913                         seg += sizeof(struct mlx5_wqe_datagram_seg);
3914                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
3915
3916                         if (unlikely((seg == qend)))
3917                                 seg = mlx5_get_send_wqe(qp, 0);
3918
3919                         /* handle qp that supports ud offload */
3920                         if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
3921                                 struct mlx5_wqe_eth_pad *pad;
3922
3923                                 pad = seg;
3924                                 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
3925                                 seg += sizeof(struct mlx5_wqe_eth_pad);
3926                                 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
3927
3928                                 seg = set_eth_seg(seg, wr, qend, qp, &size);
3929
3930                                 if (unlikely((seg == qend)))
3931                                         seg = mlx5_get_send_wqe(qp, 0);
3932                         }
3933                         break;
3934                 case MLX5_IB_QPT_REG_UMR:
3935                         if (wr->opcode != MLX5_IB_WR_UMR) {
3936                                 err = -EINVAL;
3937                                 mlx5_ib_warn(dev, "bad opcode\n");
3938                                 goto out;
3939                         }
3940                         qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
3941                         ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
3942                         set_reg_umr_segment(seg, wr);
3943                         seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3944                         size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3945                         if (unlikely((seg == qend)))
3946                                 seg = mlx5_get_send_wqe(qp, 0);
3947                         set_reg_mkey_segment(seg, wr);
3948                         seg += sizeof(struct mlx5_mkey_seg);
3949                         size += sizeof(struct mlx5_mkey_seg) / 16;
3950                         if (unlikely((seg == qend)))
3951                                 seg = mlx5_get_send_wqe(qp, 0);
3952                         break;
3953
3954                 default:
3955                         break;
3956                 }
3957
3958                 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
3959                         int uninitialized_var(sz);
3960
3961                         err = set_data_inl_seg(qp, wr, seg, &sz);
3962                         if (unlikely(err)) {
3963                                 mlx5_ib_warn(dev, "\n");
3964                                 *bad_wr = wr;
3965                                 goto out;
3966                         }
3967                         inl = 1;
3968                         size += sz;
3969                 } else {
3970                         dpseg = seg;
3971                         for (i = 0; i < num_sge; i++) {
3972                                 if (unlikely(dpseg == qend)) {
3973                                         seg = mlx5_get_send_wqe(qp, 0);
3974                                         dpseg = seg;
3975                                 }
3976                                 if (likely(wr->sg_list[i].length)) {
3977                                         set_data_ptr_seg(dpseg, wr->sg_list + i);
3978                                         size += sizeof(struct mlx5_wqe_data_seg) / 16;
3979                                         dpseg++;
3980                                 }
3981                         }
3982                 }
3983
3984                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
3985                            get_fence(fence, wr), next_fence,
3986                            mlx5_ib_opcode[wr->opcode]);
3987 skip_psv:
3988                 if (0)
3989                         dump_wqe(qp, idx, size);
3990         }
3991
3992 out:
3993         if (likely(nreq)) {
3994                 qp->sq.head += nreq;
3995
3996                 /* Make sure that descriptors are written before
3997                  * updating doorbell record and ringing the doorbell
3998                  */
3999                 wmb();
4000
4001                 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4002
4003                 /* Make sure doorbell record is visible to the HCA before
4004                  * we hit doorbell */
4005                 wmb();
4006
4007                 if (bf->need_lock)
4008                         spin_lock(&bf->lock);
4009                 else
4010                         __acquire(&bf->lock);
4011
4012                 /* TBD enable WC */
4013                 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) {
4014                         mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp);
4015                         /* wc_wmb(); */
4016                 } else {
4017                         mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset,
4018                                      MLX5_GET_DOORBELL_LOCK(&bf->lock32));
4019                         /* Make sure doorbells don't leak out of SQ spinlock
4020                          * and reach the HCA out of order.
4021                          */
4022                         mmiowb();
4023                 }
4024                 bf->offset ^= bf->buf_size;
4025                 if (bf->need_lock)
4026                         spin_unlock(&bf->lock);
4027                 else
4028                         __release(&bf->lock);
4029         }
4030
4031         spin_unlock_irqrestore(&qp->sq.lock, flags);
4032
4033         return err;
4034 }
4035
4036 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4037 {
4038         sig->signature = calc_sig(sig, size);
4039 }
4040
4041 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4042                       struct ib_recv_wr **bad_wr)
4043 {
4044         struct mlx5_ib_qp *qp = to_mqp(ibqp);
4045         struct mlx5_wqe_data_seg *scat;
4046         struct mlx5_rwqe_sig *sig;
4047         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4048         struct mlx5_core_dev *mdev = dev->mdev;
4049         unsigned long flags;
4050         int err = 0;
4051         int nreq;
4052         int ind;
4053         int i;
4054
4055         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4056                 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4057
4058         spin_lock_irqsave(&qp->rq.lock, flags);
4059
4060         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4061                 err = -EIO;
4062                 *bad_wr = wr;
4063                 nreq = 0;
4064                 goto out;
4065         }
4066
4067         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4068
4069         for (nreq = 0; wr; nreq++, wr = wr->next) {
4070                 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4071                         err = -ENOMEM;
4072                         *bad_wr = wr;
4073                         goto out;
4074                 }
4075
4076                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4077                         err = -EINVAL;
4078                         *bad_wr = wr;
4079                         goto out;
4080                 }
4081
4082                 scat = get_recv_wqe(qp, ind);
4083                 if (qp->wq_sig)
4084                         scat++;
4085
4086                 for (i = 0; i < wr->num_sge; i++)
4087                         set_data_ptr_seg(scat + i, wr->sg_list + i);
4088
4089                 if (i < qp->rq.max_gs) {
4090                         scat[i].byte_count = 0;
4091                         scat[i].lkey       = cpu_to_be32(MLX5_INVALID_LKEY);
4092                         scat[i].addr       = 0;
4093                 }
4094
4095                 if (qp->wq_sig) {
4096                         sig = (struct mlx5_rwqe_sig *)scat;
4097                         set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4098                 }
4099
4100                 qp->rq.wrid[ind] = wr->wr_id;
4101
4102                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4103         }
4104
4105 out:
4106         if (likely(nreq)) {
4107                 qp->rq.head += nreq;
4108
4109                 /* Make sure that descriptors are written before
4110                  * doorbell record.
4111                  */
4112                 wmb();
4113
4114                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4115         }
4116
4117         spin_unlock_irqrestore(&qp->rq.lock, flags);
4118
4119         return err;
4120 }
4121
4122 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4123 {
4124         switch (mlx5_state) {
4125         case MLX5_QP_STATE_RST:      return IB_QPS_RESET;
4126         case MLX5_QP_STATE_INIT:     return IB_QPS_INIT;
4127         case MLX5_QP_STATE_RTR:      return IB_QPS_RTR;
4128         case MLX5_QP_STATE_RTS:      return IB_QPS_RTS;
4129         case MLX5_QP_STATE_SQ_DRAINING:
4130         case MLX5_QP_STATE_SQD:      return IB_QPS_SQD;
4131         case MLX5_QP_STATE_SQER:     return IB_QPS_SQE;
4132         case MLX5_QP_STATE_ERR:      return IB_QPS_ERR;
4133         default:                     return -1;
4134         }
4135 }
4136
4137 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4138 {
4139         switch (mlx5_mig_state) {
4140         case MLX5_QP_PM_ARMED:          return IB_MIG_ARMED;
4141         case MLX5_QP_PM_REARM:          return IB_MIG_REARM;
4142         case MLX5_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
4143         default: return -1;
4144         }
4145 }
4146
4147 static int to_ib_qp_access_flags(int mlx5_flags)
4148 {
4149         int ib_flags = 0;
4150
4151         if (mlx5_flags & MLX5_QP_BIT_RRE)
4152                 ib_flags |= IB_ACCESS_REMOTE_READ;
4153         if (mlx5_flags & MLX5_QP_BIT_RWE)
4154                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4155         if (mlx5_flags & MLX5_QP_BIT_RAE)
4156                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4157
4158         return ib_flags;
4159 }
4160
4161 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
4162                                 struct mlx5_qp_path *path)
4163 {
4164         struct mlx5_core_dev *dev = ibdev->mdev;
4165
4166         memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
4167         ib_ah_attr->port_num      = path->port;
4168
4169         if (ib_ah_attr->port_num == 0 ||
4170             ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports))
4171                 return;
4172
4173         ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf;
4174
4175         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
4176         ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
4177         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
4178         ib_ah_attr->ah_flags      = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
4179         if (ib_ah_attr->ah_flags) {
4180                 ib_ah_attr->grh.sgid_index = path->mgid_index;
4181                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
4182                 ib_ah_attr->grh.traffic_class =
4183                         (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
4184                 ib_ah_attr->grh.flow_label =
4185                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
4186                 memcpy(ib_ah_attr->grh.dgid.raw,
4187                        path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
4188         }
4189 }
4190
4191 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4192                                         struct mlx5_ib_sq *sq,
4193                                         u8 *sq_state)
4194 {
4195         void *out;
4196         void *sqc;
4197         int inlen;
4198         int err;
4199
4200         inlen = MLX5_ST_SZ_BYTES(query_sq_out);
4201         out = mlx5_vzalloc(inlen);
4202         if (!out)
4203                 return -ENOMEM;
4204
4205         err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4206         if (err)
4207                 goto out;
4208
4209         sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4210         *sq_state = MLX5_GET(sqc, sqc, state);
4211         sq->state = *sq_state;
4212
4213 out:
4214         kvfree(out);
4215         return err;
4216 }
4217
4218 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4219                                         struct mlx5_ib_rq *rq,
4220                                         u8 *rq_state)
4221 {
4222         void *out;
4223         void *rqc;
4224         int inlen;
4225         int err;
4226
4227         inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4228         out = mlx5_vzalloc(inlen);
4229         if (!out)
4230                 return -ENOMEM;
4231
4232         err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4233         if (err)
4234                 goto out;
4235
4236         rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4237         *rq_state = MLX5_GET(rqc, rqc, state);
4238         rq->state = *rq_state;
4239
4240 out:
4241         kvfree(out);
4242         return err;
4243 }
4244
4245 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4246                                   struct mlx5_ib_qp *qp, u8 *qp_state)
4247 {
4248         static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4249                 [MLX5_RQC_STATE_RST] = {
4250                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
4251                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
4252                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE_BAD,
4253                         [MLX5_SQ_STATE_NA]      = IB_QPS_RESET,
4254                 },
4255                 [MLX5_RQC_STATE_RDY] = {
4256                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
4257                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
4258                         [MLX5_SQC_STATE_ERR]    = IB_QPS_SQE,
4259                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE,
4260                 },
4261                 [MLX5_RQC_STATE_ERR] = {
4262                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
4263                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
4264                         [MLX5_SQC_STATE_ERR]    = IB_QPS_ERR,
4265                         [MLX5_SQ_STATE_NA]      = IB_QPS_ERR,
4266                 },
4267                 [MLX5_RQ_STATE_NA] = {
4268                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
4269                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
4270                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE,
4271                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE_BAD,
4272                 },
4273         };
4274
4275         *qp_state = sqrq_trans[rq_state][sq_state];
4276
4277         if (*qp_state == MLX5_QP_STATE_BAD) {
4278                 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4279                      qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4280                      qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4281                 return -EINVAL;
4282         }
4283
4284         if (*qp_state == MLX5_QP_STATE)
4285                 *qp_state = qp->state;
4286
4287         return 0;
4288 }
4289
4290 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4291                                      struct mlx5_ib_qp *qp,
4292                                      u8 *raw_packet_qp_state)
4293 {
4294         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4295         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4296         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4297         int err;
4298         u8 sq_state = MLX5_SQ_STATE_NA;
4299         u8 rq_state = MLX5_RQ_STATE_NA;
4300
4301         if (qp->sq.wqe_cnt) {
4302                 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4303                 if (err)
4304                         return err;
4305         }
4306
4307         if (qp->rq.wqe_cnt) {
4308                 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4309                 if (err)
4310                         return err;
4311         }
4312
4313         return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4314                                       raw_packet_qp_state);
4315 }
4316
4317 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4318                          struct ib_qp_attr *qp_attr)
4319 {
4320         struct mlx5_query_qp_mbox_out *outb;
4321         struct mlx5_qp_context *context;
4322         int mlx5_state;
4323         int err = 0;
4324
4325         outb = kzalloc(sizeof(*outb), GFP_KERNEL);
4326         if (!outb)
4327                 return -ENOMEM;
4328
4329         context = &outb->ctx;
4330         err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
4331                                  sizeof(*outb));
4332         if (err)
4333                 goto out;
4334
4335         mlx5_state = be32_to_cpu(context->flags) >> 28;
4336
4337         qp->state                    = to_ib_qp_state(mlx5_state);
4338         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
4339         qp_attr->path_mig_state      =
4340                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4341         qp_attr->qkey                = be32_to_cpu(context->qkey);
4342         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4343         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
4344         qp_attr->dest_qp_num         = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4345         qp_attr->qp_access_flags     =
4346                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4347
4348         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4349                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4350                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
4351                 qp_attr->alt_pkey_index =
4352                         be16_to_cpu(context->alt_path.pkey_index);
4353                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
4354         }
4355
4356         qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
4357         qp_attr->port_num = context->pri_path.port;
4358
4359         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4360         qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4361
4362         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4363
4364         qp_attr->max_dest_rd_atomic =
4365                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4366         qp_attr->min_rnr_timer      =
4367                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4368         qp_attr->timeout            = context->pri_path.ackto_lt >> 3;
4369         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
4370         qp_attr->rnr_retry          = (be32_to_cpu(context->params1) >> 13) & 0x7;
4371         qp_attr->alt_timeout        = context->alt_path.ackto_lt >> 3;
4372
4373 out:
4374         kfree(outb);
4375         return err;
4376 }
4377
4378 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4379                      int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4380 {
4381         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4382         struct mlx5_ib_qp *qp = to_mqp(ibqp);
4383         int err = 0;
4384         u8 raw_packet_qp_state;
4385
4386         if (ibqp->rwq_ind_tbl)
4387                 return -ENOSYS;
4388
4389         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4390                 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4391                                             qp_init_attr);
4392
4393 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4394         /*
4395          * Wait for any outstanding page faults, in case the user frees memory
4396          * based upon this query's result.
4397          */
4398         flush_workqueue(mlx5_ib_page_fault_wq);
4399 #endif
4400
4401         mutex_lock(&qp->mutex);
4402
4403         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
4404                 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4405                 if (err)
4406                         goto out;
4407                 qp->state = raw_packet_qp_state;
4408                 qp_attr->port_num = 1;
4409         } else {
4410                 err = query_qp_attr(dev, qp, qp_attr);
4411                 if (err)
4412                         goto out;
4413         }
4414
4415         qp_attr->qp_state            = qp->state;
4416         qp_attr->cur_qp_state        = qp_attr->qp_state;
4417         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
4418         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
4419
4420         if (!ibqp->uobject) {
4421                 qp_attr->cap.max_send_wr  = qp->sq.max_post;
4422                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4423                 qp_init_attr->qp_context = ibqp->qp_context;
4424         } else {
4425                 qp_attr->cap.max_send_wr  = 0;
4426                 qp_attr->cap.max_send_sge = 0;
4427         }
4428
4429         qp_init_attr->qp_type = ibqp->qp_type;
4430         qp_init_attr->recv_cq = ibqp->recv_cq;
4431         qp_init_attr->send_cq = ibqp->send_cq;
4432         qp_init_attr->srq = ibqp->srq;
4433         qp_attr->cap.max_inline_data = qp->max_inline_data;
4434
4435         qp_init_attr->cap            = qp_attr->cap;
4436
4437         qp_init_attr->create_flags = 0;
4438         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4439                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4440
4441         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4442                 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4443         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4444                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4445         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4446                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
4447         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4448                 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
4449
4450         qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4451                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4452
4453 out:
4454         mutex_unlock(&qp->mutex);
4455         return err;
4456 }
4457
4458 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4459                                           struct ib_ucontext *context,
4460                                           struct ib_udata *udata)
4461 {
4462         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4463         struct mlx5_ib_xrcd *xrcd;
4464         int err;
4465
4466         if (!MLX5_CAP_GEN(dev->mdev, xrc))
4467                 return ERR_PTR(-ENOSYS);
4468
4469         xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4470         if (!xrcd)
4471                 return ERR_PTR(-ENOMEM);
4472
4473         err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
4474         if (err) {
4475                 kfree(xrcd);
4476                 return ERR_PTR(-ENOMEM);
4477         }
4478
4479         return &xrcd->ibxrcd;
4480 }
4481
4482 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
4483 {
4484         struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4485         u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4486         int err;
4487
4488         err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
4489         if (err) {
4490                 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4491                 return err;
4492         }
4493
4494         kfree(xrcd);
4495
4496         return 0;
4497 }
4498
4499 static int  create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4500                       struct ib_wq_init_attr *init_attr)
4501 {
4502         struct mlx5_ib_dev *dev;
4503         __be64 *rq_pas0;
4504         void *in;
4505         void *rqc;
4506         void *wq;
4507         int inlen;
4508         int err;
4509
4510         dev = to_mdev(pd->device);
4511
4512         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
4513         in = mlx5_vzalloc(inlen);
4514         if (!in)
4515                 return -ENOMEM;
4516
4517         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4518         MLX5_SET(rqc,  rqc, mem_rq_type,
4519                  MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4520         MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4521         MLX5_SET(rqc,  rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4522         MLX5_SET(rqc,  rqc, state, MLX5_RQC_STATE_RST);
4523         MLX5_SET(rqc,  rqc, flush_in_error_en, 1);
4524         wq = MLX5_ADDR_OF(rqc, rqc, wq);
4525         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
4526         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4527         MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4528         MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4529         MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4530         MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4531         MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4532         MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4533         MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4534         rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4535         mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
4536         err = mlx5_core_create_rq(dev->mdev, in, inlen, &rwq->rqn);
4537         kvfree(in);
4538         return err;
4539 }
4540
4541 static int set_user_rq_size(struct mlx5_ib_dev *dev,
4542                             struct ib_wq_init_attr *wq_init_attr,
4543                             struct mlx5_ib_create_wq *ucmd,
4544                             struct mlx5_ib_rwq *rwq)
4545 {
4546         /* Sanity check RQ size before proceeding */
4547         if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4548                 return -EINVAL;
4549
4550         if (!ucmd->rq_wqe_count)
4551                 return -EINVAL;
4552
4553         rwq->wqe_count = ucmd->rq_wqe_count;
4554         rwq->wqe_shift = ucmd->rq_wqe_shift;
4555         rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
4556         rwq->log_rq_stride = rwq->wqe_shift;
4557         rwq->log_rq_size = ilog2(rwq->wqe_count);
4558         return 0;
4559 }
4560
4561 static int prepare_user_rq(struct ib_pd *pd,
4562                            struct ib_wq_init_attr *init_attr,
4563                            struct ib_udata *udata,
4564                            struct mlx5_ib_rwq *rwq)
4565 {
4566         struct mlx5_ib_dev *dev = to_mdev(pd->device);
4567         struct mlx5_ib_create_wq ucmd = {};
4568         int err;
4569         size_t required_cmd_sz;
4570
4571         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4572         if (udata->inlen < required_cmd_sz) {
4573                 mlx5_ib_dbg(dev, "invalid inlen\n");
4574                 return -EINVAL;
4575         }
4576
4577         if (udata->inlen > sizeof(ucmd) &&
4578             !ib_is_udata_cleared(udata, sizeof(ucmd),
4579                                  udata->inlen - sizeof(ucmd))) {
4580                 mlx5_ib_dbg(dev, "inlen is not supported\n");
4581                 return -EOPNOTSUPP;
4582         }
4583
4584         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4585                 mlx5_ib_dbg(dev, "copy failed\n");
4586                 return -EFAULT;
4587         }
4588
4589         if (ucmd.comp_mask) {
4590                 mlx5_ib_dbg(dev, "invalid comp mask\n");
4591                 return -EOPNOTSUPP;
4592         }
4593
4594         if (ucmd.reserved) {
4595                 mlx5_ib_dbg(dev, "invalid reserved\n");
4596                 return -EOPNOTSUPP;
4597         }
4598
4599         err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4600         if (err) {
4601                 mlx5_ib_dbg(dev, "err %d\n", err);
4602                 return err;
4603         }
4604
4605         err = create_user_rq(dev, pd, rwq, &ucmd);
4606         if (err) {
4607                 mlx5_ib_dbg(dev, "err %d\n", err);
4608                 if (err)
4609                         return err;
4610         }
4611
4612         rwq->user_index = ucmd.user_index;
4613         return 0;
4614 }
4615
4616 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4617                                 struct ib_wq_init_attr *init_attr,
4618                                 struct ib_udata *udata)
4619 {
4620         struct mlx5_ib_dev *dev;
4621         struct mlx5_ib_rwq *rwq;
4622         struct mlx5_ib_create_wq_resp resp = {};
4623         size_t min_resp_len;
4624         int err;
4625
4626         if (!udata)
4627                 return ERR_PTR(-ENOSYS);
4628
4629         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4630         if (udata->outlen && udata->outlen < min_resp_len)
4631                 return ERR_PTR(-EINVAL);
4632
4633         dev = to_mdev(pd->device);
4634         switch (init_attr->wq_type) {
4635         case IB_WQT_RQ:
4636                 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
4637                 if (!rwq)
4638                         return ERR_PTR(-ENOMEM);
4639                 err = prepare_user_rq(pd, init_attr, udata, rwq);
4640                 if (err)
4641                         goto err;
4642                 err = create_rq(rwq, pd, init_attr);
4643                 if (err)
4644                         goto err_user_rq;
4645                 break;
4646         default:
4647                 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
4648                             init_attr->wq_type);
4649                 return ERR_PTR(-EINVAL);
4650         }
4651
4652         rwq->ibwq.wq_num = rwq->rqn;
4653         rwq->ibwq.state = IB_WQS_RESET;
4654         if (udata->outlen) {
4655                 resp.response_length = offsetof(typeof(resp), response_length) +
4656                                 sizeof(resp.response_length);
4657                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4658                 if (err)
4659                         goto err_copy;
4660         }
4661
4662         return &rwq->ibwq;
4663
4664 err_copy:
4665         mlx5_core_destroy_rq(dev->mdev, rwq->rqn);
4666 err_user_rq:
4667         destroy_user_rq(pd, rwq);
4668 err:
4669         kfree(rwq);
4670         return ERR_PTR(err);
4671 }
4672
4673 int mlx5_ib_destroy_wq(struct ib_wq *wq)
4674 {
4675         struct mlx5_ib_dev *dev = to_mdev(wq->device);
4676         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4677
4678         mlx5_core_destroy_rq(dev->mdev, rwq->rqn);
4679         destroy_user_rq(wq->pd, rwq);
4680         kfree(rwq);
4681
4682         return 0;
4683 }
4684
4685 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
4686                                                       struct ib_rwq_ind_table_init_attr *init_attr,
4687                                                       struct ib_udata *udata)
4688 {
4689         struct mlx5_ib_dev *dev = to_mdev(device);
4690         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
4691         int sz = 1 << init_attr->log_ind_tbl_size;
4692         struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
4693         size_t min_resp_len;
4694         int inlen;
4695         int err;
4696         int i;
4697         u32 *in;
4698         void *rqtc;
4699
4700         if (udata->inlen > 0 &&
4701             !ib_is_udata_cleared(udata, 0,
4702                                  udata->inlen))
4703                 return ERR_PTR(-EOPNOTSUPP);
4704
4705         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4706         if (udata->outlen && udata->outlen < min_resp_len)
4707                 return ERR_PTR(-EINVAL);
4708
4709         rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
4710         if (!rwq_ind_tbl)
4711                 return ERR_PTR(-ENOMEM);
4712
4713         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
4714         in = mlx5_vzalloc(inlen);
4715         if (!in) {
4716                 err = -ENOMEM;
4717                 goto err;
4718         }
4719
4720         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
4721
4722         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
4723         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
4724
4725         for (i = 0; i < sz; i++)
4726                 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
4727
4728         err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
4729         kvfree(in);
4730
4731         if (err)
4732                 goto err;
4733
4734         rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
4735         if (udata->outlen) {
4736                 resp.response_length = offsetof(typeof(resp), response_length) +
4737                                         sizeof(resp.response_length);
4738                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4739                 if (err)
4740                         goto err_copy;
4741         }
4742
4743         return &rwq_ind_tbl->ib_rwq_ind_tbl;
4744
4745 err_copy:
4746         mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4747 err:
4748         kfree(rwq_ind_tbl);
4749         return ERR_PTR(err);
4750 }
4751
4752 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4753 {
4754         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
4755         struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
4756
4757         mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4758
4759         kfree(rwq_ind_tbl);
4760         return 0;
4761 }
4762
4763 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
4764                       u32 wq_attr_mask, struct ib_udata *udata)
4765 {
4766         struct mlx5_ib_dev *dev = to_mdev(wq->device);
4767         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4768         struct mlx5_ib_modify_wq ucmd = {};
4769         size_t required_cmd_sz;
4770         int curr_wq_state;
4771         int wq_state;
4772         int inlen;
4773         int err;
4774         void *rqc;
4775         void *in;
4776
4777         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4778         if (udata->inlen < required_cmd_sz)
4779                 return -EINVAL;
4780
4781         if (udata->inlen > sizeof(ucmd) &&
4782             !ib_is_udata_cleared(udata, sizeof(ucmd),
4783                                  udata->inlen - sizeof(ucmd)))
4784                 return -EOPNOTSUPP;
4785
4786         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4787                 return -EFAULT;
4788
4789         if (ucmd.comp_mask || ucmd.reserved)
4790                 return -EOPNOTSUPP;
4791
4792         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
4793         in = mlx5_vzalloc(inlen);
4794         if (!in)
4795                 return -ENOMEM;
4796
4797         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
4798
4799         curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
4800                 wq_attr->curr_wq_state : wq->state;
4801         wq_state = (wq_attr_mask & IB_WQ_STATE) ?
4802                 wq_attr->wq_state : curr_wq_state;
4803         if (curr_wq_state == IB_WQS_ERR)
4804                 curr_wq_state = MLX5_RQC_STATE_ERR;
4805         if (wq_state == IB_WQS_ERR)
4806                 wq_state = MLX5_RQC_STATE_ERR;
4807         MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
4808         MLX5_SET(rqc, rqc, state, wq_state);
4809
4810         err = mlx5_core_modify_rq(dev->mdev, rwq->rqn, in, inlen);
4811         kvfree(in);
4812         if (!err)
4813                 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
4814
4815         return err;
4816 }