drivers/infiniband/hw/qedr/main.c

   1 /* QLogic qedr NIC Driver
   2  * Copyright (c) 2015-2016  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #include <linux/module.h>
  33 #include <rdma/ib_verbs.h>
  34 #include <rdma/ib_addr.h>
  35 #include <rdma/ib_user_verbs.h>
  36 #include <linux/netdevice.h>
  37 #include <linux/iommu.h>
  38 #include <net/addrconf.h>
  39 #include <linux/qed/qede_roce.h>
  40 #include <linux/qed/qed_chain.h>
  41 #include <linux/qed/qed_if.h>
  42 #include "qedr.h"
  43 #include "verbs.h"
  44 #include <rdma/qedr-abi.h>
  45
  46 MODULE_DESCRIPTION("QLogic 40G/100G ROCE Driver");
  47 MODULE_AUTHOR("QLogic Corporation");
  48 MODULE_LICENSE("Dual BSD/GPL");
  49 MODULE_VERSION(QEDR_MODULE_VERSION);
  50
  51 void qedr_ib_dispatch_event(struct qedr_dev *dev, u8 port_num,
  52                             enum ib_event_type type)
  53 {
  54         struct ib_event ibev;
  55
  56         ibev.device = &dev->ibdev;
  57         ibev.element.port_num = port_num;
  58         ibev.event = type;
  59
  60         ib_dispatch_event(&ibev);
  61 }
  62
  63 static enum rdma_link_layer qedr_link_layer(struct ib_device *device,
  64                                             u8 port_num)
  65 {
  66         return IB_LINK_LAYER_ETHERNET;
  67 }
  68
  69 static void qedr_get_dev_fw_str(struct ib_device *ibdev, char *str,
  70                                 size_t str_len)
  71 {
  72         struct qedr_dev *qedr = get_qedr_dev(ibdev);
  73         u32 fw_ver = (u32)qedr->attr.fw_ver;
  74
  75         snprintf(str, str_len, "%d. %d. %d. %d",
  76                  (fw_ver >> 24) & 0xFF, (fw_ver >> 16) & 0xFF,
  77                  (fw_ver >> 8) & 0xFF, fw_ver & 0xFF);
  78 }
  79
  80 static int qedr_register_device(struct qedr_dev *dev)
  81 {
  82         strlcpy(dev->ibdev.name, "qedr%d", IB_DEVICE_NAME_MAX);
  83
  84         memcpy(dev->ibdev.node_desc, QEDR_NODE_DESC, sizeof(QEDR_NODE_DESC));
  85         dev->ibdev.owner = THIS_MODULE;
  86         dev->ibdev.uverbs_abi_ver = QEDR_ABI_VERSION;
  87
  88         dev->ibdev.uverbs_cmd_mask = QEDR_UVERBS(GET_CONTEXT) |
  89                                      QEDR_UVERBS(QUERY_DEVICE) |
  90                                      QEDR_UVERBS(QUERY_PORT) |
  91                                      QEDR_UVERBS(ALLOC_PD) |
  92                                      QEDR_UVERBS(DEALLOC_PD) |
  93                                      QEDR_UVERBS(CREATE_COMP_CHANNEL) |
  94                                      QEDR_UVERBS(CREATE_CQ) |
  95                                      QEDR_UVERBS(RESIZE_CQ) |
  96                                      QEDR_UVERBS(DESTROY_CQ) |
  97                                      QEDR_UVERBS(REQ_NOTIFY_CQ);
  98
  99         dev->ibdev.phys_port_cnt = 1;
 100         dev->ibdev.num_comp_vectors = dev->num_cnq;
 101         dev->ibdev.node_type = RDMA_NODE_IB_CA;
 102
 103         dev->ibdev.query_device = qedr_query_device;
 104         dev->ibdev.query_port = qedr_query_port;
 105         dev->ibdev.modify_port = qedr_modify_port;
 106
 107         dev->ibdev.query_gid = qedr_query_gid;
 108         dev->ibdev.add_gid = qedr_add_gid;
 109         dev->ibdev.del_gid = qedr_del_gid;
 110
 111         dev->ibdev.alloc_ucontext = qedr_alloc_ucontext;
 112         dev->ibdev.dealloc_ucontext = qedr_dealloc_ucontext;
 113         dev->ibdev.mmap = qedr_mmap;
 114
 115         dev->ibdev.alloc_pd = qedr_alloc_pd;
 116         dev->ibdev.dealloc_pd = qedr_dealloc_pd;
 117
 118         dev->ibdev.create_cq = qedr_create_cq;
 119         dev->ibdev.destroy_cq = qedr_destroy_cq;
 120         dev->ibdev.resize_cq = qedr_resize_cq;
 121         dev->ibdev.req_notify_cq = qedr_arm_cq;
 122
 123         dev->ibdev.query_pkey = qedr_query_pkey;
 124
 125         dev->ibdev.dma_device = &dev->pdev->dev;
 126
 127         dev->ibdev.get_link_layer = qedr_link_layer;
 128         dev->ibdev.get_dev_fw_str = qedr_get_dev_fw_str;
 129
 130         return 0;
 131 }
 132
 133 /* This function allocates fast-path status block memory */
 134 static int qedr_alloc_mem_sb(struct qedr_dev *dev,
 135                              struct qed_sb_info *sb_info, u16 sb_id)
 136 {
 137         struct status_block *sb_virt;
 138         dma_addr_t sb_phys;
 139         int rc;
 140
 141         sb_virt = dma_alloc_coherent(&dev->pdev->dev,
 142                                      sizeof(*sb_virt), &sb_phys, GFP_KERNEL);
 143         if (!sb_virt)
 144                 return -ENOMEM;
 145
 146         rc = dev->ops->common->sb_init(dev->cdev, sb_info,
 147                                        sb_virt, sb_phys, sb_id,
 148                                        QED_SB_TYPE_CNQ);
 149         if (rc) {
 150                 pr_err("Status block initialization failed\n");
 151                 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_virt),
 152                                   sb_virt, sb_phys);
 153                 return rc;
 154         }
 155
 156         return 0;
 157 }
 158
 159 static void qedr_free_mem_sb(struct qedr_dev *dev,
 160                              struct qed_sb_info *sb_info, int sb_id)
 161 {
 162         if (sb_info->sb_virt) {
 163                 dev->ops->common->sb_release(dev->cdev, sb_info, sb_id);
 164                 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_info->sb_virt),
 165                                   (void *)sb_info->sb_virt, sb_info->sb_phys);
 166         }
 167 }
 168
 169 static void qedr_free_resources(struct qedr_dev *dev)
 170 {
 171         int i;
 172
 173         for (i = 0; i < dev->num_cnq; i++) {
 174                 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
 175                 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
 176         }
 177
 178         kfree(dev->cnq_array);
 179         kfree(dev->sb_array);
 180         kfree(dev->sgid_tbl);
 181 }
 182
 183 static int qedr_alloc_resources(struct qedr_dev *dev)
 184 {
 185         struct qedr_cnq *cnq;
 186         __le16 *cons_pi;
 187         u16 n_entries;
 188         int i, rc;
 189
 190         dev->sgid_tbl = kzalloc(sizeof(union ib_gid) *
 191                                 QEDR_MAX_SGID, GFP_KERNEL);
 192         if (!dev->sgid_tbl)
 193                 return -ENOMEM;
 194
 195         spin_lock_init(&dev->sgid_lock);
 196
 197         /* Allocate Status blocks for CNQ */
 198         dev->sb_array = kcalloc(dev->num_cnq, sizeof(*dev->sb_array),
 199                                 GFP_KERNEL);
 200         if (!dev->sb_array) {
 201                 rc = -ENOMEM;
 202                 goto err1;
 203         }
 204
 205         dev->cnq_array = kcalloc(dev->num_cnq,
 206                                  sizeof(*dev->cnq_array), GFP_KERNEL);
 207         if (!dev->cnq_array) {
 208                 rc = -ENOMEM;
 209                 goto err2;
 210         }
 211
 212         dev->sb_start = dev->ops->rdma_get_start_sb(dev->cdev);
 213
 214         /* Allocate CNQ PBLs */
 215         n_entries = min_t(u32, QED_RDMA_MAX_CNQ_SIZE, QEDR_ROCE_MAX_CNQ_SIZE);
 216         for (i = 0; i < dev->num_cnq; i++) {
 217                 cnq = &dev->cnq_array[i];
 218
 219                 rc = qedr_alloc_mem_sb(dev, &dev->sb_array[i],
 220                                        dev->sb_start + i);
 221                 if (rc)
 222                         goto err3;
 223
 224                 rc = dev->ops->common->chain_alloc(dev->cdev,
 225                                                    QED_CHAIN_USE_TO_CONSUME,
 226                                                    QED_CHAIN_MODE_PBL,
 227                                                    QED_CHAIN_CNT_TYPE_U16,
 228                                                    n_entries,
 229                                                    sizeof(struct regpair *),
 230                                                    &cnq->pbl);
 231                 if (rc)
 232                         goto err4;
 233
 234                 cnq->dev = dev;
 235                 cnq->sb = &dev->sb_array[i];
 236                 cons_pi = dev->sb_array[i].sb_virt->pi_array;
 237                 cnq->hw_cons_ptr = &cons_pi[QED_ROCE_PROTOCOL_INDEX];
 238                 cnq->index = i;
 239                 sprintf(cnq->name, "qedr%d@pci:%s", i, pci_name(dev->pdev));
 240
 241                 DP_DEBUG(dev, QEDR_MSG_INIT, "cnq[%d].cons=%d\n",
 242                          i, qed_chain_get_cons_idx(&cnq->pbl));
 243         }
 244
 245         return 0;
 246 err4:
 247         qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
 248 err3:
 249         for (--i; i >= 0; i--) {
 250                 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
 251                 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
 252         }
 253         kfree(dev->cnq_array);
 254 err2:
 255         kfree(dev->sb_array);
 256 err1:
 257         kfree(dev->sgid_tbl);
 258         return rc;
 259 }
 260
 261 /* QEDR sysfs interface */
 262 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
 263                         char *buf)
 264 {
 265         struct qedr_dev *dev = dev_get_drvdata(device);
 266
 267         return scnprintf(buf, PAGE_SIZE, "0x%x\n", dev->pdev->vendor);
 268 }
 269
 270 static ssize_t show_hca_type(struct device *device,
 271                              struct device_attribute *attr, char *buf)
 272 {
 273         return scnprintf(buf, PAGE_SIZE, "%s\n", "HCA_TYPE_TO_SET");
 274 }
 275
 276 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
 277 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca_type, NULL);
 278
 279 static struct device_attribute *qedr_attributes[] = {
 280         &dev_attr_hw_rev,
 281         &dev_attr_hca_type
 282 };
 283
 284 static void qedr_remove_sysfiles(struct qedr_dev *dev)
 285 {
 286         int i;
 287
 288         for (i = 0; i < ARRAY_SIZE(qedr_attributes); i++)
 289                 device_remove_file(&dev->ibdev.dev, qedr_attributes[i]);
 290 }
 291
 292 static void qedr_pci_set_atomic(struct qedr_dev *dev, struct pci_dev *pdev)
 293 {
 294         struct pci_dev *bridge;
 295         u32 val;
 296
 297         dev->atomic_cap = IB_ATOMIC_NONE;
 298
 299         bridge = pdev->bus->self;
 300         if (!bridge)
 301                 return;
 302
 303         /* Check whether we are connected directly or via a switch */
 304         while (bridge && bridge->bus->parent) {
 305                 DP_DEBUG(dev, QEDR_MSG_INIT,
 306                          "Device is not connected directly to root. bridge->bus->number=%d primary=%d\n",
 307                          bridge->bus->number, bridge->bus->primary);
 308                 /* Need to check Atomic Op Routing Supported all the way to
 309                  * root complex.
 310                  */
 311                 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &val);
 312                 if (!(val & PCI_EXP_DEVCAP2_ATOMIC_ROUTE)) {
 313                         pcie_capability_clear_word(pdev,
 314                                                    PCI_EXP_DEVCTL2,
 315                                                    PCI_EXP_DEVCTL2_ATOMIC_REQ);
 316                         return;
 317                 }
 318                 bridge = bridge->bus->parent->self;
 319         }
 320         bridge = pdev->bus->self;
 321
 322         /* according to bridge capability */
 323         pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &val);
 324         if (val & PCI_EXP_DEVCAP2_ATOMIC_COMP64) {
 325                 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2,
 326                                          PCI_EXP_DEVCTL2_ATOMIC_REQ);
 327                 dev->atomic_cap = IB_ATOMIC_GLOB;
 328         } else {
 329                 pcie_capability_clear_word(pdev, PCI_EXP_DEVCTL2,
 330                                            PCI_EXP_DEVCTL2_ATOMIC_REQ);
 331         }
 332 }
 333
 334 static const struct qed_rdma_ops *qed_ops;
 335
 336 #define HILO_U64(hi, lo)                ((((u64)(hi)) << 32) + (lo))
 337
 338 static irqreturn_t qedr_irq_handler(int irq, void *handle)
 339 {
 340         u16 hw_comp_cons, sw_comp_cons;
 341         struct qedr_cnq *cnq = handle;
 342         struct regpair *cq_handle;
 343         struct qedr_cq *cq;
 344
 345         qed_sb_ack(cnq->sb, IGU_INT_DISABLE, 0);
 346
 347         qed_sb_update_sb_idx(cnq->sb);
 348
 349         hw_comp_cons = le16_to_cpu(*cnq->hw_cons_ptr);
 350         sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
 351
 352         /* Align protocol-index and chain reads */
 353         rmb();
 354
 355         while (sw_comp_cons != hw_comp_cons) {
 356                 cq_handle = (struct regpair *)qed_chain_consume(&cnq->pbl);
 357                 cq = (struct qedr_cq *)(uintptr_t)HILO_U64(cq_handle->hi,
 358                                 cq_handle->lo);
 359
 360                 if (cq == NULL) {
 361                         DP_ERR(cnq->dev,
 362                                "Received NULL CQ cq_handle->hi=%d cq_handle->lo=%d sw_comp_cons=%d hw_comp_cons=%d\n",
 363                                cq_handle->hi, cq_handle->lo, sw_comp_cons,
 364                                hw_comp_cons);
 365
 366                         break;
 367                 }
 368
 369                 if (cq->sig != QEDR_CQ_MAGIC_NUMBER) {
 370                         DP_ERR(cnq->dev,
 371                                "Problem with cq signature, cq_handle->hi=%d ch_handle->lo=%d cq=%p\n",
 372                                cq_handle->hi, cq_handle->lo, cq);
 373                         break;
 374                 }
 375
 376                 cq->arm_flags = 0;
 377
 378                 if (cq->ibcq.comp_handler)
 379                         (*cq->ibcq.comp_handler)
 380                                 (&cq->ibcq, cq->ibcq.cq_context);
 381
 382                 sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
 383
 384                 cnq->n_comp++;
 385
 386         }
 387
 388         qed_ops->rdma_cnq_prod_update(cnq->dev->rdma_ctx, cnq->index,
 389                                       sw_comp_cons);
 390
 391         qed_sb_ack(cnq->sb, IGU_INT_ENABLE, 1);
 392
 393         return IRQ_HANDLED;
 394 }
 395
 396 static void qedr_sync_free_irqs(struct qedr_dev *dev)
 397 {
 398         u32 vector;
 399         int i;
 400
 401         for (i = 0; i < dev->int_info.used_cnt; i++) {
 402                 if (dev->int_info.msix_cnt) {
 403                         vector = dev->int_info.msix[i * dev->num_hwfns].vector;
 404                         synchronize_irq(vector);
 405                         free_irq(vector, &dev->cnq_array[i]);
 406                 }
 407         }
 408
 409         dev->int_info.used_cnt = 0;
 410 }
 411
 412 static int qedr_req_msix_irqs(struct qedr_dev *dev)
 413 {
 414         int i, rc = 0;
 415
 416         if (dev->num_cnq > dev->int_info.msix_cnt) {
 417                 DP_ERR(dev,
 418                        "Interrupt mismatch: %d CNQ queues > %d MSI-x vectors\n",
 419                        dev->num_cnq, dev->int_info.msix_cnt);
 420                 return -EINVAL;
 421         }
 422
 423         for (i = 0; i < dev->num_cnq; i++) {
 424                 rc = request_irq(dev->int_info.msix[i * dev->num_hwfns].vector,
 425                                  qedr_irq_handler, 0, dev->cnq_array[i].name,
 426                                  &dev->cnq_array[i]);
 427                 if (rc) {
 428                         DP_ERR(dev, "Request cnq %d irq failed\n", i);
 429                         qedr_sync_free_irqs(dev);
 430                 } else {
 431                         DP_DEBUG(dev, QEDR_MSG_INIT,
 432                                  "Requested cnq irq for %s [entry %d]. Cookie is at %p\n",
 433                                  dev->cnq_array[i].name, i,
 434                                  &dev->cnq_array[i]);
 435                         dev->int_info.used_cnt++;
 436                 }
 437         }
 438
 439         return rc;
 440 }
 441
 442 static int qedr_setup_irqs(struct qedr_dev *dev)
 443 {
 444         int rc;
 445
 446         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs\n");
 447
 448         /* Learn Interrupt configuration */
 449         rc = dev->ops->rdma_set_rdma_int(dev->cdev, dev->num_cnq);
 450         if (rc < 0)
 451                 return rc;
 452
 453         rc = dev->ops->rdma_get_rdma_int(dev->cdev, &dev->int_info);
 454         if (rc) {
 455                 DP_DEBUG(dev, QEDR_MSG_INIT, "get_rdma_int failed\n");
 456                 return rc;
 457         }
 458
 459         if (dev->int_info.msix_cnt) {
 460                 DP_DEBUG(dev, QEDR_MSG_INIT, "rdma msix_cnt = %d\n",
 461                          dev->int_info.msix_cnt);
 462                 rc = qedr_req_msix_irqs(dev);
 463                 if (rc)
 464                         return rc;
 465         }
 466
 467         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs succeeded\n");
 468
 469         return 0;
 470 }
 471
 472 static int qedr_set_device_attr(struct qedr_dev *dev)
 473 {
 474         struct qed_rdma_device *qed_attr;
 475         struct qedr_device_attr *attr;
 476         u32 page_size;
 477
 478         /* Part 1 - query core capabilities */
 479         qed_attr = dev->ops->rdma_query_device(dev->rdma_ctx);
 480
 481         /* Part 2 - check capabilities */
 482         page_size = ~dev->attr.page_size_caps + 1;
 483         if (page_size > PAGE_SIZE) {
 484                 DP_ERR(dev,
 485                        "Kernel PAGE_SIZE is %ld which is smaller than minimum page size (%d) required by qedr\n",
 486                        PAGE_SIZE, page_size);
 487                 return -ENODEV;
 488         }
 489
 490         /* Part 3 - copy and update capabilities */
 491         attr = &dev->attr;
 492         attr->vendor_id = qed_attr->vendor_id;
 493         attr->vendor_part_id = qed_attr->vendor_part_id;
 494         attr->hw_ver = qed_attr->hw_ver;
 495         attr->fw_ver = qed_attr->fw_ver;
 496         attr->node_guid = qed_attr->node_guid;
 497         attr->sys_image_guid = qed_attr->sys_image_guid;
 498         attr->max_cnq = qed_attr->max_cnq;
 499         attr->max_sge = qed_attr->max_sge;
 500         attr->max_inline = qed_attr->max_inline;
 501         attr->max_sqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_SQE);
 502         attr->max_rqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_RQE);
 503         attr->max_qp_resp_rd_atomic_resc = qed_attr->max_qp_resp_rd_atomic_resc;
 504         attr->max_qp_req_rd_atomic_resc = qed_attr->max_qp_req_rd_atomic_resc;
 505         attr->max_dev_resp_rd_atomic_resc =
 506             qed_attr->max_dev_resp_rd_atomic_resc;
 507         attr->max_cq = qed_attr->max_cq;
 508         attr->max_qp = qed_attr->max_qp;
 509         attr->max_mr = qed_attr->max_mr;
 510         attr->max_mr_size = qed_attr->max_mr_size;
 511         attr->max_cqe = min_t(u64, qed_attr->max_cqe, QEDR_MAX_CQES);
 512         attr->max_mw = qed_attr->max_mw;
 513         attr->max_fmr = qed_attr->max_fmr;
 514         attr->max_mr_mw_fmr_pbl = qed_attr->max_mr_mw_fmr_pbl;
 515         attr->max_mr_mw_fmr_size = qed_attr->max_mr_mw_fmr_size;
 516         attr->max_pd = qed_attr->max_pd;
 517         attr->max_ah = qed_attr->max_ah;
 518         attr->max_pkey = qed_attr->max_pkey;
 519         attr->max_srq = qed_attr->max_srq;
 520         attr->max_srq_wr = qed_attr->max_srq_wr;
 521         attr->dev_caps = qed_attr->dev_caps;
 522         attr->page_size_caps = qed_attr->page_size_caps;
 523         attr->dev_ack_delay = qed_attr->dev_ack_delay;
 524         attr->reserved_lkey = qed_attr->reserved_lkey;
 525         attr->bad_pkey_counter = qed_attr->bad_pkey_counter;
 526         attr->max_stats_queues = qed_attr->max_stats_queues;
 527
 528         return 0;
 529 }
 530
 531 static int qedr_init_hw(struct qedr_dev *dev)
 532 {
 533         struct qed_rdma_add_user_out_params out_params;
 534         struct qed_rdma_start_in_params *in_params;
 535         struct qed_rdma_cnq_params *cur_pbl;
 536         struct qed_rdma_events events;
 537         dma_addr_t p_phys_table;
 538         u32 page_cnt;
 539         int rc = 0;
 540         int i;
 541
 542         in_params =  kzalloc(sizeof(*in_params), GFP_KERNEL);
 543         if (!in_params) {
 544                 rc = -ENOMEM;
 545                 goto out;
 546         }
 547
 548         in_params->desired_cnq = dev->num_cnq;
 549         for (i = 0; i < dev->num_cnq; i++) {
 550                 cur_pbl = &in_params->cnq_pbl_list[i];
 551
 552                 page_cnt = qed_chain_get_page_cnt(&dev->cnq_array[i].pbl);
 553                 cur_pbl->num_pbl_pages = page_cnt;
 554
 555                 p_phys_table = qed_chain_get_pbl_phys(&dev->cnq_array[i].pbl);
 556                 cur_pbl->pbl_ptr = (u64)p_phys_table;
 557         }
 558
 559         events.context = dev;
 560
 561         in_params->events = &events;
 562         in_params->cq_mode = QED_RDMA_CQ_MODE_32_BITS;
 563         in_params->max_mtu = dev->ndev->mtu;
 564         ether_addr_copy(&in_params->mac_addr[0], dev->ndev->dev_addr);
 565
 566         rc = dev->ops->rdma_init(dev->cdev, in_params);
 567         if (rc)
 568                 goto out;
 569
 570         rc = dev->ops->rdma_add_user(dev->rdma_ctx, &out_params);
 571         if (rc)
 572                 goto out;
 573
 574         dev->db_addr = (void *)(uintptr_t)out_params.dpi_addr;
 575         dev->db_phys_addr = out_params.dpi_phys_addr;
 576         dev->db_size = out_params.dpi_size;
 577         dev->dpi = out_params.dpi;
 578
 579         rc = qedr_set_device_attr(dev);
 580 out:
 581         kfree(in_params);
 582         if (rc)
 583                 DP_ERR(dev, "Init HW Failed rc = %d\n", rc);
 584
 585         return rc;
 586 }
 587
 588 void qedr_stop_hw(struct qedr_dev *dev)
 589 {
 590         dev->ops->rdma_remove_user(dev->rdma_ctx, dev->dpi);
 591         dev->ops->rdma_stop(dev->rdma_ctx);
 592 }
 593
 594 static struct qedr_dev *qedr_add(struct qed_dev *cdev, struct pci_dev *pdev,
 595                                  struct net_device *ndev)
 596 {
 597         struct qed_dev_rdma_info dev_info;
 598         struct qedr_dev *dev;
 599         int rc = 0, i;
 600
 601         dev = (struct qedr_dev *)ib_alloc_device(sizeof(*dev));
 602         if (!dev) {
 603                 pr_err("Unable to allocate ib device\n");
 604                 return NULL;
 605         }
 606
 607         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr add device called\n");
 608
 609         dev->pdev = pdev;
 610         dev->ndev = ndev;
 611         dev->cdev = cdev;
 612
 613         qed_ops = qed_get_rdma_ops();
 614         if (!qed_ops) {
 615                 DP_ERR(dev, "Failed to get qed roce operations\n");
 616                 goto init_err;
 617         }
 618
 619         dev->ops = qed_ops;
 620         rc = qed_ops->fill_dev_info(cdev, &dev_info);
 621         if (rc)
 622                 goto init_err;
 623
 624         dev->num_hwfns = dev_info.common.num_hwfns;
 625         dev->rdma_ctx = dev->ops->rdma_get_rdma_ctx(cdev);
 626
 627         dev->num_cnq = dev->ops->rdma_get_min_cnq_msix(cdev);
 628         if (!dev->num_cnq) {
 629                 DP_ERR(dev, "not enough CNQ resources.\n");
 630                 goto init_err;
 631         }
 632
 633         qedr_pci_set_atomic(dev, pdev);
 634
 635         rc = qedr_alloc_resources(dev);
 636         if (rc)
 637                 goto init_err;
 638
 639         rc = qedr_init_hw(dev);
 640         if (rc)
 641                 goto alloc_err;
 642
 643         rc = qedr_setup_irqs(dev);
 644         if (rc)
 645                 goto irq_err;
 646
 647         rc = qedr_register_device(dev);
 648         if (rc) {
 649                 DP_ERR(dev, "Unable to allocate register device\n");
 650                 goto reg_err;
 651         }
 652
 653         for (i = 0; i < ARRAY_SIZE(qedr_attributes); i++)
 654                 if (device_create_file(&dev->ibdev.dev, qedr_attributes[i]))
 655                         goto reg_err;
 656
 657         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr driver loaded successfully\n");
 658         return dev;
 659
 660 reg_err:
 661         qedr_sync_free_irqs(dev);
 662 irq_err:
 663         qedr_stop_hw(dev);
 664 alloc_err:
 665         qedr_free_resources(dev);
 666 init_err:
 667         ib_dealloc_device(&dev->ibdev);
 668         DP_ERR(dev, "qedr driver load failed rc=%d\n", rc);
 669
 670         return NULL;
 671 }
 672
 673 static void qedr_remove(struct qedr_dev *dev)
 674 {
 675         /* First unregister with stack to stop all the active traffic
 676          * of the registered clients.
 677          */
 678         qedr_remove_sysfiles(dev);
 679
 680         qedr_stop_hw(dev);
 681         qedr_sync_free_irqs(dev);
 682         qedr_free_resources(dev);
 683         ib_dealloc_device(&dev->ibdev);
 684 }
 685
 686 static int qedr_close(struct qedr_dev *dev)
 687 {
 688         qedr_ib_dispatch_event(dev, 1, IB_EVENT_PORT_ERR);
 689
 690         return 0;
 691 }
 692
 693 static void qedr_shutdown(struct qedr_dev *dev)
 694 {
 695         qedr_close(dev);
 696         qedr_remove(dev);
 697 }
 698
 699 /* event handling via NIC driver ensures that all the NIC specific
 700  * initialization done before RoCE driver notifies
 701  * event to stack.
 702  */
 703 static void qedr_notify(struct qedr_dev *dev, enum qede_roce_event event)
 704 {
 705         switch (event) {
 706         case QEDE_UP:
 707                 qedr_ib_dispatch_event(dev, 1, IB_EVENT_PORT_ACTIVE);
 708                 break;
 709         case QEDE_DOWN:
 710                 qedr_close(dev);
 711                 break;
 712         case QEDE_CLOSE:
 713                 qedr_shutdown(dev);
 714                 break;
 715         case QEDE_CHANGE_ADDR:
 716                 qedr_ib_dispatch_event(dev, 1, IB_EVENT_GID_CHANGE);
 717                 break;
 718         default:
 719                 pr_err("Event not supported\n");
 720         }
 721 }
 722
 723 static struct qedr_driver qedr_drv = {
 724         .name = "qedr_driver",
 725         .add = qedr_add,
 726         .remove = qedr_remove,
 727         .notify = qedr_notify,
 728 };
 729
 730 static int __init qedr_init_module(void)
 731 {
 732         return qede_roce_register_driver(&qedr_drv);
 733 }
 734
 735 static void __exit qedr_exit_module(void)
 736 {
 737         qede_roce_unregister_driver(&qedr_drv);
 738 }
 739
 740 module_init(qedr_init_module);
 741 module_exit(qedr_exit_module);