drivers/infiniband/hw/qedr/main.c

   1 /* QLogic qedr NIC Driver
   2  * Copyright (c) 2015-2016  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #include <linux/module.h>
  33 #include <rdma/ib_verbs.h>
  34 #include <rdma/ib_addr.h>
  35 #include <rdma/ib_user_verbs.h>
  36 #include <linux/netdevice.h>
  37 #include <linux/iommu.h>
  38 #include <net/addrconf.h>
  39 #include <linux/qed/qede_roce.h>
  40 #include <linux/qed/qed_chain.h>
  41 #include <linux/qed/qed_if.h>
  42 #include "qedr.h"
  43 #include "verbs.h"
  44 #include <rdma/qedr-abi.h>
  45
  46 MODULE_DESCRIPTION("QLogic 40G/100G ROCE Driver");
  47 MODULE_AUTHOR("QLogic Corporation");
  48 MODULE_LICENSE("Dual BSD/GPL");
  49 MODULE_VERSION(QEDR_MODULE_VERSION);
  50
  51 #define QEDR_WQ_MULTIPLIER_DFT  (3)
  52
  53 void qedr_ib_dispatch_event(struct qedr_dev *dev, u8 port_num,
  54                             enum ib_event_type type)
  55 {
  56         struct ib_event ibev;
  57
  58         ibev.device = &dev->ibdev;
  59         ibev.element.port_num = port_num;
  60         ibev.event = type;
  61
  62         ib_dispatch_event(&ibev);
  63 }
  64
  65 static enum rdma_link_layer qedr_link_layer(struct ib_device *device,
  66                                             u8 port_num)
  67 {
  68         return IB_LINK_LAYER_ETHERNET;
  69 }
  70
  71 static void qedr_get_dev_fw_str(struct ib_device *ibdev, char *str,
  72                                 size_t str_len)
  73 {
  74         struct qedr_dev *qedr = get_qedr_dev(ibdev);
  75         u32 fw_ver = (u32)qedr->attr.fw_ver;
  76
  77         snprintf(str, str_len, "%d. %d. %d. %d",
  78                  (fw_ver >> 24) & 0xFF, (fw_ver >> 16) & 0xFF,
  79                  (fw_ver >> 8) & 0xFF, fw_ver & 0xFF);
  80 }
  81
  82 static int qedr_register_device(struct qedr_dev *dev)
  83 {
  84         strlcpy(dev->ibdev.name, "qedr%d", IB_DEVICE_NAME_MAX);
  85
  86         memcpy(dev->ibdev.node_desc, QEDR_NODE_DESC, sizeof(QEDR_NODE_DESC));
  87         dev->ibdev.owner = THIS_MODULE;
  88         dev->ibdev.uverbs_abi_ver = QEDR_ABI_VERSION;
  89
  90         dev->ibdev.uverbs_cmd_mask = QEDR_UVERBS(GET_CONTEXT) |
  91                                      QEDR_UVERBS(QUERY_DEVICE) |
  92                                      QEDR_UVERBS(QUERY_PORT) |
  93                                      QEDR_UVERBS(ALLOC_PD) |
  94                                      QEDR_UVERBS(DEALLOC_PD) |
  95                                      QEDR_UVERBS(CREATE_COMP_CHANNEL) |
  96                                      QEDR_UVERBS(CREATE_CQ) |
  97                                      QEDR_UVERBS(RESIZE_CQ) |
  98                                      QEDR_UVERBS(DESTROY_CQ) |
  99                                      QEDR_UVERBS(REQ_NOTIFY_CQ) |
 100                                      QEDR_UVERBS(CREATE_QP) |
 101                                      QEDR_UVERBS(MODIFY_QP) |
 102                                      QEDR_UVERBS(QUERY_QP) |
 103                                      QEDR_UVERBS(DESTROY_QP) |
 104                                      QEDR_UVERBS(REG_MR) |
 105                                      QEDR_UVERBS(DEREG_MR) |
 106                                      QEDR_UVERBS(POLL_CQ) |
 107                                      QEDR_UVERBS(POST_SEND) |
 108                                      QEDR_UVERBS(POST_RECV);
 109
 110         dev->ibdev.phys_port_cnt = 1;
 111         dev->ibdev.num_comp_vectors = dev->num_cnq;
 112         dev->ibdev.node_type = RDMA_NODE_IB_CA;
 113
 114         dev->ibdev.query_device = qedr_query_device;
 115         dev->ibdev.query_port = qedr_query_port;
 116         dev->ibdev.modify_port = qedr_modify_port;
 117
 118         dev->ibdev.query_gid = qedr_query_gid;
 119         dev->ibdev.add_gid = qedr_add_gid;
 120         dev->ibdev.del_gid = qedr_del_gid;
 121
 122         dev->ibdev.alloc_ucontext = qedr_alloc_ucontext;
 123         dev->ibdev.dealloc_ucontext = qedr_dealloc_ucontext;
 124         dev->ibdev.mmap = qedr_mmap;
 125
 126         dev->ibdev.alloc_pd = qedr_alloc_pd;
 127         dev->ibdev.dealloc_pd = qedr_dealloc_pd;
 128
 129         dev->ibdev.create_cq = qedr_create_cq;
 130         dev->ibdev.destroy_cq = qedr_destroy_cq;
 131         dev->ibdev.resize_cq = qedr_resize_cq;
 132         dev->ibdev.req_notify_cq = qedr_arm_cq;
 133
 134         dev->ibdev.create_qp = qedr_create_qp;
 135         dev->ibdev.modify_qp = qedr_modify_qp;
 136         dev->ibdev.query_qp = qedr_query_qp;
 137         dev->ibdev.destroy_qp = qedr_destroy_qp;
 138
 139         dev->ibdev.query_pkey = qedr_query_pkey;
 140
 141         dev->ibdev.create_ah = qedr_create_ah;
 142         dev->ibdev.destroy_ah = qedr_destroy_ah;
 143
 144         dev->ibdev.get_dma_mr = qedr_get_dma_mr;
 145         dev->ibdev.dereg_mr = qedr_dereg_mr;
 146         dev->ibdev.reg_user_mr = qedr_reg_user_mr;
 147         dev->ibdev.alloc_mr = qedr_alloc_mr;
 148         dev->ibdev.map_mr_sg = qedr_map_mr_sg;
 149
 150         dev->ibdev.poll_cq = qedr_poll_cq;
 151         dev->ibdev.post_send = qedr_post_send;
 152         dev->ibdev.post_recv = qedr_post_recv;
 153
 154         dev->ibdev.dma_device = &dev->pdev->dev;
 155
 156         dev->ibdev.get_link_layer = qedr_link_layer;
 157         dev->ibdev.get_dev_fw_str = qedr_get_dev_fw_str;
 158
 159         return 0;
 160 }
 161
 162 /* This function allocates fast-path status block memory */
 163 static int qedr_alloc_mem_sb(struct qedr_dev *dev,
 164                              struct qed_sb_info *sb_info, u16 sb_id)
 165 {
 166         struct status_block *sb_virt;
 167         dma_addr_t sb_phys;
 168         int rc;
 169
 170         sb_virt = dma_alloc_coherent(&dev->pdev->dev,
 171                                      sizeof(*sb_virt), &sb_phys, GFP_KERNEL);
 172         if (!sb_virt)
 173                 return -ENOMEM;
 174
 175         rc = dev->ops->common->sb_init(dev->cdev, sb_info,
 176                                        sb_virt, sb_phys, sb_id,
 177                                        QED_SB_TYPE_CNQ);
 178         if (rc) {
 179                 pr_err("Status block initialization failed\n");
 180                 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_virt),
 181                                   sb_virt, sb_phys);
 182                 return rc;
 183         }
 184
 185         return 0;
 186 }
 187
 188 static void qedr_free_mem_sb(struct qedr_dev *dev,
 189                              struct qed_sb_info *sb_info, int sb_id)
 190 {
 191         if (sb_info->sb_virt) {
 192                 dev->ops->common->sb_release(dev->cdev, sb_info, sb_id);
 193                 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_info->sb_virt),
 194                                   (void *)sb_info->sb_virt, sb_info->sb_phys);
 195         }
 196 }
 197
 198 static void qedr_free_resources(struct qedr_dev *dev)
 199 {
 200         int i;
 201
 202         for (i = 0; i < dev->num_cnq; i++) {
 203                 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
 204                 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
 205         }
 206
 207         kfree(dev->cnq_array);
 208         kfree(dev->sb_array);
 209         kfree(dev->sgid_tbl);
 210 }
 211
 212 static int qedr_alloc_resources(struct qedr_dev *dev)
 213 {
 214         struct qedr_cnq *cnq;
 215         __le16 *cons_pi;
 216         u16 n_entries;
 217         int i, rc;
 218
 219         dev->sgid_tbl = kzalloc(sizeof(union ib_gid) *
 220                                 QEDR_MAX_SGID, GFP_KERNEL);
 221         if (!dev->sgid_tbl)
 222                 return -ENOMEM;
 223
 224         spin_lock_init(&dev->sgid_lock);
 225
 226         /* Allocate Status blocks for CNQ */
 227         dev->sb_array = kcalloc(dev->num_cnq, sizeof(*dev->sb_array),
 228                                 GFP_KERNEL);
 229         if (!dev->sb_array) {
 230                 rc = -ENOMEM;
 231                 goto err1;
 232         }
 233
 234         dev->cnq_array = kcalloc(dev->num_cnq,
 235                                  sizeof(*dev->cnq_array), GFP_KERNEL);
 236         if (!dev->cnq_array) {
 237                 rc = -ENOMEM;
 238                 goto err2;
 239         }
 240
 241         dev->sb_start = dev->ops->rdma_get_start_sb(dev->cdev);
 242
 243         /* Allocate CNQ PBLs */
 244         n_entries = min_t(u32, QED_RDMA_MAX_CNQ_SIZE, QEDR_ROCE_MAX_CNQ_SIZE);
 245         for (i = 0; i < dev->num_cnq; i++) {
 246                 cnq = &dev->cnq_array[i];
 247
 248                 rc = qedr_alloc_mem_sb(dev, &dev->sb_array[i],
 249                                        dev->sb_start + i);
 250                 if (rc)
 251                         goto err3;
 252
 253                 rc = dev->ops->common->chain_alloc(dev->cdev,
 254                                                    QED_CHAIN_USE_TO_CONSUME,
 255                                                    QED_CHAIN_MODE_PBL,
 256                                                    QED_CHAIN_CNT_TYPE_U16,
 257                                                    n_entries,
 258                                                    sizeof(struct regpair *),
 259                                                    &cnq->pbl);
 260                 if (rc)
 261                         goto err4;
 262
 263                 cnq->dev = dev;
 264                 cnq->sb = &dev->sb_array[i];
 265                 cons_pi = dev->sb_array[i].sb_virt->pi_array;
 266                 cnq->hw_cons_ptr = &cons_pi[QED_ROCE_PROTOCOL_INDEX];
 267                 cnq->index = i;
 268                 sprintf(cnq->name, "qedr%d@pci:%s", i, pci_name(dev->pdev));
 269
 270                 DP_DEBUG(dev, QEDR_MSG_INIT, "cnq[%d].cons=%d\n",
 271                          i, qed_chain_get_cons_idx(&cnq->pbl));
 272         }
 273
 274         return 0;
 275 err4:
 276         qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
 277 err3:
 278         for (--i; i >= 0; i--) {
 279                 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
 280                 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
 281         }
 282         kfree(dev->cnq_array);
 283 err2:
 284         kfree(dev->sb_array);
 285 err1:
 286         kfree(dev->sgid_tbl);
 287         return rc;
 288 }
 289
 290 /* QEDR sysfs interface */
 291 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
 292                         char *buf)
 293 {
 294         struct qedr_dev *dev = dev_get_drvdata(device);
 295
 296         return scnprintf(buf, PAGE_SIZE, "0x%x\n", dev->pdev->vendor);
 297 }
 298
 299 static ssize_t show_hca_type(struct device *device,
 300                              struct device_attribute *attr, char *buf)
 301 {
 302         return scnprintf(buf, PAGE_SIZE, "%s\n", "HCA_TYPE_TO_SET");
 303 }
 304
 305 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
 306 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca_type, NULL);
 307
 308 static struct device_attribute *qedr_attributes[] = {
 309         &dev_attr_hw_rev,
 310         &dev_attr_hca_type
 311 };
 312
 313 static void qedr_remove_sysfiles(struct qedr_dev *dev)
 314 {
 315         int i;
 316
 317         for (i = 0; i < ARRAY_SIZE(qedr_attributes); i++)
 318                 device_remove_file(&dev->ibdev.dev, qedr_attributes[i]);
 319 }
 320
 321 static void qedr_pci_set_atomic(struct qedr_dev *dev, struct pci_dev *pdev)
 322 {
 323         struct pci_dev *bridge;
 324         u32 val;
 325
 326         dev->atomic_cap = IB_ATOMIC_NONE;
 327
 328         bridge = pdev->bus->self;
 329         if (!bridge)
 330                 return;
 331
 332         /* Check whether we are connected directly or via a switch */
 333         while (bridge && bridge->bus->parent) {
 334                 DP_DEBUG(dev, QEDR_MSG_INIT,
 335                          "Device is not connected directly to root. bridge->bus->number=%d primary=%d\n",
 336                          bridge->bus->number, bridge->bus->primary);
 337                 /* Need to check Atomic Op Routing Supported all the way to
 338                  * root complex.
 339                  */
 340                 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &val);
 341                 if (!(val & PCI_EXP_DEVCAP2_ATOMIC_ROUTE)) {
 342                         pcie_capability_clear_word(pdev,
 343                                                    PCI_EXP_DEVCTL2,
 344                                                    PCI_EXP_DEVCTL2_ATOMIC_REQ);
 345                         return;
 346                 }
 347                 bridge = bridge->bus->parent->self;
 348         }
 349         bridge = pdev->bus->self;
 350
 351         /* according to bridge capability */
 352         pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &val);
 353         if (val & PCI_EXP_DEVCAP2_ATOMIC_COMP64) {
 354                 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2,
 355                                          PCI_EXP_DEVCTL2_ATOMIC_REQ);
 356                 dev->atomic_cap = IB_ATOMIC_GLOB;
 357         } else {
 358                 pcie_capability_clear_word(pdev, PCI_EXP_DEVCTL2,
 359                                            PCI_EXP_DEVCTL2_ATOMIC_REQ);
 360         }
 361 }
 362
 363 static const struct qed_rdma_ops *qed_ops;
 364
 365 #define HILO_U64(hi, lo)                ((((u64)(hi)) << 32) + (lo))
 366
 367 static irqreturn_t qedr_irq_handler(int irq, void *handle)
 368 {
 369         u16 hw_comp_cons, sw_comp_cons;
 370         struct qedr_cnq *cnq = handle;
 371         struct regpair *cq_handle;
 372         struct qedr_cq *cq;
 373
 374         qed_sb_ack(cnq->sb, IGU_INT_DISABLE, 0);
 375
 376         qed_sb_update_sb_idx(cnq->sb);
 377
 378         hw_comp_cons = le16_to_cpu(*cnq->hw_cons_ptr);
 379         sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
 380
 381         /* Align protocol-index and chain reads */
 382         rmb();
 383
 384         while (sw_comp_cons != hw_comp_cons) {
 385                 cq_handle = (struct regpair *)qed_chain_consume(&cnq->pbl);
 386                 cq = (struct qedr_cq *)(uintptr_t)HILO_U64(cq_handle->hi,
 387                                 cq_handle->lo);
 388
 389                 if (cq == NULL) {
 390                         DP_ERR(cnq->dev,
 391                                "Received NULL CQ cq_handle->hi=%d cq_handle->lo=%d sw_comp_cons=%d hw_comp_cons=%d\n",
 392                                cq_handle->hi, cq_handle->lo, sw_comp_cons,
 393                                hw_comp_cons);
 394
 395                         break;
 396                 }
 397
 398                 if (cq->sig != QEDR_CQ_MAGIC_NUMBER) {
 399                         DP_ERR(cnq->dev,
 400                                "Problem with cq signature, cq_handle->hi=%d ch_handle->lo=%d cq=%p\n",
 401                                cq_handle->hi, cq_handle->lo, cq);
 402                         break;
 403                 }
 404
 405                 cq->arm_flags = 0;
 406
 407                 if (cq->ibcq.comp_handler)
 408                         (*cq->ibcq.comp_handler)
 409                                 (&cq->ibcq, cq->ibcq.cq_context);
 410
 411                 sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
 412
 413                 cnq->n_comp++;
 414
 415         }
 416
 417         qed_ops->rdma_cnq_prod_update(cnq->dev->rdma_ctx, cnq->index,
 418                                       sw_comp_cons);
 419
 420         qed_sb_ack(cnq->sb, IGU_INT_ENABLE, 1);
 421
 422         return IRQ_HANDLED;
 423 }
 424
 425 static void qedr_sync_free_irqs(struct qedr_dev *dev)
 426 {
 427         u32 vector;
 428         int i;
 429
 430         for (i = 0; i < dev->int_info.used_cnt; i++) {
 431                 if (dev->int_info.msix_cnt) {
 432                         vector = dev->int_info.msix[i * dev->num_hwfns].vector;
 433                         synchronize_irq(vector);
 434                         free_irq(vector, &dev->cnq_array[i]);
 435                 }
 436         }
 437
 438         dev->int_info.used_cnt = 0;
 439 }
 440
 441 static int qedr_req_msix_irqs(struct qedr_dev *dev)
 442 {
 443         int i, rc = 0;
 444
 445         if (dev->num_cnq > dev->int_info.msix_cnt) {
 446                 DP_ERR(dev,
 447                        "Interrupt mismatch: %d CNQ queues > %d MSI-x vectors\n",
 448                        dev->num_cnq, dev->int_info.msix_cnt);
 449                 return -EINVAL;
 450         }
 451
 452         for (i = 0; i < dev->num_cnq; i++) {
 453                 rc = request_irq(dev->int_info.msix[i * dev->num_hwfns].vector,
 454                                  qedr_irq_handler, 0, dev->cnq_array[i].name,
 455                                  &dev->cnq_array[i]);
 456                 if (rc) {
 457                         DP_ERR(dev, "Request cnq %d irq failed\n", i);
 458                         qedr_sync_free_irqs(dev);
 459                 } else {
 460                         DP_DEBUG(dev, QEDR_MSG_INIT,
 461                                  "Requested cnq irq for %s [entry %d]. Cookie is at %p\n",
 462                                  dev->cnq_array[i].name, i,
 463                                  &dev->cnq_array[i]);
 464                         dev->int_info.used_cnt++;
 465                 }
 466         }
 467
 468         return rc;
 469 }
 470
 471 static int qedr_setup_irqs(struct qedr_dev *dev)
 472 {
 473         int rc;
 474
 475         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs\n");
 476
 477         /* Learn Interrupt configuration */
 478         rc = dev->ops->rdma_set_rdma_int(dev->cdev, dev->num_cnq);
 479         if (rc < 0)
 480                 return rc;
 481
 482         rc = dev->ops->rdma_get_rdma_int(dev->cdev, &dev->int_info);
 483         if (rc) {
 484                 DP_DEBUG(dev, QEDR_MSG_INIT, "get_rdma_int failed\n");
 485                 return rc;
 486         }
 487
 488         if (dev->int_info.msix_cnt) {
 489                 DP_DEBUG(dev, QEDR_MSG_INIT, "rdma msix_cnt = %d\n",
 490                          dev->int_info.msix_cnt);
 491                 rc = qedr_req_msix_irqs(dev);
 492                 if (rc)
 493                         return rc;
 494         }
 495
 496         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs succeeded\n");
 497
 498         return 0;
 499 }
 500
 501 static int qedr_set_device_attr(struct qedr_dev *dev)
 502 {
 503         struct qed_rdma_device *qed_attr;
 504         struct qedr_device_attr *attr;
 505         u32 page_size;
 506
 507         /* Part 1 - query core capabilities */
 508         qed_attr = dev->ops->rdma_query_device(dev->rdma_ctx);
 509
 510         /* Part 2 - check capabilities */
 511         page_size = ~dev->attr.page_size_caps + 1;
 512         if (page_size > PAGE_SIZE) {
 513                 DP_ERR(dev,
 514                        "Kernel PAGE_SIZE is %ld which is smaller than minimum page size (%d) required by qedr\n",
 515                        PAGE_SIZE, page_size);
 516                 return -ENODEV;
 517         }
 518
 519         /* Part 3 - copy and update capabilities */
 520         attr = &dev->attr;
 521         attr->vendor_id = qed_attr->vendor_id;
 522         attr->vendor_part_id = qed_attr->vendor_part_id;
 523         attr->hw_ver = qed_attr->hw_ver;
 524         attr->fw_ver = qed_attr->fw_ver;
 525         attr->node_guid = qed_attr->node_guid;
 526         attr->sys_image_guid = qed_attr->sys_image_guid;
 527         attr->max_cnq = qed_attr->max_cnq;
 528         attr->max_sge = qed_attr->max_sge;
 529         attr->max_inline = qed_attr->max_inline;
 530         attr->max_sqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_SQE);
 531         attr->max_rqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_RQE);
 532         attr->max_qp_resp_rd_atomic_resc = qed_attr->max_qp_resp_rd_atomic_resc;
 533         attr->max_qp_req_rd_atomic_resc = qed_attr->max_qp_req_rd_atomic_resc;
 534         attr->max_dev_resp_rd_atomic_resc =
 535             qed_attr->max_dev_resp_rd_atomic_resc;
 536         attr->max_cq = qed_attr->max_cq;
 537         attr->max_qp = qed_attr->max_qp;
 538         attr->max_mr = qed_attr->max_mr;
 539         attr->max_mr_size = qed_attr->max_mr_size;
 540         attr->max_cqe = min_t(u64, qed_attr->max_cqe, QEDR_MAX_CQES);
 541         attr->max_mw = qed_attr->max_mw;
 542         attr->max_fmr = qed_attr->max_fmr;
 543         attr->max_mr_mw_fmr_pbl = qed_attr->max_mr_mw_fmr_pbl;
 544         attr->max_mr_mw_fmr_size = qed_attr->max_mr_mw_fmr_size;
 545         attr->max_pd = qed_attr->max_pd;
 546         attr->max_ah = qed_attr->max_ah;
 547         attr->max_pkey = qed_attr->max_pkey;
 548         attr->max_srq = qed_attr->max_srq;
 549         attr->max_srq_wr = qed_attr->max_srq_wr;
 550         attr->dev_caps = qed_attr->dev_caps;
 551         attr->page_size_caps = qed_attr->page_size_caps;
 552         attr->dev_ack_delay = qed_attr->dev_ack_delay;
 553         attr->reserved_lkey = qed_attr->reserved_lkey;
 554         attr->bad_pkey_counter = qed_attr->bad_pkey_counter;
 555         attr->max_stats_queues = qed_attr->max_stats_queues;
 556
 557         return 0;
 558 }
 559
 560 static int qedr_init_hw(struct qedr_dev *dev)
 561 {
 562         struct qed_rdma_add_user_out_params out_params;
 563         struct qed_rdma_start_in_params *in_params;
 564         struct qed_rdma_cnq_params *cur_pbl;
 565         struct qed_rdma_events events;
 566         dma_addr_t p_phys_table;
 567         u32 page_cnt;
 568         int rc = 0;
 569         int i;
 570
 571         in_params =  kzalloc(sizeof(*in_params), GFP_KERNEL);
 572         if (!in_params) {
 573                 rc = -ENOMEM;
 574                 goto out;
 575         }
 576
 577         in_params->desired_cnq = dev->num_cnq;
 578         for (i = 0; i < dev->num_cnq; i++) {
 579                 cur_pbl = &in_params->cnq_pbl_list[i];
 580
 581                 page_cnt = qed_chain_get_page_cnt(&dev->cnq_array[i].pbl);
 582                 cur_pbl->num_pbl_pages = page_cnt;
 583
 584                 p_phys_table = qed_chain_get_pbl_phys(&dev->cnq_array[i].pbl);
 585                 cur_pbl->pbl_ptr = (u64)p_phys_table;
 586         }
 587
 588         events.context = dev;
 589
 590         in_params->events = &events;
 591         in_params->cq_mode = QED_RDMA_CQ_MODE_32_BITS;
 592         in_params->max_mtu = dev->ndev->mtu;
 593         ether_addr_copy(&in_params->mac_addr[0], dev->ndev->dev_addr);
 594
 595         rc = dev->ops->rdma_init(dev->cdev, in_params);
 596         if (rc)
 597                 goto out;
 598
 599         rc = dev->ops->rdma_add_user(dev->rdma_ctx, &out_params);
 600         if (rc)
 601                 goto out;
 602
 603         dev->db_addr = (void *)(uintptr_t)out_params.dpi_addr;
 604         dev->db_phys_addr = out_params.dpi_phys_addr;
 605         dev->db_size = out_params.dpi_size;
 606         dev->dpi = out_params.dpi;
 607
 608         rc = qedr_set_device_attr(dev);
 609 out:
 610         kfree(in_params);
 611         if (rc)
 612                 DP_ERR(dev, "Init HW Failed rc = %d\n", rc);
 613
 614         return rc;
 615 }
 616
 617 void qedr_stop_hw(struct qedr_dev *dev)
 618 {
 619         dev->ops->rdma_remove_user(dev->rdma_ctx, dev->dpi);
 620         dev->ops->rdma_stop(dev->rdma_ctx);
 621 }
 622
 623 static struct qedr_dev *qedr_add(struct qed_dev *cdev, struct pci_dev *pdev,
 624                                  struct net_device *ndev)
 625 {
 626         struct qed_dev_rdma_info dev_info;
 627         struct qedr_dev *dev;
 628         int rc = 0, i;
 629
 630         dev = (struct qedr_dev *)ib_alloc_device(sizeof(*dev));
 631         if (!dev) {
 632                 pr_err("Unable to allocate ib device\n");
 633                 return NULL;
 634         }
 635
 636         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr add device called\n");
 637
 638         dev->pdev = pdev;
 639         dev->ndev = ndev;
 640         dev->cdev = cdev;
 641
 642         qed_ops = qed_get_rdma_ops();
 643         if (!qed_ops) {
 644                 DP_ERR(dev, "Failed to get qed roce operations\n");
 645                 goto init_err;
 646         }
 647
 648         dev->ops = qed_ops;
 649         rc = qed_ops->fill_dev_info(cdev, &dev_info);
 650         if (rc)
 651                 goto init_err;
 652
 653         dev->num_hwfns = dev_info.common.num_hwfns;
 654         dev->rdma_ctx = dev->ops->rdma_get_rdma_ctx(cdev);
 655
 656         dev->num_cnq = dev->ops->rdma_get_min_cnq_msix(cdev);
 657         if (!dev->num_cnq) {
 658                 DP_ERR(dev, "not enough CNQ resources.\n");
 659                 goto init_err;
 660         }
 661
 662         dev->wq_multiplier = QEDR_WQ_MULTIPLIER_DFT;
 663
 664         qedr_pci_set_atomic(dev, pdev);
 665
 666         rc = qedr_alloc_resources(dev);
 667         if (rc)
 668                 goto init_err;
 669
 670         rc = qedr_init_hw(dev);
 671         if (rc)
 672                 goto alloc_err;
 673
 674         rc = qedr_setup_irqs(dev);
 675         if (rc)
 676                 goto irq_err;
 677
 678         rc = qedr_register_device(dev);
 679         if (rc) {
 680                 DP_ERR(dev, "Unable to allocate register device\n");
 681                 goto reg_err;
 682         }
 683
 684         for (i = 0; i < ARRAY_SIZE(qedr_attributes); i++)
 685                 if (device_create_file(&dev->ibdev.dev, qedr_attributes[i]))
 686                         goto reg_err;
 687
 688         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr driver loaded successfully\n");
 689         return dev;
 690
 691 reg_err:
 692         qedr_sync_free_irqs(dev);
 693 irq_err:
 694         qedr_stop_hw(dev);
 695 alloc_err:
 696         qedr_free_resources(dev);
 697 init_err:
 698         ib_dealloc_device(&dev->ibdev);
 699         DP_ERR(dev, "qedr driver load failed rc=%d\n", rc);
 700
 701         return NULL;
 702 }
 703
 704 static void qedr_remove(struct qedr_dev *dev)
 705 {
 706         /* First unregister with stack to stop all the active traffic
 707          * of the registered clients.
 708          */
 709         qedr_remove_sysfiles(dev);
 710
 711         qedr_stop_hw(dev);
 712         qedr_sync_free_irqs(dev);
 713         qedr_free_resources(dev);
 714         ib_dealloc_device(&dev->ibdev);
 715 }
 716
 717 static int qedr_close(struct qedr_dev *dev)
 718 {
 719         qedr_ib_dispatch_event(dev, 1, IB_EVENT_PORT_ERR);
 720
 721         return 0;
 722 }
 723
 724 static void qedr_shutdown(struct qedr_dev *dev)
 725 {
 726         qedr_close(dev);
 727         qedr_remove(dev);
 728 }
 729
 730 static void qedr_mac_address_change(struct qedr_dev *dev)
 731 {
 732         union ib_gid *sgid = &dev->sgid_tbl[0];
 733         u8 guid[8], mac_addr[6];
 734         int rc;
 735
 736         /* Update SGID */
 737         ether_addr_copy(&mac_addr[0], dev->ndev->dev_addr);
 738         guid[0] = mac_addr[0] ^ 2;
 739         guid[1] = mac_addr[1];
 740         guid[2] = mac_addr[2];
 741         guid[3] = 0xff;
 742         guid[4] = 0xfe;
 743         guid[5] = mac_addr[3];
 744         guid[6] = mac_addr[4];
 745         guid[7] = mac_addr[5];
 746         sgid->global.subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
 747         memcpy(&sgid->raw[8], guid, sizeof(guid));
 748
 749         /* Update LL2 */
 750         rc = dev->ops->roce_ll2_set_mac_filter(dev->cdev,
 751                                                dev->gsi_ll2_mac_address,
 752                                                dev->ndev->dev_addr);
 753
 754         ether_addr_copy(dev->gsi_ll2_mac_address, dev->ndev->dev_addr);
 755
 756         qedr_ib_dispatch_event(dev, 1, IB_EVENT_GID_CHANGE);
 757
 758         if (rc)
 759                 DP_ERR(dev, "Error updating mac filter\n");
 760 }
 761
 762 /* event handling via NIC driver ensures that all the NIC specific
 763  * initialization done before RoCE driver notifies
 764  * event to stack.
 765  */
 766 static void qedr_notify(struct qedr_dev *dev, enum qede_roce_event event)
 767 {
 768         switch (event) {
 769         case QEDE_UP:
 770                 qedr_ib_dispatch_event(dev, 1, IB_EVENT_PORT_ACTIVE);
 771                 break;
 772         case QEDE_DOWN:
 773                 qedr_close(dev);
 774                 break;
 775         case QEDE_CLOSE:
 776                 qedr_shutdown(dev);
 777                 break;
 778         case QEDE_CHANGE_ADDR:
 779                 qedr_mac_address_change(dev);
 780                 break;
 781         default:
 782                 pr_err("Event not supported\n");
 783         }
 784 }
 785
 786 static struct qedr_driver qedr_drv = {
 787         .name = "qedr_driver",
 788         .add = qedr_add,
 789         .remove = qedr_remove,
 790         .notify = qedr_notify,
 791 };
 792
 793 static int __init qedr_init_module(void)
 794 {
 795         return qede_roce_register_driver(&qedr_drv);
 796 }
 797
 798 static void __exit qedr_exit_module(void)
 799 {
 800         qede_roce_unregister_driver(&qedr_drv);
 801 }
 802
 803 module_init(qedr_init_module);
 804 module_exit(qedr_exit_module);