drivers/infiniband/hw/qedr/main.c

   1 /* QLogic qedr NIC Driver
   2  * Copyright (c) 2015-2016  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #include <linux/module.h>
  33 #include <rdma/ib_verbs.h>
  34 #include <rdma/ib_addr.h>
  35 #include <linux/netdevice.h>
  36 #include <linux/iommu.h>
  37 #include <net/addrconf.h>
  38 #include <linux/qed/qede_roce.h>
  39 #include <linux/qed/qed_chain.h>
  40 #include <linux/qed/qed_if.h>
  41 #include "qedr.h"
  42
  43 MODULE_DESCRIPTION("QLogic 40G/100G ROCE Driver");
  44 MODULE_AUTHOR("QLogic Corporation");
  45 MODULE_LICENSE("Dual BSD/GPL");
  46 MODULE_VERSION(QEDR_MODULE_VERSION);
  47
  48 void qedr_ib_dispatch_event(struct qedr_dev *dev, u8 port_num,
  49                             enum ib_event_type type)
  50 {
  51         struct ib_event ibev;
  52
  53         ibev.device = &dev->ibdev;
  54         ibev.element.port_num = port_num;
  55         ibev.event = type;
  56
  57         ib_dispatch_event(&ibev);
  58 }
  59
  60 static enum rdma_link_layer qedr_link_layer(struct ib_device *device,
  61                                             u8 port_num)
  62 {
  63         return IB_LINK_LAYER_ETHERNET;
  64 }
  65
  66 static void qedr_get_dev_fw_str(struct ib_device *ibdev, char *str,
  67                                 size_t str_len)
  68 {
  69         struct qedr_dev *qedr = get_qedr_dev(ibdev);
  70         u32 fw_ver = (u32)qedr->attr.fw_ver;
  71
  72         snprintf(str, str_len, "%d. %d. %d. %d",
  73                  (fw_ver >> 24) & 0xFF, (fw_ver >> 16) & 0xFF,
  74                  (fw_ver >> 8) & 0xFF, fw_ver & 0xFF);
  75 }
  76
  77 static int qedr_register_device(struct qedr_dev *dev)
  78 {
  79         strlcpy(dev->ibdev.name, "qedr%d", IB_DEVICE_NAME_MAX);
  80
  81         memcpy(dev->ibdev.node_desc, QEDR_NODE_DESC, sizeof(QEDR_NODE_DESC));
  82         dev->ibdev.owner = THIS_MODULE;
  83
  84         dev->ibdev.get_link_layer = qedr_link_layer;
  85         dev->ibdev.get_dev_fw_str = qedr_get_dev_fw_str;
  86
  87         return 0;
  88 }
  89
  90 /* This function allocates fast-path status block memory */
  91 static int qedr_alloc_mem_sb(struct qedr_dev *dev,
  92                              struct qed_sb_info *sb_info, u16 sb_id)
  93 {
  94         struct status_block *sb_virt;
  95         dma_addr_t sb_phys;
  96         int rc;
  97
  98         sb_virt = dma_alloc_coherent(&dev->pdev->dev,
  99                                      sizeof(*sb_virt), &sb_phys, GFP_KERNEL);
 100         if (!sb_virt)
 101                 return -ENOMEM;
 102
 103         rc = dev->ops->common->sb_init(dev->cdev, sb_info,
 104                                        sb_virt, sb_phys, sb_id,
 105                                        QED_SB_TYPE_CNQ);
 106         if (rc) {
 107                 pr_err("Status block initialization failed\n");
 108                 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_virt),
 109                                   sb_virt, sb_phys);
 110                 return rc;
 111         }
 112
 113         return 0;
 114 }
 115
 116 static void qedr_free_mem_sb(struct qedr_dev *dev,
 117                              struct qed_sb_info *sb_info, int sb_id)
 118 {
 119         if (sb_info->sb_virt) {
 120                 dev->ops->common->sb_release(dev->cdev, sb_info, sb_id);
 121                 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_info->sb_virt),
 122                                   (void *)sb_info->sb_virt, sb_info->sb_phys);
 123         }
 124 }
 125
 126 static void qedr_free_resources(struct qedr_dev *dev)
 127 {
 128         int i;
 129
 130         for (i = 0; i < dev->num_cnq; i++) {
 131                 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
 132                 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
 133         }
 134
 135         kfree(dev->cnq_array);
 136         kfree(dev->sb_array);
 137         kfree(dev->sgid_tbl);
 138 }
 139
 140 static int qedr_alloc_resources(struct qedr_dev *dev)
 141 {
 142         struct qedr_cnq *cnq;
 143         __le16 *cons_pi;
 144         u16 n_entries;
 145         int i, rc;
 146
 147         dev->sgid_tbl = kzalloc(sizeof(union ib_gid) *
 148                                 QEDR_MAX_SGID, GFP_KERNEL);
 149         if (!dev->sgid_tbl)
 150                 return -ENOMEM;
 151
 152         spin_lock_init(&dev->sgid_lock);
 153
 154         /* Allocate Status blocks for CNQ */
 155         dev->sb_array = kcalloc(dev->num_cnq, sizeof(*dev->sb_array),
 156                                 GFP_KERNEL);
 157         if (!dev->sb_array) {
 158                 rc = -ENOMEM;
 159                 goto err1;
 160         }
 161
 162         dev->cnq_array = kcalloc(dev->num_cnq,
 163                                  sizeof(*dev->cnq_array), GFP_KERNEL);
 164         if (!dev->cnq_array) {
 165                 rc = -ENOMEM;
 166                 goto err2;
 167         }
 168
 169         dev->sb_start = dev->ops->rdma_get_start_sb(dev->cdev);
 170
 171         /* Allocate CNQ PBLs */
 172         n_entries = min_t(u32, QED_RDMA_MAX_CNQ_SIZE, QEDR_ROCE_MAX_CNQ_SIZE);
 173         for (i = 0; i < dev->num_cnq; i++) {
 174                 cnq = &dev->cnq_array[i];
 175
 176                 rc = qedr_alloc_mem_sb(dev, &dev->sb_array[i],
 177                                        dev->sb_start + i);
 178                 if (rc)
 179                         goto err3;
 180
 181                 rc = dev->ops->common->chain_alloc(dev->cdev,
 182                                                    QED_CHAIN_USE_TO_CONSUME,
 183                                                    QED_CHAIN_MODE_PBL,
 184                                                    QED_CHAIN_CNT_TYPE_U16,
 185                                                    n_entries,
 186                                                    sizeof(struct regpair *),
 187                                                    &cnq->pbl);
 188                 if (rc)
 189                         goto err4;
 190
 191                 cnq->dev = dev;
 192                 cnq->sb = &dev->sb_array[i];
 193                 cons_pi = dev->sb_array[i].sb_virt->pi_array;
 194                 cnq->hw_cons_ptr = &cons_pi[QED_ROCE_PROTOCOL_INDEX];
 195                 cnq->index = i;
 196                 sprintf(cnq->name, "qedr%d@pci:%s", i, pci_name(dev->pdev));
 197
 198                 DP_DEBUG(dev, QEDR_MSG_INIT, "cnq[%d].cons=%d\n",
 199                          i, qed_chain_get_cons_idx(&cnq->pbl));
 200         }
 201
 202         return 0;
 203 err4:
 204         qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
 205 err3:
 206         for (--i; i >= 0; i--) {
 207                 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
 208                 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
 209         }
 210         kfree(dev->cnq_array);
 211 err2:
 212         kfree(dev->sb_array);
 213 err1:
 214         kfree(dev->sgid_tbl);
 215         return rc;
 216 }
 217
 218 /* QEDR sysfs interface */
 219 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
 220                         char *buf)
 221 {
 222         struct qedr_dev *dev = dev_get_drvdata(device);
 223
 224         return scnprintf(buf, PAGE_SIZE, "0x%x\n", dev->pdev->vendor);
 225 }
 226
 227 static ssize_t show_hca_type(struct device *device,
 228                              struct device_attribute *attr, char *buf)
 229 {
 230         return scnprintf(buf, PAGE_SIZE, "%s\n", "HCA_TYPE_TO_SET");
 231 }
 232
 233 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
 234 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca_type, NULL);
 235
 236 static struct device_attribute *qedr_attributes[] = {
 237         &dev_attr_hw_rev,
 238         &dev_attr_hca_type
 239 };
 240
 241 static void qedr_remove_sysfiles(struct qedr_dev *dev)
 242 {
 243         int i;
 244
 245         for (i = 0; i < ARRAY_SIZE(qedr_attributes); i++)
 246                 device_remove_file(&dev->ibdev.dev, qedr_attributes[i]);
 247 }
 248
 249 static void qedr_pci_set_atomic(struct qedr_dev *dev, struct pci_dev *pdev)
 250 {
 251         struct pci_dev *bridge;
 252         u32 val;
 253
 254         dev->atomic_cap = IB_ATOMIC_NONE;
 255
 256         bridge = pdev->bus->self;
 257         if (!bridge)
 258                 return;
 259
 260         /* Check whether we are connected directly or via a switch */
 261         while (bridge && bridge->bus->parent) {
 262                 DP_DEBUG(dev, QEDR_MSG_INIT,
 263                          "Device is not connected directly to root. bridge->bus->number=%d primary=%d\n",
 264                          bridge->bus->number, bridge->bus->primary);
 265                 /* Need to check Atomic Op Routing Supported all the way to
 266                  * root complex.
 267                  */
 268                 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &val);
 269                 if (!(val & PCI_EXP_DEVCAP2_ATOMIC_ROUTE)) {
 270                         pcie_capability_clear_word(pdev,
 271                                                    PCI_EXP_DEVCTL2,
 272                                                    PCI_EXP_DEVCTL2_ATOMIC_REQ);
 273                         return;
 274                 }
 275                 bridge = bridge->bus->parent->self;
 276         }
 277         bridge = pdev->bus->self;
 278
 279         /* according to bridge capability */
 280         pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &val);
 281         if (val & PCI_EXP_DEVCAP2_ATOMIC_COMP64) {
 282                 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2,
 283                                          PCI_EXP_DEVCTL2_ATOMIC_REQ);
 284                 dev->atomic_cap = IB_ATOMIC_GLOB;
 285         } else {
 286                 pcie_capability_clear_word(pdev, PCI_EXP_DEVCTL2,
 287                                            PCI_EXP_DEVCTL2_ATOMIC_REQ);
 288         }
 289 }
 290
 291 static const struct qed_rdma_ops *qed_ops;
 292
 293 #define HILO_U64(hi, lo)                ((((u64)(hi)) << 32) + (lo))
 294
 295 static irqreturn_t qedr_irq_handler(int irq, void *handle)
 296 {
 297         u16 hw_comp_cons, sw_comp_cons;
 298         struct qedr_cnq *cnq = handle;
 299
 300         qed_sb_ack(cnq->sb, IGU_INT_DISABLE, 0);
 301
 302         qed_sb_update_sb_idx(cnq->sb);
 303
 304         hw_comp_cons = le16_to_cpu(*cnq->hw_cons_ptr);
 305         sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
 306
 307         /* Align protocol-index and chain reads */
 308         rmb();
 309
 310         while (sw_comp_cons != hw_comp_cons) {
 311                 sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
 312                 cnq->n_comp++;
 313         }
 314
 315         qed_ops->rdma_cnq_prod_update(cnq->dev->rdma_ctx, cnq->index,
 316                                       sw_comp_cons);
 317
 318         qed_sb_ack(cnq->sb, IGU_INT_ENABLE, 1);
 319
 320         return IRQ_HANDLED;
 321 }
 322
 323 static void qedr_sync_free_irqs(struct qedr_dev *dev)
 324 {
 325         u32 vector;
 326         int i;
 327
 328         for (i = 0; i < dev->int_info.used_cnt; i++) {
 329                 if (dev->int_info.msix_cnt) {
 330                         vector = dev->int_info.msix[i * dev->num_hwfns].vector;
 331                         synchronize_irq(vector);
 332                         free_irq(vector, &dev->cnq_array[i]);
 333                 }
 334         }
 335
 336         dev->int_info.used_cnt = 0;
 337 }
 338
 339 static int qedr_req_msix_irqs(struct qedr_dev *dev)
 340 {
 341         int i, rc = 0;
 342
 343         if (dev->num_cnq > dev->int_info.msix_cnt) {
 344                 DP_ERR(dev,
 345                        "Interrupt mismatch: %d CNQ queues > %d MSI-x vectors\n",
 346                        dev->num_cnq, dev->int_info.msix_cnt);
 347                 return -EINVAL;
 348         }
 349
 350         for (i = 0; i < dev->num_cnq; i++) {
 351                 rc = request_irq(dev->int_info.msix[i * dev->num_hwfns].vector,
 352                                  qedr_irq_handler, 0, dev->cnq_array[i].name,
 353                                  &dev->cnq_array[i]);
 354                 if (rc) {
 355                         DP_ERR(dev, "Request cnq %d irq failed\n", i);
 356                         qedr_sync_free_irqs(dev);
 357                 } else {
 358                         DP_DEBUG(dev, QEDR_MSG_INIT,
 359                                  "Requested cnq irq for %s [entry %d]. Cookie is at %p\n",
 360                                  dev->cnq_array[i].name, i,
 361                                  &dev->cnq_array[i]);
 362                         dev->int_info.used_cnt++;
 363                 }
 364         }
 365
 366         return rc;
 367 }
 368
 369 static int qedr_setup_irqs(struct qedr_dev *dev)
 370 {
 371         int rc;
 372
 373         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs\n");
 374
 375         /* Learn Interrupt configuration */
 376         rc = dev->ops->rdma_set_rdma_int(dev->cdev, dev->num_cnq);
 377         if (rc < 0)
 378                 return rc;
 379
 380         rc = dev->ops->rdma_get_rdma_int(dev->cdev, &dev->int_info);
 381         if (rc) {
 382                 DP_DEBUG(dev, QEDR_MSG_INIT, "get_rdma_int failed\n");
 383                 return rc;
 384         }
 385
 386         if (dev->int_info.msix_cnt) {
 387                 DP_DEBUG(dev, QEDR_MSG_INIT, "rdma msix_cnt = %d\n",
 388                          dev->int_info.msix_cnt);
 389                 rc = qedr_req_msix_irqs(dev);
 390                 if (rc)
 391                         return rc;
 392         }
 393
 394         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs succeeded\n");
 395
 396         return 0;
 397 }
 398
 399 static int qedr_set_device_attr(struct qedr_dev *dev)
 400 {
 401         struct qed_rdma_device *qed_attr;
 402         struct qedr_device_attr *attr;
 403         u32 page_size;
 404
 405         /* Part 1 - query core capabilities */
 406         qed_attr = dev->ops->rdma_query_device(dev->rdma_ctx);
 407
 408         /* Part 2 - check capabilities */
 409         page_size = ~dev->attr.page_size_caps + 1;
 410         if (page_size > PAGE_SIZE) {
 411                 DP_ERR(dev,
 412                        "Kernel PAGE_SIZE is %ld which is smaller than minimum page size (%d) required by qedr\n",
 413                        PAGE_SIZE, page_size);
 414                 return -ENODEV;
 415         }
 416
 417         /* Part 3 - copy and update capabilities */
 418         attr = &dev->attr;
 419         attr->vendor_id = qed_attr->vendor_id;
 420         attr->vendor_part_id = qed_attr->vendor_part_id;
 421         attr->hw_ver = qed_attr->hw_ver;
 422         attr->fw_ver = qed_attr->fw_ver;
 423         attr->node_guid = qed_attr->node_guid;
 424         attr->sys_image_guid = qed_attr->sys_image_guid;
 425         attr->max_cnq = qed_attr->max_cnq;
 426         attr->max_sge = qed_attr->max_sge;
 427         attr->max_inline = qed_attr->max_inline;
 428         attr->max_sqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_SQE);
 429         attr->max_rqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_RQE);
 430         attr->max_qp_resp_rd_atomic_resc = qed_attr->max_qp_resp_rd_atomic_resc;
 431         attr->max_qp_req_rd_atomic_resc = qed_attr->max_qp_req_rd_atomic_resc;
 432         attr->max_dev_resp_rd_atomic_resc =
 433             qed_attr->max_dev_resp_rd_atomic_resc;
 434         attr->max_cq = qed_attr->max_cq;
 435         attr->max_qp = qed_attr->max_qp;
 436         attr->max_mr = qed_attr->max_mr;
 437         attr->max_mr_size = qed_attr->max_mr_size;
 438         attr->max_cqe = min_t(u64, qed_attr->max_cqe, QEDR_MAX_CQES);
 439         attr->max_mw = qed_attr->max_mw;
 440         attr->max_fmr = qed_attr->max_fmr;
 441         attr->max_mr_mw_fmr_pbl = qed_attr->max_mr_mw_fmr_pbl;
 442         attr->max_mr_mw_fmr_size = qed_attr->max_mr_mw_fmr_size;
 443         attr->max_pd = qed_attr->max_pd;
 444         attr->max_ah = qed_attr->max_ah;
 445         attr->max_pkey = qed_attr->max_pkey;
 446         attr->max_srq = qed_attr->max_srq;
 447         attr->max_srq_wr = qed_attr->max_srq_wr;
 448         attr->dev_caps = qed_attr->dev_caps;
 449         attr->page_size_caps = qed_attr->page_size_caps;
 450         attr->dev_ack_delay = qed_attr->dev_ack_delay;
 451         attr->reserved_lkey = qed_attr->reserved_lkey;
 452         attr->bad_pkey_counter = qed_attr->bad_pkey_counter;
 453         attr->max_stats_queues = qed_attr->max_stats_queues;
 454
 455         return 0;
 456 }
 457
 458 static int qedr_init_hw(struct qedr_dev *dev)
 459 {
 460         struct qed_rdma_add_user_out_params out_params;
 461         struct qed_rdma_start_in_params *in_params;
 462         struct qed_rdma_cnq_params *cur_pbl;
 463         struct qed_rdma_events events;
 464         dma_addr_t p_phys_table;
 465         u32 page_cnt;
 466         int rc = 0;
 467         int i;
 468
 469         in_params =  kzalloc(sizeof(*in_params), GFP_KERNEL);
 470         if (!in_params) {
 471                 rc = -ENOMEM;
 472                 goto out;
 473         }
 474
 475         in_params->desired_cnq = dev->num_cnq;
 476         for (i = 0; i < dev->num_cnq; i++) {
 477                 cur_pbl = &in_params->cnq_pbl_list[i];
 478
 479                 page_cnt = qed_chain_get_page_cnt(&dev->cnq_array[i].pbl);
 480                 cur_pbl->num_pbl_pages = page_cnt;
 481
 482                 p_phys_table = qed_chain_get_pbl_phys(&dev->cnq_array[i].pbl);
 483                 cur_pbl->pbl_ptr = (u64)p_phys_table;
 484         }
 485
 486         events.context = dev;
 487
 488         in_params->events = &events;
 489         in_params->cq_mode = QED_RDMA_CQ_MODE_32_BITS;
 490         in_params->max_mtu = dev->ndev->mtu;
 491         ether_addr_copy(&in_params->mac_addr[0], dev->ndev->dev_addr);
 492
 493         rc = dev->ops->rdma_init(dev->cdev, in_params);
 494         if (rc)
 495                 goto out;
 496
 497         rc = dev->ops->rdma_add_user(dev->rdma_ctx, &out_params);
 498         if (rc)
 499                 goto out;
 500
 501         dev->db_addr = (void *)(uintptr_t)out_params.dpi_addr;
 502         dev->db_phys_addr = out_params.dpi_phys_addr;
 503         dev->db_size = out_params.dpi_size;
 504         dev->dpi = out_params.dpi;
 505
 506         rc = qedr_set_device_attr(dev);
 507 out:
 508         kfree(in_params);
 509         if (rc)
 510                 DP_ERR(dev, "Init HW Failed rc = %d\n", rc);
 511
 512         return rc;
 513 }
 514
 515 void qedr_stop_hw(struct qedr_dev *dev)
 516 {
 517         dev->ops->rdma_remove_user(dev->rdma_ctx, dev->dpi);
 518         dev->ops->rdma_stop(dev->rdma_ctx);
 519 }
 520
 521 static struct qedr_dev *qedr_add(struct qed_dev *cdev, struct pci_dev *pdev,
 522                                  struct net_device *ndev)
 523 {
 524         struct qed_dev_rdma_info dev_info;
 525         struct qedr_dev *dev;
 526         int rc = 0, i;
 527
 528         dev = (struct qedr_dev *)ib_alloc_device(sizeof(*dev));
 529         if (!dev) {
 530                 pr_err("Unable to allocate ib device\n");
 531                 return NULL;
 532         }
 533
 534         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr add device called\n");
 535
 536         dev->pdev = pdev;
 537         dev->ndev = ndev;
 538         dev->cdev = cdev;
 539
 540         qed_ops = qed_get_rdma_ops();
 541         if (!qed_ops) {
 542                 DP_ERR(dev, "Failed to get qed roce operations\n");
 543                 goto init_err;
 544         }
 545
 546         dev->ops = qed_ops;
 547         rc = qed_ops->fill_dev_info(cdev, &dev_info);
 548         if (rc)
 549                 goto init_err;
 550
 551         dev->num_hwfns = dev_info.common.num_hwfns;
 552         dev->rdma_ctx = dev->ops->rdma_get_rdma_ctx(cdev);
 553
 554         dev->num_cnq = dev->ops->rdma_get_min_cnq_msix(cdev);
 555         if (!dev->num_cnq) {
 556                 DP_ERR(dev, "not enough CNQ resources.\n");
 557                 goto init_err;
 558         }
 559
 560         qedr_pci_set_atomic(dev, pdev);
 561
 562         rc = qedr_alloc_resources(dev);
 563         if (rc)
 564                 goto init_err;
 565
 566         rc = qedr_init_hw(dev);
 567         if (rc)
 568                 goto alloc_err;
 569
 570         rc = qedr_setup_irqs(dev);
 571         if (rc)
 572                 goto irq_err;
 573
 574         rc = qedr_register_device(dev);
 575         if (rc) {
 576                 DP_ERR(dev, "Unable to allocate register device\n");
 577                 goto reg_err;
 578         }
 579
 580         for (i = 0; i < ARRAY_SIZE(qedr_attributes); i++)
 581                 if (device_create_file(&dev->ibdev.dev, qedr_attributes[i]))
 582                         goto reg_err;
 583
 584         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr driver loaded successfully\n");
 585         return dev;
 586
 587 reg_err:
 588         qedr_sync_free_irqs(dev);
 589 irq_err:
 590         qedr_stop_hw(dev);
 591 alloc_err:
 592         qedr_free_resources(dev);
 593 init_err:
 594         ib_dealloc_device(&dev->ibdev);
 595         DP_ERR(dev, "qedr driver load failed rc=%d\n", rc);
 596
 597         return NULL;
 598 }
 599
 600 static void qedr_remove(struct qedr_dev *dev)
 601 {
 602         /* First unregister with stack to stop all the active traffic
 603          * of the registered clients.
 604          */
 605         qedr_remove_sysfiles(dev);
 606
 607         qedr_stop_hw(dev);
 608         qedr_sync_free_irqs(dev);
 609         qedr_free_resources(dev);
 610         ib_dealloc_device(&dev->ibdev);
 611 }
 612
 613 static int qedr_close(struct qedr_dev *dev)
 614 {
 615         qedr_ib_dispatch_event(dev, 1, IB_EVENT_PORT_ERR);
 616
 617         return 0;
 618 }
 619
 620 static void qedr_shutdown(struct qedr_dev *dev)
 621 {
 622         qedr_close(dev);
 623         qedr_remove(dev);
 624 }
 625
 626 /* event handling via NIC driver ensures that all the NIC specific
 627  * initialization done before RoCE driver notifies
 628  * event to stack.
 629  */
 630 static void qedr_notify(struct qedr_dev *dev, enum qede_roce_event event)
 631 {
 632         switch (event) {
 633         case QEDE_UP:
 634                 qedr_ib_dispatch_event(dev, 1, IB_EVENT_PORT_ACTIVE);
 635                 break;
 636         case QEDE_DOWN:
 637                 qedr_close(dev);
 638                 break;
 639         case QEDE_CLOSE:
 640                 qedr_shutdown(dev);
 641                 break;
 642         case QEDE_CHANGE_ADDR:
 643                 qedr_ib_dispatch_event(dev, 1, IB_EVENT_GID_CHANGE);
 644                 break;
 645         default:
 646                 pr_err("Event not supported\n");
 647         }
 648 }
 649
 650 static struct qedr_driver qedr_drv = {
 651         .name = "qedr_driver",
 652         .add = qedr_add,
 653         .remove = qedr_remove,
 654         .notify = qedr_notify,
 655 };
 656
 657 static int __init qedr_init_module(void)
 658 {
 659         return qede_roce_register_driver(&qedr_drv);
 660 }
 661
 662 static void __exit qedr_exit_module(void)
 663 {
 664         qede_roce_unregister_driver(&qedr_drv);
 665 }
 666
 667 module_init(qedr_init_module);
 668 module_exit(qedr_exit_module);