drivers/iommu/amd_iommu_v2.c

   1 /*
   2  * Copyright (C) 2010-2012 Advanced Micro Devices, Inc.
   3  * Author: Joerg Roedel <joerg.roedel@amd.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published
   7  * by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  17  */
  18
  19 #include <linux/mmu_notifier.h>
  20 #include <linux/amd-iommu.h>
  21 #include <linux/mm_types.h>
  22 #include <linux/profile.h>
  23 #include <linux/module.h>
  24 #include <linux/sched.h>
  25 #include <linux/iommu.h>
  26 #include <linux/wait.h>
  27 #include <linux/pci.h>
  28 #include <linux/gfp.h>
  29
  30 #include "amd_iommu_types.h"
  31 #include "amd_iommu_proto.h"
  32
  33 MODULE_LICENSE("GPL v2");
  34 MODULE_AUTHOR("Joerg Roedel <joerg.roedel@amd.com>");
  35
  36 #define MAX_DEVICES             0x10000
  37 #define PRI_QUEUE_SIZE          512
  38
  39 struct pri_queue {
  40         atomic_t inflight;
  41         bool finish;
  42         int status;
  43 };
  44
  45 struct pasid_state {
  46         struct list_head list;                  /* For global state-list */
  47         atomic_t count;                         /* Reference count */
  48         unsigned mmu_notifier_count;            /* Counting nested mmu_notifier
  49                                                    calls */
  50         struct task_struct *task;               /* Task bound to this PASID */
  51         struct mm_struct *mm;                   /* mm_struct for the faults */
  52         struct mmu_notifier mn;                 /* mmu_otifier handle */
  53         struct pri_queue pri[PRI_QUEUE_SIZE];   /* PRI tag states */
  54         struct device_state *device_state;      /* Link to our device_state */
  55         int pasid;                              /* PASID index */
  56         spinlock_t lock;                        /* Protect pri_queues and
  57                                                    mmu_notifer_count */
  58         wait_queue_head_t wq;                   /* To wait for count == 0 */
  59 };
  60
  61 struct device_state {
  62         struct list_head list;
  63         u16 devid;
  64         atomic_t count;
  65         struct pci_dev *pdev;
  66         struct pasid_state **states;
  67         struct iommu_domain *domain;
  68         int pasid_levels;
  69         int max_pasids;
  70         amd_iommu_invalid_ppr_cb inv_ppr_cb;
  71         amd_iommu_invalidate_ctx inv_ctx_cb;
  72         spinlock_t lock;
  73         wait_queue_head_t wq;
  74 };
  75
  76 struct fault {
  77         struct work_struct work;
  78         struct device_state *dev_state;
  79         struct pasid_state *state;
  80         struct mm_struct *mm;
  81         u64 address;
  82         u16 devid;
  83         u16 pasid;
  84         u16 tag;
  85         u16 finish;
  86         u16 flags;
  87 };
  88
  89 static LIST_HEAD(state_list);
  90 static spinlock_t state_lock;
  91
  92 static struct workqueue_struct *iommu_wq;
  93
  94 /*
  95  * Empty page table - Used between
  96  * mmu_notifier_invalidate_range_start and
  97  * mmu_notifier_invalidate_range_end
  98  */
  99 static u64 *empty_page_table;
 100
 101 static void free_pasid_states(struct device_state *dev_state);
 102 static void unbind_pasid(struct device_state *dev_state, int pasid);
 103
 104 static u16 device_id(struct pci_dev *pdev)
 105 {
 106         u16 devid;
 107
 108         devid = pdev->bus->number;
 109         devid = (devid << 8) | pdev->devfn;
 110
 111         return devid;
 112 }
 113
 114 static struct device_state *__get_device_state(u16 devid)
 115 {
 116         struct device_state *dev_state;
 117
 118         list_for_each_entry(dev_state, &state_list, list) {
 119                 if (dev_state->devid == devid)
 120                         return dev_state;
 121         }
 122
 123         return NULL;
 124 }
 125
 126 static struct device_state *get_device_state(u16 devid)
 127 {
 128         struct device_state *dev_state;
 129         unsigned long flags;
 130
 131         spin_lock_irqsave(&state_lock, flags);
 132         dev_state = __get_device_state(devid);
 133         if (dev_state != NULL)
 134                 atomic_inc(&dev_state->count);
 135         spin_unlock_irqrestore(&state_lock, flags);
 136
 137         return dev_state;
 138 }
 139
 140 static void free_device_state(struct device_state *dev_state)
 141 {
 142         /*
 143          * First detach device from domain - No more PRI requests will arrive
 144          * from that device after it is unbound from the IOMMUv2 domain.
 145          */
 146         iommu_detach_device(dev_state->domain, &dev_state->pdev->dev);
 147
 148         /* Everything is down now, free the IOMMUv2 domain */
 149         iommu_domain_free(dev_state->domain);
 150
 151         /* Finally get rid of the device-state */
 152         kfree(dev_state);
 153 }
 154
 155 static void put_device_state(struct device_state *dev_state)
 156 {
 157         if (atomic_dec_and_test(&dev_state->count))
 158                 wake_up(&dev_state->wq);
 159 }
 160
 161 static void put_device_state_wait(struct device_state *dev_state)
 162 {
 163         DEFINE_WAIT(wait);
 164
 165         prepare_to_wait(&dev_state->wq, &wait, TASK_UNINTERRUPTIBLE);
 166         if (!atomic_dec_and_test(&dev_state->count))
 167                 schedule();
 168         finish_wait(&dev_state->wq, &wait);
 169
 170         free_device_state(dev_state);
 171 }
 172
 173 /* Must be called under dev_state->lock */
 174 static struct pasid_state **__get_pasid_state_ptr(struct device_state *dev_state,
 175                                                   int pasid, bool alloc)
 176 {
 177         struct pasid_state **root, **ptr;
 178         int level, index;
 179
 180         level = dev_state->pasid_levels;
 181         root  = dev_state->states;
 182
 183         while (true) {
 184
 185                 index = (pasid >> (9 * level)) & 0x1ff;
 186                 ptr   = &root[index];
 187
 188                 if (level == 0)
 189                         break;
 190
 191                 if (*ptr == NULL) {
 192                         if (!alloc)
 193                                 return NULL;
 194
 195                         *ptr = (void *)get_zeroed_page(GFP_ATOMIC);
 196                         if (*ptr == NULL)
 197                                 return NULL;
 198                 }
 199
 200                 root   = (struct pasid_state **)*ptr;
 201                 level -= 1;
 202         }
 203
 204         return ptr;
 205 }
 206
 207 static int set_pasid_state(struct device_state *dev_state,
 208                            struct pasid_state *pasid_state,
 209                            int pasid)
 210 {
 211         struct pasid_state **ptr;
 212         unsigned long flags;
 213         int ret;
 214
 215         spin_lock_irqsave(&dev_state->lock, flags);
 216         ptr = __get_pasid_state_ptr(dev_state, pasid, true);
 217
 218         ret = -ENOMEM;
 219         if (ptr == NULL)
 220                 goto out_unlock;
 221
 222         ret = -ENOMEM;
 223         if (*ptr != NULL)
 224                 goto out_unlock;
 225
 226         *ptr = pasid_state;
 227
 228         ret = 0;
 229
 230 out_unlock:
 231         spin_unlock_irqrestore(&dev_state->lock, flags);
 232
 233         return ret;
 234 }
 235
 236 static void clear_pasid_state(struct device_state *dev_state, int pasid)
 237 {
 238         struct pasid_state **ptr;
 239         unsigned long flags;
 240
 241         spin_lock_irqsave(&dev_state->lock, flags);
 242         ptr = __get_pasid_state_ptr(dev_state, pasid, true);
 243
 244         if (ptr == NULL)
 245                 goto out_unlock;
 246
 247         *ptr = NULL;
 248
 249 out_unlock:
 250         spin_unlock_irqrestore(&dev_state->lock, flags);
 251 }
 252
 253 static struct pasid_state *get_pasid_state(struct device_state *dev_state,
 254                                            int pasid)
 255 {
 256         struct pasid_state **ptr, *ret = NULL;
 257         unsigned long flags;
 258
 259         spin_lock_irqsave(&dev_state->lock, flags);
 260         ptr = __get_pasid_state_ptr(dev_state, pasid, false);
 261
 262         if (ptr == NULL)
 263                 goto out_unlock;
 264
 265         ret = *ptr;
 266         if (ret)
 267                 atomic_inc(&ret->count);
 268
 269 out_unlock:
 270         spin_unlock_irqrestore(&dev_state->lock, flags);
 271
 272         return ret;
 273 }
 274
 275 static void free_pasid_state(struct pasid_state *pasid_state)
 276 {
 277         kfree(pasid_state);
 278 }
 279
 280 static void put_pasid_state(struct pasid_state *pasid_state)
 281 {
 282         if (atomic_dec_and_test(&pasid_state->count)) {
 283                 put_device_state(pasid_state->device_state);
 284                 wake_up(&pasid_state->wq);
 285         }
 286 }
 287
 288 static void put_pasid_state_wait(struct pasid_state *pasid_state)
 289 {
 290         DEFINE_WAIT(wait);
 291
 292         prepare_to_wait(&pasid_state->wq, &wait, TASK_UNINTERRUPTIBLE);
 293
 294         if (atomic_dec_and_test(&pasid_state->count))
 295                 put_device_state(pasid_state->device_state);
 296         else
 297                 schedule();
 298
 299         finish_wait(&pasid_state->wq, &wait);
 300         mmput(pasid_state->mm);
 301         free_pasid_state(pasid_state);
 302 }
 303
 304 static void __unbind_pasid(struct pasid_state *pasid_state)
 305 {
 306         struct iommu_domain *domain;
 307
 308         domain = pasid_state->device_state->domain;
 309
 310         amd_iommu_domain_clear_gcr3(domain, pasid_state->pasid);
 311         clear_pasid_state(pasid_state->device_state, pasid_state->pasid);
 312
 313         /* Make sure no more pending faults are in the queue */
 314         flush_workqueue(iommu_wq);
 315
 316         mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm);
 317
 318         put_pasid_state(pasid_state); /* Reference taken in bind() function */
 319 }
 320
 321 static void unbind_pasid(struct device_state *dev_state, int pasid)
 322 {
 323         struct pasid_state *pasid_state;
 324
 325         pasid_state = get_pasid_state(dev_state, pasid);
 326         if (pasid_state == NULL)
 327                 return;
 328
 329         __unbind_pasid(pasid_state);
 330         put_pasid_state_wait(pasid_state); /* Reference taken in this function */
 331 }
 332
 333 static void free_pasid_states_level1(struct pasid_state **tbl)
 334 {
 335         int i;
 336
 337         for (i = 0; i < 512; ++i) {
 338                 if (tbl[i] == NULL)
 339                         continue;
 340
 341                 free_page((unsigned long)tbl[i]);
 342         }
 343 }
 344
 345 static void free_pasid_states_level2(struct pasid_state **tbl)
 346 {
 347         struct pasid_state **ptr;
 348         int i;
 349
 350         for (i = 0; i < 512; ++i) {
 351                 if (tbl[i] == NULL)
 352                         continue;
 353
 354                 ptr = (struct pasid_state **)tbl[i];
 355                 free_pasid_states_level1(ptr);
 356         }
 357 }
 358
 359 static void free_pasid_states(struct device_state *dev_state)
 360 {
 361         struct pasid_state *pasid_state;
 362         int i;
 363
 364         for (i = 0; i < dev_state->max_pasids; ++i) {
 365                 pasid_state = get_pasid_state(dev_state, i);
 366                 if (pasid_state == NULL)
 367                         continue;
 368
 369                 put_pasid_state(pasid_state);
 370
 371                 /*
 372                  * This will call the mn_release function and
 373                  * unbind the PASID
 374                  */
 375                 mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm);
 376         }
 377
 378         if (dev_state->pasid_levels == 2)
 379                 free_pasid_states_level2(dev_state->states);
 380         else if (dev_state->pasid_levels == 1)
 381                 free_pasid_states_level1(dev_state->states);
 382         else if (dev_state->pasid_levels != 0)
 383                 BUG();
 384
 385         free_page((unsigned long)dev_state->states);
 386 }
 387
 388 static struct pasid_state *mn_to_state(struct mmu_notifier *mn)
 389 {
 390         return container_of(mn, struct pasid_state, mn);
 391 }
 392
 393 static void __mn_flush_page(struct mmu_notifier *mn,
 394                             unsigned long address)
 395 {
 396         struct pasid_state *pasid_state;
 397         struct device_state *dev_state;
 398
 399         pasid_state = mn_to_state(mn);
 400         dev_state   = pasid_state->device_state;
 401
 402         amd_iommu_flush_page(dev_state->domain, pasid_state->pasid, address);
 403 }
 404
 405 static int mn_clear_flush_young(struct mmu_notifier *mn,
 406                                 struct mm_struct *mm,
 407                                 unsigned long address)
 408 {
 409         __mn_flush_page(mn, address);
 410
 411         return 0;
 412 }
 413
 414 static void mn_change_pte(struct mmu_notifier *mn,
 415                           struct mm_struct *mm,
 416                           unsigned long address,
 417                           pte_t pte)
 418 {
 419         __mn_flush_page(mn, address);
 420 }
 421
 422 static void mn_invalidate_page(struct mmu_notifier *mn,
 423                                struct mm_struct *mm,
 424                                unsigned long address)
 425 {
 426         __mn_flush_page(mn, address);
 427 }
 428
 429 static void mn_invalidate_range_start(struct mmu_notifier *mn,
 430                                       struct mm_struct *mm,
 431                                       unsigned long start, unsigned long end)
 432 {
 433         struct pasid_state *pasid_state;
 434         struct device_state *dev_state;
 435         unsigned long flags;
 436
 437         pasid_state = mn_to_state(mn);
 438         dev_state   = pasid_state->device_state;
 439
 440         spin_lock_irqsave(&pasid_state->lock, flags);
 441         if (pasid_state->mmu_notifier_count == 0) {
 442                 amd_iommu_domain_set_gcr3(dev_state->domain,
 443                                           pasid_state->pasid,
 444                                           __pa(empty_page_table));
 445         }
 446         pasid_state->mmu_notifier_count += 1;
 447         spin_unlock_irqrestore(&pasid_state->lock, flags);
 448 }
 449
 450 static void mn_invalidate_range_end(struct mmu_notifier *mn,
 451                                     struct mm_struct *mm,
 452                                     unsigned long start, unsigned long end)
 453 {
 454         struct pasid_state *pasid_state;
 455         struct device_state *dev_state;
 456         unsigned long flags;
 457
 458         pasid_state = mn_to_state(mn);
 459         dev_state   = pasid_state->device_state;
 460
 461         spin_lock_irqsave(&pasid_state->lock, flags);
 462         pasid_state->mmu_notifier_count -= 1;
 463         if (pasid_state->mmu_notifier_count == 0) {
 464                 amd_iommu_domain_set_gcr3(dev_state->domain,
 465                                           pasid_state->pasid,
 466                                           __pa(pasid_state->mm->pgd));
 467         }
 468         spin_unlock_irqrestore(&pasid_state->lock, flags);
 469 }
 470
 471 static void mn_release(struct mmu_notifier *mn, struct mm_struct *mm)
 472 {
 473         struct pasid_state *pasid_state;
 474         struct device_state *dev_state;
 475
 476         might_sleep();
 477
 478         pasid_state = mn_to_state(mn);
 479         dev_state   = pasid_state->device_state;
 480
 481         if (pasid_state->device_state->inv_ctx_cb)
 482                 dev_state->inv_ctx_cb(dev_state->pdev, pasid_state->pasid);
 483
 484         unbind_pasid(dev_state, pasid_state->pasid);
 485 }
 486
 487 static struct mmu_notifier_ops iommu_mn = {
 488         .release                = mn_release,
 489         .clear_flush_young      = mn_clear_flush_young,
 490         .change_pte             = mn_change_pte,
 491         .invalidate_page        = mn_invalidate_page,
 492         .invalidate_range_start = mn_invalidate_range_start,
 493         .invalidate_range_end   = mn_invalidate_range_end,
 494 };
 495
 496 static void set_pri_tag_status(struct pasid_state *pasid_state,
 497                                u16 tag, int status)
 498 {
 499         unsigned long flags;
 500
 501         spin_lock_irqsave(&pasid_state->lock, flags);
 502         pasid_state->pri[tag].status = status;
 503         spin_unlock_irqrestore(&pasid_state->lock, flags);
 504 }
 505
 506 static void finish_pri_tag(struct device_state *dev_state,
 507                            struct pasid_state *pasid_state,
 508                            u16 tag)
 509 {
 510         unsigned long flags;
 511
 512         spin_lock_irqsave(&pasid_state->lock, flags);
 513         if (atomic_dec_and_test(&pasid_state->pri[tag].inflight) &&
 514             pasid_state->pri[tag].finish) {
 515                 amd_iommu_complete_ppr(dev_state->pdev, pasid_state->pasid,
 516                                        pasid_state->pri[tag].status, tag);
 517                 pasid_state->pri[tag].finish = false;
 518                 pasid_state->pri[tag].status = PPR_SUCCESS;
 519         }
 520         spin_unlock_irqrestore(&pasid_state->lock, flags);
 521 }
 522
 523 static void do_fault(struct work_struct *work)
 524 {
 525         struct fault *fault = container_of(work, struct fault, work);
 526         int npages, write;
 527         struct page *page;
 528
 529         write = !!(fault->flags & PPR_FAULT_WRITE);
 530
 531         down_read(&fault->state->mm->mmap_sem);
 532         npages = get_user_pages(fault->state->task, fault->state->mm,
 533                                 fault->address, 1, write, 0, &page, NULL);
 534         up_read(&fault->state->mm->mmap_sem);
 535
 536         if (npages == 1) {
 537                 put_page(page);
 538         } else if (fault->dev_state->inv_ppr_cb) {
 539                 int status;
 540
 541                 status = fault->dev_state->inv_ppr_cb(fault->dev_state->pdev,
 542                                                       fault->pasid,
 543                                                       fault->address,
 544                                                       fault->flags);
 545                 switch (status) {
 546                 case AMD_IOMMU_INV_PRI_RSP_SUCCESS:
 547                         set_pri_tag_status(fault->state, fault->tag, PPR_SUCCESS);
 548                         break;
 549                 case AMD_IOMMU_INV_PRI_RSP_INVALID:
 550                         set_pri_tag_status(fault->state, fault->tag, PPR_INVALID);
 551                         break;
 552                 case AMD_IOMMU_INV_PRI_RSP_FAIL:
 553                         set_pri_tag_status(fault->state, fault->tag, PPR_FAILURE);
 554                         break;
 555                 default:
 556                         BUG();
 557                 }
 558         } else {
 559                 set_pri_tag_status(fault->state, fault->tag, PPR_INVALID);
 560         }
 561
 562         finish_pri_tag(fault->dev_state, fault->state, fault->tag);
 563
 564         put_pasid_state(fault->state);
 565
 566         kfree(fault);
 567 }
 568
 569 static int ppr_notifier(struct notifier_block *nb, unsigned long e, void *data)
 570 {
 571         struct amd_iommu_fault *iommu_fault;
 572         struct pasid_state *pasid_state;
 573         struct device_state *dev_state;
 574         unsigned long flags;
 575         struct fault *fault;
 576         bool finish;
 577         u16 tag;
 578         int ret;
 579
 580         iommu_fault = data;
 581         tag         = iommu_fault->tag & 0x1ff;
 582         finish      = (iommu_fault->tag >> 9) & 1;
 583
 584         ret = NOTIFY_DONE;
 585         dev_state = get_device_state(iommu_fault->device_id);
 586         if (dev_state == NULL)
 587                 goto out;
 588
 589         pasid_state = get_pasid_state(dev_state, iommu_fault->pasid);
 590         if (pasid_state == NULL) {
 591                 /* We know the device but not the PASID -> send INVALID */
 592                 amd_iommu_complete_ppr(dev_state->pdev, iommu_fault->pasid,
 593                                        PPR_INVALID, tag);
 594                 goto out_drop_state;
 595         }
 596
 597         spin_lock_irqsave(&pasid_state->lock, flags);
 598         atomic_inc(&pasid_state->pri[tag].inflight);
 599         if (finish)
 600                 pasid_state->pri[tag].finish = true;
 601         spin_unlock_irqrestore(&pasid_state->lock, flags);
 602
 603         fault = kzalloc(sizeof(*fault), GFP_ATOMIC);
 604         if (fault == NULL) {
 605                 /* We are OOM - send success and let the device re-fault */
 606                 finish_pri_tag(dev_state, pasid_state, tag);
 607                 goto out_drop_state;
 608         }
 609
 610         fault->dev_state = dev_state;
 611         fault->address   = iommu_fault->address;
 612         fault->state     = pasid_state;
 613         fault->tag       = tag;
 614         fault->finish    = finish;
 615         fault->flags     = iommu_fault->flags;
 616         INIT_WORK(&fault->work, do_fault);
 617
 618         queue_work(iommu_wq, &fault->work);
 619
 620         ret = NOTIFY_OK;
 621
 622 out_drop_state:
 623         put_device_state(dev_state);
 624
 625 out:
 626         return ret;
 627 }
 628
 629 static struct notifier_block ppr_nb = {
 630         .notifier_call = ppr_notifier,
 631 };
 632
 633 int amd_iommu_bind_pasid(struct pci_dev *pdev, int pasid,
 634                          struct task_struct *task)
 635 {
 636         struct pasid_state *pasid_state;
 637         struct device_state *dev_state;
 638         u16 devid;
 639         int ret;
 640
 641         might_sleep();
 642
 643         if (!amd_iommu_v2_supported())
 644                 return -ENODEV;
 645
 646         devid     = device_id(pdev);
 647         dev_state = get_device_state(devid);
 648
 649         if (dev_state == NULL)
 650                 return -EINVAL;
 651
 652         ret = -EINVAL;
 653         if (pasid < 0 || pasid >= dev_state->max_pasids)
 654                 goto out;
 655
 656         ret = -ENOMEM;
 657         pasid_state = kzalloc(sizeof(*pasid_state), GFP_KERNEL);
 658         if (pasid_state == NULL)
 659                 goto out;
 660
 661         atomic_set(&pasid_state->count, 1);
 662         init_waitqueue_head(&pasid_state->wq);
 663         spin_lock_init(&pasid_state->lock);
 664
 665         pasid_state->task         = task;
 666         pasid_state->mm           = get_task_mm(task);
 667         pasid_state->device_state = dev_state;
 668         pasid_state->pasid        = pasid;
 669         pasid_state->mn.ops       = &iommu_mn;
 670
 671         if (pasid_state->mm == NULL)
 672                 goto out_free;
 673
 674         mmu_notifier_register(&pasid_state->mn, pasid_state->mm);
 675
 676         ret = set_pasid_state(dev_state, pasid_state, pasid);
 677         if (ret)
 678                 goto out_unregister;
 679
 680         ret = amd_iommu_domain_set_gcr3(dev_state->domain, pasid,
 681                                         __pa(pasid_state->mm->pgd));
 682         if (ret)
 683                 goto out_clear_state;
 684
 685         return 0;
 686
 687 out_clear_state:
 688         clear_pasid_state(dev_state, pasid);
 689
 690 out_unregister:
 691         mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm);
 692
 693 out_free:
 694         free_pasid_state(pasid_state);
 695
 696 out:
 697         put_device_state(dev_state);
 698
 699         return ret;
 700 }
 701 EXPORT_SYMBOL(amd_iommu_bind_pasid);
 702
 703 void amd_iommu_unbind_pasid(struct pci_dev *pdev, int pasid)
 704 {
 705         struct pasid_state *pasid_state;
 706         struct device_state *dev_state;
 707         u16 devid;
 708
 709         might_sleep();
 710
 711         if (!amd_iommu_v2_supported())
 712                 return;
 713
 714         devid = device_id(pdev);
 715         dev_state = get_device_state(devid);
 716         if (dev_state == NULL)
 717                 return;
 718
 719         if (pasid < 0 || pasid >= dev_state->max_pasids)
 720                 goto out;
 721
 722         pasid_state = get_pasid_state(dev_state, pasid);
 723         if (pasid_state == NULL)
 724                 goto out;
 725         /*
 726          * Drop reference taken here. We are safe because we still hold
 727          * the reference taken in the amd_iommu_bind_pasid function.
 728          */
 729         put_pasid_state(pasid_state);
 730
 731         /* This will call the mn_release function and unbind the PASID */
 732         mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm);
 733
 734 out:
 735         put_device_state(dev_state);
 736 }
 737 EXPORT_SYMBOL(amd_iommu_unbind_pasid);
 738
 739 int amd_iommu_init_device(struct pci_dev *pdev, int pasids)
 740 {
 741         struct device_state *dev_state;
 742         unsigned long flags;
 743         int ret, tmp;
 744         u16 devid;
 745
 746         might_sleep();
 747
 748         if (!amd_iommu_v2_supported())
 749                 return -ENODEV;
 750
 751         if (pasids <= 0 || pasids > (PASID_MASK + 1))
 752                 return -EINVAL;
 753
 754         devid = device_id(pdev);
 755
 756         dev_state = kzalloc(sizeof(*dev_state), GFP_KERNEL);
 757         if (dev_state == NULL)
 758                 return -ENOMEM;
 759
 760         spin_lock_init(&dev_state->lock);
 761         init_waitqueue_head(&dev_state->wq);
 762         dev_state->pdev  = pdev;
 763         dev_state->devid = devid;
 764
 765         tmp = pasids;
 766         for (dev_state->pasid_levels = 0; (tmp - 1) & ~0x1ff; tmp >>= 9)
 767                 dev_state->pasid_levels += 1;
 768
 769         atomic_set(&dev_state->count, 1);
 770         dev_state->max_pasids = pasids;
 771
 772         ret = -ENOMEM;
 773         dev_state->states = (void *)get_zeroed_page(GFP_KERNEL);
 774         if (dev_state->states == NULL)
 775                 goto out_free_dev_state;
 776
 777         dev_state->domain = iommu_domain_alloc(&pci_bus_type);
 778         if (dev_state->domain == NULL)
 779                 goto out_free_states;
 780
 781         amd_iommu_domain_direct_map(dev_state->domain);
 782
 783         ret = amd_iommu_domain_enable_v2(dev_state->domain, pasids);
 784         if (ret)
 785                 goto out_free_domain;
 786
 787         ret = iommu_attach_device(dev_state->domain, &pdev->dev);
 788         if (ret != 0)
 789                 goto out_free_domain;
 790
 791         spin_lock_irqsave(&state_lock, flags);
 792
 793         if (__get_device_state(devid) != NULL) {
 794                 spin_unlock_irqrestore(&state_lock, flags);
 795                 ret = -EBUSY;
 796                 goto out_free_domain;
 797         }
 798
 799         list_add_tail(&dev_state->list, &state_list);
 800
 801         spin_unlock_irqrestore(&state_lock, flags);
 802
 803         return 0;
 804
 805 out_free_domain:
 806         iommu_domain_free(dev_state->domain);
 807
 808 out_free_states:
 809         free_page((unsigned long)dev_state->states);
 810
 811 out_free_dev_state:
 812         kfree(dev_state);
 813
 814         return ret;
 815 }
 816 EXPORT_SYMBOL(amd_iommu_init_device);
 817
 818 void amd_iommu_free_device(struct pci_dev *pdev)
 819 {
 820         struct device_state *dev_state;
 821         unsigned long flags;
 822         u16 devid;
 823
 824         if (!amd_iommu_v2_supported())
 825                 return;
 826
 827         devid = device_id(pdev);
 828
 829         spin_lock_irqsave(&state_lock, flags);
 830
 831         dev_state = __get_device_state(devid);
 832         if (dev_state == NULL) {
 833                 spin_unlock_irqrestore(&state_lock, flags);
 834                 return;
 835         }
 836
 837         list_del(&dev_state->list);
 838
 839         spin_unlock_irqrestore(&state_lock, flags);
 840
 841         /* Get rid of any remaining pasid states */
 842         free_pasid_states(dev_state);
 843
 844         put_device_state_wait(dev_state);
 845 }
 846 EXPORT_SYMBOL(amd_iommu_free_device);
 847
 848 int amd_iommu_set_invalid_ppr_cb(struct pci_dev *pdev,
 849                                  amd_iommu_invalid_ppr_cb cb)
 850 {
 851         struct device_state *dev_state;
 852         unsigned long flags;
 853         u16 devid;
 854         int ret;
 855
 856         if (!amd_iommu_v2_supported())
 857                 return -ENODEV;
 858
 859         devid = device_id(pdev);
 860
 861         spin_lock_irqsave(&state_lock, flags);
 862
 863         ret = -EINVAL;
 864         dev_state = __get_device_state(devid);
 865         if (dev_state == NULL)
 866                 goto out_unlock;
 867
 868         dev_state->inv_ppr_cb = cb;
 869
 870         ret = 0;
 871
 872 out_unlock:
 873         spin_unlock_irqrestore(&state_lock, flags);
 874
 875         return ret;
 876 }
 877 EXPORT_SYMBOL(amd_iommu_set_invalid_ppr_cb);
 878
 879 int amd_iommu_set_invalidate_ctx_cb(struct pci_dev *pdev,
 880                                     amd_iommu_invalidate_ctx cb)
 881 {
 882         struct device_state *dev_state;
 883         unsigned long flags;
 884         u16 devid;
 885         int ret;
 886
 887         if (!amd_iommu_v2_supported())
 888                 return -ENODEV;
 889
 890         devid = device_id(pdev);
 891
 892         spin_lock_irqsave(&state_lock, flags);
 893
 894         ret = -EINVAL;
 895         dev_state = __get_device_state(devid);
 896         if (dev_state == NULL)
 897                 goto out_unlock;
 898
 899         dev_state->inv_ctx_cb = cb;
 900
 901         ret = 0;
 902
 903 out_unlock:
 904         spin_unlock_irqrestore(&state_lock, flags);
 905
 906         return ret;
 907 }
 908 EXPORT_SYMBOL(amd_iommu_set_invalidate_ctx_cb);
 909
 910 static int __init amd_iommu_v2_init(void)
 911 {
 912         int ret;
 913
 914         pr_info("AMD IOMMUv2 driver by Joerg Roedel <joerg.roedel@amd.com>\n");
 915
 916         if (!amd_iommu_v2_supported()) {
 917                 pr_info("AMD IOMMUv2 functionality not available on this system\n");
 918                 /*
 919                  * Load anyway to provide the symbols to other modules
 920                  * which may use AMD IOMMUv2 optionally.
 921                  */
 922                 return 0;
 923         }
 924
 925         spin_lock_init(&state_lock);
 926
 927         ret = -ENOMEM;
 928         iommu_wq = create_workqueue("amd_iommu_v2");
 929         if (iommu_wq == NULL)
 930                 goto out;
 931
 932         ret = -ENOMEM;
 933         empty_page_table = (u64 *)get_zeroed_page(GFP_KERNEL);
 934         if (empty_page_table == NULL)
 935                 goto out_destroy_wq;
 936
 937         amd_iommu_register_ppr_notifier(&ppr_nb);
 938
 939         return 0;
 940
 941 out_destroy_wq:
 942         destroy_workqueue(iommu_wq);
 943
 944 out:
 945         return ret;
 946 }
 947
 948 static void __exit amd_iommu_v2_exit(void)
 949 {
 950         struct device_state *dev_state;
 951         int i;
 952
 953         if (!amd_iommu_v2_supported())
 954                 return;
 955
 956         amd_iommu_unregister_ppr_notifier(&ppr_nb);
 957
 958         flush_workqueue(iommu_wq);
 959
 960         /*
 961          * The loop below might call flush_workqueue(), so call
 962          * destroy_workqueue() after it
 963          */
 964         for (i = 0; i < MAX_DEVICES; ++i) {
 965                 dev_state = get_device_state(i);
 966
 967                 if (dev_state == NULL)
 968                         continue;
 969
 970                 WARN_ON_ONCE(1);
 971
 972                 put_device_state(dev_state);
 973                 amd_iommu_free_device(dev_state->pdev);
 974         }
 975
 976         destroy_workqueue(iommu_wq);
 977
 978         free_page((unsigned long)empty_page_table);
 979 }
 980
 981 module_init(amd_iommu_v2_init);
 982 module_exit(amd_iommu_v2_exit);