drivers/iommu/arm-smmu.c

   1 /*
   2  * IOMMU API for ARM architected SMMU implementations.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  16  *
  17  * Copyright (C) 2013 ARM Limited
  18  *
  19  * Author: Will Deacon <will.deacon@arm.com>
  20  *
  21  * This driver currently supports:
  22  *      - SMMUv1 and v2 implementations
  23  *      - Stream-matching and stream-indexing
  24  *      - v7/v8 long-descriptor format
  25  *      - Non-secure access to the SMMU
  26  *      - 4k and 64k pages, with contiguous pte hints.
  27  *      - Up to 48-bit addressing (dependent on VA_BITS)
  28  *      - Context fault reporting
  29  */
  30
  31 #define pr_fmt(fmt) "arm-smmu: " fmt
  32
  33 #include <linux/delay.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/err.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/io.h>
  38 #include <linux/iommu.h>
  39 #include <linux/mm.h>
  40 #include <linux/module.h>
  41 #include <linux/of.h>
  42 #include <linux/pci.h>
  43 #include <linux/platform_device.h>
  44 #include <linux/slab.h>
  45 #include <linux/spinlock.h>
  46
  47 #include <linux/amba/bus.h>
  48
  49 #include <asm/pgalloc.h>
  50
  51 /* Maximum number of stream IDs assigned to a single device */
  52 #define MAX_MASTER_STREAMIDS            MAX_PHANDLE_ARGS
  53
  54 /* Maximum number of context banks per SMMU */
  55 #define ARM_SMMU_MAX_CBS                128
  56
  57 /* Maximum number of mapping groups per SMMU */
  58 #define ARM_SMMU_MAX_SMRS               128
  59
  60 /* SMMU global address space */
  61 #define ARM_SMMU_GR0(smmu)              ((smmu)->base)
  62 #define ARM_SMMU_GR1(smmu)              ((smmu)->base + (1 << (smmu)->pgshift))
  63
  64 /*
  65  * SMMU global address space with conditional offset to access secure
  66  * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448,
  67  * nsGFSYNR0: 0x450)
  68  */
  69 #define ARM_SMMU_GR0_NS(smmu)                                           \
  70         ((smmu)->base +                                                 \
  71                 ((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS)       \
  72                         ? 0x400 : 0))
  73
  74 /* Page table bits */
  75 #define ARM_SMMU_PTE_XN                 (((pteval_t)3) << 53)
  76 #define ARM_SMMU_PTE_CONT               (((pteval_t)1) << 52)
  77 #define ARM_SMMU_PTE_AF                 (((pteval_t)1) << 10)
  78 #define ARM_SMMU_PTE_SH_NS              (((pteval_t)0) << 8)
  79 #define ARM_SMMU_PTE_SH_OS              (((pteval_t)2) << 8)
  80 #define ARM_SMMU_PTE_SH_IS              (((pteval_t)3) << 8)
  81 #define ARM_SMMU_PTE_PAGE               (((pteval_t)3) << 0)
  82
  83 #if PAGE_SIZE == SZ_4K
  84 #define ARM_SMMU_PTE_CONT_ENTRIES       16
  85 #elif PAGE_SIZE == SZ_64K
  86 #define ARM_SMMU_PTE_CONT_ENTRIES       32
  87 #else
  88 #define ARM_SMMU_PTE_CONT_ENTRIES       1
  89 #endif
  90
  91 #define ARM_SMMU_PTE_CONT_SIZE          (PAGE_SIZE * ARM_SMMU_PTE_CONT_ENTRIES)
  92 #define ARM_SMMU_PTE_CONT_MASK          (~(ARM_SMMU_PTE_CONT_SIZE - 1))
  93
  94 /* Stage-1 PTE */
  95 #define ARM_SMMU_PTE_AP_UNPRIV          (((pteval_t)1) << 6)
  96 #define ARM_SMMU_PTE_AP_RDONLY          (((pteval_t)2) << 6)
  97 #define ARM_SMMU_PTE_ATTRINDX_SHIFT     2
  98 #define ARM_SMMU_PTE_nG                 (((pteval_t)1) << 11)
  99
 100 /* Stage-2 PTE */
 101 #define ARM_SMMU_PTE_HAP_FAULT          (((pteval_t)0) << 6)
 102 #define ARM_SMMU_PTE_HAP_READ           (((pteval_t)1) << 6)
 103 #define ARM_SMMU_PTE_HAP_WRITE          (((pteval_t)2) << 6)
 104 #define ARM_SMMU_PTE_MEMATTR_OIWB       (((pteval_t)0xf) << 2)
 105 #define ARM_SMMU_PTE_MEMATTR_NC         (((pteval_t)0x5) << 2)
 106 #define ARM_SMMU_PTE_MEMATTR_DEV        (((pteval_t)0x1) << 2)
 107
 108 /* Configuration registers */
 109 #define ARM_SMMU_GR0_sCR0               0x0
 110 #define sCR0_CLIENTPD                   (1 << 0)
 111 #define sCR0_GFRE                       (1 << 1)
 112 #define sCR0_GFIE                       (1 << 2)
 113 #define sCR0_GCFGFRE                    (1 << 4)
 114 #define sCR0_GCFGFIE                    (1 << 5)
 115 #define sCR0_USFCFG                     (1 << 10)
 116 #define sCR0_VMIDPNE                    (1 << 11)
 117 #define sCR0_PTM                        (1 << 12)
 118 #define sCR0_FB                         (1 << 13)
 119 #define sCR0_BSU_SHIFT                  14
 120 #define sCR0_BSU_MASK                   0x3
 121
 122 /* Identification registers */
 123 #define ARM_SMMU_GR0_ID0                0x20
 124 #define ARM_SMMU_GR0_ID1                0x24
 125 #define ARM_SMMU_GR0_ID2                0x28
 126 #define ARM_SMMU_GR0_ID3                0x2c
 127 #define ARM_SMMU_GR0_ID4                0x30
 128 #define ARM_SMMU_GR0_ID5                0x34
 129 #define ARM_SMMU_GR0_ID6                0x38
 130 #define ARM_SMMU_GR0_ID7                0x3c
 131 #define ARM_SMMU_GR0_sGFSR              0x48
 132 #define ARM_SMMU_GR0_sGFSYNR0           0x50
 133 #define ARM_SMMU_GR0_sGFSYNR1           0x54
 134 #define ARM_SMMU_GR0_sGFSYNR2           0x58
 135 #define ARM_SMMU_GR0_PIDR0              0xfe0
 136 #define ARM_SMMU_GR0_PIDR1              0xfe4
 137 #define ARM_SMMU_GR0_PIDR2              0xfe8
 138
 139 #define ID0_S1TS                        (1 << 30)
 140 #define ID0_S2TS                        (1 << 29)
 141 #define ID0_NTS                         (1 << 28)
 142 #define ID0_SMS                         (1 << 27)
 143 #define ID0_PTFS_SHIFT                  24
 144 #define ID0_PTFS_MASK                   0x2
 145 #define ID0_PTFS_V8_ONLY                0x2
 146 #define ID0_CTTW                        (1 << 14)
 147 #define ID0_NUMIRPT_SHIFT               16
 148 #define ID0_NUMIRPT_MASK                0xff
 149 #define ID0_NUMSIDB_SHIFT               9
 150 #define ID0_NUMSIDB_MASK                0xf
 151 #define ID0_NUMSMRG_SHIFT               0
 152 #define ID0_NUMSMRG_MASK                0xff
 153
 154 #define ID1_PAGESIZE                    (1 << 31)
 155 #define ID1_NUMPAGENDXB_SHIFT           28
 156 #define ID1_NUMPAGENDXB_MASK            7
 157 #define ID1_NUMS2CB_SHIFT               16
 158 #define ID1_NUMS2CB_MASK                0xff
 159 #define ID1_NUMCB_SHIFT                 0
 160 #define ID1_NUMCB_MASK                  0xff
 161
 162 #define ID2_OAS_SHIFT                   4
 163 #define ID2_OAS_MASK                    0xf
 164 #define ID2_IAS_SHIFT                   0
 165 #define ID2_IAS_MASK                    0xf
 166 #define ID2_UBS_SHIFT                   8
 167 #define ID2_UBS_MASK                    0xf
 168 #define ID2_PTFS_4K                     (1 << 12)
 169 #define ID2_PTFS_16K                    (1 << 13)
 170 #define ID2_PTFS_64K                    (1 << 14)
 171
 172 #define PIDR2_ARCH_SHIFT                4
 173 #define PIDR2_ARCH_MASK                 0xf
 174
 175 /* Global TLB invalidation */
 176 #define ARM_SMMU_GR0_STLBIALL           0x60
 177 #define ARM_SMMU_GR0_TLBIVMID           0x64
 178 #define ARM_SMMU_GR0_TLBIALLNSNH        0x68
 179 #define ARM_SMMU_GR0_TLBIALLH           0x6c
 180 #define ARM_SMMU_GR0_sTLBGSYNC          0x70
 181 #define ARM_SMMU_GR0_sTLBGSTATUS        0x74
 182 #define sTLBGSTATUS_GSACTIVE            (1 << 0)
 183 #define TLB_LOOP_TIMEOUT                1000000 /* 1s! */
 184
 185 /* Stream mapping registers */
 186 #define ARM_SMMU_GR0_SMR(n)             (0x800 + ((n) << 2))
 187 #define SMR_VALID                       (1 << 31)
 188 #define SMR_MASK_SHIFT                  16
 189 #define SMR_MASK_MASK                   0x7fff
 190 #define SMR_ID_SHIFT                    0
 191 #define SMR_ID_MASK                     0x7fff
 192
 193 #define ARM_SMMU_GR0_S2CR(n)            (0xc00 + ((n) << 2))
 194 #define S2CR_CBNDX_SHIFT                0
 195 #define S2CR_CBNDX_MASK                 0xff
 196 #define S2CR_TYPE_SHIFT                 16
 197 #define S2CR_TYPE_MASK                  0x3
 198 #define S2CR_TYPE_TRANS                 (0 << S2CR_TYPE_SHIFT)
 199 #define S2CR_TYPE_BYPASS                (1 << S2CR_TYPE_SHIFT)
 200 #define S2CR_TYPE_FAULT                 (2 << S2CR_TYPE_SHIFT)
 201
 202 /* Context bank attribute registers */
 203 #define ARM_SMMU_GR1_CBAR(n)            (0x0 + ((n) << 2))
 204 #define CBAR_VMID_SHIFT                 0
 205 #define CBAR_VMID_MASK                  0xff
 206 #define CBAR_S1_BPSHCFG_SHIFT           8
 207 #define CBAR_S1_BPSHCFG_MASK            3
 208 #define CBAR_S1_BPSHCFG_NSH             3
 209 #define CBAR_S1_MEMATTR_SHIFT           12
 210 #define CBAR_S1_MEMATTR_MASK            0xf
 211 #define CBAR_S1_MEMATTR_WB              0xf
 212 #define CBAR_TYPE_SHIFT                 16
 213 #define CBAR_TYPE_MASK                  0x3
 214 #define CBAR_TYPE_S2_TRANS              (0 << CBAR_TYPE_SHIFT)
 215 #define CBAR_TYPE_S1_TRANS_S2_BYPASS    (1 << CBAR_TYPE_SHIFT)
 216 #define CBAR_TYPE_S1_TRANS_S2_FAULT     (2 << CBAR_TYPE_SHIFT)
 217 #define CBAR_TYPE_S1_TRANS_S2_TRANS     (3 << CBAR_TYPE_SHIFT)
 218 #define CBAR_IRPTNDX_SHIFT              24
 219 #define CBAR_IRPTNDX_MASK               0xff
 220
 221 #define ARM_SMMU_GR1_CBA2R(n)           (0x800 + ((n) << 2))
 222 #define CBA2R_RW64_32BIT                (0 << 0)
 223 #define CBA2R_RW64_64BIT                (1 << 0)
 224
 225 /* Translation context bank */
 226 #define ARM_SMMU_CB_BASE(smmu)          ((smmu)->base + ((smmu)->size >> 1))
 227 #define ARM_SMMU_CB(smmu, n)            ((n) * (1 << (smmu)->pgshift))
 228
 229 #define ARM_SMMU_CB_SCTLR               0x0
 230 #define ARM_SMMU_CB_RESUME              0x8
 231 #define ARM_SMMU_CB_TTBCR2              0x10
 232 #define ARM_SMMU_CB_TTBR0_LO            0x20
 233 #define ARM_SMMU_CB_TTBR0_HI            0x24
 234 #define ARM_SMMU_CB_TTBCR               0x30
 235 #define ARM_SMMU_CB_S1_MAIR0            0x38
 236 #define ARM_SMMU_CB_FSR                 0x58
 237 #define ARM_SMMU_CB_FAR_LO              0x60
 238 #define ARM_SMMU_CB_FAR_HI              0x64
 239 #define ARM_SMMU_CB_FSYNR0              0x68
 240 #define ARM_SMMU_CB_S1_TLBIASID         0x610
 241
 242 #define SCTLR_S1_ASIDPNE                (1 << 12)
 243 #define SCTLR_CFCFG                     (1 << 7)
 244 #define SCTLR_CFIE                      (1 << 6)
 245 #define SCTLR_CFRE                      (1 << 5)
 246 #define SCTLR_E                         (1 << 4)
 247 #define SCTLR_AFE                       (1 << 2)
 248 #define SCTLR_TRE                       (1 << 1)
 249 #define SCTLR_M                         (1 << 0)
 250 #define SCTLR_EAE_SBOP                  (SCTLR_AFE | SCTLR_TRE)
 251
 252 #define RESUME_RETRY                    (0 << 0)
 253 #define RESUME_TERMINATE                (1 << 0)
 254
 255 #define TTBCR_EAE                       (1 << 31)
 256
 257 #define TTBCR_PASIZE_SHIFT              16
 258 #define TTBCR_PASIZE_MASK               0x7
 259
 260 #define TTBCR_TG0_4K                    (0 << 14)
 261 #define TTBCR_TG0_64K                   (1 << 14)
 262
 263 #define TTBCR_SH0_SHIFT                 12
 264 #define TTBCR_SH0_MASK                  0x3
 265 #define TTBCR_SH_NS                     0
 266 #define TTBCR_SH_OS                     2
 267 #define TTBCR_SH_IS                     3
 268
 269 #define TTBCR_ORGN0_SHIFT               10
 270 #define TTBCR_IRGN0_SHIFT               8
 271 #define TTBCR_RGN_MASK                  0x3
 272 #define TTBCR_RGN_NC                    0
 273 #define TTBCR_RGN_WBWA                  1
 274 #define TTBCR_RGN_WT                    2
 275 #define TTBCR_RGN_WB                    3
 276
 277 #define TTBCR_SL0_SHIFT                 6
 278 #define TTBCR_SL0_MASK                  0x3
 279 #define TTBCR_SL0_LVL_2                 0
 280 #define TTBCR_SL0_LVL_1                 1
 281
 282 #define TTBCR_T1SZ_SHIFT                16
 283 #define TTBCR_T0SZ_SHIFT                0
 284 #define TTBCR_SZ_MASK                   0xf
 285
 286 #define TTBCR2_SEP_SHIFT                15
 287 #define TTBCR2_SEP_MASK                 0x7
 288
 289 #define TTBCR2_PASIZE_SHIFT             0
 290 #define TTBCR2_PASIZE_MASK              0x7
 291
 292 /* Common definitions for PASize and SEP fields */
 293 #define TTBCR2_ADDR_32                  0
 294 #define TTBCR2_ADDR_36                  1
 295 #define TTBCR2_ADDR_40                  2
 296 #define TTBCR2_ADDR_42                  3
 297 #define TTBCR2_ADDR_44                  4
 298 #define TTBCR2_ADDR_48                  5
 299
 300 #define TTBRn_HI_ASID_SHIFT             16
 301
 302 #define MAIR_ATTR_SHIFT(n)              ((n) << 3)
 303 #define MAIR_ATTR_MASK                  0xff
 304 #define MAIR_ATTR_DEVICE                0x04
 305 #define MAIR_ATTR_NC                    0x44
 306 #define MAIR_ATTR_WBRWA                 0xff
 307 #define MAIR_ATTR_IDX_NC                0
 308 #define MAIR_ATTR_IDX_CACHE             1
 309 #define MAIR_ATTR_IDX_DEV               2
 310
 311 #define FSR_MULTI                       (1 << 31)
 312 #define FSR_SS                          (1 << 30)
 313 #define FSR_UUT                         (1 << 8)
 314 #define FSR_ASF                         (1 << 7)
 315 #define FSR_TLBLKF                      (1 << 6)
 316 #define FSR_TLBMCF                      (1 << 5)
 317 #define FSR_EF                          (1 << 4)
 318 #define FSR_PF                          (1 << 3)
 319 #define FSR_AFF                         (1 << 2)
 320 #define FSR_TF                          (1 << 1)
 321
 322 #define FSR_IGN                         (FSR_AFF | FSR_ASF | \
 323                                          FSR_TLBMCF | FSR_TLBLKF)
 324 #define FSR_FAULT                       (FSR_MULTI | FSR_SS | FSR_UUT | \
 325                                          FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
 326
 327 #define FSYNR0_WNR                      (1 << 4)
 328
 329 static int force_stage;
 330 module_param_named(force_stage, force_stage, int, S_IRUGO | S_IWUSR);
 331 MODULE_PARM_DESC(force_stage,
 332         "Force SMMU mappings to be installed at a particular stage of translation. A value of '1' or '2' forces the corresponding stage. All other values are ignored (i.e. no stage is forced). Note that selecting a specific stage will disable support for nested translation.");
 333
 334 enum arm_smmu_arch_version {
 335         ARM_SMMU_V1 = 1,
 336         ARM_SMMU_V2,
 337 };
 338
 339 struct arm_smmu_smr {
 340         u8                              idx;
 341         u16                             mask;
 342         u16                             id;
 343 };
 344
 345 struct arm_smmu_master_cfg {
 346         int                             num_streamids;
 347         u16                             streamids[MAX_MASTER_STREAMIDS];
 348         struct arm_smmu_smr             *smrs;
 349 };
 350
 351 struct arm_smmu_master {
 352         struct device_node              *of_node;
 353         struct rb_node                  node;
 354         struct arm_smmu_master_cfg      cfg;
 355 };
 356
 357 struct arm_smmu_device {
 358         struct device                   *dev;
 359
 360         void __iomem                    *base;
 361         unsigned long                   size;
 362         unsigned long                   pgshift;
 363
 364 #define ARM_SMMU_FEAT_COHERENT_WALK     (1 << 0)
 365 #define ARM_SMMU_FEAT_STREAM_MATCH      (1 << 1)
 366 #define ARM_SMMU_FEAT_TRANS_S1          (1 << 2)
 367 #define ARM_SMMU_FEAT_TRANS_S2          (1 << 3)
 368 #define ARM_SMMU_FEAT_TRANS_NESTED      (1 << 4)
 369         u32                             features;
 370
 371 #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0)
 372         u32                             options;
 373         enum arm_smmu_arch_version      version;
 374
 375         u32                             num_context_banks;
 376         u32                             num_s2_context_banks;
 377         DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS);
 378         atomic_t                        irptndx;
 379
 380         u32                             num_mapping_groups;
 381         DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS);
 382
 383         unsigned long                   s1_input_size;
 384         unsigned long                   s1_output_size;
 385         unsigned long                   s2_input_size;
 386         unsigned long                   s2_output_size;
 387
 388         u32                             num_global_irqs;
 389         u32                             num_context_irqs;
 390         unsigned int                    *irqs;
 391
 392         struct list_head                list;
 393         struct rb_root                  masters;
 394 };
 395
 396 struct arm_smmu_cfg {
 397         u8                              cbndx;
 398         u8                              irptndx;
 399         u32                             cbar;
 400         pgd_t                           *pgd;
 401 };
 402 #define INVALID_IRPTNDX                 0xff
 403
 404 #define ARM_SMMU_CB_ASID(cfg)           ((cfg)->cbndx)
 405 #define ARM_SMMU_CB_VMID(cfg)           ((cfg)->cbndx + 1)
 406
 407 enum arm_smmu_domain_stage {
 408         ARM_SMMU_DOMAIN_S1 = 0,
 409         ARM_SMMU_DOMAIN_S2,
 410         ARM_SMMU_DOMAIN_NESTED,
 411 };
 412
 413 struct arm_smmu_domain {
 414         struct arm_smmu_device          *smmu;
 415         struct arm_smmu_cfg             cfg;
 416         enum arm_smmu_domain_stage      stage;
 417         spinlock_t                      lock;
 418 };
 419
 420 static DEFINE_SPINLOCK(arm_smmu_devices_lock);
 421 static LIST_HEAD(arm_smmu_devices);
 422
 423 struct arm_smmu_option_prop {
 424         u32 opt;
 425         const char *prop;
 426 };
 427
 428 static struct arm_smmu_option_prop arm_smmu_options[] = {
 429         { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },
 430         { 0, NULL},
 431 };
 432
 433 static void parse_driver_options(struct arm_smmu_device *smmu)
 434 {
 435         int i = 0;
 436
 437         do {
 438                 if (of_property_read_bool(smmu->dev->of_node,
 439                                                 arm_smmu_options[i].prop)) {
 440                         smmu->options |= arm_smmu_options[i].opt;
 441                         dev_notice(smmu->dev, "option %s\n",
 442                                 arm_smmu_options[i].prop);
 443                 }
 444         } while (arm_smmu_options[++i].opt);
 445 }
 446
 447 static struct device_node *dev_get_dev_node(struct device *dev)
 448 {
 449         if (dev_is_pci(dev)) {
 450                 struct pci_bus *bus = to_pci_dev(dev)->bus;
 451
 452                 while (!pci_is_root_bus(bus))
 453                         bus = bus->parent;
 454                 return bus->bridge->parent->of_node;
 455         }
 456
 457         return dev->of_node;
 458 }
 459
 460 static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu,
 461                                                 struct device_node *dev_node)
 462 {
 463         struct rb_node *node = smmu->masters.rb_node;
 464
 465         while (node) {
 466                 struct arm_smmu_master *master;
 467
 468                 master = container_of(node, struct arm_smmu_master, node);
 469
 470                 if (dev_node < master->of_node)
 471                         node = node->rb_left;
 472                 else if (dev_node > master->of_node)
 473                         node = node->rb_right;
 474                 else
 475                         return master;
 476         }
 477
 478         return NULL;
 479 }
 480
 481 static struct arm_smmu_master_cfg *
 482 find_smmu_master_cfg(struct device *dev)
 483 {
 484         struct arm_smmu_master_cfg *cfg = NULL;
 485         struct iommu_group *group = iommu_group_get(dev);
 486
 487         if (group) {
 488                 cfg = iommu_group_get_iommudata(group);
 489                 iommu_group_put(group);
 490         }
 491
 492         return cfg;
 493 }
 494
 495 static int insert_smmu_master(struct arm_smmu_device *smmu,
 496                               struct arm_smmu_master *master)
 497 {
 498         struct rb_node **new, *parent;
 499
 500         new = &smmu->masters.rb_node;
 501         parent = NULL;
 502         while (*new) {
 503                 struct arm_smmu_master *this
 504                         = container_of(*new, struct arm_smmu_master, node);
 505
 506                 parent = *new;
 507                 if (master->of_node < this->of_node)
 508                         new = &((*new)->rb_left);
 509                 else if (master->of_node > this->of_node)
 510                         new = &((*new)->rb_right);
 511                 else
 512                         return -EEXIST;
 513         }
 514
 515         rb_link_node(&master->node, parent, new);
 516         rb_insert_color(&master->node, &smmu->masters);
 517         return 0;
 518 }
 519
 520 static int register_smmu_master(struct arm_smmu_device *smmu,
 521                                 struct device *dev,
 522                                 struct of_phandle_args *masterspec)
 523 {
 524         int i;
 525         struct arm_smmu_master *master;
 526
 527         master = find_smmu_master(smmu, masterspec->np);
 528         if (master) {
 529                 dev_err(dev,
 530                         "rejecting multiple registrations for master device %s\n",
 531                         masterspec->np->name);
 532                 return -EBUSY;
 533         }
 534
 535         if (masterspec->args_count > MAX_MASTER_STREAMIDS) {
 536                 dev_err(dev,
 537                         "reached maximum number (%d) of stream IDs for master device %s\n",
 538                         MAX_MASTER_STREAMIDS, masterspec->np->name);
 539                 return -ENOSPC;
 540         }
 541
 542         master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL);
 543         if (!master)
 544                 return -ENOMEM;
 545
 546         master->of_node                 = masterspec->np;
 547         master->cfg.num_streamids       = masterspec->args_count;
 548
 549         for (i = 0; i < master->cfg.num_streamids; ++i) {
 550                 u16 streamid = masterspec->args[i];
 551
 552                 if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) &&
 553                      (streamid >= smmu->num_mapping_groups)) {
 554                         dev_err(dev,
 555                                 "stream ID for master device %s greater than maximum allowed (%d)\n",
 556                                 masterspec->np->name, smmu->num_mapping_groups);
 557                         return -ERANGE;
 558                 }
 559                 master->cfg.streamids[i] = streamid;
 560         }
 561         return insert_smmu_master(smmu, master);
 562 }
 563
 564 static struct arm_smmu_device *find_smmu_for_device(struct device *dev)
 565 {
 566         struct arm_smmu_device *smmu;
 567         struct arm_smmu_master *master = NULL;
 568         struct device_node *dev_node = dev_get_dev_node(dev);
 569
 570         spin_lock(&arm_smmu_devices_lock);
 571         list_for_each_entry(smmu, &arm_smmu_devices, list) {
 572                 master = find_smmu_master(smmu, dev_node);
 573                 if (master)
 574                         break;
 575         }
 576         spin_unlock(&arm_smmu_devices_lock);
 577
 578         return master ? smmu : NULL;
 579 }
 580
 581 static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end)
 582 {
 583         int idx;
 584
 585         do {
 586                 idx = find_next_zero_bit(map, end, start);
 587                 if (idx == end)
 588                         return -ENOSPC;
 589         } while (test_and_set_bit(idx, map));
 590
 591         return idx;
 592 }
 593
 594 static void __arm_smmu_free_bitmap(unsigned long *map, int idx)
 595 {
 596         clear_bit(idx, map);
 597 }
 598
 599 /* Wait for any pending TLB invalidations to complete */
 600 static void arm_smmu_tlb_sync(struct arm_smmu_device *smmu)
 601 {
 602         int count = 0;
 603         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
 604
 605         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC);
 606         while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS)
 607                & sTLBGSTATUS_GSACTIVE) {
 608                 cpu_relax();
 609                 if (++count == TLB_LOOP_TIMEOUT) {
 610                         dev_err_ratelimited(smmu->dev,
 611                         "TLB sync timed out -- SMMU may be deadlocked\n");
 612                         return;
 613                 }
 614                 udelay(1);
 615         }
 616 }
 617
 618 static void arm_smmu_tlb_inv_context(struct arm_smmu_domain *smmu_domain)
 619 {
 620         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 621         struct arm_smmu_device *smmu = smmu_domain->smmu;
 622         void __iomem *base = ARM_SMMU_GR0(smmu);
 623         bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
 624
 625         if (stage1) {
 626                 base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
 627                 writel_relaxed(ARM_SMMU_CB_ASID(cfg),
 628                                base + ARM_SMMU_CB_S1_TLBIASID);
 629         } else {
 630                 base = ARM_SMMU_GR0(smmu);
 631                 writel_relaxed(ARM_SMMU_CB_VMID(cfg),
 632                                base + ARM_SMMU_GR0_TLBIVMID);
 633         }
 634
 635         arm_smmu_tlb_sync(smmu);
 636 }
 637
 638 static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
 639 {
 640         int flags, ret;
 641         u32 fsr, far, fsynr, resume;
 642         unsigned long iova;
 643         struct iommu_domain *domain = dev;
 644         struct arm_smmu_domain *smmu_domain = domain->priv;
 645         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 646         struct arm_smmu_device *smmu = smmu_domain->smmu;
 647         void __iomem *cb_base;
 648
 649         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
 650         fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
 651
 652         if (!(fsr & FSR_FAULT))
 653                 return IRQ_NONE;
 654
 655         if (fsr & FSR_IGN)
 656                 dev_err_ratelimited(smmu->dev,
 657                                     "Unexpected context fault (fsr 0x%x)\n",
 658                                     fsr);
 659
 660         fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
 661         flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
 662
 663         far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO);
 664         iova = far;
 665 #ifdef CONFIG_64BIT
 666         far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI);
 667         iova |= ((unsigned long)far << 32);
 668 #endif
 669
 670         if (!report_iommu_fault(domain, smmu->dev, iova, flags)) {
 671                 ret = IRQ_HANDLED;
 672                 resume = RESUME_RETRY;
 673         } else {
 674                 dev_err_ratelimited(smmu->dev,
 675                     "Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n",
 676                     iova, fsynr, cfg->cbndx);
 677                 ret = IRQ_NONE;
 678                 resume = RESUME_TERMINATE;
 679         }
 680
 681         /* Clear the faulting FSR */
 682         writel(fsr, cb_base + ARM_SMMU_CB_FSR);
 683
 684         /* Retry or terminate any stalled transactions */
 685         if (fsr & FSR_SS)
 686                 writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME);
 687
 688         return ret;
 689 }
 690
 691 static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
 692 {
 693         u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
 694         struct arm_smmu_device *smmu = dev;
 695         void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu);
 696
 697         gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
 698         gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
 699         gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
 700         gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
 701
 702         if (!gfsr)
 703                 return IRQ_NONE;
 704
 705         dev_err_ratelimited(smmu->dev,
 706                 "Unexpected global fault, this could be serious\n");
 707         dev_err_ratelimited(smmu->dev,
 708                 "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n",
 709                 gfsr, gfsynr0, gfsynr1, gfsynr2);
 710
 711         writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR);
 712         return IRQ_HANDLED;
 713 }
 714
 715 static void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr,
 716                                    size_t size)
 717 {
 718         unsigned long offset = (unsigned long)addr & ~PAGE_MASK;
 719
 720
 721         /* Ensure new page tables are visible to the hardware walker */
 722         if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) {
 723                 dsb(ishst);
 724         } else {
 725                 /*
 726                  * If the SMMU can't walk tables in the CPU caches, treat them
 727                  * like non-coherent DMA since we need to flush the new entries
 728                  * all the way out to memory. There's no possibility of
 729                  * recursion here as the SMMU table walker will not be wired
 730                  * through another SMMU.
 731                  */
 732                 dma_map_page(smmu->dev, virt_to_page(addr), offset, size,
 733                                 DMA_TO_DEVICE);
 734         }
 735 }
 736
 737 static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
 738 {
 739         u32 reg;
 740         bool stage1;
 741         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 742         struct arm_smmu_device *smmu = smmu_domain->smmu;
 743         void __iomem *cb_base, *gr0_base, *gr1_base;
 744
 745         gr0_base = ARM_SMMU_GR0(smmu);
 746         gr1_base = ARM_SMMU_GR1(smmu);
 747         stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
 748         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
 749
 750         /* CBAR */
 751         reg = cfg->cbar;
 752         if (smmu->version == ARM_SMMU_V1)
 753                 reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT;
 754
 755         /*
 756          * Use the weakest shareability/memory types, so they are
 757          * overridden by the ttbcr/pte.
 758          */
 759         if (stage1) {
 760                 reg |= (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) |
 761                         (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
 762         } else {
 763                 reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT;
 764         }
 765         writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx));
 766
 767         if (smmu->version > ARM_SMMU_V1) {
 768                 /* CBA2R */
 769 #ifdef CONFIG_64BIT
 770                 reg = CBA2R_RW64_64BIT;
 771 #else
 772                 reg = CBA2R_RW64_32BIT;
 773 #endif
 774                 writel_relaxed(reg,
 775                                gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx));
 776
 777                 /* TTBCR2 */
 778                 switch (smmu->s1_input_size) {
 779                 case 32:
 780                         reg = (TTBCR2_ADDR_32 << TTBCR2_SEP_SHIFT);
 781                         break;
 782                 case 36:
 783                         reg = (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT);
 784                         break;
 785                 case 39:
 786                 case 40:
 787                         reg = (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT);
 788                         break;
 789                 case 42:
 790                         reg = (TTBCR2_ADDR_42 << TTBCR2_SEP_SHIFT);
 791                         break;
 792                 case 44:
 793                         reg = (TTBCR2_ADDR_44 << TTBCR2_SEP_SHIFT);
 794                         break;
 795                 case 48:
 796                         reg = (TTBCR2_ADDR_48 << TTBCR2_SEP_SHIFT);
 797                         break;
 798                 }
 799
 800                 switch (smmu->s1_output_size) {
 801                 case 32:
 802                         reg |= (TTBCR2_ADDR_32 << TTBCR2_PASIZE_SHIFT);
 803                         break;
 804                 case 36:
 805                         reg |= (TTBCR2_ADDR_36 << TTBCR2_PASIZE_SHIFT);
 806                         break;
 807                 case 39:
 808                 case 40:
 809                         reg |= (TTBCR2_ADDR_40 << TTBCR2_PASIZE_SHIFT);
 810                         break;
 811                 case 42:
 812                         reg |= (TTBCR2_ADDR_42 << TTBCR2_PASIZE_SHIFT);
 813                         break;
 814                 case 44:
 815                         reg |= (TTBCR2_ADDR_44 << TTBCR2_PASIZE_SHIFT);
 816                         break;
 817                 case 48:
 818                         reg |= (TTBCR2_ADDR_48 << TTBCR2_PASIZE_SHIFT);
 819                         break;
 820                 }
 821
 822                 if (stage1)
 823                         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2);
 824         }
 825
 826         /* TTBR0 */
 827         arm_smmu_flush_pgtable(smmu, cfg->pgd,
 828                                PTRS_PER_PGD * sizeof(pgd_t));
 829         reg = __pa(cfg->pgd);
 830         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO);
 831         reg = (phys_addr_t)__pa(cfg->pgd) >> 32;
 832         if (stage1)
 833                 reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT;
 834         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI);
 835
 836         /*
 837          * TTBCR
 838          * We use long descriptor, with inner-shareable WBWA tables in TTBR0.
 839          */
 840         if (smmu->version > ARM_SMMU_V1) {
 841                 if (PAGE_SIZE == SZ_4K)
 842                         reg = TTBCR_TG0_4K;
 843                 else
 844                         reg = TTBCR_TG0_64K;
 845
 846                 if (!stage1) {
 847                         reg |= (64 - smmu->s2_input_size) << TTBCR_T0SZ_SHIFT;
 848
 849                         switch (smmu->s2_output_size) {
 850                         case 32:
 851                                 reg |= (TTBCR2_ADDR_32 << TTBCR_PASIZE_SHIFT);
 852                                 break;
 853                         case 36:
 854                                 reg |= (TTBCR2_ADDR_36 << TTBCR_PASIZE_SHIFT);
 855                                 break;
 856                         case 40:
 857                                 reg |= (TTBCR2_ADDR_40 << TTBCR_PASIZE_SHIFT);
 858                                 break;
 859                         case 42:
 860                                 reg |= (TTBCR2_ADDR_42 << TTBCR_PASIZE_SHIFT);
 861                                 break;
 862                         case 44:
 863                                 reg |= (TTBCR2_ADDR_44 << TTBCR_PASIZE_SHIFT);
 864                                 break;
 865                         case 48:
 866                                 reg |= (TTBCR2_ADDR_48 << TTBCR_PASIZE_SHIFT);
 867                                 break;
 868                         }
 869                 } else {
 870                         reg |= (64 - smmu->s1_input_size) << TTBCR_T0SZ_SHIFT;
 871                 }
 872         } else {
 873                 reg = 0;
 874         }
 875
 876         reg |= TTBCR_EAE |
 877               (TTBCR_SH_IS << TTBCR_SH0_SHIFT) |
 878               (TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) |
 879               (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT);
 880
 881         if (!stage1)
 882                 reg |= (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT);
 883
 884         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
 885
 886         /* MAIR0 (stage-1 only) */
 887         if (stage1) {
 888                 reg = (MAIR_ATTR_NC << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_NC)) |
 889                       (MAIR_ATTR_WBRWA << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_CACHE)) |
 890                       (MAIR_ATTR_DEVICE << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_DEV));
 891                 writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0);
 892         }
 893
 894         /* SCTLR */
 895         reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP;
 896         if (stage1)
 897                 reg |= SCTLR_S1_ASIDPNE;
 898 #ifdef __BIG_ENDIAN
 899         reg |= SCTLR_E;
 900 #endif
 901         writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR);
 902 }
 903
 904 static int arm_smmu_init_domain_context(struct iommu_domain *domain,
 905                                         struct arm_smmu_device *smmu)
 906 {
 907         int irq, start, ret = 0;
 908         unsigned long flags;
 909         struct arm_smmu_domain *smmu_domain = domain->priv;
 910         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 911
 912         spin_lock_irqsave(&smmu_domain->lock, flags);
 913         if (smmu_domain->smmu)
 914                 goto out_unlock;
 915
 916         /*
 917          * Mapping the requested stage onto what we support is surprisingly
 918          * complicated, mainly because the spec allows S1+S2 SMMUs without
 919          * support for nested translation. That means we end up with the
 920          * following table:
 921          *
 922          * Requested        Supported        Actual
 923          *     S1               N              S1
 924          *     S1             S1+S2            S1
 925          *     S1               S2             S2
 926          *     S1               S1             S1
 927          *     N                N              N
 928          *     N              S1+S2            S2
 929          *     N                S2             S2
 930          *     N                S1             S1
 931          *
 932          * Note that you can't actually request stage-2 mappings.
 933          */
 934         if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1))
 935                 smmu_domain->stage = ARM_SMMU_DOMAIN_S2;
 936         if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2))
 937                 smmu_domain->stage = ARM_SMMU_DOMAIN_S1;
 938
 939         switch (smmu_domain->stage) {
 940         case ARM_SMMU_DOMAIN_S1:
 941                 cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
 942                 start = smmu->num_s2_context_banks;
 943                 break;
 944         case ARM_SMMU_DOMAIN_NESTED:
 945                 /*
 946                  * We will likely want to change this if/when KVM gets
 947                  * involved.
 948                  */
 949         case ARM_SMMU_DOMAIN_S2:
 950                 cfg->cbar = CBAR_TYPE_S2_TRANS;
 951                 start = 0;
 952                 break;
 953         default:
 954                 ret = -EINVAL;
 955                 goto out_unlock;
 956         }
 957
 958         ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,
 959                                       smmu->num_context_banks);
 960         if (IS_ERR_VALUE(ret))
 961                 goto out_unlock;
 962
 963         cfg->cbndx = ret;
 964         if (smmu->version == ARM_SMMU_V1) {
 965                 cfg->irptndx = atomic_inc_return(&smmu->irptndx);
 966                 cfg->irptndx %= smmu->num_context_irqs;
 967         } else {
 968                 cfg->irptndx = cfg->cbndx;
 969         }
 970
 971         ACCESS_ONCE(smmu_domain->smmu) = smmu;
 972         arm_smmu_init_context_bank(smmu_domain);
 973         spin_unlock_irqrestore(&smmu_domain->lock, flags);
 974
 975         irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
 976         ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED,
 977                           "arm-smmu-context-fault", domain);
 978         if (IS_ERR_VALUE(ret)) {
 979                 dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n",
 980                         cfg->irptndx, irq);
 981                 cfg->irptndx = INVALID_IRPTNDX;
 982         }
 983
 984         return 0;
 985
 986 out_unlock:
 987         spin_unlock_irqrestore(&smmu_domain->lock, flags);
 988         return ret;
 989 }
 990
 991 static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
 992 {
 993         struct arm_smmu_domain *smmu_domain = domain->priv;
 994         struct arm_smmu_device *smmu = smmu_domain->smmu;
 995         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 996         void __iomem *cb_base;
 997         int irq;
 998
 999         if (!smmu)
1000                 return;
1001
1002         /* Disable the context bank and nuke the TLB before freeing it. */
1003         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
1004         writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
1005         arm_smmu_tlb_inv_context(smmu_domain);
1006
1007         if (cfg->irptndx != INVALID_IRPTNDX) {
1008                 irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
1009                 free_irq(irq, domain);
1010         }
1011
1012         __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx);
1013 }
1014
1015 static int arm_smmu_domain_init(struct iommu_domain *domain)
1016 {
1017         struct arm_smmu_domain *smmu_domain;
1018         pgd_t *pgd;
1019
1020         /*
1021          * Allocate the domain and initialise some of its data structures.
1022          * We can't really do anything meaningful until we've added a
1023          * master.
1024          */
1025         smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL);
1026         if (!smmu_domain)
1027                 return -ENOMEM;
1028
1029         pgd = kcalloc(PTRS_PER_PGD, sizeof(pgd_t), GFP_KERNEL);
1030         if (!pgd)
1031                 goto out_free_domain;
1032         smmu_domain->cfg.pgd = pgd;
1033
1034         spin_lock_init(&smmu_domain->lock);
1035         domain->priv = smmu_domain;
1036         return 0;
1037
1038 out_free_domain:
1039         kfree(smmu_domain);
1040         return -ENOMEM;
1041 }
1042
1043 static void arm_smmu_free_ptes(pmd_t *pmd)
1044 {
1045         pgtable_t table = pmd_pgtable(*pmd);
1046
1047         __free_page(table);
1048 }
1049
1050 static void arm_smmu_free_pmds(pud_t *pud)
1051 {
1052         int i;
1053         pmd_t *pmd, *pmd_base = pmd_offset(pud, 0);
1054
1055         pmd = pmd_base;
1056         for (i = 0; i < PTRS_PER_PMD; ++i) {
1057                 if (pmd_none(*pmd))
1058                         continue;
1059
1060                 arm_smmu_free_ptes(pmd);
1061                 pmd++;
1062         }
1063
1064         pmd_free(NULL, pmd_base);
1065 }
1066
1067 static void arm_smmu_free_puds(pgd_t *pgd)
1068 {
1069         int i;
1070         pud_t *pud, *pud_base = pud_offset(pgd, 0);
1071
1072         pud = pud_base;
1073         for (i = 0; i < PTRS_PER_PUD; ++i) {
1074                 if (pud_none(*pud))
1075                         continue;
1076
1077                 arm_smmu_free_pmds(pud);
1078                 pud++;
1079         }
1080
1081         pud_free(NULL, pud_base);
1082 }
1083
1084 static void arm_smmu_free_pgtables(struct arm_smmu_domain *smmu_domain)
1085 {
1086         int i;
1087         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
1088         pgd_t *pgd, *pgd_base = cfg->pgd;
1089
1090         /*
1091          * Recursively free the page tables for this domain. We don't
1092          * care about speculative TLB filling because the tables should
1093          * not be active in any context bank at this point (SCTLR.M is 0).
1094          */
1095         pgd = pgd_base;
1096         for (i = 0; i < PTRS_PER_PGD; ++i) {
1097                 if (pgd_none(*pgd))
1098                         continue;
1099                 arm_smmu_free_puds(pgd);
1100                 pgd++;
1101         }
1102
1103         kfree(pgd_base);
1104 }
1105
1106 static void arm_smmu_domain_destroy(struct iommu_domain *domain)
1107 {
1108         struct arm_smmu_domain *smmu_domain = domain->priv;
1109
1110         /*
1111          * Free the domain resources. We assume that all devices have
1112          * already been detached.
1113          */
1114         arm_smmu_destroy_domain_context(domain);
1115         arm_smmu_free_pgtables(smmu_domain);
1116         kfree(smmu_domain);
1117 }
1118
1119 static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu,
1120                                           struct arm_smmu_master_cfg *cfg)
1121 {
1122         int i;
1123         struct arm_smmu_smr *smrs;
1124         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1125
1126         if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH))
1127                 return 0;
1128
1129         if (cfg->smrs)
1130                 return -EEXIST;
1131
1132         smrs = kmalloc_array(cfg->num_streamids, sizeof(*smrs), GFP_KERNEL);
1133         if (!smrs) {
1134                 dev_err(smmu->dev, "failed to allocate %d SMRs\n",
1135                         cfg->num_streamids);
1136                 return -ENOMEM;
1137         }
1138
1139         /* Allocate the SMRs on the SMMU */
1140         for (i = 0; i < cfg->num_streamids; ++i) {
1141                 int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0,
1142                                                   smmu->num_mapping_groups);
1143                 if (IS_ERR_VALUE(idx)) {
1144                         dev_err(smmu->dev, "failed to allocate free SMR\n");
1145                         goto err_free_smrs;
1146                 }
1147
1148                 smrs[i] = (struct arm_smmu_smr) {
1149                         .idx    = idx,
1150                         .mask   = 0, /* We don't currently share SMRs */
1151                         .id     = cfg->streamids[i],
1152                 };
1153         }
1154
1155         /* It worked! Now, poke the actual hardware */
1156         for (i = 0; i < cfg->num_streamids; ++i) {
1157                 u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT |
1158                           smrs[i].mask << SMR_MASK_SHIFT;
1159                 writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx));
1160         }
1161
1162         cfg->smrs = smrs;
1163         return 0;
1164
1165 err_free_smrs:
1166         while (--i >= 0)
1167                 __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx);
1168         kfree(smrs);
1169         return -ENOSPC;
1170 }
1171
1172 static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu,
1173                                       struct arm_smmu_master_cfg *cfg)
1174 {
1175         int i;
1176         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1177         struct arm_smmu_smr *smrs = cfg->smrs;
1178
1179         if (!smrs)
1180                 return;
1181
1182         /* Invalidate the SMRs before freeing back to the allocator */
1183         for (i = 0; i < cfg->num_streamids; ++i) {
1184                 u8 idx = smrs[i].idx;
1185
1186                 writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx));
1187                 __arm_smmu_free_bitmap(smmu->smr_map, idx);
1188         }
1189
1190         cfg->smrs = NULL;
1191         kfree(smrs);
1192 }
1193
1194 static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
1195                                       struct arm_smmu_master_cfg *cfg)
1196 {
1197         int i, ret;
1198         struct arm_smmu_device *smmu = smmu_domain->smmu;
1199         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1200
1201         /* Devices in an IOMMU group may already be configured */
1202         ret = arm_smmu_master_configure_smrs(smmu, cfg);
1203         if (ret)
1204                 return ret == -EEXIST ? 0 : ret;
1205
1206         for (i = 0; i < cfg->num_streamids; ++i) {
1207                 u32 idx, s2cr;
1208
1209                 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];
1210                 s2cr = S2CR_TYPE_TRANS |
1211                        (smmu_domain->cfg.cbndx << S2CR_CBNDX_SHIFT);
1212                 writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx));
1213         }
1214
1215         return 0;
1216 }
1217
1218 static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain,
1219                                           struct arm_smmu_master_cfg *cfg)
1220 {
1221         int i;
1222         struct arm_smmu_device *smmu = smmu_domain->smmu;
1223         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1224
1225         /* An IOMMU group is torn down by the first device to be removed */
1226         if ((smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) && !cfg->smrs)
1227                 return;
1228
1229         /*
1230          * We *must* clear the S2CR first, because freeing the SMR means
1231          * that it can be re-allocated immediately.
1232          */
1233         for (i = 0; i < cfg->num_streamids; ++i) {
1234                 u32 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];
1235
1236                 writel_relaxed(S2CR_TYPE_BYPASS,
1237                                gr0_base + ARM_SMMU_GR0_S2CR(idx));
1238         }
1239
1240         arm_smmu_master_free_smrs(smmu, cfg);
1241 }
1242
1243 static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
1244 {
1245         int ret;
1246         struct arm_smmu_domain *smmu_domain = domain->priv;
1247         struct arm_smmu_device *smmu, *dom_smmu;
1248         struct arm_smmu_master_cfg *cfg;
1249
1250         smmu = find_smmu_for_device(dev);
1251         if (!smmu) {
1252                 dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n");
1253                 return -ENXIO;
1254         }
1255
1256         if (dev->archdata.iommu) {
1257                 dev_err(dev, "already attached to IOMMU domain\n");
1258                 return -EEXIST;
1259         }
1260
1261         /*
1262          * Sanity check the domain. We don't support domains across
1263          * different SMMUs.
1264          */
1265         dom_smmu = ACCESS_ONCE(smmu_domain->smmu);
1266         if (!dom_smmu) {
1267                 /* Now that we have a master, we can finalise the domain */
1268                 ret = arm_smmu_init_domain_context(domain, smmu);
1269                 if (IS_ERR_VALUE(ret))
1270                         return ret;
1271
1272                 dom_smmu = smmu_domain->smmu;
1273         }
1274
1275         if (dom_smmu != smmu) {
1276                 dev_err(dev,
1277                         "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n",
1278                         dev_name(smmu_domain->smmu->dev), dev_name(smmu->dev));
1279                 return -EINVAL;
1280         }
1281
1282         /* Looks ok, so add the device to the domain */
1283         cfg = find_smmu_master_cfg(dev);
1284         if (!cfg)
1285                 return -ENODEV;
1286
1287         ret = arm_smmu_domain_add_master(smmu_domain, cfg);
1288         if (!ret)
1289                 dev->archdata.iommu = domain;
1290         return ret;
1291 }
1292
1293 static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev)
1294 {
1295         struct arm_smmu_domain *smmu_domain = domain->priv;
1296         struct arm_smmu_master_cfg *cfg;
1297
1298         cfg = find_smmu_master_cfg(dev);
1299         if (!cfg)
1300                 return;
1301
1302         dev->archdata.iommu = NULL;
1303         arm_smmu_domain_remove_master(smmu_domain, cfg);
1304 }
1305
1306 static bool arm_smmu_pte_is_contiguous_range(unsigned long addr,
1307                                              unsigned long end)
1308 {
1309         return !(addr & ~ARM_SMMU_PTE_CONT_MASK) &&
1310                 (addr + ARM_SMMU_PTE_CONT_SIZE <= end);
1311 }
1312
1313 static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
1314                                    unsigned long addr, unsigned long end,
1315                                    unsigned long pfn, int prot, int stage)
1316 {
1317         pte_t *pte, *start;
1318         pteval_t pteval = ARM_SMMU_PTE_PAGE | ARM_SMMU_PTE_AF;
1319
1320         if (pmd_none(*pmd)) {
1321                 /* Allocate a new set of tables */
1322                 pgtable_t table = alloc_page(GFP_ATOMIC|__GFP_ZERO);
1323
1324                 if (!table)
1325                         return -ENOMEM;
1326
1327                 arm_smmu_flush_pgtable(smmu, page_address(table), PAGE_SIZE);
1328                 pmd_populate(NULL, pmd, table);
1329                 arm_smmu_flush_pgtable(smmu, pmd, sizeof(*pmd));
1330         }
1331
1332         if (stage == 1) {
1333                 pteval |= ARM_SMMU_PTE_AP_UNPRIV | ARM_SMMU_PTE_nG;
1334                 if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ))
1335                         pteval |= ARM_SMMU_PTE_AP_RDONLY;
1336
1337                 if (prot & IOMMU_CACHE)
1338                         pteval |= (MAIR_ATTR_IDX_CACHE <<
1339                                    ARM_SMMU_PTE_ATTRINDX_SHIFT);
1340         } else {
1341                 pteval |= ARM_SMMU_PTE_HAP_FAULT;
1342                 if (prot & IOMMU_READ)
1343                         pteval |= ARM_SMMU_PTE_HAP_READ;
1344                 if (prot & IOMMU_WRITE)
1345                         pteval |= ARM_SMMU_PTE_HAP_WRITE;
1346                 if (prot & IOMMU_CACHE)
1347                         pteval |= ARM_SMMU_PTE_MEMATTR_OIWB;
1348                 else
1349                         pteval |= ARM_SMMU_PTE_MEMATTR_NC;
1350         }
1351
1352         if (prot & IOMMU_NOEXEC)
1353                 pteval |= ARM_SMMU_PTE_XN;
1354
1355         /* If no access, create a faulting entry to avoid TLB fills */
1356         if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
1357                 pteval &= ~ARM_SMMU_PTE_PAGE;
1358
1359         pteval |= ARM_SMMU_PTE_SH_IS;
1360         start = pmd_page_vaddr(*pmd) + pte_index(addr);
1361         pte = start;
1362
1363         /*
1364          * Install the page table entries. This is fairly complicated
1365          * since we attempt to make use of the contiguous hint in the
1366          * ptes where possible. The contiguous hint indicates a series
1367          * of ARM_SMMU_PTE_CONT_ENTRIES ptes mapping a physically
1368          * contiguous region with the following constraints:
1369          *
1370          *   - The region start is aligned to ARM_SMMU_PTE_CONT_SIZE
1371          *   - Each pte in the region has the contiguous hint bit set
1372          *
1373          * This complicates unmapping (also handled by this code, when
1374          * neither IOMMU_READ or IOMMU_WRITE are set) because it is
1375          * possible, yet highly unlikely, that a client may unmap only
1376          * part of a contiguous range. This requires clearing of the
1377          * contiguous hint bits in the range before installing the new
1378          * faulting entries.
1379          *
1380          * Note that re-mapping an address range without first unmapping
1381          * it is not supported, so TLB invalidation is not required here
1382          * and is instead performed at unmap and domain-init time.
1383          */
1384         do {
1385                 int i = 1;
1386
1387                 pteval &= ~ARM_SMMU_PTE_CONT;
1388
1389                 if (arm_smmu_pte_is_contiguous_range(addr, end)) {
1390                         i = ARM_SMMU_PTE_CONT_ENTRIES;
1391                         pteval |= ARM_SMMU_PTE_CONT;
1392                 } else if (pte_val(*pte) &
1393                            (ARM_SMMU_PTE_CONT | ARM_SMMU_PTE_PAGE)) {
1394                         int j;
1395                         pte_t *cont_start;
1396                         unsigned long idx = pte_index(addr);
1397
1398                         idx &= ~(ARM_SMMU_PTE_CONT_ENTRIES - 1);
1399                         cont_start = pmd_page_vaddr(*pmd) + idx;
1400                         for (j = 0; j < ARM_SMMU_PTE_CONT_ENTRIES; ++j)
1401                                 pte_val(*(cont_start + j)) &=
1402                                         ~ARM_SMMU_PTE_CONT;
1403
1404                         arm_smmu_flush_pgtable(smmu, cont_start,
1405                                                sizeof(*pte) *
1406                                                ARM_SMMU_PTE_CONT_ENTRIES);
1407                 }
1408
1409                 do {
1410                         *pte = pfn_pte(pfn, __pgprot(pteval));
1411                 } while (pte++, pfn++, addr += PAGE_SIZE, --i);
1412         } while (addr != end);
1413
1414         arm_smmu_flush_pgtable(smmu, start, sizeof(*pte) * (pte - start));
1415         return 0;
1416 }
1417
1418 static int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud,
1419                                    unsigned long addr, unsigned long end,
1420                                    phys_addr_t phys, int prot, int stage)
1421 {
1422         int ret;
1423         pmd_t *pmd;
1424         unsigned long next, pfn = __phys_to_pfn(phys);
1425
1426 #ifndef __PAGETABLE_PMD_FOLDED
1427         if (pud_none(*pud)) {
1428                 pmd = (pmd_t *)get_zeroed_page(GFP_ATOMIC);
1429                 if (!pmd)
1430                         return -ENOMEM;
1431
1432                 arm_smmu_flush_pgtable(smmu, pmd, PAGE_SIZE);
1433                 pud_populate(NULL, pud, pmd);
1434                 arm_smmu_flush_pgtable(smmu, pud, sizeof(*pud));
1435
1436                 pmd += pmd_index(addr);
1437         } else
1438 #endif
1439                 pmd = pmd_offset(pud, addr);
1440
1441         do {
1442                 next = pmd_addr_end(addr, end);
1443                 ret = arm_smmu_alloc_init_pte(smmu, pmd, addr, next, pfn,
1444                                               prot, stage);
1445                 phys += next - addr;
1446                 pfn = __phys_to_pfn(phys);
1447         } while (pmd++, addr = next, addr < end);
1448
1449         return ret;
1450 }
1451
1452 static int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd,
1453                                    unsigned long addr, unsigned long end,
1454                                    phys_addr_t phys, int prot, int stage)
1455 {
1456         int ret = 0;
1457         pud_t *pud;
1458         unsigned long next;
1459
1460 #ifndef __PAGETABLE_PUD_FOLDED
1461         if (pgd_none(*pgd)) {
1462                 pud = (pud_t *)get_zeroed_page(GFP_ATOMIC);
1463                 if (!pud)
1464                         return -ENOMEM;
1465
1466                 arm_smmu_flush_pgtable(smmu, pud, PAGE_SIZE);
1467                 pgd_populate(NULL, pgd, pud);
1468                 arm_smmu_flush_pgtable(smmu, pgd, sizeof(*pgd));
1469
1470                 pud += pud_index(addr);
1471         } else
1472 #endif
1473                 pud = pud_offset(pgd, addr);
1474
1475         do {
1476                 next = pud_addr_end(addr, end);
1477                 ret = arm_smmu_alloc_init_pmd(smmu, pud, addr, next, phys,
1478                                               prot, stage);
1479                 phys += next - addr;
1480         } while (pud++, addr = next, addr < end);
1481
1482         return ret;
1483 }
1484
1485 static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
1486                                    unsigned long iova, phys_addr_t paddr,
1487                                    size_t size, int prot)
1488 {
1489         int ret, stage;
1490         unsigned long end;
1491         phys_addr_t input_mask, output_mask;
1492         struct arm_smmu_device *smmu = smmu_domain->smmu;
1493         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
1494         pgd_t *pgd = cfg->pgd;
1495         unsigned long flags;
1496
1497         if (cfg->cbar == CBAR_TYPE_S2_TRANS) {
1498                 stage = 2;
1499                 input_mask = (1ULL << smmu->s2_input_size) - 1;
1500                 output_mask = (1ULL << smmu->s2_output_size) - 1;
1501         } else {
1502                 stage = 1;
1503                 input_mask = (1ULL << smmu->s1_input_size) - 1;
1504                 output_mask = (1ULL << smmu->s1_output_size) - 1;
1505         }
1506
1507         if (!pgd)
1508                 return -EINVAL;
1509
1510         if (size & ~PAGE_MASK)
1511                 return -EINVAL;
1512
1513         if ((phys_addr_t)iova & ~input_mask)
1514                 return -ERANGE;
1515
1516         if (paddr & ~output_mask)
1517                 return -ERANGE;
1518
1519         spin_lock_irqsave(&smmu_domain->lock, flags);
1520         pgd += pgd_index(iova);
1521         end = iova + size;
1522         do {
1523                 unsigned long next = pgd_addr_end(iova, end);
1524
1525                 ret = arm_smmu_alloc_init_pud(smmu, pgd, iova, next, paddr,
1526                                               prot, stage);
1527                 if (ret)
1528                         goto out_unlock;
1529
1530                 paddr += next - iova;
1531                 iova = next;
1532         } while (pgd++, iova != end);
1533
1534 out_unlock:
1535         spin_unlock_irqrestore(&smmu_domain->lock, flags);
1536
1537         return ret;
1538 }
1539
1540 static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
1541                         phys_addr_t paddr, size_t size, int prot)
1542 {
1543         struct arm_smmu_domain *smmu_domain = domain->priv;
1544
1545         if (!smmu_domain)
1546                 return -ENODEV;
1547
1548         return arm_smmu_handle_mapping(smmu_domain, iova, paddr, size, prot);
1549 }
1550
1551 static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
1552                              size_t size)
1553 {
1554         int ret;
1555         struct arm_smmu_domain *smmu_domain = domain->priv;
1556
1557         ret = arm_smmu_handle_mapping(smmu_domain, iova, 0, size, 0);
1558         arm_smmu_tlb_inv_context(smmu_domain);
1559         return ret ? 0 : size;
1560 }
1561
1562 static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
1563                                          dma_addr_t iova)
1564 {
1565         pgd_t *pgdp, pgd;
1566         pud_t pud;
1567         pmd_t pmd;
1568         pte_t pte;
1569         struct arm_smmu_domain *smmu_domain = domain->priv;
1570         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
1571
1572         pgdp = cfg->pgd;
1573         if (!pgdp)
1574                 return 0;
1575
1576         pgd = *(pgdp + pgd_index(iova));
1577         if (pgd_none(pgd))
1578                 return 0;
1579
1580         pud = *pud_offset(&pgd, iova);
1581         if (pud_none(pud))
1582                 return 0;
1583
1584         pmd = *pmd_offset(&pud, iova);
1585         if (pmd_none(pmd))
1586                 return 0;
1587
1588         pte = *(pmd_page_vaddr(pmd) + pte_index(iova));
1589         if (pte_none(pte))
1590                 return 0;
1591
1592         return __pfn_to_phys(pte_pfn(pte)) | (iova & ~PAGE_MASK);
1593 }
1594
1595 static bool arm_smmu_capable(enum iommu_cap cap)
1596 {
1597         switch (cap) {
1598         case IOMMU_CAP_CACHE_COHERENCY:
1599                 /*
1600                  * Return true here as the SMMU can always send out coherent
1601                  * requests.
1602                  */
1603                 return true;
1604         case IOMMU_CAP_INTR_REMAP:
1605                 return true; /* MSIs are just memory writes */
1606         case IOMMU_CAP_NOEXEC:
1607                 return true;
1608         default:
1609                 return false;
1610         }
1611 }
1612
1613 static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *data)
1614 {
1615         *((u16 *)data) = alias;
1616         return 0; /* Continue walking */
1617 }
1618
1619 static void __arm_smmu_release_pci_iommudata(void *data)
1620 {
1621         kfree(data);
1622 }
1623
1624 static int arm_smmu_add_device(struct device *dev)
1625 {
1626         struct arm_smmu_device *smmu;
1627         struct arm_smmu_master_cfg *cfg;
1628         struct iommu_group *group;
1629         void (*releasefn)(void *) = NULL;
1630         int ret;
1631
1632         smmu = find_smmu_for_device(dev);
1633         if (!smmu)
1634                 return -ENODEV;
1635
1636         group = iommu_group_alloc();
1637         if (IS_ERR(group)) {
1638                 dev_err(dev, "Failed to allocate IOMMU group\n");
1639                 return PTR_ERR(group);
1640         }
1641
1642         if (dev_is_pci(dev)) {
1643                 struct pci_dev *pdev = to_pci_dev(dev);
1644
1645                 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1646                 if (!cfg) {
1647                         ret = -ENOMEM;
1648                         goto out_put_group;
1649                 }
1650
1651                 cfg->num_streamids = 1;
1652                 /*
1653                  * Assume Stream ID == Requester ID for now.
1654                  * We need a way to describe the ID mappings in FDT.
1655                  */
1656                 pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid,
1657                                        &cfg->streamids[0]);
1658                 releasefn = __arm_smmu_release_pci_iommudata;
1659         } else {
1660                 struct arm_smmu_master *master;
1661
1662                 master = find_smmu_master(smmu, dev->of_node);
1663                 if (!master) {
1664                         ret = -ENODEV;
1665                         goto out_put_group;
1666                 }
1667
1668                 cfg = &master->cfg;
1669         }
1670
1671         iommu_group_set_iommudata(group, cfg, releasefn);
1672         ret = iommu_group_add_device(group, dev);
1673
1674 out_put_group:
1675         iommu_group_put(group);
1676         return ret;
1677 }
1678
1679 static void arm_smmu_remove_device(struct device *dev)
1680 {
1681         iommu_group_remove_device(dev);
1682 }
1683
1684 static int arm_smmu_domain_get_attr(struct iommu_domain *domain,
1685                                     enum iommu_attr attr, void *data)
1686 {
1687         struct arm_smmu_domain *smmu_domain = domain->priv;
1688
1689         switch (attr) {
1690         case DOMAIN_ATTR_NESTING:
1691                 *(int *)data = (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED);
1692                 return 0;
1693         default:
1694                 return -ENODEV;
1695         }
1696 }
1697
1698 static int arm_smmu_domain_set_attr(struct iommu_domain *domain,
1699                                     enum iommu_attr attr, void *data)
1700 {
1701         struct arm_smmu_domain *smmu_domain = domain->priv;
1702
1703         switch (attr) {
1704         case DOMAIN_ATTR_NESTING:
1705                 if (smmu_domain->smmu)
1706                         return -EPERM;
1707                 if (*(int *)data)
1708                         smmu_domain->stage = ARM_SMMU_DOMAIN_NESTED;
1709                 else
1710                         smmu_domain->stage = ARM_SMMU_DOMAIN_S1;
1711
1712                 return 0;
1713         default:
1714                 return -ENODEV;
1715         }
1716 }
1717
1718 static const struct iommu_ops arm_smmu_ops = {
1719         .capable                = arm_smmu_capable,
1720         .domain_init            = arm_smmu_domain_init,
1721         .domain_destroy         = arm_smmu_domain_destroy,
1722         .attach_dev             = arm_smmu_attach_dev,
1723         .detach_dev             = arm_smmu_detach_dev,
1724         .map                    = arm_smmu_map,
1725         .unmap                  = arm_smmu_unmap,
1726         .map_sg                 = default_iommu_map_sg,
1727         .iova_to_phys           = arm_smmu_iova_to_phys,
1728         .add_device             = arm_smmu_add_device,
1729         .remove_device          = arm_smmu_remove_device,
1730         .domain_get_attr        = arm_smmu_domain_get_attr,
1731         .domain_set_attr        = arm_smmu_domain_set_attr,
1732         .pgsize_bitmap          = (SECTION_SIZE |
1733                                    ARM_SMMU_PTE_CONT_SIZE |
1734                                    PAGE_SIZE),
1735 };
1736
1737 static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
1738 {
1739         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1740         void __iomem *cb_base;
1741         int i = 0;
1742         u32 reg;
1743
1744         /* clear global FSR */
1745         reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
1746         writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
1747
1748         /* Mark all SMRn as invalid and all S2CRn as bypass */
1749         for (i = 0; i < smmu->num_mapping_groups; ++i) {
1750                 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_SMR(i));
1751                 writel_relaxed(S2CR_TYPE_BYPASS,
1752                         gr0_base + ARM_SMMU_GR0_S2CR(i));
1753         }
1754
1755         /* Make sure all context banks are disabled and clear CB_FSR  */
1756         for (i = 0; i < smmu->num_context_banks; ++i) {
1757                 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i);
1758                 writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
1759                 writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR);
1760         }
1761
1762         /* Invalidate the TLB, just in case */
1763         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_STLBIALL);
1764         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);
1765         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);
1766
1767         reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1768
1769         /* Enable fault reporting */
1770         reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE);
1771
1772         /* Disable TLB broadcasting. */
1773         reg |= (sCR0_VMIDPNE | sCR0_PTM);
1774
1775         /* Enable client access, but bypass when no mapping is found */
1776         reg &= ~(sCR0_CLIENTPD | sCR0_USFCFG);
1777
1778         /* Disable forced broadcasting */
1779         reg &= ~sCR0_FB;
1780
1781         /* Don't upgrade barriers */
1782         reg &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT);
1783
1784         /* Push the button */
1785         arm_smmu_tlb_sync(smmu);
1786         writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1787 }
1788
1789 static int arm_smmu_id_size_to_bits(int size)
1790 {
1791         switch (size) {
1792         case 0:
1793                 return 32;
1794         case 1:
1795                 return 36;
1796         case 2:
1797                 return 40;
1798         case 3:
1799                 return 42;
1800         case 4:
1801                 return 44;
1802         case 5:
1803         default:
1804                 return 48;
1805         }
1806 }
1807
1808 static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
1809 {
1810         unsigned long size;
1811         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1812         u32 id;
1813
1814         dev_notice(smmu->dev, "probing hardware configuration...\n");
1815         dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version);
1816
1817         /* ID0 */
1818         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0);
1819 #ifndef CONFIG_64BIT
1820         if (((id >> ID0_PTFS_SHIFT) & ID0_PTFS_MASK) == ID0_PTFS_V8_ONLY) {
1821                 dev_err(smmu->dev, "\tno v7 descriptor support!\n");
1822                 return -ENODEV;
1823         }
1824 #endif
1825
1826         /* Restrict available stages based on module parameter */
1827         if (force_stage == 1)
1828                 id &= ~(ID0_S2TS | ID0_NTS);
1829         else if (force_stage == 2)
1830                 id &= ~(ID0_S1TS | ID0_NTS);
1831
1832         if (id & ID0_S1TS) {
1833                 smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
1834                 dev_notice(smmu->dev, "\tstage 1 translation\n");
1835         }
1836
1837         if (id & ID0_S2TS) {
1838                 smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
1839                 dev_notice(smmu->dev, "\tstage 2 translation\n");
1840         }
1841
1842         if (id & ID0_NTS) {
1843                 smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED;
1844                 dev_notice(smmu->dev, "\tnested translation\n");
1845         }
1846
1847         if (!(smmu->features &
1848                 (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2))) {
1849                 dev_err(smmu->dev, "\tno translation support!\n");
1850                 return -ENODEV;
1851         }
1852
1853         if (id & ID0_CTTW) {
1854                 smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK;
1855                 dev_notice(smmu->dev, "\tcoherent table walk\n");
1856         }
1857
1858         if (id & ID0_SMS) {
1859                 u32 smr, sid, mask;
1860
1861                 smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH;
1862                 smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) &
1863                                            ID0_NUMSMRG_MASK;
1864                 if (smmu->num_mapping_groups == 0) {
1865                         dev_err(smmu->dev,
1866                                 "stream-matching supported, but no SMRs present!\n");
1867                         return -ENODEV;
1868                 }
1869
1870                 smr = SMR_MASK_MASK << SMR_MASK_SHIFT;
1871                 smr |= (SMR_ID_MASK << SMR_ID_SHIFT);
1872                 writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));
1873                 smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0));
1874
1875                 mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK;
1876                 sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK;
1877                 if ((mask & sid) != sid) {
1878                         dev_err(smmu->dev,
1879                                 "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n",
1880                                 mask, sid);
1881                         return -ENODEV;
1882                 }
1883
1884                 dev_notice(smmu->dev,
1885                            "\tstream matching with %u register groups, mask 0x%x",
1886                            smmu->num_mapping_groups, mask);
1887         } else {
1888                 smmu->num_mapping_groups = (id >> ID0_NUMSIDB_SHIFT) &
1889                                            ID0_NUMSIDB_MASK;
1890         }
1891
1892         /* ID1 */
1893         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1);
1894         smmu->pgshift = (id & ID1_PAGESIZE) ? 16 : 12;
1895
1896         /* Check for size mismatch of SMMU address space from mapped region */
1897         size = 1 <<
1898                 (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1);
1899         size *= 2 << smmu->pgshift;
1900         if (smmu->size != size)
1901                 dev_warn(smmu->dev,
1902                         "SMMU address space size (0x%lx) differs from mapped region size (0x%lx)!\n",
1903                         size, smmu->size);
1904
1905         smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) &
1906                                       ID1_NUMS2CB_MASK;
1907         smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK;
1908         if (smmu->num_s2_context_banks > smmu->num_context_banks) {
1909                 dev_err(smmu->dev, "impossible number of S2 context banks!\n");
1910                 return -ENODEV;
1911         }
1912         dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n",
1913                    smmu->num_context_banks, smmu->num_s2_context_banks);
1914
1915         /* ID2 */
1916         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2);
1917         size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK);
1918         smmu->s1_output_size = min_t(unsigned long, PHYS_MASK_SHIFT, size);
1919
1920         /* Stage-2 input size limited due to pgd allocation (PTRS_PER_PGD) */
1921 #ifdef CONFIG_64BIT
1922         smmu->s2_input_size = min_t(unsigned long, VA_BITS, size);
1923 #else
1924         smmu->s2_input_size = min(32UL, size);
1925 #endif
1926
1927         /* The stage-2 output mask is also applied for bypass */
1928         size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);
1929         smmu->s2_output_size = min_t(unsigned long, PHYS_MASK_SHIFT, size);
1930
1931         if (smmu->version == ARM_SMMU_V1) {
1932                 smmu->s1_input_size = 32;
1933         } else {
1934 #ifdef CONFIG_64BIT
1935                 size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK;
1936                 size = min(VA_BITS, arm_smmu_id_size_to_bits(size));
1937 #else
1938                 size = 32;
1939 #endif
1940                 smmu->s1_input_size = size;
1941
1942                 if ((PAGE_SIZE == SZ_4K && !(id & ID2_PTFS_4K)) ||
1943                     (PAGE_SIZE == SZ_64K && !(id & ID2_PTFS_64K)) ||
1944                     (PAGE_SIZE != SZ_4K && PAGE_SIZE != SZ_64K)) {
1945                         dev_err(smmu->dev, "CPU page size 0x%lx unsupported\n",
1946                                 PAGE_SIZE);
1947                         return -ENODEV;
1948                 }
1949         }
1950
1951         if (smmu->features & ARM_SMMU_FEAT_TRANS_S1)
1952                 dev_notice(smmu->dev, "\tStage-1: %lu-bit VA -> %lu-bit IPA\n",
1953                            smmu->s1_input_size, smmu->s1_output_size);
1954
1955         if (smmu->features & ARM_SMMU_FEAT_TRANS_S2)
1956                 dev_notice(smmu->dev, "\tStage-2: %lu-bit IPA -> %lu-bit PA\n",
1957                            smmu->s2_input_size, smmu->s2_output_size);
1958
1959         return 0;
1960 }
1961
1962 static const struct of_device_id arm_smmu_of_match[] = {
1963         { .compatible = "arm,smmu-v1", .data = (void *)ARM_SMMU_V1 },
1964         { .compatible = "arm,smmu-v2", .data = (void *)ARM_SMMU_V2 },
1965         { .compatible = "arm,mmu-400", .data = (void *)ARM_SMMU_V1 },
1966         { .compatible = "arm,mmu-401", .data = (void *)ARM_SMMU_V1 },
1967         { .compatible = "arm,mmu-500", .data = (void *)ARM_SMMU_V2 },
1968         { },
1969 };
1970 MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
1971
1972 static int arm_smmu_device_dt_probe(struct platform_device *pdev)
1973 {
1974         const struct of_device_id *of_id;
1975         struct resource *res;
1976         struct arm_smmu_device *smmu;
1977         struct device *dev = &pdev->dev;
1978         struct rb_node *node;
1979         struct of_phandle_args masterspec;
1980         int num_irqs, i, err;
1981
1982         smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
1983         if (!smmu) {
1984                 dev_err(dev, "failed to allocate arm_smmu_device\n");
1985                 return -ENOMEM;
1986         }
1987         smmu->dev = dev;
1988
1989         of_id = of_match_node(arm_smmu_of_match, dev->of_node);
1990         smmu->version = (enum arm_smmu_arch_version)of_id->data;
1991
1992         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1993         smmu->base = devm_ioremap_resource(dev, res);
1994         if (IS_ERR(smmu->base))
1995                 return PTR_ERR(smmu->base);
1996         smmu->size = resource_size(res);
1997
1998         if (of_property_read_u32(dev->of_node, "#global-interrupts",
1999                                  &smmu->num_global_irqs)) {
2000                 dev_err(dev, "missing #global-interrupts property\n");
2001                 return -ENODEV;
2002         }
2003
2004         num_irqs = 0;
2005         while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) {
2006                 num_irqs++;
2007                 if (num_irqs > smmu->num_global_irqs)
2008                         smmu->num_context_irqs++;
2009         }
2010
2011         if (!smmu->num_context_irqs) {
2012                 dev_err(dev, "found %d interrupts but expected at least %d\n",
2013                         num_irqs, smmu->num_global_irqs + 1);
2014                 return -ENODEV;
2015         }
2016
2017         smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs,
2018                                   GFP_KERNEL);
2019         if (!smmu->irqs) {
2020                 dev_err(dev, "failed to allocate %d irqs\n", num_irqs);
2021                 return -ENOMEM;
2022         }
2023
2024         for (i = 0; i < num_irqs; ++i) {
2025                 int irq = platform_get_irq(pdev, i);
2026
2027                 if (irq < 0) {
2028                         dev_err(dev, "failed to get irq index %d\n", i);
2029                         return -ENODEV;
2030                 }
2031                 smmu->irqs[i] = irq;
2032         }
2033
2034         err = arm_smmu_device_cfg_probe(smmu);
2035         if (err)
2036                 return err;
2037
2038         i = 0;
2039         smmu->masters = RB_ROOT;
2040         while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters",
2041                                            "#stream-id-cells", i,
2042                                            &masterspec)) {
2043                 err = register_smmu_master(smmu, dev, &masterspec);
2044                 if (err) {
2045                         dev_err(dev, "failed to add master %s\n",
2046                                 masterspec.np->name);
2047                         goto out_put_masters;
2048                 }
2049
2050                 i++;
2051         }
2052         dev_notice(dev, "registered %d master devices\n", i);
2053
2054         parse_driver_options(smmu);
2055
2056         if (smmu->version > ARM_SMMU_V1 &&
2057             smmu->num_context_banks != smmu->num_context_irqs) {
2058                 dev_err(dev,
2059                         "found only %d context interrupt(s) but %d required\n",
2060                         smmu->num_context_irqs, smmu->num_context_banks);
2061                 err = -ENODEV;
2062                 goto out_put_masters;
2063         }
2064
2065         for (i = 0; i < smmu->num_global_irqs; ++i) {
2066                 err = request_irq(smmu->irqs[i],
2067                                   arm_smmu_global_fault,
2068                                   IRQF_SHARED,
2069                                   "arm-smmu global fault",
2070                                   smmu);
2071                 if (err) {
2072                         dev_err(dev, "failed to request global IRQ %d (%u)\n",
2073                                 i, smmu->irqs[i]);
2074                         goto out_free_irqs;
2075                 }
2076         }
2077
2078         INIT_LIST_HEAD(&smmu->list);
2079         spin_lock(&arm_smmu_devices_lock);
2080         list_add(&smmu->list, &arm_smmu_devices);
2081         spin_unlock(&arm_smmu_devices_lock);
2082
2083         arm_smmu_device_reset(smmu);
2084         return 0;
2085
2086 out_free_irqs:
2087         while (i--)
2088                 free_irq(smmu->irqs[i], smmu);
2089
2090 out_put_masters:
2091         for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
2092                 struct arm_smmu_master *master
2093                         = container_of(node, struct arm_smmu_master, node);
2094                 of_node_put(master->of_node);
2095         }
2096
2097         return err;
2098 }
2099
2100 static int arm_smmu_device_remove(struct platform_device *pdev)
2101 {
2102         int i;
2103         struct device *dev = &pdev->dev;
2104         struct arm_smmu_device *curr, *smmu = NULL;
2105         struct rb_node *node;
2106
2107         spin_lock(&arm_smmu_devices_lock);
2108         list_for_each_entry(curr, &arm_smmu_devices, list) {
2109                 if (curr->dev == dev) {
2110                         smmu = curr;
2111                         list_del(&smmu->list);
2112                         break;
2113                 }
2114         }
2115         spin_unlock(&arm_smmu_devices_lock);
2116
2117         if (!smmu)
2118                 return -ENODEV;
2119
2120         for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
2121                 struct arm_smmu_master *master
2122                         = container_of(node, struct arm_smmu_master, node);
2123                 of_node_put(master->of_node);
2124         }
2125
2126         if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS))
2127                 dev_err(dev, "removing device with active domains!\n");
2128
2129         for (i = 0; i < smmu->num_global_irqs; ++i)
2130                 free_irq(smmu->irqs[i], smmu);
2131
2132         /* Turn the thing off */
2133         writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
2134         return 0;
2135 }
2136
2137 static struct platform_driver arm_smmu_driver = {
2138         .driver = {
2139                 .name           = "arm-smmu",
2140                 .of_match_table = of_match_ptr(arm_smmu_of_match),
2141         },
2142         .probe  = arm_smmu_device_dt_probe,
2143         .remove = arm_smmu_device_remove,
2144 };
2145
2146 static int __init arm_smmu_init(void)
2147 {
2148         struct device_node *np;
2149         int ret;
2150
2151         /*
2152          * Play nice with systems that don't have an ARM SMMU by checking that
2153          * an ARM SMMU exists in the system before proceeding with the driver
2154          * and IOMMU bus operation registration.
2155          */
2156         np = of_find_matching_node(NULL, arm_smmu_of_match);
2157         if (!np)
2158                 return 0;
2159
2160         of_node_put(np);
2161
2162         ret = platform_driver_register(&arm_smmu_driver);
2163         if (ret)
2164                 return ret;
2165
2166         /* Oh, for a proper bus abstraction */
2167         if (!iommu_present(&platform_bus_type))
2168                 bus_set_iommu(&platform_bus_type, &arm_smmu_ops);
2169
2170 #ifdef CONFIG_ARM_AMBA
2171         if (!iommu_present(&amba_bustype))
2172                 bus_set_iommu(&amba_bustype, &arm_smmu_ops);
2173 #endif
2174
2175 #ifdef CONFIG_PCI
2176         if (!iommu_present(&pci_bus_type))
2177                 bus_set_iommu(&pci_bus_type, &arm_smmu_ops);
2178 #endif
2179
2180         return 0;
2181 }
2182
2183 static void __exit arm_smmu_exit(void)
2184 {
2185         return platform_driver_unregister(&arm_smmu_driver);
2186 }
2187
2188 subsys_initcall(arm_smmu_init);
2189 module_exit(arm_smmu_exit);
2190
2191 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
2192 MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
2193 MODULE_LICENSE("GPL v2");