drivers/iommu/arm-smmu.c

   1 /*
   2  * IOMMU API for ARM architected SMMU implementations.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  16  *
  17  * Copyright (C) 2013 ARM Limited
  18  *
  19  * Author: Will Deacon <will.deacon@arm.com>
  20  *
  21  * This driver currently supports:
  22  *      - SMMUv1 and v2 implementations
  23  *      - Stream-matching and stream-indexing
  24  *      - v7/v8 long-descriptor format
  25  *      - Non-secure access to the SMMU
  26  *      - 4k and 64k pages, with contiguous pte hints.
  27  *      - Up to 39-bit addressing
  28  *      - Context fault reporting
  29  */
  30
  31 #define pr_fmt(fmt) "arm-smmu: " fmt
  32
  33 #include <linux/delay.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/err.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/io.h>
  38 #include <linux/iommu.h>
  39 #include <linux/mm.h>
  40 #include <linux/module.h>
  41 #include <linux/of.h>
  42 #include <linux/platform_device.h>
  43 #include <linux/slab.h>
  44 #include <linux/spinlock.h>
  45
  46 #include <linux/amba/bus.h>
  47
  48 #include <asm/pgalloc.h>
  49
  50 /* Maximum number of stream IDs assigned to a single device */
  51 #define MAX_MASTER_STREAMIDS            8
  52
  53 /* Maximum number of context banks per SMMU */
  54 #define ARM_SMMU_MAX_CBS                128
  55
  56 /* Maximum number of mapping groups per SMMU */
  57 #define ARM_SMMU_MAX_SMRS               128
  58
  59 /* SMMU global address space */
  60 #define ARM_SMMU_GR0(smmu)              ((smmu)->base)
  61 #define ARM_SMMU_GR1(smmu)              ((smmu)->base + (smmu)->pagesize)
  62
  63 /* Page table bits */
  64 #define ARM_SMMU_PTE_PAGE               (((pteval_t)3) << 0)
  65 #define ARM_SMMU_PTE_CONT               (((pteval_t)1) << 52)
  66 #define ARM_SMMU_PTE_AF                 (((pteval_t)1) << 10)
  67 #define ARM_SMMU_PTE_SH_NS              (((pteval_t)0) << 8)
  68 #define ARM_SMMU_PTE_SH_OS              (((pteval_t)2) << 8)
  69 #define ARM_SMMU_PTE_SH_IS              (((pteval_t)3) << 8)
  70
  71 #if PAGE_SIZE == SZ_4K
  72 #define ARM_SMMU_PTE_CONT_ENTRIES       16
  73 #elif PAGE_SIZE == SZ_64K
  74 #define ARM_SMMU_PTE_CONT_ENTRIES       32
  75 #else
  76 #define ARM_SMMU_PTE_CONT_ENTRIES       1
  77 #endif
  78
  79 #define ARM_SMMU_PTE_CONT_SIZE          (PAGE_SIZE * ARM_SMMU_PTE_CONT_ENTRIES)
  80 #define ARM_SMMU_PTE_CONT_MASK          (~(ARM_SMMU_PTE_CONT_SIZE - 1))
  81 #define ARM_SMMU_PTE_HWTABLE_SIZE       (PTRS_PER_PTE * sizeof(pte_t))
  82
  83 /* Stage-1 PTE */
  84 #define ARM_SMMU_PTE_AP_UNPRIV          (((pteval_t)1) << 6)
  85 #define ARM_SMMU_PTE_AP_RDONLY          (((pteval_t)2) << 6)
  86 #define ARM_SMMU_PTE_ATTRINDX_SHIFT     2
  87 #define ARM_SMMU_PTE_nG                 (((pteval_t)1) << 11)
  88
  89 /* Stage-2 PTE */
  90 #define ARM_SMMU_PTE_HAP_FAULT          (((pteval_t)0) << 6)
  91 #define ARM_SMMU_PTE_HAP_READ           (((pteval_t)1) << 6)
  92 #define ARM_SMMU_PTE_HAP_WRITE          (((pteval_t)2) << 6)
  93 #define ARM_SMMU_PTE_MEMATTR_OIWB       (((pteval_t)0xf) << 2)
  94 #define ARM_SMMU_PTE_MEMATTR_NC         (((pteval_t)0x5) << 2)
  95 #define ARM_SMMU_PTE_MEMATTR_DEV        (((pteval_t)0x1) << 2)
  96
  97 /* Configuration registers */
  98 #define ARM_SMMU_GR0_sCR0               0x0
  99 #define sCR0_CLIENTPD                   (1 << 0)
 100 #define sCR0_GFRE                       (1 << 1)
 101 #define sCR0_GFIE                       (1 << 2)
 102 #define sCR0_GCFGFRE                    (1 << 4)
 103 #define sCR0_GCFGFIE                    (1 << 5)
 104 #define sCR0_USFCFG                     (1 << 10)
 105 #define sCR0_VMIDPNE                    (1 << 11)
 106 #define sCR0_PTM                        (1 << 12)
 107 #define sCR0_FB                         (1 << 13)
 108 #define sCR0_BSU_SHIFT                  14
 109 #define sCR0_BSU_MASK                   0x3
 110
 111 /* Identification registers */
 112 #define ARM_SMMU_GR0_ID0                0x20
 113 #define ARM_SMMU_GR0_ID1                0x24
 114 #define ARM_SMMU_GR0_ID2                0x28
 115 #define ARM_SMMU_GR0_ID3                0x2c
 116 #define ARM_SMMU_GR0_ID4                0x30
 117 #define ARM_SMMU_GR0_ID5                0x34
 118 #define ARM_SMMU_GR0_ID6                0x38
 119 #define ARM_SMMU_GR0_ID7                0x3c
 120 #define ARM_SMMU_GR0_sGFSR              0x48
 121 #define ARM_SMMU_GR0_sGFSYNR0           0x50
 122 #define ARM_SMMU_GR0_sGFSYNR1           0x54
 123 #define ARM_SMMU_GR0_sGFSYNR2           0x58
 124 #define ARM_SMMU_GR0_PIDR0              0xfe0
 125 #define ARM_SMMU_GR0_PIDR1              0xfe4
 126 #define ARM_SMMU_GR0_PIDR2              0xfe8
 127
 128 #define ID0_S1TS                        (1 << 30)
 129 #define ID0_S2TS                        (1 << 29)
 130 #define ID0_NTS                         (1 << 28)
 131 #define ID0_SMS                         (1 << 27)
 132 #define ID0_PTFS_SHIFT                  24
 133 #define ID0_PTFS_MASK                   0x2
 134 #define ID0_PTFS_V8_ONLY                0x2
 135 #define ID0_CTTW                        (1 << 14)
 136 #define ID0_NUMIRPT_SHIFT               16
 137 #define ID0_NUMIRPT_MASK                0xff
 138 #define ID0_NUMSMRG_SHIFT               0
 139 #define ID0_NUMSMRG_MASK                0xff
 140
 141 #define ID1_PAGESIZE                    (1 << 31)
 142 #define ID1_NUMPAGENDXB_SHIFT           28
 143 #define ID1_NUMPAGENDXB_MASK            7
 144 #define ID1_NUMS2CB_SHIFT               16
 145 #define ID1_NUMS2CB_MASK                0xff
 146 #define ID1_NUMCB_SHIFT                 0
 147 #define ID1_NUMCB_MASK                  0xff
 148
 149 #define ID2_OAS_SHIFT                   4
 150 #define ID2_OAS_MASK                    0xf
 151 #define ID2_IAS_SHIFT                   0
 152 #define ID2_IAS_MASK                    0xf
 153 #define ID2_UBS_SHIFT                   8
 154 #define ID2_UBS_MASK                    0xf
 155 #define ID2_PTFS_4K                     (1 << 12)
 156 #define ID2_PTFS_16K                    (1 << 13)
 157 #define ID2_PTFS_64K                    (1 << 14)
 158
 159 #define PIDR2_ARCH_SHIFT                4
 160 #define PIDR2_ARCH_MASK                 0xf
 161
 162 /* Global TLB invalidation */
 163 #define ARM_SMMU_GR0_STLBIALL           0x60
 164 #define ARM_SMMU_GR0_TLBIVMID           0x64
 165 #define ARM_SMMU_GR0_TLBIALLNSNH        0x68
 166 #define ARM_SMMU_GR0_TLBIALLH           0x6c
 167 #define ARM_SMMU_GR0_sTLBGSYNC          0x70
 168 #define ARM_SMMU_GR0_sTLBGSTATUS        0x74
 169 #define sTLBGSTATUS_GSACTIVE            (1 << 0)
 170 #define TLB_LOOP_TIMEOUT                1000000 /* 1s! */
 171
 172 /* Stream mapping registers */
 173 #define ARM_SMMU_GR0_SMR(n)             (0x800 + ((n) << 2))
 174 #define SMR_VALID                       (1 << 31)
 175 #define SMR_MASK_SHIFT                  16
 176 #define SMR_MASK_MASK                   0x7fff
 177 #define SMR_ID_SHIFT                    0
 178 #define SMR_ID_MASK                     0x7fff
 179
 180 #define ARM_SMMU_GR0_S2CR(n)            (0xc00 + ((n) << 2))
 181 #define S2CR_CBNDX_SHIFT                0
 182 #define S2CR_CBNDX_MASK                 0xff
 183 #define S2CR_TYPE_SHIFT                 16
 184 #define S2CR_TYPE_MASK                  0x3
 185 #define S2CR_TYPE_TRANS                 (0 << S2CR_TYPE_SHIFT)
 186 #define S2CR_TYPE_BYPASS                (1 << S2CR_TYPE_SHIFT)
 187 #define S2CR_TYPE_FAULT                 (2 << S2CR_TYPE_SHIFT)
 188
 189 /* Context bank attribute registers */
 190 #define ARM_SMMU_GR1_CBAR(n)            (0x0 + ((n) << 2))
 191 #define CBAR_VMID_SHIFT                 0
 192 #define CBAR_VMID_MASK                  0xff
 193 #define CBAR_S1_MEMATTR_SHIFT           12
 194 #define CBAR_S1_MEMATTR_MASK            0xf
 195 #define CBAR_S1_MEMATTR_WB              0xf
 196 #define CBAR_TYPE_SHIFT                 16
 197 #define CBAR_TYPE_MASK                  0x3
 198 #define CBAR_TYPE_S2_TRANS              (0 << CBAR_TYPE_SHIFT)
 199 #define CBAR_TYPE_S1_TRANS_S2_BYPASS    (1 << CBAR_TYPE_SHIFT)
 200 #define CBAR_TYPE_S1_TRANS_S2_FAULT     (2 << CBAR_TYPE_SHIFT)
 201 #define CBAR_TYPE_S1_TRANS_S2_TRANS     (3 << CBAR_TYPE_SHIFT)
 202 #define CBAR_IRPTNDX_SHIFT              24
 203 #define CBAR_IRPTNDX_MASK               0xff
 204
 205 #define ARM_SMMU_GR1_CBA2R(n)           (0x800 + ((n) << 2))
 206 #define CBA2R_RW64_32BIT                (0 << 0)
 207 #define CBA2R_RW64_64BIT                (1 << 0)
 208
 209 /* Translation context bank */
 210 #define ARM_SMMU_CB_BASE(smmu)          ((smmu)->base + ((smmu)->size >> 1))
 211 #define ARM_SMMU_CB(smmu, n)            ((n) * (smmu)->pagesize)
 212
 213 #define ARM_SMMU_CB_SCTLR               0x0
 214 #define ARM_SMMU_CB_RESUME              0x8
 215 #define ARM_SMMU_CB_TTBCR2              0x10
 216 #define ARM_SMMU_CB_TTBR0_LO            0x20
 217 #define ARM_SMMU_CB_TTBR0_HI            0x24
 218 #define ARM_SMMU_CB_TTBCR               0x30
 219 #define ARM_SMMU_CB_S1_MAIR0            0x38
 220 #define ARM_SMMU_CB_FSR                 0x58
 221 #define ARM_SMMU_CB_FAR_LO              0x60
 222 #define ARM_SMMU_CB_FAR_HI              0x64
 223 #define ARM_SMMU_CB_FSYNR0              0x68
 224 #define ARM_SMMU_CB_S1_TLBIASID         0x610
 225
 226 #define SCTLR_S1_ASIDPNE                (1 << 12)
 227 #define SCTLR_CFCFG                     (1 << 7)
 228 #define SCTLR_CFIE                      (1 << 6)
 229 #define SCTLR_CFRE                      (1 << 5)
 230 #define SCTLR_E                         (1 << 4)
 231 #define SCTLR_AFE                       (1 << 2)
 232 #define SCTLR_TRE                       (1 << 1)
 233 #define SCTLR_M                         (1 << 0)
 234 #define SCTLR_EAE_SBOP                  (SCTLR_AFE | SCTLR_TRE)
 235
 236 #define RESUME_RETRY                    (0 << 0)
 237 #define RESUME_TERMINATE                (1 << 0)
 238
 239 #define TTBCR_EAE                       (1 << 31)
 240
 241 #define TTBCR_PASIZE_SHIFT              16
 242 #define TTBCR_PASIZE_MASK               0x7
 243
 244 #define TTBCR_TG0_4K                    (0 << 14)
 245 #define TTBCR_TG0_64K                   (1 << 14)
 246
 247 #define TTBCR_SH0_SHIFT                 12
 248 #define TTBCR_SH0_MASK                  0x3
 249 #define TTBCR_SH_NS                     0
 250 #define TTBCR_SH_OS                     2
 251 #define TTBCR_SH_IS                     3
 252
 253 #define TTBCR_ORGN0_SHIFT               10
 254 #define TTBCR_IRGN0_SHIFT               8
 255 #define TTBCR_RGN_MASK                  0x3
 256 #define TTBCR_RGN_NC                    0
 257 #define TTBCR_RGN_WBWA                  1
 258 #define TTBCR_RGN_WT                    2
 259 #define TTBCR_RGN_WB                    3
 260
 261 #define TTBCR_SL0_SHIFT                 6
 262 #define TTBCR_SL0_MASK                  0x3
 263 #define TTBCR_SL0_LVL_2                 0
 264 #define TTBCR_SL0_LVL_1                 1
 265
 266 #define TTBCR_T1SZ_SHIFT                16
 267 #define TTBCR_T0SZ_SHIFT                0
 268 #define TTBCR_SZ_MASK                   0xf
 269
 270 #define TTBCR2_SEP_SHIFT                15
 271 #define TTBCR2_SEP_MASK                 0x7
 272
 273 #define TTBCR2_PASIZE_SHIFT             0
 274 #define TTBCR2_PASIZE_MASK              0x7
 275
 276 /* Common definitions for PASize and SEP fields */
 277 #define TTBCR2_ADDR_32                  0
 278 #define TTBCR2_ADDR_36                  1
 279 #define TTBCR2_ADDR_40                  2
 280 #define TTBCR2_ADDR_42                  3
 281 #define TTBCR2_ADDR_44                  4
 282 #define TTBCR2_ADDR_48                  5
 283
 284 #define TTBRn_HI_ASID_SHIFT             16
 285
 286 #define MAIR_ATTR_SHIFT(n)              ((n) << 3)
 287 #define MAIR_ATTR_MASK                  0xff
 288 #define MAIR_ATTR_DEVICE                0x04
 289 #define MAIR_ATTR_NC                    0x44
 290 #define MAIR_ATTR_WBRWA                 0xff
 291 #define MAIR_ATTR_IDX_NC                0
 292 #define MAIR_ATTR_IDX_CACHE             1
 293 #define MAIR_ATTR_IDX_DEV               2
 294
 295 #define FSR_MULTI                       (1 << 31)
 296 #define FSR_SS                          (1 << 30)
 297 #define FSR_UUT                         (1 << 8)
 298 #define FSR_ASF                         (1 << 7)
 299 #define FSR_TLBLKF                      (1 << 6)
 300 #define FSR_TLBMCF                      (1 << 5)
 301 #define FSR_EF                          (1 << 4)
 302 #define FSR_PF                          (1 << 3)
 303 #define FSR_AFF                         (1 << 2)
 304 #define FSR_TF                          (1 << 1)
 305
 306 #define FSR_IGN                         (FSR_AFF | FSR_ASF | FSR_TLBMCF |       \
 307                                          FSR_TLBLKF)
 308 #define FSR_FAULT                       (FSR_MULTI | FSR_SS | FSR_UUT |         \
 309                                          FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
 310
 311 #define FSYNR0_WNR                      (1 << 4)
 312
 313 struct arm_smmu_smr {
 314         u8                              idx;
 315         u16                             mask;
 316         u16                             id;
 317 };
 318
 319 struct arm_smmu_master {
 320         struct device_node              *of_node;
 321
 322         /*
 323          * The following is specific to the master's position in the
 324          * SMMU chain.
 325          */
 326         struct rb_node                  node;
 327         int                             num_streamids;
 328         u16                             streamids[MAX_MASTER_STREAMIDS];
 329
 330         /*
 331          * We only need to allocate these on the root SMMU, as we
 332          * configure unmatched streams to bypass translation.
 333          */
 334         struct arm_smmu_smr             *smrs;
 335 };
 336
 337 struct arm_smmu_device {
 338         struct device                   *dev;
 339         struct device_node              *parent_of_node;
 340
 341         void __iomem                    *base;
 342         unsigned long                   size;
 343         unsigned long                   pagesize;
 344
 345 #define ARM_SMMU_FEAT_COHERENT_WALK     (1 << 0)
 346 #define ARM_SMMU_FEAT_STREAM_MATCH      (1 << 1)
 347 #define ARM_SMMU_FEAT_TRANS_S1          (1 << 2)
 348 #define ARM_SMMU_FEAT_TRANS_S2          (1 << 3)
 349 #define ARM_SMMU_FEAT_TRANS_NESTED      (1 << 4)
 350         u32                             features;
 351         int                             version;
 352
 353         u32                             num_context_banks;
 354         u32                             num_s2_context_banks;
 355         DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS);
 356         atomic_t                        irptndx;
 357
 358         u32                             num_mapping_groups;
 359         DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS);
 360
 361         unsigned long                   input_size;
 362         unsigned long                   s1_output_size;
 363         unsigned long                   s2_output_size;
 364
 365         u32                             num_global_irqs;
 366         u32                             num_context_irqs;
 367         unsigned int                    *irqs;
 368
 369         struct list_head                list;
 370         struct rb_root                  masters;
 371 };
 372
 373 struct arm_smmu_cfg {
 374         struct arm_smmu_device          *smmu;
 375         u8                              cbndx;
 376         u8                              irptndx;
 377         u32                             cbar;
 378         pgd_t                           *pgd;
 379 };
 380
 381 #define ARM_SMMU_CB_ASID(cfg)           ((cfg)->cbndx)
 382 #define ARM_SMMU_CB_VMID(cfg)           ((cfg)->cbndx + 1)
 383
 384 struct arm_smmu_domain {
 385         /*
 386          * A domain can span across multiple, chained SMMUs and requires
 387          * all devices within the domain to follow the same translation
 388          * path.
 389          */
 390         struct arm_smmu_device          *leaf_smmu;
 391         struct arm_smmu_cfg             root_cfg;
 392         phys_addr_t                     output_mask;
 393
 394         spinlock_t                      lock;
 395 };
 396
 397 static DEFINE_SPINLOCK(arm_smmu_devices_lock);
 398 static LIST_HEAD(arm_smmu_devices);
 399
 400 static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu,
 401                                                 struct device_node *dev_node)
 402 {
 403         struct rb_node *node = smmu->masters.rb_node;
 404
 405         while (node) {
 406                 struct arm_smmu_master *master;
 407                 master = container_of(node, struct arm_smmu_master, node);
 408
 409                 if (dev_node < master->of_node)
 410                         node = node->rb_left;
 411                 else if (dev_node > master->of_node)
 412                         node = node->rb_right;
 413                 else
 414                         return master;
 415         }
 416
 417         return NULL;
 418 }
 419
 420 static int insert_smmu_master(struct arm_smmu_device *smmu,
 421                               struct arm_smmu_master *master)
 422 {
 423         struct rb_node **new, *parent;
 424
 425         new = &smmu->masters.rb_node;
 426         parent = NULL;
 427         while (*new) {
 428                 struct arm_smmu_master *this;
 429                 this = container_of(*new, struct arm_smmu_master, node);
 430
 431                 parent = *new;
 432                 if (master->of_node < this->of_node)
 433                         new = &((*new)->rb_left);
 434                 else if (master->of_node > this->of_node)
 435                         new = &((*new)->rb_right);
 436                 else
 437                         return -EEXIST;
 438         }
 439
 440         rb_link_node(&master->node, parent, new);
 441         rb_insert_color(&master->node, &smmu->masters);
 442         return 0;
 443 }
 444
 445 static int register_smmu_master(struct arm_smmu_device *smmu,
 446                                 struct device *dev,
 447                                 struct of_phandle_args *masterspec)
 448 {
 449         int i;
 450         struct arm_smmu_master *master;
 451
 452         master = find_smmu_master(smmu, masterspec->np);
 453         if (master) {
 454                 dev_err(dev,
 455                         "rejecting multiple registrations for master device %s\n",
 456                         masterspec->np->name);
 457                 return -EBUSY;
 458         }
 459
 460         if (masterspec->args_count > MAX_MASTER_STREAMIDS) {
 461                 dev_err(dev,
 462                         "reached maximum number (%d) of stream IDs for master device %s\n",
 463                         MAX_MASTER_STREAMIDS, masterspec->np->name);
 464                 return -ENOSPC;
 465         }
 466
 467         master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL);
 468         if (!master)
 469                 return -ENOMEM;
 470
 471         master->of_node         = masterspec->np;
 472         master->num_streamids   = masterspec->args_count;
 473
 474         for (i = 0; i < master->num_streamids; ++i)
 475                 master->streamids[i] = masterspec->args[i];
 476
 477         return insert_smmu_master(smmu, master);
 478 }
 479
 480 static struct arm_smmu_device *find_parent_smmu(struct arm_smmu_device *smmu)
 481 {
 482         struct arm_smmu_device *parent;
 483
 484         if (!smmu->parent_of_node)
 485                 return NULL;
 486
 487         spin_lock(&arm_smmu_devices_lock);
 488         list_for_each_entry(parent, &arm_smmu_devices, list)
 489                 if (parent->dev->of_node == smmu->parent_of_node)
 490                         goto out_unlock;
 491
 492         parent = NULL;
 493         dev_warn(smmu->dev,
 494                  "Failed to find SMMU parent despite parent in DT\n");
 495 out_unlock:
 496         spin_unlock(&arm_smmu_devices_lock);
 497         return parent;
 498 }
 499
 500 static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end)
 501 {
 502         int idx;
 503
 504         do {
 505                 idx = find_next_zero_bit(map, end, start);
 506                 if (idx == end)
 507                         return -ENOSPC;
 508         } while (test_and_set_bit(idx, map));
 509
 510         return idx;
 511 }
 512
 513 static void __arm_smmu_free_bitmap(unsigned long *map, int idx)
 514 {
 515         clear_bit(idx, map);
 516 }
 517
 518 /* Wait for any pending TLB invalidations to complete */
 519 static void arm_smmu_tlb_sync(struct arm_smmu_device *smmu)
 520 {
 521         int count = 0;
 522         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
 523
 524         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC);
 525         while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS)
 526                & sTLBGSTATUS_GSACTIVE) {
 527                 cpu_relax();
 528                 if (++count == TLB_LOOP_TIMEOUT) {
 529                         dev_err_ratelimited(smmu->dev,
 530                         "TLB sync timed out -- SMMU may be deadlocked\n");
 531                         return;
 532                 }
 533                 udelay(1);
 534         }
 535 }
 536
 537 static void arm_smmu_tlb_inv_context(struct arm_smmu_cfg *cfg)
 538 {
 539         struct arm_smmu_device *smmu = cfg->smmu;
 540         void __iomem *base = ARM_SMMU_GR0(smmu);
 541         bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
 542
 543         if (stage1) {
 544                 base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
 545                 writel_relaxed(ARM_SMMU_CB_ASID(cfg),
 546                                base + ARM_SMMU_CB_S1_TLBIASID);
 547         } else {
 548                 base = ARM_SMMU_GR0(smmu);
 549                 writel_relaxed(ARM_SMMU_CB_VMID(cfg),
 550                                base + ARM_SMMU_GR0_TLBIVMID);
 551         }
 552
 553         arm_smmu_tlb_sync(smmu);
 554 }
 555
 556 static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
 557 {
 558         int flags, ret;
 559         u32 fsr, far, fsynr, resume;
 560         unsigned long iova;
 561         struct iommu_domain *domain = dev;
 562         struct arm_smmu_domain *smmu_domain = domain->priv;
 563         struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
 564         struct arm_smmu_device *smmu = root_cfg->smmu;
 565         void __iomem *cb_base;
 566
 567         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, root_cfg->cbndx);
 568         fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
 569
 570         if (!(fsr & FSR_FAULT))
 571                 return IRQ_NONE;
 572
 573         if (fsr & FSR_IGN)
 574                 dev_err_ratelimited(smmu->dev,
 575                                     "Unexpected context fault (fsr 0x%u)\n",
 576                                     fsr);
 577
 578         fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
 579         flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
 580
 581         far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO);
 582         iova = far;
 583 #ifdef CONFIG_64BIT
 584         far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI);
 585         iova |= ((unsigned long)far << 32);
 586 #endif
 587
 588         if (!report_iommu_fault(domain, smmu->dev, iova, flags)) {
 589                 ret = IRQ_HANDLED;
 590                 resume = RESUME_RETRY;
 591         } else {
 592                 ret = IRQ_NONE;
 593                 resume = RESUME_TERMINATE;
 594         }
 595
 596         /* Clear the faulting FSR */
 597         writel(fsr, cb_base + ARM_SMMU_CB_FSR);
 598
 599         /* Retry or terminate any stalled transactions */
 600         if (fsr & FSR_SS)
 601                 writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME);
 602
 603         return ret;
 604 }
 605
 606 static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
 607 {
 608         u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
 609         struct arm_smmu_device *smmu = dev;
 610         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
 611
 612         gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
 613         if (!gfsr)
 614                 return IRQ_NONE;
 615
 616         gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
 617         gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
 618         gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
 619
 620         dev_err_ratelimited(smmu->dev,
 621                 "Unexpected global fault, this could be serious\n");
 622         dev_err_ratelimited(smmu->dev,
 623                 "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n",
 624                 gfsr, gfsynr0, gfsynr1, gfsynr2);
 625
 626         writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR);
 627         return IRQ_HANDLED;
 628 }
 629
 630 static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
 631 {
 632         u32 reg;
 633         bool stage1;
 634         struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
 635         struct arm_smmu_device *smmu = root_cfg->smmu;
 636         void __iomem *cb_base, *gr0_base, *gr1_base;
 637
 638         gr0_base = ARM_SMMU_GR0(smmu);
 639         gr1_base = ARM_SMMU_GR1(smmu);
 640         stage1 = root_cfg->cbar != CBAR_TYPE_S2_TRANS;
 641         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, root_cfg->cbndx);
 642
 643         /* CBAR */
 644         reg = root_cfg->cbar;
 645         if (smmu->version == 1)
 646               reg |= root_cfg->irptndx << CBAR_IRPTNDX_SHIFT;
 647
 648         /* Use the weakest memory type, so it is overridden by the pte */
 649         if (stage1)
 650                 reg |= (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
 651         else
 652                 reg |= ARM_SMMU_CB_VMID(root_cfg) << CBAR_VMID_SHIFT;
 653         writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(root_cfg->cbndx));
 654
 655         if (smmu->version > 1) {
 656                 /* CBA2R */
 657 #ifdef CONFIG_64BIT
 658                 reg = CBA2R_RW64_64BIT;
 659 #else
 660                 reg = CBA2R_RW64_32BIT;
 661 #endif
 662                 writel_relaxed(reg,
 663                                gr1_base + ARM_SMMU_GR1_CBA2R(root_cfg->cbndx));
 664
 665                 /* TTBCR2 */
 666                 switch (smmu->input_size) {
 667                 case 32:
 668                         reg = (TTBCR2_ADDR_32 << TTBCR2_SEP_SHIFT);
 669                         break;
 670                 case 36:
 671                         reg = (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT);
 672                         break;
 673                 case 39:
 674                         reg = (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT);
 675                         break;
 676                 case 42:
 677                         reg = (TTBCR2_ADDR_42 << TTBCR2_SEP_SHIFT);
 678                         break;
 679                 case 44:
 680                         reg = (TTBCR2_ADDR_44 << TTBCR2_SEP_SHIFT);
 681                         break;
 682                 case 48:
 683                         reg = (TTBCR2_ADDR_48 << TTBCR2_SEP_SHIFT);
 684                         break;
 685                 }
 686
 687                 switch (smmu->s1_output_size) {
 688                 case 32:
 689                         reg |= (TTBCR2_ADDR_32 << TTBCR2_PASIZE_SHIFT);
 690                         break;
 691                 case 36:
 692                         reg |= (TTBCR2_ADDR_36 << TTBCR2_PASIZE_SHIFT);
 693                         break;
 694                 case 39:
 695                         reg |= (TTBCR2_ADDR_40 << TTBCR2_PASIZE_SHIFT);
 696                         break;
 697                 case 42:
 698                         reg |= (TTBCR2_ADDR_42 << TTBCR2_PASIZE_SHIFT);
 699                         break;
 700                 case 44:
 701                         reg |= (TTBCR2_ADDR_44 << TTBCR2_PASIZE_SHIFT);
 702                         break;
 703                 case 48:
 704                         reg |= (TTBCR2_ADDR_48 << TTBCR2_PASIZE_SHIFT);
 705                         break;
 706                 }
 707
 708                 if (stage1)
 709                         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2);
 710         }
 711
 712         /* TTBR0 */
 713         reg = __pa(root_cfg->pgd);
 714         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO);
 715         reg = (phys_addr_t)__pa(root_cfg->pgd) >> 32;
 716         if (stage1)
 717                 reg |= ARM_SMMU_CB_ASID(root_cfg) << TTBRn_HI_ASID_SHIFT;
 718         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI);
 719
 720         /*
 721          * TTBCR
 722          * We use long descriptor, with inner-shareable WBWA tables in TTBR0.
 723          */
 724         if (smmu->version > 1) {
 725                 if (PAGE_SIZE == SZ_4K)
 726                         reg = TTBCR_TG0_4K;
 727                 else
 728                         reg = TTBCR_TG0_64K;
 729
 730                 if (!stage1) {
 731                         switch (smmu->s2_output_size) {
 732                         case 32:
 733                                 reg |= (TTBCR2_ADDR_32 << TTBCR_PASIZE_SHIFT);
 734                                 break;
 735                         case 36:
 736                                 reg |= (TTBCR2_ADDR_36 << TTBCR_PASIZE_SHIFT);
 737                                 break;
 738                         case 40:
 739                                 reg |= (TTBCR2_ADDR_40 << TTBCR_PASIZE_SHIFT);
 740                                 break;
 741                         case 42:
 742                                 reg |= (TTBCR2_ADDR_42 << TTBCR_PASIZE_SHIFT);
 743                                 break;
 744                         case 44:
 745                                 reg |= (TTBCR2_ADDR_44 << TTBCR_PASIZE_SHIFT);
 746                                 break;
 747                         case 48:
 748                                 reg |= (TTBCR2_ADDR_48 << TTBCR_PASIZE_SHIFT);
 749                                 break;
 750                         }
 751                 } else {
 752                         reg |= (64 - smmu->s1_output_size) << TTBCR_T0SZ_SHIFT;
 753                 }
 754         } else {
 755                 reg = 0;
 756         }
 757
 758         reg |= TTBCR_EAE |
 759               (TTBCR_SH_IS << TTBCR_SH0_SHIFT) |
 760               (TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) |
 761               (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT) |
 762               (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT);
 763         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
 764
 765         /* MAIR0 (stage-1 only) */
 766         if (stage1) {
 767                 reg = (MAIR_ATTR_NC << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_NC)) |
 768                       (MAIR_ATTR_WBRWA << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_CACHE)) |
 769                       (MAIR_ATTR_DEVICE << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_DEV));
 770                 writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0);
 771         }
 772
 773         /* SCTLR */
 774         reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP;
 775         if (stage1)
 776                 reg |= SCTLR_S1_ASIDPNE;
 777 #ifdef __BIG_ENDIAN
 778         reg |= SCTLR_E;
 779 #endif
 780         writel(reg, cb_base + ARM_SMMU_CB_SCTLR);
 781 }
 782
 783 static int arm_smmu_init_domain_context(struct iommu_domain *domain,
 784                                         struct device *dev)
 785 {
 786         int irq, ret, start;
 787         struct arm_smmu_domain *smmu_domain = domain->priv;
 788         struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
 789         struct arm_smmu_device *smmu, *parent;
 790
 791         /*
 792          * Walk the SMMU chain to find the root device for this chain.
 793          * We assume that no masters have translations which terminate
 794          * early, and therefore check that the root SMMU does indeed have
 795          * a StreamID for the master in question.
 796          */
 797         parent = dev->archdata.iommu;
 798         smmu_domain->output_mask = -1;
 799         do {
 800                 smmu = parent;
 801                 smmu_domain->output_mask &= (1ULL << smmu->s2_output_size) - 1;
 802         } while ((parent = find_parent_smmu(smmu)));
 803
 804         if (!find_smmu_master(smmu, dev->of_node)) {
 805                 dev_err(dev, "unable to find root SMMU for device\n");
 806                 return -ENODEV;
 807         }
 808
 809         if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) {
 810                 /*
 811                  * We will likely want to change this if/when KVM gets
 812                  * involved.
 813                  */
 814                 root_cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
 815                 start = smmu->num_s2_context_banks;
 816         } else if (smmu->features & ARM_SMMU_FEAT_TRANS_S2) {
 817                 root_cfg->cbar = CBAR_TYPE_S2_TRANS;
 818                 start = 0;
 819         } else {
 820                 root_cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
 821                 start = smmu->num_s2_context_banks;
 822         }
 823
 824         ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,
 825                                       smmu->num_context_banks);
 826         if (IS_ERR_VALUE(ret))
 827                 return ret;
 828
 829         root_cfg->cbndx = ret;
 830         if (smmu->version == 1) {
 831                 root_cfg->irptndx = atomic_inc_return(&smmu->irptndx);
 832                 root_cfg->irptndx %= smmu->num_context_irqs;
 833         } else {
 834                 root_cfg->irptndx = root_cfg->cbndx;
 835         }
 836
 837         irq = smmu->irqs[smmu->num_global_irqs + root_cfg->irptndx];
 838         ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED,
 839                           "arm-smmu-context-fault", domain);
 840         if (IS_ERR_VALUE(ret)) {
 841                 dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n",
 842                         root_cfg->irptndx, irq);
 843                 root_cfg->irptndx = -1;
 844                 goto out_free_context;
 845         }
 846
 847         root_cfg->smmu = smmu;
 848         arm_smmu_init_context_bank(smmu_domain);
 849         return ret;
 850
 851 out_free_context:
 852         __arm_smmu_free_bitmap(smmu->context_map, root_cfg->cbndx);
 853         return ret;
 854 }
 855
 856 static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
 857 {
 858         struct arm_smmu_domain *smmu_domain = domain->priv;
 859         struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
 860         struct arm_smmu_device *smmu = root_cfg->smmu;
 861         void __iomem *cb_base;
 862         int irq;
 863
 864         if (!smmu)
 865                 return;
 866
 867         /* Disable the context bank and nuke the TLB before freeing it. */
 868         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, root_cfg->cbndx);
 869         writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
 870         arm_smmu_tlb_inv_context(root_cfg);
 871
 872         if (root_cfg->irptndx != -1) {
 873                 irq = smmu->irqs[smmu->num_global_irqs + root_cfg->irptndx];
 874                 free_irq(irq, domain);
 875         }
 876
 877         __arm_smmu_free_bitmap(smmu->context_map, root_cfg->cbndx);
 878 }
 879
 880 static int arm_smmu_domain_init(struct iommu_domain *domain)
 881 {
 882         struct arm_smmu_domain *smmu_domain;
 883         pgd_t *pgd;
 884
 885         /*
 886          * Allocate the domain and initialise some of its data structures.
 887          * We can't really do anything meaningful until we've added a
 888          * master.
 889          */
 890         smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL);
 891         if (!smmu_domain)
 892                 return -ENOMEM;
 893
 894         pgd = kzalloc(PTRS_PER_PGD * sizeof(pgd_t), GFP_KERNEL);
 895         if (!pgd)
 896                 goto out_free_domain;
 897         smmu_domain->root_cfg.pgd = pgd;
 898
 899         spin_lock_init(&smmu_domain->lock);
 900         domain->priv = smmu_domain;
 901         return 0;
 902
 903 out_free_domain:
 904         kfree(smmu_domain);
 905         return -ENOMEM;
 906 }
 907
 908 static void arm_smmu_free_ptes(pmd_t *pmd)
 909 {
 910         pgtable_t table = pmd_pgtable(*pmd);
 911         pgtable_page_dtor(table);
 912         __free_page(table);
 913 }
 914
 915 static void arm_smmu_free_pmds(pud_t *pud)
 916 {
 917         int i;
 918         pmd_t *pmd, *pmd_base = pmd_offset(pud, 0);
 919
 920         pmd = pmd_base;
 921         for (i = 0; i < PTRS_PER_PMD; ++i) {
 922                 if (pmd_none(*pmd))
 923                         continue;
 924
 925                 arm_smmu_free_ptes(pmd);
 926                 pmd++;
 927         }
 928
 929         pmd_free(NULL, pmd_base);
 930 }
 931
 932 static void arm_smmu_free_puds(pgd_t *pgd)
 933 {
 934         int i;
 935         pud_t *pud, *pud_base = pud_offset(pgd, 0);
 936
 937         pud = pud_base;
 938         for (i = 0; i < PTRS_PER_PUD; ++i) {
 939                 if (pud_none(*pud))
 940                         continue;
 941
 942                 arm_smmu_free_pmds(pud);
 943                 pud++;
 944         }
 945
 946         pud_free(NULL, pud_base);
 947 }
 948
 949 static void arm_smmu_free_pgtables(struct arm_smmu_domain *smmu_domain)
 950 {
 951         int i;
 952         struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
 953         pgd_t *pgd, *pgd_base = root_cfg->pgd;
 954
 955         /*
 956          * Recursively free the page tables for this domain. We don't
 957          * care about speculative TLB filling, because the TLB will be
 958          * nuked next time this context bank is re-allocated and no devices
 959          * currently map to these tables.
 960          */
 961         pgd = pgd_base;
 962         for (i = 0; i < PTRS_PER_PGD; ++i) {
 963                 if (pgd_none(*pgd))
 964                         continue;
 965                 arm_smmu_free_puds(pgd);
 966                 pgd++;
 967         }
 968
 969         kfree(pgd_base);
 970 }
 971
 972 static void arm_smmu_domain_destroy(struct iommu_domain *domain)
 973 {
 974         struct arm_smmu_domain *smmu_domain = domain->priv;
 975
 976         /*
 977          * Free the domain resources. We assume that all devices have
 978          * already been detached.
 979          */
 980         arm_smmu_destroy_domain_context(domain);
 981         arm_smmu_free_pgtables(smmu_domain);
 982         kfree(smmu_domain);
 983 }
 984
 985 static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu,
 986                                           struct arm_smmu_master *master)
 987 {
 988         int i;
 989         struct arm_smmu_smr *smrs;
 990         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
 991
 992         if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH))
 993                 return 0;
 994
 995         if (master->smrs)
 996                 return -EEXIST;
 997
 998         smrs = kmalloc(sizeof(*smrs) * master->num_streamids, GFP_KERNEL);
 999         if (!smrs) {
1000                 dev_err(smmu->dev, "failed to allocate %d SMRs for master %s\n",
1001                         master->num_streamids, master->of_node->name);
1002                 return -ENOMEM;
1003         }
1004
1005         /* Allocate the SMRs on the root SMMU */
1006         for (i = 0; i < master->num_streamids; ++i) {
1007                 int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0,
1008                                                   smmu->num_mapping_groups);
1009                 if (IS_ERR_VALUE(idx)) {
1010                         dev_err(smmu->dev, "failed to allocate free SMR\n");
1011                         goto err_free_smrs;
1012                 }
1013
1014                 smrs[i] = (struct arm_smmu_smr) {
1015                         .idx    = idx,
1016                         .mask   = 0, /* We don't currently share SMRs */
1017                         .id     = master->streamids[i],
1018                 };
1019         }
1020
1021         /* It worked! Now, poke the actual hardware */
1022         for (i = 0; i < master->num_streamids; ++i) {
1023                 u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT |
1024                           smrs[i].mask << SMR_MASK_SHIFT;
1025                 writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx));
1026         }
1027
1028         master->smrs = smrs;
1029         return 0;
1030
1031 err_free_smrs:
1032         while (--i >= 0)
1033                 __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx);
1034         kfree(smrs);
1035         return -ENOSPC;
1036 }
1037
1038 static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu,
1039                                       struct arm_smmu_master *master)
1040 {
1041         int i;
1042         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1043         struct arm_smmu_smr *smrs = master->smrs;
1044
1045         /* Invalidate the SMRs before freeing back to the allocator */
1046         for (i = 0; i < master->num_streamids; ++i) {
1047                 u8 idx = smrs[i].idx;
1048                 writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx));
1049                 __arm_smmu_free_bitmap(smmu->smr_map, idx);
1050         }
1051
1052         master->smrs = NULL;
1053         kfree(smrs);
1054 }
1055
1056 static void arm_smmu_bypass_stream_mapping(struct arm_smmu_device *smmu,
1057                                            struct arm_smmu_master *master)
1058 {
1059         int i;
1060         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1061
1062         for (i = 0; i < master->num_streamids; ++i) {
1063                 u16 sid = master->streamids[i];
1064                 writel_relaxed(S2CR_TYPE_BYPASS,
1065                                gr0_base + ARM_SMMU_GR0_S2CR(sid));
1066         }
1067 }
1068
1069 static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
1070                                       struct arm_smmu_master *master)
1071 {
1072         int i, ret;
1073         struct arm_smmu_device *parent, *smmu = smmu_domain->root_cfg.smmu;
1074         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1075
1076         ret = arm_smmu_master_configure_smrs(smmu, master);
1077         if (ret)
1078                 return ret;
1079
1080         /* Bypass the leaves */
1081         smmu = smmu_domain->leaf_smmu;
1082         while ((parent = find_parent_smmu(smmu))) {
1083                 /*
1084                  * We won't have a StreamID match for anything but the root
1085                  * smmu, so we only need to worry about StreamID indexing,
1086                  * where we must install bypass entries in the S2CRs.
1087                  */
1088                 if (smmu->features & ARM_SMMU_FEAT_STREAM_MATCH)
1089                         continue;
1090
1091                 arm_smmu_bypass_stream_mapping(smmu, master);
1092                 smmu = parent;
1093         }
1094
1095         /* Now we're at the root, time to point at our context bank */
1096         for (i = 0; i < master->num_streamids; ++i) {
1097                 u32 idx, s2cr;
1098                 idx = master->smrs ? master->smrs[i].idx : master->streamids[i];
1099                 s2cr = (S2CR_TYPE_TRANS << S2CR_TYPE_SHIFT) |
1100                        (smmu_domain->root_cfg.cbndx << S2CR_CBNDX_SHIFT);
1101                 writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx));
1102         }
1103
1104         return 0;
1105 }
1106
1107 static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain,
1108                                           struct arm_smmu_master *master)
1109 {
1110         struct arm_smmu_device *smmu = smmu_domain->root_cfg.smmu;
1111
1112         /*
1113          * We *must* clear the S2CR first, because freeing the SMR means
1114          * that it can be re-allocated immediately.
1115          */
1116         arm_smmu_bypass_stream_mapping(smmu, master);
1117         arm_smmu_master_free_smrs(smmu, master);
1118 }
1119
1120 static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
1121 {
1122         int ret = -EINVAL;
1123         struct arm_smmu_domain *smmu_domain = domain->priv;
1124         struct arm_smmu_device *device_smmu = dev->archdata.iommu;
1125         struct arm_smmu_master *master;
1126
1127         if (!device_smmu) {
1128                 dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n");
1129                 return -ENXIO;
1130         }
1131
1132         /*
1133          * Sanity check the domain. We don't currently support domains
1134          * that cross between different SMMU chains.
1135          */
1136         spin_lock(&smmu_domain->lock);
1137         if (!smmu_domain->leaf_smmu) {
1138                 /* Now that we have a master, we can finalise the domain */
1139                 ret = arm_smmu_init_domain_context(domain, dev);
1140                 if (IS_ERR_VALUE(ret))
1141                         goto err_unlock;
1142
1143                 smmu_domain->leaf_smmu = device_smmu;
1144         } else if (smmu_domain->leaf_smmu != device_smmu) {
1145                 dev_err(dev,
1146                         "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n",
1147                         dev_name(smmu_domain->leaf_smmu->dev),
1148                         dev_name(device_smmu->dev));
1149                 goto err_unlock;
1150         }
1151         spin_unlock(&smmu_domain->lock);
1152
1153         /* Looks ok, so add the device to the domain */
1154         master = find_smmu_master(smmu_domain->leaf_smmu, dev->of_node);
1155         if (!master)
1156                 return -ENODEV;
1157
1158         return arm_smmu_domain_add_master(smmu_domain, master);
1159
1160 err_unlock:
1161         spin_unlock(&smmu_domain->lock);
1162         return ret;
1163 }
1164
1165 static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev)
1166 {
1167         struct arm_smmu_domain *smmu_domain = domain->priv;
1168         struct arm_smmu_master *master;
1169
1170         master = find_smmu_master(smmu_domain->leaf_smmu, dev->of_node);
1171         if (master)
1172                 arm_smmu_domain_remove_master(smmu_domain, master);
1173 }
1174
1175 static void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr,
1176                                    size_t size)
1177 {
1178         unsigned long offset = (unsigned long)addr & ~PAGE_MASK;
1179
1180         /*
1181          * If the SMMU can't walk tables in the CPU caches, treat them
1182          * like non-coherent DMA since we need to flush the new entries
1183          * all the way out to memory. There's no possibility of recursion
1184          * here as the SMMU table walker will not be wired through another
1185          * SMMU.
1186          */
1187         if (!(smmu->features & ARM_SMMU_FEAT_COHERENT_WALK))
1188                 dma_map_page(smmu->dev, virt_to_page(addr), offset, size,
1189                              DMA_TO_DEVICE);
1190 }
1191
1192 static bool arm_smmu_pte_is_contiguous_range(unsigned long addr,
1193                                              unsigned long end)
1194 {
1195         return !(addr & ~ARM_SMMU_PTE_CONT_MASK) &&
1196                 (addr + ARM_SMMU_PTE_CONT_SIZE <= end);
1197 }
1198
1199 static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
1200                                    unsigned long addr, unsigned long end,
1201                                    unsigned long pfn, int flags, int stage)
1202 {
1203         pte_t *pte, *start;
1204         pteval_t pteval = ARM_SMMU_PTE_PAGE | ARM_SMMU_PTE_AF;
1205
1206         if (pmd_none(*pmd)) {
1207                 /* Allocate a new set of tables */
1208                 pgtable_t table = alloc_page(PGALLOC_GFP);
1209                 if (!table)
1210                         return -ENOMEM;
1211
1212                 arm_smmu_flush_pgtable(smmu, page_address(table),
1213                                        ARM_SMMU_PTE_HWTABLE_SIZE);
1214                 pgtable_page_ctor(table);
1215                 pmd_populate(NULL, pmd, table);
1216                 arm_smmu_flush_pgtable(smmu, pmd, sizeof(*pmd));
1217         }
1218
1219         if (stage == 1) {
1220                 pteval |= ARM_SMMU_PTE_AP_UNPRIV | ARM_SMMU_PTE_nG;
1221                 if (!(flags & IOMMU_WRITE) && (flags & IOMMU_READ))
1222                         pteval |= ARM_SMMU_PTE_AP_RDONLY;
1223
1224                 if (flags & IOMMU_CACHE)
1225                         pteval |= (MAIR_ATTR_IDX_CACHE <<
1226                                    ARM_SMMU_PTE_ATTRINDX_SHIFT);
1227         } else {
1228                 pteval |= ARM_SMMU_PTE_HAP_FAULT;
1229                 if (flags & IOMMU_READ)
1230                         pteval |= ARM_SMMU_PTE_HAP_READ;
1231                 if (flags & IOMMU_WRITE)
1232                         pteval |= ARM_SMMU_PTE_HAP_WRITE;
1233                 if (flags & IOMMU_CACHE)
1234                         pteval |= ARM_SMMU_PTE_MEMATTR_OIWB;
1235                 else
1236                         pteval |= ARM_SMMU_PTE_MEMATTR_NC;
1237         }
1238
1239         /* If no access, create a faulting entry to avoid TLB fills */
1240         if (!(flags & (IOMMU_READ | IOMMU_WRITE)))
1241                 pteval &= ~ARM_SMMU_PTE_PAGE;
1242
1243         pteval |= ARM_SMMU_PTE_SH_IS;
1244         start = pmd_page_vaddr(*pmd) + pte_index(addr);
1245         pte = start;
1246
1247         /*
1248          * Install the page table entries. This is fairly complicated
1249          * since we attempt to make use of the contiguous hint in the
1250          * ptes where possible. The contiguous hint indicates a series
1251          * of ARM_SMMU_PTE_CONT_ENTRIES ptes mapping a physically
1252          * contiguous region with the following constraints:
1253          *
1254          *   - The region start is aligned to ARM_SMMU_PTE_CONT_SIZE
1255          *   - Each pte in the region has the contiguous hint bit set
1256          *
1257          * This complicates unmapping (also handled by this code, when
1258          * neither IOMMU_READ or IOMMU_WRITE are set) because it is
1259          * possible, yet highly unlikely, that a client may unmap only
1260          * part of a contiguous range. This requires clearing of the
1261          * contiguous hint bits in the range before installing the new
1262          * faulting entries.
1263          *
1264          * Note that re-mapping an address range without first unmapping
1265          * it is not supported, so TLB invalidation is not required here
1266          * and is instead performed at unmap and domain-init time.
1267          */
1268         do {
1269                 int i = 1;
1270                 pteval &= ~ARM_SMMU_PTE_CONT;
1271
1272                 if (arm_smmu_pte_is_contiguous_range(addr, end)) {
1273                         i = ARM_SMMU_PTE_CONT_ENTRIES;
1274                         pteval |= ARM_SMMU_PTE_CONT;
1275                 } else if (pte_val(*pte) &
1276                            (ARM_SMMU_PTE_CONT | ARM_SMMU_PTE_PAGE)) {
1277                         int j;
1278                         pte_t *cont_start;
1279                         unsigned long idx = pte_index(addr);
1280
1281                         idx &= ~(ARM_SMMU_PTE_CONT_ENTRIES - 1);
1282                         cont_start = pmd_page_vaddr(*pmd) + idx;
1283                         for (j = 0; j < ARM_SMMU_PTE_CONT_ENTRIES; ++j)
1284                                 pte_val(*(cont_start + j)) &= ~ARM_SMMU_PTE_CONT;
1285
1286                         arm_smmu_flush_pgtable(smmu, cont_start,
1287                                                sizeof(*pte) *
1288                                                ARM_SMMU_PTE_CONT_ENTRIES);
1289                 }
1290
1291                 do {
1292                         *pte = pfn_pte(pfn, __pgprot(pteval));
1293                 } while (pte++, pfn++, addr += PAGE_SIZE, --i);
1294         } while (addr != end);
1295
1296         arm_smmu_flush_pgtable(smmu, start, sizeof(*pte) * (pte - start));
1297         return 0;
1298 }
1299
1300 static int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud,
1301                                    unsigned long addr, unsigned long end,
1302                                    phys_addr_t phys, int flags, int stage)
1303 {
1304         int ret;
1305         pmd_t *pmd;
1306         unsigned long next, pfn = __phys_to_pfn(phys);
1307
1308 #ifndef __PAGETABLE_PMD_FOLDED
1309         if (pud_none(*pud)) {
1310                 pmd = pmd_alloc_one(NULL, addr);
1311                 if (!pmd)
1312                         return -ENOMEM;
1313         } else
1314 #endif
1315                 pmd = pmd_offset(pud, addr);
1316
1317         do {
1318                 next = pmd_addr_end(addr, end);
1319                 ret = arm_smmu_alloc_init_pte(smmu, pmd, addr, end, pfn,
1320                                               flags, stage);
1321                 pud_populate(NULL, pud, pmd);
1322                 arm_smmu_flush_pgtable(smmu, pud, sizeof(*pud));
1323                 phys += next - addr;
1324         } while (pmd++, addr = next, addr < end);
1325
1326         return ret;
1327 }
1328
1329 static int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd,
1330                                    unsigned long addr, unsigned long end,
1331                                    phys_addr_t phys, int flags, int stage)
1332 {
1333         int ret = 0;
1334         pud_t *pud;
1335         unsigned long next;
1336
1337 #ifndef __PAGETABLE_PUD_FOLDED
1338         if (pgd_none(*pgd)) {
1339                 pud = pud_alloc_one(NULL, addr);
1340                 if (!pud)
1341                         return -ENOMEM;
1342         } else
1343 #endif
1344                 pud = pud_offset(pgd, addr);
1345
1346         do {
1347                 next = pud_addr_end(addr, end);
1348                 ret = arm_smmu_alloc_init_pmd(smmu, pud, addr, next, phys,
1349                                               flags, stage);
1350                 pgd_populate(NULL, pud, pgd);
1351                 arm_smmu_flush_pgtable(smmu, pgd, sizeof(*pgd));
1352                 phys += next - addr;
1353         } while (pud++, addr = next, addr < end);
1354
1355         return ret;
1356 }
1357
1358 static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
1359                                    unsigned long iova, phys_addr_t paddr,
1360                                    size_t size, int flags)
1361 {
1362         int ret, stage;
1363         unsigned long end;
1364         phys_addr_t input_mask, output_mask;
1365         struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
1366         pgd_t *pgd = root_cfg->pgd;
1367         struct arm_smmu_device *smmu = root_cfg->smmu;
1368
1369         if (root_cfg->cbar == CBAR_TYPE_S2_TRANS) {
1370                 stage = 2;
1371                 output_mask = (1ULL << smmu->s2_output_size) - 1;
1372         } else {
1373                 stage = 1;
1374                 output_mask = (1ULL << smmu->s1_output_size) - 1;
1375         }
1376
1377         if (!pgd)
1378                 return -EINVAL;
1379
1380         if (size & ~PAGE_MASK)
1381                 return -EINVAL;
1382
1383         input_mask = (1ULL << smmu->input_size) - 1;
1384         if ((phys_addr_t)iova & ~input_mask)
1385                 return -ERANGE;
1386
1387         if (paddr & ~output_mask)
1388                 return -ERANGE;
1389
1390         spin_lock(&smmu_domain->lock);
1391         pgd += pgd_index(iova);
1392         end = iova + size;
1393         do {
1394                 unsigned long next = pgd_addr_end(iova, end);
1395
1396                 ret = arm_smmu_alloc_init_pud(smmu, pgd, iova, next, paddr,
1397                                               flags, stage);
1398                 if (ret)
1399                         goto out_unlock;
1400
1401                 paddr += next - iova;
1402                 iova = next;
1403         } while (pgd++, iova != end);
1404
1405 out_unlock:
1406         spin_unlock(&smmu_domain->lock);
1407
1408         /* Ensure new page tables are visible to the hardware walker */
1409         if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK)
1410                 dsb();
1411
1412         return ret;
1413 }
1414
1415 static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
1416                         phys_addr_t paddr, size_t size, int flags)
1417 {
1418         struct arm_smmu_domain *smmu_domain = domain->priv;
1419         struct arm_smmu_device *smmu = smmu_domain->leaf_smmu;
1420
1421         if (!smmu_domain || !smmu)
1422                 return -ENODEV;
1423
1424         /* Check for silent address truncation up the SMMU chain. */
1425         if ((phys_addr_t)iova & ~smmu_domain->output_mask)
1426                 return -ERANGE;
1427
1428         return arm_smmu_handle_mapping(smmu_domain, iova, paddr, size, flags);
1429 }
1430
1431 static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
1432                              size_t size)
1433 {
1434         int ret;
1435         struct arm_smmu_domain *smmu_domain = domain->priv;
1436
1437         ret = arm_smmu_handle_mapping(smmu_domain, iova, 0, size, 0);
1438         arm_smmu_tlb_inv_context(&smmu_domain->root_cfg);
1439         return ret ? ret : size;
1440 }
1441
1442 static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
1443                                          dma_addr_t iova)
1444 {
1445         pgd_t *pgd;
1446         pud_t *pud;
1447         pmd_t *pmd;
1448         pte_t *pte;
1449         struct arm_smmu_domain *smmu_domain = domain->priv;
1450         struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
1451         struct arm_smmu_device *smmu = root_cfg->smmu;
1452
1453         spin_lock(&smmu_domain->lock);
1454         pgd = root_cfg->pgd;
1455         if (!pgd)
1456                 goto err_unlock;
1457
1458         pgd += pgd_index(iova);
1459         if (pgd_none_or_clear_bad(pgd))
1460                 goto err_unlock;
1461
1462         pud = pud_offset(pgd, iova);
1463         if (pud_none_or_clear_bad(pud))
1464                 goto err_unlock;
1465
1466         pmd = pmd_offset(pud, iova);
1467         if (pmd_none_or_clear_bad(pmd))
1468                 goto err_unlock;
1469
1470         pte = pmd_page_vaddr(*pmd) + pte_index(iova);
1471         if (pte_none(pte))
1472                 goto err_unlock;
1473
1474         spin_unlock(&smmu_domain->lock);
1475         return __pfn_to_phys(pte_pfn(*pte)) | (iova & ~PAGE_MASK);
1476
1477 err_unlock:
1478         spin_unlock(&smmu_domain->lock);
1479         dev_warn(smmu->dev,
1480                  "invalid (corrupt?) page tables detected for iova 0x%llx\n",
1481                  (unsigned long long)iova);
1482         return -EINVAL;
1483 }
1484
1485 static int arm_smmu_domain_has_cap(struct iommu_domain *domain,
1486                                    unsigned long cap)
1487 {
1488         unsigned long caps = 0;
1489         struct arm_smmu_domain *smmu_domain = domain->priv;
1490
1491         if (smmu_domain->root_cfg.smmu->features & ARM_SMMU_FEAT_COHERENT_WALK)
1492                 caps |= IOMMU_CAP_CACHE_COHERENCY;
1493
1494         return !!(cap & caps);
1495 }
1496
1497 static int arm_smmu_add_device(struct device *dev)
1498 {
1499         struct arm_smmu_device *child, *parent, *smmu;
1500         struct arm_smmu_master *master = NULL;
1501
1502         spin_lock(&arm_smmu_devices_lock);
1503         list_for_each_entry(parent, &arm_smmu_devices, list) {
1504                 smmu = parent;
1505
1506                 /* Try to find a child of the current SMMU. */
1507                 list_for_each_entry(child, &arm_smmu_devices, list) {
1508                         if (child->parent_of_node == parent->dev->of_node) {
1509                                 /* Does the child sit above our master? */
1510                                 master = find_smmu_master(child, dev->of_node);
1511                                 if (master) {
1512                                         smmu = NULL;
1513                                         break;
1514                                 }
1515                         }
1516                 }
1517
1518                 /* We found some children, so keep searching. */
1519                 if (!smmu) {
1520                         master = NULL;
1521                         continue;
1522                 }
1523
1524                 master = find_smmu_master(smmu, dev->of_node);
1525                 if (master)
1526                         break;
1527         }
1528         spin_unlock(&arm_smmu_devices_lock);
1529
1530         if (!master)
1531                 return -ENODEV;
1532
1533         dev->archdata.iommu = smmu;
1534         return 0;
1535 }
1536
1537 static void arm_smmu_remove_device(struct device *dev)
1538 {
1539         dev->archdata.iommu = NULL;
1540 }
1541
1542 static struct iommu_ops arm_smmu_ops = {
1543         .domain_init    = arm_smmu_domain_init,
1544         .domain_destroy = arm_smmu_domain_destroy,
1545         .attach_dev     = arm_smmu_attach_dev,
1546         .detach_dev     = arm_smmu_detach_dev,
1547         .map            = arm_smmu_map,
1548         .unmap          = arm_smmu_unmap,
1549         .iova_to_phys   = arm_smmu_iova_to_phys,
1550         .domain_has_cap = arm_smmu_domain_has_cap,
1551         .add_device     = arm_smmu_add_device,
1552         .remove_device  = arm_smmu_remove_device,
1553         .pgsize_bitmap  = (SECTION_SIZE |
1554                            ARM_SMMU_PTE_CONT_SIZE |
1555                            PAGE_SIZE),
1556 };
1557
1558 static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
1559 {
1560         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1561         void __iomem *sctlr_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB_SCTLR;
1562         int i = 0;
1563         u32 scr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sCR0);
1564
1565         /* Mark all SMRn as invalid and all S2CRn as bypass */
1566         for (i = 0; i < smmu->num_mapping_groups; ++i) {
1567                 writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(i));
1568                 writel_relaxed(S2CR_TYPE_BYPASS, gr0_base + ARM_SMMU_GR0_S2CR(i));
1569         }
1570
1571         /* Make sure all context banks are disabled */
1572         for (i = 0; i < smmu->num_context_banks; ++i)
1573                 writel_relaxed(0, sctlr_base + ARM_SMMU_CB(smmu, i));
1574
1575         /* Invalidate the TLB, just in case */
1576         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_STLBIALL);
1577         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);
1578         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);
1579
1580         /* Enable fault reporting */
1581         scr0 |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE);
1582
1583         /* Disable TLB broadcasting. */
1584         scr0 |= (sCR0_VMIDPNE | sCR0_PTM);
1585
1586         /* Enable client access, but bypass when no mapping is found */
1587         scr0 &= ~(sCR0_CLIENTPD | sCR0_USFCFG);
1588
1589         /* Disable forced broadcasting */
1590         scr0 &= ~sCR0_FB;
1591
1592         /* Don't upgrade barriers */
1593         scr0 &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT);
1594
1595         /* Push the button */
1596         arm_smmu_tlb_sync(smmu);
1597         writel(scr0, gr0_base + ARM_SMMU_GR0_sCR0);
1598 }
1599
1600 static int arm_smmu_id_size_to_bits(int size)
1601 {
1602         switch (size) {
1603         case 0:
1604                 return 32;
1605         case 1:
1606                 return 36;
1607         case 2:
1608                 return 40;
1609         case 3:
1610                 return 42;
1611         case 4:
1612                 return 44;
1613         case 5:
1614         default:
1615                 return 48;
1616         }
1617 }
1618
1619 static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
1620 {
1621         unsigned long size;
1622         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1623         u32 id;
1624
1625         dev_notice(smmu->dev, "probing hardware configuration...\n");
1626
1627         /* Primecell ID */
1628         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_PIDR2);
1629         smmu->version = ((id >> PIDR2_ARCH_SHIFT) & PIDR2_ARCH_MASK) + 1;
1630         dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version);
1631
1632         /* ID0 */
1633         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0);
1634 #ifndef CONFIG_64BIT
1635         if (((id >> ID0_PTFS_SHIFT) & ID0_PTFS_MASK) == ID0_PTFS_V8_ONLY) {
1636                 dev_err(smmu->dev, "\tno v7 descriptor support!\n");
1637                 return -ENODEV;
1638         }
1639 #endif
1640         if (id & ID0_S1TS) {
1641                 smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
1642                 dev_notice(smmu->dev, "\tstage 1 translation\n");
1643         }
1644
1645         if (id & ID0_S2TS) {
1646                 smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
1647                 dev_notice(smmu->dev, "\tstage 2 translation\n");
1648         }
1649
1650         if (id & ID0_NTS) {
1651                 smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED;
1652                 dev_notice(smmu->dev, "\tnested translation\n");
1653         }
1654
1655         if (!(smmu->features &
1656                 (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2 |
1657                  ARM_SMMU_FEAT_TRANS_NESTED))) {
1658                 dev_err(smmu->dev, "\tno translation support!\n");
1659                 return -ENODEV;
1660         }
1661
1662         if (id & ID0_CTTW) {
1663                 smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK;
1664                 dev_notice(smmu->dev, "\tcoherent table walk\n");
1665         }
1666
1667         if (id & ID0_SMS) {
1668                 u32 smr, sid, mask;
1669
1670                 smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH;
1671                 smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) &
1672                                            ID0_NUMSMRG_MASK;
1673                 if (smmu->num_mapping_groups == 0) {
1674                         dev_err(smmu->dev,
1675                                 "stream-matching supported, but no SMRs present!\n");
1676                         return -ENODEV;
1677                 }
1678
1679                 smr = SMR_MASK_MASK << SMR_MASK_SHIFT;
1680                 smr |= (SMR_ID_MASK << SMR_ID_SHIFT);
1681                 writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));
1682                 smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0));
1683
1684                 mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK;
1685                 sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK;
1686                 if ((mask & sid) != sid) {
1687                         dev_err(smmu->dev,
1688                                 "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n",
1689                                 mask, sid);
1690                         return -ENODEV;
1691                 }
1692
1693                 dev_notice(smmu->dev,
1694                            "\tstream matching with %u register groups, mask 0x%x",
1695                            smmu->num_mapping_groups, mask);
1696         }
1697
1698         /* ID1 */
1699         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1);
1700         smmu->pagesize = (id & ID1_PAGESIZE) ? SZ_64K : SZ_4K;
1701
1702         /* Check that we ioremapped enough */
1703         size = 1 << (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1);
1704         size *= (smmu->pagesize << 1);
1705         if (smmu->size < size)
1706                 dev_warn(smmu->dev,
1707                          "device is 0x%lx bytes but only mapped 0x%lx!\n",
1708                          size, smmu->size);
1709
1710         smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) &
1711                                       ID1_NUMS2CB_MASK;
1712         smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK;
1713         if (smmu->num_s2_context_banks > smmu->num_context_banks) {
1714                 dev_err(smmu->dev, "impossible number of S2 context banks!\n");
1715                 return -ENODEV;
1716         }
1717         dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n",
1718                    smmu->num_context_banks, smmu->num_s2_context_banks);
1719
1720         /* ID2 */
1721         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2);
1722         size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK);
1723
1724         /*
1725          * Stage-1 output limited by stage-2 input size due to pgd
1726          * allocation (PTRS_PER_PGD).
1727          */
1728 #ifdef CONFIG_64BIT
1729         /* Current maximum output size of 39 bits */
1730         smmu->s1_output_size = min(39UL, size);
1731 #else
1732         smmu->s1_output_size = min(32UL, size);
1733 #endif
1734
1735         /* The stage-2 output mask is also applied for bypass */
1736         size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);
1737         smmu->s2_output_size = min((unsigned long)PHYS_MASK_SHIFT, size);
1738
1739         if (smmu->version == 1) {
1740                 smmu->input_size = 32;
1741         } else {
1742 #ifdef CONFIG_64BIT
1743                 size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK;
1744                 size = min(39, arm_smmu_id_size_to_bits(size));
1745 #else
1746                 size = 32;
1747 #endif
1748                 smmu->input_size = size;
1749
1750                 if ((PAGE_SIZE == SZ_4K && !(id & ID2_PTFS_4K)) ||
1751                     (PAGE_SIZE == SZ_64K && !(id & ID2_PTFS_64K)) ||
1752                     (PAGE_SIZE != SZ_4K && PAGE_SIZE != SZ_64K)) {
1753                         dev_err(smmu->dev, "CPU page size 0x%lx unsupported\n",
1754                                 PAGE_SIZE);
1755                         return -ENODEV;
1756                 }
1757         }
1758
1759         dev_notice(smmu->dev,
1760                    "\t%lu-bit VA, %lu-bit IPA, %lu-bit PA\n",
1761                    smmu->input_size, smmu->s1_output_size, smmu->s2_output_size);
1762         return 0;
1763 }
1764
1765 static int arm_smmu_device_dt_probe(struct platform_device *pdev)
1766 {
1767         struct resource *res;
1768         struct arm_smmu_device *smmu;
1769         struct device_node *dev_node;
1770         struct device *dev = &pdev->dev;
1771         struct rb_node *node;
1772         struct of_phandle_args masterspec;
1773         int num_irqs, i, err;
1774
1775         smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
1776         if (!smmu) {
1777                 dev_err(dev, "failed to allocate arm_smmu_device\n");
1778                 return -ENOMEM;
1779         }
1780         smmu->dev = dev;
1781
1782         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1783         if (!res) {
1784                 dev_err(dev, "missing base address/size\n");
1785                 return -ENODEV;
1786         }
1787
1788         smmu->size = resource_size(res);
1789         smmu->base = devm_request_and_ioremap(dev, res);
1790         if (!smmu->base)
1791                 return -EADDRNOTAVAIL;
1792
1793         if (of_property_read_u32(dev->of_node, "#global-interrupts",
1794                                  &smmu->num_global_irqs)) {
1795                 dev_err(dev, "missing #global-interrupts property\n");
1796                 return -ENODEV;
1797         }
1798
1799         num_irqs = 0;
1800         while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) {
1801                 num_irqs++;
1802                 if (num_irqs > smmu->num_global_irqs)
1803                         smmu->num_context_irqs++;
1804         }
1805
1806         if (num_irqs < smmu->num_global_irqs) {
1807                 dev_warn(dev, "found %d interrupts but expected at least %d\n",
1808                          num_irqs, smmu->num_global_irqs);
1809                 smmu->num_global_irqs = num_irqs;
1810         }
1811         smmu->num_context_irqs = num_irqs - smmu->num_global_irqs;
1812
1813         smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs,
1814                                   GFP_KERNEL);
1815         if (!smmu->irqs) {
1816                 dev_err(dev, "failed to allocate %d irqs\n", num_irqs);
1817                 return -ENOMEM;
1818         }
1819
1820         for (i = 0; i < num_irqs; ++i) {
1821                 int irq = platform_get_irq(pdev, i);
1822                 if (irq < 0) {
1823                         dev_err(dev, "failed to get irq index %d\n", i);
1824                         return -ENODEV;
1825                 }
1826                 smmu->irqs[i] = irq;
1827         }
1828
1829         i = 0;
1830         smmu->masters = RB_ROOT;
1831         while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters",
1832                                            "#stream-id-cells", i,
1833                                            &masterspec)) {
1834                 err = register_smmu_master(smmu, dev, &masterspec);
1835                 if (err) {
1836                         dev_err(dev, "failed to add master %s\n",
1837                                 masterspec.np->name);
1838                         goto out_put_masters;
1839                 }
1840
1841                 i++;
1842         }
1843         dev_notice(dev, "registered %d master devices\n", i);
1844
1845         if ((dev_node = of_parse_phandle(dev->of_node, "smmu-parent", 0)))
1846                 smmu->parent_of_node = dev_node;
1847
1848         err = arm_smmu_device_cfg_probe(smmu);
1849         if (err)
1850                 goto out_put_parent;
1851
1852         if (smmu->version > 1 &&
1853             smmu->num_context_banks != smmu->num_context_irqs) {
1854                 dev_err(dev,
1855                         "found only %d context interrupt(s) but %d required\n",
1856                         smmu->num_context_irqs, smmu->num_context_banks);
1857                 goto out_put_parent;
1858         }
1859
1860         arm_smmu_device_reset(smmu);
1861
1862         for (i = 0; i < smmu->num_global_irqs; ++i) {
1863                 err = request_irq(smmu->irqs[i],
1864                                   arm_smmu_global_fault,
1865                                   IRQF_SHARED,
1866                                   "arm-smmu global fault",
1867                                   smmu);
1868                 if (err) {
1869                         dev_err(dev, "failed to request global IRQ %d (%u)\n",
1870                                 i, smmu->irqs[i]);
1871                         goto out_free_irqs;
1872                 }
1873         }
1874
1875         INIT_LIST_HEAD(&smmu->list);
1876         spin_lock(&arm_smmu_devices_lock);
1877         list_add(&smmu->list, &arm_smmu_devices);
1878         spin_unlock(&arm_smmu_devices_lock);
1879         return 0;
1880
1881 out_free_irqs:
1882         while (i--)
1883                 free_irq(smmu->irqs[i], smmu);
1884
1885 out_put_parent:
1886         if (smmu->parent_of_node)
1887                 of_node_put(smmu->parent_of_node);
1888
1889 out_put_masters:
1890         for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1891                 struct arm_smmu_master *master;
1892                 master = container_of(node, struct arm_smmu_master, node);
1893                 of_node_put(master->of_node);
1894         }
1895
1896         return err;
1897 }
1898
1899 static int arm_smmu_device_remove(struct platform_device *pdev)
1900 {
1901         int i;
1902         struct device *dev = &pdev->dev;
1903         struct arm_smmu_device *curr, *smmu = NULL;
1904         struct rb_node *node;
1905
1906         spin_lock(&arm_smmu_devices_lock);
1907         list_for_each_entry(curr, &arm_smmu_devices, list) {
1908                 if (curr->dev == dev) {
1909                         smmu = curr;
1910                         list_del(&smmu->list);
1911                         break;
1912                 }
1913         }
1914         spin_unlock(&arm_smmu_devices_lock);
1915
1916         if (!smmu)
1917                 return -ENODEV;
1918
1919         if (smmu->parent_of_node)
1920                 of_node_put(smmu->parent_of_node);
1921
1922         for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1923                 struct arm_smmu_master *master;
1924                 master = container_of(node, struct arm_smmu_master, node);
1925                 of_node_put(master->of_node);
1926         }
1927
1928         if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS))
1929                 dev_err(dev, "removing device with active domains!\n");
1930
1931         for (i = 0; i < smmu->num_global_irqs; ++i)
1932                 free_irq(smmu->irqs[i], smmu);
1933
1934         /* Turn the thing off */
1935         writel(sCR0_CLIENTPD, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_sCR0);
1936         return 0;
1937 }
1938
1939 #ifdef CONFIG_OF
1940 static struct of_device_id arm_smmu_of_match[] = {
1941         { .compatible = "arm,smmu-v1", },
1942         { .compatible = "arm,smmu-v2", },
1943         { .compatible = "arm,mmu-400", },
1944         { .compatible = "arm,mmu-500", },
1945         { },
1946 };
1947 MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
1948 #endif
1949
1950 static struct platform_driver arm_smmu_driver = {
1951         .driver = {
1952                 .owner          = THIS_MODULE,
1953                 .name           = "arm-smmu",
1954                 .of_match_table = of_match_ptr(arm_smmu_of_match),
1955         },
1956         .probe  = arm_smmu_device_dt_probe,
1957         .remove = arm_smmu_device_remove,
1958 };
1959
1960 static int __init arm_smmu_init(void)
1961 {
1962         int ret;
1963
1964         ret = platform_driver_register(&arm_smmu_driver);
1965         if (ret)
1966                 return ret;
1967
1968         /* Oh, for a proper bus abstraction */
1969         if (!iommu_present(&platform_bus_type));
1970                 bus_set_iommu(&platform_bus_type, &arm_smmu_ops);
1971
1972         if (!iommu_present(&amba_bustype));
1973                 bus_set_iommu(&amba_bustype, &arm_smmu_ops);
1974
1975         return 0;
1976 }
1977
1978 static void __exit arm_smmu_exit(void)
1979 {
1980         return platform_driver_unregister(&arm_smmu_driver);
1981 }
1982
1983 module_init(arm_smmu_init);
1984 module_exit(arm_smmu_exit);
1985
1986 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
1987 MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
1988 MODULE_LICENSE("GPL v2");