drivers/iommu/exynos-iommu.c

   1 /*
   2  * Copyright (c) 2011,2016 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #ifdef CONFIG_EXYNOS_IOMMU_DEBUG
  11 #define DEBUG
  12 #endif
  13
  14 #include <linux/clk.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/iommu.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/list.h>
  21 #include <linux/of.h>
  22 #include <linux/of_iommu.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/slab.h>
  27 #include <linux/dma-iommu.h>
  28
  29 typedef u32 sysmmu_iova_t;
  30 typedef u32 sysmmu_pte_t;
  31
  32 /* We do not consider super section mapping (16MB) */
  33 #define SECT_ORDER 20
  34 #define LPAGE_ORDER 16
  35 #define SPAGE_ORDER 12
  36
  37 #define SECT_SIZE (1 << SECT_ORDER)
  38 #define LPAGE_SIZE (1 << LPAGE_ORDER)
  39 #define SPAGE_SIZE (1 << SPAGE_ORDER)
  40
  41 #define SECT_MASK (~(SECT_SIZE - 1))
  42 #define LPAGE_MASK (~(LPAGE_SIZE - 1))
  43 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
  44
  45 #define lv1ent_fault(sent) ((*(sent) == ZERO_LV2LINK) || \
  46                            ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3))
  47 #define lv1ent_zero(sent) (*(sent) == ZERO_LV2LINK)
  48 #define lv1ent_page_zero(sent) ((*(sent) & 3) == 1)
  49 #define lv1ent_page(sent) ((*(sent) != ZERO_LV2LINK) && \
  50                           ((*(sent) & 3) == 1))
  51 #define lv1ent_section(sent) ((*(sent) & 3) == 2)
  52
  53 #define lv2ent_fault(pent) ((*(pent) & 3) == 0)
  54 #define lv2ent_small(pent) ((*(pent) & 2) == 2)
  55 #define lv2ent_large(pent) ((*(pent) & 3) == 1)
  56
  57 #ifdef CONFIG_BIG_ENDIAN
  58 #warning "revisit driver if we can enable big-endian ptes"
  59 #endif
  60
  61 /*
  62  * v1.x - v3.x SYSMMU supports 32bit physical and 32bit virtual address spaces
  63  * v5.0 introduced support for 36bit physical address space by shifting
  64  * all page entry values by 4 bits.
  65  * All SYSMMU controllers in the system support the address spaces of the same
  66  * size, so PG_ENT_SHIFT can be initialized on first SYSMMU probe to proper
  67  * value (0 or 4).
  68  */
  69 static short PG_ENT_SHIFT = -1;
  70 #define SYSMMU_PG_ENT_SHIFT 0
  71 #define SYSMMU_V5_PG_ENT_SHIFT 4
  72
  73 #define sect_to_phys(ent) (((phys_addr_t) ent) << PG_ENT_SHIFT)
  74 #define section_phys(sent) (sect_to_phys(*(sent)) & SECT_MASK)
  75 #define section_offs(iova) (iova & (SECT_SIZE - 1))
  76 #define lpage_phys(pent) (sect_to_phys(*(pent)) & LPAGE_MASK)
  77 #define lpage_offs(iova) (iova & (LPAGE_SIZE - 1))
  78 #define spage_phys(pent) (sect_to_phys(*(pent)) & SPAGE_MASK)
  79 #define spage_offs(iova) (iova & (SPAGE_SIZE - 1))
  80
  81 #define NUM_LV1ENTRIES 4096
  82 #define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE)
  83
  84 static u32 lv1ent_offset(sysmmu_iova_t iova)
  85 {
  86         return iova >> SECT_ORDER;
  87 }
  88
  89 static u32 lv2ent_offset(sysmmu_iova_t iova)
  90 {
  91         return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1);
  92 }
  93
  94 #define LV1TABLE_SIZE (NUM_LV1ENTRIES * sizeof(sysmmu_pte_t))
  95 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t))
  96
  97 #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE)
  98 #define lv2table_base(sent) (sect_to_phys(*(sent) & 0xFFFFFFC0))
  99
 100 #define mk_lv1ent_sect(pa) ((pa >> PG_ENT_SHIFT) | 2)
 101 #define mk_lv1ent_page(pa) ((pa >> PG_ENT_SHIFT) | 1)
 102 #define mk_lv2ent_lpage(pa) ((pa >> PG_ENT_SHIFT) | 1)
 103 #define mk_lv2ent_spage(pa) ((pa >> PG_ENT_SHIFT) | 2)
 104
 105 #define CTRL_ENABLE     0x5
 106 #define CTRL_BLOCK      0x7
 107 #define CTRL_DISABLE    0x0
 108
 109 #define CFG_LRU         0x1
 110 #define CFG_QOS(n)      ((n & 0xF) << 7)
 111 #define CFG_ACGEN       (1 << 24) /* System MMU 3.3 only */
 112 #define CFG_SYSSEL      (1 << 22) /* System MMU 3.2 only */
 113 #define CFG_FLPDCACHE   (1 << 20) /* System MMU 3.2+ only */
 114
 115 /* common registers */
 116 #define REG_MMU_CTRL            0x000
 117 #define REG_MMU_CFG             0x004
 118 #define REG_MMU_STATUS          0x008
 119 #define REG_MMU_VERSION         0x034
 120
 121 #define MMU_MAJ_VER(val)        ((val) >> 7)
 122 #define MMU_MIN_VER(val)        ((val) & 0x7F)
 123 #define MMU_RAW_VER(reg)        (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */
 124
 125 #define MAKE_MMU_VER(maj, min)  ((((maj) & 0xF) << 7) | ((min) & 0x7F))
 126
 127 /* v1.x - v3.x registers */
 128 #define REG_MMU_FLUSH           0x00C
 129 #define REG_MMU_FLUSH_ENTRY     0x010
 130 #define REG_PT_BASE_ADDR        0x014
 131 #define REG_INT_STATUS          0x018
 132 #define REG_INT_CLEAR           0x01C
 133
 134 #define REG_PAGE_FAULT_ADDR     0x024
 135 #define REG_AW_FAULT_ADDR       0x028
 136 #define REG_AR_FAULT_ADDR       0x02C
 137 #define REG_DEFAULT_SLAVE_ADDR  0x030
 138
 139 /* v5.x registers */
 140 #define REG_V5_PT_BASE_PFN      0x00C
 141 #define REG_V5_MMU_FLUSH_ALL    0x010
 142 #define REG_V5_MMU_FLUSH_ENTRY  0x014
 143 #define REG_V5_INT_STATUS       0x060
 144 #define REG_V5_INT_CLEAR        0x064
 145 #define REG_V5_FAULT_AR_VA      0x070
 146 #define REG_V5_FAULT_AW_VA      0x080
 147
 148 #define has_sysmmu(dev)         (dev->archdata.iommu != NULL)
 149
 150 static struct device *dma_dev;
 151 static struct kmem_cache *lv2table_kmem_cache;
 152 static sysmmu_pte_t *zero_lv2_table;
 153 #define ZERO_LV2LINK mk_lv1ent_page(virt_to_phys(zero_lv2_table))
 154
 155 static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova)
 156 {
 157         return pgtable + lv1ent_offset(iova);
 158 }
 159
 160 static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova)
 161 {
 162         return (sysmmu_pte_t *)phys_to_virt(
 163                                 lv2table_base(sent)) + lv2ent_offset(iova);
 164 }
 165
 166 /*
 167  * IOMMU fault information register
 168  */
 169 struct sysmmu_fault_info {
 170         unsigned int bit;       /* bit number in STATUS register */
 171         unsigned short addr_reg; /* register to read VA fault address */
 172         const char *name;       /* human readable fault name */
 173         unsigned int type;      /* fault type for report_iommu_fault */
 174 };
 175
 176 static const struct sysmmu_fault_info sysmmu_faults[] = {
 177         { 0, REG_PAGE_FAULT_ADDR, "PAGE", IOMMU_FAULT_READ },
 178         { 1, REG_AR_FAULT_ADDR, "AR MULTI-HIT", IOMMU_FAULT_READ },
 179         { 2, REG_AW_FAULT_ADDR, "AW MULTI-HIT", IOMMU_FAULT_WRITE },
 180         { 3, REG_DEFAULT_SLAVE_ADDR, "BUS ERROR", IOMMU_FAULT_READ },
 181         { 4, REG_AR_FAULT_ADDR, "AR SECURITY PROTECTION", IOMMU_FAULT_READ },
 182         { 5, REG_AR_FAULT_ADDR, "AR ACCESS PROTECTION", IOMMU_FAULT_READ },
 183         { 6, REG_AW_FAULT_ADDR, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE },
 184         { 7, REG_AW_FAULT_ADDR, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE },
 185 };
 186
 187 static const struct sysmmu_fault_info sysmmu_v5_faults[] = {
 188         { 0, REG_V5_FAULT_AR_VA, "AR PTW", IOMMU_FAULT_READ },
 189         { 1, REG_V5_FAULT_AR_VA, "AR PAGE", IOMMU_FAULT_READ },
 190         { 2, REG_V5_FAULT_AR_VA, "AR MULTI-HIT", IOMMU_FAULT_READ },
 191         { 3, REG_V5_FAULT_AR_VA, "AR ACCESS PROTECTION", IOMMU_FAULT_READ },
 192         { 4, REG_V5_FAULT_AR_VA, "AR SECURITY PROTECTION", IOMMU_FAULT_READ },
 193         { 16, REG_V5_FAULT_AW_VA, "AW PTW", IOMMU_FAULT_WRITE },
 194         { 17, REG_V5_FAULT_AW_VA, "AW PAGE", IOMMU_FAULT_WRITE },
 195         { 18, REG_V5_FAULT_AW_VA, "AW MULTI-HIT", IOMMU_FAULT_WRITE },
 196         { 19, REG_V5_FAULT_AW_VA, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE },
 197         { 20, REG_V5_FAULT_AW_VA, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE },
 198 };
 199
 200 /*
 201  * This structure is attached to dev.archdata.iommu of the master device
 202  * on device add, contains a list of SYSMMU controllers defined by device tree,
 203  * which are bound to given master device. It is usually referenced by 'owner'
 204  * pointer.
 205 */
 206 struct exynos_iommu_owner {
 207         struct list_head controllers;   /* list of sysmmu_drvdata.owner_node */
 208         struct iommu_domain *domain;    /* domain this device is attached */
 209 };
 210
 211 /*
 212  * This structure exynos specific generalization of struct iommu_domain.
 213  * It contains list of SYSMMU controllers from all master devices, which has
 214  * been attached to this domain and page tables of IO address space defined by
 215  * it. It is usually referenced by 'domain' pointer.
 216  */
 217 struct exynos_iommu_domain {
 218         struct list_head clients; /* list of sysmmu_drvdata.domain_node */
 219         sysmmu_pte_t *pgtable;  /* lv1 page table, 16KB */
 220         short *lv2entcnt;       /* free lv2 entry counter for each section */
 221         spinlock_t lock;        /* lock for modyfying list of clients */
 222         spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
 223         struct iommu_domain domain; /* generic domain data structure */
 224 };
 225
 226 /*
 227  * This structure hold all data of a single SYSMMU controller, this includes
 228  * hw resources like registers and clocks, pointers and list nodes to connect
 229  * it to all other structures, internal state and parameters read from device
 230  * tree. It is usually referenced by 'data' pointer.
 231  */
 232 struct sysmmu_drvdata {
 233         struct device *sysmmu;          /* SYSMMU controller device */
 234         struct device *master;          /* master device (owner) */
 235         void __iomem *sfrbase;          /* our registers */
 236         struct clk *clk;                /* SYSMMU's clock */
 237         struct clk *aclk;               /* SYSMMU's aclk clock */
 238         struct clk *pclk;               /* SYSMMU's pclk clock */
 239         struct clk *clk_master;         /* master's device clock */
 240         int activations;                /* number of calls to sysmmu_enable */
 241         spinlock_t lock;                /* lock for modyfying state */
 242         struct exynos_iommu_domain *domain; /* domain we belong to */
 243         struct list_head domain_node;   /* node for domain clients list */
 244         struct list_head owner_node;    /* node for owner controllers list */
 245         phys_addr_t pgtable;            /* assigned page table structure */
 246         unsigned int version;           /* our version */
 247 };
 248
 249 static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom)
 250 {
 251         return container_of(dom, struct exynos_iommu_domain, domain);
 252 }
 253
 254 static bool set_sysmmu_active(struct sysmmu_drvdata *data)
 255 {
 256         /* return true if the System MMU was not active previously
 257            and it needs to be initialized */
 258         return ++data->activations == 1;
 259 }
 260
 261 static bool set_sysmmu_inactive(struct sysmmu_drvdata *data)
 262 {
 263         /* return true if the System MMU is needed to be disabled */
 264         BUG_ON(data->activations < 1);
 265         return --data->activations == 0;
 266 }
 267
 268 static bool is_sysmmu_active(struct sysmmu_drvdata *data)
 269 {
 270         return data->activations > 0;
 271 }
 272
 273 static void sysmmu_unblock(struct sysmmu_drvdata *data)
 274 {
 275         writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
 276 }
 277
 278 static bool sysmmu_block(struct sysmmu_drvdata *data)
 279 {
 280         int i = 120;
 281
 282         writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
 283         while ((i > 0) && !(readl(data->sfrbase + REG_MMU_STATUS) & 1))
 284                 --i;
 285
 286         if (!(readl(data->sfrbase + REG_MMU_STATUS) & 1)) {
 287                 sysmmu_unblock(data);
 288                 return false;
 289         }
 290
 291         return true;
 292 }
 293
 294 static void __sysmmu_tlb_invalidate(struct sysmmu_drvdata *data)
 295 {
 296         if (MMU_MAJ_VER(data->version) < 5)
 297                 writel(0x1, data->sfrbase + REG_MMU_FLUSH);
 298         else
 299                 writel(0x1, data->sfrbase + REG_V5_MMU_FLUSH_ALL);
 300 }
 301
 302 static void __sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data,
 303                                 sysmmu_iova_t iova, unsigned int num_inv)
 304 {
 305         unsigned int i;
 306
 307         for (i = 0; i < num_inv; i++) {
 308                 if (MMU_MAJ_VER(data->version) < 5)
 309                         writel((iova & SPAGE_MASK) | 1,
 310                                      data->sfrbase + REG_MMU_FLUSH_ENTRY);
 311                 else
 312                         writel((iova & SPAGE_MASK) | 1,
 313                                      data->sfrbase + REG_V5_MMU_FLUSH_ENTRY);
 314                 iova += SPAGE_SIZE;
 315         }
 316 }
 317
 318 static void __sysmmu_set_ptbase(struct sysmmu_drvdata *data, phys_addr_t pgd)
 319 {
 320         if (MMU_MAJ_VER(data->version) < 5)
 321                 writel(pgd, data->sfrbase + REG_PT_BASE_ADDR);
 322         else
 323                 writel(pgd >> PAGE_SHIFT,
 324                              data->sfrbase + REG_V5_PT_BASE_PFN);
 325
 326         __sysmmu_tlb_invalidate(data);
 327 }
 328
 329 static void __sysmmu_enable_clocks(struct sysmmu_drvdata *data)
 330 {
 331         BUG_ON(clk_prepare_enable(data->clk_master));
 332         BUG_ON(clk_prepare_enable(data->clk));
 333         BUG_ON(clk_prepare_enable(data->pclk));
 334         BUG_ON(clk_prepare_enable(data->aclk));
 335 }
 336
 337 static void __sysmmu_disable_clocks(struct sysmmu_drvdata *data)
 338 {
 339         clk_disable_unprepare(data->aclk);
 340         clk_disable_unprepare(data->pclk);
 341         clk_disable_unprepare(data->clk);
 342         clk_disable_unprepare(data->clk_master);
 343 }
 344
 345 static void __sysmmu_get_version(struct sysmmu_drvdata *data)
 346 {
 347         u32 ver;
 348
 349         __sysmmu_enable_clocks(data);
 350
 351         ver = readl(data->sfrbase + REG_MMU_VERSION);
 352
 353         /* controllers on some SoCs don't report proper version */
 354         if (ver == 0x80000001u)
 355                 data->version = MAKE_MMU_VER(1, 0);
 356         else
 357                 data->version = MMU_RAW_VER(ver);
 358
 359         dev_dbg(data->sysmmu, "hardware version: %d.%d\n",
 360                 MMU_MAJ_VER(data->version), MMU_MIN_VER(data->version));
 361
 362         __sysmmu_disable_clocks(data);
 363 }
 364
 365 static void show_fault_information(struct sysmmu_drvdata *data,
 366                                    const struct sysmmu_fault_info *finfo,
 367                                    sysmmu_iova_t fault_addr)
 368 {
 369         sysmmu_pte_t *ent;
 370
 371         dev_err(data->sysmmu, "%s FAULT occurred at %#x (page table base: %pa)\n",
 372                 finfo->name, fault_addr, &data->pgtable);
 373         ent = section_entry(phys_to_virt(data->pgtable), fault_addr);
 374         dev_err(data->sysmmu, "\tLv1 entry: %#x\n", *ent);
 375         if (lv1ent_page(ent)) {
 376                 ent = page_entry(ent, fault_addr);
 377                 dev_err(data->sysmmu, "\t Lv2 entry: %#x\n", *ent);
 378         }
 379 }
 380
 381 static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
 382 {
 383         /* SYSMMU is in blocked state when interrupt occurred. */
 384         struct sysmmu_drvdata *data = dev_id;
 385         const struct sysmmu_fault_info *finfo;
 386         unsigned int i, n, itype;
 387         sysmmu_iova_t fault_addr = -1;
 388         unsigned short reg_status, reg_clear;
 389         int ret = -ENOSYS;
 390
 391         WARN_ON(!is_sysmmu_active(data));
 392
 393         if (MMU_MAJ_VER(data->version) < 5) {
 394                 reg_status = REG_INT_STATUS;
 395                 reg_clear = REG_INT_CLEAR;
 396                 finfo = sysmmu_faults;
 397                 n = ARRAY_SIZE(sysmmu_faults);
 398         } else {
 399                 reg_status = REG_V5_INT_STATUS;
 400                 reg_clear = REG_V5_INT_CLEAR;
 401                 finfo = sysmmu_v5_faults;
 402                 n = ARRAY_SIZE(sysmmu_v5_faults);
 403         }
 404
 405         spin_lock(&data->lock);
 406
 407         clk_enable(data->clk_master);
 408
 409         itype = __ffs(readl(data->sfrbase + reg_status));
 410         for (i = 0; i < n; i++, finfo++)
 411                 if (finfo->bit == itype)
 412                         break;
 413         /* unknown/unsupported fault */
 414         BUG_ON(i == n);
 415
 416         /* print debug message */
 417         fault_addr = readl(data->sfrbase + finfo->addr_reg);
 418         show_fault_information(data, finfo, fault_addr);
 419
 420         if (data->domain)
 421                 ret = report_iommu_fault(&data->domain->domain,
 422                                         data->master, fault_addr, finfo->type);
 423         /* fault is not recovered by fault handler */
 424         BUG_ON(ret != 0);
 425
 426         writel(1 << itype, data->sfrbase + reg_clear);
 427
 428         sysmmu_unblock(data);
 429
 430         clk_disable(data->clk_master);
 431
 432         spin_unlock(&data->lock);
 433
 434         return IRQ_HANDLED;
 435 }
 436
 437 static void __sysmmu_disable_nocount(struct sysmmu_drvdata *data)
 438 {
 439         clk_enable(data->clk_master);
 440
 441         writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL);
 442         writel(0, data->sfrbase + REG_MMU_CFG);
 443
 444         __sysmmu_disable_clocks(data);
 445 }
 446
 447 static bool __sysmmu_disable(struct sysmmu_drvdata *data)
 448 {
 449         bool disabled;
 450         unsigned long flags;
 451
 452         spin_lock_irqsave(&data->lock, flags);
 453
 454         disabled = set_sysmmu_inactive(data);
 455
 456         if (disabled) {
 457                 data->pgtable = 0;
 458                 data->domain = NULL;
 459
 460                 __sysmmu_disable_nocount(data);
 461
 462                 dev_dbg(data->sysmmu, "Disabled\n");
 463         } else  {
 464                 dev_dbg(data->sysmmu, "%d times left to disable\n",
 465                                         data->activations);
 466         }
 467
 468         spin_unlock_irqrestore(&data->lock, flags);
 469
 470         return disabled;
 471 }
 472
 473 static void __sysmmu_init_config(struct sysmmu_drvdata *data)
 474 {
 475         unsigned int cfg;
 476
 477         if (data->version <= MAKE_MMU_VER(3, 1))
 478                 cfg = CFG_LRU | CFG_QOS(15);
 479         else if (data->version <= MAKE_MMU_VER(3, 2))
 480                 cfg = CFG_LRU | CFG_QOS(15) | CFG_FLPDCACHE | CFG_SYSSEL;
 481         else
 482                 cfg = CFG_QOS(15) | CFG_FLPDCACHE | CFG_ACGEN;
 483
 484         writel(cfg, data->sfrbase + REG_MMU_CFG);
 485 }
 486
 487 static void __sysmmu_enable_nocount(struct sysmmu_drvdata *data)
 488 {
 489         __sysmmu_enable_clocks(data);
 490
 491         writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
 492
 493         __sysmmu_init_config(data);
 494
 495         __sysmmu_set_ptbase(data, data->pgtable);
 496
 497         writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
 498
 499         /*
 500          * SYSMMU driver keeps master's clock enabled only for the short
 501          * time, while accessing the registers. For performing address
 502          * translation during DMA transaction it relies on the client
 503          * driver to enable it.
 504          */
 505         clk_disable(data->clk_master);
 506 }
 507
 508 static int __sysmmu_enable(struct sysmmu_drvdata *data, phys_addr_t pgtable,
 509                            struct exynos_iommu_domain *domain)
 510 {
 511         int ret = 0;
 512         unsigned long flags;
 513
 514         spin_lock_irqsave(&data->lock, flags);
 515         if (set_sysmmu_active(data)) {
 516                 data->pgtable = pgtable;
 517                 data->domain = domain;
 518
 519                 __sysmmu_enable_nocount(data);
 520
 521                 dev_dbg(data->sysmmu, "Enabled\n");
 522         } else {
 523                 ret = (pgtable == data->pgtable) ? 1 : -EBUSY;
 524
 525                 dev_dbg(data->sysmmu, "already enabled\n");
 526         }
 527
 528         if (WARN_ON(ret < 0))
 529                 set_sysmmu_inactive(data); /* decrement count */
 530
 531         spin_unlock_irqrestore(&data->lock, flags);
 532
 533         return ret;
 534 }
 535
 536 static void sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data,
 537                                             sysmmu_iova_t iova)
 538 {
 539         unsigned long flags;
 540
 541
 542         spin_lock_irqsave(&data->lock, flags);
 543         if (is_sysmmu_active(data) && data->version >= MAKE_MMU_VER(3, 3)) {
 544                 clk_enable(data->clk_master);
 545                 __sysmmu_tlb_invalidate_entry(data, iova, 1);
 546                 clk_disable(data->clk_master);
 547         }
 548         spin_unlock_irqrestore(&data->lock, flags);
 549
 550 }
 551
 552 static void sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data,
 553                                         sysmmu_iova_t iova, size_t size)
 554 {
 555         unsigned long flags;
 556
 557         spin_lock_irqsave(&data->lock, flags);
 558         if (is_sysmmu_active(data)) {
 559                 unsigned int num_inv = 1;
 560
 561                 clk_enable(data->clk_master);
 562
 563                 /*
 564                  * L2TLB invalidation required
 565                  * 4KB page: 1 invalidation
 566                  * 64KB page: 16 invalidations
 567                  * 1MB page: 64 invalidations
 568                  * because it is set-associative TLB
 569                  * with 8-way and 64 sets.
 570                  * 1MB page can be cached in one of all sets.
 571                  * 64KB page can be one of 16 consecutive sets.
 572                  */
 573                 if (MMU_MAJ_VER(data->version) == 2)
 574                         num_inv = min_t(unsigned int, size / PAGE_SIZE, 64);
 575
 576                 if (sysmmu_block(data)) {
 577                         __sysmmu_tlb_invalidate_entry(data, iova, num_inv);
 578                         sysmmu_unblock(data);
 579                 }
 580                 clk_disable(data->clk_master);
 581         } else {
 582                 dev_dbg(data->master,
 583                         "disabled. Skipping TLB invalidation @ %#x\n", iova);
 584         }
 585         spin_unlock_irqrestore(&data->lock, flags);
 586 }
 587
 588 static struct iommu_ops exynos_iommu_ops;
 589
 590 static int __init exynos_sysmmu_probe(struct platform_device *pdev)
 591 {
 592         int irq, ret;
 593         struct device *dev = &pdev->dev;
 594         struct sysmmu_drvdata *data;
 595         struct resource *res;
 596
 597         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 598         if (!data)
 599                 return -ENOMEM;
 600
 601         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 602         data->sfrbase = devm_ioremap_resource(dev, res);
 603         if (IS_ERR(data->sfrbase))
 604                 return PTR_ERR(data->sfrbase);
 605
 606         irq = platform_get_irq(pdev, 0);
 607         if (irq <= 0) {
 608                 dev_err(dev, "Unable to find IRQ resource\n");
 609                 return irq;
 610         }
 611
 612         ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0,
 613                                 dev_name(dev), data);
 614         if (ret) {
 615                 dev_err(dev, "Unabled to register handler of irq %d\n", irq);
 616                 return ret;
 617         }
 618
 619         data->clk = devm_clk_get(dev, "sysmmu");
 620         if (PTR_ERR(data->clk) == -ENOENT)
 621                 data->clk = NULL;
 622         else if (IS_ERR(data->clk))
 623                 return PTR_ERR(data->clk);
 624
 625         data->aclk = devm_clk_get(dev, "aclk");
 626         if (PTR_ERR(data->aclk) == -ENOENT)
 627                 data->aclk = NULL;
 628         else if (IS_ERR(data->aclk))
 629                 return PTR_ERR(data->aclk);
 630
 631         data->pclk = devm_clk_get(dev, "pclk");
 632         if (PTR_ERR(data->pclk) == -ENOENT)
 633                 data->pclk = NULL;
 634         else if (IS_ERR(data->pclk))
 635                 return PTR_ERR(data->pclk);
 636
 637         if (!data->clk && (!data->aclk || !data->pclk)) {
 638                 dev_err(dev, "Failed to get device clock(s)!\n");
 639                 return -ENOSYS;
 640         }
 641
 642         data->clk_master = devm_clk_get(dev, "master");
 643         if (PTR_ERR(data->clk_master) == -ENOENT)
 644                 data->clk_master = NULL;
 645         else if (IS_ERR(data->clk_master))
 646                 return PTR_ERR(data->clk_master);
 647
 648         data->sysmmu = dev;
 649         spin_lock_init(&data->lock);
 650
 651         platform_set_drvdata(pdev, data);
 652
 653         __sysmmu_get_version(data);
 654         if (PG_ENT_SHIFT < 0) {
 655                 if (MMU_MAJ_VER(data->version) < 5)
 656                         PG_ENT_SHIFT = SYSMMU_PG_ENT_SHIFT;
 657                 else
 658                         PG_ENT_SHIFT = SYSMMU_V5_PG_ENT_SHIFT;
 659         }
 660
 661         pm_runtime_enable(dev);
 662
 663         of_iommu_set_ops(dev->of_node, &exynos_iommu_ops);
 664
 665         return 0;
 666 }
 667
 668 #ifdef CONFIG_PM_SLEEP
 669 static int exynos_sysmmu_suspend(struct device *dev)
 670 {
 671         struct sysmmu_drvdata *data = dev_get_drvdata(dev);
 672
 673         dev_dbg(dev, "suspend\n");
 674         if (is_sysmmu_active(data)) {
 675                 __sysmmu_disable_nocount(data);
 676                 pm_runtime_put(dev);
 677         }
 678         return 0;
 679 }
 680
 681 static int exynos_sysmmu_resume(struct device *dev)
 682 {
 683         struct sysmmu_drvdata *data = dev_get_drvdata(dev);
 684
 685         dev_dbg(dev, "resume\n");
 686         if (is_sysmmu_active(data)) {
 687                 pm_runtime_get_sync(dev);
 688                 __sysmmu_enable_nocount(data);
 689         }
 690         return 0;
 691 }
 692 #endif
 693
 694 static const struct dev_pm_ops sysmmu_pm_ops = {
 695         SET_LATE_SYSTEM_SLEEP_PM_OPS(exynos_sysmmu_suspend, exynos_sysmmu_resume)
 696 };
 697
 698 static const struct of_device_id sysmmu_of_match[] __initconst = {
 699         { .compatible   = "samsung,exynos-sysmmu", },
 700         { },
 701 };
 702
 703 static struct platform_driver exynos_sysmmu_driver __refdata = {
 704         .probe  = exynos_sysmmu_probe,
 705         .driver = {
 706                 .name           = "exynos-sysmmu",
 707                 .of_match_table = sysmmu_of_match,
 708                 .pm             = &sysmmu_pm_ops,
 709                 .suppress_bind_attrs = true,
 710         }
 711 };
 712
 713 static inline void update_pte(sysmmu_pte_t *ent, sysmmu_pte_t val)
 714 {
 715         dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), sizeof(*ent),
 716                                 DMA_TO_DEVICE);
 717         *ent = cpu_to_le32(val);
 718         dma_sync_single_for_device(dma_dev, virt_to_phys(ent), sizeof(*ent),
 719                                    DMA_TO_DEVICE);
 720 }
 721
 722 static struct iommu_domain *exynos_iommu_domain_alloc(unsigned type)
 723 {
 724         struct exynos_iommu_domain *domain;
 725         dma_addr_t handle;
 726         int i;
 727
 728         /* Check if correct PTE offsets are initialized */
 729         BUG_ON(PG_ENT_SHIFT < 0 || !dma_dev);
 730
 731         domain = kzalloc(sizeof(*domain), GFP_KERNEL);
 732         if (!domain)
 733                 return NULL;
 734
 735         if (type == IOMMU_DOMAIN_DMA) {
 736                 if (iommu_get_dma_cookie(&domain->domain) != 0)
 737                         goto err_pgtable;
 738         } else if (type != IOMMU_DOMAIN_UNMANAGED) {
 739                 goto err_pgtable;
 740         }
 741
 742         domain->pgtable = (sysmmu_pte_t *)__get_free_pages(GFP_KERNEL, 2);
 743         if (!domain->pgtable)
 744                 goto err_dma_cookie;
 745
 746         domain->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 1);
 747         if (!domain->lv2entcnt)
 748                 goto err_counter;
 749
 750         /* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */
 751         for (i = 0; i < NUM_LV1ENTRIES; i += 8) {
 752                 domain->pgtable[i + 0] = ZERO_LV2LINK;
 753                 domain->pgtable[i + 1] = ZERO_LV2LINK;
 754                 domain->pgtable[i + 2] = ZERO_LV2LINK;
 755                 domain->pgtable[i + 3] = ZERO_LV2LINK;
 756                 domain->pgtable[i + 4] = ZERO_LV2LINK;
 757                 domain->pgtable[i + 5] = ZERO_LV2LINK;
 758                 domain->pgtable[i + 6] = ZERO_LV2LINK;
 759                 domain->pgtable[i + 7] = ZERO_LV2LINK;
 760         }
 761
 762         handle = dma_map_single(dma_dev, domain->pgtable, LV1TABLE_SIZE,
 763                                 DMA_TO_DEVICE);
 764         /* For mapping page table entries we rely on dma == phys */
 765         BUG_ON(handle != virt_to_phys(domain->pgtable));
 766
 767         spin_lock_init(&domain->lock);
 768         spin_lock_init(&domain->pgtablelock);
 769         INIT_LIST_HEAD(&domain->clients);
 770
 771         domain->domain.geometry.aperture_start = 0;
 772         domain->domain.geometry.aperture_end   = ~0UL;
 773         domain->domain.geometry.force_aperture = true;
 774
 775         return &domain->domain;
 776
 777 err_counter:
 778         free_pages((unsigned long)domain->pgtable, 2);
 779 err_dma_cookie:
 780         if (type == IOMMU_DOMAIN_DMA)
 781                 iommu_put_dma_cookie(&domain->domain);
 782 err_pgtable:
 783         kfree(domain);
 784         return NULL;
 785 }
 786
 787 static void exynos_iommu_domain_free(struct iommu_domain *iommu_domain)
 788 {
 789         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 790         struct sysmmu_drvdata *data, *next;
 791         unsigned long flags;
 792         int i;
 793
 794         WARN_ON(!list_empty(&domain->clients));
 795
 796         spin_lock_irqsave(&domain->lock, flags);
 797
 798         list_for_each_entry_safe(data, next, &domain->clients, domain_node) {
 799                 if (__sysmmu_disable(data))
 800                         data->master = NULL;
 801                 list_del_init(&data->domain_node);
 802         }
 803
 804         spin_unlock_irqrestore(&domain->lock, flags);
 805
 806         if (iommu_domain->type == IOMMU_DOMAIN_DMA)
 807                 iommu_put_dma_cookie(iommu_domain);
 808
 809         dma_unmap_single(dma_dev, virt_to_phys(domain->pgtable), LV1TABLE_SIZE,
 810                          DMA_TO_DEVICE);
 811
 812         for (i = 0; i < NUM_LV1ENTRIES; i++)
 813                 if (lv1ent_page(domain->pgtable + i)) {
 814                         phys_addr_t base = lv2table_base(domain->pgtable + i);
 815
 816                         dma_unmap_single(dma_dev, base, LV2TABLE_SIZE,
 817                                          DMA_TO_DEVICE);
 818                         kmem_cache_free(lv2table_kmem_cache,
 819                                         phys_to_virt(base));
 820                 }
 821
 822         free_pages((unsigned long)domain->pgtable, 2);
 823         free_pages((unsigned long)domain->lv2entcnt, 1);
 824         kfree(domain);
 825 }
 826
 827 static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain,
 828                                     struct device *dev)
 829 {
 830         struct exynos_iommu_owner *owner = dev->archdata.iommu;
 831         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 832         phys_addr_t pagetable = virt_to_phys(domain->pgtable);
 833         struct sysmmu_drvdata *data, *next;
 834         unsigned long flags;
 835         bool found = false;
 836
 837         if (!has_sysmmu(dev) || owner->domain != iommu_domain)
 838                 return;
 839
 840         spin_lock_irqsave(&domain->lock, flags);
 841         list_for_each_entry_safe(data, next, &domain->clients, domain_node) {
 842                 if (data->master == dev) {
 843                         if (__sysmmu_disable(data)) {
 844                                 data->master = NULL;
 845                                 list_del_init(&data->domain_node);
 846                         }
 847                         pm_runtime_put(data->sysmmu);
 848                         found = true;
 849                 }
 850         }
 851         spin_unlock_irqrestore(&domain->lock, flags);
 852
 853         owner->domain = NULL;
 854
 855         if (found)
 856                 dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n",
 857                                         __func__, &pagetable);
 858         else
 859                 dev_err(dev, "%s: No IOMMU is attached\n", __func__);
 860 }
 861
 862 static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain,
 863                                    struct device *dev)
 864 {
 865         struct exynos_iommu_owner *owner = dev->archdata.iommu;
 866         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 867         struct sysmmu_drvdata *data;
 868         phys_addr_t pagetable = virt_to_phys(domain->pgtable);
 869         unsigned long flags;
 870         int ret = -ENODEV;
 871
 872         if (!has_sysmmu(dev))
 873                 return -ENODEV;
 874
 875         if (owner->domain)
 876                 exynos_iommu_detach_device(owner->domain, dev);
 877
 878         list_for_each_entry(data, &owner->controllers, owner_node) {
 879                 pm_runtime_get_sync(data->sysmmu);
 880                 ret = __sysmmu_enable(data, pagetable, domain);
 881                 if (ret >= 0) {
 882                         data->master = dev;
 883
 884                         spin_lock_irqsave(&domain->lock, flags);
 885                         list_add_tail(&data->domain_node, &domain->clients);
 886                         spin_unlock_irqrestore(&domain->lock, flags);
 887                 }
 888         }
 889
 890         if (ret < 0) {
 891                 dev_err(dev, "%s: Failed to attach IOMMU with pgtable %pa\n",
 892                                         __func__, &pagetable);
 893                 return ret;
 894         }
 895
 896         owner->domain = iommu_domain;
 897         dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa %s\n",
 898                 __func__, &pagetable, (ret == 0) ? "" : ", again");
 899
 900         return ret;
 901 }
 902
 903 static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *domain,
 904                 sysmmu_pte_t *sent, sysmmu_iova_t iova, short *pgcounter)
 905 {
 906         if (lv1ent_section(sent)) {
 907                 WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova);
 908                 return ERR_PTR(-EADDRINUSE);
 909         }
 910
 911         if (lv1ent_fault(sent)) {
 912                 sysmmu_pte_t *pent;
 913                 bool need_flush_flpd_cache = lv1ent_zero(sent);
 914
 915                 pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
 916                 BUG_ON((uintptr_t)pent & (LV2TABLE_SIZE - 1));
 917                 if (!pent)
 918                         return ERR_PTR(-ENOMEM);
 919
 920                 update_pte(sent, mk_lv1ent_page(virt_to_phys(pent)));
 921                 kmemleak_ignore(pent);
 922                 *pgcounter = NUM_LV2ENTRIES;
 923                 dma_map_single(dma_dev, pent, LV2TABLE_SIZE, DMA_TO_DEVICE);
 924
 925                 /*
 926                  * If pre-fetched SLPD is a faulty SLPD in zero_l2_table,
 927                  * FLPD cache may cache the address of zero_l2_table. This
 928                  * function replaces the zero_l2_table with new L2 page table
 929                  * to write valid mappings.
 930                  * Accessing the valid area may cause page fault since FLPD
 931                  * cache may still cache zero_l2_table for the valid area
 932                  * instead of new L2 page table that has the mapping
 933                  * information of the valid area.
 934                  * Thus any replacement of zero_l2_table with other valid L2
 935                  * page table must involve FLPD cache invalidation for System
 936                  * MMU v3.3.
 937                  * FLPD cache invalidation is performed with TLB invalidation
 938                  * by VPN without blocking. It is safe to invalidate TLB without
 939                  * blocking because the target address of TLB invalidation is
 940                  * not currently mapped.
 941                  */
 942                 if (need_flush_flpd_cache) {
 943                         struct sysmmu_drvdata *data;
 944
 945                         spin_lock(&domain->lock);
 946                         list_for_each_entry(data, &domain->clients, domain_node)
 947                                 sysmmu_tlb_invalidate_flpdcache(data, iova);
 948                         spin_unlock(&domain->lock);
 949                 }
 950         }
 951
 952         return page_entry(sent, iova);
 953 }
 954
 955 static int lv1set_section(struct exynos_iommu_domain *domain,
 956                           sysmmu_pte_t *sent, sysmmu_iova_t iova,
 957                           phys_addr_t paddr, short *pgcnt)
 958 {
 959         if (lv1ent_section(sent)) {
 960                 WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
 961                         iova);
 962                 return -EADDRINUSE;
 963         }
 964
 965         if (lv1ent_page(sent)) {
 966                 if (*pgcnt != NUM_LV2ENTRIES) {
 967                         WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
 968                                 iova);
 969                         return -EADDRINUSE;
 970                 }
 971
 972                 kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0));
 973                 *pgcnt = 0;
 974         }
 975
 976         update_pte(sent, mk_lv1ent_sect(paddr));
 977
 978         spin_lock(&domain->lock);
 979         if (lv1ent_page_zero(sent)) {
 980                 struct sysmmu_drvdata *data;
 981                 /*
 982                  * Flushing FLPD cache in System MMU v3.3 that may cache a FLPD
 983                  * entry by speculative prefetch of SLPD which has no mapping.
 984                  */
 985                 list_for_each_entry(data, &domain->clients, domain_node)
 986                         sysmmu_tlb_invalidate_flpdcache(data, iova);
 987         }
 988         spin_unlock(&domain->lock);
 989
 990         return 0;
 991 }
 992
 993 static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size,
 994                                                                 short *pgcnt)
 995 {
 996         if (size == SPAGE_SIZE) {
 997                 if (WARN_ON(!lv2ent_fault(pent)))
 998                         return -EADDRINUSE;
 999
1000                 update_pte(pent, mk_lv2ent_spage(paddr));
1001                 *pgcnt -= 1;
1002         } else { /* size == LPAGE_SIZE */
1003                 int i;
1004                 dma_addr_t pent_base = virt_to_phys(pent);
1005
1006                 dma_sync_single_for_cpu(dma_dev, pent_base,
1007                                         sizeof(*pent) * SPAGES_PER_LPAGE,
1008                                         DMA_TO_DEVICE);
1009                 for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) {
1010                         if (WARN_ON(!lv2ent_fault(pent))) {
1011                                 if (i > 0)
1012                                         memset(pent - i, 0, sizeof(*pent) * i);
1013                                 return -EADDRINUSE;
1014                         }
1015
1016                         *pent = mk_lv2ent_lpage(paddr);
1017                 }
1018                 dma_sync_single_for_device(dma_dev, pent_base,
1019                                            sizeof(*pent) * SPAGES_PER_LPAGE,
1020                                            DMA_TO_DEVICE);
1021                 *pgcnt -= SPAGES_PER_LPAGE;
1022         }
1023
1024         return 0;
1025 }
1026
1027 /*
1028  * *CAUTION* to the I/O virtual memory managers that support exynos-iommu:
1029  *
1030  * System MMU v3.x has advanced logic to improve address translation
1031  * performance with caching more page table entries by a page table walk.
1032  * However, the logic has a bug that while caching faulty page table entries,
1033  * System MMU reports page fault if the cached fault entry is hit even though
1034  * the fault entry is updated to a valid entry after the entry is cached.
1035  * To prevent caching faulty page table entries which may be updated to valid
1036  * entries later, the virtual memory manager should care about the workaround
1037  * for the problem. The following describes the workaround.
1038  *
1039  * Any two consecutive I/O virtual address regions must have a hole of 128KiB
1040  * at maximum to prevent misbehavior of System MMU 3.x (workaround for h/w bug).
1041  *
1042  * Precisely, any start address of I/O virtual region must be aligned with
1043  * the following sizes for System MMU v3.1 and v3.2.
1044  * System MMU v3.1: 128KiB
1045  * System MMU v3.2: 256KiB
1046  *
1047  * Because System MMU v3.3 caches page table entries more aggressively, it needs
1048  * more workarounds.
1049  * - Any two consecutive I/O virtual regions must have a hole of size larger
1050  *   than or equal to 128KiB.
1051  * - Start address of an I/O virtual region must be aligned by 128KiB.
1052  */
1053 static int exynos_iommu_map(struct iommu_domain *iommu_domain,
1054                             unsigned long l_iova, phys_addr_t paddr, size_t size,
1055                             int prot)
1056 {
1057         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1058         sysmmu_pte_t *entry;
1059         sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
1060         unsigned long flags;
1061         int ret = -ENOMEM;
1062
1063         BUG_ON(domain->pgtable == NULL);
1064
1065         spin_lock_irqsave(&domain->pgtablelock, flags);
1066
1067         entry = section_entry(domain->pgtable, iova);
1068
1069         if (size == SECT_SIZE) {
1070                 ret = lv1set_section(domain, entry, iova, paddr,
1071                                      &domain->lv2entcnt[lv1ent_offset(iova)]);
1072         } else {
1073                 sysmmu_pte_t *pent;
1074
1075                 pent = alloc_lv2entry(domain, entry, iova,
1076                                       &domain->lv2entcnt[lv1ent_offset(iova)]);
1077
1078                 if (IS_ERR(pent))
1079                         ret = PTR_ERR(pent);
1080                 else
1081                         ret = lv2set_page(pent, paddr, size,
1082                                        &domain->lv2entcnt[lv1ent_offset(iova)]);
1083         }
1084
1085         if (ret)
1086                 pr_err("%s: Failed(%d) to map %#zx bytes @ %#x\n",
1087                         __func__, ret, size, iova);
1088
1089         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1090
1091         return ret;
1092 }
1093
1094 static void exynos_iommu_tlb_invalidate_entry(struct exynos_iommu_domain *domain,
1095                                               sysmmu_iova_t iova, size_t size)
1096 {
1097         struct sysmmu_drvdata *data;
1098         unsigned long flags;
1099
1100         spin_lock_irqsave(&domain->lock, flags);
1101
1102         list_for_each_entry(data, &domain->clients, domain_node)
1103                 sysmmu_tlb_invalidate_entry(data, iova, size);
1104
1105         spin_unlock_irqrestore(&domain->lock, flags);
1106 }
1107
1108 static size_t exynos_iommu_unmap(struct iommu_domain *iommu_domain,
1109                                  unsigned long l_iova, size_t size)
1110 {
1111         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1112         sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
1113         sysmmu_pte_t *ent;
1114         size_t err_pgsize;
1115         unsigned long flags;
1116
1117         BUG_ON(domain->pgtable == NULL);
1118
1119         spin_lock_irqsave(&domain->pgtablelock, flags);
1120
1121         ent = section_entry(domain->pgtable, iova);
1122
1123         if (lv1ent_section(ent)) {
1124                 if (WARN_ON(size < SECT_SIZE)) {
1125                         err_pgsize = SECT_SIZE;
1126                         goto err;
1127                 }
1128
1129                 /* workaround for h/w bug in System MMU v3.3 */
1130                 update_pte(ent, ZERO_LV2LINK);
1131                 size = SECT_SIZE;
1132                 goto done;
1133         }
1134
1135         if (unlikely(lv1ent_fault(ent))) {
1136                 if (size > SECT_SIZE)
1137                         size = SECT_SIZE;
1138                 goto done;
1139         }
1140
1141         /* lv1ent_page(sent) == true here */
1142
1143         ent = page_entry(ent, iova);
1144
1145         if (unlikely(lv2ent_fault(ent))) {
1146                 size = SPAGE_SIZE;
1147                 goto done;
1148         }
1149
1150         if (lv2ent_small(ent)) {
1151                 update_pte(ent, 0);
1152                 size = SPAGE_SIZE;
1153                 domain->lv2entcnt[lv1ent_offset(iova)] += 1;
1154                 goto done;
1155         }
1156
1157         /* lv1ent_large(ent) == true here */
1158         if (WARN_ON(size < LPAGE_SIZE)) {
1159                 err_pgsize = LPAGE_SIZE;
1160                 goto err;
1161         }
1162
1163         dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent),
1164                                 sizeof(*ent) * SPAGES_PER_LPAGE,
1165                                 DMA_TO_DEVICE);
1166         memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE);
1167         dma_sync_single_for_device(dma_dev, virt_to_phys(ent),
1168                                    sizeof(*ent) * SPAGES_PER_LPAGE,
1169                                    DMA_TO_DEVICE);
1170         size = LPAGE_SIZE;
1171         domain->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE;
1172 done:
1173         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1174
1175         exynos_iommu_tlb_invalidate_entry(domain, iova, size);
1176
1177         return size;
1178 err:
1179         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1180
1181         pr_err("%s: Failed: size(%#zx) @ %#x is smaller than page size %#zx\n",
1182                 __func__, size, iova, err_pgsize);
1183
1184         return 0;
1185 }
1186
1187 static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *iommu_domain,
1188                                           dma_addr_t iova)
1189 {
1190         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1191         sysmmu_pte_t *entry;
1192         unsigned long flags;
1193         phys_addr_t phys = 0;
1194
1195         spin_lock_irqsave(&domain->pgtablelock, flags);
1196
1197         entry = section_entry(domain->pgtable, iova);
1198
1199         if (lv1ent_section(entry)) {
1200                 phys = section_phys(entry) + section_offs(iova);
1201         } else if (lv1ent_page(entry)) {
1202                 entry = page_entry(entry, iova);
1203
1204                 if (lv2ent_large(entry))
1205                         phys = lpage_phys(entry) + lpage_offs(iova);
1206                 else if (lv2ent_small(entry))
1207                         phys = spage_phys(entry) + spage_offs(iova);
1208         }
1209
1210         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1211
1212         return phys;
1213 }
1214
1215 static struct iommu_group *get_device_iommu_group(struct device *dev)
1216 {
1217         struct iommu_group *group;
1218
1219         group = iommu_group_get(dev);
1220         if (!group)
1221                 group = iommu_group_alloc();
1222
1223         return group;
1224 }
1225
1226 static int exynos_iommu_add_device(struct device *dev)
1227 {
1228         struct iommu_group *group;
1229
1230         if (!has_sysmmu(dev))
1231                 return -ENODEV;
1232
1233         group = iommu_group_get_for_dev(dev);
1234
1235         if (IS_ERR(group))
1236                 return PTR_ERR(group);
1237
1238         iommu_group_put(group);
1239
1240         return 0;
1241 }
1242
1243 static void exynos_iommu_remove_device(struct device *dev)
1244 {
1245         if (!has_sysmmu(dev))
1246                 return;
1247
1248         iommu_group_remove_device(dev);
1249 }
1250
1251 static int exynos_iommu_of_xlate(struct device *dev,
1252                                  struct of_phandle_args *spec)
1253 {
1254         struct exynos_iommu_owner *owner = dev->archdata.iommu;
1255         struct platform_device *sysmmu = of_find_device_by_node(spec->np);
1256         struct sysmmu_drvdata *data;
1257
1258         if (!sysmmu)
1259                 return -ENODEV;
1260
1261         data = platform_get_drvdata(sysmmu);
1262         if (!data)
1263                 return -ENODEV;
1264
1265         if (!owner) {
1266                 owner = kzalloc(sizeof(*owner), GFP_KERNEL);
1267                 if (!owner)
1268                         return -ENOMEM;
1269
1270                 INIT_LIST_HEAD(&owner->controllers);
1271                 dev->archdata.iommu = owner;
1272         }
1273
1274         list_add_tail(&data->owner_node, &owner->controllers);
1275         return 0;
1276 }
1277
1278 static struct iommu_ops exynos_iommu_ops = {
1279         .domain_alloc = exynos_iommu_domain_alloc,
1280         .domain_free = exynos_iommu_domain_free,
1281         .attach_dev = exynos_iommu_attach_device,
1282         .detach_dev = exynos_iommu_detach_device,
1283         .map = exynos_iommu_map,
1284         .unmap = exynos_iommu_unmap,
1285         .map_sg = default_iommu_map_sg,
1286         .iova_to_phys = exynos_iommu_iova_to_phys,
1287         .device_group = get_device_iommu_group,
1288         .add_device = exynos_iommu_add_device,
1289         .remove_device = exynos_iommu_remove_device,
1290         .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE,
1291         .of_xlate = exynos_iommu_of_xlate,
1292 };
1293
1294 static bool init_done;
1295
1296 static int __init exynos_iommu_init(void)
1297 {
1298         int ret;
1299
1300         lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table",
1301                                 LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL);
1302         if (!lv2table_kmem_cache) {
1303                 pr_err("%s: Failed to create kmem cache\n", __func__);
1304                 return -ENOMEM;
1305         }
1306
1307         ret = platform_driver_register(&exynos_sysmmu_driver);
1308         if (ret) {
1309                 pr_err("%s: Failed to register driver\n", __func__);
1310                 goto err_reg_driver;
1311         }
1312
1313         zero_lv2_table = kmem_cache_zalloc(lv2table_kmem_cache, GFP_KERNEL);
1314         if (zero_lv2_table == NULL) {
1315                 pr_err("%s: Failed to allocate zero level2 page table\n",
1316                         __func__);
1317                 ret = -ENOMEM;
1318                 goto err_zero_lv2;
1319         }
1320
1321         ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops);
1322         if (ret) {
1323                 pr_err("%s: Failed to register exynos-iommu driver.\n",
1324                                                                 __func__);
1325                 goto err_set_iommu;
1326         }
1327
1328         init_done = true;
1329
1330         return 0;
1331 err_set_iommu:
1332         kmem_cache_free(lv2table_kmem_cache, zero_lv2_table);
1333 err_zero_lv2:
1334         platform_driver_unregister(&exynos_sysmmu_driver);
1335 err_reg_driver:
1336         kmem_cache_destroy(lv2table_kmem_cache);
1337         return ret;
1338 }
1339
1340 static int __init exynos_iommu_of_setup(struct device_node *np)
1341 {
1342         struct platform_device *pdev;
1343
1344         if (!init_done)
1345                 exynos_iommu_init();
1346
1347         pdev = of_platform_device_create(np, NULL, platform_bus_type.dev_root);
1348         if (IS_ERR(pdev))
1349                 return PTR_ERR(pdev);
1350
1351         /*
1352          * use the first registered sysmmu device for performing
1353          * dma mapping operations on iommu page tables (cpu cache flush)
1354          */
1355         if (!dma_dev)
1356                 dma_dev = &pdev->dev;
1357
1358         return 0;
1359 }
1360
1361 IOMMU_OF_DECLARE(exynos_iommu_of, "samsung,exynos-sysmmu",
1362                  exynos_iommu_of_setup);