drivers/memory/omap-gpmc.c

   1 /*
   2  * GPMC support functions
   3  *
   4  * Copyright (C) 2005-2006 Nokia Corporation
   5  *
   6  * Author: Juha Yrjola
   7  *
   8  * Copyright (C) 2009 Texas Instruments
   9  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15 #include <linux/irq.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/ioport.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/io.h>
  23 #include <linux/module.h>
  24 #include <linux/gpio/driver.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/irqdomain.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_device.h>
  31 #include <linux/of_platform.h>
  32 #include <linux/omap-gpmc.h>
  33 #include <linux/pm_runtime.h>
  34
  35 #include <linux/platform_data/mtd-nand-omap2.h>
  36 #include <linux/platform_data/mtd-onenand-omap2.h>
  37
  38 #include <asm/mach-types.h>
  39
  40 #define DEVICE_NAME             "omap-gpmc"
  41
  42 /* GPMC register offsets */
  43 #define GPMC_REVISION           0x00
  44 #define GPMC_SYSCONFIG          0x10
  45 #define GPMC_SYSSTATUS          0x14
  46 #define GPMC_IRQSTATUS          0x18
  47 #define GPMC_IRQENABLE          0x1c
  48 #define GPMC_TIMEOUT_CONTROL    0x40
  49 #define GPMC_ERR_ADDRESS        0x44
  50 #define GPMC_ERR_TYPE           0x48
  51 #define GPMC_CONFIG             0x50
  52 #define GPMC_STATUS             0x54
  53 #define GPMC_PREFETCH_CONFIG1   0x1e0
  54 #define GPMC_PREFETCH_CONFIG2   0x1e4
  55 #define GPMC_PREFETCH_CONTROL   0x1ec
  56 #define GPMC_PREFETCH_STATUS    0x1f0
  57 #define GPMC_ECC_CONFIG         0x1f4
  58 #define GPMC_ECC_CONTROL        0x1f8
  59 #define GPMC_ECC_SIZE_CONFIG    0x1fc
  60 #define GPMC_ECC1_RESULT        0x200
  61 #define GPMC_ECC_BCH_RESULT_0   0x240   /* not available on OMAP2 */
  62 #define GPMC_ECC_BCH_RESULT_1   0x244   /* not available on OMAP2 */
  63 #define GPMC_ECC_BCH_RESULT_2   0x248   /* not available on OMAP2 */
  64 #define GPMC_ECC_BCH_RESULT_3   0x24c   /* not available on OMAP2 */
  65 #define GPMC_ECC_BCH_RESULT_4   0x300   /* not available on OMAP2 */
  66 #define GPMC_ECC_BCH_RESULT_5   0x304   /* not available on OMAP2 */
  67 #define GPMC_ECC_BCH_RESULT_6   0x308   /* not available on OMAP2 */
  68
  69 /* GPMC ECC control settings */
  70 #define GPMC_ECC_CTRL_ECCCLEAR          0x100
  71 #define GPMC_ECC_CTRL_ECCDISABLE        0x000
  72 #define GPMC_ECC_CTRL_ECCREG1           0x001
  73 #define GPMC_ECC_CTRL_ECCREG2           0x002
  74 #define GPMC_ECC_CTRL_ECCREG3           0x003
  75 #define GPMC_ECC_CTRL_ECCREG4           0x004
  76 #define GPMC_ECC_CTRL_ECCREG5           0x005
  77 #define GPMC_ECC_CTRL_ECCREG6           0x006
  78 #define GPMC_ECC_CTRL_ECCREG7           0x007
  79 #define GPMC_ECC_CTRL_ECCREG8           0x008
  80 #define GPMC_ECC_CTRL_ECCREG9           0x009
  81
  82 #define GPMC_CONFIG_LIMITEDADDRESS              BIT(1)
  83
  84 #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS      BIT(0)
  85
  86 #define GPMC_CONFIG2_CSEXTRADELAY               BIT(7)
  87 #define GPMC_CONFIG3_ADVEXTRADELAY              BIT(7)
  88 #define GPMC_CONFIG4_OEEXTRADELAY               BIT(7)
  89 #define GPMC_CONFIG4_WEEXTRADELAY               BIT(23)
  90 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN        BIT(6)
  91 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN        BIT(7)
  92
  93 #define GPMC_CS0_OFFSET         0x60
  94 #define GPMC_CS_SIZE            0x30
  95 #define GPMC_BCH_SIZE           0x10
  96
  97 /*
  98  * The first 1MB of GPMC address space is typically mapped to
  99  * the internal ROM. Never allocate the first page, to
 100  * facilitate bug detection; even if we didn't boot from ROM.
 101  * As GPMC minimum partition size is 16MB we can only start from
 102  * there.
 103  */
 104 #define GPMC_MEM_START          0x1000000
 105 #define GPMC_MEM_END            0x3FFFFFFF
 106
 107 #define GPMC_CHUNK_SHIFT        24              /* 16 MB */
 108 #define GPMC_SECTION_SHIFT      28              /* 128 MB */
 109
 110 #define CS_NUM_SHIFT            24
 111 #define ENABLE_PREFETCH         (0x1 << 7)
 112 #define DMA_MPU_MODE            2
 113
 114 #define GPMC_REVISION_MAJOR(l)          ((l >> 4) & 0xf)
 115 #define GPMC_REVISION_MINOR(l)          (l & 0xf)
 116
 117 #define GPMC_HAS_WR_ACCESS              0x1
 118 #define GPMC_HAS_WR_DATA_MUX_BUS        0x2
 119 #define GPMC_HAS_MUX_AAD                0x4
 120
 121 #define GPMC_NR_WAITPINS                4
 122
 123 #define GPMC_CS_CONFIG1         0x00
 124 #define GPMC_CS_CONFIG2         0x04
 125 #define GPMC_CS_CONFIG3         0x08
 126 #define GPMC_CS_CONFIG4         0x0c
 127 #define GPMC_CS_CONFIG5         0x10
 128 #define GPMC_CS_CONFIG6         0x14
 129 #define GPMC_CS_CONFIG7         0x18
 130 #define GPMC_CS_NAND_COMMAND    0x1c
 131 #define GPMC_CS_NAND_ADDRESS    0x20
 132 #define GPMC_CS_NAND_DATA       0x24
 133
 134 /* Control Commands */
 135 #define GPMC_CONFIG_RDY_BSY     0x00000001
 136 #define GPMC_CONFIG_DEV_SIZE    0x00000002
 137 #define GPMC_CONFIG_DEV_TYPE    0x00000003
 138
 139 #define GPMC_CONFIG1_WRAPBURST_SUPP     (1 << 31)
 140 #define GPMC_CONFIG1_READMULTIPLE_SUPP  (1 << 30)
 141 #define GPMC_CONFIG1_READTYPE_ASYNC     (0 << 29)
 142 #define GPMC_CONFIG1_READTYPE_SYNC      (1 << 29)
 143 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
 144 #define GPMC_CONFIG1_WRITETYPE_ASYNC    (0 << 27)
 145 #define GPMC_CONFIG1_WRITETYPE_SYNC     (1 << 27)
 146 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
 147 /** CLKACTIVATIONTIME Max Ticks */
 148 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
 149 #define GPMC_CONFIG1_PAGE_LEN(val)      ((val & 3) << 23)
 150 /** ATTACHEDDEVICEPAGELENGTH Max Value */
 151 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
 152 #define GPMC_CONFIG1_WAIT_READ_MON      (1 << 22)
 153 #define GPMC_CONFIG1_WAIT_WRITE_MON     (1 << 21)
 154 #define GPMC_CONFIG1_WAIT_MON_TIME(val) ((val & 3) << 18)
 155 /** WAITMONITORINGTIME Max Ticks */
 156 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX  2
 157 #define GPMC_CONFIG1_WAIT_PIN_SEL(val)  ((val & 3) << 16)
 158 #define GPMC_CONFIG1_DEVICESIZE(val)    ((val & 3) << 12)
 159 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
 160 /** DEVICESIZE Max Value */
 161 #define GPMC_CONFIG1_DEVICESIZE_MAX     1
 162 #define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
 163 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
 164 #define GPMC_CONFIG1_MUXTYPE(val)       ((val & 3) << 8)
 165 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
 166 #define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
 167 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
 168 #define GPMC_CONFIG1_FCLK_DIV3          (GPMC_CONFIG1_FCLK_DIV(2))
 169 #define GPMC_CONFIG1_FCLK_DIV4          (GPMC_CONFIG1_FCLK_DIV(3))
 170 #define GPMC_CONFIG7_CSVALID            (1 << 6)
 171
 172 #define GPMC_CONFIG7_BASEADDRESS_MASK   0x3f
 173 #define GPMC_CONFIG7_CSVALID_MASK       BIT(6)
 174 #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
 175 #define GPMC_CONFIG7_MASKADDRESS_MASK   (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
 176 /* All CONFIG7 bits except reserved bits */
 177 #define GPMC_CONFIG7_MASK               (GPMC_CONFIG7_BASEADDRESS_MASK | \
 178                                          GPMC_CONFIG7_CSVALID_MASK |     \
 179                                          GPMC_CONFIG7_MASKADDRESS_MASK)
 180
 181 #define GPMC_DEVICETYPE_NOR             0
 182 #define GPMC_DEVICETYPE_NAND            2
 183 #define GPMC_CONFIG_WRITEPROTECT        0x00000010
 184 #define WR_RD_PIN_MONITORING            0x00600000
 185
 186 /* ECC commands */
 187 #define GPMC_ECC_READ           0 /* Reset Hardware ECC for read */
 188 #define GPMC_ECC_WRITE          1 /* Reset Hardware ECC for write */
 189 #define GPMC_ECC_READSYN        2 /* Reset before syndrom is read back */
 190
 191 #define GPMC_NR_NAND_IRQS       2 /* number of NAND specific IRQs */
 192
 193 enum gpmc_clk_domain {
 194         GPMC_CD_FCLK,
 195         GPMC_CD_CLK
 196 };
 197
 198 struct gpmc_cs_data {
 199         const char *name;
 200
 201 #define GPMC_CS_RESERVED        (1 << 0)
 202         u32 flags;
 203
 204         struct resource mem;
 205 };
 206
 207 /* Structure to save gpmc cs context */
 208 struct gpmc_cs_config {
 209         u32 config1;
 210         u32 config2;
 211         u32 config3;
 212         u32 config4;
 213         u32 config5;
 214         u32 config6;
 215         u32 config7;
 216         int is_valid;
 217 };
 218
 219 /*
 220  * Structure to save/restore gpmc context
 221  * to support core off on OMAP3
 222  */
 223 struct omap3_gpmc_regs {
 224         u32 sysconfig;
 225         u32 irqenable;
 226         u32 timeout_ctrl;
 227         u32 config;
 228         u32 prefetch_config1;
 229         u32 prefetch_config2;
 230         u32 prefetch_control;
 231         struct gpmc_cs_config cs_context[GPMC_CS_NUM];
 232 };
 233
 234 struct gpmc_device {
 235         struct device *dev;
 236         int irq;
 237         struct irq_chip irq_chip;
 238         struct gpio_chip gpio_chip;
 239         int nirqs;
 240 };
 241
 242 static struct irq_domain *gpmc_irq_domain;
 243
 244 static struct resource  gpmc_mem_root;
 245 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
 246 static DEFINE_SPINLOCK(gpmc_mem_lock);
 247 /* Define chip-selects as reserved by default until probe completes */
 248 static unsigned int gpmc_cs_num = GPMC_CS_NUM;
 249 static unsigned int gpmc_nr_waitpins;
 250 static resource_size_t phys_base, mem_size;
 251 static unsigned gpmc_capability;
 252 static void __iomem *gpmc_base;
 253
 254 static struct clk *gpmc_l3_clk;
 255
 256 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
 257
 258 static void gpmc_write_reg(int idx, u32 val)
 259 {
 260         writel_relaxed(val, gpmc_base + idx);
 261 }
 262
 263 static u32 gpmc_read_reg(int idx)
 264 {
 265         return readl_relaxed(gpmc_base + idx);
 266 }
 267
 268 void gpmc_cs_write_reg(int cs, int idx, u32 val)
 269 {
 270         void __iomem *reg_addr;
 271
 272         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 273         writel_relaxed(val, reg_addr);
 274 }
 275
 276 static u32 gpmc_cs_read_reg(int cs, int idx)
 277 {
 278         void __iomem *reg_addr;
 279
 280         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 281         return readl_relaxed(reg_addr);
 282 }
 283
 284 /* TODO: Add support for gpmc_fck to clock framework and use it */
 285 static unsigned long gpmc_get_fclk_period(void)
 286 {
 287         unsigned long rate = clk_get_rate(gpmc_l3_clk);
 288
 289         rate /= 1000;
 290         rate = 1000000000 / rate;       /* In picoseconds */
 291
 292         return rate;
 293 }
 294
 295 /**
 296  * gpmc_get_clk_period - get period of selected clock domain in ps
 297  * @cs Chip Select Region.
 298  * @cd Clock Domain.
 299  *
 300  * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
 301  * prior to calling this function with GPMC_CD_CLK.
 302  */
 303 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
 304 {
 305
 306         unsigned long tick_ps = gpmc_get_fclk_period();
 307         u32 l;
 308         int div;
 309
 310         switch (cd) {
 311         case GPMC_CD_CLK:
 312                 /* get current clk divider */
 313                 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 314                 div = (l & 0x03) + 1;
 315                 /* get GPMC_CLK period */
 316                 tick_ps *= div;
 317                 break;
 318         case GPMC_CD_FCLK:
 319                 /* FALL-THROUGH */
 320         default:
 321                 break;
 322         }
 323
 324         return tick_ps;
 325
 326 }
 327
 328 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
 329                                          enum gpmc_clk_domain cd)
 330 {
 331         unsigned long tick_ps;
 332
 333         /* Calculate in picosecs to yield more exact results */
 334         tick_ps = gpmc_get_clk_period(cs, cd);
 335
 336         return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 337 }
 338
 339 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
 340 {
 341         return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
 342 }
 343
 344 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
 345 {
 346         unsigned long tick_ps;
 347
 348         /* Calculate in picosecs to yield more exact results */
 349         tick_ps = gpmc_get_fclk_period();
 350
 351         return (time_ps + tick_ps - 1) / tick_ps;
 352 }
 353
 354 unsigned int gpmc_clk_ticks_to_ns(unsigned ticks, int cs,
 355                                   enum gpmc_clk_domain cd)
 356 {
 357         return ticks * gpmc_get_clk_period(cs, cd) / 1000;
 358 }
 359
 360 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
 361 {
 362         return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
 363 }
 364
 365 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
 366 {
 367         return ticks * gpmc_get_fclk_period();
 368 }
 369
 370 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
 371 {
 372         unsigned long ticks = gpmc_ps_to_ticks(time_ps);
 373
 374         return ticks * gpmc_get_fclk_period();
 375 }
 376
 377 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
 378 {
 379         u32 l;
 380
 381         l = gpmc_cs_read_reg(cs, reg);
 382         if (value)
 383                 l |= mask;
 384         else
 385                 l &= ~mask;
 386         gpmc_cs_write_reg(cs, reg, l);
 387 }
 388
 389 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
 390 {
 391         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
 392                            GPMC_CONFIG1_TIME_PARA_GRAN,
 393                            p->time_para_granularity);
 394         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
 395                            GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
 396         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
 397                            GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
 398         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 399                            GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
 400         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 401                            GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay);
 402         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 403                            GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
 404                            p->cycle2cyclesamecsen);
 405         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 406                            GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
 407                            p->cycle2cyclediffcsen);
 408 }
 409
 410 #ifdef CONFIG_OMAP_GPMC_DEBUG
 411 /**
 412  * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
 413  * @cs:      Chip Select Region
 414  * @reg:     GPMC_CS_CONFIGn register offset.
 415  * @st_bit:  Start Bit
 416  * @end_bit: End Bit. Must be >= @st_bit.
 417  * @ma:x     Maximum parameter value (before optional @shift).
 418  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 419  * @name:    DTS node name, w/o "gpmc,"
 420  * @cd:      Clock Domain of timing parameter.
 421  * @shift:   Parameter value left shifts @shift, which is then printed instead of value.
 422  * @raw:     Raw Format Option.
 423  *           raw format:  gpmc,name = <value>
 424  *           tick format: gpmc,name = <value> /&zwj;* x ns -- y ns; x ticks *&zwj;/
 425  *           Where x ns -- y ns result in the same tick value.
 426  *           When @max is exceeded, "invalid" is printed inside comment.
 427  * @noval:   Parameter values equal to 0 are not printed.
 428  * @return:  Specified timing parameter (after optional @shift).
 429  *
 430  */
 431 static int get_gpmc_timing_reg(
 432         /* timing specifiers */
 433         int cs, int reg, int st_bit, int end_bit, int max,
 434         const char *name, const enum gpmc_clk_domain cd,
 435         /* value transform */
 436         int shift,
 437         /* format specifiers */
 438         bool raw, bool noval)
 439 {
 440         u32 l;
 441         int nr_bits;
 442         int mask;
 443         bool invalid;
 444
 445         l = gpmc_cs_read_reg(cs, reg);
 446         nr_bits = end_bit - st_bit + 1;
 447         mask = (1 << nr_bits) - 1;
 448         l = (l >> st_bit) & mask;
 449         if (!max)
 450                 max = mask;
 451         invalid = l > max;
 452         if (shift)
 453                 l = (shift << l);
 454         if (noval && (l == 0))
 455                 return 0;
 456         if (!raw) {
 457                 /* DTS tick format for timings in ns */
 458                 unsigned int time_ns;
 459                 unsigned int time_ns_min = 0;
 460
 461                 if (l)
 462                         time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
 463                 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
 464                 pr_info("gpmc,%s = <%u> /* %u ns - %u ns; %i ticks%s*/\n",
 465                         name, time_ns, time_ns_min, time_ns, l,
 466                         invalid ? "; invalid " : " ");
 467         } else {
 468                 /* raw format */
 469                 pr_info("gpmc,%s = <%u>%s\n", name, l,
 470                         invalid ? " /* invalid */" : "");
 471         }
 472
 473         return l;
 474 }
 475
 476 #define GPMC_PRINT_CONFIG(cs, config) \
 477         pr_info("cs%i %s: 0x%08x\n", cs, #config, \
 478                 gpmc_cs_read_reg(cs, config))
 479 #define GPMC_GET_RAW(reg, st, end, field) \
 480         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
 481 #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
 482         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
 483 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
 484         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
 485 #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
 486         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
 487 #define GPMC_GET_TICKS(reg, st, end, field) \
 488         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
 489 #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
 490         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
 491 #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
 492         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
 493
 494 static void gpmc_show_regs(int cs, const char *desc)
 495 {
 496         pr_info("gpmc cs%i %s:\n", cs, desc);
 497         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
 498         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
 499         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
 500         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
 501         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
 502         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
 503 }
 504
 505 /*
 506  * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
 507  * see commit c9fb809.
 508  */
 509 static void gpmc_cs_show_timings(int cs, const char *desc)
 510 {
 511         gpmc_show_regs(cs, desc);
 512
 513         pr_info("gpmc cs%i access configuration:\n", cs);
 514         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1,  4,  4, "time-para-granularity");
 515         GPMC_GET_RAW(GPMC_CS_CONFIG1,  8,  9, "mux-add-data");
 516         GPMC_GET_RAW_MAX(GPMC_CS_CONFIG1, 12, 13,
 517                          GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
 518         GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
 519         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
 520         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
 521         GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
 522                                GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
 523                                "burst-length");
 524         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
 525         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
 526         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
 527         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
 528         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
 529
 530         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2,  7,  7, "cs-extra-delay");
 531
 532         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3,  7,  7, "adv-extra-delay");
 533
 534         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
 535         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4,  7,  7, "oe-extra-delay");
 536
 537         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  7,  7, "cycle2cycle-samecsen");
 538         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  6,  6, "cycle2cycle-diffcsen");
 539
 540         pr_info("gpmc cs%i timings configuration:\n", cs);
 541         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  0,  3, "cs-on-ns");
 542         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  8, 12, "cs-rd-off-ns");
 543         GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
 544
 545         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  0,  3, "adv-on-ns");
 546         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  8, 12, "adv-rd-off-ns");
 547         GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
 548         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 549                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
 550                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
 551                                 "adv-aad-mux-rd-off-ns");
 552                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
 553                                 "adv-aad-mux-wr-off-ns");
 554         }
 555
 556         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  0,  3, "oe-on-ns");
 557         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  8, 12, "oe-off-ns");
 558         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 559                 GPMC_GET_TICKS(GPMC_CS_CONFIG4,  4,  6, "oe-aad-mux-on-ns");
 560                 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
 561         }
 562         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
 563         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
 564
 565         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  0,  4, "rd-cycle-ns");
 566         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  8, 12, "wr-cycle-ns");
 567         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
 568
 569         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
 570
 571         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
 572         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
 573
 574         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
 575                               GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 576                               "wait-monitoring-ns", GPMC_CD_CLK);
 577         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
 578                               GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 579                               "clk-activation-ns", GPMC_CD_FCLK);
 580
 581         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
 582         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
 583 }
 584 #else
 585 static inline void gpmc_cs_show_timings(int cs, const char *desc)
 586 {
 587 }
 588 #endif
 589
 590 /**
 591  * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
 592  * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
 593  * prior to calling this function with @cd equal to GPMC_CD_CLK.
 594  *
 595  * @cs:      Chip Select Region.
 596  * @reg:     GPMC_CS_CONFIGn register offset.
 597  * @st_bit:  Start Bit
 598  * @end_bit: End Bit. Must be >= @st_bit.
 599  * @max:     Maximum parameter value.
 600  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 601  * @time:    Timing parameter in ns.
 602  * @cd:      Timing parameter clock domain.
 603  * @name:    Timing parameter name.
 604  * @return:  0 on success, -1 on error.
 605  */
 606 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
 607                                int time, enum gpmc_clk_domain cd, const char *name)
 608 {
 609         u32 l;
 610         int ticks, mask, nr_bits;
 611
 612         if (time == 0)
 613                 ticks = 0;
 614         else
 615                 ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
 616         nr_bits = end_bit - st_bit + 1;
 617         mask = (1 << nr_bits) - 1;
 618
 619         if (!max)
 620                 max = mask;
 621
 622         if (ticks > max) {
 623                 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
 624                        __func__, cs, name, time, ticks, max);
 625
 626                 return -1;
 627         }
 628
 629         l = gpmc_cs_read_reg(cs, reg);
 630 #ifdef CONFIG_OMAP_GPMC_DEBUG
 631         pr_info(
 632                 "GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
 633                cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
 634                         (l >> st_bit) & mask, time);
 635 #endif
 636         l &= ~(mask << st_bit);
 637         l |= ticks << st_bit;
 638         gpmc_cs_write_reg(cs, reg, l);
 639
 640         return 0;
 641 }
 642
 643 #define GPMC_SET_ONE_CD_MAX(reg, st, end, max, field, cd)  \
 644         if (set_gpmc_timing_reg(cs, (reg), (st), (end), (max), \
 645             t->field, (cd), #field) < 0)                       \
 646                 return -1
 647
 648 #define GPMC_SET_ONE(reg, st, end, field) \
 649         GPMC_SET_ONE_CD_MAX(reg, st, end, 0, field, GPMC_CD_FCLK)
 650
 651 /**
 652  * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
 653  * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
 654  * read  --> don't sample bus too early
 655  * write --> data is longer on bus
 656  *
 657  * Formula:
 658  * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
 659  *                    / waitmonitoring_ticks)
 660  * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
 661  * div <= 0 check.
 662  *
 663  * @wait_monitoring: WAITMONITORINGTIME in ns.
 664  * @return:          -1 on failure to scale, else proper divider > 0.
 665  */
 666 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
 667 {
 668
 669         int div = gpmc_ns_to_ticks(wait_monitoring);
 670
 671         div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
 672         div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
 673
 674         if (div > 4)
 675                 return -1;
 676         if (div <= 0)
 677                 div = 1;
 678
 679         return div;
 680
 681 }
 682
 683 /**
 684  * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
 685  * @sync_clk: GPMC_CLK period in ps.
 686  * @return:   Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
 687  *            Else, returns -1.
 688  */
 689 int gpmc_calc_divider(unsigned int sync_clk)
 690 {
 691         int div = gpmc_ps_to_ticks(sync_clk);
 692
 693         if (div > 4)
 694                 return -1;
 695         if (div <= 0)
 696                 div = 1;
 697
 698         return div;
 699 }
 700
 701 /**
 702  * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
 703  * @cs:     Chip Select Region.
 704  * @t:      GPMC timing parameters.
 705  * @s:      GPMC timing settings.
 706  * @return: 0 on success, -1 on error.
 707  */
 708 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
 709                         const struct gpmc_settings *s)
 710 {
 711         int div;
 712         u32 l;
 713
 714         div = gpmc_calc_divider(t->sync_clk);
 715         if (div < 0)
 716                 return div;
 717
 718         /*
 719          * See if we need to change the divider for waitmonitoringtime.
 720          *
 721          * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
 722          * pure asynchronous accesses, i.e. both read and write asynchronous.
 723          * However, only do so if WAITMONITORINGTIME is actually used, i.e.
 724          * either WAITREADMONITORING or WAITWRITEMONITORING is set.
 725          *
 726          * This statement must not change div to scale async WAITMONITORINGTIME
 727          * to protect mixed synchronous and asynchronous accesses.
 728          *
 729          * We raise an error later if WAITMONITORINGTIME does not fit.
 730          */
 731         if (!s->sync_read && !s->sync_write &&
 732             (s->wait_on_read || s->wait_on_write)
 733            ) {
 734
 735                 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
 736                 if (div < 0) {
 737                         pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
 738                                __func__,
 739                                t->wait_monitoring
 740                                );
 741                         return -1;
 742                 }
 743         }
 744
 745         GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
 746         GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
 747         GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
 748
 749         GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
 750         GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
 751         GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
 752         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 753                 GPMC_SET_ONE(GPMC_CS_CONFIG3,  4,  6, adv_aad_mux_on);
 754                 GPMC_SET_ONE(GPMC_CS_CONFIG3, 24, 26, adv_aad_mux_rd_off);
 755                 GPMC_SET_ONE(GPMC_CS_CONFIG3, 28, 30, adv_aad_mux_wr_off);
 756         }
 757
 758         GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
 759         GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
 760         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 761                 GPMC_SET_ONE(GPMC_CS_CONFIG4,  4,  6, oe_aad_mux_on);
 762                 GPMC_SET_ONE(GPMC_CS_CONFIG4, 13, 15, oe_aad_mux_off);
 763         }
 764         GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
 765         GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
 766
 767         GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
 768         GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
 769         GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
 770
 771         GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
 772
 773         GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
 774         GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
 775
 776         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
 777                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
 778         if (gpmc_capability & GPMC_HAS_WR_ACCESS)
 779                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
 780
 781         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 782         l &= ~0x03;
 783         l |= (div - 1);
 784         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
 785
 786         GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
 787                             GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 788                             wait_monitoring, GPMC_CD_CLK);
 789         GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
 790                             GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 791                             clk_activation, GPMC_CD_FCLK);
 792
 793 #ifdef CONFIG_OMAP_GPMC_DEBUG
 794         pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
 795                         cs, (div * gpmc_get_fclk_period()) / 1000, div);
 796 #endif
 797
 798         gpmc_cs_bool_timings(cs, &t->bool_timings);
 799         gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
 800
 801         return 0;
 802 }
 803
 804 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
 805 {
 806         u32 l;
 807         u32 mask;
 808
 809         /*
 810          * Ensure that base address is aligned on a
 811          * boundary equal to or greater than size.
 812          */
 813         if (base & (size - 1))
 814                 return -EINVAL;
 815
 816         base >>= GPMC_CHUNK_SHIFT;
 817         mask = (1 << GPMC_SECTION_SHIFT) - size;
 818         mask >>= GPMC_CHUNK_SHIFT;
 819         mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
 820
 821         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 822         l &= ~GPMC_CONFIG7_MASK;
 823         l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
 824         l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
 825         l |= GPMC_CONFIG7_CSVALID;
 826         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 827
 828         return 0;
 829 }
 830
 831 static void gpmc_cs_enable_mem(int cs)
 832 {
 833         u32 l;
 834
 835         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 836         l |= GPMC_CONFIG7_CSVALID;
 837         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 838 }
 839
 840 static void gpmc_cs_disable_mem(int cs)
 841 {
 842         u32 l;
 843
 844         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 845         l &= ~GPMC_CONFIG7_CSVALID;
 846         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 847 }
 848
 849 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
 850 {
 851         u32 l;
 852         u32 mask;
 853
 854         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 855         *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
 856         mask = (l >> 8) & 0x0f;
 857         *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
 858 }
 859
 860 static int gpmc_cs_mem_enabled(int cs)
 861 {
 862         u32 l;
 863
 864         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 865         return l & GPMC_CONFIG7_CSVALID;
 866 }
 867
 868 static void gpmc_cs_set_reserved(int cs, int reserved)
 869 {
 870         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 871
 872         gpmc->flags |= GPMC_CS_RESERVED;
 873 }
 874
 875 static bool gpmc_cs_reserved(int cs)
 876 {
 877         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 878
 879         return gpmc->flags & GPMC_CS_RESERVED;
 880 }
 881
 882 static void gpmc_cs_set_name(int cs, const char *name)
 883 {
 884         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 885
 886         gpmc->name = name;
 887 }
 888
 889 static const char *gpmc_cs_get_name(int cs)
 890 {
 891         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 892
 893         return gpmc->name;
 894 }
 895
 896 static unsigned long gpmc_mem_align(unsigned long size)
 897 {
 898         int order;
 899
 900         size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
 901         order = GPMC_CHUNK_SHIFT - 1;
 902         do {
 903                 size >>= 1;
 904                 order++;
 905         } while (size);
 906         size = 1 << order;
 907         return size;
 908 }
 909
 910 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
 911 {
 912         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 913         struct resource *res = &gpmc->mem;
 914         int r;
 915
 916         size = gpmc_mem_align(size);
 917         spin_lock(&gpmc_mem_lock);
 918         res->start = base;
 919         res->end = base + size - 1;
 920         r = request_resource(&gpmc_mem_root, res);
 921         spin_unlock(&gpmc_mem_lock);
 922
 923         return r;
 924 }
 925
 926 static int gpmc_cs_delete_mem(int cs)
 927 {
 928         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 929         struct resource *res = &gpmc->mem;
 930         int r;
 931
 932         spin_lock(&gpmc_mem_lock);
 933         r = release_resource(res);
 934         res->start = 0;
 935         res->end = 0;
 936         spin_unlock(&gpmc_mem_lock);
 937
 938         return r;
 939 }
 940
 941 /**
 942  * gpmc_cs_remap - remaps a chip-select physical base address
 943  * @cs:         chip-select to remap
 944  * @base:       physical base address to re-map chip-select to
 945  *
 946  * Re-maps a chip-select to a new physical base address specified by
 947  * "base". Returns 0 on success and appropriate negative error code
 948  * on failure.
 949  */
 950 static int gpmc_cs_remap(int cs, u32 base)
 951 {
 952         int ret;
 953         u32 old_base, size;
 954
 955         if (cs > gpmc_cs_num) {
 956                 pr_err("%s: requested chip-select is disabled\n", __func__);
 957                 return -ENODEV;
 958         }
 959
 960         /*
 961          * Make sure we ignore any device offsets from the GPMC partition
 962          * allocated for the chip select and that the new base confirms
 963          * to the GPMC 16MB minimum granularity.
 964          */
 965         base &= ~(SZ_16M - 1);
 966
 967         gpmc_cs_get_memconf(cs, &old_base, &size);
 968         if (base == old_base)
 969                 return 0;
 970
 971         ret = gpmc_cs_delete_mem(cs);
 972         if (ret < 0)
 973                 return ret;
 974
 975         ret = gpmc_cs_insert_mem(cs, base, size);
 976         if (ret < 0)
 977                 return ret;
 978
 979         ret = gpmc_cs_set_memconf(cs, base, size);
 980
 981         return ret;
 982 }
 983
 984 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 985 {
 986         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 987         struct resource *res = &gpmc->mem;
 988         int r = -1;
 989
 990         if (cs > gpmc_cs_num) {
 991                 pr_err("%s: requested chip-select is disabled\n", __func__);
 992                 return -ENODEV;
 993         }
 994         size = gpmc_mem_align(size);
 995         if (size > (1 << GPMC_SECTION_SHIFT))
 996                 return -ENOMEM;
 997
 998         spin_lock(&gpmc_mem_lock);
 999         if (gpmc_cs_reserved(cs)) {
1000                 r = -EBUSY;
1001                 goto out;
1002         }
1003         if (gpmc_cs_mem_enabled(cs))
1004                 r = adjust_resource(res, res->start & ~(size - 1), size);
1005         if (r < 0)
1006                 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
1007                                       size, NULL, NULL);
1008         if (r < 0)
1009                 goto out;
1010
1011         /* Disable CS while changing base address and size mask */
1012         gpmc_cs_disable_mem(cs);
1013
1014         r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
1015         if (r < 0) {
1016                 release_resource(res);
1017                 goto out;
1018         }
1019
1020         /* Enable CS */
1021         gpmc_cs_enable_mem(cs);
1022         *base = res->start;
1023         gpmc_cs_set_reserved(cs, 1);
1024 out:
1025         spin_unlock(&gpmc_mem_lock);
1026         return r;
1027 }
1028 EXPORT_SYMBOL(gpmc_cs_request);
1029
1030 void gpmc_cs_free(int cs)
1031 {
1032         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1033         struct resource *res = &gpmc->mem;
1034
1035         spin_lock(&gpmc_mem_lock);
1036         if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
1037                 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
1038                 BUG();
1039                 spin_unlock(&gpmc_mem_lock);
1040                 return;
1041         }
1042         gpmc_cs_disable_mem(cs);
1043         if (res->flags)
1044                 release_resource(res);
1045         gpmc_cs_set_reserved(cs, 0);
1046         spin_unlock(&gpmc_mem_lock);
1047 }
1048 EXPORT_SYMBOL(gpmc_cs_free);
1049
1050 /**
1051  * gpmc_configure - write request to configure gpmc
1052  * @cmd: command type
1053  * @wval: value to write
1054  * @return status of the operation
1055  */
1056 int gpmc_configure(int cmd, int wval)
1057 {
1058         u32 regval;
1059
1060         switch (cmd) {
1061         case GPMC_CONFIG_WP:
1062                 regval = gpmc_read_reg(GPMC_CONFIG);
1063                 if (wval)
1064                         regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
1065                 else
1066                         regval |= GPMC_CONFIG_WRITEPROTECT;  /* WP is OFF */
1067                 gpmc_write_reg(GPMC_CONFIG, regval);
1068                 break;
1069
1070         default:
1071                 pr_err("%s: command not supported\n", __func__);
1072                 return -EINVAL;
1073         }
1074
1075         return 0;
1076 }
1077 EXPORT_SYMBOL(gpmc_configure);
1078
1079 void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
1080 {
1081         int i;
1082
1083         reg->gpmc_status = NULL;        /* deprecated */
1084         reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
1085                                 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
1086         reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
1087                                 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
1088         reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
1089                                 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
1090         reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
1091         reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
1092         reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
1093         reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
1094         reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
1095         reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
1096         reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
1097         reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
1098
1099         for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
1100                 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
1101                                            GPMC_BCH_SIZE * i;
1102                 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
1103                                            GPMC_BCH_SIZE * i;
1104                 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
1105                                            GPMC_BCH_SIZE * i;
1106                 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
1107                                            GPMC_BCH_SIZE * i;
1108                 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
1109                                            i * GPMC_BCH_SIZE;
1110                 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
1111                                            i * GPMC_BCH_SIZE;
1112                 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
1113                                            i * GPMC_BCH_SIZE;
1114         }
1115 }
1116
1117 static bool gpmc_nand_writebuffer_empty(void)
1118 {
1119         if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS)
1120                 return true;
1121
1122         return false;
1123 }
1124
1125 static struct gpmc_nand_ops nand_ops = {
1126         .nand_writebuffer_empty = gpmc_nand_writebuffer_empty,
1127 };
1128
1129 /**
1130  * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
1131  * @regs: the GPMC NAND register map exclusive for NAND use.
1132  * @cs: GPMC chip select number on which the NAND sits. The
1133  *      register map returned will be specific to this chip select.
1134  *
1135  * Returns NULL on error e.g. invalid cs.
1136  */
1137 struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)
1138 {
1139         if (cs >= gpmc_cs_num)
1140                 return NULL;
1141
1142         gpmc_update_nand_reg(reg, cs);
1143
1144         return &nand_ops;
1145 }
1146 EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
1147
1148 int gpmc_get_client_irq(unsigned irq_config)
1149 {
1150         if (!gpmc_irq_domain) {
1151                 pr_warn("%s called before GPMC IRQ domain available\n",
1152                         __func__);
1153                 return 0;
1154         }
1155
1156         /* we restrict this to NAND IRQs only */
1157         if (irq_config >= GPMC_NR_NAND_IRQS)
1158                 return 0;
1159
1160         return irq_create_mapping(gpmc_irq_domain, irq_config);
1161 }
1162
1163 static int gpmc_irq_endis(unsigned long hwirq, bool endis)
1164 {
1165         u32 regval;
1166
1167         /* bits GPMC_NR_NAND_IRQS to 8 are reserved */
1168         if (hwirq >= GPMC_NR_NAND_IRQS)
1169                 hwirq += 8 - GPMC_NR_NAND_IRQS;
1170
1171         regval = gpmc_read_reg(GPMC_IRQENABLE);
1172         if (endis)
1173                 regval |= BIT(hwirq);
1174         else
1175                 regval &= ~BIT(hwirq);
1176         gpmc_write_reg(GPMC_IRQENABLE, regval);
1177
1178         return 0;
1179 }
1180
1181 static void gpmc_irq_disable(struct irq_data *p)
1182 {
1183         gpmc_irq_endis(p->hwirq, false);
1184 }
1185
1186 static void gpmc_irq_enable(struct irq_data *p)
1187 {
1188         gpmc_irq_endis(p->hwirq, true);
1189 }
1190
1191 static void gpmc_irq_mask(struct irq_data *d)
1192 {
1193         gpmc_irq_endis(d->hwirq, false);
1194 }
1195
1196 static void gpmc_irq_unmask(struct irq_data *d)
1197 {
1198         gpmc_irq_endis(d->hwirq, true);
1199 }
1200
1201 static void gpmc_irq_edge_config(unsigned long hwirq, bool rising_edge)
1202 {
1203         u32 regval;
1204
1205         /* NAND IRQs polarity is not configurable */
1206         if (hwirq < GPMC_NR_NAND_IRQS)
1207                 return;
1208
1209         /* WAITPIN starts at BIT 8 */
1210         hwirq += 8 - GPMC_NR_NAND_IRQS;
1211
1212         regval = gpmc_read_reg(GPMC_CONFIG);
1213         if (rising_edge)
1214                 regval &= ~BIT(hwirq);
1215         else
1216                 regval |= BIT(hwirq);
1217
1218         gpmc_write_reg(GPMC_CONFIG, regval);
1219 }
1220
1221 static void gpmc_irq_ack(struct irq_data *d)
1222 {
1223         unsigned int hwirq = d->hwirq;
1224
1225         /* skip reserved bits */
1226         if (hwirq >= GPMC_NR_NAND_IRQS)
1227                 hwirq += 8 - GPMC_NR_NAND_IRQS;
1228
1229         /* Setting bit to 1 clears (or Acks) the interrupt */
1230         gpmc_write_reg(GPMC_IRQSTATUS, BIT(hwirq));
1231 }
1232
1233 static int gpmc_irq_set_type(struct irq_data *d, unsigned int trigger)
1234 {
1235         /* can't set type for NAND IRQs */
1236         if (d->hwirq < GPMC_NR_NAND_IRQS)
1237                 return -EINVAL;
1238
1239         /* We can support either rising or falling edge at a time */
1240         if (trigger == IRQ_TYPE_EDGE_FALLING)
1241                 gpmc_irq_edge_config(d->hwirq, false);
1242         else if (trigger == IRQ_TYPE_EDGE_RISING)
1243                 gpmc_irq_edge_config(d->hwirq, true);
1244         else
1245                 return -EINVAL;
1246
1247         return 0;
1248 }
1249
1250 static int gpmc_irq_map(struct irq_domain *d, unsigned int virq,
1251                         irq_hw_number_t hw)
1252 {
1253         struct gpmc_device *gpmc = d->host_data;
1254
1255         irq_set_chip_data(virq, gpmc);
1256         if (hw < GPMC_NR_NAND_IRQS) {
1257                 irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN);
1258                 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1259                                          handle_simple_irq);
1260         } else {
1261                 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1262                                          handle_edge_irq);
1263         }
1264
1265         return 0;
1266 }
1267
1268 static const struct irq_domain_ops gpmc_irq_domain_ops = {
1269         .map    = gpmc_irq_map,
1270         .xlate  = irq_domain_xlate_twocell,
1271 };
1272
1273 static irqreturn_t gpmc_handle_irq(int irq, void *data)
1274 {
1275         int hwirq, virq;
1276         u32 regval, regvalx;
1277         struct gpmc_device *gpmc = data;
1278
1279         regval = gpmc_read_reg(GPMC_IRQSTATUS);
1280         regvalx = regval;
1281
1282         if (!regval)
1283                 return IRQ_NONE;
1284
1285         for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) {
1286                 /* skip reserved status bits */
1287                 if (hwirq == GPMC_NR_NAND_IRQS)
1288                         regvalx >>= 8 - GPMC_NR_NAND_IRQS;
1289
1290                 if (regvalx & BIT(hwirq)) {
1291                         virq = irq_find_mapping(gpmc_irq_domain, hwirq);
1292                         if (!virq) {
1293                                 dev_warn(gpmc->dev,
1294                                          "spurious irq detected hwirq %d, virq %d\n",
1295                                          hwirq, virq);
1296                         }
1297
1298                         generic_handle_irq(virq);
1299                 }
1300         }
1301
1302         gpmc_write_reg(GPMC_IRQSTATUS, regval);
1303
1304         return IRQ_HANDLED;
1305 }
1306
1307 static int gpmc_setup_irq(struct gpmc_device *gpmc)
1308 {
1309         u32 regval;
1310         int rc;
1311
1312         /* Disable interrupts */
1313         gpmc_write_reg(GPMC_IRQENABLE, 0);
1314
1315         /* clear interrupts */
1316         regval = gpmc_read_reg(GPMC_IRQSTATUS);
1317         gpmc_write_reg(GPMC_IRQSTATUS, regval);
1318
1319         gpmc->irq_chip.name = "gpmc";
1320         gpmc->irq_chip.irq_enable = gpmc_irq_enable;
1321         gpmc->irq_chip.irq_disable = gpmc_irq_disable;
1322         gpmc->irq_chip.irq_ack = gpmc_irq_ack;
1323         gpmc->irq_chip.irq_mask = gpmc_irq_mask;
1324         gpmc->irq_chip.irq_unmask = gpmc_irq_unmask;
1325         gpmc->irq_chip.irq_set_type = gpmc_irq_set_type;
1326
1327         gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node,
1328                                                 gpmc->nirqs,
1329                                                 &gpmc_irq_domain_ops,
1330                                                 gpmc);
1331         if (!gpmc_irq_domain) {
1332                 dev_err(gpmc->dev, "IRQ domain add failed\n");
1333                 return -ENODEV;
1334         }
1335
1336         rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc);
1337         if (rc) {
1338                 dev_err(gpmc->dev, "failed to request irq %d: %d\n",
1339                         gpmc->irq, rc);
1340                 irq_domain_remove(gpmc_irq_domain);
1341                 gpmc_irq_domain = NULL;
1342         }
1343
1344         return rc;
1345 }
1346
1347 static int gpmc_free_irq(struct gpmc_device *gpmc)
1348 {
1349         int hwirq;
1350
1351         free_irq(gpmc->irq, gpmc);
1352
1353         for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++)
1354                 irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq));
1355
1356         irq_domain_remove(gpmc_irq_domain);
1357         gpmc_irq_domain = NULL;
1358
1359         return 0;
1360 }
1361
1362 static void gpmc_mem_exit(void)
1363 {
1364         int cs;
1365
1366         for (cs = 0; cs < gpmc_cs_num; cs++) {
1367                 if (!gpmc_cs_mem_enabled(cs))
1368                         continue;
1369                 gpmc_cs_delete_mem(cs);
1370         }
1371
1372 }
1373
1374 static void gpmc_mem_init(void)
1375 {
1376         int cs;
1377
1378         gpmc_mem_root.start = GPMC_MEM_START;
1379         gpmc_mem_root.end = GPMC_MEM_END;
1380
1381         /* Reserve all regions that has been set up by bootloader */
1382         for (cs = 0; cs < gpmc_cs_num; cs++) {
1383                 u32 base, size;
1384
1385                 if (!gpmc_cs_mem_enabled(cs))
1386                         continue;
1387                 gpmc_cs_get_memconf(cs, &base, &size);
1388                 if (gpmc_cs_insert_mem(cs, base, size)) {
1389                         pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1390                                 __func__, cs, base, base + size);
1391                         gpmc_cs_disable_mem(cs);
1392                 }
1393         }
1394 }
1395
1396 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
1397 {
1398         u32 temp;
1399         int div;
1400
1401         div = gpmc_calc_divider(sync_clk);
1402         temp = gpmc_ps_to_ticks(time_ps);
1403         temp = (temp + div - 1) / div;
1404         return gpmc_ticks_to_ps(temp * div);
1405 }
1406
1407 /* XXX: can the cycles be avoided ? */
1408 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
1409                                        struct gpmc_device_timings *dev_t,
1410                                        bool mux)
1411 {
1412         u32 temp;
1413
1414         /* adv_rd_off */
1415         temp = dev_t->t_avdp_r;
1416         /* XXX: mux check required ? */
1417         if (mux) {
1418                 /* XXX: t_avdp not to be required for sync, only added for tusb
1419                  * this indirectly necessitates requirement of t_avdp_r and
1420                  * t_avdp_w instead of having a single t_avdp
1421                  */
1422                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
1423                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1424         }
1425         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1426
1427         /* oe_on */
1428         temp = dev_t->t_oeasu; /* XXX: remove this ? */
1429         if (mux) {
1430                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
1431                 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1432                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1433         }
1434         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1435
1436         /* access */
1437         /* XXX: any scope for improvement ?, by combining oe_on
1438          * and clk_activation, need to check whether
1439          * access = clk_activation + round to sync clk ?
1440          */
1441         temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
1442         temp += gpmc_t->clk_activation;
1443         if (dev_t->cyc_oe)
1444                 temp = max_t(u32, temp, gpmc_t->oe_on +
1445                                 gpmc_ticks_to_ps(dev_t->cyc_oe));
1446         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1447
1448         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1449         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1450
1451         /* rd_cycle */
1452         temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1453         temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1454                                                         gpmc_t->access;
1455         /* XXX: barter t_ce_rdyz with t_cez_r ? */
1456         if (dev_t->t_ce_rdyz)
1457                 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1458         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1459
1460         return 0;
1461 }
1462
1463 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
1464                                         struct gpmc_device_timings *dev_t,
1465                                         bool mux)
1466 {
1467         u32 temp;
1468
1469         /* adv_wr_off */
1470         temp = dev_t->t_avdp_w;
1471         if (mux) {
1472                 temp = max_t(u32, temp,
1473                         gpmc_t->clk_activation + dev_t->t_avdh);
1474                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1475         }
1476         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1477
1478         /* wr_data_mux_bus */
1479         temp = max_t(u32, dev_t->t_weasu,
1480                         gpmc_t->clk_activation + dev_t->t_rdyo);
1481         /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1482          * and in that case remember to handle we_on properly
1483          */
1484         if (mux) {
1485                 temp = max_t(u32, temp,
1486                         gpmc_t->adv_wr_off + dev_t->t_aavdh);
1487                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1488                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1489         }
1490         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1491
1492         /* we_on */
1493         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1494                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1495         else
1496                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1497
1498         /* wr_access */
1499         /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1500         gpmc_t->wr_access = gpmc_t->access;
1501
1502         /* we_off */
1503         temp = gpmc_t->we_on + dev_t->t_wpl;
1504         temp = max_t(u32, temp,
1505                         gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1506         temp = max_t(u32, temp,
1507                 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1508         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1509
1510         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1511                                                         dev_t->t_wph);
1512
1513         /* wr_cycle */
1514         temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1515         temp += gpmc_t->wr_access;
1516         /* XXX: barter t_ce_rdyz with t_cez_w ? */
1517         if (dev_t->t_ce_rdyz)
1518                 temp = max_t(u32, temp,
1519                                  gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1520         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1521
1522         return 0;
1523 }
1524
1525 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
1526                                         struct gpmc_device_timings *dev_t,
1527                                         bool mux)
1528 {
1529         u32 temp;
1530
1531         /* adv_rd_off */
1532         temp = dev_t->t_avdp_r;
1533         if (mux)
1534                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1535         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1536
1537         /* oe_on */
1538         temp = dev_t->t_oeasu;
1539         if (mux)
1540                 temp = max_t(u32, temp,
1541                         gpmc_t->adv_rd_off + dev_t->t_aavdh);
1542         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1543
1544         /* access */
1545         temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
1546                                 gpmc_t->oe_on + dev_t->t_oe);
1547         temp = max_t(u32, temp,
1548                                 gpmc_t->cs_on + dev_t->t_ce);
1549         temp = max_t(u32, temp,
1550                                 gpmc_t->adv_on + dev_t->t_aa);
1551         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1552
1553         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1554         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1555
1556         /* rd_cycle */
1557         temp = max_t(u32, dev_t->t_rd_cycle,
1558                         gpmc_t->cs_rd_off + dev_t->t_cez_r);
1559         temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1560         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1561
1562         return 0;
1563 }
1564
1565 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
1566                                          struct gpmc_device_timings *dev_t,
1567                                          bool mux)
1568 {
1569         u32 temp;
1570
1571         /* adv_wr_off */
1572         temp = dev_t->t_avdp_w;
1573         if (mux)
1574                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1575         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1576
1577         /* wr_data_mux_bus */
1578         temp = dev_t->t_weasu;
1579         if (mux) {
1580                 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1581                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1582                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1583         }
1584         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1585
1586         /* we_on */
1587         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1588                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1589         else
1590                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1591
1592         /* we_off */
1593         temp = gpmc_t->we_on + dev_t->t_wpl;
1594         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1595
1596         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1597                                                         dev_t->t_wph);
1598
1599         /* wr_cycle */
1600         temp = max_t(u32, dev_t->t_wr_cycle,
1601                                 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1602         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1603
1604         return 0;
1605 }
1606
1607 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1608                         struct gpmc_device_timings *dev_t)
1609 {
1610         u32 temp;
1611
1612         gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1613                                                 gpmc_get_fclk_period();
1614
1615         gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1616                                         dev_t->t_bacc,
1617                                         gpmc_t->sync_clk);
1618
1619         temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1620         gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1621
1622         if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1623                 return 0;
1624
1625         if (dev_t->ce_xdelay)
1626                 gpmc_t->bool_timings.cs_extra_delay = true;
1627         if (dev_t->avd_xdelay)
1628                 gpmc_t->bool_timings.adv_extra_delay = true;
1629         if (dev_t->oe_xdelay)
1630                 gpmc_t->bool_timings.oe_extra_delay = true;
1631         if (dev_t->we_xdelay)
1632                 gpmc_t->bool_timings.we_extra_delay = true;
1633
1634         return 0;
1635 }
1636
1637 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1638                                     struct gpmc_device_timings *dev_t,
1639                                     bool sync)
1640 {
1641         u32 temp;
1642
1643         /* cs_on */
1644         gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1645
1646         /* adv_on */
1647         temp = dev_t->t_avdasu;
1648         if (dev_t->t_ce_avd)
1649                 temp = max_t(u32, temp,
1650                                 gpmc_t->cs_on + dev_t->t_ce_avd);
1651         gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1652
1653         if (sync)
1654                 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1655
1656         return 0;
1657 }
1658
1659 /* TODO: remove this function once all peripherals are confirmed to
1660  * work with generic timing. Simultaneously gpmc_cs_set_timings()
1661  * has to be modified to handle timings in ps instead of ns
1662 */
1663 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1664 {
1665         t->cs_on /= 1000;
1666         t->cs_rd_off /= 1000;
1667         t->cs_wr_off /= 1000;
1668         t->adv_on /= 1000;
1669         t->adv_rd_off /= 1000;
1670         t->adv_wr_off /= 1000;
1671         t->we_on /= 1000;
1672         t->we_off /= 1000;
1673         t->oe_on /= 1000;
1674         t->oe_off /= 1000;
1675         t->page_burst_access /= 1000;
1676         t->access /= 1000;
1677         t->rd_cycle /= 1000;
1678         t->wr_cycle /= 1000;
1679         t->bus_turnaround /= 1000;
1680         t->cycle2cycle_delay /= 1000;
1681         t->wait_monitoring /= 1000;
1682         t->clk_activation /= 1000;
1683         t->wr_access /= 1000;
1684         t->wr_data_mux_bus /= 1000;
1685 }
1686
1687 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1688                       struct gpmc_settings *gpmc_s,
1689                       struct gpmc_device_timings *dev_t)
1690 {
1691         bool mux = false, sync = false;
1692
1693         if (gpmc_s) {
1694                 mux = gpmc_s->mux_add_data ? true : false;
1695                 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1696         }
1697
1698         memset(gpmc_t, 0, sizeof(*gpmc_t));
1699
1700         gpmc_calc_common_timings(gpmc_t, dev_t, sync);
1701
1702         if (gpmc_s && gpmc_s->sync_read)
1703                 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
1704         else
1705                 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
1706
1707         if (gpmc_s && gpmc_s->sync_write)
1708                 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
1709         else
1710                 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
1711
1712         /* TODO: remove, see function definition */
1713         gpmc_convert_ps_to_ns(gpmc_t);
1714
1715         return 0;
1716 }
1717
1718 /**
1719  * gpmc_cs_program_settings - programs non-timing related settings
1720  * @cs:         GPMC chip-select to program
1721  * @p:          pointer to GPMC settings structure
1722  *
1723  * Programs non-timing related settings for a GPMC chip-select, such as
1724  * bus-width, burst configuration, etc. Function should be called once
1725  * for each chip-select that is being used and must be called before
1726  * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1727  * register will be initialised to zero by this function. Returns 0 on
1728  * success and appropriate negative error code on failure.
1729  */
1730 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1731 {
1732         u32 config1;
1733
1734         if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1735                 pr_err("%s: invalid width %d!", __func__, p->device_width);
1736                 return -EINVAL;
1737         }
1738
1739         /* Address-data multiplexing not supported for NAND devices */
1740         if (p->device_nand && p->mux_add_data) {
1741                 pr_err("%s: invalid configuration!\n", __func__);
1742                 return -EINVAL;
1743         }
1744
1745         if ((p->mux_add_data > GPMC_MUX_AD) ||
1746             ((p->mux_add_data == GPMC_MUX_AAD) &&
1747              !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1748                 pr_err("%s: invalid multiplex configuration!\n", __func__);
1749                 return -EINVAL;
1750         }
1751
1752         /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1753         if (p->burst_read || p->burst_write) {
1754                 switch (p->burst_len) {
1755                 case GPMC_BURST_4:
1756                 case GPMC_BURST_8:
1757                 case GPMC_BURST_16:
1758                         break;
1759                 default:
1760                         pr_err("%s: invalid page/burst-length (%d)\n",
1761                                __func__, p->burst_len);
1762                         return -EINVAL;
1763                 }
1764         }
1765
1766         if (p->wait_pin > gpmc_nr_waitpins) {
1767                 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1768                 return -EINVAL;
1769         }
1770
1771         config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1772
1773         if (p->sync_read)
1774                 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1775         if (p->sync_write)
1776                 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1777         if (p->wait_on_read)
1778                 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1779         if (p->wait_on_write)
1780                 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1781         if (p->wait_on_read || p->wait_on_write)
1782                 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1783         if (p->device_nand)
1784                 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1785         if (p->mux_add_data)
1786                 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1787         if (p->burst_read)
1788                 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1789         if (p->burst_write)
1790                 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1791         if (p->burst_read || p->burst_write) {
1792                 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1793                 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1794         }
1795
1796         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1797
1798         return 0;
1799 }
1800
1801 #ifdef CONFIG_OF
1802 static const struct of_device_id gpmc_dt_ids[] = {
1803         { .compatible = "ti,omap2420-gpmc" },
1804         { .compatible = "ti,omap2430-gpmc" },
1805         { .compatible = "ti,omap3430-gpmc" },   /* omap3430 & omap3630 */
1806         { .compatible = "ti,omap4430-gpmc" },   /* omap4430 & omap4460 & omap543x */
1807         { .compatible = "ti,am3352-gpmc" },     /* am335x devices */
1808         { }
1809 };
1810 MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
1811
1812 /**
1813  * gpmc_read_settings_dt - read gpmc settings from device-tree
1814  * @np:         pointer to device-tree node for a gpmc child device
1815  * @p:          pointer to gpmc settings structure
1816  *
1817  * Reads the GPMC settings for a GPMC child device from device-tree and
1818  * stores them in the GPMC settings structure passed. The GPMC settings
1819  * structure is initialised to zero by this function and so any
1820  * previously stored settings will be cleared.
1821  */
1822 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1823 {
1824         memset(p, 0, sizeof(struct gpmc_settings));
1825
1826         p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1827         p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
1828         of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1829         of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1830
1831         if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1832                 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1833                 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1834                 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1835                 if (!p->burst_read && !p->burst_write)
1836                         pr_warn("%s: page/burst-length set but not used!\n",
1837                                 __func__);
1838         }
1839
1840         if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1841                 p->wait_on_read = of_property_read_bool(np,
1842                                                         "gpmc,wait-on-read");
1843                 p->wait_on_write = of_property_read_bool(np,
1844                                                          "gpmc,wait-on-write");
1845                 if (!p->wait_on_read && !p->wait_on_write)
1846                         pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1847                                  __func__);
1848         }
1849 }
1850
1851 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1852                                                 struct gpmc_timings *gpmc_t)
1853 {
1854         struct gpmc_bool_timings *p;
1855
1856         if (!np || !gpmc_t)
1857                 return;
1858
1859         memset(gpmc_t, 0, sizeof(*gpmc_t));
1860
1861         /* minimum clock period for syncronous mode */
1862         of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
1863
1864         /* chip select timtings */
1865         of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
1866         of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
1867         of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
1868
1869         /* ADV signal timings */
1870         of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
1871         of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
1872         of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
1873         of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns",
1874                              &gpmc_t->adv_aad_mux_on);
1875         of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
1876                              &gpmc_t->adv_aad_mux_rd_off);
1877         of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
1878                              &gpmc_t->adv_aad_mux_wr_off);
1879
1880         /* WE signal timings */
1881         of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
1882         of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
1883
1884         /* OE signal timings */
1885         of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
1886         of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
1887         of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns",
1888                              &gpmc_t->oe_aad_mux_on);
1889         of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns",
1890                              &gpmc_t->oe_aad_mux_off);
1891
1892         /* access and cycle timings */
1893         of_property_read_u32(np, "gpmc,page-burst-access-ns",
1894                              &gpmc_t->page_burst_access);
1895         of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
1896         of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
1897         of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
1898         of_property_read_u32(np, "gpmc,bus-turnaround-ns",
1899                              &gpmc_t->bus_turnaround);
1900         of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
1901                              &gpmc_t->cycle2cycle_delay);
1902         of_property_read_u32(np, "gpmc,wait-monitoring-ns",
1903                              &gpmc_t->wait_monitoring);
1904         of_property_read_u32(np, "gpmc,clk-activation-ns",
1905                              &gpmc_t->clk_activation);
1906
1907         /* only applicable to OMAP3+ */
1908         of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
1909         of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
1910                              &gpmc_t->wr_data_mux_bus);
1911
1912         /* bool timing parameters */
1913         p = &gpmc_t->bool_timings;
1914
1915         p->cycle2cyclediffcsen =
1916                 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
1917         p->cycle2cyclesamecsen =
1918                 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
1919         p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
1920         p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
1921         p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
1922         p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
1923         p->time_para_granularity =
1924                 of_property_read_bool(np, "gpmc,time-para-granularity");
1925 }
1926
1927 #if IS_ENABLED(CONFIG_MTD_ONENAND)
1928 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1929                                  struct device_node *child)
1930 {
1931         u32 val;
1932         struct omap_onenand_platform_data *gpmc_onenand_data;
1933
1934         if (of_property_read_u32(child, "reg", &val) < 0) {
1935                 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1936                         child->full_name);
1937                 return -ENODEV;
1938         }
1939
1940         gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data),
1941                                          GFP_KERNEL);
1942         if (!gpmc_onenand_data)
1943                 return -ENOMEM;
1944
1945         gpmc_onenand_data->cs = val;
1946         gpmc_onenand_data->of_node = child;
1947         gpmc_onenand_data->dma_channel = -1;
1948
1949         if (!of_property_read_u32(child, "dma-channel", &val))
1950                 gpmc_onenand_data->dma_channel = val;
1951
1952         gpmc_onenand_init(gpmc_onenand_data);
1953
1954         return 0;
1955 }
1956 #else
1957 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1958                                     struct device_node *child)
1959 {
1960         return 0;
1961 }
1962 #endif
1963
1964 /**
1965  * gpmc_probe_generic_child - configures the gpmc for a child device
1966  * @pdev:       pointer to gpmc platform device
1967  * @child:      pointer to device-tree node for child device
1968  *
1969  * Allocates and configures a GPMC chip-select for a child device.
1970  * Returns 0 on success and appropriate negative error code on failure.
1971  */
1972 static int gpmc_probe_generic_child(struct platform_device *pdev,
1973                                 struct device_node *child)
1974 {
1975         struct gpmc_settings gpmc_s;
1976         struct gpmc_timings gpmc_t;
1977         struct resource res;
1978         unsigned long base;
1979         const char *name;
1980         int ret, cs;
1981         u32 val;
1982         struct gpio_desc *waitpin_desc = NULL;
1983         struct gpmc_device *gpmc = platform_get_drvdata(pdev);
1984
1985         if (of_property_read_u32(child, "reg", &cs) < 0) {
1986                 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1987                         child->full_name);
1988                 return -ENODEV;
1989         }
1990
1991         if (of_address_to_resource(child, 0, &res) < 0) {
1992                 dev_err(&pdev->dev, "%s has malformed 'reg' property\n",
1993                         child->full_name);
1994                 return -ENODEV;
1995         }
1996
1997         /*
1998          * Check if we have multiple instances of the same device
1999          * on a single chip select. If so, use the already initialized
2000          * timings.
2001          */
2002         name = gpmc_cs_get_name(cs);
2003         if (name && child->name && of_node_cmp(child->name, name) == 0)
2004                         goto no_timings;
2005
2006         ret = gpmc_cs_request(cs, resource_size(&res), &base);
2007         if (ret < 0) {
2008                 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
2009                 return ret;
2010         }
2011         gpmc_cs_set_name(cs, child->name);
2012
2013         gpmc_read_settings_dt(child, &gpmc_s);
2014         gpmc_read_timings_dt(child, &gpmc_t);
2015
2016         /*
2017          * For some GPMC devices we still need to rely on the bootloader
2018          * timings because the devices can be connected via FPGA.
2019          * REVISIT: Add timing support from slls644g.pdf.
2020          */
2021         if (!gpmc_t.cs_rd_off) {
2022                 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
2023                         cs);
2024                 gpmc_cs_show_timings(cs,
2025                                      "please add GPMC bootloader timings to .dts");
2026                 goto no_timings;
2027         }
2028
2029         /* CS must be disabled while making changes to gpmc configuration */
2030         gpmc_cs_disable_mem(cs);
2031
2032         /*
2033          * FIXME: gpmc_cs_request() will map the CS to an arbitary
2034          * location in the gpmc address space. When booting with
2035          * device-tree we want the NOR flash to be mapped to the
2036          * location specified in the device-tree blob. So remap the
2037          * CS to this location. Once DT migration is complete should
2038          * just make gpmc_cs_request() map a specific address.
2039          */
2040         ret = gpmc_cs_remap(cs, res.start);
2041         if (ret < 0) {
2042                 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
2043                         cs, &res.start);
2044                 if (res.start < GPMC_MEM_START) {
2045                         dev_info(&pdev->dev,
2046                                  "GPMC CS %d start cannot be lesser than 0x%x\n",
2047                                  cs, GPMC_MEM_START);
2048                 } else if (res.end > GPMC_MEM_END) {
2049                         dev_info(&pdev->dev,
2050                                  "GPMC CS %d end cannot be greater than 0x%x\n",
2051                                  cs, GPMC_MEM_END);
2052                 }
2053                 goto err;
2054         }
2055
2056         if (of_node_cmp(child->name, "nand") == 0) {
2057                 /* Warn about older DT blobs with no compatible property */
2058                 if (!of_property_read_bool(child, "compatible")) {
2059                         dev_warn(&pdev->dev,
2060                                  "Incompatible NAND node: missing compatible");
2061                         ret = -EINVAL;
2062                         goto err;
2063                 }
2064         }
2065
2066         if (of_device_is_compatible(child, "ti,omap2-nand")) {
2067                 /* NAND specific setup */
2068                 val = 8;
2069                 of_property_read_u32(child, "nand-bus-width", &val);
2070                 switch (val) {
2071                 case 8:
2072                         gpmc_s.device_width = GPMC_DEVWIDTH_8BIT;
2073                         break;
2074                 case 16:
2075                         gpmc_s.device_width = GPMC_DEVWIDTH_16BIT;
2076                         break;
2077                 default:
2078                         dev_err(&pdev->dev, "%s: invalid 'nand-bus-width'\n",
2079                                 child->name);
2080                         ret = -EINVAL;
2081                         goto err;
2082                 }
2083
2084                 /* disable write protect */
2085                 gpmc_configure(GPMC_CONFIG_WP, 0);
2086                 gpmc_s.device_nand = true;
2087         } else {
2088                 ret = of_property_read_u32(child, "bank-width",
2089                                            &gpmc_s.device_width);
2090                 if (ret < 0)
2091                         goto err;
2092         }
2093
2094         /* Reserve wait pin if it is required and valid */
2095         if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) {
2096                 unsigned int wait_pin = gpmc_s.wait_pin;
2097
2098                 waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip,
2099                                                          wait_pin, "WAITPIN");
2100                 if (IS_ERR(waitpin_desc)) {
2101                         dev_err(&pdev->dev, "invalid wait-pin: %d\n", wait_pin);
2102                         ret = PTR_ERR(waitpin_desc);
2103                         goto err;
2104                 }
2105         }
2106
2107         gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
2108
2109         ret = gpmc_cs_program_settings(cs, &gpmc_s);
2110         if (ret < 0)
2111                 goto err_cs;
2112
2113         ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
2114         if (ret) {
2115                 dev_err(&pdev->dev, "failed to set gpmc timings for: %s\n",
2116                         child->name);
2117                 goto err_cs;
2118         }
2119
2120         /* Clear limited address i.e. enable A26-A11 */
2121         val = gpmc_read_reg(GPMC_CONFIG);
2122         val &= ~GPMC_CONFIG_LIMITEDADDRESS;
2123         gpmc_write_reg(GPMC_CONFIG, val);
2124
2125         /* Enable CS region */
2126         gpmc_cs_enable_mem(cs);
2127
2128 no_timings:
2129
2130         /* create platform device, NULL on error or when disabled */
2131         if (!of_platform_device_create(child, NULL, &pdev->dev))
2132                 goto err_child_fail;
2133
2134         /* is child a common bus? */
2135         if (of_match_node(of_default_bus_match_table, child))
2136                 /* create children and other common bus children */
2137                 if (of_platform_populate(child, of_default_bus_match_table,
2138                                          NULL, &pdev->dev))
2139                         goto err_child_fail;
2140
2141         return 0;
2142
2143 err_child_fail:
2144
2145         dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
2146         ret = -ENODEV;
2147
2148 err_cs:
2149         if (waitpin_desc)
2150                 gpiochip_free_own_desc(waitpin_desc);
2151
2152 err:
2153         gpmc_cs_free(cs);
2154
2155         return ret;
2156 }
2157
2158 static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
2159 {
2160         return 1;       /* we're input only */
2161 }
2162
2163 static int gpmc_gpio_direction_input(struct gpio_chip *chip,
2164                                      unsigned int offset)
2165 {
2166         return 0;       /* we're input only */
2167 }
2168
2169 static int gpmc_gpio_direction_output(struct gpio_chip *chip,
2170                                       unsigned int offset, int value)
2171 {
2172         return -EINVAL; /* we're input only */
2173 }
2174
2175 static void gpmc_gpio_set(struct gpio_chip *chip, unsigned int offset,
2176                           int value)
2177 {
2178 }
2179
2180 static int gpmc_gpio_get(struct gpio_chip *chip, unsigned int offset)
2181 {
2182         u32 reg;
2183
2184         offset += 8;
2185
2186         reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset);
2187
2188         return !!reg;
2189 }
2190
2191 static int gpmc_gpio_init(struct gpmc_device *gpmc)
2192 {
2193         int ret;
2194
2195         gpmc->gpio_chip.parent = gpmc->dev;
2196         gpmc->gpio_chip.owner = THIS_MODULE;
2197         gpmc->gpio_chip.label = DEVICE_NAME;
2198         gpmc->gpio_chip.ngpio = gpmc_nr_waitpins;
2199         gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction;
2200         gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input;
2201         gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output;
2202         gpmc->gpio_chip.set = gpmc_gpio_set;
2203         gpmc->gpio_chip.get = gpmc_gpio_get;
2204         gpmc->gpio_chip.base = -1;
2205
2206         ret = gpiochip_add(&gpmc->gpio_chip);
2207         if (ret < 0) {
2208                 dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret);
2209                 return ret;
2210         }
2211
2212         return 0;
2213 }
2214
2215 static void gpmc_gpio_exit(struct gpmc_device *gpmc)
2216 {
2217         gpiochip_remove(&gpmc->gpio_chip);
2218 }
2219
2220 static int gpmc_probe_dt(struct platform_device *pdev)
2221 {
2222         int ret;
2223         const struct of_device_id *of_id =
2224                 of_match_device(gpmc_dt_ids, &pdev->dev);
2225
2226         if (!of_id)
2227                 return 0;
2228
2229         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
2230                                    &gpmc_cs_num);
2231         if (ret < 0) {
2232                 pr_err("%s: number of chip-selects not defined\n", __func__);
2233                 return ret;
2234         } else if (gpmc_cs_num < 1) {
2235                 pr_err("%s: all chip-selects are disabled\n", __func__);
2236                 return -EINVAL;
2237         } else if (gpmc_cs_num > GPMC_CS_NUM) {
2238                 pr_err("%s: number of supported chip-selects cannot be > %d\n",
2239                                          __func__, GPMC_CS_NUM);
2240                 return -EINVAL;
2241         }
2242
2243         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
2244                                    &gpmc_nr_waitpins);
2245         if (ret < 0) {
2246                 pr_err("%s: number of wait pins not found!\n", __func__);
2247                 return ret;
2248         }
2249
2250         return 0;
2251 }
2252
2253 static int gpmc_probe_dt_children(struct platform_device *pdev)
2254 {
2255         int ret;
2256         struct device_node *child;
2257
2258         for_each_available_child_of_node(pdev->dev.of_node, child) {
2259
2260                 if (!child->name)
2261                         continue;
2262
2263                 if (of_node_cmp(child->name, "onenand") == 0)
2264                         ret = gpmc_probe_onenand_child(pdev, child);
2265                 else
2266                         ret = gpmc_probe_generic_child(pdev, child);
2267
2268                 if (ret)
2269                         return ret;
2270         }
2271
2272         return 0;
2273 }
2274 #else
2275 static int gpmc_probe_dt(struct platform_device *pdev)
2276 {
2277         return 0;
2278 }
2279
2280 static int gpmc_probe_dt_children(struct platform_device *pdev)
2281 {
2282         return 0;
2283 }
2284 #endif
2285
2286 static int gpmc_probe(struct platform_device *pdev)
2287 {
2288         int rc;
2289         u32 l;
2290         struct resource *res;
2291         struct gpmc_device *gpmc;
2292
2293         gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL);
2294         if (!gpmc)
2295                 return -ENOMEM;
2296
2297         gpmc->dev = &pdev->dev;
2298         platform_set_drvdata(pdev, gpmc);
2299
2300         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2301         if (res == NULL)
2302                 return -ENOENT;
2303
2304         phys_base = res->start;
2305         mem_size = resource_size(res);
2306
2307         gpmc_base = devm_ioremap_resource(&pdev->dev, res);
2308         if (IS_ERR(gpmc_base))
2309                 return PTR_ERR(gpmc_base);
2310
2311         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2312         if (!res) {
2313                 dev_err(&pdev->dev, "Failed to get resource: irq\n");
2314                 return -ENOENT;
2315         }
2316
2317         gpmc->irq = res->start;
2318
2319         gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
2320         if (IS_ERR(gpmc_l3_clk)) {
2321                 dev_err(&pdev->dev, "Failed to get GPMC fck\n");
2322                 return PTR_ERR(gpmc_l3_clk);
2323         }
2324
2325         if (!clk_get_rate(gpmc_l3_clk)) {
2326                 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
2327                 return -EINVAL;
2328         }
2329
2330         if (pdev->dev.of_node) {
2331                 rc = gpmc_probe_dt(pdev);
2332                 if (rc)
2333                         return rc;
2334         } else {
2335                 gpmc_cs_num = GPMC_CS_NUM;
2336                 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
2337         }
2338
2339         pm_runtime_enable(&pdev->dev);
2340         pm_runtime_get_sync(&pdev->dev);
2341
2342         l = gpmc_read_reg(GPMC_REVISION);
2343
2344         /*
2345          * FIXME: Once device-tree migration is complete the below flags
2346          * should be populated based upon the device-tree compatible
2347          * string. For now just use the IP revision. OMAP3+ devices have
2348          * the wr_access and wr_data_mux_bus register fields. OMAP4+
2349          * devices support the addr-addr-data multiplex protocol.
2350          *
2351          * GPMC IP revisions:
2352          * - OMAP24xx                   = 2.0
2353          * - OMAP3xxx                   = 5.0
2354          * - OMAP44xx/54xx/AM335x       = 6.0
2355          */
2356         if (GPMC_REVISION_MAJOR(l) > 0x4)
2357                 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
2358         if (GPMC_REVISION_MAJOR(l) > 0x5)
2359                 gpmc_capability |= GPMC_HAS_MUX_AAD;
2360         dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
2361                  GPMC_REVISION_MINOR(l));
2362
2363         gpmc_mem_init();
2364         rc = gpmc_gpio_init(gpmc);
2365         if (rc)
2366                 goto gpio_init_failed;
2367
2368         gpmc->nirqs = GPMC_NR_NAND_IRQS + gpmc_nr_waitpins;
2369         rc = gpmc_setup_irq(gpmc);
2370         if (rc) {
2371                 dev_err(gpmc->dev, "gpmc_setup_irq failed\n");
2372                 goto setup_irq_failed;
2373         }
2374
2375         rc = gpmc_probe_dt_children(pdev);
2376         if (rc < 0) {
2377                 dev_err(gpmc->dev, "failed to probe DT children\n");
2378                 goto dt_children_failed;
2379         }
2380
2381         return 0;
2382
2383 dt_children_failed:
2384         gpmc_free_irq(gpmc);
2385 setup_irq_failed:
2386         gpmc_gpio_exit(gpmc);
2387 gpio_init_failed:
2388         gpmc_mem_exit();
2389         pm_runtime_put_sync(&pdev->dev);
2390         pm_runtime_disable(&pdev->dev);
2391
2392         return rc;
2393 }
2394
2395 static int gpmc_remove(struct platform_device *pdev)
2396 {
2397         struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2398
2399         gpmc_free_irq(gpmc);
2400         gpmc_gpio_exit(gpmc);
2401         gpmc_mem_exit();
2402         pm_runtime_put_sync(&pdev->dev);
2403         pm_runtime_disable(&pdev->dev);
2404
2405         return 0;
2406 }
2407
2408 #ifdef CONFIG_PM_SLEEP
2409 static int gpmc_suspend(struct device *dev)
2410 {
2411         omap3_gpmc_save_context();
2412         pm_runtime_put_sync(dev);
2413         return 0;
2414 }
2415
2416 static int gpmc_resume(struct device *dev)
2417 {
2418         pm_runtime_get_sync(dev);
2419         omap3_gpmc_restore_context();
2420         return 0;
2421 }
2422 #endif
2423
2424 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
2425
2426 static struct platform_driver gpmc_driver = {
2427         .probe          = gpmc_probe,
2428         .remove         = gpmc_remove,
2429         .driver         = {
2430                 .name   = DEVICE_NAME,
2431                 .of_match_table = of_match_ptr(gpmc_dt_ids),
2432                 .pm     = &gpmc_pm_ops,
2433         },
2434 };
2435
2436 static __init int gpmc_init(void)
2437 {
2438         return platform_driver_register(&gpmc_driver);
2439 }
2440
2441 static __exit void gpmc_exit(void)
2442 {
2443         platform_driver_unregister(&gpmc_driver);
2444
2445 }
2446
2447 postcore_initcall(gpmc_init);
2448 module_exit(gpmc_exit);
2449
2450 static struct omap3_gpmc_regs gpmc_context;
2451
2452 void omap3_gpmc_save_context(void)
2453 {
2454         int i;
2455
2456         if (!gpmc_base)
2457                 return;
2458
2459         gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2460         gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2461         gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2462         gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
2463         gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2464         gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2465         gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
2466         for (i = 0; i < gpmc_cs_num; i++) {
2467                 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2468                 if (gpmc_context.cs_context[i].is_valid) {
2469                         gpmc_context.cs_context[i].config1 =
2470                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2471                         gpmc_context.cs_context[i].config2 =
2472                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2473                         gpmc_context.cs_context[i].config3 =
2474                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2475                         gpmc_context.cs_context[i].config4 =
2476                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2477                         gpmc_context.cs_context[i].config5 =
2478                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2479                         gpmc_context.cs_context[i].config6 =
2480                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2481                         gpmc_context.cs_context[i].config7 =
2482                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2483                 }
2484         }
2485 }
2486
2487 void omap3_gpmc_restore_context(void)
2488 {
2489         int i;
2490
2491         if (!gpmc_base)
2492                 return;
2493
2494         gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
2495         gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
2496         gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
2497         gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
2498         gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
2499         gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
2500         gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
2501         for (i = 0; i < gpmc_cs_num; i++) {
2502                 if (gpmc_context.cs_context[i].is_valid) {
2503                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2504                                 gpmc_context.cs_context[i].config1);
2505                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2506                                 gpmc_context.cs_context[i].config2);
2507                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2508                                 gpmc_context.cs_context[i].config3);
2509                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2510                                 gpmc_context.cs_context[i].config4);
2511                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2512                                 gpmc_context.cs_context[i].config5);
2513                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2514                                 gpmc_context.cs_context[i].config6);
2515                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2516                                 gpmc_context.cs_context[i].config7);
2517                 }
2518         }
2519 }