2 * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
4 * Copyright (C) 2012, Samsung Electronics Co., Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/clk.h>
15 #include <linux/mmc/host.h>
16 #include <linux/mmc/dw_mmc.h>
18 #include <linux/of_gpio.h>
21 #include "dw_mmc-pltfm.h"
23 #define NUM_PINS(x) (x + 2)
25 #define SDMMC_CLKSEL 0x09C
26 #define SDMMC_CLKSEL_CCLK_SAMPLE(x) (((x) & 7) << 0)
27 #define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16)
28 #define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x) & 7) << 24)
29 #define SDMMC_CLKSEL_GET_DRV_WD3(x) (((x) >> 16) & 0x7)
30 #define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) | \
31 SDMMC_CLKSEL_CCLK_DRIVE(y) | \
32 SDMMC_CLKSEL_CCLK_DIVIDER(z))
33 #define SDMMC_CLKSEL_WAKEUP_INT BIT(11)
35 #define EXYNOS4210_FIXED_CIU_CLK_DIV 2
36 #define EXYNOS4412_FIXED_CIU_CLK_DIV 4
38 /* Variations in Exynos specific dw-mshc controller */
39 enum dw_mci_exynos_type {
40 DW_MCI_TYPE_EXYNOS4210,
41 DW_MCI_TYPE_EXYNOS4412,
42 DW_MCI_TYPE_EXYNOS5250,
43 DW_MCI_TYPE_EXYNOS5420,
46 /* Exynos implementation specific driver private data */
47 struct dw_mci_exynos_priv_data {
48 enum dw_mci_exynos_type ctrl_type;
54 static struct dw_mci_exynos_compatible {
56 enum dw_mci_exynos_type ctrl_type;
59 .compatible = "samsung,exynos4210-dw-mshc",
60 .ctrl_type = DW_MCI_TYPE_EXYNOS4210,
62 .compatible = "samsung,exynos4412-dw-mshc",
63 .ctrl_type = DW_MCI_TYPE_EXYNOS4412,
65 .compatible = "samsung,exynos5250-dw-mshc",
66 .ctrl_type = DW_MCI_TYPE_EXYNOS5250,
68 .compatible = "samsung,exynos5420-dw-mshc",
69 .ctrl_type = DW_MCI_TYPE_EXYNOS5420,
73 static int dw_mci_exynos_priv_init(struct dw_mci *host)
75 struct dw_mci_exynos_priv_data *priv;
78 priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
80 dev_err(host->dev, "mem alloc failed for private data\n");
84 for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
85 if (of_device_is_compatible(host->dev->of_node,
86 exynos_compat[idx].compatible))
87 priv->ctrl_type = exynos_compat[idx].ctrl_type;
94 static int dw_mci_exynos_setup_clock(struct dw_mci *host)
96 struct dw_mci_exynos_priv_data *priv = host->priv;
98 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5250 ||
99 priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420)
100 host->bus_hz /= (priv->ciu_div + 1);
101 else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
102 host->bus_hz /= EXYNOS4412_FIXED_CIU_CLK_DIV;
103 else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
104 host->bus_hz /= EXYNOS4210_FIXED_CIU_CLK_DIV;
109 #ifdef CONFIG_PM_SLEEP
110 static int dw_mci_exynos_suspend(struct device *dev)
112 struct dw_mci *host = dev_get_drvdata(dev);
114 return dw_mci_suspend(host);
117 static int dw_mci_exynos_resume(struct device *dev)
119 struct dw_mci *host = dev_get_drvdata(dev);
121 return dw_mci_resume(host);
125 * dw_mci_exynos_resume_noirq - Exynos-specific resume code
127 * On exynos5420 there is a silicon errata that will sometimes leave the
128 * WAKEUP_INT bit in the CLKSEL register asserted. This bit is 1 to indicate
129 * that it fired and we can clear it by writing a 1 back. Clear it to prevent
130 * interrupts from going off constantly.
132 * We run this code on all exynos variants because it doesn't hurt.
135 static int dw_mci_exynos_resume_noirq(struct device *dev)
137 struct dw_mci *host = dev_get_drvdata(dev);
140 clksel = mci_readl(host, CLKSEL);
141 if (clksel & SDMMC_CLKSEL_WAKEUP_INT)
142 mci_writel(host, CLKSEL, clksel);
147 #define dw_mci_exynos_suspend NULL
148 #define dw_mci_exynos_resume NULL
149 #define dw_mci_exynos_resume_noirq NULL
150 #endif /* CONFIG_PM_SLEEP */
152 static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr)
155 * Exynos4412 and Exynos5250 extends the use of CMD register with the
156 * use of bit 29 (which is reserved on standard MSHC controllers) for
157 * optionally bypassing the HOLD register for command and data. The
158 * HOLD register should be bypassed in case there is no phase shift
159 * applied on CMD/DATA that is sent to the card.
161 if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL)))
162 *cmdr |= SDMMC_CMD_USE_HOLD_REG;
165 static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
167 struct dw_mci_exynos_priv_data *priv = host->priv;
169 if (ios->timing == MMC_TIMING_UHS_DDR50)
170 mci_writel(host, CLKSEL, priv->ddr_timing);
172 mci_writel(host, CLKSEL, priv->sdr_timing);
175 static int dw_mci_exynos_parse_dt(struct dw_mci *host)
177 struct dw_mci_exynos_priv_data *priv = host->priv;
178 struct device_node *np = host->dev->of_node;
183 of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
186 ret = of_property_read_u32_array(np,
187 "samsung,dw-mshc-sdr-timing", timing, 2);
191 priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
193 ret = of_property_read_u32_array(np,
194 "samsung,dw-mshc-ddr-timing", timing, 2);
198 priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
202 /* Common capabilities of Exynos4/Exynos5 SoC */
203 static unsigned long exynos_dwmmc_caps[4] = {
204 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
205 MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
211 static const struct dw_mci_drv_data exynos_drv_data = {
212 .caps = exynos_dwmmc_caps,
213 .init = dw_mci_exynos_priv_init,
214 .setup_clock = dw_mci_exynos_setup_clock,
215 .prepare_command = dw_mci_exynos_prepare_command,
216 .set_ios = dw_mci_exynos_set_ios,
217 .parse_dt = dw_mci_exynos_parse_dt,
220 static const struct of_device_id dw_mci_exynos_match[] = {
221 { .compatible = "samsung,exynos4412-dw-mshc",
222 .data = &exynos_drv_data, },
223 { .compatible = "samsung,exynos5250-dw-mshc",
224 .data = &exynos_drv_data, },
225 { .compatible = "samsung,exynos5420-dw-mshc",
226 .data = &exynos_drv_data, },
229 MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
231 static int dw_mci_exynos_probe(struct platform_device *pdev)
233 const struct dw_mci_drv_data *drv_data;
234 const struct of_device_id *match;
236 match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node);
237 drv_data = match->data;
238 return dw_mci_pltfm_register(pdev, drv_data);
241 const struct dev_pm_ops dw_mci_exynos_pmops = {
242 SET_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend, dw_mci_exynos_resume)
243 .resume_noirq = dw_mci_exynos_resume_noirq,
244 .thaw_noirq = dw_mci_exynos_resume_noirq,
245 .restore_noirq = dw_mci_exynos_resume_noirq,
248 static struct platform_driver dw_mci_exynos_pltfm_driver = {
249 .probe = dw_mci_exynos_probe,
250 .remove = __exit_p(dw_mci_pltfm_remove),
252 .name = "dwmmc_exynos",
253 .of_match_table = dw_mci_exynos_match,
254 .pm = &dw_mci_exynos_pmops,
258 module_platform_driver(dw_mci_exynos_pltfm_driver);
260 MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension");
261 MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com");
262 MODULE_LICENSE("GPL v2");
263 MODULE_ALIAS("platform:dwmmc-exynos");