drivers/mmc/host/dw_mmc.c

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/blkdev.h>
  15 #include <linux/clk.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/device.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/ioport.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/seq_file.h>
  26 #include <linux/slab.h>
  27 #include <linux/stat.h>
  28 #include <linux/delay.h>
  29 #include <linux/irq.h>
  30 #include <linux/mmc/host.h>
  31 #include <linux/mmc/mmc.h>
  32 #include <linux/mmc/sd.h>
  33 #include <linux/mmc/sdio.h>
  34 #include <linux/mmc/dw_mmc.h>
  35 #include <linux/bitops.h>
  36 #include <linux/regulator/consumer.h>
  37 #include <linux/workqueue.h>
  38 #include <linux/of.h>
  39 #include <linux/of_gpio.h>
  40 #include <linux/mmc/slot-gpio.h>
  41
  42 #include "dw_mmc.h"
  43
  44 /* Common flag combinations */
  45 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
  46                                  SDMMC_INT_HTO | SDMMC_INT_SBE  | \
  47                                  SDMMC_INT_EBE)
  48 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  49                                  SDMMC_INT_RESP_ERR)
  50 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
  51                                  DW_MCI_CMD_ERROR_FLAGS  | SDMMC_INT_HLE)
  52 #define DW_MCI_SEND_STATUS      1
  53 #define DW_MCI_RECV_STATUS      2
  54 #define DW_MCI_DMA_THRESHOLD    16
  55
  56 #define DW_MCI_FREQ_MAX 200000000       /* unit: HZ */
  57 #define DW_MCI_FREQ_MIN 400000          /* unit: HZ */
  58
  59 #ifdef CONFIG_MMC_DW_IDMAC
  60 #define IDMAC_INT_CLR           (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
  61                                  SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
  62                                  SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
  63                                  SDMMC_IDMAC_INT_TI)
  64
  65 struct idmac_desc {
  66         u32             des0;   /* Control Descriptor */
  67 #define IDMAC_DES0_DIC  BIT(1)
  68 #define IDMAC_DES0_LD   BIT(2)
  69 #define IDMAC_DES0_FD   BIT(3)
  70 #define IDMAC_DES0_CH   BIT(4)
  71 #define IDMAC_DES0_ER   BIT(5)
  72 #define IDMAC_DES0_CES  BIT(30)
  73 #define IDMAC_DES0_OWN  BIT(31)
  74
  75         u32             des1;   /* Buffer sizes */
  76 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
  77         ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
  78
  79         u32             des2;   /* buffer 1 physical address */
  80
  81         u32             des3;   /* buffer 2 physical address */
  82 };
  83 #endif /* CONFIG_MMC_DW_IDMAC */
  84
  85 static bool dw_mci_reset(struct dw_mci *host);
  86 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
  87
  88 #if defined(CONFIG_DEBUG_FS)
  89 static int dw_mci_req_show(struct seq_file *s, void *v)
  90 {
  91         struct dw_mci_slot *slot = s->private;
  92         struct mmc_request *mrq;
  93         struct mmc_command *cmd;
  94         struct mmc_command *stop;
  95         struct mmc_data *data;
  96
  97         /* Make sure we get a consistent snapshot */
  98         spin_lock_bh(&slot->host->lock);
  99         mrq = slot->mrq;
 100
 101         if (mrq) {
 102                 cmd = mrq->cmd;
 103                 data = mrq->data;
 104                 stop = mrq->stop;
 105
 106                 if (cmd)
 107                         seq_printf(s,
 108                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 109                                    cmd->opcode, cmd->arg, cmd->flags,
 110                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
 111                                    cmd->resp[2], cmd->error);
 112                 if (data)
 113                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 114                                    data->bytes_xfered, data->blocks,
 115                                    data->blksz, data->flags, data->error);
 116                 if (stop)
 117                         seq_printf(s,
 118                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 119                                    stop->opcode, stop->arg, stop->flags,
 120                                    stop->resp[0], stop->resp[1], stop->resp[2],
 121                                    stop->resp[2], stop->error);
 122         }
 123
 124         spin_unlock_bh(&slot->host->lock);
 125
 126         return 0;
 127 }
 128
 129 static int dw_mci_req_open(struct inode *inode, struct file *file)
 130 {
 131         return single_open(file, dw_mci_req_show, inode->i_private);
 132 }
 133
 134 static const struct file_operations dw_mci_req_fops = {
 135         .owner          = THIS_MODULE,
 136         .open           = dw_mci_req_open,
 137         .read           = seq_read,
 138         .llseek         = seq_lseek,
 139         .release        = single_release,
 140 };
 141
 142 static int dw_mci_regs_show(struct seq_file *s, void *v)
 143 {
 144         seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
 145         seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
 146         seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
 147         seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
 148         seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
 149         seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
 150
 151         return 0;
 152 }
 153
 154 static int dw_mci_regs_open(struct inode *inode, struct file *file)
 155 {
 156         return single_open(file, dw_mci_regs_show, inode->i_private);
 157 }
 158
 159 static const struct file_operations dw_mci_regs_fops = {
 160         .owner          = THIS_MODULE,
 161         .open           = dw_mci_regs_open,
 162         .read           = seq_read,
 163         .llseek         = seq_lseek,
 164         .release        = single_release,
 165 };
 166
 167 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
 168 {
 169         struct mmc_host *mmc = slot->mmc;
 170         struct dw_mci *host = slot->host;
 171         struct dentry *root;
 172         struct dentry *node;
 173
 174         root = mmc->debugfs_root;
 175         if (!root)
 176                 return;
 177
 178         node = debugfs_create_file("regs", S_IRUSR, root, host,
 179                                    &dw_mci_regs_fops);
 180         if (!node)
 181                 goto err;
 182
 183         node = debugfs_create_file("req", S_IRUSR, root, slot,
 184                                    &dw_mci_req_fops);
 185         if (!node)
 186                 goto err;
 187
 188         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 189         if (!node)
 190                 goto err;
 191
 192         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 193                                   (u32 *)&host->pending_events);
 194         if (!node)
 195                 goto err;
 196
 197         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 198                                   (u32 *)&host->completed_events);
 199         if (!node)
 200                 goto err;
 201
 202         return;
 203
 204 err:
 205         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 206 }
 207 #endif /* defined(CONFIG_DEBUG_FS) */
 208
 209 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
 210
 211 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 212 {
 213         struct mmc_data *data;
 214         struct dw_mci_slot *slot = mmc_priv(mmc);
 215         struct dw_mci *host = slot->host;
 216         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
 217         u32 cmdr;
 218         cmd->error = -EINPROGRESS;
 219
 220         cmdr = cmd->opcode;
 221
 222         if (cmd->opcode == MMC_STOP_TRANSMISSION ||
 223             cmd->opcode == MMC_GO_IDLE_STATE ||
 224             cmd->opcode == MMC_GO_INACTIVE_STATE ||
 225             (cmd->opcode == SD_IO_RW_DIRECT &&
 226              ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
 227                 cmdr |= SDMMC_CMD_STOP;
 228         else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
 229                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 230
 231         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
 232                 u32 clk_en_a;
 233
 234                 /* Special bit makes CMD11 not die */
 235                 cmdr |= SDMMC_CMD_VOLT_SWITCH;
 236
 237                 /* Change state to continue to handle CMD11 weirdness */
 238                 WARN_ON(slot->host->state != STATE_SENDING_CMD);
 239                 slot->host->state = STATE_SENDING_CMD11;
 240
 241                 /*
 242                  * We need to disable low power mode (automatic clock stop)
 243                  * while doing voltage switch so we don't confuse the card,
 244                  * since stopping the clock is a specific part of the UHS
 245                  * voltage change dance.
 246                  *
 247                  * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
 248                  * unconditionally turned back on in dw_mci_setup_bus() if it's
 249                  * ever called with a non-zero clock.  That shouldn't happen
 250                  * until the voltage change is all done.
 251                  */
 252                 clk_en_a = mci_readl(host, CLKENA);
 253                 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
 254                 mci_writel(host, CLKENA, clk_en_a);
 255                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
 256                              SDMMC_CMD_PRV_DAT_WAIT, 0);
 257         }
 258
 259         if (cmd->flags & MMC_RSP_PRESENT) {
 260                 /* We expect a response, so set this bit */
 261                 cmdr |= SDMMC_CMD_RESP_EXP;
 262                 if (cmd->flags & MMC_RSP_136)
 263                         cmdr |= SDMMC_CMD_RESP_LONG;
 264         }
 265
 266         if (cmd->flags & MMC_RSP_CRC)
 267                 cmdr |= SDMMC_CMD_RESP_CRC;
 268
 269         data = cmd->data;
 270         if (data) {
 271                 cmdr |= SDMMC_CMD_DAT_EXP;
 272                 if (data->flags & MMC_DATA_STREAM)
 273                         cmdr |= SDMMC_CMD_STRM_MODE;
 274                 if (data->flags & MMC_DATA_WRITE)
 275                         cmdr |= SDMMC_CMD_DAT_WR;
 276         }
 277
 278         if (drv_data && drv_data->prepare_command)
 279                 drv_data->prepare_command(slot->host, &cmdr);
 280
 281         return cmdr;
 282 }
 283
 284 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
 285 {
 286         struct mmc_command *stop;
 287         u32 cmdr;
 288
 289         if (!cmd->data)
 290                 return 0;
 291
 292         stop = &host->stop_abort;
 293         cmdr = cmd->opcode;
 294         memset(stop, 0, sizeof(struct mmc_command));
 295
 296         if (cmdr == MMC_READ_SINGLE_BLOCK ||
 297             cmdr == MMC_READ_MULTIPLE_BLOCK ||
 298             cmdr == MMC_WRITE_BLOCK ||
 299             cmdr == MMC_WRITE_MULTIPLE_BLOCK) {
 300                 stop->opcode = MMC_STOP_TRANSMISSION;
 301                 stop->arg = 0;
 302                 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
 303         } else if (cmdr == SD_IO_RW_EXTENDED) {
 304                 stop->opcode = SD_IO_RW_DIRECT;
 305                 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
 306                              ((cmd->arg >> 28) & 0x7);
 307                 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
 308         } else {
 309                 return 0;
 310         }
 311
 312         cmdr = stop->opcode | SDMMC_CMD_STOP |
 313                 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
 314
 315         return cmdr;
 316 }
 317
 318 static void dw_mci_start_command(struct dw_mci *host,
 319                                  struct mmc_command *cmd, u32 cmd_flags)
 320 {
 321         host->cmd = cmd;
 322         dev_vdbg(host->dev,
 323                  "start command: ARGR=0x%08x CMDR=0x%08x\n",
 324                  cmd->arg, cmd_flags);
 325
 326         mci_writel(host, CMDARG, cmd->arg);
 327         wmb();
 328
 329         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 330 }
 331
 332 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
 333 {
 334         struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort;
 335         dw_mci_start_command(host, stop, host->stop_cmdr);
 336 }
 337
 338 /* DMA interface functions */
 339 static void dw_mci_stop_dma(struct dw_mci *host)
 340 {
 341         if (host->using_dma) {
 342                 host->dma_ops->stop(host);
 343                 host->dma_ops->cleanup(host);
 344         }
 345
 346         /* Data transfer was stopped by the interrupt handler */
 347         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 348 }
 349
 350 static int dw_mci_get_dma_dir(struct mmc_data *data)
 351 {
 352         if (data->flags & MMC_DATA_WRITE)
 353                 return DMA_TO_DEVICE;
 354         else
 355                 return DMA_FROM_DEVICE;
 356 }
 357
 358 #ifdef CONFIG_MMC_DW_IDMAC
 359 static void dw_mci_dma_cleanup(struct dw_mci *host)
 360 {
 361         struct mmc_data *data = host->data;
 362
 363         if (data)
 364                 if (!data->host_cookie)
 365                         dma_unmap_sg(host->dev,
 366                                      data->sg,
 367                                      data->sg_len,
 368                                      dw_mci_get_dma_dir(data));
 369 }
 370
 371 static void dw_mci_idmac_reset(struct dw_mci *host)
 372 {
 373         u32 bmod = mci_readl(host, BMOD);
 374         /* Software reset of DMA */
 375         bmod |= SDMMC_IDMAC_SWRESET;
 376         mci_writel(host, BMOD, bmod);
 377 }
 378
 379 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 380 {
 381         u32 temp;
 382
 383         /* Disable and reset the IDMAC interface */
 384         temp = mci_readl(host, CTRL);
 385         temp &= ~SDMMC_CTRL_USE_IDMAC;
 386         temp |= SDMMC_CTRL_DMA_RESET;
 387         mci_writel(host, CTRL, temp);
 388
 389         /* Stop the IDMAC running */
 390         temp = mci_readl(host, BMOD);
 391         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
 392         temp |= SDMMC_IDMAC_SWRESET;
 393         mci_writel(host, BMOD, temp);
 394 }
 395
 396 static void dw_mci_idmac_complete_dma(struct dw_mci *host)
 397 {
 398         struct mmc_data *data = host->data;
 399
 400         dev_vdbg(host->dev, "DMA complete\n");
 401
 402         host->dma_ops->cleanup(host);
 403
 404         /*
 405          * If the card was removed, data will be NULL. No point in trying to
 406          * send the stop command or waiting for NBUSY in this case.
 407          */
 408         if (data) {
 409                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 410                 tasklet_schedule(&host->tasklet);
 411         }
 412 }
 413
 414 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
 415                                     unsigned int sg_len)
 416 {
 417         int i;
 418         struct idmac_desc *desc = host->sg_cpu;
 419
 420         for (i = 0; i < sg_len; i++, desc++) {
 421                 unsigned int length = sg_dma_len(&data->sg[i]);
 422                 u32 mem_addr = sg_dma_address(&data->sg[i]);
 423
 424                 /* Set the OWN bit and disable interrupts for this descriptor */
 425                 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
 426
 427                 /* Buffer length */
 428                 IDMAC_SET_BUFFER1_SIZE(desc, length);
 429
 430                 /* Physical address to DMA to/from */
 431                 desc->des2 = mem_addr;
 432         }
 433
 434         /* Set first descriptor */
 435         desc = host->sg_cpu;
 436         desc->des0 |= IDMAC_DES0_FD;
 437
 438         /* Set last descriptor */
 439         desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
 440         desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
 441         desc->des0 |= IDMAC_DES0_LD;
 442
 443         wmb();
 444 }
 445
 446 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 447 {
 448         u32 temp;
 449
 450         dw_mci_translate_sglist(host, host->data, sg_len);
 451
 452         /* Make sure to reset DMA in case we did PIO before this */
 453         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
 454         dw_mci_idmac_reset(host);
 455
 456         /* Select IDMAC interface */
 457         temp = mci_readl(host, CTRL);
 458         temp |= SDMMC_CTRL_USE_IDMAC;
 459         mci_writel(host, CTRL, temp);
 460
 461         wmb();
 462
 463         /* Enable the IDMAC */
 464         temp = mci_readl(host, BMOD);
 465         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
 466         mci_writel(host, BMOD, temp);
 467
 468         /* Start it running */
 469         mci_writel(host, PLDMND, 1);
 470 }
 471
 472 static int dw_mci_idmac_init(struct dw_mci *host)
 473 {
 474         struct idmac_desc *p;
 475         int i;
 476
 477         /* Number of descriptors in the ring buffer */
 478         host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
 479
 480         /* Forward link the descriptor list */
 481         for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
 482                 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
 483
 484         /* Set the last descriptor as the end-of-ring descriptor */
 485         p->des3 = host->sg_dma;
 486         p->des0 = IDMAC_DES0_ER;
 487
 488         dw_mci_idmac_reset(host);
 489
 490         /* Mask out interrupts - get Tx & Rx complete only */
 491         mci_writel(host, IDSTS, IDMAC_INT_CLR);
 492         mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
 493                    SDMMC_IDMAC_INT_TI);
 494
 495         /* Set the descriptor base address */
 496         mci_writel(host, DBADDR, host->sg_dma);
 497         return 0;
 498 }
 499
 500 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
 501         .init = dw_mci_idmac_init,
 502         .start = dw_mci_idmac_start_dma,
 503         .stop = dw_mci_idmac_stop_dma,
 504         .complete = dw_mci_idmac_complete_dma,
 505         .cleanup = dw_mci_dma_cleanup,
 506 };
 507 #endif /* CONFIG_MMC_DW_IDMAC */
 508
 509 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
 510                                    struct mmc_data *data,
 511                                    bool next)
 512 {
 513         struct scatterlist *sg;
 514         unsigned int i, sg_len;
 515
 516         if (!next && data->host_cookie)
 517                 return data->host_cookie;
 518
 519         /*
 520          * We don't do DMA on "complex" transfers, i.e. with
 521          * non-word-aligned buffers or lengths. Also, we don't bother
 522          * with all the DMA setup overhead for short transfers.
 523          */
 524         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
 525                 return -EINVAL;
 526
 527         if (data->blksz & 3)
 528                 return -EINVAL;
 529
 530         for_each_sg(data->sg, sg, data->sg_len, i) {
 531                 if (sg->offset & 3 || sg->length & 3)
 532                         return -EINVAL;
 533         }
 534
 535         sg_len = dma_map_sg(host->dev,
 536                             data->sg,
 537                             data->sg_len,
 538                             dw_mci_get_dma_dir(data));
 539         if (sg_len == 0)
 540                 return -EINVAL;
 541
 542         if (next)
 543                 data->host_cookie = sg_len;
 544
 545         return sg_len;
 546 }
 547
 548 static void dw_mci_pre_req(struct mmc_host *mmc,
 549                            struct mmc_request *mrq,
 550                            bool is_first_req)
 551 {
 552         struct dw_mci_slot *slot = mmc_priv(mmc);
 553         struct mmc_data *data = mrq->data;
 554
 555         if (!slot->host->use_dma || !data)
 556                 return;
 557
 558         if (data->host_cookie) {
 559                 data->host_cookie = 0;
 560                 return;
 561         }
 562
 563         if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
 564                 data->host_cookie = 0;
 565 }
 566
 567 static void dw_mci_post_req(struct mmc_host *mmc,
 568                             struct mmc_request *mrq,
 569                             int err)
 570 {
 571         struct dw_mci_slot *slot = mmc_priv(mmc);
 572         struct mmc_data *data = mrq->data;
 573
 574         if (!slot->host->use_dma || !data)
 575                 return;
 576
 577         if (data->host_cookie)
 578                 dma_unmap_sg(slot->host->dev,
 579                              data->sg,
 580                              data->sg_len,
 581                              dw_mci_get_dma_dir(data));
 582         data->host_cookie = 0;
 583 }
 584
 585 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
 586 {
 587 #ifdef CONFIG_MMC_DW_IDMAC
 588         unsigned int blksz = data->blksz;
 589         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 590         u32 fifo_width = 1 << host->data_shift;
 591         u32 blksz_depth = blksz / fifo_width, fifoth_val;
 592         u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
 593         int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1;
 594
 595         tx_wmark = (host->fifo_depth) / 2;
 596         tx_wmark_invers = host->fifo_depth - tx_wmark;
 597
 598         /*
 599          * MSIZE is '1',
 600          * if blksz is not a multiple of the FIFO width
 601          */
 602         if (blksz % fifo_width) {
 603                 msize = 0;
 604                 rx_wmark = 1;
 605                 goto done;
 606         }
 607
 608         do {
 609                 if (!((blksz_depth % mszs[idx]) ||
 610                      (tx_wmark_invers % mszs[idx]))) {
 611                         msize = idx;
 612                         rx_wmark = mszs[idx] - 1;
 613                         break;
 614                 }
 615         } while (--idx > 0);
 616         /*
 617          * If idx is '0', it won't be tried
 618          * Thus, initial values are uesed
 619          */
 620 done:
 621         fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
 622         mci_writel(host, FIFOTH, fifoth_val);
 623 #endif
 624 }
 625
 626 static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
 627 {
 628         unsigned int blksz = data->blksz;
 629         u32 blksz_depth, fifo_depth;
 630         u16 thld_size;
 631
 632         WARN_ON(!(data->flags & MMC_DATA_READ));
 633
 634         if (host->timing != MMC_TIMING_MMC_HS200 &&
 635             host->timing != MMC_TIMING_UHS_SDR104)
 636                 goto disable;
 637
 638         blksz_depth = blksz / (1 << host->data_shift);
 639         fifo_depth = host->fifo_depth;
 640
 641         if (blksz_depth > fifo_depth)
 642                 goto disable;
 643
 644         /*
 645          * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
 646          * If (blksz_depth) <  (fifo_depth >> 1), should be thld_size = blksz
 647          * Currently just choose blksz.
 648          */
 649         thld_size = blksz;
 650         mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
 651         return;
 652
 653 disable:
 654         mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
 655 }
 656
 657 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
 658 {
 659         int sg_len;
 660         u32 temp;
 661
 662         host->using_dma = 0;
 663
 664         /* If we don't have a channel, we can't do DMA */
 665         if (!host->use_dma)
 666                 return -ENODEV;
 667
 668         sg_len = dw_mci_pre_dma_transfer(host, data, 0);
 669         if (sg_len < 0) {
 670                 host->dma_ops->stop(host);
 671                 return sg_len;
 672         }
 673
 674         host->using_dma = 1;
 675
 676         dev_vdbg(host->dev,
 677                  "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
 678                  (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
 679                  sg_len);
 680
 681         /*
 682          * Decide the MSIZE and RX/TX Watermark.
 683          * If current block size is same with previous size,
 684          * no need to update fifoth.
 685          */
 686         if (host->prev_blksz != data->blksz)
 687                 dw_mci_adjust_fifoth(host, data);
 688
 689         /* Enable the DMA interface */
 690         temp = mci_readl(host, CTRL);
 691         temp |= SDMMC_CTRL_DMA_ENABLE;
 692         mci_writel(host, CTRL, temp);
 693
 694         /* Disable RX/TX IRQs, let DMA handle it */
 695         temp = mci_readl(host, INTMASK);
 696         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
 697         mci_writel(host, INTMASK, temp);
 698
 699         host->dma_ops->start(host, sg_len);
 700
 701         return 0;
 702 }
 703
 704 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
 705 {
 706         u32 temp;
 707
 708         data->error = -EINPROGRESS;
 709
 710         WARN_ON(host->data);
 711         host->sg = NULL;
 712         host->data = data;
 713
 714         if (data->flags & MMC_DATA_READ) {
 715                 host->dir_status = DW_MCI_RECV_STATUS;
 716                 dw_mci_ctrl_rd_thld(host, data);
 717         } else {
 718                 host->dir_status = DW_MCI_SEND_STATUS;
 719         }
 720
 721         if (dw_mci_submit_data_dma(host, data)) {
 722                 int flags = SG_MITER_ATOMIC;
 723                 if (host->data->flags & MMC_DATA_READ)
 724                         flags |= SG_MITER_TO_SG;
 725                 else
 726                         flags |= SG_MITER_FROM_SG;
 727
 728                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 729                 host->sg = data->sg;
 730                 host->part_buf_start = 0;
 731                 host->part_buf_count = 0;
 732
 733                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
 734                 temp = mci_readl(host, INTMASK);
 735                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
 736                 mci_writel(host, INTMASK, temp);
 737
 738                 temp = mci_readl(host, CTRL);
 739                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
 740                 mci_writel(host, CTRL, temp);
 741
 742                 /*
 743                  * Use the initial fifoth_val for PIO mode.
 744                  * If next issued data may be transfered by DMA mode,
 745                  * prev_blksz should be invalidated.
 746                  */
 747                 mci_writel(host, FIFOTH, host->fifoth_val);
 748                 host->prev_blksz = 0;
 749         } else {
 750                 /*
 751                  * Keep the current block size.
 752                  * It will be used to decide whether to update
 753                  * fifoth register next time.
 754                  */
 755                 host->prev_blksz = data->blksz;
 756         }
 757 }
 758
 759 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
 760 {
 761         struct dw_mci *host = slot->host;
 762         unsigned long timeout = jiffies + msecs_to_jiffies(500);
 763         unsigned int cmd_status = 0;
 764
 765         mci_writel(host, CMDARG, arg);
 766         wmb();
 767         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
 768
 769         while (time_before(jiffies, timeout)) {
 770                 cmd_status = mci_readl(host, CMD);
 771                 if (!(cmd_status & SDMMC_CMD_START))
 772                         return;
 773         }
 774         dev_err(&slot->mmc->class_dev,
 775                 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
 776                 cmd, arg, cmd_status);
 777 }
 778
 779 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
 780 {
 781         struct dw_mci *host = slot->host;
 782         unsigned int clock = slot->clock;
 783         u32 div;
 784         u32 clk_en_a;
 785         u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
 786
 787         /* We must continue to set bit 28 in CMD until the change is complete */
 788         if (host->state == STATE_WAITING_CMD11_DONE)
 789                 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
 790
 791         if (!clock) {
 792                 mci_writel(host, CLKENA, 0);
 793                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
 794         } else if (clock != host->current_speed || force_clkinit) {
 795                 div = host->bus_hz / clock;
 796                 if (host->bus_hz % clock && host->bus_hz > clock)
 797                         /*
 798                          * move the + 1 after the divide to prevent
 799                          * over-clocking the card.
 800                          */
 801                         div += 1;
 802
 803                 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
 804
 805                 if ((clock << div) != slot->__clk_old || force_clkinit)
 806                         dev_info(&slot->mmc->class_dev,
 807                                  "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
 808                                  slot->id, host->bus_hz, clock,
 809                                  div ? ((host->bus_hz / div) >> 1) :
 810                                  host->bus_hz, div);
 811
 812                 /* disable clock */
 813                 mci_writel(host, CLKENA, 0);
 814                 mci_writel(host, CLKSRC, 0);
 815
 816                 /* inform CIU */
 817                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
 818
 819                 /* set clock to desired speed */
 820                 mci_writel(host, CLKDIV, div);
 821
 822                 /* inform CIU */
 823                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
 824
 825                 /* enable clock; only low power if no SDIO */
 826                 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
 827                 if (!(mci_readl(host, INTMASK) & SDMMC_INT_SDIO(slot->id)))
 828                         clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
 829                 mci_writel(host, CLKENA, clk_en_a);
 830
 831                 /* inform CIU */
 832                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
 833
 834                 /* keep the clock with reflecting clock dividor */
 835                 slot->__clk_old = clock << div;
 836         }
 837
 838         host->current_speed = clock;
 839
 840         /* Set the current slot bus width */
 841         mci_writel(host, CTYPE, (slot->ctype << slot->id));
 842 }
 843
 844 static void __dw_mci_start_request(struct dw_mci *host,
 845                                    struct dw_mci_slot *slot,
 846                                    struct mmc_command *cmd)
 847 {
 848         struct mmc_request *mrq;
 849         struct mmc_data *data;
 850         u32 cmdflags;
 851
 852         mrq = slot->mrq;
 853
 854         host->cur_slot = slot;
 855         host->mrq = mrq;
 856
 857         host->pending_events = 0;
 858         host->completed_events = 0;
 859         host->cmd_status = 0;
 860         host->data_status = 0;
 861         host->dir_status = 0;
 862
 863         data = cmd->data;
 864         if (data) {
 865                 mci_writel(host, TMOUT, 0xFFFFFFFF);
 866                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
 867                 mci_writel(host, BLKSIZ, data->blksz);
 868         }
 869
 870         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
 871
 872         /* this is the first command, send the initialization clock */
 873         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
 874                 cmdflags |= SDMMC_CMD_INIT;
 875
 876         if (data) {
 877                 dw_mci_submit_data(host, data);
 878                 wmb();
 879         }
 880
 881         dw_mci_start_command(host, cmd, cmdflags);
 882
 883         if (mrq->stop)
 884                 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
 885         else
 886                 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
 887 }
 888
 889 static void dw_mci_start_request(struct dw_mci *host,
 890                                  struct dw_mci_slot *slot)
 891 {
 892         struct mmc_request *mrq = slot->mrq;
 893         struct mmc_command *cmd;
 894
 895         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
 896         __dw_mci_start_request(host, slot, cmd);
 897 }
 898
 899 /* must be called with host->lock held */
 900 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
 901                                  struct mmc_request *mrq)
 902 {
 903         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
 904                  host->state);
 905
 906         slot->mrq = mrq;
 907
 908         if (host->state == STATE_WAITING_CMD11_DONE) {
 909                 dev_warn(&slot->mmc->class_dev,
 910                          "Voltage change didn't complete\n");
 911                 /*
 912                  * this case isn't expected to happen, so we can
 913                  * either crash here or just try to continue on
 914                  * in the closest possible state
 915                  */
 916                 host->state = STATE_IDLE;
 917         }
 918
 919         if (host->state == STATE_IDLE) {
 920                 host->state = STATE_SENDING_CMD;
 921                 dw_mci_start_request(host, slot);
 922         } else {
 923                 list_add_tail(&slot->queue_node, &host->queue);
 924         }
 925 }
 926
 927 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
 928 {
 929         struct dw_mci_slot *slot = mmc_priv(mmc);
 930         struct dw_mci *host = slot->host;
 931
 932         WARN_ON(slot->mrq);
 933
 934         /*
 935          * The check for card presence and queueing of the request must be
 936          * atomic, otherwise the card could be removed in between and the
 937          * request wouldn't fail until another card was inserted.
 938          */
 939         spin_lock_bh(&host->lock);
 940
 941         if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
 942                 spin_unlock_bh(&host->lock);
 943                 mrq->cmd->error = -ENOMEDIUM;
 944                 mmc_request_done(mmc, mrq);
 945                 return;
 946         }
 947
 948         dw_mci_queue_request(host, slot, mrq);
 949
 950         spin_unlock_bh(&host->lock);
 951 }
 952
 953 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 954 {
 955         struct dw_mci_slot *slot = mmc_priv(mmc);
 956         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
 957         u32 regs;
 958         int ret;
 959
 960         switch (ios->bus_width) {
 961         case MMC_BUS_WIDTH_4:
 962                 slot->ctype = SDMMC_CTYPE_4BIT;
 963                 break;
 964         case MMC_BUS_WIDTH_8:
 965                 slot->ctype = SDMMC_CTYPE_8BIT;
 966                 break;
 967         default:
 968                 /* set default 1 bit mode */
 969                 slot->ctype = SDMMC_CTYPE_1BIT;
 970         }
 971
 972         regs = mci_readl(slot->host, UHS_REG);
 973
 974         /* DDR mode set */
 975         if (ios->timing == MMC_TIMING_MMC_DDR52)
 976                 regs |= ((0x1 << slot->id) << 16);
 977         else
 978                 regs &= ~((0x1 << slot->id) << 16);
 979
 980         mci_writel(slot->host, UHS_REG, regs);
 981         slot->host->timing = ios->timing;
 982
 983         /*
 984          * Use mirror of ios->clock to prevent race with mmc
 985          * core ios update when finding the minimum.
 986          */
 987         slot->clock = ios->clock;
 988
 989         if (drv_data && drv_data->set_ios)
 990                 drv_data->set_ios(slot->host, ios);
 991
 992         /* Slot specific timing and width adjustment */
 993         dw_mci_setup_bus(slot, false);
 994
 995         if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
 996                 slot->host->state = STATE_IDLE;
 997
 998         switch (ios->power_mode) {
 999         case MMC_POWER_UP:
1000                 if (!IS_ERR(mmc->supply.vmmc)) {
1001                         ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1002                                         ios->vdd);
1003                         if (ret) {
1004                                 dev_err(slot->host->dev,
1005                                         "failed to enable vmmc regulator\n");
1006                                 /*return, if failed turn on vmmc*/
1007                                 return;
1008                         }
1009                 }
1010                 if (!IS_ERR(mmc->supply.vqmmc) && !slot->host->vqmmc_enabled) {
1011                         ret = regulator_enable(mmc->supply.vqmmc);
1012                         if (ret < 0)
1013                                 dev_err(slot->host->dev,
1014                                         "failed to enable vqmmc regulator\n");
1015                         else
1016                                 slot->host->vqmmc_enabled = true;
1017                 }
1018                 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1019                 regs = mci_readl(slot->host, PWREN);
1020                 regs |= (1 << slot->id);
1021                 mci_writel(slot->host, PWREN, regs);
1022                 break;
1023         case MMC_POWER_OFF:
1024                 if (!IS_ERR(mmc->supply.vmmc))
1025                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1026
1027                 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) {
1028                         regulator_disable(mmc->supply.vqmmc);
1029                         slot->host->vqmmc_enabled = false;
1030                 }
1031
1032                 regs = mci_readl(slot->host, PWREN);
1033                 regs &= ~(1 << slot->id);
1034                 mci_writel(slot->host, PWREN, regs);
1035                 break;
1036         default:
1037                 break;
1038         }
1039 }
1040
1041 static int dw_mci_card_busy(struct mmc_host *mmc)
1042 {
1043         struct dw_mci_slot *slot = mmc_priv(mmc);
1044         u32 status;
1045
1046         /*
1047          * Check the busy bit which is low when DAT[3:0]
1048          * (the data lines) are 0000
1049          */
1050         status = mci_readl(slot->host, STATUS);
1051
1052         return !!(status & SDMMC_STATUS_BUSY);
1053 }
1054
1055 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1056 {
1057         struct dw_mci_slot *slot = mmc_priv(mmc);
1058         struct dw_mci *host = slot->host;
1059         u32 uhs;
1060         u32 v18 = SDMMC_UHS_18V << slot->id;
1061         int min_uv, max_uv;
1062         int ret;
1063
1064         /*
1065          * Program the voltage.  Note that some instances of dw_mmc may use
1066          * the UHS_REG for this.  For other instances (like exynos) the UHS_REG
1067          * does no harm but you need to set the regulator directly.  Try both.
1068          */
1069         uhs = mci_readl(host, UHS_REG);
1070         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1071                 min_uv = 2700000;
1072                 max_uv = 3600000;
1073                 uhs &= ~v18;
1074         } else {
1075                 min_uv = 1700000;
1076                 max_uv = 1950000;
1077                 uhs |= v18;
1078         }
1079         if (!IS_ERR(mmc->supply.vqmmc)) {
1080                 ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv);
1081
1082                 if (ret) {
1083                         dev_dbg(&mmc->class_dev,
1084                                          "Regulator set error %d: %d - %d\n",
1085                                          ret, min_uv, max_uv);
1086                         return ret;
1087                 }
1088         }
1089         mci_writel(host, UHS_REG, uhs);
1090
1091         return 0;
1092 }
1093
1094 static int dw_mci_get_ro(struct mmc_host *mmc)
1095 {
1096         int read_only;
1097         struct dw_mci_slot *slot = mmc_priv(mmc);
1098         int gpio_ro = mmc_gpio_get_ro(mmc);
1099
1100         /* Use platform get_ro function, else try on board write protect */
1101         if ((slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT) ||
1102                         (slot->host->quirks & DW_MCI_QUIRK_NO_WRITE_PROTECT))
1103                 read_only = 0;
1104         else if (!IS_ERR_VALUE(gpio_ro))
1105                 read_only = gpio_ro;
1106         else
1107                 read_only =
1108                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1109
1110         dev_dbg(&mmc->class_dev, "card is %s\n",
1111                 read_only ? "read-only" : "read-write");
1112
1113         return read_only;
1114 }
1115
1116 static int dw_mci_get_cd(struct mmc_host *mmc)
1117 {
1118         int present;
1119         struct dw_mci_slot *slot = mmc_priv(mmc);
1120         struct dw_mci_board *brd = slot->host->pdata;
1121         struct dw_mci *host = slot->host;
1122         int gpio_cd = mmc_gpio_get_cd(mmc);
1123
1124         /* Use platform get_cd function, else try onboard card detect */
1125         if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
1126                 present = 1;
1127         else if (!IS_ERR_VALUE(gpio_cd))
1128                 present = gpio_cd;
1129         else
1130                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1131                         == 0 ? 1 : 0;
1132
1133         spin_lock_bh(&host->lock);
1134         if (present) {
1135                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1136                 dev_dbg(&mmc->class_dev, "card is present\n");
1137         } else {
1138                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1139                 dev_dbg(&mmc->class_dev, "card is not present\n");
1140         }
1141         spin_unlock_bh(&host->lock);
1142
1143         return present;
1144 }
1145
1146 /*
1147  * Disable lower power mode.
1148  *
1149  * Low power mode will stop the card clock when idle.  According to the
1150  * description of the CLKENA register we should disable low power mode
1151  * for SDIO cards if we need SDIO interrupts to work.
1152  *
1153  * This function is fast if low power mode is already disabled.
1154  */
1155 static void dw_mci_disable_low_power(struct dw_mci_slot *slot)
1156 {
1157         struct dw_mci *host = slot->host;
1158         u32 clk_en_a;
1159         const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1160
1161         clk_en_a = mci_readl(host, CLKENA);
1162
1163         if (clk_en_a & clken_low_pwr) {
1164                 mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr);
1165                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1166                              SDMMC_CMD_PRV_DAT_WAIT, 0);
1167         }
1168 }
1169
1170 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1171 {
1172         struct dw_mci_slot *slot = mmc_priv(mmc);
1173         struct dw_mci *host = slot->host;
1174         u32 int_mask;
1175
1176         /* Enable/disable Slot Specific SDIO interrupt */
1177         int_mask = mci_readl(host, INTMASK);
1178         if (enb) {
1179                 /*
1180                  * Turn off low power mode if it was enabled.  This is a bit of
1181                  * a heavy operation and we disable / enable IRQs a lot, so
1182                  * we'll leave low power mode disabled and it will get
1183                  * re-enabled again in dw_mci_setup_bus().
1184                  */
1185                 dw_mci_disable_low_power(slot);
1186
1187                 mci_writel(host, INTMASK,
1188                            (int_mask | SDMMC_INT_SDIO(slot->id)));
1189         } else {
1190                 mci_writel(host, INTMASK,
1191                            (int_mask & ~SDMMC_INT_SDIO(slot->id)));
1192         }
1193 }
1194
1195 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1196 {
1197         struct dw_mci_slot *slot = mmc_priv(mmc);
1198         struct dw_mci *host = slot->host;
1199         const struct dw_mci_drv_data *drv_data = host->drv_data;
1200         struct dw_mci_tuning_data tuning_data;
1201         int err = -ENOSYS;
1202
1203         if (opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1204                 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
1205                         tuning_data.blk_pattern = tuning_blk_pattern_8bit;
1206                         tuning_data.blksz = sizeof(tuning_blk_pattern_8bit);
1207                 } else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
1208                         tuning_data.blk_pattern = tuning_blk_pattern_4bit;
1209                         tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
1210                 } else {
1211                         return -EINVAL;
1212                 }
1213         } else if (opcode == MMC_SEND_TUNING_BLOCK) {
1214                 tuning_data.blk_pattern = tuning_blk_pattern_4bit;
1215                 tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
1216         } else {
1217                 dev_err(host->dev,
1218                         "Undefined command(%d) for tuning\n", opcode);
1219                 return -EINVAL;
1220         }
1221
1222         if (drv_data && drv_data->execute_tuning)
1223                 err = drv_data->execute_tuning(slot, opcode, &tuning_data);
1224         return err;
1225 }
1226
1227 static const struct mmc_host_ops dw_mci_ops = {
1228         .request                = dw_mci_request,
1229         .pre_req                = dw_mci_pre_req,
1230         .post_req               = dw_mci_post_req,
1231         .set_ios                = dw_mci_set_ios,
1232         .get_ro                 = dw_mci_get_ro,
1233         .get_cd                 = dw_mci_get_cd,
1234         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
1235         .execute_tuning         = dw_mci_execute_tuning,
1236         .card_busy              = dw_mci_card_busy,
1237         .start_signal_voltage_switch = dw_mci_switch_voltage,
1238
1239 };
1240
1241 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1242         __releases(&host->lock)
1243         __acquires(&host->lock)
1244 {
1245         struct dw_mci_slot *slot;
1246         struct mmc_host *prev_mmc = host->cur_slot->mmc;
1247
1248         WARN_ON(host->cmd || host->data);
1249
1250         host->cur_slot->mrq = NULL;
1251         host->mrq = NULL;
1252         if (!list_empty(&host->queue)) {
1253                 slot = list_entry(host->queue.next,
1254                                   struct dw_mci_slot, queue_node);
1255                 list_del(&slot->queue_node);
1256                 dev_vdbg(host->dev, "list not empty: %s is next\n",
1257                          mmc_hostname(slot->mmc));
1258                 host->state = STATE_SENDING_CMD;
1259                 dw_mci_start_request(host, slot);
1260         } else {
1261                 dev_vdbg(host->dev, "list empty\n");
1262
1263                 if (host->state == STATE_SENDING_CMD11)
1264                         host->state = STATE_WAITING_CMD11_DONE;
1265                 else
1266                         host->state = STATE_IDLE;
1267         }
1268
1269         spin_unlock(&host->lock);
1270         mmc_request_done(prev_mmc, mrq);
1271         spin_lock(&host->lock);
1272 }
1273
1274 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1275 {
1276         u32 status = host->cmd_status;
1277
1278         host->cmd_status = 0;
1279
1280         /* Read the response from the card (up to 16 bytes) */
1281         if (cmd->flags & MMC_RSP_PRESENT) {
1282                 if (cmd->flags & MMC_RSP_136) {
1283                         cmd->resp[3] = mci_readl(host, RESP0);
1284                         cmd->resp[2] = mci_readl(host, RESP1);
1285                         cmd->resp[1] = mci_readl(host, RESP2);
1286                         cmd->resp[0] = mci_readl(host, RESP3);
1287                 } else {
1288                         cmd->resp[0] = mci_readl(host, RESP0);
1289                         cmd->resp[1] = 0;
1290                         cmd->resp[2] = 0;
1291                         cmd->resp[3] = 0;
1292                 }
1293         }
1294
1295         if (status & SDMMC_INT_RTO)
1296                 cmd->error = -ETIMEDOUT;
1297         else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1298                 cmd->error = -EILSEQ;
1299         else if (status & SDMMC_INT_RESP_ERR)
1300                 cmd->error = -EIO;
1301         else
1302                 cmd->error = 0;
1303
1304         if (cmd->error) {
1305                 /* newer ip versions need a delay between retries */
1306                 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
1307                         mdelay(20);
1308         }
1309
1310         return cmd->error;
1311 }
1312
1313 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1314 {
1315         u32 status = host->data_status;
1316
1317         if (status & DW_MCI_DATA_ERROR_FLAGS) {
1318                 if (status & SDMMC_INT_DRTO) {
1319                         data->error = -ETIMEDOUT;
1320                 } else if (status & SDMMC_INT_DCRC) {
1321                         data->error = -EILSEQ;
1322                 } else if (status & SDMMC_INT_EBE) {
1323                         if (host->dir_status ==
1324                                 DW_MCI_SEND_STATUS) {
1325                                 /*
1326                                  * No data CRC status was returned.
1327                                  * The number of bytes transferred
1328                                  * will be exaggerated in PIO mode.
1329                                  */
1330                                 data->bytes_xfered = 0;
1331                                 data->error = -ETIMEDOUT;
1332                         } else if (host->dir_status ==
1333                                         DW_MCI_RECV_STATUS) {
1334                                 data->error = -EIO;
1335                         }
1336                 } else {
1337                         /* SDMMC_INT_SBE is included */
1338                         data->error = -EIO;
1339                 }
1340
1341                 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1342
1343                 /*
1344                  * After an error, there may be data lingering
1345                  * in the FIFO
1346                  */
1347                 dw_mci_reset(host);
1348         } else {
1349                 data->bytes_xfered = data->blocks * data->blksz;
1350                 data->error = 0;
1351         }
1352
1353         return data->error;
1354 }
1355
1356 static void dw_mci_tasklet_func(unsigned long priv)
1357 {
1358         struct dw_mci *host = (struct dw_mci *)priv;
1359         struct mmc_data *data;
1360         struct mmc_command *cmd;
1361         struct mmc_request *mrq;
1362         enum dw_mci_state state;
1363         enum dw_mci_state prev_state;
1364         unsigned int err;
1365
1366         spin_lock(&host->lock);
1367
1368         state = host->state;
1369         data = host->data;
1370         mrq = host->mrq;
1371
1372         do {
1373                 prev_state = state;
1374
1375                 switch (state) {
1376                 case STATE_IDLE:
1377                 case STATE_WAITING_CMD11_DONE:
1378                         break;
1379
1380                 case STATE_SENDING_CMD11:
1381                 case STATE_SENDING_CMD:
1382                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1383                                                 &host->pending_events))
1384                                 break;
1385
1386                         cmd = host->cmd;
1387                         host->cmd = NULL;
1388                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1389                         err = dw_mci_command_complete(host, cmd);
1390                         if (cmd == mrq->sbc && !err) {
1391                                 prev_state = state = STATE_SENDING_CMD;
1392                                 __dw_mci_start_request(host, host->cur_slot,
1393                                                        mrq->cmd);
1394                                 goto unlock;
1395                         }
1396
1397                         if (cmd->data && err) {
1398                                 dw_mci_stop_dma(host);
1399                                 send_stop_abort(host, data);
1400                                 state = STATE_SENDING_STOP;
1401                                 break;
1402                         }
1403
1404                         if (!cmd->data || err) {
1405                                 dw_mci_request_end(host, mrq);
1406                                 goto unlock;
1407                         }
1408
1409                         prev_state = state = STATE_SENDING_DATA;
1410                         /* fall through */
1411
1412                 case STATE_SENDING_DATA:
1413                         /*
1414                          * We could get a data error and never a transfer
1415                          * complete so we'd better check for it here.
1416                          *
1417                          * Note that we don't really care if we also got a
1418                          * transfer complete; stopping the DMA and sending an
1419                          * abort won't hurt.
1420                          */
1421                         if (test_and_clear_bit(EVENT_DATA_ERROR,
1422                                                &host->pending_events)) {
1423                                 dw_mci_stop_dma(host);
1424                                 send_stop_abort(host, data);
1425                                 state = STATE_DATA_ERROR;
1426                                 break;
1427                         }
1428
1429                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1430                                                 &host->pending_events))
1431                                 break;
1432
1433                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1434
1435                         /*
1436                          * Handle an EVENT_DATA_ERROR that might have shown up
1437                          * before the transfer completed.  This might not have
1438                          * been caught by the check above because the interrupt
1439                          * could have gone off between the previous check and
1440                          * the check for transfer complete.
1441                          *
1442                          * Technically this ought not be needed assuming we
1443                          * get a DATA_COMPLETE eventually (we'll notice the
1444                          * error and end the request), but it shouldn't hurt.
1445                          *
1446                          * This has the advantage of sending the stop command.
1447                          */
1448                         if (test_and_clear_bit(EVENT_DATA_ERROR,
1449                                                &host->pending_events)) {
1450                                 dw_mci_stop_dma(host);
1451                                 send_stop_abort(host, data);
1452                                 state = STATE_DATA_ERROR;
1453                                 break;
1454                         }
1455                         prev_state = state = STATE_DATA_BUSY;
1456
1457                         /* fall through */
1458
1459                 case STATE_DATA_BUSY:
1460                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1461                                                 &host->pending_events))
1462                                 break;
1463
1464                         host->data = NULL;
1465                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1466                         err = dw_mci_data_complete(host, data);
1467
1468                         if (!err) {
1469                                 if (!data->stop || mrq->sbc) {
1470                                         if (mrq->sbc && data->stop)
1471                                                 data->stop->error = 0;
1472                                         dw_mci_request_end(host, mrq);
1473                                         goto unlock;
1474                                 }
1475
1476                                 /* stop command for open-ended transfer*/
1477                                 if (data->stop)
1478                                         send_stop_abort(host, data);
1479                         } else {
1480                                 /*
1481                                  * If we don't have a command complete now we'll
1482                                  * never get one since we just reset everything;
1483                                  * better end the request.
1484                                  *
1485                                  * If we do have a command complete we'll fall
1486                                  * through to the SENDING_STOP command and
1487                                  * everything will be peachy keen.
1488                                  */
1489                                 if (!test_bit(EVENT_CMD_COMPLETE,
1490                                               &host->pending_events)) {
1491                                         host->cmd = NULL;
1492                                         dw_mci_request_end(host, mrq);
1493                                         goto unlock;
1494                                 }
1495                         }
1496
1497                         /*
1498                          * If err has non-zero,
1499                          * stop-abort command has been already issued.
1500                          */
1501                         prev_state = state = STATE_SENDING_STOP;
1502
1503                         /* fall through */
1504
1505                 case STATE_SENDING_STOP:
1506                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1507                                                 &host->pending_events))
1508                                 break;
1509
1510                         /* CMD error in data command */
1511                         if (mrq->cmd->error && mrq->data)
1512                                 dw_mci_reset(host);
1513
1514                         host->cmd = NULL;
1515                         host->data = NULL;
1516
1517                         if (mrq->stop)
1518                                 dw_mci_command_complete(host, mrq->stop);
1519                         else
1520                                 host->cmd_status = 0;
1521
1522                         dw_mci_request_end(host, mrq);
1523                         goto unlock;
1524
1525                 case STATE_DATA_ERROR:
1526                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1527                                                 &host->pending_events))
1528                                 break;
1529
1530                         state = STATE_DATA_BUSY;
1531                         break;
1532                 }
1533         } while (state != prev_state);
1534
1535         host->state = state;
1536 unlock:
1537         spin_unlock(&host->lock);
1538
1539 }
1540
1541 /* push final bytes to part_buf, only use during push */
1542 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
1543 {
1544         memcpy((void *)&host->part_buf, buf, cnt);
1545         host->part_buf_count = cnt;
1546 }
1547
1548 /* append bytes to part_buf, only use during push */
1549 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1550 {
1551         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1552         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1553         host->part_buf_count += cnt;
1554         return cnt;
1555 }
1556
1557 /* pull first bytes from part_buf, only use during pull */
1558 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1559 {
1560         cnt = min(cnt, (int)host->part_buf_count);
1561         if (cnt) {
1562                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1563                        cnt);
1564                 host->part_buf_count -= cnt;
1565                 host->part_buf_start += cnt;
1566         }
1567         return cnt;
1568 }
1569
1570 /* pull final bytes from the part_buf, assuming it's just been filled */
1571 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
1572 {
1573         memcpy(buf, &host->part_buf, cnt);
1574         host->part_buf_start = cnt;
1575         host->part_buf_count = (1 << host->data_shift) - cnt;
1576 }
1577
1578 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1579 {
1580         struct mmc_data *data = host->data;
1581         int init_cnt = cnt;
1582
1583         /* try and push anything in the part_buf */
1584         if (unlikely(host->part_buf_count)) {
1585                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1586                 buf += len;
1587                 cnt -= len;
1588                 if (host->part_buf_count == 2) {
1589                         mci_writew(host, DATA(host->data_offset),
1590                                         host->part_buf16);
1591                         host->part_buf_count = 0;
1592                 }
1593         }
1594 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1595         if (unlikely((unsigned long)buf & 0x1)) {
1596                 while (cnt >= 2) {
1597                         u16 aligned_buf[64];
1598                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
1599                         int items = len >> 1;
1600                         int i;
1601                         /* memcpy from input buffer into aligned buffer */
1602                         memcpy(aligned_buf, buf, len);
1603                         buf += len;
1604                         cnt -= len;
1605                         /* push data from aligned buffer into fifo */
1606                         for (i = 0; i < items; ++i)
1607                                 mci_writew(host, DATA(host->data_offset),
1608                                                 aligned_buf[i]);
1609                 }
1610         } else
1611 #endif
1612         {
1613                 u16 *pdata = buf;
1614                 for (; cnt >= 2; cnt -= 2)
1615                         mci_writew(host, DATA(host->data_offset), *pdata++);
1616                 buf = pdata;
1617         }
1618         /* put anything remaining in the part_buf */
1619         if (cnt) {
1620                 dw_mci_set_part_bytes(host, buf, cnt);
1621                  /* Push data if we have reached the expected data length */
1622                 if ((data->bytes_xfered + init_cnt) ==
1623                     (data->blksz * data->blocks))
1624                         mci_writew(host, DATA(host->data_offset),
1625                                    host->part_buf16);
1626         }
1627 }
1628
1629 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1630 {
1631 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1632         if (unlikely((unsigned long)buf & 0x1)) {
1633                 while (cnt >= 2) {
1634                         /* pull data from fifo into aligned buffer */
1635                         u16 aligned_buf[64];
1636                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
1637                         int items = len >> 1;
1638                         int i;
1639                         for (i = 0; i < items; ++i)
1640                                 aligned_buf[i] = mci_readw(host,
1641                                                 DATA(host->data_offset));
1642                         /* memcpy from aligned buffer into output buffer */
1643                         memcpy(buf, aligned_buf, len);
1644                         buf += len;
1645                         cnt -= len;
1646                 }
1647         } else
1648 #endif
1649         {
1650                 u16 *pdata = buf;
1651                 for (; cnt >= 2; cnt -= 2)
1652                         *pdata++ = mci_readw(host, DATA(host->data_offset));
1653                 buf = pdata;
1654         }
1655         if (cnt) {
1656                 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
1657                 dw_mci_pull_final_bytes(host, buf, cnt);
1658         }
1659 }
1660
1661 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
1662 {
1663         struct mmc_data *data = host->data;
1664         int init_cnt = cnt;
1665
1666         /* try and push anything in the part_buf */
1667         if (unlikely(host->part_buf_count)) {
1668                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1669                 buf += len;
1670                 cnt -= len;
1671                 if (host->part_buf_count == 4) {
1672                         mci_writel(host, DATA(host->data_offset),
1673                                         host->part_buf32);
1674                         host->part_buf_count = 0;
1675                 }
1676         }
1677 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1678         if (unlikely((unsigned long)buf & 0x3)) {
1679                 while (cnt >= 4) {
1680                         u32 aligned_buf[32];
1681                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
1682                         int items = len >> 2;
1683                         int i;
1684                         /* memcpy from input buffer into aligned buffer */
1685                         memcpy(aligned_buf, buf, len);
1686                         buf += len;
1687                         cnt -= len;
1688                         /* push data from aligned buffer into fifo */
1689                         for (i = 0; i < items; ++i)
1690                                 mci_writel(host, DATA(host->data_offset),
1691                                                 aligned_buf[i]);
1692                 }
1693         } else
1694 #endif
1695         {
1696                 u32 *pdata = buf;
1697                 for (; cnt >= 4; cnt -= 4)
1698                         mci_writel(host, DATA(host->data_offset), *pdata++);
1699                 buf = pdata;
1700         }
1701         /* put anything remaining in the part_buf */
1702         if (cnt) {
1703                 dw_mci_set_part_bytes(host, buf, cnt);
1704                  /* Push data if we have reached the expected data length */
1705                 if ((data->bytes_xfered + init_cnt) ==
1706                     (data->blksz * data->blocks))
1707                         mci_writel(host, DATA(host->data_offset),
1708                                    host->part_buf32);
1709         }
1710 }
1711
1712 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
1713 {
1714 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1715         if (unlikely((unsigned long)buf & 0x3)) {
1716                 while (cnt >= 4) {
1717                         /* pull data from fifo into aligned buffer */
1718                         u32 aligned_buf[32];
1719                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
1720                         int items = len >> 2;
1721                         int i;
1722                         for (i = 0; i < items; ++i)
1723                                 aligned_buf[i] = mci_readl(host,
1724                                                 DATA(host->data_offset));
1725                         /* memcpy from aligned buffer into output buffer */
1726                         memcpy(buf, aligned_buf, len);
1727                         buf += len;
1728                         cnt -= len;
1729                 }
1730         } else
1731 #endif
1732         {
1733                 u32 *pdata = buf;
1734                 for (; cnt >= 4; cnt -= 4)
1735                         *pdata++ = mci_readl(host, DATA(host->data_offset));
1736                 buf = pdata;
1737         }
1738         if (cnt) {
1739                 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
1740                 dw_mci_pull_final_bytes(host, buf, cnt);
1741         }
1742 }
1743
1744 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1745 {
1746         struct mmc_data *data = host->data;
1747         int init_cnt = cnt;
1748
1749         /* try and push anything in the part_buf */
1750         if (unlikely(host->part_buf_count)) {
1751                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1752                 buf += len;
1753                 cnt -= len;
1754
1755                 if (host->part_buf_count == 8) {
1756                         mci_writeq(host, DATA(host->data_offset),
1757                                         host->part_buf);
1758                         host->part_buf_count = 0;
1759                 }
1760         }
1761 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1762         if (unlikely((unsigned long)buf & 0x7)) {
1763                 while (cnt >= 8) {
1764                         u64 aligned_buf[16];
1765                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
1766                         int items = len >> 3;
1767                         int i;
1768                         /* memcpy from input buffer into aligned buffer */
1769                         memcpy(aligned_buf, buf, len);
1770                         buf += len;
1771                         cnt -= len;
1772                         /* push data from aligned buffer into fifo */
1773                         for (i = 0; i < items; ++i)
1774                                 mci_writeq(host, DATA(host->data_offset),
1775                                                 aligned_buf[i]);
1776                 }
1777         } else
1778 #endif
1779         {
1780                 u64 *pdata = buf;
1781                 for (; cnt >= 8; cnt -= 8)
1782                         mci_writeq(host, DATA(host->data_offset), *pdata++);
1783                 buf = pdata;
1784         }
1785         /* put anything remaining in the part_buf */
1786         if (cnt) {
1787                 dw_mci_set_part_bytes(host, buf, cnt);
1788                 /* Push data if we have reached the expected data length */
1789                 if ((data->bytes_xfered + init_cnt) ==
1790                     (data->blksz * data->blocks))
1791                         mci_writeq(host, DATA(host->data_offset),
1792                                    host->part_buf);
1793         }
1794 }
1795
1796 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1797 {
1798 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1799         if (unlikely((unsigned long)buf & 0x7)) {
1800                 while (cnt >= 8) {
1801                         /* pull data from fifo into aligned buffer */
1802                         u64 aligned_buf[16];
1803                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
1804                         int items = len >> 3;
1805                         int i;
1806                         for (i = 0; i < items; ++i)
1807                                 aligned_buf[i] = mci_readq(host,
1808                                                 DATA(host->data_offset));
1809                         /* memcpy from aligned buffer into output buffer */
1810                         memcpy(buf, aligned_buf, len);
1811                         buf += len;
1812                         cnt -= len;
1813                 }
1814         } else
1815 #endif
1816         {
1817                 u64 *pdata = buf;
1818                 for (; cnt >= 8; cnt -= 8)
1819                         *pdata++ = mci_readq(host, DATA(host->data_offset));
1820                 buf = pdata;
1821         }
1822         if (cnt) {
1823                 host->part_buf = mci_readq(host, DATA(host->data_offset));
1824                 dw_mci_pull_final_bytes(host, buf, cnt);
1825         }
1826 }
1827
1828 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
1829 {
1830         int len;
1831
1832         /* get remaining partial bytes */
1833         len = dw_mci_pull_part_bytes(host, buf, cnt);
1834         if (unlikely(len == cnt))
1835                 return;
1836         buf += len;
1837         cnt -= len;
1838
1839         /* get the rest of the data */
1840         host->pull_data(host, buf, cnt);
1841 }
1842
1843 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
1844 {
1845         struct sg_mapping_iter *sg_miter = &host->sg_miter;
1846         void *buf;
1847         unsigned int offset;
1848         struct mmc_data *data = host->data;
1849         int shift = host->data_shift;
1850         u32 status;
1851         unsigned int len;
1852         unsigned int remain, fcnt;
1853
1854         do {
1855                 if (!sg_miter_next(sg_miter))
1856                         goto done;
1857
1858                 host->sg = sg_miter->piter.sg;
1859                 buf = sg_miter->addr;
1860                 remain = sg_miter->length;
1861                 offset = 0;
1862
1863                 do {
1864                         fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
1865                                         << shift) + host->part_buf_count;
1866                         len = min(remain, fcnt);
1867                         if (!len)
1868                                 break;
1869                         dw_mci_pull_data(host, (void *)(buf + offset), len);
1870                         data->bytes_xfered += len;
1871                         offset += len;
1872                         remain -= len;
1873                 } while (remain);
1874
1875                 sg_miter->consumed = offset;
1876                 status = mci_readl(host, MINTSTS);
1877                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1878         /* if the RXDR is ready read again */
1879         } while ((status & SDMMC_INT_RXDR) ||
1880                  (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
1881
1882         if (!remain) {
1883                 if (!sg_miter_next(sg_miter))
1884                         goto done;
1885                 sg_miter->consumed = 0;
1886         }
1887         sg_miter_stop(sg_miter);
1888         return;
1889
1890 done:
1891         sg_miter_stop(sg_miter);
1892         host->sg = NULL;
1893         smp_wmb();
1894         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1895 }
1896
1897 static void dw_mci_write_data_pio(struct dw_mci *host)
1898 {
1899         struct sg_mapping_iter *sg_miter = &host->sg_miter;
1900         void *buf;
1901         unsigned int offset;
1902         struct mmc_data *data = host->data;
1903         int shift = host->data_shift;
1904         u32 status;
1905         unsigned int len;
1906         unsigned int fifo_depth = host->fifo_depth;
1907         unsigned int remain, fcnt;
1908
1909         do {
1910                 if (!sg_miter_next(sg_miter))
1911                         goto done;
1912
1913                 host->sg = sg_miter->piter.sg;
1914                 buf = sg_miter->addr;
1915                 remain = sg_miter->length;
1916                 offset = 0;
1917
1918                 do {
1919                         fcnt = ((fifo_depth -
1920                                  SDMMC_GET_FCNT(mci_readl(host, STATUS)))
1921                                         << shift) - host->part_buf_count;
1922                         len = min(remain, fcnt);
1923                         if (!len)
1924                                 break;
1925                         host->push_data(host, (void *)(buf + offset), len);
1926                         data->bytes_xfered += len;
1927                         offset += len;
1928                         remain -= len;
1929                 } while (remain);
1930
1931                 sg_miter->consumed = offset;
1932                 status = mci_readl(host, MINTSTS);
1933                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1934         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
1935
1936         if (!remain) {
1937                 if (!sg_miter_next(sg_miter))
1938                         goto done;
1939                 sg_miter->consumed = 0;
1940         }
1941         sg_miter_stop(sg_miter);
1942         return;
1943
1944 done:
1945         sg_miter_stop(sg_miter);
1946         host->sg = NULL;
1947         smp_wmb();
1948         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1949 }
1950
1951 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
1952 {
1953         if (!host->cmd_status)
1954                 host->cmd_status = status;
1955
1956         smp_wmb();
1957
1958         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1959         tasklet_schedule(&host->tasklet);
1960 }
1961
1962 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
1963 {
1964         struct dw_mci *host = dev_id;
1965         u32 pending;
1966         int i;
1967
1968         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
1969
1970         /*
1971          * DTO fix - version 2.10a and below, and only if internal DMA
1972          * is configured.
1973          */
1974         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
1975                 if (!pending &&
1976                     ((mci_readl(host, STATUS) >> 17) & 0x1fff))
1977                         pending |= SDMMC_INT_DATA_OVER;
1978         }
1979
1980         if (pending) {
1981                 /* Check volt switch first, since it can look like an error */
1982                 if ((host->state == STATE_SENDING_CMD11) &&
1983                     (pending & SDMMC_INT_VOLT_SWITCH)) {
1984                         mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
1985                         pending &= ~SDMMC_INT_VOLT_SWITCH;
1986                         dw_mci_cmd_interrupt(host, pending);
1987                 }
1988
1989                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
1990                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
1991                         host->cmd_status = pending;
1992                         smp_wmb();
1993                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1994                 }
1995
1996                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
1997                         /* if there is an error report DATA_ERROR */
1998                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
1999                         host->data_status = pending;
2000                         smp_wmb();
2001                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
2002                         tasklet_schedule(&host->tasklet);
2003                 }
2004
2005                 if (pending & SDMMC_INT_DATA_OVER) {
2006                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2007                         if (!host->data_status)
2008                                 host->data_status = pending;
2009                         smp_wmb();
2010                         if (host->dir_status == DW_MCI_RECV_STATUS) {
2011                                 if (host->sg != NULL)
2012                                         dw_mci_read_data_pio(host, true);
2013                         }
2014                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2015                         tasklet_schedule(&host->tasklet);
2016                 }
2017
2018                 if (pending & SDMMC_INT_RXDR) {
2019                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2020                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2021                                 dw_mci_read_data_pio(host, false);
2022                 }
2023
2024                 if (pending & SDMMC_INT_TXDR) {
2025                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2026                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2027                                 dw_mci_write_data_pio(host);
2028                 }
2029
2030                 if (pending & SDMMC_INT_CMD_DONE) {
2031                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2032                         dw_mci_cmd_interrupt(host, pending);
2033                 }
2034
2035                 if (pending & SDMMC_INT_CD) {
2036                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
2037                         queue_work(host->card_workqueue, &host->card_work);
2038                 }
2039
2040                 /* Handle SDIO Interrupts */
2041                 for (i = 0; i < host->num_slots; i++) {
2042                         struct dw_mci_slot *slot = host->slot[i];
2043                         if (pending & SDMMC_INT_SDIO(i)) {
2044                                 mci_writel(host, RINTSTS, SDMMC_INT_SDIO(i));
2045                                 mmc_signal_sdio_irq(slot->mmc);
2046                         }
2047                 }
2048
2049         }
2050
2051 #ifdef CONFIG_MMC_DW_IDMAC
2052         /* Handle DMA interrupts */
2053         pending = mci_readl(host, IDSTS);
2054         if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2055                 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
2056                 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2057                 host->dma_ops->complete(host);
2058         }
2059 #endif
2060
2061         return IRQ_HANDLED;
2062 }
2063
2064 static void dw_mci_work_routine_card(struct work_struct *work)
2065 {
2066         struct dw_mci *host = container_of(work, struct dw_mci, card_work);
2067         int i;
2068
2069         for (i = 0; i < host->num_slots; i++) {
2070                 struct dw_mci_slot *slot = host->slot[i];
2071                 struct mmc_host *mmc = slot->mmc;
2072                 struct mmc_request *mrq;
2073                 int present;
2074
2075                 present = dw_mci_get_cd(mmc);
2076                 while (present != slot->last_detect_state) {
2077                         dev_dbg(&slot->mmc->class_dev, "card %s\n",
2078                                 present ? "inserted" : "removed");
2079
2080                         spin_lock_bh(&host->lock);
2081
2082                         /* Card change detected */
2083                         slot->last_detect_state = present;
2084
2085                         /* Clean up queue if present */
2086                         mrq = slot->mrq;
2087                         if (mrq) {
2088                                 if (mrq == host->mrq) {
2089                                         host->data = NULL;
2090                                         host->cmd = NULL;
2091
2092                                         switch (host->state) {
2093                                         case STATE_IDLE:
2094                                         case STATE_WAITING_CMD11_DONE:
2095                                                 break;
2096                                         case STATE_SENDING_CMD11:
2097                                         case STATE_SENDING_CMD:
2098                                                 mrq->cmd->error = -ENOMEDIUM;
2099                                                 if (!mrq->data)
2100                                                         break;
2101                                                 /* fall through */
2102                                         case STATE_SENDING_DATA:
2103                                                 mrq->data->error = -ENOMEDIUM;
2104                                                 dw_mci_stop_dma(host);
2105                                                 break;
2106                                         case STATE_DATA_BUSY:
2107                                         case STATE_DATA_ERROR:
2108                                                 if (mrq->data->error == -EINPROGRESS)
2109                                                         mrq->data->error = -ENOMEDIUM;
2110                                                 /* fall through */
2111                                         case STATE_SENDING_STOP:
2112                                                 if (mrq->stop)
2113                                                         mrq->stop->error = -ENOMEDIUM;
2114                                                 break;
2115                                         }
2116
2117                                         dw_mci_request_end(host, mrq);
2118                                 } else {
2119                                         list_del(&slot->queue_node);
2120                                         mrq->cmd->error = -ENOMEDIUM;
2121                                         if (mrq->data)
2122                                                 mrq->data->error = -ENOMEDIUM;
2123                                         if (mrq->stop)
2124                                                 mrq->stop->error = -ENOMEDIUM;
2125
2126                                         spin_unlock(&host->lock);
2127                                         mmc_request_done(slot->mmc, mrq);
2128                                         spin_lock(&host->lock);
2129                                 }
2130                         }
2131
2132                         /* Power down slot */
2133                         if (present == 0)
2134                                 dw_mci_reset(host);
2135
2136                         spin_unlock_bh(&host->lock);
2137
2138                         present = dw_mci_get_cd(mmc);
2139                 }
2140
2141                 mmc_detect_change(slot->mmc,
2142                         msecs_to_jiffies(host->pdata->detect_delay_ms));
2143         }
2144 }
2145
2146 #ifdef CONFIG_OF
2147 /* given a slot id, find out the device node representing that slot */
2148 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
2149 {
2150         struct device_node *np;
2151         const __be32 *addr;
2152         int len;
2153
2154         if (!dev || !dev->of_node)
2155                 return NULL;
2156
2157         for_each_child_of_node(dev->of_node, np) {
2158                 addr = of_get_property(np, "reg", &len);
2159                 if (!addr || (len < sizeof(int)))
2160                         continue;
2161                 if (be32_to_cpup(addr) == slot)
2162                         return np;
2163         }
2164         return NULL;
2165 }
2166
2167 static struct dw_mci_of_slot_quirks {
2168         char *quirk;
2169         int id;
2170 } of_slot_quirks[] = {
2171         {
2172                 .quirk  = "disable-wp",
2173                 .id     = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
2174         },
2175 };
2176
2177 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
2178 {
2179         struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
2180         int quirks = 0;
2181         int idx;
2182
2183         /* get quirks */
2184         for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++)
2185                 if (of_get_property(np, of_slot_quirks[idx].quirk, NULL)) {
2186                         dev_warn(dev, "Slot quirk %s is deprecated\n",
2187                                         of_slot_quirks[idx].quirk);
2188                         quirks |= of_slot_quirks[idx].id;
2189                 }
2190
2191         return quirks;
2192 }
2193 #else /* CONFIG_OF */
2194 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
2195 {
2196         return 0;
2197 }
2198 #endif /* CONFIG_OF */
2199
2200 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
2201 {
2202         struct mmc_host *mmc;
2203         struct dw_mci_slot *slot;
2204         const struct dw_mci_drv_data *drv_data = host->drv_data;
2205         int ctrl_id, ret;
2206         u32 freq[2];
2207
2208         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2209         if (!mmc)
2210                 return -ENOMEM;
2211
2212         slot = mmc_priv(mmc);
2213         slot->id = id;
2214         slot->mmc = mmc;
2215         slot->host = host;
2216         host->slot[id] = slot;
2217
2218         slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id);
2219
2220         mmc->ops = &dw_mci_ops;
2221         if (of_property_read_u32_array(host->dev->of_node,
2222                                        "clock-freq-min-max", freq, 2)) {
2223                 mmc->f_min = DW_MCI_FREQ_MIN;
2224                 mmc->f_max = DW_MCI_FREQ_MAX;
2225         } else {
2226                 mmc->f_min = freq[0];
2227                 mmc->f_max = freq[1];
2228         }
2229
2230         /*if there are external regulators, get them*/
2231         ret = mmc_regulator_get_supply(mmc);
2232         if (ret == -EPROBE_DEFER)
2233                 goto err_host_allocated;
2234
2235         if (!mmc->ocr_avail)
2236                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2237
2238         if (host->pdata->caps)
2239                 mmc->caps = host->pdata->caps;
2240
2241         if (host->pdata->pm_caps)
2242                 mmc->pm_caps = host->pdata->pm_caps;
2243
2244         if (host->dev->of_node) {
2245                 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2246                 if (ctrl_id < 0)
2247                         ctrl_id = 0;
2248         } else {
2249                 ctrl_id = to_platform_device(host->dev)->id;
2250         }
2251         if (drv_data && drv_data->caps)
2252                 mmc->caps |= drv_data->caps[ctrl_id];
2253
2254         if (host->pdata->caps2)
2255                 mmc->caps2 = host->pdata->caps2;
2256
2257         ret = mmc_of_parse(mmc);
2258         if (ret)
2259                 goto err_host_allocated;
2260
2261         if (host->pdata->blk_settings) {
2262                 mmc->max_segs = host->pdata->blk_settings->max_segs;
2263                 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
2264                 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
2265                 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
2266                 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
2267         } else {
2268                 /* Useful defaults if platform data is unset. */
2269 #ifdef CONFIG_MMC_DW_IDMAC
2270                 mmc->max_segs = host->ring_size;
2271                 mmc->max_blk_size = 65536;
2272                 mmc->max_blk_count = host->ring_size;
2273                 mmc->max_seg_size = 0x1000;
2274                 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
2275 #else
2276                 mmc->max_segs = 64;
2277                 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
2278                 mmc->max_blk_count = 512;
2279                 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2280                 mmc->max_seg_size = mmc->max_req_size;
2281 #endif /* CONFIG_MMC_DW_IDMAC */
2282         }
2283
2284         if (dw_mci_get_cd(mmc))
2285                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2286         else
2287                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2288
2289         ret = mmc_add_host(mmc);
2290         if (ret)
2291                 goto err_host_allocated;
2292
2293 #if defined(CONFIG_DEBUG_FS)
2294         dw_mci_init_debugfs(slot);
2295 #endif
2296
2297         /* Card initially undetected */
2298         slot->last_detect_state = 0;
2299
2300         return 0;
2301
2302 err_host_allocated:
2303         mmc_free_host(mmc);
2304         return ret;
2305 }
2306
2307 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2308 {
2309         /* Debugfs stuff is cleaned up by mmc core */
2310         mmc_remove_host(slot->mmc);
2311         slot->host->slot[id] = NULL;
2312         mmc_free_host(slot->mmc);
2313 }
2314
2315 static void dw_mci_init_dma(struct dw_mci *host)
2316 {
2317         /* Alloc memory for sg translation */
2318         host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
2319                                           &host->sg_dma, GFP_KERNEL);
2320         if (!host->sg_cpu) {
2321                 dev_err(host->dev, "%s: could not alloc DMA memory\n",
2322                         __func__);
2323                 goto no_dma;
2324         }
2325
2326         /* Determine which DMA interface to use */
2327 #ifdef CONFIG_MMC_DW_IDMAC
2328         host->dma_ops = &dw_mci_idmac_ops;
2329         dev_info(host->dev, "Using internal DMA controller.\n");
2330 #endif
2331
2332         if (!host->dma_ops)
2333                 goto no_dma;
2334
2335         if (host->dma_ops->init && host->dma_ops->start &&
2336             host->dma_ops->stop && host->dma_ops->cleanup) {
2337                 if (host->dma_ops->init(host)) {
2338                         dev_err(host->dev, "%s: Unable to initialize "
2339                                 "DMA Controller.\n", __func__);
2340                         goto no_dma;
2341                 }
2342         } else {
2343                 dev_err(host->dev, "DMA initialization not found.\n");
2344                 goto no_dma;
2345         }
2346
2347         host->use_dma = 1;
2348         return;
2349
2350 no_dma:
2351         dev_info(host->dev, "Using PIO mode.\n");
2352         host->use_dma = 0;
2353         return;
2354 }
2355
2356 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
2357 {
2358         unsigned long timeout = jiffies + msecs_to_jiffies(500);
2359         u32 ctrl;
2360
2361         ctrl = mci_readl(host, CTRL);
2362         ctrl |= reset;
2363         mci_writel(host, CTRL, ctrl);
2364
2365         /* wait till resets clear */
2366         do {
2367                 ctrl = mci_readl(host, CTRL);
2368                 if (!(ctrl & reset))
2369                         return true;
2370         } while (time_before(jiffies, timeout));
2371
2372         dev_err(host->dev,
2373                 "Timeout resetting block (ctrl reset %#x)\n",
2374                 ctrl & reset);
2375
2376         return false;
2377 }
2378
2379 static bool dw_mci_reset(struct dw_mci *host)
2380 {
2381         u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
2382         bool ret = false;
2383
2384         /*
2385          * Reseting generates a block interrupt, hence setting
2386          * the scatter-gather pointer to NULL.
2387          */
2388         if (host->sg) {
2389                 sg_miter_stop(&host->sg_miter);
2390                 host->sg = NULL;
2391         }
2392
2393         if (host->use_dma)
2394                 flags |= SDMMC_CTRL_DMA_RESET;
2395
2396         if (dw_mci_ctrl_reset(host, flags)) {
2397                 /*
2398                  * In all cases we clear the RAWINTS register to clear any
2399                  * interrupts.
2400                  */
2401                 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2402
2403                 /* if using dma we wait for dma_req to clear */
2404                 if (host->use_dma) {
2405                         unsigned long timeout = jiffies + msecs_to_jiffies(500);
2406                         u32 status;
2407                         do {
2408                                 status = mci_readl(host, STATUS);
2409                                 if (!(status & SDMMC_STATUS_DMA_REQ))
2410                                         break;
2411                                 cpu_relax();
2412                         } while (time_before(jiffies, timeout));
2413
2414                         if (status & SDMMC_STATUS_DMA_REQ) {
2415                                 dev_err(host->dev,
2416                                         "%s: Timeout waiting for dma_req to "
2417                                         "clear during reset\n", __func__);
2418                                 goto ciu_out;
2419                         }
2420
2421                         /* when using DMA next we reset the fifo again */
2422                         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2423                                 goto ciu_out;
2424                 }
2425         } else {
2426                 /* if the controller reset bit did clear, then set clock regs */
2427                 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
2428                         dev_err(host->dev, "%s: fifo/dma reset bits didn't "
2429                                 "clear but ciu was reset, doing clock update\n",
2430                                 __func__);
2431                         goto ciu_out;
2432                 }
2433         }
2434
2435 #if IS_ENABLED(CONFIG_MMC_DW_IDMAC)
2436         /* It is also recommended that we reset and reprogram idmac */
2437         dw_mci_idmac_reset(host);
2438 #endif
2439
2440         ret = true;
2441
2442 ciu_out:
2443         /* After a CTRL reset we need to have CIU set clock registers  */
2444         mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2445
2446         return ret;
2447 }
2448
2449 #ifdef CONFIG_OF
2450 static struct dw_mci_of_quirks {
2451         char *quirk;
2452         int id;
2453 } of_quirks[] = {
2454         {
2455                 .quirk  = "broken-cd",
2456                 .id     = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
2457         }, {
2458                 .quirk  = "disable-wp",
2459                 .id     = DW_MCI_QUIRK_NO_WRITE_PROTECT,
2460         },
2461 };
2462
2463 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2464 {
2465         struct dw_mci_board *pdata;
2466         struct device *dev = host->dev;
2467         struct device_node *np = dev->of_node;
2468         const struct dw_mci_drv_data *drv_data = host->drv_data;
2469         int idx, ret;
2470         u32 clock_frequency;
2471
2472         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2473         if (!pdata) {
2474                 dev_err(dev, "could not allocate memory for pdata\n");
2475                 return ERR_PTR(-ENOMEM);
2476         }
2477
2478         /* find out number of slots supported */
2479         if (of_property_read_u32(dev->of_node, "num-slots",
2480                                 &pdata->num_slots)) {
2481                 dev_info(dev, "num-slots property not found, "
2482                                 "assuming 1 slot is available\n");
2483                 pdata->num_slots = 1;
2484         }
2485
2486         /* get quirks */
2487         for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
2488                 if (of_get_property(np, of_quirks[idx].quirk, NULL))
2489                         pdata->quirks |= of_quirks[idx].id;
2490
2491         if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
2492                 dev_info(dev, "fifo-depth property not found, using "
2493                                 "value of FIFOTH register as default\n");
2494
2495         of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2496
2497         if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
2498                 pdata->bus_hz = clock_frequency;
2499
2500         if (drv_data && drv_data->parse_dt) {
2501                 ret = drv_data->parse_dt(host);
2502                 if (ret)
2503                         return ERR_PTR(ret);
2504         }
2505
2506         if (of_find_property(np, "supports-highspeed", NULL))
2507                 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2508
2509         return pdata;
2510 }
2511
2512 #else /* CONFIG_OF */
2513 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2514 {
2515         return ERR_PTR(-EINVAL);
2516 }
2517 #endif /* CONFIG_OF */
2518
2519 int dw_mci_probe(struct dw_mci *host)
2520 {
2521         const struct dw_mci_drv_data *drv_data = host->drv_data;
2522         int width, i, ret = 0;
2523         u32 fifo_size;
2524         int init_slots = 0;
2525
2526         if (!host->pdata) {
2527                 host->pdata = dw_mci_parse_dt(host);
2528                 if (IS_ERR(host->pdata)) {
2529                         dev_err(host->dev, "platform data not available\n");
2530                         return -EINVAL;
2531                 }
2532         }
2533
2534         if (host->pdata->num_slots > 1) {
2535                 dev_err(host->dev,
2536                         "Platform data must supply num_slots.\n");
2537                 return -ENODEV;
2538         }
2539
2540         host->biu_clk = devm_clk_get(host->dev, "biu");
2541         if (IS_ERR(host->biu_clk)) {
2542                 dev_dbg(host->dev, "biu clock not available\n");
2543         } else {
2544                 ret = clk_prepare_enable(host->biu_clk);
2545                 if (ret) {
2546                         dev_err(host->dev, "failed to enable biu clock\n");
2547                         return ret;
2548                 }
2549         }
2550
2551         host->ciu_clk = devm_clk_get(host->dev, "ciu");
2552         if (IS_ERR(host->ciu_clk)) {
2553                 dev_dbg(host->dev, "ciu clock not available\n");
2554                 host->bus_hz = host->pdata->bus_hz;
2555         } else {
2556                 ret = clk_prepare_enable(host->ciu_clk);
2557                 if (ret) {
2558                         dev_err(host->dev, "failed to enable ciu clock\n");
2559                         goto err_clk_biu;
2560                 }
2561
2562                 if (host->pdata->bus_hz) {
2563                         ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
2564                         if (ret)
2565                                 dev_warn(host->dev,
2566                                          "Unable to set bus rate to %uHz\n",
2567                                          host->pdata->bus_hz);
2568                 }
2569                 host->bus_hz = clk_get_rate(host->ciu_clk);
2570         }
2571
2572         if (!host->bus_hz) {
2573                 dev_err(host->dev,
2574                         "Platform data must supply bus speed\n");
2575                 ret = -ENODEV;
2576                 goto err_clk_ciu;
2577         }
2578
2579         if (drv_data && drv_data->init) {
2580                 ret = drv_data->init(host);
2581                 if (ret) {
2582                         dev_err(host->dev,
2583                                 "implementation specific init failed\n");
2584                         goto err_clk_ciu;
2585                 }
2586         }
2587
2588         if (drv_data && drv_data->setup_clock) {
2589                 ret = drv_data->setup_clock(host);
2590                 if (ret) {
2591                         dev_err(host->dev,
2592                                 "implementation specific clock setup failed\n");
2593                         goto err_clk_ciu;
2594                 }
2595         }
2596
2597         host->quirks = host->pdata->quirks;
2598
2599         spin_lock_init(&host->lock);
2600         INIT_LIST_HEAD(&host->queue);
2601
2602         /*
2603          * Get the host data width - this assumes that HCON has been set with
2604          * the correct values.
2605          */
2606         i = (mci_readl(host, HCON) >> 7) & 0x7;
2607         if (!i) {
2608                 host->push_data = dw_mci_push_data16;
2609                 host->pull_data = dw_mci_pull_data16;
2610                 width = 16;
2611                 host->data_shift = 1;
2612         } else if (i == 2) {
2613                 host->push_data = dw_mci_push_data64;
2614                 host->pull_data = dw_mci_pull_data64;
2615                 width = 64;
2616                 host->data_shift = 3;
2617         } else {
2618                 /* Check for a reserved value, and warn if it is */
2619                 WARN((i != 1),
2620                      "HCON reports a reserved host data width!\n"
2621                      "Defaulting to 32-bit access.\n");
2622                 host->push_data = dw_mci_push_data32;
2623                 host->pull_data = dw_mci_pull_data32;
2624                 width = 32;
2625                 host->data_shift = 2;
2626         }
2627
2628         /* Reset all blocks */
2629         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS))
2630                 return -ENODEV;
2631
2632         host->dma_ops = host->pdata->dma_ops;
2633         dw_mci_init_dma(host);
2634
2635         /* Clear the interrupts for the host controller */
2636         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2637         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2638
2639         /* Put in max timeout */
2640         mci_writel(host, TMOUT, 0xFFFFFFFF);
2641
2642         /*
2643          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
2644          *                          Tx Mark = fifo_size / 2 DMA Size = 8
2645          */
2646         if (!host->pdata->fifo_depth) {
2647                 /*
2648                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
2649                  * have been overwritten by the bootloader, just like we're
2650                  * about to do, so if you know the value for your hardware, you
2651                  * should put it in the platform data.
2652                  */
2653                 fifo_size = mci_readl(host, FIFOTH);
2654                 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
2655         } else {
2656                 fifo_size = host->pdata->fifo_depth;
2657         }
2658         host->fifo_depth = fifo_size;
2659         host->fifoth_val =
2660                 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
2661         mci_writel(host, FIFOTH, host->fifoth_val);
2662
2663         /* disable clock to CIU */
2664         mci_writel(host, CLKENA, 0);
2665         mci_writel(host, CLKSRC, 0);
2666
2667         /*
2668          * In 2.40a spec, Data offset is changed.
2669          * Need to check the version-id and set data-offset for DATA register.
2670          */
2671         host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
2672         dev_info(host->dev, "Version ID is %04x\n", host->verid);
2673
2674         if (host->verid < DW_MMC_240A)
2675                 host->data_offset = DATA_OFFSET;
2676         else
2677                 host->data_offset = DATA_240A_OFFSET;
2678
2679         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
2680         host->card_workqueue = alloc_workqueue("dw-mci-card",
2681                         WQ_MEM_RECLAIM, 1);
2682         if (!host->card_workqueue) {
2683                 ret = -ENOMEM;
2684                 goto err_dmaunmap;
2685         }
2686         INIT_WORK(&host->card_work, dw_mci_work_routine_card);
2687         ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
2688                                host->irq_flags, "dw-mci", host);
2689         if (ret)
2690                 goto err_workqueue;
2691
2692         if (host->pdata->num_slots)
2693                 host->num_slots = host->pdata->num_slots;
2694         else
2695                 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
2696
2697         /*
2698          * Enable interrupts for command done, data over, data empty, card det,
2699          * receive ready and error such as transmit, receive timeout, crc error
2700          */
2701         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2702         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2703                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2704                    DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2705         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
2706
2707         dev_info(host->dev, "DW MMC controller at irq %d, "
2708                  "%d bit host data width, "
2709                  "%u deep fifo\n",
2710                  host->irq, width, fifo_size);
2711
2712         /* We need at least one slot to succeed */
2713         for (i = 0; i < host->num_slots; i++) {
2714                 ret = dw_mci_init_slot(host, i);
2715                 if (ret)
2716                         dev_dbg(host->dev, "slot %d init failed\n", i);
2717                 else
2718                         init_slots++;
2719         }
2720
2721         if (init_slots) {
2722                 dev_info(host->dev, "%d slots initialized\n", init_slots);
2723         } else {
2724                 dev_dbg(host->dev, "attempted to initialize %d slots, "
2725                                         "but failed on all\n", host->num_slots);
2726                 goto err_workqueue;
2727         }
2728
2729         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
2730                 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
2731
2732         return 0;
2733
2734 err_workqueue:
2735         destroy_workqueue(host->card_workqueue);
2736
2737 err_dmaunmap:
2738         if (host->use_dma && host->dma_ops->exit)
2739                 host->dma_ops->exit(host);
2740
2741 err_clk_ciu:
2742         if (!IS_ERR(host->ciu_clk))
2743                 clk_disable_unprepare(host->ciu_clk);
2744
2745 err_clk_biu:
2746         if (!IS_ERR(host->biu_clk))
2747                 clk_disable_unprepare(host->biu_clk);
2748
2749         return ret;
2750 }
2751 EXPORT_SYMBOL(dw_mci_probe);
2752
2753 void dw_mci_remove(struct dw_mci *host)
2754 {
2755         int i;
2756
2757         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2758         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2759
2760         for (i = 0; i < host->num_slots; i++) {
2761                 dev_dbg(host->dev, "remove slot %d\n", i);
2762                 if (host->slot[i])
2763                         dw_mci_cleanup_slot(host->slot[i], i);
2764         }
2765
2766         /* disable clock to CIU */
2767         mci_writel(host, CLKENA, 0);
2768         mci_writel(host, CLKSRC, 0);
2769
2770         destroy_workqueue(host->card_workqueue);
2771
2772         if (host->use_dma && host->dma_ops->exit)
2773                 host->dma_ops->exit(host);
2774
2775         if (!IS_ERR(host->ciu_clk))
2776                 clk_disable_unprepare(host->ciu_clk);
2777
2778         if (!IS_ERR(host->biu_clk))
2779                 clk_disable_unprepare(host->biu_clk);
2780 }
2781 EXPORT_SYMBOL(dw_mci_remove);
2782
2783
2784
2785 #ifdef CONFIG_PM_SLEEP
2786 /*
2787  * TODO: we should probably disable the clock to the card in the suspend path.
2788  */
2789 int dw_mci_suspend(struct dw_mci *host)
2790 {
2791         return 0;
2792 }
2793 EXPORT_SYMBOL(dw_mci_suspend);
2794
2795 int dw_mci_resume(struct dw_mci *host)
2796 {
2797         int i, ret;
2798
2799         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
2800                 ret = -ENODEV;
2801                 return ret;
2802         }
2803
2804         if (host->use_dma && host->dma_ops->init)
2805                 host->dma_ops->init(host);
2806
2807         /*
2808          * Restore the initial value at FIFOTH register
2809          * And Invalidate the prev_blksz with zero
2810          */
2811         mci_writel(host, FIFOTH, host->fifoth_val);
2812         host->prev_blksz = 0;
2813
2814         /* Put in max timeout */
2815         mci_writel(host, TMOUT, 0xFFFFFFFF);
2816
2817         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2818         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2819                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2820                    DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2821         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2822
2823         for (i = 0; i < host->num_slots; i++) {
2824                 struct dw_mci_slot *slot = host->slot[i];
2825                 if (!slot)
2826                         continue;
2827                 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
2828                         dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
2829                         dw_mci_setup_bus(slot, true);
2830                 }
2831         }
2832         return 0;
2833 }
2834 EXPORT_SYMBOL(dw_mci_resume);
2835 #endif /* CONFIG_PM_SLEEP */
2836
2837 static int __init dw_mci_init(void)
2838 {
2839         pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
2840         return 0;
2841 }
2842
2843 static void __exit dw_mci_exit(void)
2844 {
2845 }
2846
2847 module_init(dw_mci_init);
2848 module_exit(dw_mci_exit);
2849
2850 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
2851 MODULE_AUTHOR("NXP Semiconductor VietNam");
2852 MODULE_AUTHOR("Imagination Technologies Ltd");
2853 MODULE_LICENSE("GPL v2");