2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/blkdev.h>
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/seq_file.h>
26 #include <linux/slab.h>
27 #include <linux/stat.h>
28 #include <linux/delay.h>
29 #include <linux/irq.h>
30 #include <linux/mmc/host.h>
31 #include <linux/mmc/mmc.h>
32 #include <linux/mmc/sd.h>
33 #include <linux/mmc/sdio.h>
34 #include <linux/mmc/dw_mmc.h>
35 #include <linux/bitops.h>
36 #include <linux/regulator/consumer.h>
37 #include <linux/workqueue.h>
39 #include <linux/of_gpio.h>
40 #include <linux/mmc/slot-gpio.h>
44 /* Common flag combinations */
45 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
46 SDMMC_INT_HTO | SDMMC_INT_SBE | \
48 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
50 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
51 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
52 #define DW_MCI_SEND_STATUS 1
53 #define DW_MCI_RECV_STATUS 2
54 #define DW_MCI_DMA_THRESHOLD 16
56 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
57 #define DW_MCI_FREQ_MIN 400000 /* unit: HZ */
59 #ifdef CONFIG_MMC_DW_IDMAC
60 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
61 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
62 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
66 u32 des0; /* Control Descriptor */
67 #define IDMAC_DES0_DIC BIT(1)
68 #define IDMAC_DES0_LD BIT(2)
69 #define IDMAC_DES0_FD BIT(3)
70 #define IDMAC_DES0_CH BIT(4)
71 #define IDMAC_DES0_ER BIT(5)
72 #define IDMAC_DES0_CES BIT(30)
73 #define IDMAC_DES0_OWN BIT(31)
75 u32 des1; /* Buffer sizes */
76 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
77 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
79 u32 des2; /* buffer 1 physical address */
81 u32 des3; /* buffer 2 physical address */
83 #endif /* CONFIG_MMC_DW_IDMAC */
85 static bool dw_mci_reset(struct dw_mci *host);
86 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
88 #if defined(CONFIG_DEBUG_FS)
89 static int dw_mci_req_show(struct seq_file *s, void *v)
91 struct dw_mci_slot *slot = s->private;
92 struct mmc_request *mrq;
93 struct mmc_command *cmd;
94 struct mmc_command *stop;
95 struct mmc_data *data;
97 /* Make sure we get a consistent snapshot */
98 spin_lock_bh(&slot->host->lock);
108 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
109 cmd->opcode, cmd->arg, cmd->flags,
110 cmd->resp[0], cmd->resp[1], cmd->resp[2],
111 cmd->resp[2], cmd->error);
113 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
114 data->bytes_xfered, data->blocks,
115 data->blksz, data->flags, data->error);
118 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
119 stop->opcode, stop->arg, stop->flags,
120 stop->resp[0], stop->resp[1], stop->resp[2],
121 stop->resp[2], stop->error);
124 spin_unlock_bh(&slot->host->lock);
129 static int dw_mci_req_open(struct inode *inode, struct file *file)
131 return single_open(file, dw_mci_req_show, inode->i_private);
134 static const struct file_operations dw_mci_req_fops = {
135 .owner = THIS_MODULE,
136 .open = dw_mci_req_open,
139 .release = single_release,
142 static int dw_mci_regs_show(struct seq_file *s, void *v)
144 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
145 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
146 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
147 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
148 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
149 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
154 static int dw_mci_regs_open(struct inode *inode, struct file *file)
156 return single_open(file, dw_mci_regs_show, inode->i_private);
159 static const struct file_operations dw_mci_regs_fops = {
160 .owner = THIS_MODULE,
161 .open = dw_mci_regs_open,
164 .release = single_release,
167 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
169 struct mmc_host *mmc = slot->mmc;
170 struct dw_mci *host = slot->host;
174 root = mmc->debugfs_root;
178 node = debugfs_create_file("regs", S_IRUSR, root, host,
183 node = debugfs_create_file("req", S_IRUSR, root, slot,
188 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
192 node = debugfs_create_x32("pending_events", S_IRUSR, root,
193 (u32 *)&host->pending_events);
197 node = debugfs_create_x32("completed_events", S_IRUSR, root,
198 (u32 *)&host->completed_events);
205 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
207 #endif /* defined(CONFIG_DEBUG_FS) */
209 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
211 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
213 struct mmc_data *data;
214 struct dw_mci_slot *slot = mmc_priv(mmc);
215 struct dw_mci *host = slot->host;
216 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
218 cmd->error = -EINPROGRESS;
222 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
223 cmd->opcode == MMC_GO_IDLE_STATE ||
224 cmd->opcode == MMC_GO_INACTIVE_STATE ||
225 (cmd->opcode == SD_IO_RW_DIRECT &&
226 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
227 cmdr |= SDMMC_CMD_STOP;
228 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
229 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
231 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
234 /* Special bit makes CMD11 not die */
235 cmdr |= SDMMC_CMD_VOLT_SWITCH;
237 /* Change state to continue to handle CMD11 weirdness */
238 WARN_ON(slot->host->state != STATE_SENDING_CMD);
239 slot->host->state = STATE_SENDING_CMD11;
242 * We need to disable low power mode (automatic clock stop)
243 * while doing voltage switch so we don't confuse the card,
244 * since stopping the clock is a specific part of the UHS
245 * voltage change dance.
247 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
248 * unconditionally turned back on in dw_mci_setup_bus() if it's
249 * ever called with a non-zero clock. That shouldn't happen
250 * until the voltage change is all done.
252 clk_en_a = mci_readl(host, CLKENA);
253 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
254 mci_writel(host, CLKENA, clk_en_a);
255 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
256 SDMMC_CMD_PRV_DAT_WAIT, 0);
259 if (cmd->flags & MMC_RSP_PRESENT) {
260 /* We expect a response, so set this bit */
261 cmdr |= SDMMC_CMD_RESP_EXP;
262 if (cmd->flags & MMC_RSP_136)
263 cmdr |= SDMMC_CMD_RESP_LONG;
266 if (cmd->flags & MMC_RSP_CRC)
267 cmdr |= SDMMC_CMD_RESP_CRC;
271 cmdr |= SDMMC_CMD_DAT_EXP;
272 if (data->flags & MMC_DATA_STREAM)
273 cmdr |= SDMMC_CMD_STRM_MODE;
274 if (data->flags & MMC_DATA_WRITE)
275 cmdr |= SDMMC_CMD_DAT_WR;
278 if (drv_data && drv_data->prepare_command)
279 drv_data->prepare_command(slot->host, &cmdr);
284 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
286 struct mmc_command *stop;
292 stop = &host->stop_abort;
294 memset(stop, 0, sizeof(struct mmc_command));
296 if (cmdr == MMC_READ_SINGLE_BLOCK ||
297 cmdr == MMC_READ_MULTIPLE_BLOCK ||
298 cmdr == MMC_WRITE_BLOCK ||
299 cmdr == MMC_WRITE_MULTIPLE_BLOCK) {
300 stop->opcode = MMC_STOP_TRANSMISSION;
302 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
303 } else if (cmdr == SD_IO_RW_EXTENDED) {
304 stop->opcode = SD_IO_RW_DIRECT;
305 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
306 ((cmd->arg >> 28) & 0x7);
307 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
312 cmdr = stop->opcode | SDMMC_CMD_STOP |
313 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
318 static void dw_mci_start_command(struct dw_mci *host,
319 struct mmc_command *cmd, u32 cmd_flags)
323 "start command: ARGR=0x%08x CMDR=0x%08x\n",
324 cmd->arg, cmd_flags);
326 mci_writel(host, CMDARG, cmd->arg);
329 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
332 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
334 struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort;
335 dw_mci_start_command(host, stop, host->stop_cmdr);
338 /* DMA interface functions */
339 static void dw_mci_stop_dma(struct dw_mci *host)
341 if (host->using_dma) {
342 host->dma_ops->stop(host);
343 host->dma_ops->cleanup(host);
346 /* Data transfer was stopped by the interrupt handler */
347 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
350 static int dw_mci_get_dma_dir(struct mmc_data *data)
352 if (data->flags & MMC_DATA_WRITE)
353 return DMA_TO_DEVICE;
355 return DMA_FROM_DEVICE;
358 #ifdef CONFIG_MMC_DW_IDMAC
359 static void dw_mci_dma_cleanup(struct dw_mci *host)
361 struct mmc_data *data = host->data;
364 if (!data->host_cookie)
365 dma_unmap_sg(host->dev,
368 dw_mci_get_dma_dir(data));
371 static void dw_mci_idmac_reset(struct dw_mci *host)
373 u32 bmod = mci_readl(host, BMOD);
374 /* Software reset of DMA */
375 bmod |= SDMMC_IDMAC_SWRESET;
376 mci_writel(host, BMOD, bmod);
379 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
383 /* Disable and reset the IDMAC interface */
384 temp = mci_readl(host, CTRL);
385 temp &= ~SDMMC_CTRL_USE_IDMAC;
386 temp |= SDMMC_CTRL_DMA_RESET;
387 mci_writel(host, CTRL, temp);
389 /* Stop the IDMAC running */
390 temp = mci_readl(host, BMOD);
391 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
392 temp |= SDMMC_IDMAC_SWRESET;
393 mci_writel(host, BMOD, temp);
396 static void dw_mci_idmac_complete_dma(struct dw_mci *host)
398 struct mmc_data *data = host->data;
400 dev_vdbg(host->dev, "DMA complete\n");
402 host->dma_ops->cleanup(host);
405 * If the card was removed, data will be NULL. No point in trying to
406 * send the stop command or waiting for NBUSY in this case.
409 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
410 tasklet_schedule(&host->tasklet);
414 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
418 struct idmac_desc *desc = host->sg_cpu;
420 for (i = 0; i < sg_len; i++, desc++) {
421 unsigned int length = sg_dma_len(&data->sg[i]);
422 u32 mem_addr = sg_dma_address(&data->sg[i]);
424 /* Set the OWN bit and disable interrupts for this descriptor */
425 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
428 IDMAC_SET_BUFFER1_SIZE(desc, length);
430 /* Physical address to DMA to/from */
431 desc->des2 = mem_addr;
434 /* Set first descriptor */
436 desc->des0 |= IDMAC_DES0_FD;
438 /* Set last descriptor */
439 desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
440 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
441 desc->des0 |= IDMAC_DES0_LD;
446 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
450 dw_mci_translate_sglist(host, host->data, sg_len);
452 /* Make sure to reset DMA in case we did PIO before this */
453 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
454 dw_mci_idmac_reset(host);
456 /* Select IDMAC interface */
457 temp = mci_readl(host, CTRL);
458 temp |= SDMMC_CTRL_USE_IDMAC;
459 mci_writel(host, CTRL, temp);
463 /* Enable the IDMAC */
464 temp = mci_readl(host, BMOD);
465 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
466 mci_writel(host, BMOD, temp);
468 /* Start it running */
469 mci_writel(host, PLDMND, 1);
472 static int dw_mci_idmac_init(struct dw_mci *host)
474 struct idmac_desc *p;
477 /* Number of descriptors in the ring buffer */
478 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
480 /* Forward link the descriptor list */
481 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
482 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
484 /* Set the last descriptor as the end-of-ring descriptor */
485 p->des3 = host->sg_dma;
486 p->des0 = IDMAC_DES0_ER;
488 dw_mci_idmac_reset(host);
490 /* Mask out interrupts - get Tx & Rx complete only */
491 mci_writel(host, IDSTS, IDMAC_INT_CLR);
492 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
495 /* Set the descriptor base address */
496 mci_writel(host, DBADDR, host->sg_dma);
500 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
501 .init = dw_mci_idmac_init,
502 .start = dw_mci_idmac_start_dma,
503 .stop = dw_mci_idmac_stop_dma,
504 .complete = dw_mci_idmac_complete_dma,
505 .cleanup = dw_mci_dma_cleanup,
507 #endif /* CONFIG_MMC_DW_IDMAC */
509 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
510 struct mmc_data *data,
513 struct scatterlist *sg;
514 unsigned int i, sg_len;
516 if (!next && data->host_cookie)
517 return data->host_cookie;
520 * We don't do DMA on "complex" transfers, i.e. with
521 * non-word-aligned buffers or lengths. Also, we don't bother
522 * with all the DMA setup overhead for short transfers.
524 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
530 for_each_sg(data->sg, sg, data->sg_len, i) {
531 if (sg->offset & 3 || sg->length & 3)
535 sg_len = dma_map_sg(host->dev,
538 dw_mci_get_dma_dir(data));
543 data->host_cookie = sg_len;
548 static void dw_mci_pre_req(struct mmc_host *mmc,
549 struct mmc_request *mrq,
552 struct dw_mci_slot *slot = mmc_priv(mmc);
553 struct mmc_data *data = mrq->data;
555 if (!slot->host->use_dma || !data)
558 if (data->host_cookie) {
559 data->host_cookie = 0;
563 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
564 data->host_cookie = 0;
567 static void dw_mci_post_req(struct mmc_host *mmc,
568 struct mmc_request *mrq,
571 struct dw_mci_slot *slot = mmc_priv(mmc);
572 struct mmc_data *data = mrq->data;
574 if (!slot->host->use_dma || !data)
577 if (data->host_cookie)
578 dma_unmap_sg(slot->host->dev,
581 dw_mci_get_dma_dir(data));
582 data->host_cookie = 0;
585 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
587 #ifdef CONFIG_MMC_DW_IDMAC
588 unsigned int blksz = data->blksz;
589 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
590 u32 fifo_width = 1 << host->data_shift;
591 u32 blksz_depth = blksz / fifo_width, fifoth_val;
592 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
593 int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1;
595 tx_wmark = (host->fifo_depth) / 2;
596 tx_wmark_invers = host->fifo_depth - tx_wmark;
600 * if blksz is not a multiple of the FIFO width
602 if (blksz % fifo_width) {
609 if (!((blksz_depth % mszs[idx]) ||
610 (tx_wmark_invers % mszs[idx]))) {
612 rx_wmark = mszs[idx] - 1;
617 * If idx is '0', it won't be tried
618 * Thus, initial values are uesed
621 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
622 mci_writel(host, FIFOTH, fifoth_val);
626 static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
628 unsigned int blksz = data->blksz;
629 u32 blksz_depth, fifo_depth;
632 WARN_ON(!(data->flags & MMC_DATA_READ));
634 if (host->timing != MMC_TIMING_MMC_HS200 &&
635 host->timing != MMC_TIMING_UHS_SDR104)
638 blksz_depth = blksz / (1 << host->data_shift);
639 fifo_depth = host->fifo_depth;
641 if (blksz_depth > fifo_depth)
645 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
646 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
647 * Currently just choose blksz.
650 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
654 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
657 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
664 /* If we don't have a channel, we can't do DMA */
668 sg_len = dw_mci_pre_dma_transfer(host, data, 0);
670 host->dma_ops->stop(host);
677 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
678 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
682 * Decide the MSIZE and RX/TX Watermark.
683 * If current block size is same with previous size,
684 * no need to update fifoth.
686 if (host->prev_blksz != data->blksz)
687 dw_mci_adjust_fifoth(host, data);
689 /* Enable the DMA interface */
690 temp = mci_readl(host, CTRL);
691 temp |= SDMMC_CTRL_DMA_ENABLE;
692 mci_writel(host, CTRL, temp);
694 /* Disable RX/TX IRQs, let DMA handle it */
695 temp = mci_readl(host, INTMASK);
696 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
697 mci_writel(host, INTMASK, temp);
699 host->dma_ops->start(host, sg_len);
704 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
708 data->error = -EINPROGRESS;
714 if (data->flags & MMC_DATA_READ) {
715 host->dir_status = DW_MCI_RECV_STATUS;
716 dw_mci_ctrl_rd_thld(host, data);
718 host->dir_status = DW_MCI_SEND_STATUS;
721 if (dw_mci_submit_data_dma(host, data)) {
722 int flags = SG_MITER_ATOMIC;
723 if (host->data->flags & MMC_DATA_READ)
724 flags |= SG_MITER_TO_SG;
726 flags |= SG_MITER_FROM_SG;
728 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
730 host->part_buf_start = 0;
731 host->part_buf_count = 0;
733 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
734 temp = mci_readl(host, INTMASK);
735 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
736 mci_writel(host, INTMASK, temp);
738 temp = mci_readl(host, CTRL);
739 temp &= ~SDMMC_CTRL_DMA_ENABLE;
740 mci_writel(host, CTRL, temp);
743 * Use the initial fifoth_val for PIO mode.
744 * If next issued data may be transfered by DMA mode,
745 * prev_blksz should be invalidated.
747 mci_writel(host, FIFOTH, host->fifoth_val);
748 host->prev_blksz = 0;
751 * Keep the current block size.
752 * It will be used to decide whether to update
753 * fifoth register next time.
755 host->prev_blksz = data->blksz;
759 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
761 struct dw_mci *host = slot->host;
762 unsigned long timeout = jiffies + msecs_to_jiffies(500);
763 unsigned int cmd_status = 0;
765 mci_writel(host, CMDARG, arg);
767 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
769 while (time_before(jiffies, timeout)) {
770 cmd_status = mci_readl(host, CMD);
771 if (!(cmd_status & SDMMC_CMD_START))
774 dev_err(&slot->mmc->class_dev,
775 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
776 cmd, arg, cmd_status);
779 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
781 struct dw_mci *host = slot->host;
782 unsigned int clock = slot->clock;
785 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
787 /* We must continue to set bit 28 in CMD until the change is complete */
788 if (host->state == STATE_WAITING_CMD11_DONE)
789 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
792 mci_writel(host, CLKENA, 0);
793 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
794 } else if (clock != host->current_speed || force_clkinit) {
795 div = host->bus_hz / clock;
796 if (host->bus_hz % clock && host->bus_hz > clock)
798 * move the + 1 after the divide to prevent
799 * over-clocking the card.
803 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
805 if ((clock << div) != slot->__clk_old || force_clkinit)
806 dev_info(&slot->mmc->class_dev,
807 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
808 slot->id, host->bus_hz, clock,
809 div ? ((host->bus_hz / div) >> 1) :
813 mci_writel(host, CLKENA, 0);
814 mci_writel(host, CLKSRC, 0);
817 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
819 /* set clock to desired speed */
820 mci_writel(host, CLKDIV, div);
823 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
825 /* enable clock; only low power if no SDIO */
826 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
827 if (!(mci_readl(host, INTMASK) & SDMMC_INT_SDIO(slot->id)))
828 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
829 mci_writel(host, CLKENA, clk_en_a);
832 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
834 /* keep the clock with reflecting clock dividor */
835 slot->__clk_old = clock << div;
838 host->current_speed = clock;
840 /* Set the current slot bus width */
841 mci_writel(host, CTYPE, (slot->ctype << slot->id));
844 static void __dw_mci_start_request(struct dw_mci *host,
845 struct dw_mci_slot *slot,
846 struct mmc_command *cmd)
848 struct mmc_request *mrq;
849 struct mmc_data *data;
854 host->cur_slot = slot;
857 host->pending_events = 0;
858 host->completed_events = 0;
859 host->cmd_status = 0;
860 host->data_status = 0;
861 host->dir_status = 0;
865 mci_writel(host, TMOUT, 0xFFFFFFFF);
866 mci_writel(host, BYTCNT, data->blksz*data->blocks);
867 mci_writel(host, BLKSIZ, data->blksz);
870 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
872 /* this is the first command, send the initialization clock */
873 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
874 cmdflags |= SDMMC_CMD_INIT;
877 dw_mci_submit_data(host, data);
881 dw_mci_start_command(host, cmd, cmdflags);
884 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
886 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
889 static void dw_mci_start_request(struct dw_mci *host,
890 struct dw_mci_slot *slot)
892 struct mmc_request *mrq = slot->mrq;
893 struct mmc_command *cmd;
895 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
896 __dw_mci_start_request(host, slot, cmd);
899 /* must be called with host->lock held */
900 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
901 struct mmc_request *mrq)
903 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
908 if (host->state == STATE_WAITING_CMD11_DONE) {
909 dev_warn(&slot->mmc->class_dev,
910 "Voltage change didn't complete\n");
912 * this case isn't expected to happen, so we can
913 * either crash here or just try to continue on
914 * in the closest possible state
916 host->state = STATE_IDLE;
919 if (host->state == STATE_IDLE) {
920 host->state = STATE_SENDING_CMD;
921 dw_mci_start_request(host, slot);
923 list_add_tail(&slot->queue_node, &host->queue);
927 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
929 struct dw_mci_slot *slot = mmc_priv(mmc);
930 struct dw_mci *host = slot->host;
935 * The check for card presence and queueing of the request must be
936 * atomic, otherwise the card could be removed in between and the
937 * request wouldn't fail until another card was inserted.
939 spin_lock_bh(&host->lock);
941 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
942 spin_unlock_bh(&host->lock);
943 mrq->cmd->error = -ENOMEDIUM;
944 mmc_request_done(mmc, mrq);
948 dw_mci_queue_request(host, slot, mrq);
950 spin_unlock_bh(&host->lock);
953 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
955 struct dw_mci_slot *slot = mmc_priv(mmc);
956 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
960 switch (ios->bus_width) {
961 case MMC_BUS_WIDTH_4:
962 slot->ctype = SDMMC_CTYPE_4BIT;
964 case MMC_BUS_WIDTH_8:
965 slot->ctype = SDMMC_CTYPE_8BIT;
968 /* set default 1 bit mode */
969 slot->ctype = SDMMC_CTYPE_1BIT;
972 regs = mci_readl(slot->host, UHS_REG);
975 if (ios->timing == MMC_TIMING_MMC_DDR52)
976 regs |= ((0x1 << slot->id) << 16);
978 regs &= ~((0x1 << slot->id) << 16);
980 mci_writel(slot->host, UHS_REG, regs);
981 slot->host->timing = ios->timing;
984 * Use mirror of ios->clock to prevent race with mmc
985 * core ios update when finding the minimum.
987 slot->clock = ios->clock;
989 if (drv_data && drv_data->set_ios)
990 drv_data->set_ios(slot->host, ios);
992 /* Slot specific timing and width adjustment */
993 dw_mci_setup_bus(slot, false);
995 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
996 slot->host->state = STATE_IDLE;
998 switch (ios->power_mode) {
1000 if (!IS_ERR(mmc->supply.vmmc)) {
1001 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1004 dev_err(slot->host->dev,
1005 "failed to enable vmmc regulator\n");
1006 /*return, if failed turn on vmmc*/
1010 if (!IS_ERR(mmc->supply.vqmmc) && !slot->host->vqmmc_enabled) {
1011 ret = regulator_enable(mmc->supply.vqmmc);
1013 dev_err(slot->host->dev,
1014 "failed to enable vqmmc regulator\n");
1016 slot->host->vqmmc_enabled = true;
1018 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1019 regs = mci_readl(slot->host, PWREN);
1020 regs |= (1 << slot->id);
1021 mci_writel(slot->host, PWREN, regs);
1024 if (!IS_ERR(mmc->supply.vmmc))
1025 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1027 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) {
1028 regulator_disable(mmc->supply.vqmmc);
1029 slot->host->vqmmc_enabled = false;
1032 regs = mci_readl(slot->host, PWREN);
1033 regs &= ~(1 << slot->id);
1034 mci_writel(slot->host, PWREN, regs);
1041 static int dw_mci_card_busy(struct mmc_host *mmc)
1043 struct dw_mci_slot *slot = mmc_priv(mmc);
1047 * Check the busy bit which is low when DAT[3:0]
1048 * (the data lines) are 0000
1050 status = mci_readl(slot->host, STATUS);
1052 return !!(status & SDMMC_STATUS_BUSY);
1055 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1057 struct dw_mci_slot *slot = mmc_priv(mmc);
1058 struct dw_mci *host = slot->host;
1060 u32 v18 = SDMMC_UHS_18V << slot->id;
1065 * Program the voltage. Note that some instances of dw_mmc may use
1066 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1067 * does no harm but you need to set the regulator directly. Try both.
1069 uhs = mci_readl(host, UHS_REG);
1070 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1079 if (!IS_ERR(mmc->supply.vqmmc)) {
1080 ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv);
1083 dev_err(&mmc->class_dev,
1084 "Regulator set error %d: %d - %d\n",
1085 ret, min_uv, max_uv);
1089 mci_writel(host, UHS_REG, uhs);
1094 static int dw_mci_get_ro(struct mmc_host *mmc)
1097 struct dw_mci_slot *slot = mmc_priv(mmc);
1098 int gpio_ro = mmc_gpio_get_ro(mmc);
1100 /* Use platform get_ro function, else try on board write protect */
1101 if ((slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT) ||
1102 (slot->host->quirks & DW_MCI_QUIRK_NO_WRITE_PROTECT))
1104 else if (!IS_ERR_VALUE(gpio_ro))
1105 read_only = gpio_ro;
1108 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1110 dev_dbg(&mmc->class_dev, "card is %s\n",
1111 read_only ? "read-only" : "read-write");
1116 static int dw_mci_get_cd(struct mmc_host *mmc)
1119 struct dw_mci_slot *slot = mmc_priv(mmc);
1120 struct dw_mci_board *brd = slot->host->pdata;
1121 struct dw_mci *host = slot->host;
1122 int gpio_cd = mmc_gpio_get_cd(mmc);
1124 /* Use platform get_cd function, else try onboard card detect */
1125 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
1127 else if (!IS_ERR_VALUE(gpio_cd))
1130 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1133 spin_lock_bh(&host->lock);
1135 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1136 dev_dbg(&mmc->class_dev, "card is present\n");
1138 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1139 dev_dbg(&mmc->class_dev, "card is not present\n");
1141 spin_unlock_bh(&host->lock);
1147 * Disable lower power mode.
1149 * Low power mode will stop the card clock when idle. According to the
1150 * description of the CLKENA register we should disable low power mode
1151 * for SDIO cards if we need SDIO interrupts to work.
1153 * This function is fast if low power mode is already disabled.
1155 static void dw_mci_disable_low_power(struct dw_mci_slot *slot)
1157 struct dw_mci *host = slot->host;
1159 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1161 clk_en_a = mci_readl(host, CLKENA);
1163 if (clk_en_a & clken_low_pwr) {
1164 mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr);
1165 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1166 SDMMC_CMD_PRV_DAT_WAIT, 0);
1170 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1172 struct dw_mci_slot *slot = mmc_priv(mmc);
1173 struct dw_mci *host = slot->host;
1176 /* Enable/disable Slot Specific SDIO interrupt */
1177 int_mask = mci_readl(host, INTMASK);
1180 * Turn off low power mode if it was enabled. This is a bit of
1181 * a heavy operation and we disable / enable IRQs a lot, so
1182 * we'll leave low power mode disabled and it will get
1183 * re-enabled again in dw_mci_setup_bus().
1185 dw_mci_disable_low_power(slot);
1187 mci_writel(host, INTMASK,
1188 (int_mask | SDMMC_INT_SDIO(slot->id)));
1190 mci_writel(host, INTMASK,
1191 (int_mask & ~SDMMC_INT_SDIO(slot->id)));
1195 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1197 struct dw_mci_slot *slot = mmc_priv(mmc);
1198 struct dw_mci *host = slot->host;
1199 const struct dw_mci_drv_data *drv_data = host->drv_data;
1200 struct dw_mci_tuning_data tuning_data;
1203 if (opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1204 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
1205 tuning_data.blk_pattern = tuning_blk_pattern_8bit;
1206 tuning_data.blksz = sizeof(tuning_blk_pattern_8bit);
1207 } else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
1208 tuning_data.blk_pattern = tuning_blk_pattern_4bit;
1209 tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
1213 } else if (opcode == MMC_SEND_TUNING_BLOCK) {
1214 tuning_data.blk_pattern = tuning_blk_pattern_4bit;
1215 tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
1218 "Undefined command(%d) for tuning\n", opcode);
1222 if (drv_data && drv_data->execute_tuning)
1223 err = drv_data->execute_tuning(slot, opcode, &tuning_data);
1227 static const struct mmc_host_ops dw_mci_ops = {
1228 .request = dw_mci_request,
1229 .pre_req = dw_mci_pre_req,
1230 .post_req = dw_mci_post_req,
1231 .set_ios = dw_mci_set_ios,
1232 .get_ro = dw_mci_get_ro,
1233 .get_cd = dw_mci_get_cd,
1234 .enable_sdio_irq = dw_mci_enable_sdio_irq,
1235 .execute_tuning = dw_mci_execute_tuning,
1236 .card_busy = dw_mci_card_busy,
1237 .start_signal_voltage_switch = dw_mci_switch_voltage,
1241 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1242 __releases(&host->lock)
1243 __acquires(&host->lock)
1245 struct dw_mci_slot *slot;
1246 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1248 WARN_ON(host->cmd || host->data);
1250 host->cur_slot->mrq = NULL;
1252 if (!list_empty(&host->queue)) {
1253 slot = list_entry(host->queue.next,
1254 struct dw_mci_slot, queue_node);
1255 list_del(&slot->queue_node);
1256 dev_vdbg(host->dev, "list not empty: %s is next\n",
1257 mmc_hostname(slot->mmc));
1258 host->state = STATE_SENDING_CMD;
1259 dw_mci_start_request(host, slot);
1261 dev_vdbg(host->dev, "list empty\n");
1263 if (host->state == STATE_SENDING_CMD11)
1264 host->state = STATE_WAITING_CMD11_DONE;
1266 host->state = STATE_IDLE;
1269 spin_unlock(&host->lock);
1270 mmc_request_done(prev_mmc, mrq);
1271 spin_lock(&host->lock);
1274 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1276 u32 status = host->cmd_status;
1278 host->cmd_status = 0;
1280 /* Read the response from the card (up to 16 bytes) */
1281 if (cmd->flags & MMC_RSP_PRESENT) {
1282 if (cmd->flags & MMC_RSP_136) {
1283 cmd->resp[3] = mci_readl(host, RESP0);
1284 cmd->resp[2] = mci_readl(host, RESP1);
1285 cmd->resp[1] = mci_readl(host, RESP2);
1286 cmd->resp[0] = mci_readl(host, RESP3);
1288 cmd->resp[0] = mci_readl(host, RESP0);
1295 if (status & SDMMC_INT_RTO)
1296 cmd->error = -ETIMEDOUT;
1297 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1298 cmd->error = -EILSEQ;
1299 else if (status & SDMMC_INT_RESP_ERR)
1305 /* newer ip versions need a delay between retries */
1306 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
1313 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1315 u32 status = host->data_status;
1317 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1318 if (status & SDMMC_INT_DRTO) {
1319 data->error = -ETIMEDOUT;
1320 } else if (status & SDMMC_INT_DCRC) {
1321 data->error = -EILSEQ;
1322 } else if (status & SDMMC_INT_EBE) {
1323 if (host->dir_status ==
1324 DW_MCI_SEND_STATUS) {
1326 * No data CRC status was returned.
1327 * The number of bytes transferred
1328 * will be exaggerated in PIO mode.
1330 data->bytes_xfered = 0;
1331 data->error = -ETIMEDOUT;
1332 } else if (host->dir_status ==
1333 DW_MCI_RECV_STATUS) {
1337 /* SDMMC_INT_SBE is included */
1341 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1344 * After an error, there may be data lingering
1349 data->bytes_xfered = data->blocks * data->blksz;
1356 static void dw_mci_tasklet_func(unsigned long priv)
1358 struct dw_mci *host = (struct dw_mci *)priv;
1359 struct mmc_data *data;
1360 struct mmc_command *cmd;
1361 struct mmc_request *mrq;
1362 enum dw_mci_state state;
1363 enum dw_mci_state prev_state;
1366 spin_lock(&host->lock);
1368 state = host->state;
1377 case STATE_WAITING_CMD11_DONE:
1380 case STATE_SENDING_CMD11:
1381 case STATE_SENDING_CMD:
1382 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1383 &host->pending_events))
1388 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1389 err = dw_mci_command_complete(host, cmd);
1390 if (cmd == mrq->sbc && !err) {
1391 prev_state = state = STATE_SENDING_CMD;
1392 __dw_mci_start_request(host, host->cur_slot,
1397 if (cmd->data && err) {
1398 dw_mci_stop_dma(host);
1399 send_stop_abort(host, data);
1400 state = STATE_SENDING_STOP;
1404 if (!cmd->data || err) {
1405 dw_mci_request_end(host, mrq);
1409 prev_state = state = STATE_SENDING_DATA;
1412 case STATE_SENDING_DATA:
1414 * We could get a data error and never a transfer
1415 * complete so we'd better check for it here.
1417 * Note that we don't really care if we also got a
1418 * transfer complete; stopping the DMA and sending an
1421 if (test_and_clear_bit(EVENT_DATA_ERROR,
1422 &host->pending_events)) {
1423 dw_mci_stop_dma(host);
1424 send_stop_abort(host, data);
1425 state = STATE_DATA_ERROR;
1429 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1430 &host->pending_events))
1433 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1436 * Handle an EVENT_DATA_ERROR that might have shown up
1437 * before the transfer completed. This might not have
1438 * been caught by the check above because the interrupt
1439 * could have gone off between the previous check and
1440 * the check for transfer complete.
1442 * Technically this ought not be needed assuming we
1443 * get a DATA_COMPLETE eventually (we'll notice the
1444 * error and end the request), but it shouldn't hurt.
1446 * This has the advantage of sending the stop command.
1448 if (test_and_clear_bit(EVENT_DATA_ERROR,
1449 &host->pending_events)) {
1450 dw_mci_stop_dma(host);
1451 send_stop_abort(host, data);
1452 state = STATE_DATA_ERROR;
1455 prev_state = state = STATE_DATA_BUSY;
1459 case STATE_DATA_BUSY:
1460 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1461 &host->pending_events))
1465 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1466 err = dw_mci_data_complete(host, data);
1469 if (!data->stop || mrq->sbc) {
1470 if (mrq->sbc && data->stop)
1471 data->stop->error = 0;
1472 dw_mci_request_end(host, mrq);
1476 /* stop command for open-ended transfer*/
1478 send_stop_abort(host, data);
1481 * If we don't have a command complete now we'll
1482 * never get one since we just reset everything;
1483 * better end the request.
1485 * If we do have a command complete we'll fall
1486 * through to the SENDING_STOP command and
1487 * everything will be peachy keen.
1489 if (!test_bit(EVENT_CMD_COMPLETE,
1490 &host->pending_events)) {
1492 dw_mci_request_end(host, mrq);
1498 * If err has non-zero,
1499 * stop-abort command has been already issued.
1501 prev_state = state = STATE_SENDING_STOP;
1505 case STATE_SENDING_STOP:
1506 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1507 &host->pending_events))
1510 /* CMD error in data command */
1511 if (mrq->cmd->error && mrq->data)
1518 dw_mci_command_complete(host, mrq->stop);
1520 host->cmd_status = 0;
1522 dw_mci_request_end(host, mrq);
1525 case STATE_DATA_ERROR:
1526 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1527 &host->pending_events))
1530 state = STATE_DATA_BUSY;
1533 } while (state != prev_state);
1535 host->state = state;
1537 spin_unlock(&host->lock);
1541 /* push final bytes to part_buf, only use during push */
1542 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
1544 memcpy((void *)&host->part_buf, buf, cnt);
1545 host->part_buf_count = cnt;
1548 /* append bytes to part_buf, only use during push */
1549 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1551 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1552 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1553 host->part_buf_count += cnt;
1557 /* pull first bytes from part_buf, only use during pull */
1558 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1560 cnt = min(cnt, (int)host->part_buf_count);
1562 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1564 host->part_buf_count -= cnt;
1565 host->part_buf_start += cnt;
1570 /* pull final bytes from the part_buf, assuming it's just been filled */
1571 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
1573 memcpy(buf, &host->part_buf, cnt);
1574 host->part_buf_start = cnt;
1575 host->part_buf_count = (1 << host->data_shift) - cnt;
1578 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1580 struct mmc_data *data = host->data;
1583 /* try and push anything in the part_buf */
1584 if (unlikely(host->part_buf_count)) {
1585 int len = dw_mci_push_part_bytes(host, buf, cnt);
1588 if (host->part_buf_count == 2) {
1589 mci_writew(host, DATA(host->data_offset),
1591 host->part_buf_count = 0;
1594 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1595 if (unlikely((unsigned long)buf & 0x1)) {
1597 u16 aligned_buf[64];
1598 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1599 int items = len >> 1;
1601 /* memcpy from input buffer into aligned buffer */
1602 memcpy(aligned_buf, buf, len);
1605 /* push data from aligned buffer into fifo */
1606 for (i = 0; i < items; ++i)
1607 mci_writew(host, DATA(host->data_offset),
1614 for (; cnt >= 2; cnt -= 2)
1615 mci_writew(host, DATA(host->data_offset), *pdata++);
1618 /* put anything remaining in the part_buf */
1620 dw_mci_set_part_bytes(host, buf, cnt);
1621 /* Push data if we have reached the expected data length */
1622 if ((data->bytes_xfered + init_cnt) ==
1623 (data->blksz * data->blocks))
1624 mci_writew(host, DATA(host->data_offset),
1629 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1631 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1632 if (unlikely((unsigned long)buf & 0x1)) {
1634 /* pull data from fifo into aligned buffer */
1635 u16 aligned_buf[64];
1636 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1637 int items = len >> 1;
1639 for (i = 0; i < items; ++i)
1640 aligned_buf[i] = mci_readw(host,
1641 DATA(host->data_offset));
1642 /* memcpy from aligned buffer into output buffer */
1643 memcpy(buf, aligned_buf, len);
1651 for (; cnt >= 2; cnt -= 2)
1652 *pdata++ = mci_readw(host, DATA(host->data_offset));
1656 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
1657 dw_mci_pull_final_bytes(host, buf, cnt);
1661 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
1663 struct mmc_data *data = host->data;
1666 /* try and push anything in the part_buf */
1667 if (unlikely(host->part_buf_count)) {
1668 int len = dw_mci_push_part_bytes(host, buf, cnt);
1671 if (host->part_buf_count == 4) {
1672 mci_writel(host, DATA(host->data_offset),
1674 host->part_buf_count = 0;
1677 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1678 if (unlikely((unsigned long)buf & 0x3)) {
1680 u32 aligned_buf[32];
1681 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1682 int items = len >> 2;
1684 /* memcpy from input buffer into aligned buffer */
1685 memcpy(aligned_buf, buf, len);
1688 /* push data from aligned buffer into fifo */
1689 for (i = 0; i < items; ++i)
1690 mci_writel(host, DATA(host->data_offset),
1697 for (; cnt >= 4; cnt -= 4)
1698 mci_writel(host, DATA(host->data_offset), *pdata++);
1701 /* put anything remaining in the part_buf */
1703 dw_mci_set_part_bytes(host, buf, cnt);
1704 /* Push data if we have reached the expected data length */
1705 if ((data->bytes_xfered + init_cnt) ==
1706 (data->blksz * data->blocks))
1707 mci_writel(host, DATA(host->data_offset),
1712 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
1714 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1715 if (unlikely((unsigned long)buf & 0x3)) {
1717 /* pull data from fifo into aligned buffer */
1718 u32 aligned_buf[32];
1719 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1720 int items = len >> 2;
1722 for (i = 0; i < items; ++i)
1723 aligned_buf[i] = mci_readl(host,
1724 DATA(host->data_offset));
1725 /* memcpy from aligned buffer into output buffer */
1726 memcpy(buf, aligned_buf, len);
1734 for (; cnt >= 4; cnt -= 4)
1735 *pdata++ = mci_readl(host, DATA(host->data_offset));
1739 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
1740 dw_mci_pull_final_bytes(host, buf, cnt);
1744 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1746 struct mmc_data *data = host->data;
1749 /* try and push anything in the part_buf */
1750 if (unlikely(host->part_buf_count)) {
1751 int len = dw_mci_push_part_bytes(host, buf, cnt);
1755 if (host->part_buf_count == 8) {
1756 mci_writeq(host, DATA(host->data_offset),
1758 host->part_buf_count = 0;
1761 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1762 if (unlikely((unsigned long)buf & 0x7)) {
1764 u64 aligned_buf[16];
1765 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1766 int items = len >> 3;
1768 /* memcpy from input buffer into aligned buffer */
1769 memcpy(aligned_buf, buf, len);
1772 /* push data from aligned buffer into fifo */
1773 for (i = 0; i < items; ++i)
1774 mci_writeq(host, DATA(host->data_offset),
1781 for (; cnt >= 8; cnt -= 8)
1782 mci_writeq(host, DATA(host->data_offset), *pdata++);
1785 /* put anything remaining in the part_buf */
1787 dw_mci_set_part_bytes(host, buf, cnt);
1788 /* Push data if we have reached the expected data length */
1789 if ((data->bytes_xfered + init_cnt) ==
1790 (data->blksz * data->blocks))
1791 mci_writeq(host, DATA(host->data_offset),
1796 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1798 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1799 if (unlikely((unsigned long)buf & 0x7)) {
1801 /* pull data from fifo into aligned buffer */
1802 u64 aligned_buf[16];
1803 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1804 int items = len >> 3;
1806 for (i = 0; i < items; ++i)
1807 aligned_buf[i] = mci_readq(host,
1808 DATA(host->data_offset));
1809 /* memcpy from aligned buffer into output buffer */
1810 memcpy(buf, aligned_buf, len);
1818 for (; cnt >= 8; cnt -= 8)
1819 *pdata++ = mci_readq(host, DATA(host->data_offset));
1823 host->part_buf = mci_readq(host, DATA(host->data_offset));
1824 dw_mci_pull_final_bytes(host, buf, cnt);
1828 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
1832 /* get remaining partial bytes */
1833 len = dw_mci_pull_part_bytes(host, buf, cnt);
1834 if (unlikely(len == cnt))
1839 /* get the rest of the data */
1840 host->pull_data(host, buf, cnt);
1843 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
1845 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1847 unsigned int offset;
1848 struct mmc_data *data = host->data;
1849 int shift = host->data_shift;
1852 unsigned int remain, fcnt;
1855 if (!sg_miter_next(sg_miter))
1858 host->sg = sg_miter->piter.sg;
1859 buf = sg_miter->addr;
1860 remain = sg_miter->length;
1864 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
1865 << shift) + host->part_buf_count;
1866 len = min(remain, fcnt);
1869 dw_mci_pull_data(host, (void *)(buf + offset), len);
1870 data->bytes_xfered += len;
1875 sg_miter->consumed = offset;
1876 status = mci_readl(host, MINTSTS);
1877 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1878 /* if the RXDR is ready read again */
1879 } while ((status & SDMMC_INT_RXDR) ||
1880 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
1883 if (!sg_miter_next(sg_miter))
1885 sg_miter->consumed = 0;
1887 sg_miter_stop(sg_miter);
1891 sg_miter_stop(sg_miter);
1894 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1897 static void dw_mci_write_data_pio(struct dw_mci *host)
1899 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1901 unsigned int offset;
1902 struct mmc_data *data = host->data;
1903 int shift = host->data_shift;
1906 unsigned int fifo_depth = host->fifo_depth;
1907 unsigned int remain, fcnt;
1910 if (!sg_miter_next(sg_miter))
1913 host->sg = sg_miter->piter.sg;
1914 buf = sg_miter->addr;
1915 remain = sg_miter->length;
1919 fcnt = ((fifo_depth -
1920 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
1921 << shift) - host->part_buf_count;
1922 len = min(remain, fcnt);
1925 host->push_data(host, (void *)(buf + offset), len);
1926 data->bytes_xfered += len;
1931 sg_miter->consumed = offset;
1932 status = mci_readl(host, MINTSTS);
1933 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1934 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
1937 if (!sg_miter_next(sg_miter))
1939 sg_miter->consumed = 0;
1941 sg_miter_stop(sg_miter);
1945 sg_miter_stop(sg_miter);
1948 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1951 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
1953 if (!host->cmd_status)
1954 host->cmd_status = status;
1958 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1959 tasklet_schedule(&host->tasklet);
1962 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
1964 struct dw_mci *host = dev_id;
1968 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
1971 * DTO fix - version 2.10a and below, and only if internal DMA
1974 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
1976 ((mci_readl(host, STATUS) >> 17) & 0x1fff))
1977 pending |= SDMMC_INT_DATA_OVER;
1981 /* Check volt switch first, since it can look like an error */
1982 if ((host->state == STATE_SENDING_CMD11) &&
1983 (pending & SDMMC_INT_VOLT_SWITCH)) {
1984 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
1985 pending &= ~SDMMC_INT_VOLT_SWITCH;
1986 dw_mci_cmd_interrupt(host, pending);
1989 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
1990 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
1991 host->cmd_status = pending;
1993 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1996 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
1997 /* if there is an error report DATA_ERROR */
1998 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
1999 host->data_status = pending;
2001 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2002 tasklet_schedule(&host->tasklet);
2005 if (pending & SDMMC_INT_DATA_OVER) {
2006 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2007 if (!host->data_status)
2008 host->data_status = pending;
2010 if (host->dir_status == DW_MCI_RECV_STATUS) {
2011 if (host->sg != NULL)
2012 dw_mci_read_data_pio(host, true);
2014 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2015 tasklet_schedule(&host->tasklet);
2018 if (pending & SDMMC_INT_RXDR) {
2019 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2020 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2021 dw_mci_read_data_pio(host, false);
2024 if (pending & SDMMC_INT_TXDR) {
2025 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2026 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2027 dw_mci_write_data_pio(host);
2030 if (pending & SDMMC_INT_CMD_DONE) {
2031 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2032 dw_mci_cmd_interrupt(host, pending);
2035 if (pending & SDMMC_INT_CD) {
2036 mci_writel(host, RINTSTS, SDMMC_INT_CD);
2037 queue_work(host->card_workqueue, &host->card_work);
2040 /* Handle SDIO Interrupts */
2041 for (i = 0; i < host->num_slots; i++) {
2042 struct dw_mci_slot *slot = host->slot[i];
2043 if (pending & SDMMC_INT_SDIO(i)) {
2044 mci_writel(host, RINTSTS, SDMMC_INT_SDIO(i));
2045 mmc_signal_sdio_irq(slot->mmc);
2051 #ifdef CONFIG_MMC_DW_IDMAC
2052 /* Handle DMA interrupts */
2053 pending = mci_readl(host, IDSTS);
2054 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2055 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
2056 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2057 host->dma_ops->complete(host);
2064 static void dw_mci_work_routine_card(struct work_struct *work)
2066 struct dw_mci *host = container_of(work, struct dw_mci, card_work);
2069 for (i = 0; i < host->num_slots; i++) {
2070 struct dw_mci_slot *slot = host->slot[i];
2071 struct mmc_host *mmc = slot->mmc;
2072 struct mmc_request *mrq;
2075 present = dw_mci_get_cd(mmc);
2076 while (present != slot->last_detect_state) {
2077 dev_dbg(&slot->mmc->class_dev, "card %s\n",
2078 present ? "inserted" : "removed");
2080 spin_lock_bh(&host->lock);
2082 /* Card change detected */
2083 slot->last_detect_state = present;
2085 /* Clean up queue if present */
2088 if (mrq == host->mrq) {
2092 switch (host->state) {
2094 case STATE_WAITING_CMD11_DONE:
2096 case STATE_SENDING_CMD11:
2097 case STATE_SENDING_CMD:
2098 mrq->cmd->error = -ENOMEDIUM;
2102 case STATE_SENDING_DATA:
2103 mrq->data->error = -ENOMEDIUM;
2104 dw_mci_stop_dma(host);
2106 case STATE_DATA_BUSY:
2107 case STATE_DATA_ERROR:
2108 if (mrq->data->error == -EINPROGRESS)
2109 mrq->data->error = -ENOMEDIUM;
2111 case STATE_SENDING_STOP:
2113 mrq->stop->error = -ENOMEDIUM;
2117 dw_mci_request_end(host, mrq);
2119 list_del(&slot->queue_node);
2120 mrq->cmd->error = -ENOMEDIUM;
2122 mrq->data->error = -ENOMEDIUM;
2124 mrq->stop->error = -ENOMEDIUM;
2126 spin_unlock(&host->lock);
2127 mmc_request_done(slot->mmc, mrq);
2128 spin_lock(&host->lock);
2132 /* Power down slot */
2136 spin_unlock_bh(&host->lock);
2138 present = dw_mci_get_cd(mmc);
2141 mmc_detect_change(slot->mmc,
2142 msecs_to_jiffies(host->pdata->detect_delay_ms));
2147 /* given a slot id, find out the device node representing that slot */
2148 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
2150 struct device_node *np;
2154 if (!dev || !dev->of_node)
2157 for_each_child_of_node(dev->of_node, np) {
2158 addr = of_get_property(np, "reg", &len);
2159 if (!addr || (len < sizeof(int)))
2161 if (be32_to_cpup(addr) == slot)
2167 static struct dw_mci_of_slot_quirks {
2170 } of_slot_quirks[] = {
2172 .quirk = "disable-wp",
2173 .id = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
2177 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
2179 struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
2184 for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++)
2185 if (of_get_property(np, of_slot_quirks[idx].quirk, NULL)) {
2186 dev_warn(dev, "Slot quirk %s is deprecated\n",
2187 of_slot_quirks[idx].quirk);
2188 quirks |= of_slot_quirks[idx].id;
2193 #else /* CONFIG_OF */
2194 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
2198 #endif /* CONFIG_OF */
2200 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
2202 struct mmc_host *mmc;
2203 struct dw_mci_slot *slot;
2204 const struct dw_mci_drv_data *drv_data = host->drv_data;
2208 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2212 slot = mmc_priv(mmc);
2216 host->slot[id] = slot;
2218 slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id);
2220 mmc->ops = &dw_mci_ops;
2221 if (of_property_read_u32_array(host->dev->of_node,
2222 "clock-freq-min-max", freq, 2)) {
2223 mmc->f_min = DW_MCI_FREQ_MIN;
2224 mmc->f_max = DW_MCI_FREQ_MAX;
2226 mmc->f_min = freq[0];
2227 mmc->f_max = freq[1];
2230 /*if there are external regulators, get them*/
2231 ret = mmc_regulator_get_supply(mmc);
2232 if (ret == -EPROBE_DEFER)
2233 goto err_host_allocated;
2235 if (!mmc->ocr_avail)
2236 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2238 if (host->pdata->caps)
2239 mmc->caps = host->pdata->caps;
2241 if (host->pdata->pm_caps)
2242 mmc->pm_caps = host->pdata->pm_caps;
2244 if (host->dev->of_node) {
2245 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2249 ctrl_id = to_platform_device(host->dev)->id;
2251 if (drv_data && drv_data->caps)
2252 mmc->caps |= drv_data->caps[ctrl_id];
2254 if (host->pdata->caps2)
2255 mmc->caps2 = host->pdata->caps2;
2257 ret = mmc_of_parse(mmc);
2259 goto err_host_allocated;
2261 if (host->pdata->blk_settings) {
2262 mmc->max_segs = host->pdata->blk_settings->max_segs;
2263 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
2264 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
2265 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
2266 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
2268 /* Useful defaults if platform data is unset. */
2269 #ifdef CONFIG_MMC_DW_IDMAC
2270 mmc->max_segs = host->ring_size;
2271 mmc->max_blk_size = 65536;
2272 mmc->max_blk_count = host->ring_size;
2273 mmc->max_seg_size = 0x1000;
2274 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
2277 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
2278 mmc->max_blk_count = 512;
2279 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2280 mmc->max_seg_size = mmc->max_req_size;
2281 #endif /* CONFIG_MMC_DW_IDMAC */
2284 if (dw_mci_get_cd(mmc))
2285 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2287 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2289 ret = mmc_add_host(mmc);
2291 goto err_host_allocated;
2293 #if defined(CONFIG_DEBUG_FS)
2294 dw_mci_init_debugfs(slot);
2297 /* Card initially undetected */
2298 slot->last_detect_state = 0;
2307 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2309 /* Debugfs stuff is cleaned up by mmc core */
2310 mmc_remove_host(slot->mmc);
2311 slot->host->slot[id] = NULL;
2312 mmc_free_host(slot->mmc);
2315 static void dw_mci_init_dma(struct dw_mci *host)
2317 /* Alloc memory for sg translation */
2318 host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
2319 &host->sg_dma, GFP_KERNEL);
2320 if (!host->sg_cpu) {
2321 dev_err(host->dev, "%s: could not alloc DMA memory\n",
2326 /* Determine which DMA interface to use */
2327 #ifdef CONFIG_MMC_DW_IDMAC
2328 host->dma_ops = &dw_mci_idmac_ops;
2329 dev_info(host->dev, "Using internal DMA controller.\n");
2335 if (host->dma_ops->init && host->dma_ops->start &&
2336 host->dma_ops->stop && host->dma_ops->cleanup) {
2337 if (host->dma_ops->init(host)) {
2338 dev_err(host->dev, "%s: Unable to initialize "
2339 "DMA Controller.\n", __func__);
2343 dev_err(host->dev, "DMA initialization not found.\n");
2351 dev_info(host->dev, "Using PIO mode.\n");
2356 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
2358 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2361 ctrl = mci_readl(host, CTRL);
2363 mci_writel(host, CTRL, ctrl);
2365 /* wait till resets clear */
2367 ctrl = mci_readl(host, CTRL);
2368 if (!(ctrl & reset))
2370 } while (time_before(jiffies, timeout));
2373 "Timeout resetting block (ctrl reset %#x)\n",
2379 static bool dw_mci_reset(struct dw_mci *host)
2381 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
2385 * Reseting generates a block interrupt, hence setting
2386 * the scatter-gather pointer to NULL.
2389 sg_miter_stop(&host->sg_miter);
2394 flags |= SDMMC_CTRL_DMA_RESET;
2396 if (dw_mci_ctrl_reset(host, flags)) {
2398 * In all cases we clear the RAWINTS register to clear any
2401 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2403 /* if using dma we wait for dma_req to clear */
2404 if (host->use_dma) {
2405 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2408 status = mci_readl(host, STATUS);
2409 if (!(status & SDMMC_STATUS_DMA_REQ))
2412 } while (time_before(jiffies, timeout));
2414 if (status & SDMMC_STATUS_DMA_REQ) {
2416 "%s: Timeout waiting for dma_req to "
2417 "clear during reset\n", __func__);
2421 /* when using DMA next we reset the fifo again */
2422 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2426 /* if the controller reset bit did clear, then set clock regs */
2427 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
2428 dev_err(host->dev, "%s: fifo/dma reset bits didn't "
2429 "clear but ciu was reset, doing clock update\n",
2435 #if IS_ENABLED(CONFIG_MMC_DW_IDMAC)
2436 /* It is also recommended that we reset and reprogram idmac */
2437 dw_mci_idmac_reset(host);
2443 /* After a CTRL reset we need to have CIU set clock registers */
2444 mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2450 static struct dw_mci_of_quirks {
2455 .quirk = "broken-cd",
2456 .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
2458 .quirk = "disable-wp",
2459 .id = DW_MCI_QUIRK_NO_WRITE_PROTECT,
2463 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2465 struct dw_mci_board *pdata;
2466 struct device *dev = host->dev;
2467 struct device_node *np = dev->of_node;
2468 const struct dw_mci_drv_data *drv_data = host->drv_data;
2470 u32 clock_frequency;
2472 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2474 dev_err(dev, "could not allocate memory for pdata\n");
2475 return ERR_PTR(-ENOMEM);
2478 /* find out number of slots supported */
2479 if (of_property_read_u32(dev->of_node, "num-slots",
2480 &pdata->num_slots)) {
2481 dev_info(dev, "num-slots property not found, "
2482 "assuming 1 slot is available\n");
2483 pdata->num_slots = 1;
2487 for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
2488 if (of_get_property(np, of_quirks[idx].quirk, NULL))
2489 pdata->quirks |= of_quirks[idx].id;
2491 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
2492 dev_info(dev, "fifo-depth property not found, using "
2493 "value of FIFOTH register as default\n");
2495 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2497 if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
2498 pdata->bus_hz = clock_frequency;
2500 if (drv_data && drv_data->parse_dt) {
2501 ret = drv_data->parse_dt(host);
2503 return ERR_PTR(ret);
2506 if (of_find_property(np, "supports-highspeed", NULL))
2507 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2512 #else /* CONFIG_OF */
2513 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2515 return ERR_PTR(-EINVAL);
2517 #endif /* CONFIG_OF */
2519 int dw_mci_probe(struct dw_mci *host)
2521 const struct dw_mci_drv_data *drv_data = host->drv_data;
2522 int width, i, ret = 0;
2527 host->pdata = dw_mci_parse_dt(host);
2528 if (IS_ERR(host->pdata)) {
2529 dev_err(host->dev, "platform data not available\n");
2534 if (host->pdata->num_slots > 1) {
2536 "Platform data must supply num_slots.\n");
2540 host->biu_clk = devm_clk_get(host->dev, "biu");
2541 if (IS_ERR(host->biu_clk)) {
2542 dev_dbg(host->dev, "biu clock not available\n");
2544 ret = clk_prepare_enable(host->biu_clk);
2546 dev_err(host->dev, "failed to enable biu clock\n");
2551 host->ciu_clk = devm_clk_get(host->dev, "ciu");
2552 if (IS_ERR(host->ciu_clk)) {
2553 dev_dbg(host->dev, "ciu clock not available\n");
2554 host->bus_hz = host->pdata->bus_hz;
2556 ret = clk_prepare_enable(host->ciu_clk);
2558 dev_err(host->dev, "failed to enable ciu clock\n");
2562 if (host->pdata->bus_hz) {
2563 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
2566 "Unable to set bus rate to %uHz\n",
2567 host->pdata->bus_hz);
2569 host->bus_hz = clk_get_rate(host->ciu_clk);
2572 if (!host->bus_hz) {
2574 "Platform data must supply bus speed\n");
2579 if (drv_data && drv_data->init) {
2580 ret = drv_data->init(host);
2583 "implementation specific init failed\n");
2588 if (drv_data && drv_data->setup_clock) {
2589 ret = drv_data->setup_clock(host);
2592 "implementation specific clock setup failed\n");
2597 host->quirks = host->pdata->quirks;
2599 spin_lock_init(&host->lock);
2600 INIT_LIST_HEAD(&host->queue);
2603 * Get the host data width - this assumes that HCON has been set with
2604 * the correct values.
2606 i = (mci_readl(host, HCON) >> 7) & 0x7;
2608 host->push_data = dw_mci_push_data16;
2609 host->pull_data = dw_mci_pull_data16;
2611 host->data_shift = 1;
2612 } else if (i == 2) {
2613 host->push_data = dw_mci_push_data64;
2614 host->pull_data = dw_mci_pull_data64;
2616 host->data_shift = 3;
2618 /* Check for a reserved value, and warn if it is */
2620 "HCON reports a reserved host data width!\n"
2621 "Defaulting to 32-bit access.\n");
2622 host->push_data = dw_mci_push_data32;
2623 host->pull_data = dw_mci_pull_data32;
2625 host->data_shift = 2;
2628 /* Reset all blocks */
2629 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS))
2632 host->dma_ops = host->pdata->dma_ops;
2633 dw_mci_init_dma(host);
2635 /* Clear the interrupts for the host controller */
2636 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2637 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2639 /* Put in max timeout */
2640 mci_writel(host, TMOUT, 0xFFFFFFFF);
2643 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
2644 * Tx Mark = fifo_size / 2 DMA Size = 8
2646 if (!host->pdata->fifo_depth) {
2648 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
2649 * have been overwritten by the bootloader, just like we're
2650 * about to do, so if you know the value for your hardware, you
2651 * should put it in the platform data.
2653 fifo_size = mci_readl(host, FIFOTH);
2654 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
2656 fifo_size = host->pdata->fifo_depth;
2658 host->fifo_depth = fifo_size;
2660 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
2661 mci_writel(host, FIFOTH, host->fifoth_val);
2663 /* disable clock to CIU */
2664 mci_writel(host, CLKENA, 0);
2665 mci_writel(host, CLKSRC, 0);
2668 * In 2.40a spec, Data offset is changed.
2669 * Need to check the version-id and set data-offset for DATA register.
2671 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
2672 dev_info(host->dev, "Version ID is %04x\n", host->verid);
2674 if (host->verid < DW_MMC_240A)
2675 host->data_offset = DATA_OFFSET;
2677 host->data_offset = DATA_240A_OFFSET;
2679 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
2680 host->card_workqueue = alloc_workqueue("dw-mci-card",
2682 if (!host->card_workqueue) {
2686 INIT_WORK(&host->card_work, dw_mci_work_routine_card);
2687 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
2688 host->irq_flags, "dw-mci", host);
2692 if (host->pdata->num_slots)
2693 host->num_slots = host->pdata->num_slots;
2695 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
2698 * Enable interrupts for command done, data over, data empty, card det,
2699 * receive ready and error such as transmit, receive timeout, crc error
2701 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2702 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2703 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2704 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2705 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
2707 dev_info(host->dev, "DW MMC controller at irq %d, "
2708 "%d bit host data width, "
2710 host->irq, width, fifo_size);
2712 /* We need at least one slot to succeed */
2713 for (i = 0; i < host->num_slots; i++) {
2714 ret = dw_mci_init_slot(host, i);
2716 dev_dbg(host->dev, "slot %d init failed\n", i);
2722 dev_info(host->dev, "%d slots initialized\n", init_slots);
2724 dev_dbg(host->dev, "attempted to initialize %d slots, "
2725 "but failed on all\n", host->num_slots);
2729 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
2730 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
2735 destroy_workqueue(host->card_workqueue);
2738 if (host->use_dma && host->dma_ops->exit)
2739 host->dma_ops->exit(host);
2742 if (!IS_ERR(host->ciu_clk))
2743 clk_disable_unprepare(host->ciu_clk);
2746 if (!IS_ERR(host->biu_clk))
2747 clk_disable_unprepare(host->biu_clk);
2751 EXPORT_SYMBOL(dw_mci_probe);
2753 void dw_mci_remove(struct dw_mci *host)
2757 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2758 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2760 for (i = 0; i < host->num_slots; i++) {
2761 dev_dbg(host->dev, "remove slot %d\n", i);
2763 dw_mci_cleanup_slot(host->slot[i], i);
2766 /* disable clock to CIU */
2767 mci_writel(host, CLKENA, 0);
2768 mci_writel(host, CLKSRC, 0);
2770 destroy_workqueue(host->card_workqueue);
2772 if (host->use_dma && host->dma_ops->exit)
2773 host->dma_ops->exit(host);
2775 if (!IS_ERR(host->ciu_clk))
2776 clk_disable_unprepare(host->ciu_clk);
2778 if (!IS_ERR(host->biu_clk))
2779 clk_disable_unprepare(host->biu_clk);
2781 EXPORT_SYMBOL(dw_mci_remove);
2785 #ifdef CONFIG_PM_SLEEP
2787 * TODO: we should probably disable the clock to the card in the suspend path.
2789 int dw_mci_suspend(struct dw_mci *host)
2793 EXPORT_SYMBOL(dw_mci_suspend);
2795 int dw_mci_resume(struct dw_mci *host)
2799 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
2804 if (host->use_dma && host->dma_ops->init)
2805 host->dma_ops->init(host);
2808 * Restore the initial value at FIFOTH register
2809 * And Invalidate the prev_blksz with zero
2811 mci_writel(host, FIFOTH, host->fifoth_val);
2812 host->prev_blksz = 0;
2814 /* Put in max timeout */
2815 mci_writel(host, TMOUT, 0xFFFFFFFF);
2817 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2818 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2819 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2820 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2821 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2823 for (i = 0; i < host->num_slots; i++) {
2824 struct dw_mci_slot *slot = host->slot[i];
2827 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
2828 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
2829 dw_mci_setup_bus(slot, true);
2834 EXPORT_SYMBOL(dw_mci_resume);
2835 #endif /* CONFIG_PM_SLEEP */
2837 static int __init dw_mci_init(void)
2839 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
2843 static void __exit dw_mci_exit(void)
2847 module_init(dw_mci_init);
2848 module_exit(dw_mci_exit);
2850 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
2851 MODULE_AUTHOR("NXP Semiconductor VietNam");
2852 MODULE_AUTHOR("Imagination Technologies Ltd");
2853 MODULE_LICENSE("GPL v2");