2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
17 #define DW_MMC_240A 0x240a
19 #define SDMMC_CTRL 0x000
20 #define SDMMC_PWREN 0x004
21 #define SDMMC_CLKDIV 0x008
22 #define SDMMC_CLKSRC 0x00c
23 #define SDMMC_CLKENA 0x010
24 #define SDMMC_TMOUT 0x014
25 #define SDMMC_CTYPE 0x018
26 #define SDMMC_BLKSIZ 0x01c
27 #define SDMMC_BYTCNT 0x020
28 #define SDMMC_INTMASK 0x024
29 #define SDMMC_CMDARG 0x028
30 #define SDMMC_CMD 0x02c
31 #define SDMMC_RESP0 0x030
32 #define SDMMC_RESP1 0x034
33 #define SDMMC_RESP2 0x038
34 #define SDMMC_RESP3 0x03c
35 #define SDMMC_MINTSTS 0x040
36 #define SDMMC_RINTSTS 0x044
37 #define SDMMC_STATUS 0x048
38 #define SDMMC_FIFOTH 0x04c
39 #define SDMMC_CDETECT 0x050
40 #define SDMMC_WRTPRT 0x054
41 #define SDMMC_GPIO 0x058
42 #define SDMMC_TCBCNT 0x05c
43 #define SDMMC_TBBCNT 0x060
44 #define SDMMC_DEBNCE 0x064
45 #define SDMMC_USRID 0x068
46 #define SDMMC_VERID 0x06c
47 #define SDMMC_HCON 0x070
48 #define SDMMC_UHS_REG 0x074
49 #define SDMMC_BMOD 0x080
50 #define SDMMC_PLDMND 0x084
51 #define SDMMC_DBADDR 0x088
52 #define SDMMC_IDSTS 0x08c
53 #define SDMMC_IDINTEN 0x090
54 #define SDMMC_DSCADDR 0x094
55 #define SDMMC_BUFADDR 0x098
56 #define SDMMC_CDTHRCTL 0x100
57 #define SDMMC_DATA(x) (x)
60 * Data offset is difference according to Version
61 * Lower than 2.40a : data register offest is 0x100
63 #define DATA_OFFSET 0x100
64 #define DATA_240A_OFFSET 0x200
67 #define _SBF(f, v) ((v) << (f))
69 /* Control register defines */
70 #define SDMMC_CTRL_USE_IDMAC BIT(25)
71 #define SDMMC_CTRL_CEATA_INT_EN BIT(11)
72 #define SDMMC_CTRL_SEND_AS_CCSD BIT(10)
73 #define SDMMC_CTRL_SEND_CCSD BIT(9)
74 #define SDMMC_CTRL_ABRT_READ_DATA BIT(8)
75 #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7)
76 #define SDMMC_CTRL_READ_WAIT BIT(6)
77 #define SDMMC_CTRL_DMA_ENABLE BIT(5)
78 #define SDMMC_CTRL_INT_ENABLE BIT(4)
79 #define SDMMC_CTRL_DMA_RESET BIT(2)
80 #define SDMMC_CTRL_FIFO_RESET BIT(1)
81 #define SDMMC_CTRL_RESET BIT(0)
82 /* Clock Enable register defines */
83 #define SDMMC_CLKEN_LOW_PWR BIT(16)
84 #define SDMMC_CLKEN_ENABLE BIT(0)
85 /* time-out register defines */
86 #define SDMMC_TMOUT_DATA(n) _SBF(8, (n))
87 #define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00
88 #define SDMMC_TMOUT_RESP(n) ((n) & 0xFF)
89 #define SDMMC_TMOUT_RESP_MSK 0xFF
90 /* card-type register defines */
91 #define SDMMC_CTYPE_8BIT BIT(16)
92 #define SDMMC_CTYPE_4BIT BIT(0)
93 #define SDMMC_CTYPE_1BIT 0
94 /* Interrupt status & mask register defines */
95 #define SDMMC_INT_SDIO(n) BIT(16 + (n))
96 #define SDMMC_INT_EBE BIT(15)
97 #define SDMMC_INT_ACD BIT(14)
98 #define SDMMC_INT_SBE BIT(13)
99 #define SDMMC_INT_HLE BIT(12)
100 #define SDMMC_INT_FRUN BIT(11)
101 #define SDMMC_INT_HTO BIT(10)
102 #define SDMMC_INT_VOLT_SWITCH BIT(10) /* overloads bit 10! */
103 #define SDMMC_INT_DRTO BIT(9)
104 #define SDMMC_INT_RTO BIT(8)
105 #define SDMMC_INT_DCRC BIT(7)
106 #define SDMMC_INT_RCRC BIT(6)
107 #define SDMMC_INT_RXDR BIT(5)
108 #define SDMMC_INT_TXDR BIT(4)
109 #define SDMMC_INT_DATA_OVER BIT(3)
110 #define SDMMC_INT_CMD_DONE BIT(2)
111 #define SDMMC_INT_RESP_ERR BIT(1)
112 #define SDMMC_INT_CD BIT(0)
113 #define SDMMC_INT_ERROR 0xbfc2
114 /* Command register defines */
115 #define SDMMC_CMD_START BIT(31)
116 #define SDMMC_CMD_USE_HOLD_REG BIT(29)
117 #define SDMMC_CMD_VOLT_SWITCH BIT(28)
118 #define SDMMC_CMD_CCS_EXP BIT(23)
119 #define SDMMC_CMD_CEATA_RD BIT(22)
120 #define SDMMC_CMD_UPD_CLK BIT(21)
121 #define SDMMC_CMD_INIT BIT(15)
122 #define SDMMC_CMD_STOP BIT(14)
123 #define SDMMC_CMD_PRV_DAT_WAIT BIT(13)
124 #define SDMMC_CMD_SEND_STOP BIT(12)
125 #define SDMMC_CMD_STRM_MODE BIT(11)
126 #define SDMMC_CMD_DAT_WR BIT(10)
127 #define SDMMC_CMD_DAT_EXP BIT(9)
128 #define SDMMC_CMD_RESP_CRC BIT(8)
129 #define SDMMC_CMD_RESP_LONG BIT(7)
130 #define SDMMC_CMD_RESP_EXP BIT(6)
131 #define SDMMC_CMD_INDX(n) ((n) & 0x1F)
132 /* Status register defines */
133 #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF)
134 #define SDMMC_STATUS_DMA_REQ BIT(31)
135 #define SDMMC_STATUS_BUSY BIT(9)
136 /* FIFOTH register defines */
137 #define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \
138 ((r) & 0xFFF) << 16 | \
140 /* Internal DMAC interrupt defines */
141 #define SDMMC_IDMAC_INT_AI BIT(9)
142 #define SDMMC_IDMAC_INT_NI BIT(8)
143 #define SDMMC_IDMAC_INT_CES BIT(5)
144 #define SDMMC_IDMAC_INT_DU BIT(4)
145 #define SDMMC_IDMAC_INT_FBE BIT(2)
146 #define SDMMC_IDMAC_INT_RI BIT(1)
147 #define SDMMC_IDMAC_INT_TI BIT(0)
148 /* Internal DMAC bus mode bits */
149 #define SDMMC_IDMAC_ENABLE BIT(7)
150 #define SDMMC_IDMAC_FB BIT(1)
151 #define SDMMC_IDMAC_SWRESET BIT(0)
152 /* Version ID register define */
153 #define SDMMC_GET_VERID(x) ((x) & 0xFFFF)
154 /* Card read threshold */
155 #define SDMMC_SET_RD_THLD(v, x) (((v) & 0x1FFF) << 16 | (x))
156 #define SDMMC_UHS_18V BIT(0)
157 /* All ctrl reset bits */
158 #define SDMMC_CTRL_ALL_RESET_FLAGS \
159 (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET)
161 /* Register access macros */
162 #define mci_readl(dev, reg) \
163 __raw_readl((dev)->regs + SDMMC_##reg)
164 #define mci_writel(dev, reg, value) \
165 __raw_writel((value), (dev)->regs + SDMMC_##reg)
167 /* 16-bit FIFO access macros */
168 #define mci_readw(dev, reg) \
169 __raw_readw((dev)->regs + SDMMC_##reg)
170 #define mci_writew(dev, reg, value) \
171 __raw_writew((value), (dev)->regs + SDMMC_##reg)
173 /* 64-bit FIFO access macros */
175 #define mci_readq(dev, reg) \
176 __raw_readq((dev)->regs + SDMMC_##reg)
177 #define mci_writeq(dev, reg, value) \
178 __raw_writeq((value), (dev)->regs + SDMMC_##reg)
181 * Dummy readq implementation for architectures that don't define it.
183 * We would assume that none of these architectures would configure
184 * the IP block with a 64bit FIFO width, so this code will never be
185 * executed on those machines. Defining these macros here keeps the
186 * rest of the code free from ifdefs.
188 #define mci_readq(dev, reg) \
189 (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg))
190 #define mci_writeq(dev, reg, value) \
191 (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value))
194 extern int dw_mci_probe(struct dw_mci *host);
195 extern void dw_mci_remove(struct dw_mci *host);
196 #ifdef CONFIG_PM_SLEEP
197 extern int dw_mci_suspend(struct dw_mci *host);
198 extern int dw_mci_resume(struct dw_mci *host);
202 * struct dw_mci_slot - MMC slot state
203 * @mmc: The mmc_host representing this slot.
204 * @host: The MMC controller this slot is using.
205 * @quirks: Slot-level quirks (DW_MCI_SLOT_QUIRK_XXX)
206 * @ctype: Card type for this slot.
207 * @mrq: mmc_request currently being processed or waiting to be
208 * processed, or NULL when the slot is idle.
209 * @queue_node: List node for placing this node in the @queue list of
211 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
212 * @__clk_old: The last updated clock with reflecting clock divider.
213 * Keeping track of this helps us to avoid spamming the console
214 * with CONFIG_MMC_CLKGATE.
215 * @flags: Random state bits associated with the slot.
216 * @id: Number of this slot.
217 * @last_detect_state: Most recently observed card detect state.
220 struct mmc_host *mmc;
227 struct mmc_request *mrq;
228 struct list_head queue_node;
231 unsigned int __clk_old;
234 #define DW_MMC_CARD_PRESENT 0
235 #define DW_MMC_CARD_NEED_INIT 1
237 int last_detect_state;
240 struct dw_mci_tuning_data {
241 const u8 *blk_pattern;
246 * dw_mci driver data - dw-mshc implementation specific driver data.
247 * @caps: mmc subsystem specified capabilities of the controller(s).
248 * @init: early implementation specific initialization.
249 * @setup_clock: implementation specific clock configuration.
250 * @prepare_command: handle CMD register extensions.
251 * @set_ios: handle bus specific extensions.
252 * @parse_dt: parse implementation specific device tree properties.
253 * @execute_tuning: implementation specific tuning procedure.
255 * Provide controller implementation specific extensions. The usage of this
256 * data structure is fully optional and usage of each member in this structure
257 * is optional as well.
259 struct dw_mci_drv_data {
261 int (*init)(struct dw_mci *host);
262 int (*setup_clock)(struct dw_mci *host);
263 void (*prepare_command)(struct dw_mci *host, u32 *cmdr);
264 void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios);
265 int (*parse_dt)(struct dw_mci *host);
266 int (*execute_tuning)(struct dw_mci_slot *slot, u32 opcode,
267 struct dw_mci_tuning_data *tuning_data);
269 #endif /* _DW_MMC_H_ */