drivers/mmc/host/rtsx_pci_sdmmc.c

   1 /* Realtek PCI-Express SD/MMC Card Interface driver
   2  *
   3  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   Wei WANG <wei_wang@realsil.com.cn>
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/slab.h>
  24 #include <linux/highmem.h>
  25 #include <linux/delay.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/workqueue.h>
  28 #include <linux/mmc/host.h>
  29 #include <linux/mmc/mmc.h>
  30 #include <linux/mmc/sd.h>
  31 #include <linux/mmc/sdio.h>
  32 #include <linux/mmc/card.h>
  33 #include <linux/mfd/rtsx_pci.h>
  34 #include <asm/unaligned.h>
  35
  36 struct realtek_pci_sdmmc {
  37         struct platform_device  *pdev;
  38         struct rtsx_pcr         *pcr;
  39         struct mmc_host         *mmc;
  40         struct mmc_request      *mrq;
  41 #define SDMMC_WORKQ_NAME        "rtsx_pci_sdmmc_workq"
  42
  43         struct work_struct      work;
  44         struct mutex            host_mutex;
  45
  46         u8                      ssc_depth;
  47         unsigned int            clock;
  48         bool                    vpclk;
  49         bool                    double_clk;
  50         bool                    eject;
  51         bool                    initial_mode;
  52         int                     power_state;
  53 #define SDMMC_POWER_ON          1
  54 #define SDMMC_POWER_OFF         0
  55
  56         int                     sg_count;
  57         s32                     cookie;
  58         int                     cookie_sg_count;
  59         bool                    using_cookie;
  60 };
  61
  62 static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
  63 {
  64         return &(host->pdev->dev);
  65 }
  66
  67 static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
  68 {
  69         rtsx_pci_write_register(host->pcr, CARD_STOP,
  70                         SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
  71 }
  72
  73 #ifdef DEBUG
  74 static void dump_reg_range(struct realtek_pci_sdmmc *host, u16 start, u16 end)
  75 {
  76         u16 len = end - start + 1;
  77         int i;
  78         u8 data[8];
  79
  80         for (i = 0; i < len; i += 8) {
  81                 int j;
  82                 int n = min(8, len - i);
  83
  84                 memset(&data, 0, sizeof(data));
  85                 for (j = 0; j < n; j++)
  86                         rtsx_pci_read_register(host->pcr, start + i + j,
  87                                 data + j);
  88                 dev_dbg(sdmmc_dev(host), "0x%04X(%d): %8ph\n",
  89                         start + i, n, data);
  90         }
  91 }
  92
  93 static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
  94 {
  95         dump_reg_range(host, 0xFDA0, 0xFDB3);
  96         dump_reg_range(host, 0xFD52, 0xFD69);
  97 }
  98 #else
  99 #define sd_print_debug_regs(host)
 100 #endif /* DEBUG */
 101
 102 static inline int sd_get_cd_int(struct realtek_pci_sdmmc *host)
 103 {
 104         return rtsx_pci_readl(host->pcr, RTSX_BIPR) & SD_EXIST;
 105 }
 106
 107 static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd)
 108 {
 109         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF,
 110                 SD_CMD_START | cmd->opcode);
 111         rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg);
 112 }
 113
 114 static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz)
 115 {
 116         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks);
 117         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8);
 118         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz);
 119         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8);
 120 }
 121
 122 static int sd_response_type(struct mmc_command *cmd)
 123 {
 124         switch (mmc_resp_type(cmd)) {
 125         case MMC_RSP_NONE:
 126                 return SD_RSP_TYPE_R0;
 127         case MMC_RSP_R1:
 128                 return SD_RSP_TYPE_R1;
 129         case MMC_RSP_R1_NO_CRC:
 130                 return SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7;
 131         case MMC_RSP_R1B:
 132                 return SD_RSP_TYPE_R1b;
 133         case MMC_RSP_R2:
 134                 return SD_RSP_TYPE_R2;
 135         case MMC_RSP_R3:
 136                 return SD_RSP_TYPE_R3;
 137         default:
 138                 return -EINVAL;
 139         }
 140 }
 141
 142 static int sd_status_index(int resp_type)
 143 {
 144         if (resp_type == SD_RSP_TYPE_R0)
 145                 return 0;
 146         else if (resp_type == SD_RSP_TYPE_R2)
 147                 return 16;
 148
 149         return 5;
 150 }
 151 /*
 152  * sd_pre_dma_transfer - do dma_map_sg() or using cookie
 153  *
 154  * @pre: if called in pre_req()
 155  * return:
 156  *      0 - do dma_map_sg()
 157  *      1 - using cookie
 158  */
 159 static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host,
 160                 struct mmc_data *data, bool pre)
 161 {
 162         struct rtsx_pcr *pcr = host->pcr;
 163         int read = data->flags & MMC_DATA_READ;
 164         int count = 0;
 165         int using_cookie = 0;
 166
 167         if (!pre && data->host_cookie && data->host_cookie != host->cookie) {
 168                 dev_err(sdmmc_dev(host),
 169                         "error: data->host_cookie = %d, host->cookie = %d\n",
 170                         data->host_cookie, host->cookie);
 171                 data->host_cookie = 0;
 172         }
 173
 174         if (pre || data->host_cookie != host->cookie) {
 175                 count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read);
 176         } else {
 177                 count = host->cookie_sg_count;
 178                 using_cookie = 1;
 179         }
 180
 181         if (pre) {
 182                 host->cookie_sg_count = count;
 183                 if (++host->cookie < 0)
 184                         host->cookie = 1;
 185                 data->host_cookie = host->cookie;
 186         } else {
 187                 host->sg_count = count;
 188         }
 189
 190         return using_cookie;
 191 }
 192
 193 static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
 194                 bool is_first_req)
 195 {
 196         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
 197         struct mmc_data *data = mrq->data;
 198
 199         if (data->host_cookie) {
 200                 dev_err(sdmmc_dev(host),
 201                         "error: reset data->host_cookie = %d\n",
 202                         data->host_cookie);
 203                 data->host_cookie = 0;
 204         }
 205
 206         sd_pre_dma_transfer(host, data, true);
 207         dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count);
 208 }
 209
 210 static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
 211                 int err)
 212 {
 213         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
 214         struct rtsx_pcr *pcr = host->pcr;
 215         struct mmc_data *data = mrq->data;
 216         int read = data->flags & MMC_DATA_READ;
 217
 218         rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read);
 219         data->host_cookie = 0;
 220 }
 221
 222 static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
 223                 struct mmc_command *cmd)
 224 {
 225         struct rtsx_pcr *pcr = host->pcr;
 226         u8 cmd_idx = (u8)cmd->opcode;
 227         u32 arg = cmd->arg;
 228         int err = 0;
 229         int timeout = 100;
 230         int i;
 231         u8 *ptr;
 232         int rsp_type;
 233         int stat_idx;
 234         bool clock_toggled = false;
 235
 236         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 237                         __func__, cmd_idx, arg);
 238
 239         rsp_type = sd_response_type(cmd);
 240         if (rsp_type < 0)
 241                 goto out;
 242
 243         stat_idx = sd_status_index(rsp_type);
 244
 245         if (rsp_type == SD_RSP_TYPE_R1b)
 246                 timeout = cmd->busy_timeout ? cmd->busy_timeout : 3000;
 247
 248         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
 249                 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
 250                                 0xFF, SD_CLK_TOGGLE_EN);
 251                 if (err < 0)
 252                         goto out;
 253
 254                 clock_toggled = true;
 255         }
 256
 257         rtsx_pci_init_cmd(pcr);
 258         sd_cmd_set_sd_cmd(pcr, cmd);
 259         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
 260         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
 261                         0x01, PINGPONG_BUFFER);
 262         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
 263                         0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
 264         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 265                      SD_TRANSFER_END | SD_STAT_IDLE,
 266                      SD_TRANSFER_END | SD_STAT_IDLE);
 267
 268         if (rsp_type == SD_RSP_TYPE_R2) {
 269                 /* Read data from ping-pong buffer */
 270                 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
 271                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
 272         } else if (rsp_type != SD_RSP_TYPE_R0) {
 273                 /* Read data from SD_CMDx registers */
 274                 for (i = SD_CMD0; i <= SD_CMD4; i++)
 275                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
 276         }
 277
 278         rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
 279
 280         err = rtsx_pci_send_cmd(pcr, timeout);
 281         if (err < 0) {
 282                 sd_print_debug_regs(host);
 283                 sd_clear_error(host);
 284                 dev_dbg(sdmmc_dev(host),
 285                         "rtsx_pci_send_cmd error (err = %d)\n", err);
 286                 goto out;
 287         }
 288
 289         if (rsp_type == SD_RSP_TYPE_R0) {
 290                 err = 0;
 291                 goto out;
 292         }
 293
 294         /* Eliminate returned value of CHECK_REG_CMD */
 295         ptr = rtsx_pci_get_cmd_data(pcr) + 1;
 296
 297         /* Check (Start,Transmission) bit of Response */
 298         if ((ptr[0] & 0xC0) != 0) {
 299                 err = -EILSEQ;
 300                 dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
 301                 goto out;
 302         }
 303
 304         /* Check CRC7 */
 305         if (!(rsp_type & SD_NO_CHECK_CRC7)) {
 306                 if (ptr[stat_idx] & SD_CRC7_ERR) {
 307                         err = -EILSEQ;
 308                         dev_dbg(sdmmc_dev(host), "CRC7 error\n");
 309                         goto out;
 310                 }
 311         }
 312
 313         if (rsp_type == SD_RSP_TYPE_R2) {
 314                 /*
 315                  * The controller offloads the last byte {CRC-7, end bit 1'b1}
 316                  * of response type R2. Assign dummy CRC, 0, and end bit to the
 317                  * byte(ptr[16], goes into the LSB of resp[3] later).
 318                  */
 319                 ptr[16] = 1;
 320
 321                 for (i = 0; i < 4; i++) {
 322                         cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
 323                         dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
 324                                         i, cmd->resp[i]);
 325                 }
 326         } else {
 327                 cmd->resp[0] = get_unaligned_be32(ptr + 1);
 328                 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
 329                                 cmd->resp[0]);
 330         }
 331
 332 out:
 333         cmd->error = err;
 334
 335         if (err && clock_toggled)
 336                 rtsx_pci_write_register(pcr, SD_BUS_STAT,
 337                                 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
 338 }
 339
 340 static int sd_read_data(struct realtek_pci_sdmmc *host, struct mmc_command *cmd,
 341         u16 byte_cnt, u8 *buf, int buf_len, int timeout)
 342 {
 343         struct rtsx_pcr *pcr = host->pcr;
 344         int err;
 345         u8 trans_mode;
 346
 347         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 348                 __func__, cmd->opcode, cmd->arg);
 349
 350         if (!buf)
 351                 buf_len = 0;
 352
 353         if (cmd->opcode == MMC_SEND_TUNING_BLOCK)
 354                 trans_mode = SD_TM_AUTO_TUNING;
 355         else
 356                 trans_mode = SD_TM_NORMAL_READ;
 357
 358         rtsx_pci_init_cmd(pcr);
 359         sd_cmd_set_sd_cmd(pcr, cmd);
 360         sd_cmd_set_data_len(pcr, 1, byte_cnt);
 361         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
 362                         SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 363                         SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
 364         if (trans_mode != SD_TM_AUTO_TUNING)
 365                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 366                                 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
 367
 368         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
 369                         0xFF, trans_mode | SD_TRANSFER_START);
 370         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 371                         SD_TRANSFER_END, SD_TRANSFER_END);
 372
 373         err = rtsx_pci_send_cmd(pcr, timeout);
 374         if (err < 0) {
 375                 sd_print_debug_regs(host);
 376                 dev_dbg(sdmmc_dev(host),
 377                         "rtsx_pci_send_cmd fail (err = %d)\n", err);
 378                 return err;
 379         }
 380
 381         if (buf && buf_len) {
 382                 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
 383                 if (err < 0) {
 384                         dev_dbg(sdmmc_dev(host),
 385                                 "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
 386                         return err;
 387                 }
 388         }
 389
 390         return 0;
 391 }
 392
 393 static int sd_write_data(struct realtek_pci_sdmmc *host,
 394         struct mmc_command *cmd, u16 byte_cnt, u8 *buf, int buf_len,
 395         int timeout)
 396 {
 397         struct rtsx_pcr *pcr = host->pcr;
 398         int err;
 399
 400         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 401                 __func__, cmd->opcode, cmd->arg);
 402
 403         if (!buf)
 404                 buf_len = 0;
 405
 406         sd_send_cmd_get_rsp(host, cmd);
 407         if (cmd->error)
 408                 return cmd->error;
 409
 410         if (buf && buf_len) {
 411                 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
 412                 if (err < 0) {
 413                         dev_dbg(sdmmc_dev(host),
 414                                 "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
 415                         return err;
 416                 }
 417         }
 418
 419         rtsx_pci_init_cmd(pcr);
 420         sd_cmd_set_data_len(pcr, 1, byte_cnt);
 421         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
 422                 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 423                 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0);
 424         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 425                         SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
 426         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 427                         SD_TRANSFER_END, SD_TRANSFER_END);
 428
 429         err = rtsx_pci_send_cmd(pcr, timeout);
 430         if (err < 0) {
 431                 sd_print_debug_regs(host);
 432                 dev_dbg(sdmmc_dev(host),
 433                         "rtsx_pci_send_cmd fail (err = %d)\n", err);
 434                 return err;
 435         }
 436
 437         return 0;
 438 }
 439
 440 static int sd_read_long_data(struct realtek_pci_sdmmc *host,
 441         struct mmc_request *mrq)
 442 {
 443         struct rtsx_pcr *pcr = host->pcr;
 444         struct mmc_host *mmc = host->mmc;
 445         struct mmc_card *card = mmc->card;
 446         struct mmc_command *cmd = mrq->cmd;
 447         struct mmc_data *data = mrq->data;
 448         int uhs = mmc_card_uhs(card);
 449         u8 cfg2 = 0;
 450         int err;
 451         int resp_type;
 452         size_t data_len = data->blksz * data->blocks;
 453
 454         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 455                 __func__, cmd->opcode, cmd->arg);
 456
 457         resp_type = sd_response_type(cmd);
 458         if (resp_type < 0)
 459                 return resp_type;
 460
 461         if (!uhs)
 462                 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
 463
 464         rtsx_pci_init_cmd(pcr);
 465         sd_cmd_set_sd_cmd(pcr, cmd);
 466         sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
 467         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
 468                         DMA_DONE_INT, DMA_DONE_INT);
 469         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
 470                 0xFF, (u8)(data_len >> 24));
 471         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
 472                 0xFF, (u8)(data_len >> 16));
 473         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
 474                 0xFF, (u8)(data_len >> 8));
 475         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
 476         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
 477                 0x03 | DMA_PACK_SIZE_MASK,
 478                 DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
 479         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
 480                         0x01, RING_BUFFER);
 481         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type);
 482         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 483                         SD_TRANSFER_START | SD_TM_AUTO_READ_2);
 484         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 485                         SD_TRANSFER_END, SD_TRANSFER_END);
 486         rtsx_pci_send_cmd_no_wait(pcr);
 487
 488         err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000);
 489         if (err < 0) {
 490                 sd_print_debug_regs(host);
 491                 sd_clear_error(host);
 492                 return err;
 493         }
 494
 495         return 0;
 496 }
 497
 498 static int sd_write_long_data(struct realtek_pci_sdmmc *host,
 499         struct mmc_request *mrq)
 500 {
 501         struct rtsx_pcr *pcr = host->pcr;
 502         struct mmc_host *mmc = host->mmc;
 503         struct mmc_card *card = mmc->card;
 504         struct mmc_command *cmd = mrq->cmd;
 505         struct mmc_data *data = mrq->data;
 506         int uhs = mmc_card_uhs(card);
 507         u8 cfg2;
 508         int err;
 509         size_t data_len = data->blksz * data->blocks;
 510
 511         sd_send_cmd_get_rsp(host, cmd);
 512         if (cmd->error)
 513                 return cmd->error;
 514
 515         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 516                 __func__, cmd->opcode, cmd->arg);
 517
 518         cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 519                 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
 520
 521         if (!uhs)
 522                 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
 523
 524         rtsx_pci_init_cmd(pcr);
 525         sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
 526         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
 527                         DMA_DONE_INT, DMA_DONE_INT);
 528         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
 529                 0xFF, (u8)(data_len >> 24));
 530         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
 531                 0xFF, (u8)(data_len >> 16));
 532         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
 533                 0xFF, (u8)(data_len >> 8));
 534         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
 535         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
 536                 0x03 | DMA_PACK_SIZE_MASK,
 537                 DMA_DIR_TO_CARD | DMA_EN | DMA_512);
 538         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
 539                         0x01, RING_BUFFER);
 540         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
 541         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 542                         SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
 543         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 544                         SD_TRANSFER_END, SD_TRANSFER_END);
 545         rtsx_pci_send_cmd_no_wait(pcr);
 546         err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000);
 547         if (err < 0) {
 548                 sd_clear_error(host);
 549                 return err;
 550         }
 551
 552         return 0;
 553 }
 554
 555 static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
 556 {
 557         struct mmc_data *data = mrq->data;
 558
 559         if (host->sg_count < 0) {
 560                 data->error = host->sg_count;
 561                 dev_dbg(sdmmc_dev(host), "%s: sg_count = %d is invalid\n",
 562                         __func__, host->sg_count);
 563                 return data->error;
 564         }
 565
 566         if (data->flags & MMC_DATA_READ)
 567                 return sd_read_long_data(host, mrq);
 568
 569         return sd_write_long_data(host, mrq);
 570 }
 571
 572 static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
 573 {
 574         rtsx_pci_write_register(host->pcr, SD_CFG1,
 575                         SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
 576 }
 577
 578 static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
 579 {
 580         rtsx_pci_write_register(host->pcr, SD_CFG1,
 581                         SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
 582 }
 583
 584 static void sd_normal_rw(struct realtek_pci_sdmmc *host,
 585                 struct mmc_request *mrq)
 586 {
 587         struct mmc_command *cmd = mrq->cmd;
 588         struct mmc_data *data = mrq->data;
 589         u8 *buf;
 590
 591         buf = kzalloc(data->blksz, GFP_NOIO);
 592         if (!buf) {
 593                 cmd->error = -ENOMEM;
 594                 return;
 595         }
 596
 597         if (data->flags & MMC_DATA_READ) {
 598                 if (host->initial_mode)
 599                         sd_disable_initial_mode(host);
 600
 601                 cmd->error = sd_read_data(host, cmd, (u16)data->blksz, buf,
 602                                 data->blksz, 200);
 603
 604                 if (host->initial_mode)
 605                         sd_enable_initial_mode(host);
 606
 607                 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
 608         } else {
 609                 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
 610
 611                 cmd->error = sd_write_data(host, cmd, (u16)data->blksz, buf,
 612                                 data->blksz, 200);
 613         }
 614
 615         kfree(buf);
 616 }
 617
 618 static int sd_change_phase(struct realtek_pci_sdmmc *host,
 619                 u8 sample_point, bool rx)
 620 {
 621         struct rtsx_pcr *pcr = host->pcr;
 622         int err;
 623
 624         dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",
 625                         __func__, rx ? "RX" : "TX", sample_point);
 626
 627         rtsx_pci_init_cmd(pcr);
 628
 629         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
 630         if (rx)
 631                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 632                                 SD_VPRX_CTL, 0x1F, sample_point);
 633         else
 634                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 635                                 SD_VPTX_CTL, 0x1F, sample_point);
 636         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
 637         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
 638                         PHASE_NOT_RESET, PHASE_NOT_RESET);
 639         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0);
 640         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
 641
 642         err = rtsx_pci_send_cmd(pcr, 100);
 643         if (err < 0)
 644                 return err;
 645
 646         return 0;
 647 }
 648
 649 static inline u32 test_phase_bit(u32 phase_map, unsigned int bit)
 650 {
 651         bit %= RTSX_PHASE_MAX;
 652         return phase_map & (1 << bit);
 653 }
 654
 655 static int sd_get_phase_len(u32 phase_map, unsigned int start_bit)
 656 {
 657         int i;
 658
 659         for (i = 0; i < RTSX_PHASE_MAX; i++) {
 660                 if (test_phase_bit(phase_map, start_bit + i) == 0)
 661                         return i;
 662         }
 663         return RTSX_PHASE_MAX;
 664 }
 665
 666 static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
 667 {
 668         int start = 0, len = 0;
 669         int start_final = 0, len_final = 0;
 670         u8 final_phase = 0xFF;
 671
 672         if (phase_map == 0) {
 673                 dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map);
 674                 return final_phase;
 675         }
 676
 677         while (start < RTSX_PHASE_MAX) {
 678                 len = sd_get_phase_len(phase_map, start);
 679                 if (len_final < len) {
 680                         start_final = start;
 681                         len_final = len;
 682                 }
 683                 start += len ? len : 1;
 684         }
 685
 686         final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX;
 687         dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n",
 688                 phase_map, len_final, final_phase);
 689
 690         return final_phase;
 691 }
 692
 693 static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
 694 {
 695         int err, i;
 696         u8 val = 0;
 697
 698         for (i = 0; i < 100; i++) {
 699                 err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
 700                 if (val & SD_DATA_IDLE)
 701                         return;
 702
 703                 udelay(100);
 704         }
 705 }
 706
 707 static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
 708                 u8 opcode, u8 sample_point)
 709 {
 710         int err;
 711         struct mmc_command cmd = {0};
 712
 713         err = sd_change_phase(host, sample_point, true);
 714         if (err < 0)
 715                 return err;
 716
 717         cmd.opcode = opcode;
 718         err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100);
 719         if (err < 0) {
 720                 /* Wait till SD DATA IDLE */
 721                 sd_wait_data_idle(host);
 722                 sd_clear_error(host);
 723                 return err;
 724         }
 725
 726         return 0;
 727 }
 728
 729 static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
 730                 u8 opcode, u32 *phase_map)
 731 {
 732         int err, i;
 733         u32 raw_phase_map = 0;
 734
 735         for (i = 0; i < RTSX_PHASE_MAX; i++) {
 736                 err = sd_tuning_rx_cmd(host, opcode, (u8)i);
 737                 if (err == 0)
 738                         raw_phase_map |= 1 << i;
 739         }
 740
 741         if (phase_map)
 742                 *phase_map = raw_phase_map;
 743
 744         return 0;
 745 }
 746
 747 static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
 748 {
 749         int err, i;
 750         u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
 751         u8 final_phase;
 752
 753         for (i = 0; i < RX_TUNING_CNT; i++) {
 754                 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
 755                 if (err < 0)
 756                         return err;
 757
 758                 if (raw_phase_map[i] == 0)
 759                         break;
 760         }
 761
 762         phase_map = 0xFFFFFFFF;
 763         for (i = 0; i < RX_TUNING_CNT; i++) {
 764                 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
 765                                 i, raw_phase_map[i]);
 766                 phase_map &= raw_phase_map[i];
 767         }
 768         dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
 769
 770         if (phase_map) {
 771                 final_phase = sd_search_final_phase(host, phase_map);
 772                 if (final_phase == 0xFF)
 773                         return -EINVAL;
 774
 775                 err = sd_change_phase(host, final_phase, true);
 776                 if (err < 0)
 777                         return err;
 778         } else {
 779                 return -EINVAL;
 780         }
 781
 782         return 0;
 783 }
 784
 785 static inline int sdio_extblock_cmd(struct mmc_command *cmd,
 786         struct mmc_data *data)
 787 {
 788         return (cmd->opcode == SD_IO_RW_EXTENDED) && (data->blksz == 512);
 789 }
 790
 791 static inline int sd_rw_cmd(struct mmc_command *cmd)
 792 {
 793         return mmc_op_multi(cmd->opcode) ||
 794                 (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
 795                 (cmd->opcode == MMC_WRITE_BLOCK);
 796 }
 797
 798 static void sd_request(struct work_struct *work)
 799 {
 800         struct realtek_pci_sdmmc *host = container_of(work,
 801                         struct realtek_pci_sdmmc, work);
 802         struct rtsx_pcr *pcr = host->pcr;
 803
 804         struct mmc_host *mmc = host->mmc;
 805         struct mmc_request *mrq = host->mrq;
 806         struct mmc_command *cmd = mrq->cmd;
 807         struct mmc_data *data = mrq->data;
 808
 809         unsigned int data_size = 0;
 810         int err;
 811
 812         if (host->eject || !sd_get_cd_int(host)) {
 813                 cmd->error = -ENOMEDIUM;
 814                 goto finish;
 815         }
 816
 817         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
 818         if (err) {
 819                 cmd->error = err;
 820                 goto finish;
 821         }
 822
 823         mutex_lock(&pcr->pcr_mutex);
 824
 825         rtsx_pci_start_run(pcr);
 826
 827         rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
 828                         host->initial_mode, host->double_clk, host->vpclk);
 829         rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
 830         rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
 831                         CARD_SHARE_MASK, CARD_SHARE_48_SD);
 832
 833         mutex_lock(&host->host_mutex);
 834         host->mrq = mrq;
 835         mutex_unlock(&host->host_mutex);
 836
 837         if (mrq->data)
 838                 data_size = data->blocks * data->blksz;
 839
 840         if (!data_size) {
 841                 sd_send_cmd_get_rsp(host, cmd);
 842         } else if (sd_rw_cmd(cmd) || sdio_extblock_cmd(cmd, data)) {
 843                 cmd->error = sd_rw_multi(host, mrq);
 844                 if (!host->using_cookie)
 845                         sdmmc_post_req(host->mmc, host->mrq, 0);
 846
 847                 if (mmc_op_multi(cmd->opcode) && mrq->stop)
 848                         sd_send_cmd_get_rsp(host, mrq->stop);
 849         } else {
 850                 sd_normal_rw(host, mrq);
 851         }
 852
 853         if (mrq->data) {
 854                 if (cmd->error || data->error)
 855                         data->bytes_xfered = 0;
 856                 else
 857                         data->bytes_xfered = data->blocks * data->blksz;
 858         }
 859
 860         mutex_unlock(&pcr->pcr_mutex);
 861
 862 finish:
 863         if (cmd->error) {
 864                 dev_dbg(sdmmc_dev(host), "CMD %d 0x%08x error(%d)\n",
 865                         cmd->opcode, cmd->arg, cmd->error);
 866         }
 867
 868         mutex_lock(&host->host_mutex);
 869         host->mrq = NULL;
 870         mutex_unlock(&host->host_mutex);
 871
 872         mmc_request_done(mmc, mrq);
 873 }
 874
 875 static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
 876 {
 877         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
 878         struct mmc_data *data = mrq->data;
 879
 880         mutex_lock(&host->host_mutex);
 881         host->mrq = mrq;
 882         mutex_unlock(&host->host_mutex);
 883
 884         if (sd_rw_cmd(mrq->cmd) || sdio_extblock_cmd(mrq->cmd, data))
 885                 host->using_cookie = sd_pre_dma_transfer(host, data, false);
 886
 887         schedule_work(&host->work);
 888 }
 889
 890 static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
 891                 unsigned char bus_width)
 892 {
 893         int err = 0;
 894         u8 width[] = {
 895                 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
 896                 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
 897                 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
 898         };
 899
 900         if (bus_width <= MMC_BUS_WIDTH_8)
 901                 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
 902                                 0x03, width[bus_width]);
 903
 904         return err;
 905 }
 906
 907 static int sd_power_on(struct realtek_pci_sdmmc *host)
 908 {
 909         struct rtsx_pcr *pcr = host->pcr;
 910         int err;
 911
 912         if (host->power_state == SDMMC_POWER_ON)
 913                 return 0;
 914
 915         rtsx_pci_init_cmd(pcr);
 916         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
 917         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
 918                         CARD_SHARE_MASK, CARD_SHARE_48_SD);
 919         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
 920                         SD_CLK_EN, SD_CLK_EN);
 921         err = rtsx_pci_send_cmd(pcr, 100);
 922         if (err < 0)
 923                 return err;
 924
 925         err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
 926         if (err < 0)
 927                 return err;
 928
 929         err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
 930         if (err < 0)
 931                 return err;
 932
 933         err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
 934         if (err < 0)
 935                 return err;
 936
 937         host->power_state = SDMMC_POWER_ON;
 938         return 0;
 939 }
 940
 941 static int sd_power_off(struct realtek_pci_sdmmc *host)
 942 {
 943         struct rtsx_pcr *pcr = host->pcr;
 944         int err;
 945
 946         host->power_state = SDMMC_POWER_OFF;
 947
 948         rtsx_pci_init_cmd(pcr);
 949
 950         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
 951         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
 952
 953         err = rtsx_pci_send_cmd(pcr, 100);
 954         if (err < 0)
 955                 return err;
 956
 957         err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
 958         if (err < 0)
 959                 return err;
 960
 961         return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
 962 }
 963
 964 static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
 965                 unsigned char power_mode)
 966 {
 967         int err;
 968
 969         if (power_mode == MMC_POWER_OFF)
 970                 err = sd_power_off(host);
 971         else
 972                 err = sd_power_on(host);
 973
 974         return err;
 975 }
 976
 977 static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing)
 978 {
 979         struct rtsx_pcr *pcr = host->pcr;
 980         int err = 0;
 981
 982         rtsx_pci_init_cmd(pcr);
 983
 984         switch (timing) {
 985         case MMC_TIMING_UHS_SDR104:
 986         case MMC_TIMING_UHS_SDR50:
 987                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
 988                                 0x0C | SD_ASYNC_FIFO_NOT_RST,
 989                                 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
 990                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
 991                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
 992                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
 993                                 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
 994                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
 995                 break;
 996
 997         case MMC_TIMING_MMC_DDR52:
 998         case MMC_TIMING_UHS_DDR50:
 999                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1000                                 0x0C | SD_ASYNC_FIFO_NOT_RST,
1001                                 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
1002                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1003                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1004                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1005                                 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1006                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1007                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1008                                 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
1009                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1010                                 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
1011                                 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
1012                 break;
1013
1014         case MMC_TIMING_MMC_HS:
1015         case MMC_TIMING_SD_HS:
1016                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1017                                 0x0C, SD_20_MODE);
1018                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1019                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1020                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1021                                 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1022                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1023                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1024                                 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
1025                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1026                                 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
1027                 break;
1028
1029         default:
1030                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1031                                 SD_CFG1, 0x0C, SD_20_MODE);
1032                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1033                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1034                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1035                                 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1036                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1037                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1038                                 SD_PUSH_POINT_CTL, 0xFF, 0);
1039                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1040                                 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
1041                 break;
1042         }
1043
1044         err = rtsx_pci_send_cmd(pcr, 100);
1045
1046         return err;
1047 }
1048
1049 static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1050 {
1051         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1052         struct rtsx_pcr *pcr = host->pcr;
1053
1054         if (host->eject)
1055                 return;
1056
1057         if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
1058                 return;
1059
1060         mutex_lock(&pcr->pcr_mutex);
1061
1062         rtsx_pci_start_run(pcr);
1063
1064         sd_set_bus_width(host, ios->bus_width);
1065         sd_set_power_mode(host, ios->power_mode);
1066         sd_set_timing(host, ios->timing);
1067
1068         host->vpclk = false;
1069         host->double_clk = true;
1070
1071         switch (ios->timing) {
1072         case MMC_TIMING_UHS_SDR104:
1073         case MMC_TIMING_UHS_SDR50:
1074                 host->ssc_depth = RTSX_SSC_DEPTH_2M;
1075                 host->vpclk = true;
1076                 host->double_clk = false;
1077                 break;
1078         case MMC_TIMING_MMC_DDR52:
1079         case MMC_TIMING_UHS_DDR50:
1080         case MMC_TIMING_UHS_SDR25:
1081                 host->ssc_depth = RTSX_SSC_DEPTH_1M;
1082                 break;
1083         default:
1084                 host->ssc_depth = RTSX_SSC_DEPTH_500K;
1085                 break;
1086         }
1087
1088         host->initial_mode = (ios->clock <= 1000000) ? true : false;
1089
1090         host->clock = ios->clock;
1091         rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
1092                         host->initial_mode, host->double_clk, host->vpclk);
1093
1094         mutex_unlock(&pcr->pcr_mutex);
1095 }
1096
1097 static int sdmmc_get_ro(struct mmc_host *mmc)
1098 {
1099         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1100         struct rtsx_pcr *pcr = host->pcr;
1101         int ro = 0;
1102         u32 val;
1103
1104         if (host->eject)
1105                 return -ENOMEDIUM;
1106
1107         mutex_lock(&pcr->pcr_mutex);
1108
1109         rtsx_pci_start_run(pcr);
1110
1111         /* Check SD mechanical write-protect switch */
1112         val = rtsx_pci_readl(pcr, RTSX_BIPR);
1113         dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1114         if (val & SD_WRITE_PROTECT)
1115                 ro = 1;
1116
1117         mutex_unlock(&pcr->pcr_mutex);
1118
1119         return ro;
1120 }
1121
1122 static int sdmmc_get_cd(struct mmc_host *mmc)
1123 {
1124         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1125         struct rtsx_pcr *pcr = host->pcr;
1126         int cd = 0;
1127         u32 val;
1128
1129         if (host->eject)
1130                 return cd;
1131
1132         mutex_lock(&pcr->pcr_mutex);
1133
1134         rtsx_pci_start_run(pcr);
1135
1136         /* Check SD card detect */
1137         val = rtsx_pci_card_exist(pcr);
1138         dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1139         if (val & SD_EXIST)
1140                 cd = 1;
1141
1142         mutex_unlock(&pcr->pcr_mutex);
1143
1144         return cd;
1145 }
1146
1147 static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
1148 {
1149         struct rtsx_pcr *pcr = host->pcr;
1150         int err;
1151         u8 stat;
1152
1153         /* Reference to Signal Voltage Switch Sequence in SD spec.
1154          * Wait for a period of time so that the card can drive SD_CMD and
1155          * SD_DAT[3:0] to low after sending back CMD11 response.
1156          */
1157         mdelay(1);
1158
1159         /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
1160          * If either one of SD_CMD,SD_DAT[3:0] is not low,
1161          * abort the voltage switch sequence;
1162          */
1163         err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1164         if (err < 0)
1165                 return err;
1166
1167         if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1168                                 SD_DAT1_STATUS | SD_DAT0_STATUS))
1169                 return -EINVAL;
1170
1171         /* Stop toggle SD clock */
1172         err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1173                         0xFF, SD_CLK_FORCE_STOP);
1174         if (err < 0)
1175                 return err;
1176
1177         return 0;
1178 }
1179
1180 static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1181 {
1182         struct rtsx_pcr *pcr = host->pcr;
1183         int err;
1184         u8 stat, mask, val;
1185
1186         /* Wait 1.8V output of voltage regulator in card stable */
1187         msleep(50);
1188
1189         /* Toggle SD clock again */
1190         err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1191         if (err < 0)
1192                 return err;
1193
1194         /* Wait for a period of time so that the card can drive
1195          * SD_DAT[3:0] to high at 1.8V
1196          */
1197         msleep(20);
1198
1199         /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1200         err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1201         if (err < 0)
1202                 return err;
1203
1204         mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1205                 SD_DAT1_STATUS | SD_DAT0_STATUS;
1206         val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1207                 SD_DAT1_STATUS | SD_DAT0_STATUS;
1208         if ((stat & mask) != val) {
1209                 dev_dbg(sdmmc_dev(host),
1210                         "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1211                 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1212                                 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1213                 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1214                 return -EINVAL;
1215         }
1216
1217         return 0;
1218 }
1219
1220 static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1221 {
1222         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1223         struct rtsx_pcr *pcr = host->pcr;
1224         int err = 0;
1225         u8 voltage;
1226
1227         dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1228                         __func__, ios->signal_voltage);
1229
1230         if (host->eject)
1231                 return -ENOMEDIUM;
1232
1233         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1234         if (err)
1235                 return err;
1236
1237         mutex_lock(&pcr->pcr_mutex);
1238
1239         rtsx_pci_start_run(pcr);
1240
1241         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1242                 voltage = OUTPUT_3V3;
1243         else
1244                 voltage = OUTPUT_1V8;
1245
1246         if (voltage == OUTPUT_1V8) {
1247                 err = sd_wait_voltage_stable_1(host);
1248                 if (err < 0)
1249                         goto out;
1250         }
1251
1252         err = rtsx_pci_switch_output_voltage(pcr, voltage);
1253         if (err < 0)
1254                 goto out;
1255
1256         if (voltage == OUTPUT_1V8) {
1257                 err = sd_wait_voltage_stable_2(host);
1258                 if (err < 0)
1259                         goto out;
1260         }
1261
1262 out:
1263         /* Stop toggle SD clock in idle */
1264         err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1265                         SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1266
1267         mutex_unlock(&pcr->pcr_mutex);
1268
1269         return err;
1270 }
1271
1272 static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1273 {
1274         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1275         struct rtsx_pcr *pcr = host->pcr;
1276         int err = 0;
1277
1278         if (host->eject)
1279                 return -ENOMEDIUM;
1280
1281         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1282         if (err)
1283                 return err;
1284
1285         mutex_lock(&pcr->pcr_mutex);
1286
1287         rtsx_pci_start_run(pcr);
1288
1289         /* Set initial TX phase */
1290         switch (mmc->ios.timing) {
1291         case MMC_TIMING_UHS_SDR104:
1292                 err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false);
1293                 break;
1294
1295         case MMC_TIMING_UHS_SDR50:
1296                 err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false);
1297                 break;
1298
1299         case MMC_TIMING_UHS_DDR50:
1300                 err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false);
1301                 break;
1302
1303         default:
1304                 err = 0;
1305         }
1306
1307         if (err)
1308                 goto out;
1309
1310         /* Tuning RX phase */
1311         if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
1312                         (mmc->ios.timing == MMC_TIMING_UHS_SDR50))
1313                 err = sd_tuning_rx(host, opcode);
1314         else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
1315                 err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true);
1316
1317 out:
1318         mutex_unlock(&pcr->pcr_mutex);
1319
1320         return err;
1321 }
1322
1323 static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
1324         .pre_req = sdmmc_pre_req,
1325         .post_req = sdmmc_post_req,
1326         .request = sdmmc_request,
1327         .set_ios = sdmmc_set_ios,
1328         .get_ro = sdmmc_get_ro,
1329         .get_cd = sdmmc_get_cd,
1330         .start_signal_voltage_switch = sdmmc_switch_voltage,
1331         .execute_tuning = sdmmc_execute_tuning,
1332 };
1333
1334 static void init_extra_caps(struct realtek_pci_sdmmc *host)
1335 {
1336         struct mmc_host *mmc = host->mmc;
1337         struct rtsx_pcr *pcr = host->pcr;
1338
1339         dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1340
1341         if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1342                 mmc->caps |= MMC_CAP_UHS_SDR50;
1343         if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1344                 mmc->caps |= MMC_CAP_UHS_SDR104;
1345         if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1346                 mmc->caps |= MMC_CAP_UHS_DDR50;
1347         if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1348                 mmc->caps |= MMC_CAP_1_8V_DDR;
1349         if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1350                 mmc->caps |= MMC_CAP_8_BIT_DATA;
1351 }
1352
1353 static void realtek_init_host(struct realtek_pci_sdmmc *host)
1354 {
1355         struct mmc_host *mmc = host->mmc;
1356
1357         mmc->f_min = 250000;
1358         mmc->f_max = 208000000;
1359         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1360         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1361                 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1362                 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_ERASE;
1363         mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE;
1364         mmc->max_current_330 = 400;
1365         mmc->max_current_180 = 800;
1366         mmc->ops = &realtek_pci_sdmmc_ops;
1367
1368         init_extra_caps(host);
1369
1370         mmc->max_segs = 256;
1371         mmc->max_seg_size = 65536;
1372         mmc->max_blk_size = 512;
1373         mmc->max_blk_count = 65535;
1374         mmc->max_req_size = 524288;
1375 }
1376
1377 static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1378 {
1379         struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1380
1381         host->cookie = -1;
1382         mmc_detect_change(host->mmc, 0);
1383 }
1384
1385 static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1386 {
1387         struct mmc_host *mmc;
1388         struct realtek_pci_sdmmc *host;
1389         struct rtsx_pcr *pcr;
1390         struct pcr_handle *handle = pdev->dev.platform_data;
1391
1392         if (!handle)
1393                 return -ENXIO;
1394
1395         pcr = handle->pcr;
1396         if (!pcr)
1397                 return -ENXIO;
1398
1399         dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1400
1401         mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1402         if (!mmc)
1403                 return -ENOMEM;
1404
1405         host = mmc_priv(mmc);
1406         host->pcr = pcr;
1407         host->mmc = mmc;
1408         host->pdev = pdev;
1409         host->cookie = -1;
1410         host->power_state = SDMMC_POWER_OFF;
1411         INIT_WORK(&host->work, sd_request);
1412         platform_set_drvdata(pdev, host);
1413         pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1414         pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1415
1416         mutex_init(&host->host_mutex);
1417
1418         realtek_init_host(host);
1419
1420         mmc_add_host(mmc);
1421
1422         return 0;
1423 }
1424
1425 static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1426 {
1427         struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1428         struct rtsx_pcr *pcr;
1429         struct mmc_host *mmc;
1430
1431         if (!host)
1432                 return 0;
1433
1434         pcr = host->pcr;
1435         pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1436         pcr->slots[RTSX_SD_CARD].card_event = NULL;
1437         mmc = host->mmc;
1438
1439         cancel_work_sync(&host->work);
1440
1441         mutex_lock(&host->host_mutex);
1442         if (host->mrq) {
1443                 dev_dbg(&(pdev->dev),
1444                         "%s: Controller removed during transfer\n",
1445                         mmc_hostname(mmc));
1446
1447                 rtsx_pci_complete_unfinished_transfer(pcr);
1448
1449                 host->mrq->cmd->error = -ENOMEDIUM;
1450                 if (host->mrq->stop)
1451                         host->mrq->stop->error = -ENOMEDIUM;
1452                 mmc_request_done(mmc, host->mrq);
1453         }
1454         mutex_unlock(&host->host_mutex);
1455
1456         mmc_remove_host(mmc);
1457         host->eject = true;
1458
1459         flush_work(&host->work);
1460
1461         mmc_free_host(mmc);
1462
1463         dev_dbg(&(pdev->dev),
1464                 ": Realtek PCI-E SDMMC controller has been removed\n");
1465
1466         return 0;
1467 }
1468
1469 static const struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1470         {
1471                 .name = DRV_NAME_RTSX_PCI_SDMMC,
1472         }, {
1473                 /* sentinel */
1474         }
1475 };
1476 MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1477
1478 static struct platform_driver rtsx_pci_sdmmc_driver = {
1479         .probe          = rtsx_pci_sdmmc_drv_probe,
1480         .remove         = rtsx_pci_sdmmc_drv_remove,
1481         .id_table       = rtsx_pci_sdmmc_ids,
1482         .driver         = {
1483                 .name   = DRV_NAME_RTSX_PCI_SDMMC,
1484         },
1485 };
1486 module_platform_driver(rtsx_pci_sdmmc_driver);
1487
1488 MODULE_LICENSE("GPL");
1489 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1490 MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");