drivers/mtd/nand/brcmnand/brcmnand.c

   1 /*
   2  * Copyright © 2010-2015 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/version.h>
  16 #include <linux/module.h>
  17 #include <linux/init.h>
  18 #include <linux/delay.h>
  19 #include <linux/device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/err.h>
  22 #include <linux/completion.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/ioport.h>
  27 #include <linux/bug.h>
  28 #include <linux/kernel.h>
  29 #include <linux/bitops.h>
  30 #include <linux/mm.h>
  31 #include <linux/mtd/mtd.h>
  32 #include <linux/mtd/nand.h>
  33 #include <linux/mtd/partitions.h>
  34 #include <linux/of.h>
  35 #include <linux/of_platform.h>
  36 #include <linux/slab.h>
  37 #include <linux/list.h>
  38 #include <linux/log2.h>
  39
  40 #include "brcmnand.h"
  41
  42 /*
  43  * This flag controls if WP stays on between erase/write commands to mitigate
  44  * flash corruption due to power glitches. Values:
  45  * 0: NAND_WP is not used or not available
  46  * 1: NAND_WP is set by default, cleared for erase/write operations
  47  * 2: NAND_WP is always cleared
  48  */
  49 static int wp_on = 1;
  50 module_param(wp_on, int, 0444);
  51
  52 /***********************************************************************
  53  * Definitions
  54  ***********************************************************************/
  55
  56 #define DRV_NAME                        "brcmnand"
  57
  58 #define CMD_NULL                        0x00
  59 #define CMD_PAGE_READ                   0x01
  60 #define CMD_SPARE_AREA_READ             0x02
  61 #define CMD_STATUS_READ                 0x03
  62 #define CMD_PROGRAM_PAGE                0x04
  63 #define CMD_PROGRAM_SPARE_AREA          0x05
  64 #define CMD_COPY_BACK                   0x06
  65 #define CMD_DEVICE_ID_READ              0x07
  66 #define CMD_BLOCK_ERASE                 0x08
  67 #define CMD_FLASH_RESET                 0x09
  68 #define CMD_BLOCKS_LOCK                 0x0a
  69 #define CMD_BLOCKS_LOCK_DOWN            0x0b
  70 #define CMD_BLOCKS_UNLOCK               0x0c
  71 #define CMD_READ_BLOCKS_LOCK_STATUS     0x0d
  72 #define CMD_PARAMETER_READ              0x0e
  73 #define CMD_PARAMETER_CHANGE_COL        0x0f
  74 #define CMD_LOW_LEVEL_OP                0x10
  75
  76 struct brcm_nand_dma_desc {
  77         u32 next_desc;
  78         u32 next_desc_ext;
  79         u32 cmd_irq;
  80         u32 dram_addr;
  81         u32 dram_addr_ext;
  82         u32 tfr_len;
  83         u32 total_len;
  84         u32 flash_addr;
  85         u32 flash_addr_ext;
  86         u32 cs;
  87         u32 pad2[5];
  88         u32 status_valid;
  89 } __packed;
  90
  91 /* Bitfields for brcm_nand_dma_desc::status_valid */
  92 #define FLASH_DMA_ECC_ERROR     (1 << 8)
  93 #define FLASH_DMA_CORR_ERROR    (1 << 9)
  94
  95 /* 512B flash cache in the NAND controller HW */
  96 #define FC_SHIFT                9U
  97 #define FC_BYTES                512U
  98 #define FC_WORDS                (FC_BYTES >> 2)
  99
 100 #define BRCMNAND_MIN_PAGESIZE   512
 101 #define BRCMNAND_MIN_BLOCKSIZE  (8 * 1024)
 102 #define BRCMNAND_MIN_DEVSIZE    (4ULL * 1024 * 1024)
 103
 104 /* Controller feature flags */
 105 enum {
 106         BRCMNAND_HAS_1K_SECTORS                 = BIT(0),
 107         BRCMNAND_HAS_PREFETCH                   = BIT(1),
 108         BRCMNAND_HAS_CACHE_MODE                 = BIT(2),
 109         BRCMNAND_HAS_WP                         = BIT(3),
 110 };
 111
 112 struct brcmnand_controller {
 113         struct device           *dev;
 114         struct nand_hw_control  controller;
 115         void __iomem            *nand_base;
 116         void __iomem            *nand_fc; /* flash cache */
 117         void __iomem            *flash_dma_base;
 118         unsigned int            irq;
 119         unsigned int            dma_irq;
 120         int                     nand_version;
 121
 122         /* Some SoCs provide custom interrupt status register(s) */
 123         struct brcmnand_soc     *soc;
 124
 125         /* Some SoCs have a gateable clock for the controller */
 126         struct clk              *clk;
 127
 128         int                     cmd_pending;
 129         bool                    dma_pending;
 130         struct completion       done;
 131         struct completion       dma_done;
 132
 133         /* List of NAND hosts (one for each chip-select) */
 134         struct list_head host_list;
 135
 136         struct brcm_nand_dma_desc *dma_desc;
 137         dma_addr_t              dma_pa;
 138
 139         /* in-memory cache of the FLASH_CACHE, used only for some commands */
 140         u8                      flash_cache[FC_BYTES];
 141
 142         /* Controller revision details */
 143         const u16               *reg_offsets;
 144         unsigned int            reg_spacing; /* between CS1, CS2, ... regs */
 145         const u8                *cs_offsets; /* within each chip-select */
 146         const u8                *cs0_offsets; /* within CS0, if different */
 147         unsigned int            max_block_size;
 148         const unsigned int      *block_sizes;
 149         unsigned int            max_page_size;
 150         const unsigned int      *page_sizes;
 151         unsigned int            max_oob;
 152         u32                     features;
 153
 154         /* for low-power standby/resume only */
 155         u32                     nand_cs_nand_select;
 156         u32                     nand_cs_nand_xor;
 157         u32                     corr_stat_threshold;
 158         u32                     flash_dma_mode;
 159 };
 160
 161 struct brcmnand_cfg {
 162         u64                     device_size;
 163         unsigned int            block_size;
 164         unsigned int            page_size;
 165         unsigned int            spare_area_size;
 166         unsigned int            device_width;
 167         unsigned int            col_adr_bytes;
 168         unsigned int            blk_adr_bytes;
 169         unsigned int            ful_adr_bytes;
 170         unsigned int            sector_size_1k;
 171         unsigned int            ecc_level;
 172         /* use for low-power standby/resume only */
 173         u32                     acc_control;
 174         u32                     config;
 175         u32                     config_ext;
 176         u32                     timing_1;
 177         u32                     timing_2;
 178 };
 179
 180 struct brcmnand_host {
 181         struct list_head        node;
 182
 183         struct nand_chip        chip;
 184         struct platform_device  *pdev;
 185         int                     cs;
 186
 187         unsigned int            last_cmd;
 188         unsigned int            last_byte;
 189         u64                     last_addr;
 190         struct brcmnand_cfg     hwcfg;
 191         struct brcmnand_controller *ctrl;
 192 };
 193
 194 enum brcmnand_reg {
 195         BRCMNAND_CMD_START = 0,
 196         BRCMNAND_CMD_EXT_ADDRESS,
 197         BRCMNAND_CMD_ADDRESS,
 198         BRCMNAND_INTFC_STATUS,
 199         BRCMNAND_CS_SELECT,
 200         BRCMNAND_CS_XOR,
 201         BRCMNAND_LL_OP,
 202         BRCMNAND_CS0_BASE,
 203         BRCMNAND_CS1_BASE,              /* CS1 regs, if non-contiguous */
 204         BRCMNAND_CORR_THRESHOLD,
 205         BRCMNAND_CORR_THRESHOLD_EXT,
 206         BRCMNAND_UNCORR_COUNT,
 207         BRCMNAND_CORR_COUNT,
 208         BRCMNAND_CORR_EXT_ADDR,
 209         BRCMNAND_CORR_ADDR,
 210         BRCMNAND_UNCORR_EXT_ADDR,
 211         BRCMNAND_UNCORR_ADDR,
 212         BRCMNAND_SEMAPHORE,
 213         BRCMNAND_ID,
 214         BRCMNAND_ID_EXT,
 215         BRCMNAND_LL_RDATA,
 216         BRCMNAND_OOB_READ_BASE,
 217         BRCMNAND_OOB_READ_10_BASE,      /* offset 0x10, if non-contiguous */
 218         BRCMNAND_OOB_WRITE_BASE,
 219         BRCMNAND_OOB_WRITE_10_BASE,     /* offset 0x10, if non-contiguous */
 220         BRCMNAND_FC_BASE,
 221 };
 222
 223 /* BRCMNAND v4.0 */
 224 static const u16 brcmnand_regs_v40[] = {
 225         [BRCMNAND_CMD_START]            =  0x04,
 226         [BRCMNAND_CMD_EXT_ADDRESS]      =  0x08,
 227         [BRCMNAND_CMD_ADDRESS]          =  0x0c,
 228         [BRCMNAND_INTFC_STATUS]         =  0x6c,
 229         [BRCMNAND_CS_SELECT]            =  0x14,
 230         [BRCMNAND_CS_XOR]               =  0x18,
 231         [BRCMNAND_LL_OP]                = 0x178,
 232         [BRCMNAND_CS0_BASE]             =  0x40,
 233         [BRCMNAND_CS1_BASE]             =  0xd0,
 234         [BRCMNAND_CORR_THRESHOLD]       =  0x84,
 235         [BRCMNAND_CORR_THRESHOLD_EXT]   =     0,
 236         [BRCMNAND_UNCORR_COUNT]         =     0,
 237         [BRCMNAND_CORR_COUNT]           =     0,
 238         [BRCMNAND_CORR_EXT_ADDR]        =  0x70,
 239         [BRCMNAND_CORR_ADDR]            =  0x74,
 240         [BRCMNAND_UNCORR_EXT_ADDR]      =  0x78,
 241         [BRCMNAND_UNCORR_ADDR]          =  0x7c,
 242         [BRCMNAND_SEMAPHORE]            =  0x58,
 243         [BRCMNAND_ID]                   =  0x60,
 244         [BRCMNAND_ID_EXT]               =  0x64,
 245         [BRCMNAND_LL_RDATA]             = 0x17c,
 246         [BRCMNAND_OOB_READ_BASE]        =  0x20,
 247         [BRCMNAND_OOB_READ_10_BASE]     = 0x130,
 248         [BRCMNAND_OOB_WRITE_BASE]       =  0x30,
 249         [BRCMNAND_OOB_WRITE_10_BASE]    =     0,
 250         [BRCMNAND_FC_BASE]              = 0x200,
 251 };
 252
 253 /* BRCMNAND v5.0 */
 254 static const u16 brcmnand_regs_v50[] = {
 255         [BRCMNAND_CMD_START]            =  0x04,
 256         [BRCMNAND_CMD_EXT_ADDRESS]      =  0x08,
 257         [BRCMNAND_CMD_ADDRESS]          =  0x0c,
 258         [BRCMNAND_INTFC_STATUS]         =  0x6c,
 259         [BRCMNAND_CS_SELECT]            =  0x14,
 260         [BRCMNAND_CS_XOR]               =  0x18,
 261         [BRCMNAND_LL_OP]                = 0x178,
 262         [BRCMNAND_CS0_BASE]             =  0x40,
 263         [BRCMNAND_CS1_BASE]             =  0xd0,
 264         [BRCMNAND_CORR_THRESHOLD]       =  0x84,
 265         [BRCMNAND_CORR_THRESHOLD_EXT]   =     0,
 266         [BRCMNAND_UNCORR_COUNT]         =     0,
 267         [BRCMNAND_CORR_COUNT]           =     0,
 268         [BRCMNAND_CORR_EXT_ADDR]        =  0x70,
 269         [BRCMNAND_CORR_ADDR]            =  0x74,
 270         [BRCMNAND_UNCORR_EXT_ADDR]      =  0x78,
 271         [BRCMNAND_UNCORR_ADDR]          =  0x7c,
 272         [BRCMNAND_SEMAPHORE]            =  0x58,
 273         [BRCMNAND_ID]                   =  0x60,
 274         [BRCMNAND_ID_EXT]               =  0x64,
 275         [BRCMNAND_LL_RDATA]             = 0x17c,
 276         [BRCMNAND_OOB_READ_BASE]        =  0x20,
 277         [BRCMNAND_OOB_READ_10_BASE]     = 0x130,
 278         [BRCMNAND_OOB_WRITE_BASE]       =  0x30,
 279         [BRCMNAND_OOB_WRITE_10_BASE]    = 0x140,
 280         [BRCMNAND_FC_BASE]              = 0x200,
 281 };
 282
 283 /* BRCMNAND v6.0 - v7.1 */
 284 static const u16 brcmnand_regs_v60[] = {
 285         [BRCMNAND_CMD_START]            =  0x04,
 286         [BRCMNAND_CMD_EXT_ADDRESS]      =  0x08,
 287         [BRCMNAND_CMD_ADDRESS]          =  0x0c,
 288         [BRCMNAND_INTFC_STATUS]         =  0x14,
 289         [BRCMNAND_CS_SELECT]            =  0x18,
 290         [BRCMNAND_CS_XOR]               =  0x1c,
 291         [BRCMNAND_LL_OP]                =  0x20,
 292         [BRCMNAND_CS0_BASE]             =  0x50,
 293         [BRCMNAND_CS1_BASE]             =     0,
 294         [BRCMNAND_CORR_THRESHOLD]       =  0xc0,
 295         [BRCMNAND_CORR_THRESHOLD_EXT]   =  0xc4,
 296         [BRCMNAND_UNCORR_COUNT]         =  0xfc,
 297         [BRCMNAND_CORR_COUNT]           = 0x100,
 298         [BRCMNAND_CORR_EXT_ADDR]        = 0x10c,
 299         [BRCMNAND_CORR_ADDR]            = 0x110,
 300         [BRCMNAND_UNCORR_EXT_ADDR]      = 0x114,
 301         [BRCMNAND_UNCORR_ADDR]          = 0x118,
 302         [BRCMNAND_SEMAPHORE]            = 0x150,
 303         [BRCMNAND_ID]                   = 0x194,
 304         [BRCMNAND_ID_EXT]               = 0x198,
 305         [BRCMNAND_LL_RDATA]             = 0x19c,
 306         [BRCMNAND_OOB_READ_BASE]        = 0x200,
 307         [BRCMNAND_OOB_READ_10_BASE]     =     0,
 308         [BRCMNAND_OOB_WRITE_BASE]       = 0x280,
 309         [BRCMNAND_OOB_WRITE_10_BASE]    =     0,
 310         [BRCMNAND_FC_BASE]              = 0x400,
 311 };
 312
 313 /* BRCMNAND v7.1 */
 314 static const u16 brcmnand_regs_v71[] = {
 315         [BRCMNAND_CMD_START]            =  0x04,
 316         [BRCMNAND_CMD_EXT_ADDRESS]      =  0x08,
 317         [BRCMNAND_CMD_ADDRESS]          =  0x0c,
 318         [BRCMNAND_INTFC_STATUS]         =  0x14,
 319         [BRCMNAND_CS_SELECT]            =  0x18,
 320         [BRCMNAND_CS_XOR]               =  0x1c,
 321         [BRCMNAND_LL_OP]                =  0x20,
 322         [BRCMNAND_CS0_BASE]             =  0x50,
 323         [BRCMNAND_CS1_BASE]             =     0,
 324         [BRCMNAND_CORR_THRESHOLD]       =  0xdc,
 325         [BRCMNAND_CORR_THRESHOLD_EXT]   =  0xe0,
 326         [BRCMNAND_UNCORR_COUNT]         =  0xfc,
 327         [BRCMNAND_CORR_COUNT]           = 0x100,
 328         [BRCMNAND_CORR_EXT_ADDR]        = 0x10c,
 329         [BRCMNAND_CORR_ADDR]            = 0x110,
 330         [BRCMNAND_UNCORR_EXT_ADDR]      = 0x114,
 331         [BRCMNAND_UNCORR_ADDR]          = 0x118,
 332         [BRCMNAND_SEMAPHORE]            = 0x150,
 333         [BRCMNAND_ID]                   = 0x194,
 334         [BRCMNAND_ID_EXT]               = 0x198,
 335         [BRCMNAND_LL_RDATA]             = 0x19c,
 336         [BRCMNAND_OOB_READ_BASE]        = 0x200,
 337         [BRCMNAND_OOB_READ_10_BASE]     =     0,
 338         [BRCMNAND_OOB_WRITE_BASE]       = 0x280,
 339         [BRCMNAND_OOB_WRITE_10_BASE]    =     0,
 340         [BRCMNAND_FC_BASE]              = 0x400,
 341 };
 342
 343 /* BRCMNAND v7.2 */
 344 static const u16 brcmnand_regs_v72[] = {
 345         [BRCMNAND_CMD_START]            =  0x04,
 346         [BRCMNAND_CMD_EXT_ADDRESS]      =  0x08,
 347         [BRCMNAND_CMD_ADDRESS]          =  0x0c,
 348         [BRCMNAND_INTFC_STATUS]         =  0x14,
 349         [BRCMNAND_CS_SELECT]            =  0x18,
 350         [BRCMNAND_CS_XOR]               =  0x1c,
 351         [BRCMNAND_LL_OP]                =  0x20,
 352         [BRCMNAND_CS0_BASE]             =  0x50,
 353         [BRCMNAND_CS1_BASE]             =     0,
 354         [BRCMNAND_CORR_THRESHOLD]       =  0xdc,
 355         [BRCMNAND_CORR_THRESHOLD_EXT]   =  0xe0,
 356         [BRCMNAND_UNCORR_COUNT]         =  0xfc,
 357         [BRCMNAND_CORR_COUNT]           = 0x100,
 358         [BRCMNAND_CORR_EXT_ADDR]        = 0x10c,
 359         [BRCMNAND_CORR_ADDR]            = 0x110,
 360         [BRCMNAND_UNCORR_EXT_ADDR]      = 0x114,
 361         [BRCMNAND_UNCORR_ADDR]          = 0x118,
 362         [BRCMNAND_SEMAPHORE]            = 0x150,
 363         [BRCMNAND_ID]                   = 0x194,
 364         [BRCMNAND_ID_EXT]               = 0x198,
 365         [BRCMNAND_LL_RDATA]             = 0x19c,
 366         [BRCMNAND_OOB_READ_BASE]        = 0x200,
 367         [BRCMNAND_OOB_READ_10_BASE]     =     0,
 368         [BRCMNAND_OOB_WRITE_BASE]       = 0x400,
 369         [BRCMNAND_OOB_WRITE_10_BASE]    =     0,
 370         [BRCMNAND_FC_BASE]              = 0x600,
 371 };
 372
 373 enum brcmnand_cs_reg {
 374         BRCMNAND_CS_CFG_EXT = 0,
 375         BRCMNAND_CS_CFG,
 376         BRCMNAND_CS_ACC_CONTROL,
 377         BRCMNAND_CS_TIMING1,
 378         BRCMNAND_CS_TIMING2,
 379 };
 380
 381 /* Per chip-select offsets for v7.1 */
 382 static const u8 brcmnand_cs_offsets_v71[] = {
 383         [BRCMNAND_CS_ACC_CONTROL]       = 0x00,
 384         [BRCMNAND_CS_CFG_EXT]           = 0x04,
 385         [BRCMNAND_CS_CFG]               = 0x08,
 386         [BRCMNAND_CS_TIMING1]           = 0x0c,
 387         [BRCMNAND_CS_TIMING2]           = 0x10,
 388 };
 389
 390 /* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */
 391 static const u8 brcmnand_cs_offsets[] = {
 392         [BRCMNAND_CS_ACC_CONTROL]       = 0x00,
 393         [BRCMNAND_CS_CFG_EXT]           = 0x04,
 394         [BRCMNAND_CS_CFG]               = 0x04,
 395         [BRCMNAND_CS_TIMING1]           = 0x08,
 396         [BRCMNAND_CS_TIMING2]           = 0x0c,
 397 };
 398
 399 /* Per chip-select offset for <= v5.0 on CS0 only */
 400 static const u8 brcmnand_cs_offsets_cs0[] = {
 401         [BRCMNAND_CS_ACC_CONTROL]       = 0x00,
 402         [BRCMNAND_CS_CFG_EXT]           = 0x08,
 403         [BRCMNAND_CS_CFG]               = 0x08,
 404         [BRCMNAND_CS_TIMING1]           = 0x10,
 405         [BRCMNAND_CS_TIMING2]           = 0x14,
 406 };
 407
 408 /*
 409  * Bitfields for the CFG and CFG_EXT registers. Pre-v7.1 controllers only had
 410  * one config register, but once the bitfields overflowed, newer controllers
 411  * (v7.1 and newer) added a CFG_EXT register and shuffled a few fields around.
 412  */
 413 enum {
 414         CFG_BLK_ADR_BYTES_SHIFT         = 8,
 415         CFG_COL_ADR_BYTES_SHIFT         = 12,
 416         CFG_FUL_ADR_BYTES_SHIFT         = 16,
 417         CFG_BUS_WIDTH_SHIFT             = 23,
 418         CFG_BUS_WIDTH                   = BIT(CFG_BUS_WIDTH_SHIFT),
 419         CFG_DEVICE_SIZE_SHIFT           = 24,
 420
 421         /* Only for pre-v7.1 (with no CFG_EXT register) */
 422         CFG_PAGE_SIZE_SHIFT             = 20,
 423         CFG_BLK_SIZE_SHIFT              = 28,
 424
 425         /* Only for v7.1+ (with CFG_EXT register) */
 426         CFG_EXT_PAGE_SIZE_SHIFT         = 0,
 427         CFG_EXT_BLK_SIZE_SHIFT          = 4,
 428 };
 429
 430 /* BRCMNAND_INTFC_STATUS */
 431 enum {
 432         INTFC_FLASH_STATUS              = GENMASK(7, 0),
 433
 434         INTFC_ERASED                    = BIT(27),
 435         INTFC_OOB_VALID                 = BIT(28),
 436         INTFC_CACHE_VALID               = BIT(29),
 437         INTFC_FLASH_READY               = BIT(30),
 438         INTFC_CTLR_READY                = BIT(31),
 439 };
 440
 441 static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs)
 442 {
 443         return brcmnand_readl(ctrl->nand_base + offs);
 444 }
 445
 446 static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs,
 447                                  u32 val)
 448 {
 449         brcmnand_writel(val, ctrl->nand_base + offs);
 450 }
 451
 452 static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
 453 {
 454         static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
 455         static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
 456         static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192, 0 };
 457
 458         ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
 459
 460         /* Only support v4.0+? */
 461         if (ctrl->nand_version < 0x0400) {
 462                 dev_err(ctrl->dev, "version %#x not supported\n",
 463                         ctrl->nand_version);
 464                 return -ENODEV;
 465         }
 466
 467         /* Register offsets */
 468         if (ctrl->nand_version >= 0x0702)
 469                 ctrl->reg_offsets = brcmnand_regs_v72;
 470         else if (ctrl->nand_version >= 0x0701)
 471                 ctrl->reg_offsets = brcmnand_regs_v71;
 472         else if (ctrl->nand_version >= 0x0600)
 473                 ctrl->reg_offsets = brcmnand_regs_v60;
 474         else if (ctrl->nand_version >= 0x0500)
 475                 ctrl->reg_offsets = brcmnand_regs_v50;
 476         else if (ctrl->nand_version >= 0x0400)
 477                 ctrl->reg_offsets = brcmnand_regs_v40;
 478
 479         /* Chip-select stride */
 480         if (ctrl->nand_version >= 0x0701)
 481                 ctrl->reg_spacing = 0x14;
 482         else
 483                 ctrl->reg_spacing = 0x10;
 484
 485         /* Per chip-select registers */
 486         if (ctrl->nand_version >= 0x0701) {
 487                 ctrl->cs_offsets = brcmnand_cs_offsets_v71;
 488         } else {
 489                 ctrl->cs_offsets = brcmnand_cs_offsets;
 490
 491                 /* v5.0 and earlier has a different CS0 offset layout */
 492                 if (ctrl->nand_version <= 0x0500)
 493                         ctrl->cs0_offsets = brcmnand_cs_offsets_cs0;
 494         }
 495
 496         /* Page / block sizes */
 497         if (ctrl->nand_version >= 0x0701) {
 498                 /* >= v7.1 use nice power-of-2 values! */
 499                 ctrl->max_page_size = 16 * 1024;
 500                 ctrl->max_block_size = 2 * 1024 * 1024;
 501         } else {
 502                 ctrl->page_sizes = page_sizes;
 503                 if (ctrl->nand_version >= 0x0600)
 504                         ctrl->block_sizes = block_sizes_v6;
 505                 else
 506                         ctrl->block_sizes = block_sizes_v4;
 507
 508                 if (ctrl->nand_version < 0x0400) {
 509                         ctrl->max_page_size = 4096;
 510                         ctrl->max_block_size = 512 * 1024;
 511                 }
 512         }
 513
 514         /* Maximum spare area sector size (per 512B) */
 515         if (ctrl->nand_version >= 0x0702)
 516                 ctrl->max_oob = 128;
 517         else if (ctrl->nand_version >= 0x0600)
 518                 ctrl->max_oob = 64;
 519         else if (ctrl->nand_version >= 0x0500)
 520                 ctrl->max_oob = 32;
 521         else
 522                 ctrl->max_oob = 16;
 523
 524         /* v6.0 and newer (except v6.1) have prefetch support */
 525         if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601)
 526                 ctrl->features |= BRCMNAND_HAS_PREFETCH;
 527
 528         /*
 529          * v6.x has cache mode, but it's implemented differently. Ignore it for
 530          * now.
 531          */
 532         if (ctrl->nand_version >= 0x0700)
 533                 ctrl->features |= BRCMNAND_HAS_CACHE_MODE;
 534
 535         if (ctrl->nand_version >= 0x0500)
 536                 ctrl->features |= BRCMNAND_HAS_1K_SECTORS;
 537
 538         if (ctrl->nand_version >= 0x0700)
 539                 ctrl->features |= BRCMNAND_HAS_WP;
 540         else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp"))
 541                 ctrl->features |= BRCMNAND_HAS_WP;
 542
 543         return 0;
 544 }
 545
 546 static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl,
 547                 enum brcmnand_reg reg)
 548 {
 549         u16 offs = ctrl->reg_offsets[reg];
 550
 551         if (offs)
 552                 return nand_readreg(ctrl, offs);
 553         else
 554                 return 0;
 555 }
 556
 557 static inline void brcmnand_write_reg(struct brcmnand_controller *ctrl,
 558                                       enum brcmnand_reg reg, u32 val)
 559 {
 560         u16 offs = ctrl->reg_offsets[reg];
 561
 562         if (offs)
 563                 nand_writereg(ctrl, offs, val);
 564 }
 565
 566 static inline void brcmnand_rmw_reg(struct brcmnand_controller *ctrl,
 567                                     enum brcmnand_reg reg, u32 mask, unsigned
 568                                     int shift, u32 val)
 569 {
 570         u32 tmp = brcmnand_read_reg(ctrl, reg);
 571
 572         tmp &= ~mask;
 573         tmp |= val << shift;
 574         brcmnand_write_reg(ctrl, reg, tmp);
 575 }
 576
 577 static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word)
 578 {
 579         return __raw_readl(ctrl->nand_fc + word * 4);
 580 }
 581
 582 static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl,
 583                                      int word, u32 val)
 584 {
 585         __raw_writel(val, ctrl->nand_fc + word * 4);
 586 }
 587
 588 static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs,
 589                                      enum brcmnand_cs_reg reg)
 590 {
 591         u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE];
 592         u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE];
 593         u8 cs_offs;
 594
 595         if (cs == 0 && ctrl->cs0_offsets)
 596                 cs_offs = ctrl->cs0_offsets[reg];
 597         else
 598                 cs_offs = ctrl->cs_offsets[reg];
 599
 600         if (cs && offs_cs1)
 601                 return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs;
 602
 603         return offs_cs0 + cs * ctrl->reg_spacing + cs_offs;
 604 }
 605
 606 static inline u32 brcmnand_count_corrected(struct brcmnand_controller *ctrl)
 607 {
 608         if (ctrl->nand_version < 0x0600)
 609                 return 1;
 610         return brcmnand_read_reg(ctrl, BRCMNAND_CORR_COUNT);
 611 }
 612
 613 static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val)
 614 {
 615         struct brcmnand_controller *ctrl = host->ctrl;
 616         unsigned int shift = 0, bits;
 617         enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
 618         int cs = host->cs;
 619
 620         if (ctrl->nand_version >= 0x0702)
 621                 bits = 7;
 622         else if (ctrl->nand_version >= 0x0600)
 623                 bits = 6;
 624         else if (ctrl->nand_version >= 0x0500)
 625                 bits = 5;
 626         else
 627                 bits = 4;
 628
 629         if (ctrl->nand_version >= 0x0702) {
 630                 if (cs >= 4)
 631                         reg = BRCMNAND_CORR_THRESHOLD_EXT;
 632                 shift = (cs % 4) * bits;
 633         } else if (ctrl->nand_version >= 0x0600) {
 634                 if (cs >= 5)
 635                         reg = BRCMNAND_CORR_THRESHOLD_EXT;
 636                 shift = (cs % 5) * bits;
 637         }
 638         brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val);
 639 }
 640
 641 static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl)
 642 {
 643         if (ctrl->nand_version < 0x0602)
 644                 return 24;
 645         return 0;
 646 }
 647
 648 /***********************************************************************
 649  * NAND ACC CONTROL bitfield
 650  *
 651  * Some bits have remained constant throughout hardware revision, while
 652  * others have shifted around.
 653  ***********************************************************************/
 654
 655 /* Constant for all versions (where supported) */
 656 enum {
 657         /* See BRCMNAND_HAS_CACHE_MODE */
 658         ACC_CONTROL_CACHE_MODE                          = BIT(22),
 659
 660         /* See BRCMNAND_HAS_PREFETCH */
 661         ACC_CONTROL_PREFETCH                            = BIT(23),
 662
 663         ACC_CONTROL_PAGE_HIT                            = BIT(24),
 664         ACC_CONTROL_WR_PREEMPT                          = BIT(25),
 665         ACC_CONTROL_PARTIAL_PAGE                        = BIT(26),
 666         ACC_CONTROL_RD_ERASED                           = BIT(27),
 667         ACC_CONTROL_FAST_PGM_RDIN                       = BIT(28),
 668         ACC_CONTROL_WR_ECC                              = BIT(30),
 669         ACC_CONTROL_RD_ECC                              = BIT(31),
 670 };
 671
 672 static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl)
 673 {
 674         if (ctrl->nand_version >= 0x0702)
 675                 return GENMASK(7, 0);
 676         else if (ctrl->nand_version >= 0x0600)
 677                 return GENMASK(6, 0);
 678         else
 679                 return GENMASK(5, 0);
 680 }
 681
 682 #define NAND_ACC_CONTROL_ECC_SHIFT      16
 683 #define NAND_ACC_CONTROL_ECC_EXT_SHIFT  13
 684
 685 static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl)
 686 {
 687         u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f;
 688
 689         mask <<= NAND_ACC_CONTROL_ECC_SHIFT;
 690
 691         /* v7.2 includes additional ECC levels */
 692         if (ctrl->nand_version >= 0x0702)
 693                 mask |= 0x7 << NAND_ACC_CONTROL_ECC_EXT_SHIFT;
 694
 695         return mask;
 696 }
 697
 698 static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en)
 699 {
 700         struct brcmnand_controller *ctrl = host->ctrl;
 701         u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
 702         u32 acc_control = nand_readreg(ctrl, offs);
 703         u32 ecc_flags = ACC_CONTROL_WR_ECC | ACC_CONTROL_RD_ECC;
 704
 705         if (en) {
 706                 acc_control |= ecc_flags; /* enable RD/WR ECC */
 707                 acc_control |= host->hwcfg.ecc_level
 708                                << NAND_ACC_CONTROL_ECC_SHIFT;
 709         } else {
 710                 acc_control &= ~ecc_flags; /* disable RD/WR ECC */
 711                 acc_control &= ~brcmnand_ecc_level_mask(ctrl);
 712         }
 713
 714         nand_writereg(ctrl, offs, acc_control);
 715 }
 716
 717 static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl)
 718 {
 719         if (ctrl->nand_version >= 0x0702)
 720                 return 9;
 721         else if (ctrl->nand_version >= 0x0600)
 722                 return 7;
 723         else if (ctrl->nand_version >= 0x0500)
 724                 return 6;
 725         else
 726                 return -1;
 727 }
 728
 729 static int brcmnand_get_sector_size_1k(struct brcmnand_host *host)
 730 {
 731         struct brcmnand_controller *ctrl = host->ctrl;
 732         int shift = brcmnand_sector_1k_shift(ctrl);
 733         u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
 734                                                   BRCMNAND_CS_ACC_CONTROL);
 735
 736         if (shift < 0)
 737                 return 0;
 738
 739         return (nand_readreg(ctrl, acc_control_offs) >> shift) & 0x1;
 740 }
 741
 742 static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val)
 743 {
 744         struct brcmnand_controller *ctrl = host->ctrl;
 745         int shift = brcmnand_sector_1k_shift(ctrl);
 746         u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
 747                                                   BRCMNAND_CS_ACC_CONTROL);
 748         u32 tmp;
 749
 750         if (shift < 0)
 751                 return;
 752
 753         tmp = nand_readreg(ctrl, acc_control_offs);
 754         tmp &= ~(1 << shift);
 755         tmp |= (!!val) << shift;
 756         nand_writereg(ctrl, acc_control_offs, tmp);
 757 }
 758
 759 /***********************************************************************
 760  * CS_NAND_SELECT
 761  ***********************************************************************/
 762
 763 enum {
 764         CS_SELECT_NAND_WP                       = BIT(29),
 765         CS_SELECT_AUTO_DEVICE_ID_CFG            = BIT(30),
 766 };
 767
 768 static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en)
 769 {
 770         u32 val = en ? CS_SELECT_NAND_WP : 0;
 771
 772         brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val);
 773 }
 774
 775 /***********************************************************************
 776  * Flash DMA
 777  ***********************************************************************/
 778
 779 enum flash_dma_reg {
 780         FLASH_DMA_REVISION              = 0x00,
 781         FLASH_DMA_FIRST_DESC            = 0x04,
 782         FLASH_DMA_FIRST_DESC_EXT        = 0x08,
 783         FLASH_DMA_CTRL                  = 0x0c,
 784         FLASH_DMA_MODE                  = 0x10,
 785         FLASH_DMA_STATUS                = 0x14,
 786         FLASH_DMA_INTERRUPT_DESC        = 0x18,
 787         FLASH_DMA_INTERRUPT_DESC_EXT    = 0x1c,
 788         FLASH_DMA_ERROR_STATUS          = 0x20,
 789         FLASH_DMA_CURRENT_DESC          = 0x24,
 790         FLASH_DMA_CURRENT_DESC_EXT      = 0x28,
 791 };
 792
 793 static inline bool has_flash_dma(struct brcmnand_controller *ctrl)
 794 {
 795         return ctrl->flash_dma_base;
 796 }
 797
 798 static inline bool flash_dma_buf_ok(const void *buf)
 799 {
 800         return buf && !is_vmalloc_addr(buf) &&
 801                 likely(IS_ALIGNED((uintptr_t)buf, 4));
 802 }
 803
 804 static inline void flash_dma_writel(struct brcmnand_controller *ctrl, u8 offs,
 805                                     u32 val)
 806 {
 807         brcmnand_writel(val, ctrl->flash_dma_base + offs);
 808 }
 809
 810 static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, u8 offs)
 811 {
 812         return brcmnand_readl(ctrl->flash_dma_base + offs);
 813 }
 814
 815 /* Low-level operation types: command, address, write, or read */
 816 enum brcmnand_llop_type {
 817         LL_OP_CMD,
 818         LL_OP_ADDR,
 819         LL_OP_WR,
 820         LL_OP_RD,
 821 };
 822
 823 /***********************************************************************
 824  * Internal support functions
 825  ***********************************************************************/
 826
 827 static inline bool is_hamming_ecc(struct brcmnand_controller *ctrl,
 828                                   struct brcmnand_cfg *cfg)
 829 {
 830         if (ctrl->nand_version <= 0x0701)
 831                 return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 &&
 832                         cfg->ecc_level == 15;
 833         else
 834                 return cfg->sector_size_1k == 0 && ((cfg->spare_area_size == 16 &&
 835                         cfg->ecc_level == 15) ||
 836                         (cfg->spare_area_size == 28 && cfg->ecc_level == 16));
 837 }
 838
 839 /*
 840  * Set mtd->ooblayout to the appropriate mtd_ooblayout_ops given
 841  * the layout/configuration.
 842  * Returns -ERRCODE on failure.
 843  */
 844 static int brcmnand_hamming_ooblayout_ecc(struct mtd_info *mtd, int section,
 845                                           struct mtd_oob_region *oobregion)
 846 {
 847         struct nand_chip *chip = mtd_to_nand(mtd);
 848         struct brcmnand_host *host = nand_get_controller_data(chip);
 849         struct brcmnand_cfg *cfg = &host->hwcfg;
 850         int sas = cfg->spare_area_size << cfg->sector_size_1k;
 851         int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
 852
 853         if (section >= sectors)
 854                 return -ERANGE;
 855
 856         oobregion->offset = (section * sas) + 6;
 857         oobregion->length = 3;
 858
 859         return 0;
 860 }
 861
 862 static int brcmnand_hamming_ooblayout_free(struct mtd_info *mtd, int section,
 863                                            struct mtd_oob_region *oobregion)
 864 {
 865         struct nand_chip *chip = mtd_to_nand(mtd);
 866         struct brcmnand_host *host = nand_get_controller_data(chip);
 867         struct brcmnand_cfg *cfg = &host->hwcfg;
 868         int sas = cfg->spare_area_size << cfg->sector_size_1k;
 869         int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
 870
 871         if (section >= sectors * 2)
 872                 return -ERANGE;
 873
 874         oobregion->offset = (section / 2) * sas;
 875
 876         if (section & 1) {
 877                 oobregion->offset += 9;
 878                 oobregion->length = 7;
 879         } else {
 880                 oobregion->length = 6;
 881
 882                 /* First sector of each page may have BBI */
 883                 if (!section) {
 884                         /*
 885                          * Small-page NAND use byte 6 for BBI while large-page
 886                          * NAND use byte 0.
 887                          */
 888                         if (cfg->page_size > 512)
 889                                 oobregion->offset++;
 890                         oobregion->length--;
 891                 }
 892         }
 893
 894         return 0;
 895 }
 896
 897 static const struct mtd_ooblayout_ops brcmnand_hamming_ooblayout_ops = {
 898         .ecc = brcmnand_hamming_ooblayout_ecc,
 899         .free = brcmnand_hamming_ooblayout_free,
 900 };
 901
 902 static int brcmnand_bch_ooblayout_ecc(struct mtd_info *mtd, int section,
 903                                       struct mtd_oob_region *oobregion)
 904 {
 905         struct nand_chip *chip = mtd_to_nand(mtd);
 906         struct brcmnand_host *host = nand_get_controller_data(chip);
 907         struct brcmnand_cfg *cfg = &host->hwcfg;
 908         int sas = cfg->spare_area_size << cfg->sector_size_1k;
 909         int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
 910
 911         if (section >= sectors)
 912                 return -ERANGE;
 913
 914         oobregion->offset = (section * (sas + 1)) - chip->ecc.bytes;
 915         oobregion->length = chip->ecc.bytes;
 916
 917         return 0;
 918 }
 919
 920 static int brcmnand_bch_ooblayout_free_lp(struct mtd_info *mtd, int section,
 921                                           struct mtd_oob_region *oobregion)
 922 {
 923         struct nand_chip *chip = mtd_to_nand(mtd);
 924         struct brcmnand_host *host = nand_get_controller_data(chip);
 925         struct brcmnand_cfg *cfg = &host->hwcfg;
 926         int sas = cfg->spare_area_size << cfg->sector_size_1k;
 927         int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
 928
 929         if (section >= sectors)
 930                 return -ERANGE;
 931
 932         if (sas <= chip->ecc.bytes)
 933                 return 0;
 934
 935         oobregion->offset = section * sas;
 936         oobregion->length = sas - chip->ecc.bytes;
 937
 938         if (!section) {
 939                 oobregion->offset++;
 940                 oobregion->length--;
 941         }
 942
 943         return 0;
 944 }
 945
 946 static int brcmnand_bch_ooblayout_free_sp(struct mtd_info *mtd, int section,
 947                                           struct mtd_oob_region *oobregion)
 948 {
 949         struct nand_chip *chip = mtd_to_nand(mtd);
 950         struct brcmnand_host *host = nand_get_controller_data(chip);
 951         struct brcmnand_cfg *cfg = &host->hwcfg;
 952         int sas = cfg->spare_area_size << cfg->sector_size_1k;
 953
 954         if (section > 1 || sas - chip->ecc.bytes < 6 ||
 955             (section && sas - chip->ecc.bytes == 6))
 956                 return -ERANGE;
 957
 958         if (!section) {
 959                 oobregion->offset = 0;
 960                 oobregion->length = 5;
 961         } else {
 962                 oobregion->offset = 6;
 963                 oobregion->length = sas - chip->ecc.bytes - 6;
 964         }
 965
 966         return 0;
 967 }
 968
 969 static const struct mtd_ooblayout_ops brcmnand_bch_lp_ooblayout_ops = {
 970         .ecc = brcmnand_bch_ooblayout_ecc,
 971         .free = brcmnand_bch_ooblayout_free_lp,
 972 };
 973
 974 static const struct mtd_ooblayout_ops brcmnand_bch_sp_ooblayout_ops = {
 975         .ecc = brcmnand_bch_ooblayout_ecc,
 976         .free = brcmnand_bch_ooblayout_free_sp,
 977 };
 978
 979 static int brcmstb_choose_ecc_layout(struct brcmnand_host *host)
 980 {
 981         struct brcmnand_cfg *p = &host->hwcfg;
 982         struct mtd_info *mtd = nand_to_mtd(&host->chip);
 983         struct nand_ecc_ctrl *ecc = &host->chip.ecc;
 984         unsigned int ecc_level = p->ecc_level;
 985         int sas = p->spare_area_size << p->sector_size_1k;
 986         int sectors = p->page_size / (512 << p->sector_size_1k);
 987
 988         if (p->sector_size_1k)
 989                 ecc_level <<= 1;
 990
 991         if (is_hamming_ecc(host->ctrl, p)) {
 992                 ecc->bytes = 3 * sectors;
 993                 mtd_set_ooblayout(mtd, &brcmnand_hamming_ooblayout_ops);
 994                 return 0;
 995         }
 996
 997         /*
 998          * CONTROLLER_VERSION:
 999          *   < v5.0: ECC_REQ = ceil(BCH_T * 13/8)
1000          *  >= v5.0: ECC_REQ = ceil(BCH_T * 14/8)
1001          * But we will just be conservative.
1002          */
1003         ecc->bytes = DIV_ROUND_UP(ecc_level * 14, 8);
1004         if (p->page_size == 512)
1005                 mtd_set_ooblayout(mtd, &brcmnand_bch_sp_ooblayout_ops);
1006         else
1007                 mtd_set_ooblayout(mtd, &brcmnand_bch_lp_ooblayout_ops);
1008
1009         if (ecc->bytes >= sas) {
1010                 dev_err(&host->pdev->dev,
1011                         "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n",
1012                         ecc->bytes, sas);
1013                 return -EINVAL;
1014         }
1015
1016         return 0;
1017 }
1018
1019 static void brcmnand_wp(struct mtd_info *mtd, int wp)
1020 {
1021         struct nand_chip *chip = mtd_to_nand(mtd);
1022         struct brcmnand_host *host = nand_get_controller_data(chip);
1023         struct brcmnand_controller *ctrl = host->ctrl;
1024
1025         if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) {
1026                 static int old_wp = -1;
1027
1028                 if (old_wp != wp) {
1029                         dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off");
1030                         old_wp = wp;
1031                 }
1032                 brcmnand_set_wp(ctrl, wp);
1033         }
1034 }
1035
1036 /* Helper functions for reading and writing OOB registers */
1037 static inline u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs)
1038 {
1039         u16 offset0, offset10, reg_offs;
1040
1041         offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE];
1042         offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE];
1043
1044         if (offs >= ctrl->max_oob)
1045                 return 0x77;
1046
1047         if (offs >= 16 && offset10)
1048                 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
1049         else
1050                 reg_offs = offset0 + (offs & ~0x03);
1051
1052         return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3));
1053 }
1054
1055 static inline void oob_reg_write(struct brcmnand_controller *ctrl, u32 offs,
1056                                  u32 data)
1057 {
1058         u16 offset0, offset10, reg_offs;
1059
1060         offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE];
1061         offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE];
1062
1063         if (offs >= ctrl->max_oob)
1064                 return;
1065
1066         if (offs >= 16 && offset10)
1067                 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
1068         else
1069                 reg_offs = offset0 + (offs & ~0x03);
1070
1071         nand_writereg(ctrl, reg_offs, data);
1072 }
1073
1074 /*
1075  * read_oob_from_regs - read data from OOB registers
1076  * @ctrl: NAND controller
1077  * @i: sub-page sector index
1078  * @oob: buffer to read to
1079  * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
1080  * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
1081  */
1082 static int read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob,
1083                               int sas, int sector_1k)
1084 {
1085         int tbytes = sas << sector_1k;
1086         int j;
1087
1088         /* Adjust OOB values for 1K sector size */
1089         if (sector_1k && (i & 0x01))
1090                 tbytes = max(0, tbytes - (int)ctrl->max_oob);
1091         tbytes = min_t(int, tbytes, ctrl->max_oob);
1092
1093         for (j = 0; j < tbytes; j++)
1094                 oob[j] = oob_reg_read(ctrl, j);
1095         return tbytes;
1096 }
1097
1098 /*
1099  * write_oob_to_regs - write data to OOB registers
1100  * @i: sub-page sector index
1101  * @oob: buffer to write from
1102  * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
1103  * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
1104  */
1105 static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i,
1106                              const u8 *oob, int sas, int sector_1k)
1107 {
1108         int tbytes = sas << sector_1k;
1109         int j;
1110
1111         /* Adjust OOB values for 1K sector size */
1112         if (sector_1k && (i & 0x01))
1113                 tbytes = max(0, tbytes - (int)ctrl->max_oob);
1114         tbytes = min_t(int, tbytes, ctrl->max_oob);
1115
1116         for (j = 0; j < tbytes; j += 4)
1117                 oob_reg_write(ctrl, j,
1118                                 (oob[j + 0] << 24) |
1119                                 (oob[j + 1] << 16) |
1120                                 (oob[j + 2] <<  8) |
1121                                 (oob[j + 3] <<  0));
1122         return tbytes;
1123 }
1124
1125 static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data)
1126 {
1127         struct brcmnand_controller *ctrl = data;
1128
1129         /* Discard all NAND_CTLRDY interrupts during DMA */
1130         if (ctrl->dma_pending)
1131                 return IRQ_HANDLED;
1132
1133         complete(&ctrl->done);
1134         return IRQ_HANDLED;
1135 }
1136
1137 /* Handle SoC-specific interrupt hardware */
1138 static irqreturn_t brcmnand_irq(int irq, void *data)
1139 {
1140         struct brcmnand_controller *ctrl = data;
1141
1142         if (ctrl->soc->ctlrdy_ack(ctrl->soc))
1143                 return brcmnand_ctlrdy_irq(irq, data);
1144
1145         return IRQ_NONE;
1146 }
1147
1148 static irqreturn_t brcmnand_dma_irq(int irq, void *data)
1149 {
1150         struct brcmnand_controller *ctrl = data;
1151
1152         complete(&ctrl->dma_done);
1153
1154         return IRQ_HANDLED;
1155 }
1156
1157 static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd)
1158 {
1159         struct brcmnand_controller *ctrl = host->ctrl;
1160         u32 intfc;
1161
1162         dev_dbg(ctrl->dev, "send native cmd %d addr_lo 0x%x\n", cmd,
1163                 brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS));
1164         BUG_ON(ctrl->cmd_pending != 0);
1165         ctrl->cmd_pending = cmd;
1166
1167         intfc = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
1168         WARN_ON(!(intfc & INTFC_CTLR_READY));
1169
1170         mb(); /* flush previous writes */
1171         brcmnand_write_reg(ctrl, BRCMNAND_CMD_START,
1172                            cmd << brcmnand_cmd_shift(ctrl));
1173 }
1174
1175 /***********************************************************************
1176  * NAND MTD API: read/program/erase
1177  ***********************************************************************/
1178
1179 static void brcmnand_cmd_ctrl(struct mtd_info *mtd, int dat,
1180         unsigned int ctrl)
1181 {
1182         /* intentionally left blank */
1183 }
1184
1185 static int brcmnand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
1186 {
1187         struct nand_chip *chip = mtd_to_nand(mtd);
1188         struct brcmnand_host *host = nand_get_controller_data(chip);
1189         struct brcmnand_controller *ctrl = host->ctrl;
1190         unsigned long timeo = msecs_to_jiffies(100);
1191
1192         dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending);
1193         if (ctrl->cmd_pending &&
1194                         wait_for_completion_timeout(&ctrl->done, timeo) <= 0) {
1195                 u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START)
1196                                         >> brcmnand_cmd_shift(ctrl);
1197
1198                 dev_err_ratelimited(ctrl->dev,
1199                         "timeout waiting for command %#02x\n", cmd);
1200                 dev_err_ratelimited(ctrl->dev, "intfc status %08x\n",
1201                         brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS));
1202         }
1203         ctrl->cmd_pending = 0;
1204         return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1205                                  INTFC_FLASH_STATUS;
1206 }
1207
1208 enum {
1209         LLOP_RE                         = BIT(16),
1210         LLOP_WE                         = BIT(17),
1211         LLOP_ALE                        = BIT(18),
1212         LLOP_CLE                        = BIT(19),
1213         LLOP_RETURN_IDLE                = BIT(31),
1214
1215         LLOP_DATA_MASK                  = GENMASK(15, 0),
1216 };
1217
1218 static int brcmnand_low_level_op(struct brcmnand_host *host,
1219                                  enum brcmnand_llop_type type, u32 data,
1220                                  bool last_op)
1221 {
1222         struct mtd_info *mtd = nand_to_mtd(&host->chip);
1223         struct nand_chip *chip = &host->chip;
1224         struct brcmnand_controller *ctrl = host->ctrl;
1225         u32 tmp;
1226
1227         tmp = data & LLOP_DATA_MASK;
1228         switch (type) {
1229         case LL_OP_CMD:
1230                 tmp |= LLOP_WE | LLOP_CLE;
1231                 break;
1232         case LL_OP_ADDR:
1233                 /* WE | ALE */
1234                 tmp |= LLOP_WE | LLOP_ALE;
1235                 break;
1236         case LL_OP_WR:
1237                 /* WE */
1238                 tmp |= LLOP_WE;
1239                 break;
1240         case LL_OP_RD:
1241                 /* RE */
1242                 tmp |= LLOP_RE;
1243                 break;
1244         }
1245         if (last_op)
1246                 /* RETURN_IDLE */
1247                 tmp |= LLOP_RETURN_IDLE;
1248
1249         dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp);
1250
1251         brcmnand_write_reg(ctrl, BRCMNAND_LL_OP, tmp);
1252         (void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP);
1253
1254         brcmnand_send_cmd(host, CMD_LOW_LEVEL_OP);
1255         return brcmnand_waitfunc(mtd, chip);
1256 }
1257
1258 static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command,
1259                              int column, int page_addr)
1260 {
1261         struct nand_chip *chip = mtd_to_nand(mtd);
1262         struct brcmnand_host *host = nand_get_controller_data(chip);
1263         struct brcmnand_controller *ctrl = host->ctrl;
1264         u64 addr = (u64)page_addr << chip->page_shift;
1265         int native_cmd = 0;
1266
1267         if (command == NAND_CMD_READID || command == NAND_CMD_PARAM ||
1268                         command == NAND_CMD_RNDOUT)
1269                 addr = (u64)column;
1270         /* Avoid propagating a negative, don't-care address */
1271         else if (page_addr < 0)
1272                 addr = 0;
1273
1274         dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command,
1275                 (unsigned long long)addr);
1276
1277         host->last_cmd = command;
1278         host->last_byte = 0;
1279         host->last_addr = addr;
1280
1281         switch (command) {
1282         case NAND_CMD_RESET:
1283                 native_cmd = CMD_FLASH_RESET;
1284                 break;
1285         case NAND_CMD_STATUS:
1286                 native_cmd = CMD_STATUS_READ;
1287                 break;
1288         case NAND_CMD_READID:
1289                 native_cmd = CMD_DEVICE_ID_READ;
1290                 break;
1291         case NAND_CMD_READOOB:
1292                 native_cmd = CMD_SPARE_AREA_READ;
1293                 break;
1294         case NAND_CMD_ERASE1:
1295                 native_cmd = CMD_BLOCK_ERASE;
1296                 brcmnand_wp(mtd, 0);
1297                 break;
1298         case NAND_CMD_PARAM:
1299                 native_cmd = CMD_PARAMETER_READ;
1300                 break;
1301         case NAND_CMD_SET_FEATURES:
1302         case NAND_CMD_GET_FEATURES:
1303                 brcmnand_low_level_op(host, LL_OP_CMD, command, false);
1304                 brcmnand_low_level_op(host, LL_OP_ADDR, column, false);
1305                 break;
1306         case NAND_CMD_RNDOUT:
1307                 native_cmd = CMD_PARAMETER_CHANGE_COL;
1308                 addr &= ~((u64)(FC_BYTES - 1));
1309                 /*
1310                  * HW quirk: PARAMETER_CHANGE_COL requires SECTOR_SIZE_1K=0
1311                  * NB: hwcfg.sector_size_1k may not be initialized yet
1312                  */
1313                 if (brcmnand_get_sector_size_1k(host)) {
1314                         host->hwcfg.sector_size_1k =
1315                                 brcmnand_get_sector_size_1k(host);
1316                         brcmnand_set_sector_size_1k(host, 0);
1317                 }
1318                 break;
1319         }
1320
1321         if (!native_cmd)
1322                 return;
1323
1324         brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1325                 (host->cs << 16) | ((addr >> 32) & 0xffff));
1326         (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1327         brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, lower_32_bits(addr));
1328         (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1329
1330         brcmnand_send_cmd(host, native_cmd);
1331         brcmnand_waitfunc(mtd, chip);
1332
1333         if (native_cmd == CMD_PARAMETER_READ ||
1334                         native_cmd == CMD_PARAMETER_CHANGE_COL) {
1335                 /* Copy flash cache word-wise */
1336                 u32 *flash_cache = (u32 *)ctrl->flash_cache;
1337                 int i;
1338
1339                 brcmnand_soc_data_bus_prepare(ctrl->soc, true);
1340
1341                 /*
1342                  * Must cache the FLASH_CACHE now, since changes in
1343                  * SECTOR_SIZE_1K may invalidate it
1344                  */
1345                 for (i = 0; i < FC_WORDS; i++)
1346                         /*
1347                          * Flash cache is big endian for parameter pages, at
1348                          * least on STB SoCs
1349                          */
1350                         flash_cache[i] = be32_to_cpu(brcmnand_read_fc(ctrl, i));
1351
1352                 brcmnand_soc_data_bus_unprepare(ctrl->soc, true);
1353
1354                 /* Cleanup from HW quirk: restore SECTOR_SIZE_1K */
1355                 if (host->hwcfg.sector_size_1k)
1356                         brcmnand_set_sector_size_1k(host,
1357                                                     host->hwcfg.sector_size_1k);
1358         }
1359
1360         /* Re-enable protection is necessary only after erase */
1361         if (command == NAND_CMD_ERASE1)
1362                 brcmnand_wp(mtd, 1);
1363 }
1364
1365 static uint8_t brcmnand_read_byte(struct mtd_info *mtd)
1366 {
1367         struct nand_chip *chip = mtd_to_nand(mtd);
1368         struct brcmnand_host *host = nand_get_controller_data(chip);
1369         struct brcmnand_controller *ctrl = host->ctrl;
1370         uint8_t ret = 0;
1371         int addr, offs;
1372
1373         switch (host->last_cmd) {
1374         case NAND_CMD_READID:
1375                 if (host->last_byte < 4)
1376                         ret = brcmnand_read_reg(ctrl, BRCMNAND_ID) >>
1377                                 (24 - (host->last_byte << 3));
1378                 else if (host->last_byte < 8)
1379                         ret = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT) >>
1380                                 (56 - (host->last_byte << 3));
1381                 break;
1382
1383         case NAND_CMD_READOOB:
1384                 ret = oob_reg_read(ctrl, host->last_byte);
1385                 break;
1386
1387         case NAND_CMD_STATUS:
1388                 ret = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1389                                         INTFC_FLASH_STATUS;
1390                 if (wp_on) /* hide WP status */
1391                         ret |= NAND_STATUS_WP;
1392                 break;
1393
1394         case NAND_CMD_PARAM:
1395         case NAND_CMD_RNDOUT:
1396                 addr = host->last_addr + host->last_byte;
1397                 offs = addr & (FC_BYTES - 1);
1398
1399                 /* At FC_BYTES boundary, switch to next column */
1400                 if (host->last_byte > 0 && offs == 0)
1401                         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, addr, -1);
1402
1403                 ret = ctrl->flash_cache[offs];
1404                 break;
1405         case NAND_CMD_GET_FEATURES:
1406                 if (host->last_byte >= ONFI_SUBFEATURE_PARAM_LEN) {
1407                         ret = 0;
1408                 } else {
1409                         bool last = host->last_byte ==
1410                                 ONFI_SUBFEATURE_PARAM_LEN - 1;
1411                         brcmnand_low_level_op(host, LL_OP_RD, 0, last);
1412                         ret = brcmnand_read_reg(ctrl, BRCMNAND_LL_RDATA) & 0xff;
1413                 }
1414         }
1415
1416         dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret);
1417         host->last_byte++;
1418
1419         return ret;
1420 }
1421
1422 static void brcmnand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1423 {
1424         int i;
1425
1426         for (i = 0; i < len; i++, buf++)
1427                 *buf = brcmnand_read_byte(mtd);
1428 }
1429
1430 static void brcmnand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
1431                                    int len)
1432 {
1433         int i;
1434         struct nand_chip *chip = mtd_to_nand(mtd);
1435         struct brcmnand_host *host = nand_get_controller_data(chip);
1436
1437         switch (host->last_cmd) {
1438         case NAND_CMD_SET_FEATURES:
1439                 for (i = 0; i < len; i++)
1440                         brcmnand_low_level_op(host, LL_OP_WR, buf[i],
1441                                                   (i + 1) == len);
1442                 break;
1443         default:
1444                 BUG();
1445                 break;
1446         }
1447 }
1448
1449 /**
1450  * Construct a FLASH_DMA descriptor as part of a linked list. You must know the
1451  * following ahead of time:
1452  *  - Is this descriptor the beginning or end of a linked list?
1453  *  - What is the (DMA) address of the next descriptor in the linked list?
1454  */
1455 static int brcmnand_fill_dma_desc(struct brcmnand_host *host,
1456                                   struct brcm_nand_dma_desc *desc, u64 addr,
1457                                   dma_addr_t buf, u32 len, u8 dma_cmd,
1458                                   bool begin, bool end,
1459                                   dma_addr_t next_desc)
1460 {
1461         memset(desc, 0, sizeof(*desc));
1462         /* Descriptors are written in native byte order (wordwise) */
1463         desc->next_desc = lower_32_bits(next_desc);
1464         desc->next_desc_ext = upper_32_bits(next_desc);
1465         desc->cmd_irq = (dma_cmd << 24) |
1466                 (end ? (0x03 << 8) : 0) | /* IRQ | STOP */
1467                 (!!begin) | ((!!end) << 1); /* head, tail */
1468 #ifdef CONFIG_CPU_BIG_ENDIAN
1469         desc->cmd_irq |= 0x01 << 12;
1470 #endif
1471         desc->dram_addr = lower_32_bits(buf);
1472         desc->dram_addr_ext = upper_32_bits(buf);
1473         desc->tfr_len = len;
1474         desc->total_len = len;
1475         desc->flash_addr = lower_32_bits(addr);
1476         desc->flash_addr_ext = upper_32_bits(addr);
1477         desc->cs = host->cs;
1478         desc->status_valid = 0x01;
1479         return 0;
1480 }
1481
1482 /**
1483  * Kick the FLASH_DMA engine, with a given DMA descriptor
1484  */
1485 static void brcmnand_dma_run(struct brcmnand_host *host, dma_addr_t desc)
1486 {
1487         struct brcmnand_controller *ctrl = host->ctrl;
1488         unsigned long timeo = msecs_to_jiffies(100);
1489
1490         flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc));
1491         (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC);
1492         flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, upper_32_bits(desc));
1493         (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT);
1494
1495         /* Start FLASH_DMA engine */
1496         ctrl->dma_pending = true;
1497         mb(); /* flush previous writes */
1498         flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */
1499
1500         if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) {
1501                 dev_err(ctrl->dev,
1502                                 "timeout waiting for DMA; status %#x, error status %#x\n",
1503                                 flash_dma_readl(ctrl, FLASH_DMA_STATUS),
1504                                 flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS));
1505         }
1506         ctrl->dma_pending = false;
1507         flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */
1508 }
1509
1510 static int brcmnand_dma_trans(struct brcmnand_host *host, u64 addr, u32 *buf,
1511                               u32 len, u8 dma_cmd)
1512 {
1513         struct brcmnand_controller *ctrl = host->ctrl;
1514         dma_addr_t buf_pa;
1515         int dir = dma_cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1516
1517         buf_pa = dma_map_single(ctrl->dev, buf, len, dir);
1518         if (dma_mapping_error(ctrl->dev, buf_pa)) {
1519                 dev_err(ctrl->dev, "unable to map buffer for DMA\n");
1520                 return -ENOMEM;
1521         }
1522
1523         brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len,
1524                                    dma_cmd, true, true, 0);
1525
1526         brcmnand_dma_run(host, ctrl->dma_pa);
1527
1528         dma_unmap_single(ctrl->dev, buf_pa, len, dir);
1529
1530         if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR)
1531                 return -EBADMSG;
1532         else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR)
1533                 return -EUCLEAN;
1534
1535         return 0;
1536 }
1537
1538 /*
1539  * Assumes proper CS is already set
1540  */
1541 static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip,
1542                                 u64 addr, unsigned int trans, u32 *buf,
1543                                 u8 *oob, u64 *err_addr)
1544 {
1545         struct brcmnand_host *host = nand_get_controller_data(chip);
1546         struct brcmnand_controller *ctrl = host->ctrl;
1547         int i, j, ret = 0;
1548
1549         /* Clear error addresses */
1550         brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0);
1551         brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0);
1552         brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_EXT_ADDR, 0);
1553         brcmnand_write_reg(ctrl, BRCMNAND_CORR_EXT_ADDR, 0);
1554
1555         brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1556                         (host->cs << 16) | ((addr >> 32) & 0xffff));
1557         (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1558
1559         for (i = 0; i < trans; i++, addr += FC_BYTES) {
1560                 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1561                                    lower_32_bits(addr));
1562                 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1563                 /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */
1564                 brcmnand_send_cmd(host, CMD_PAGE_READ);
1565                 brcmnand_waitfunc(mtd, chip);
1566
1567                 if (likely(buf)) {
1568                         brcmnand_soc_data_bus_prepare(ctrl->soc, false);
1569
1570                         for (j = 0; j < FC_WORDS; j++, buf++)
1571                                 *buf = brcmnand_read_fc(ctrl, j);
1572
1573                         brcmnand_soc_data_bus_unprepare(ctrl->soc, false);
1574                 }
1575
1576                 if (oob)
1577                         oob += read_oob_from_regs(ctrl, i, oob,
1578                                         mtd->oobsize / trans,
1579                                         host->hwcfg.sector_size_1k);
1580
1581                 if (!ret) {
1582                         *err_addr = brcmnand_read_reg(ctrl,
1583                                         BRCMNAND_UNCORR_ADDR) |
1584                                 ((u64)(brcmnand_read_reg(ctrl,
1585                                                 BRCMNAND_UNCORR_EXT_ADDR)
1586                                         & 0xffff) << 32);
1587                         if (*err_addr)
1588                                 ret = -EBADMSG;
1589                 }
1590
1591                 if (!ret) {
1592                         *err_addr = brcmnand_read_reg(ctrl,
1593                                         BRCMNAND_CORR_ADDR) |
1594                                 ((u64)(brcmnand_read_reg(ctrl,
1595                                                 BRCMNAND_CORR_EXT_ADDR)
1596                                         & 0xffff) << 32);
1597                         if (*err_addr)
1598                                 ret = -EUCLEAN;
1599                 }
1600         }
1601
1602         return ret;
1603 }
1604
1605 /*
1606  * Check a page to see if it is erased (w/ bitflips) after an uncorrectable ECC
1607  * error
1608  *
1609  * Because the HW ECC signals an ECC error if an erase paged has even a single
1610  * bitflip, we must check each ECC error to see if it is actually an erased
1611  * page with bitflips, not a truly corrupted page.
1612  *
1613  * On a real error, return a negative error code (-EBADMSG for ECC error), and
1614  * buf will contain raw data.
1615  * Otherwise, buf gets filled with 0xffs and return the maximum number of
1616  * bitflips-per-ECC-sector to the caller.
1617  *
1618  */
1619 static int brcmstb_nand_verify_erased_page(struct mtd_info *mtd,
1620                   struct nand_chip *chip, void *buf, u64 addr)
1621 {
1622         int i, sas;
1623         void *oob = chip->oob_poi;
1624         int bitflips = 0;
1625         int page = addr >> chip->page_shift;
1626         int ret;
1627
1628         if (!buf) {
1629                 buf = chip->buffers->databuf;
1630                 /* Invalidate page cache */
1631                 chip->pagebuf = -1;
1632         }
1633
1634         sas = mtd->oobsize / chip->ecc.steps;
1635
1636         /* read without ecc for verification */
1637         chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1638         ret = chip->ecc.read_page_raw(mtd, chip, buf, true, page);
1639         if (ret)
1640                 return ret;
1641
1642         for (i = 0; i < chip->ecc.steps; i++, oob += sas) {
1643                 ret = nand_check_erased_ecc_chunk(buf, chip->ecc.size,
1644                                                   oob, sas, NULL, 0,
1645                                                   chip->ecc.strength);
1646                 if (ret < 0)
1647                         return ret;
1648
1649                 bitflips = max(bitflips, ret);
1650         }
1651
1652         return bitflips;
1653 }
1654
1655 static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip,
1656                          u64 addr, unsigned int trans, u32 *buf, u8 *oob)
1657 {
1658         struct brcmnand_host *host = nand_get_controller_data(chip);
1659         struct brcmnand_controller *ctrl = host->ctrl;
1660         u64 err_addr = 0;
1661         int err;
1662         bool retry = true;
1663
1664         dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf);
1665
1666 try_dmaread:
1667         brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_COUNT, 0);
1668
1669         if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1670                 err = brcmnand_dma_trans(host, addr, buf, trans * FC_BYTES,
1671                                              CMD_PAGE_READ);
1672                 if (err) {
1673                         if (mtd_is_bitflip_or_eccerr(err))
1674                                 err_addr = addr;
1675                         else
1676                                 return -EIO;
1677                 }
1678         } else {
1679                 if (oob)
1680                         memset(oob, 0x99, mtd->oobsize);
1681
1682                 err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf,
1683                                                oob, &err_addr);
1684         }
1685
1686         if (mtd_is_eccerr(err)) {
1687                 /*
1688                  * On controller version and 7.0, 7.1 , DMA read after a
1689                  * prior PIO read that reported uncorrectable error,
1690                  * the DMA engine captures this error following DMA read
1691                  * cleared only on subsequent DMA read, so just retry once
1692                  * to clear a possible false error reported for current DMA
1693                  * read
1694                  */
1695                 if ((ctrl->nand_version == 0x0700) ||
1696                     (ctrl->nand_version == 0x0701)) {
1697                         if (retry) {
1698                                 retry = false;
1699                                 goto try_dmaread;
1700                         }
1701                 }
1702
1703                 /*
1704                  * Controller version 7.2 has hw encoder to detect erased page
1705                  * bitflips, apply sw verification for older controllers only
1706                  */
1707                 if (ctrl->nand_version < 0x0702) {
1708                         err = brcmstb_nand_verify_erased_page(mtd, chip, buf,
1709                                                               addr);
1710                         /* erased page bitflips corrected */
1711                         if (err > 0)
1712                                 return err;
1713                 }
1714
1715                 dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n",
1716                         (unsigned long long)err_addr);
1717                 mtd->ecc_stats.failed++;
1718                 /* NAND layer expects zero on ECC errors */
1719                 return 0;
1720         }
1721
1722         if (mtd_is_bitflip(err)) {
1723                 unsigned int corrected = brcmnand_count_corrected(ctrl);
1724
1725                 dev_dbg(ctrl->dev, "corrected error at 0x%llx\n",
1726                         (unsigned long long)err_addr);
1727                 mtd->ecc_stats.corrected += corrected;
1728                 /* Always exceed the software-imposed threshold */
1729                 return max(mtd->bitflip_threshold, corrected);
1730         }
1731
1732         return 0;
1733 }
1734
1735 static int brcmnand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1736                               uint8_t *buf, int oob_required, int page)
1737 {
1738         struct brcmnand_host *host = nand_get_controller_data(chip);
1739         u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1740
1741         return brcmnand_read(mtd, chip, host->last_addr,
1742                         mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1743 }
1744
1745 static int brcmnand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1746                                   uint8_t *buf, int oob_required, int page)
1747 {
1748         struct brcmnand_host *host = nand_get_controller_data(chip);
1749         u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1750         int ret;
1751
1752         brcmnand_set_ecc_enabled(host, 0);
1753         ret = brcmnand_read(mtd, chip, host->last_addr,
1754                         mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1755         brcmnand_set_ecc_enabled(host, 1);
1756         return ret;
1757 }
1758
1759 static int brcmnand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1760                              int page)
1761 {
1762         return brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1763                         mtd->writesize >> FC_SHIFT,
1764                         NULL, (u8 *)chip->oob_poi);
1765 }
1766
1767 static int brcmnand_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1768                                  int page)
1769 {
1770         struct brcmnand_host *host = nand_get_controller_data(chip);
1771
1772         brcmnand_set_ecc_enabled(host, 0);
1773         brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1774                 mtd->writesize >> FC_SHIFT,
1775                 NULL, (u8 *)chip->oob_poi);
1776         brcmnand_set_ecc_enabled(host, 1);
1777         return 0;
1778 }
1779
1780 static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip,
1781                           u64 addr, const u32 *buf, u8 *oob)
1782 {
1783         struct brcmnand_host *host = nand_get_controller_data(chip);
1784         struct brcmnand_controller *ctrl = host->ctrl;
1785         unsigned int i, j, trans = mtd->writesize >> FC_SHIFT;
1786         int status, ret = 0;
1787
1788         dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf);
1789
1790         if (unlikely((unsigned long)buf & 0x03)) {
1791                 dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf);
1792                 buf = (u32 *)((unsigned long)buf & ~0x03);
1793         }
1794
1795         brcmnand_wp(mtd, 0);
1796
1797         for (i = 0; i < ctrl->max_oob; i += 4)
1798                 oob_reg_write(ctrl, i, 0xffffffff);
1799
1800         if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1801                 if (brcmnand_dma_trans(host, addr, (u32 *)buf,
1802                                         mtd->writesize, CMD_PROGRAM_PAGE))
1803                         ret = -EIO;
1804                 goto out;
1805         }
1806
1807         brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1808                         (host->cs << 16) | ((addr >> 32) & 0xffff));
1809         (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1810
1811         for (i = 0; i < trans; i++, addr += FC_BYTES) {
1812                 /* full address MUST be set before populating FC */
1813                 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1814                                    lower_32_bits(addr));
1815                 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1816
1817                 if (buf) {
1818                         brcmnand_soc_data_bus_prepare(ctrl->soc, false);
1819
1820                         for (j = 0; j < FC_WORDS; j++, buf++)
1821                                 brcmnand_write_fc(ctrl, j, *buf);
1822
1823                         brcmnand_soc_data_bus_unprepare(ctrl->soc, false);
1824                 } else if (oob) {
1825                         for (j = 0; j < FC_WORDS; j++)
1826                                 brcmnand_write_fc(ctrl, j, 0xffffffff);
1827                 }
1828
1829                 if (oob) {
1830                         oob += write_oob_to_regs(ctrl, i, oob,
1831                                         mtd->oobsize / trans,
1832                                         host->hwcfg.sector_size_1k);
1833                 }
1834
1835                 /* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */
1836                 brcmnand_send_cmd(host, CMD_PROGRAM_PAGE);
1837                 status = brcmnand_waitfunc(mtd, chip);
1838
1839                 if (status & NAND_STATUS_FAIL) {
1840                         dev_info(ctrl->dev, "program failed at %llx\n",
1841                                 (unsigned long long)addr);
1842                         ret = -EIO;
1843                         goto out;
1844                 }
1845         }
1846 out:
1847         brcmnand_wp(mtd, 1);
1848         return ret;
1849 }
1850
1851 static int brcmnand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1852                                const uint8_t *buf, int oob_required, int page)
1853 {
1854         struct brcmnand_host *host = nand_get_controller_data(chip);
1855         void *oob = oob_required ? chip->oob_poi : NULL;
1856
1857         brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1858         return 0;
1859 }
1860
1861 static int brcmnand_write_page_raw(struct mtd_info *mtd,
1862                                    struct nand_chip *chip, const uint8_t *buf,
1863                                    int oob_required, int page)
1864 {
1865         struct brcmnand_host *host = nand_get_controller_data(chip);
1866         void *oob = oob_required ? chip->oob_poi : NULL;
1867
1868         brcmnand_set_ecc_enabled(host, 0);
1869         brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1870         brcmnand_set_ecc_enabled(host, 1);
1871         return 0;
1872 }
1873
1874 static int brcmnand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1875                                   int page)
1876 {
1877         return brcmnand_write(mtd, chip, (u64)page << chip->page_shift,
1878                                   NULL, chip->oob_poi);
1879 }
1880
1881 static int brcmnand_write_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1882                                   int page)
1883 {
1884         struct brcmnand_host *host = nand_get_controller_data(chip);
1885         int ret;
1886
1887         brcmnand_set_ecc_enabled(host, 0);
1888         ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL,
1889                                  (u8 *)chip->oob_poi);
1890         brcmnand_set_ecc_enabled(host, 1);
1891
1892         return ret;
1893 }
1894
1895 /***********************************************************************
1896  * Per-CS setup (1 NAND device)
1897  ***********************************************************************/
1898
1899 static int brcmnand_set_cfg(struct brcmnand_host *host,
1900                             struct brcmnand_cfg *cfg)
1901 {
1902         struct brcmnand_controller *ctrl = host->ctrl;
1903         struct nand_chip *chip = &host->chip;
1904         u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
1905         u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
1906                         BRCMNAND_CS_CFG_EXT);
1907         u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
1908                         BRCMNAND_CS_ACC_CONTROL);
1909         u8 block_size = 0, page_size = 0, device_size = 0;
1910         u32 tmp;
1911
1912         if (ctrl->block_sizes) {
1913                 int i, found;
1914
1915                 for (i = 0, found = 0; ctrl->block_sizes[i]; i++)
1916                         if (ctrl->block_sizes[i] * 1024 == cfg->block_size) {
1917                                 block_size = i;
1918                                 found = 1;
1919                         }
1920                 if (!found) {
1921                         dev_warn(ctrl->dev, "invalid block size %u\n",
1922                                         cfg->block_size);
1923                         return -EINVAL;
1924                 }
1925         } else {
1926                 block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE);
1927         }
1928
1929         if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size &&
1930                                 cfg->block_size > ctrl->max_block_size)) {
1931                 dev_warn(ctrl->dev, "invalid block size %u\n",
1932                                 cfg->block_size);
1933                 block_size = 0;
1934         }
1935
1936         if (ctrl->page_sizes) {
1937                 int i, found;
1938
1939                 for (i = 0, found = 0; ctrl->page_sizes[i]; i++)
1940                         if (ctrl->page_sizes[i] == cfg->page_size) {
1941                                 page_size = i;
1942                                 found = 1;
1943                         }
1944                 if (!found) {
1945                         dev_warn(ctrl->dev, "invalid page size %u\n",
1946                                         cfg->page_size);
1947                         return -EINVAL;
1948                 }
1949         } else {
1950                 page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE);
1951         }
1952
1953         if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size &&
1954                                 cfg->page_size > ctrl->max_page_size)) {
1955                 dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size);
1956                 return -EINVAL;
1957         }
1958
1959         if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) {
1960                 dev_warn(ctrl->dev, "invalid device size 0x%llx\n",
1961                         (unsigned long long)cfg->device_size);
1962                 return -EINVAL;
1963         }
1964         device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE);
1965
1966         tmp = (cfg->blk_adr_bytes << CFG_BLK_ADR_BYTES_SHIFT) |
1967                 (cfg->col_adr_bytes << CFG_COL_ADR_BYTES_SHIFT) |
1968                 (cfg->ful_adr_bytes << CFG_FUL_ADR_BYTES_SHIFT) |
1969                 (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) |
1970                 (device_size << CFG_DEVICE_SIZE_SHIFT);
1971         if (cfg_offs == cfg_ext_offs) {
1972                 tmp |= (page_size << CFG_PAGE_SIZE_SHIFT) |
1973                        (block_size << CFG_BLK_SIZE_SHIFT);
1974                 nand_writereg(ctrl, cfg_offs, tmp);
1975         } else {
1976                 nand_writereg(ctrl, cfg_offs, tmp);
1977                 tmp = (page_size << CFG_EXT_PAGE_SIZE_SHIFT) |
1978                       (block_size << CFG_EXT_BLK_SIZE_SHIFT);
1979                 nand_writereg(ctrl, cfg_ext_offs, tmp);
1980         }
1981
1982         tmp = nand_readreg(ctrl, acc_control_offs);
1983         tmp &= ~brcmnand_ecc_level_mask(ctrl);
1984         tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
1985         tmp &= ~brcmnand_spare_area_mask(ctrl);
1986         tmp |= cfg->spare_area_size;
1987         nand_writereg(ctrl, acc_control_offs, tmp);
1988
1989         brcmnand_set_sector_size_1k(host, cfg->sector_size_1k);
1990
1991         /* threshold = ceil(BCH-level * 0.75) */
1992         brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4));
1993
1994         return 0;
1995 }
1996
1997 static void brcmnand_print_cfg(struct brcmnand_host *host,
1998                                char *buf, struct brcmnand_cfg *cfg)
1999 {
2000         buf += sprintf(buf,
2001                 "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit",
2002                 (unsigned long long)cfg->device_size >> 20,
2003                 cfg->block_size >> 10,
2004                 cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size,
2005                 cfg->page_size >= 1024 ? "KiB" : "B",
2006                 cfg->spare_area_size, cfg->device_width);
2007
2008         /* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */
2009         if (is_hamming_ecc(host->ctrl, cfg))
2010                 sprintf(buf, ", Hamming ECC");
2011         else if (cfg->sector_size_1k)
2012                 sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1);
2013         else
2014                 sprintf(buf, ", BCH-%u", cfg->ecc_level);
2015 }
2016
2017 /*
2018  * Minimum number of bytes to address a page. Calculated as:
2019  *     roundup(log2(size / page-size) / 8)
2020  *
2021  * NB: the following does not "round up" for non-power-of-2 'size'; but this is
2022  *     OK because many other things will break if 'size' is irregular...
2023  */
2024 static inline int get_blk_adr_bytes(u64 size, u32 writesize)
2025 {
2026         return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3;
2027 }
2028
2029 static int brcmnand_setup_dev(struct brcmnand_host *host)
2030 {
2031         struct mtd_info *mtd = nand_to_mtd(&host->chip);
2032         struct nand_chip *chip = &host->chip;
2033         struct brcmnand_controller *ctrl = host->ctrl;
2034         struct brcmnand_cfg *cfg = &host->hwcfg;
2035         char msg[128];
2036         u32 offs, tmp, oob_sector;
2037         int ret;
2038
2039         memset(cfg, 0, sizeof(*cfg));
2040
2041         ret = of_property_read_u32(nand_get_flash_node(chip),
2042                                    "brcm,nand-oob-sector-size",
2043                                    &oob_sector);
2044         if (ret) {
2045                 /* Use detected size */
2046                 cfg->spare_area_size = mtd->oobsize /
2047                                         (mtd->writesize >> FC_SHIFT);
2048         } else {
2049                 cfg->spare_area_size = oob_sector;
2050         }
2051         if (cfg->spare_area_size > ctrl->max_oob)
2052                 cfg->spare_area_size = ctrl->max_oob;
2053         /*
2054          * Set oobsize to be consistent with controller's spare_area_size, as
2055          * the rest is inaccessible.
2056          */
2057         mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT);
2058
2059         cfg->device_size = mtd->size;
2060         cfg->block_size = mtd->erasesize;
2061         cfg->page_size = mtd->writesize;
2062         cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8;
2063         cfg->col_adr_bytes = 2;
2064         cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize);
2065
2066         if (chip->ecc.mode != NAND_ECC_HW) {
2067                 dev_err(ctrl->dev, "only HW ECC supported; selected: %d\n",
2068                         chip->ecc.mode);
2069                 return -EINVAL;
2070         }
2071
2072         if (chip->ecc.algo == NAND_ECC_UNKNOWN) {
2073                 if (chip->ecc.strength == 1 && chip->ecc.size == 512)
2074                         /* Default to Hamming for 1-bit ECC, if unspecified */
2075                         chip->ecc.algo = NAND_ECC_HAMMING;
2076                 else
2077                         /* Otherwise, BCH */
2078                         chip->ecc.algo = NAND_ECC_BCH;
2079         }
2080
2081         if (chip->ecc.algo == NAND_ECC_HAMMING && (chip->ecc.strength != 1 ||
2082                                                    chip->ecc.size != 512)) {
2083                 dev_err(ctrl->dev, "invalid Hamming params: %d bits per %d bytes\n",
2084                         chip->ecc.strength, chip->ecc.size);
2085                 return -EINVAL;
2086         }
2087
2088         switch (chip->ecc.size) {
2089         case 512:
2090                 if (chip->ecc.algo == NAND_ECC_HAMMING)
2091                         cfg->ecc_level = 15;
2092                 else
2093                         cfg->ecc_level = chip->ecc.strength;
2094                 cfg->sector_size_1k = 0;
2095                 break;
2096         case 1024:
2097                 if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) {
2098                         dev_err(ctrl->dev, "1KB sectors not supported\n");
2099                         return -EINVAL;
2100                 }
2101                 if (chip->ecc.strength & 0x1) {
2102                         dev_err(ctrl->dev,
2103                                 "odd ECC not supported with 1KB sectors\n");
2104                         return -EINVAL;
2105                 }
2106
2107                 cfg->ecc_level = chip->ecc.strength >> 1;
2108                 cfg->sector_size_1k = 1;
2109                 break;
2110         default:
2111                 dev_err(ctrl->dev, "unsupported ECC size: %d\n",
2112                         chip->ecc.size);
2113                 return -EINVAL;
2114         }
2115
2116         cfg->ful_adr_bytes = cfg->blk_adr_bytes;
2117         if (mtd->writesize > 512)
2118                 cfg->ful_adr_bytes += cfg->col_adr_bytes;
2119         else
2120                 cfg->ful_adr_bytes += 1;
2121
2122         ret = brcmnand_set_cfg(host, cfg);
2123         if (ret)
2124                 return ret;
2125
2126         brcmnand_set_ecc_enabled(host, 1);
2127
2128         brcmnand_print_cfg(host, msg, cfg);
2129         dev_info(ctrl->dev, "detected %s\n", msg);
2130
2131         /* Configure ACC_CONTROL */
2132         offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
2133         tmp = nand_readreg(ctrl, offs);
2134         tmp &= ~ACC_CONTROL_PARTIAL_PAGE;
2135         tmp &= ~ACC_CONTROL_RD_ERASED;
2136
2137         /* We need to turn on Read from erased paged protected by ECC */
2138         if (ctrl->nand_version >= 0x0702)
2139                 tmp |= ACC_CONTROL_RD_ERASED;
2140         tmp &= ~ACC_CONTROL_FAST_PGM_RDIN;
2141         if (ctrl->features & BRCMNAND_HAS_PREFETCH) {
2142                 /*
2143                  * FIXME: Flash DMA + prefetch may see spurious erased-page ECC
2144                  * errors
2145                  */
2146                 if (has_flash_dma(ctrl))
2147                         tmp &= ~ACC_CONTROL_PREFETCH;
2148                 else
2149                         tmp |= ACC_CONTROL_PREFETCH;
2150         }
2151         nand_writereg(ctrl, offs, tmp);
2152
2153         return 0;
2154 }
2155
2156 static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn)
2157 {
2158         struct brcmnand_controller *ctrl = host->ctrl;
2159         struct platform_device *pdev = host->pdev;
2160         struct mtd_info *mtd;
2161         struct nand_chip *chip;
2162         int ret;
2163         u16 cfg_offs;
2164
2165         ret = of_property_read_u32(dn, "reg", &host->cs);
2166         if (ret) {
2167                 dev_err(&pdev->dev, "can't get chip-select\n");
2168                 return -ENXIO;
2169         }
2170
2171         mtd = nand_to_mtd(&host->chip);
2172         chip = &host->chip;
2173
2174         nand_set_flash_node(chip, dn);
2175         nand_set_controller_data(chip, host);
2176         mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "brcmnand.%d",
2177                                    host->cs);
2178         mtd->owner = THIS_MODULE;
2179         mtd->dev.parent = &pdev->dev;
2180
2181         chip->IO_ADDR_R = (void __iomem *)0xdeadbeef;
2182         chip->IO_ADDR_W = (void __iomem *)0xdeadbeef;
2183
2184         chip->cmd_ctrl = brcmnand_cmd_ctrl;
2185         chip->cmdfunc = brcmnand_cmdfunc;
2186         chip->waitfunc = brcmnand_waitfunc;
2187         chip->read_byte = brcmnand_read_byte;
2188         chip->read_buf = brcmnand_read_buf;
2189         chip->write_buf = brcmnand_write_buf;
2190
2191         chip->ecc.mode = NAND_ECC_HW;
2192         chip->ecc.read_page = brcmnand_read_page;
2193         chip->ecc.write_page = brcmnand_write_page;
2194         chip->ecc.read_page_raw = brcmnand_read_page_raw;
2195         chip->ecc.write_page_raw = brcmnand_write_page_raw;
2196         chip->ecc.write_oob_raw = brcmnand_write_oob_raw;
2197         chip->ecc.read_oob_raw = brcmnand_read_oob_raw;
2198         chip->ecc.read_oob = brcmnand_read_oob;
2199         chip->ecc.write_oob = brcmnand_write_oob;
2200
2201         chip->controller = &ctrl->controller;
2202
2203         /*
2204          * The bootloader might have configured 16bit mode but
2205          * NAND READID command only works in 8bit mode. We force
2206          * 8bit mode here to ensure that NAND READID commands works.
2207          */
2208         cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
2209         nand_writereg(ctrl, cfg_offs,
2210                       nand_readreg(ctrl, cfg_offs) & ~CFG_BUS_WIDTH);
2211
2212         if (nand_scan_ident(mtd, 1, NULL))
2213                 return -ENXIO;
2214
2215         chip->options |= NAND_NO_SUBPAGE_WRITE;
2216         /*
2217          * Avoid (for instance) kmap()'d buffers from JFFS2, which we can't DMA
2218          * to/from, and have nand_base pass us a bounce buffer instead, as
2219          * needed.
2220          */
2221         chip->options |= NAND_USE_BOUNCE_BUFFER;
2222
2223         if (chip->bbt_options & NAND_BBT_USE_FLASH)
2224                 chip->bbt_options |= NAND_BBT_NO_OOB;
2225
2226         if (brcmnand_setup_dev(host))
2227                 return -ENXIO;
2228
2229         chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512;
2230         /* only use our internal HW threshold */
2231         mtd->bitflip_threshold = 1;
2232
2233         ret = brcmstb_choose_ecc_layout(host);
2234         if (ret)
2235                 return ret;
2236
2237         if (nand_scan_tail(mtd))
2238                 return -ENXIO;
2239
2240         return mtd_device_register(mtd, NULL, 0);
2241 }
2242
2243 static void brcmnand_save_restore_cs_config(struct brcmnand_host *host,
2244                                             int restore)
2245 {
2246         struct brcmnand_controller *ctrl = host->ctrl;
2247         u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
2248         u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
2249                         BRCMNAND_CS_CFG_EXT);
2250         u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
2251                         BRCMNAND_CS_ACC_CONTROL);
2252         u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1);
2253         u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2);
2254
2255         if (restore) {
2256                 nand_writereg(ctrl, cfg_offs, host->hwcfg.config);
2257                 if (cfg_offs != cfg_ext_offs)
2258                         nand_writereg(ctrl, cfg_ext_offs,
2259                                       host->hwcfg.config_ext);
2260                 nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control);
2261                 nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1);
2262                 nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2);
2263         } else {
2264                 host->hwcfg.config = nand_readreg(ctrl, cfg_offs);
2265                 if (cfg_offs != cfg_ext_offs)
2266                         host->hwcfg.config_ext =
2267                                 nand_readreg(ctrl, cfg_ext_offs);
2268                 host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs);
2269                 host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs);
2270                 host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs);
2271         }
2272 }
2273
2274 static int brcmnand_suspend(struct device *dev)
2275 {
2276         struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
2277         struct brcmnand_host *host;
2278
2279         list_for_each_entry(host, &ctrl->host_list, node)
2280                 brcmnand_save_restore_cs_config(host, 0);
2281
2282         ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT);
2283         ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR);
2284         ctrl->corr_stat_threshold =
2285                 brcmnand_read_reg(ctrl, BRCMNAND_CORR_THRESHOLD);
2286
2287         if (has_flash_dma(ctrl))
2288                 ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE);
2289
2290         return 0;
2291 }
2292
2293 static int brcmnand_resume(struct device *dev)
2294 {
2295         struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
2296         struct brcmnand_host *host;
2297
2298         if (has_flash_dma(ctrl)) {
2299                 flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode);
2300                 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2301         }
2302
2303         brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select);
2304         brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor);
2305         brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD,
2306                         ctrl->corr_stat_threshold);
2307         if (ctrl->soc) {
2308                 /* Clear/re-enable interrupt */
2309                 ctrl->soc->ctlrdy_ack(ctrl->soc);
2310                 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
2311         }
2312
2313         list_for_each_entry(host, &ctrl->host_list, node) {
2314                 struct nand_chip *chip = &host->chip;
2315                 struct mtd_info *mtd = nand_to_mtd(chip);
2316
2317                 brcmnand_save_restore_cs_config(host, 1);
2318
2319                 /* Reset the chip, required by some chips after power-up */
2320                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2321         }
2322
2323         return 0;
2324 }
2325
2326 const struct dev_pm_ops brcmnand_pm_ops = {
2327         .suspend                = brcmnand_suspend,
2328         .resume                 = brcmnand_resume,
2329 };
2330 EXPORT_SYMBOL_GPL(brcmnand_pm_ops);
2331
2332 static const struct of_device_id brcmnand_of_match[] = {
2333         { .compatible = "brcm,brcmnand-v4.0" },
2334         { .compatible = "brcm,brcmnand-v5.0" },
2335         { .compatible = "brcm,brcmnand-v6.0" },
2336         { .compatible = "brcm,brcmnand-v6.1" },
2337         { .compatible = "brcm,brcmnand-v6.2" },
2338         { .compatible = "brcm,brcmnand-v7.0" },
2339         { .compatible = "brcm,brcmnand-v7.1" },
2340         { .compatible = "brcm,brcmnand-v7.2" },
2341         {},
2342 };
2343 MODULE_DEVICE_TABLE(of, brcmnand_of_match);
2344
2345 /***********************************************************************
2346  * Platform driver setup (per controller)
2347  ***********************************************************************/
2348
2349 int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
2350 {
2351         struct device *dev = &pdev->dev;
2352         struct device_node *dn = dev->of_node, *child;
2353         struct brcmnand_controller *ctrl;
2354         struct resource *res;
2355         int ret;
2356
2357         /* We only support device-tree instantiation */
2358         if (!dn)
2359                 return -ENODEV;
2360
2361         if (!of_match_node(brcmnand_of_match, dn))
2362                 return -ENODEV;
2363
2364         ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
2365         if (!ctrl)
2366                 return -ENOMEM;
2367
2368         dev_set_drvdata(dev, ctrl);
2369         ctrl->dev = dev;
2370
2371         init_completion(&ctrl->done);
2372         init_completion(&ctrl->dma_done);
2373         nand_hw_control_init(&ctrl->controller);
2374         INIT_LIST_HEAD(&ctrl->host_list);
2375
2376         /* NAND register range */
2377         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2378         ctrl->nand_base = devm_ioremap_resource(dev, res);
2379         if (IS_ERR(ctrl->nand_base))
2380                 return PTR_ERR(ctrl->nand_base);
2381
2382         /* Enable clock before using NAND registers */
2383         ctrl->clk = devm_clk_get(dev, "nand");
2384         if (!IS_ERR(ctrl->clk)) {
2385                 ret = clk_prepare_enable(ctrl->clk);
2386                 if (ret)
2387                         return ret;
2388         } else {
2389                 ret = PTR_ERR(ctrl->clk);
2390                 if (ret == -EPROBE_DEFER)
2391                         return ret;
2392
2393                 ctrl->clk = NULL;
2394         }
2395
2396         /* Initialize NAND revision */
2397         ret = brcmnand_revision_init(ctrl);
2398         if (ret)
2399                 goto err;
2400
2401         /*
2402          * Most chips have this cache at a fixed offset within 'nand' block.
2403          * Some must specify this region separately.
2404          */
2405         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache");
2406         if (res) {
2407                 ctrl->nand_fc = devm_ioremap_resource(dev, res);
2408                 if (IS_ERR(ctrl->nand_fc)) {
2409                         ret = PTR_ERR(ctrl->nand_fc);
2410                         goto err;
2411                 }
2412         } else {
2413                 ctrl->nand_fc = ctrl->nand_base +
2414                                 ctrl->reg_offsets[BRCMNAND_FC_BASE];
2415         }
2416
2417         /* FLASH_DMA */
2418         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma");
2419         if (res) {
2420                 ctrl->flash_dma_base = devm_ioremap_resource(dev, res);
2421                 if (IS_ERR(ctrl->flash_dma_base)) {
2422                         ret = PTR_ERR(ctrl->flash_dma_base);
2423                         goto err;
2424                 }
2425
2426                 flash_dma_writel(ctrl, FLASH_DMA_MODE, 1); /* linked-list */
2427                 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2428
2429                 /* Allocate descriptor(s) */
2430                 ctrl->dma_desc = dmam_alloc_coherent(dev,
2431                                                      sizeof(*ctrl->dma_desc),
2432                                                      &ctrl->dma_pa, GFP_KERNEL);
2433                 if (!ctrl->dma_desc) {
2434                         ret = -ENOMEM;
2435                         goto err;
2436                 }
2437
2438                 ctrl->dma_irq = platform_get_irq(pdev, 1);
2439                 if ((int)ctrl->dma_irq < 0) {
2440                         dev_err(dev, "missing FLASH_DMA IRQ\n");
2441                         ret = -ENODEV;
2442                         goto err;
2443                 }
2444
2445                 ret = devm_request_irq(dev, ctrl->dma_irq,
2446                                 brcmnand_dma_irq, 0, DRV_NAME,
2447                                 ctrl);
2448                 if (ret < 0) {
2449                         dev_err(dev, "can't allocate IRQ %d: error %d\n",
2450                                         ctrl->dma_irq, ret);
2451                         goto err;
2452                 }
2453
2454                 dev_info(dev, "enabling FLASH_DMA\n");
2455         }
2456
2457         /* Disable automatic device ID config, direct addressing */
2458         brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT,
2459                          CS_SELECT_AUTO_DEVICE_ID_CFG | 0xff, 0, 0);
2460         /* Disable XOR addressing */
2461         brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0);
2462
2463         if (ctrl->features & BRCMNAND_HAS_WP) {
2464                 /* Permanently disable write protection */
2465                 if (wp_on == 2)
2466                         brcmnand_set_wp(ctrl, false);
2467         } else {
2468                 wp_on = 0;
2469         }
2470
2471         /* IRQ */
2472         ctrl->irq = platform_get_irq(pdev, 0);
2473         if ((int)ctrl->irq < 0) {
2474                 dev_err(dev, "no IRQ defined\n");
2475                 ret = -ENODEV;
2476                 goto err;
2477         }
2478
2479         /*
2480          * Some SoCs integrate this controller (e.g., its interrupt bits) in
2481          * interesting ways
2482          */
2483         if (soc) {
2484                 ctrl->soc = soc;
2485
2486                 ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
2487                                        DRV_NAME, ctrl);
2488
2489                 /* Enable interrupt */
2490                 ctrl->soc->ctlrdy_ack(ctrl->soc);
2491                 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
2492         } else {
2493                 /* Use standard interrupt infrastructure */
2494                 ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
2495                                        DRV_NAME, ctrl);
2496         }
2497         if (ret < 0) {
2498                 dev_err(dev, "can't allocate IRQ %d: error %d\n",
2499                         ctrl->irq, ret);
2500                 goto err;
2501         }
2502
2503         for_each_available_child_of_node(dn, child) {
2504                 if (of_device_is_compatible(child, "brcm,nandcs")) {
2505                         struct brcmnand_host *host;
2506
2507                         host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
2508                         if (!host) {
2509                                 of_node_put(child);
2510                                 ret = -ENOMEM;
2511                                 goto err;
2512                         }
2513                         host->pdev = pdev;
2514                         host->ctrl = ctrl;
2515
2516                         ret = brcmnand_init_cs(host, child);
2517                         if (ret) {
2518                                 devm_kfree(dev, host);
2519                                 continue; /* Try all chip-selects */
2520                         }
2521
2522                         list_add_tail(&host->node, &ctrl->host_list);
2523                 }
2524         }
2525
2526         /* No chip-selects could initialize properly */
2527         if (list_empty(&ctrl->host_list)) {
2528                 ret = -ENODEV;
2529                 goto err;
2530         }
2531
2532         return 0;
2533
2534 err:
2535         clk_disable_unprepare(ctrl->clk);
2536         return ret;
2537
2538 }
2539 EXPORT_SYMBOL_GPL(brcmnand_probe);
2540
2541 int brcmnand_remove(struct platform_device *pdev)
2542 {
2543         struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev);
2544         struct brcmnand_host *host;
2545
2546         list_for_each_entry(host, &ctrl->host_list, node)
2547                 nand_release(nand_to_mtd(&host->chip));
2548
2549         clk_disable_unprepare(ctrl->clk);
2550
2551         dev_set_drvdata(&pdev->dev, NULL);
2552
2553         return 0;
2554 }
2555 EXPORT_SYMBOL_GPL(brcmnand_remove);
2556
2557 MODULE_LICENSE("GPL v2");
2558 MODULE_AUTHOR("Kevin Cernekee");
2559 MODULE_AUTHOR("Brian Norris");
2560 MODULE_DESCRIPTION("NAND driver for Broadcom chips");
2561 MODULE_ALIAS("platform:brcmnand");