drivers/mtd/nand/jz4740_nand.c

   1 /*
   2  *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
   3  *  JZ4740 SoC NAND controller driver
   4  *
   5  *  This program is free software; you can redistribute it and/or modify it
   6  *  under  the terms of the GNU General  Public License as published by the
   7  *  Free Software Foundation;  either version 2 of the License, or (at your
   8  *  option) any later version.
   9  *
  10  *  You should have received a copy of the GNU General Public License along
  11  *  with this program; if not, write to the Free Software Foundation, Inc.,
  12  *  675 Mass Ave, Cambridge, MA 02139, USA.
  13  *
  14  */
  15
  16 #include <linux/ioport.h>
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/slab.h>
  21
  22 #include <linux/mtd/mtd.h>
  23 #include <linux/mtd/nand.h>
  24 #include <linux/mtd/partitions.h>
  25
  26 #include <linux/gpio.h>
  27
  28 #include <asm/mach-jz4740/gpio.h>
  29 #include <asm/mach-jz4740/jz4740_nand.h>
  30
  31 #define JZ_REG_NAND_CTRL        0x50
  32 #define JZ_REG_NAND_ECC_CTRL    0x100
  33 #define JZ_REG_NAND_DATA        0x104
  34 #define JZ_REG_NAND_PAR0        0x108
  35 #define JZ_REG_NAND_PAR1        0x10C
  36 #define JZ_REG_NAND_PAR2        0x110
  37 #define JZ_REG_NAND_IRQ_STAT    0x114
  38 #define JZ_REG_NAND_IRQ_CTRL    0x118
  39 #define JZ_REG_NAND_ERR(x)      (0x11C + ((x) << 2))
  40
  41 #define JZ_NAND_ECC_CTRL_PAR_READY      BIT(4)
  42 #define JZ_NAND_ECC_CTRL_ENCODING       BIT(3)
  43 #define JZ_NAND_ECC_CTRL_RS             BIT(2)
  44 #define JZ_NAND_ECC_CTRL_RESET          BIT(1)
  45 #define JZ_NAND_ECC_CTRL_ENABLE         BIT(0)
  46
  47 #define JZ_NAND_STATUS_ERR_COUNT        (BIT(31) | BIT(30) | BIT(29))
  48 #define JZ_NAND_STATUS_PAD_FINISH       BIT(4)
  49 #define JZ_NAND_STATUS_DEC_FINISH       BIT(3)
  50 #define JZ_NAND_STATUS_ENC_FINISH       BIT(2)
  51 #define JZ_NAND_STATUS_UNCOR_ERROR      BIT(1)
  52 #define JZ_NAND_STATUS_ERROR            BIT(0)
  53
  54 #define JZ_NAND_CTRL_ENABLE_CHIP(x) BIT((x) << 1)
  55 #define JZ_NAND_CTRL_ASSERT_CHIP(x) BIT(((x) << 1) + 1)
  56 #define JZ_NAND_CTRL_ASSERT_CHIP_MASK 0xaa
  57
  58 #define JZ_NAND_MEM_CMD_OFFSET 0x08000
  59 #define JZ_NAND_MEM_ADDR_OFFSET 0x10000
  60
  61 struct jz_nand {
  62         struct mtd_info mtd;
  63         struct nand_chip chip;
  64         void __iomem *base;
  65         struct resource *mem;
  66
  67         unsigned char banks[JZ_NAND_NUM_BANKS];
  68         void __iomem *bank_base[JZ_NAND_NUM_BANKS];
  69         struct resource *bank_mem[JZ_NAND_NUM_BANKS];
  70
  71         int selected_bank;
  72
  73         struct gpio_desc *busy_gpio;
  74         bool is_reading;
  75 };
  76
  77 static inline struct jz_nand *mtd_to_jz_nand(struct mtd_info *mtd)
  78 {
  79         return container_of(mtd, struct jz_nand, mtd);
  80 }
  81
  82 static void jz_nand_select_chip(struct mtd_info *mtd, int chipnr)
  83 {
  84         struct jz_nand *nand = mtd_to_jz_nand(mtd);
  85         struct nand_chip *chip = mtd->priv;
  86         uint32_t ctrl;
  87         int banknr;
  88
  89         ctrl = readl(nand->base + JZ_REG_NAND_CTRL);
  90         ctrl &= ~JZ_NAND_CTRL_ASSERT_CHIP_MASK;
  91
  92         if (chipnr == -1) {
  93                 banknr = -1;
  94         } else {
  95                 banknr = nand->banks[chipnr] - 1;
  96                 chip->IO_ADDR_R = nand->bank_base[banknr];
  97                 chip->IO_ADDR_W = nand->bank_base[banknr];
  98         }
  99         writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
 100
 101         nand->selected_bank = banknr;
 102 }
 103
 104 static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
 105 {
 106         struct jz_nand *nand = mtd_to_jz_nand(mtd);
 107         struct nand_chip *chip = mtd->priv;
 108         uint32_t reg;
 109         void __iomem *bank_base = nand->bank_base[nand->selected_bank];
 110
 111         BUG_ON(nand->selected_bank < 0);
 112
 113         if (ctrl & NAND_CTRL_CHANGE) {
 114                 BUG_ON((ctrl & NAND_ALE) && (ctrl & NAND_CLE));
 115                 if (ctrl & NAND_ALE)
 116                         bank_base += JZ_NAND_MEM_ADDR_OFFSET;
 117                 else if (ctrl & NAND_CLE)
 118                         bank_base += JZ_NAND_MEM_CMD_OFFSET;
 119                 chip->IO_ADDR_W = bank_base;
 120
 121                 reg = readl(nand->base + JZ_REG_NAND_CTRL);
 122                 if (ctrl & NAND_NCE)
 123                         reg |= JZ_NAND_CTRL_ASSERT_CHIP(nand->selected_bank);
 124                 else
 125                         reg &= ~JZ_NAND_CTRL_ASSERT_CHIP(nand->selected_bank);
 126                 writel(reg, nand->base + JZ_REG_NAND_CTRL);
 127         }
 128         if (dat != NAND_CMD_NONE)
 129                 writeb(dat, chip->IO_ADDR_W);
 130 }
 131
 132 static int jz_nand_dev_ready(struct mtd_info *mtd)
 133 {
 134         struct jz_nand *nand = mtd_to_jz_nand(mtd);
 135         return gpiod_get_value_cansleep(nand->busy_gpio);
 136 }
 137
 138 static void jz_nand_hwctl(struct mtd_info *mtd, int mode)
 139 {
 140         struct jz_nand *nand = mtd_to_jz_nand(mtd);
 141         uint32_t reg;
 142
 143         writel(0, nand->base + JZ_REG_NAND_IRQ_STAT);
 144         reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
 145
 146         reg |= JZ_NAND_ECC_CTRL_RESET;
 147         reg |= JZ_NAND_ECC_CTRL_ENABLE;
 148         reg |= JZ_NAND_ECC_CTRL_RS;
 149
 150         switch (mode) {
 151         case NAND_ECC_READ:
 152                 reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
 153                 nand->is_reading = true;
 154                 break;
 155         case NAND_ECC_WRITE:
 156                 reg |= JZ_NAND_ECC_CTRL_ENCODING;
 157                 nand->is_reading = false;
 158                 break;
 159         default:
 160                 break;
 161         }
 162
 163         writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
 164 }
 165
 166 static int jz_nand_calculate_ecc_rs(struct mtd_info *mtd, const uint8_t *dat,
 167         uint8_t *ecc_code)
 168 {
 169         struct jz_nand *nand = mtd_to_jz_nand(mtd);
 170         uint32_t reg, status;
 171         int i;
 172         unsigned int timeout = 1000;
 173         static uint8_t empty_block_ecc[] = {0xcd, 0x9d, 0x90, 0x58, 0xf4,
 174                                                 0x8b, 0xff, 0xb7, 0x6f};
 175
 176         if (nand->is_reading)
 177                 return 0;
 178
 179         do {
 180                 status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
 181         } while (!(status & JZ_NAND_STATUS_ENC_FINISH) && --timeout);
 182
 183         if (timeout == 0)
 184             return -1;
 185
 186         reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
 187         reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
 188         writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
 189
 190         for (i = 0; i < 9; ++i)
 191                 ecc_code[i] = readb(nand->base + JZ_REG_NAND_PAR0 + i);
 192
 193         /* If the written data is completly 0xff, we also want to write 0xff as
 194          * ecc, otherwise we will get in trouble when doing subpage writes. */
 195         if (memcmp(ecc_code, empty_block_ecc, 9) == 0)
 196                 memset(ecc_code, 0xff, 9);
 197
 198         return 0;
 199 }
 200
 201 static void jz_nand_correct_data(uint8_t *dat, int index, int mask)
 202 {
 203         int offset = index & 0x7;
 204         uint16_t data;
 205
 206         index += (index >> 3);
 207
 208         data = dat[index];
 209         data |= dat[index+1] << 8;
 210
 211         mask ^= (data >> offset) & 0x1ff;
 212         data &= ~(0x1ff << offset);
 213         data |= (mask << offset);
 214
 215         dat[index] = data & 0xff;
 216         dat[index+1] = (data >> 8) & 0xff;
 217 }
 218
 219 static int jz_nand_correct_ecc_rs(struct mtd_info *mtd, uint8_t *dat,
 220         uint8_t *read_ecc, uint8_t *calc_ecc)
 221 {
 222         struct jz_nand *nand = mtd_to_jz_nand(mtd);
 223         int i, error_count, index;
 224         uint32_t reg, status, error;
 225         uint32_t t;
 226         unsigned int timeout = 1000;
 227
 228         t = read_ecc[0];
 229
 230         if (t == 0xff) {
 231                 for (i = 1; i < 9; ++i)
 232                         t &= read_ecc[i];
 233
 234                 t &= dat[0];
 235                 t &= dat[nand->chip.ecc.size / 2];
 236                 t &= dat[nand->chip.ecc.size - 1];
 237
 238                 if (t == 0xff) {
 239                         for (i = 1; i < nand->chip.ecc.size - 1; ++i)
 240                                 t &= dat[i];
 241                         if (t == 0xff)
 242                                 return 0;
 243                 }
 244         }
 245
 246         for (i = 0; i < 9; ++i)
 247                 writeb(read_ecc[i], nand->base + JZ_REG_NAND_PAR0 + i);
 248
 249         reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
 250         reg |= JZ_NAND_ECC_CTRL_PAR_READY;
 251         writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
 252
 253         do {
 254                 status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
 255         } while (!(status & JZ_NAND_STATUS_DEC_FINISH) && --timeout);
 256
 257         if (timeout == 0)
 258             return -1;
 259
 260         reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
 261         reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
 262         writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
 263
 264         if (status & JZ_NAND_STATUS_ERROR) {
 265                 if (status & JZ_NAND_STATUS_UNCOR_ERROR)
 266                         return -1;
 267
 268                 error_count = (status & JZ_NAND_STATUS_ERR_COUNT) >> 29;
 269
 270                 for (i = 0; i < error_count; ++i) {
 271                         error = readl(nand->base + JZ_REG_NAND_ERR(i));
 272                         index = ((error >> 16) & 0x1ff) - 1;
 273                         if (index >= 0 && index < 512)
 274                                 jz_nand_correct_data(dat, index, error & 0x1ff);
 275                 }
 276
 277                 return error_count;
 278         }
 279
 280         return 0;
 281 }
 282
 283 static int jz_nand_ioremap_resource(struct platform_device *pdev,
 284         const char *name, struct resource **res, void *__iomem *base)
 285 {
 286         int ret;
 287
 288         *res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
 289         if (!*res) {
 290                 dev_err(&pdev->dev, "Failed to get platform %s memory\n", name);
 291                 ret = -ENXIO;
 292                 goto err;
 293         }
 294
 295         *res = request_mem_region((*res)->start, resource_size(*res),
 296                                 pdev->name);
 297         if (!*res) {
 298                 dev_err(&pdev->dev, "Failed to request %s memory region\n", name);
 299                 ret = -EBUSY;
 300                 goto err;
 301         }
 302
 303         *base = ioremap((*res)->start, resource_size(*res));
 304         if (!*base) {
 305                 dev_err(&pdev->dev, "Failed to ioremap %s memory region\n", name);
 306                 ret = -EBUSY;
 307                 goto err_release_mem;
 308         }
 309
 310         return 0;
 311
 312 err_release_mem:
 313         release_mem_region((*res)->start, resource_size(*res));
 314 err:
 315         *res = NULL;
 316         *base = NULL;
 317         return ret;
 318 }
 319
 320 static inline void jz_nand_iounmap_resource(struct resource *res,
 321                                             void __iomem *base)
 322 {
 323         iounmap(base);
 324         release_mem_region(res->start, resource_size(res));
 325 }
 326
 327 static int jz_nand_detect_bank(struct platform_device *pdev,
 328                                struct jz_nand *nand, unsigned char bank,
 329                                size_t chipnr, uint8_t *nand_maf_id,
 330                                uint8_t *nand_dev_id)
 331 {
 332         int ret;
 333         int gpio;
 334         char gpio_name[9];
 335         char res_name[6];
 336         uint32_t ctrl;
 337         struct mtd_info *mtd = &nand->mtd;
 338         struct nand_chip *chip = &nand->chip;
 339
 340         /* Request GPIO port. */
 341         gpio = JZ_GPIO_MEM_CS0 + bank - 1;
 342         sprintf(gpio_name, "NAND CS%d", bank);
 343         ret = gpio_request(gpio, gpio_name);
 344         if (ret) {
 345                 dev_warn(&pdev->dev,
 346                         "Failed to request %s gpio %d: %d\n",
 347                         gpio_name, gpio, ret);
 348                 goto notfound_gpio;
 349         }
 350
 351         /* Request I/O resource. */
 352         sprintf(res_name, "bank%d", bank);
 353         ret = jz_nand_ioremap_resource(pdev, res_name,
 354                                         &nand->bank_mem[bank - 1],
 355                                         &nand->bank_base[bank - 1]);
 356         if (ret)
 357                 goto notfound_resource;
 358
 359         /* Enable chip in bank. */
 360         jz_gpio_set_function(gpio, JZ_GPIO_FUNC_MEM_CS0);
 361         ctrl = readl(nand->base + JZ_REG_NAND_CTRL);
 362         ctrl |= JZ_NAND_CTRL_ENABLE_CHIP(bank - 1);
 363         writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
 364
 365         if (chipnr == 0) {
 366                 /* Detect first chip. */
 367                 ret = nand_scan_ident(mtd, 1, NULL);
 368                 if (ret)
 369                         goto notfound_id;
 370
 371                 /* Retrieve the IDs from the first chip. */
 372                 chip->select_chip(mtd, 0);
 373                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
 374                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
 375                 *nand_maf_id = chip->read_byte(mtd);
 376                 *nand_dev_id = chip->read_byte(mtd);
 377         } else {
 378                 /* Detect additional chip. */
 379                 chip->select_chip(mtd, chipnr);
 380                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
 381                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
 382                 if (*nand_maf_id != chip->read_byte(mtd)
 383                  || *nand_dev_id != chip->read_byte(mtd)) {
 384                         ret = -ENODEV;
 385                         goto notfound_id;
 386                 }
 387
 388                 /* Update size of the MTD. */
 389                 chip->numchips++;
 390                 mtd->size += chip->chipsize;
 391         }
 392
 393         dev_info(&pdev->dev, "Found chip %i on bank %i\n", chipnr, bank);
 394         return 0;
 395
 396 notfound_id:
 397         dev_info(&pdev->dev, "No chip found on bank %i\n", bank);
 398         ctrl &= ~(JZ_NAND_CTRL_ENABLE_CHIP(bank - 1));
 399         writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
 400         jz_gpio_set_function(gpio, JZ_GPIO_FUNC_NONE);
 401         jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
 402                                  nand->bank_base[bank - 1]);
 403 notfound_resource:
 404         gpio_free(gpio);
 405 notfound_gpio:
 406         return ret;
 407 }
 408
 409 static int jz_nand_probe(struct platform_device *pdev)
 410 {
 411         int ret;
 412         struct jz_nand *nand;
 413         struct nand_chip *chip;
 414         struct mtd_info *mtd;
 415         struct jz_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
 416         size_t chipnr, bank_idx;
 417         uint8_t nand_maf_id = 0, nand_dev_id = 0;
 418
 419         nand = kzalloc(sizeof(*nand), GFP_KERNEL);
 420         if (!nand)
 421                 return -ENOMEM;
 422
 423         ret = jz_nand_ioremap_resource(pdev, "mmio", &nand->mem, &nand->base);
 424         if (ret)
 425                 goto err_free;
 426
 427         nand->busy_gpio = devm_gpiod_get_optional(&pdev->dev, "busy", GPIOD_IN);
 428         if (IS_ERR(nand->busy_gpio)) {
 429                 ret = PTR_ERR(nand->busy_gpio);
 430                 dev_err(&pdev->dev, "Failed to request busy gpio %d\n",
 431                     ret);
 432                 goto err_iounmap_mmio;
 433         }
 434
 435         mtd             = &nand->mtd;
 436         chip            = &nand->chip;
 437         mtd->priv       = chip;
 438         mtd->dev.parent = &pdev->dev;
 439         mtd->name       = "jz4740-nand";
 440
 441         chip->ecc.hwctl         = jz_nand_hwctl;
 442         chip->ecc.calculate     = jz_nand_calculate_ecc_rs;
 443         chip->ecc.correct       = jz_nand_correct_ecc_rs;
 444         chip->ecc.mode          = NAND_ECC_HW_OOB_FIRST;
 445         chip->ecc.size          = 512;
 446         chip->ecc.bytes         = 9;
 447         chip->ecc.strength      = 4;
 448
 449         if (pdata)
 450                 chip->ecc.layout = pdata->ecc_layout;
 451
 452         chip->chip_delay = 50;
 453         chip->cmd_ctrl = jz_nand_cmd_ctrl;
 454         chip->select_chip = jz_nand_select_chip;
 455
 456         if (nand->busy_gpio)
 457                 chip->dev_ready = jz_nand_dev_ready;
 458
 459         platform_set_drvdata(pdev, nand);
 460
 461         /* We are going to autodetect NAND chips in the banks specified in the
 462          * platform data. Although nand_scan_ident() can detect multiple chips,
 463          * it requires those chips to be numbered consecuitively, which is not
 464          * always the case for external memory banks. And a fixed chip-to-bank
 465          * mapping is not practical either, since for example Dingoo units
 466          * produced at different times have NAND chips in different banks.
 467          */
 468         chipnr = 0;
 469         for (bank_idx = 0; bank_idx < JZ_NAND_NUM_BANKS; bank_idx++) {
 470                 unsigned char bank;
 471
 472                 /* If there is no platform data, look for NAND in bank 1,
 473                  * which is the most likely bank since it is the only one
 474                  * that can be booted from.
 475                  */
 476                 bank = pdata ? pdata->banks[bank_idx] : bank_idx ^ 1;
 477                 if (bank == 0)
 478                         break;
 479                 if (bank > JZ_NAND_NUM_BANKS) {
 480                         dev_warn(&pdev->dev,
 481                                 "Skipping non-existing bank: %d\n", bank);
 482                         continue;
 483                 }
 484                 /* The detection routine will directly or indirectly call
 485                  * jz_nand_select_chip(), so nand->banks has to contain the
 486                  * bank we're checking.
 487                  */
 488                 nand->banks[chipnr] = bank;
 489                 if (jz_nand_detect_bank(pdev, nand, bank, chipnr,
 490                                         &nand_maf_id, &nand_dev_id) == 0)
 491                         chipnr++;
 492                 else
 493                         nand->banks[chipnr] = 0;
 494         }
 495         if (chipnr == 0) {
 496                 dev_err(&pdev->dev, "No NAND chips found\n");
 497                 goto err_iounmap_mmio;
 498         }
 499
 500         if (pdata && pdata->ident_callback) {
 501                 pdata->ident_callback(pdev, chip, &pdata->partitions,
 502                                         &pdata->num_partitions);
 503         }
 504
 505         ret = nand_scan_tail(mtd);
 506         if (ret) {
 507                 dev_err(&pdev->dev,  "Failed to scan NAND\n");
 508                 goto err_unclaim_banks;
 509         }
 510
 511         ret = mtd_device_parse_register(mtd, NULL, NULL,
 512                                         pdata ? pdata->partitions : NULL,
 513                                         pdata ? pdata->num_partitions : 0);
 514
 515         if (ret) {
 516                 dev_err(&pdev->dev, "Failed to add mtd device\n");
 517                 goto err_nand_release;
 518         }
 519
 520         dev_info(&pdev->dev, "Successfully registered JZ4740 NAND driver\n");
 521
 522         return 0;
 523
 524 err_nand_release:
 525         nand_release(mtd);
 526 err_unclaim_banks:
 527         while (chipnr--) {
 528                 unsigned char bank = nand->banks[chipnr];
 529                 gpio_free(JZ_GPIO_MEM_CS0 + bank - 1);
 530                 jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
 531                                          nand->bank_base[bank - 1]);
 532         }
 533         writel(0, nand->base + JZ_REG_NAND_CTRL);
 534 err_iounmap_mmio:
 535         jz_nand_iounmap_resource(nand->mem, nand->base);
 536 err_free:
 537         kfree(nand);
 538         return ret;
 539 }
 540
 541 static int jz_nand_remove(struct platform_device *pdev)
 542 {
 543         struct jz_nand *nand = platform_get_drvdata(pdev);
 544         size_t i;
 545
 546         nand_release(&nand->mtd);
 547
 548         /* Deassert and disable all chips */
 549         writel(0, nand->base + JZ_REG_NAND_CTRL);
 550
 551         for (i = 0; i < JZ_NAND_NUM_BANKS; ++i) {
 552                 unsigned char bank = nand->banks[i];
 553                 if (bank != 0) {
 554                         jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
 555                                                  nand->bank_base[bank - 1]);
 556                         gpio_free(JZ_GPIO_MEM_CS0 + bank - 1);
 557                 }
 558         }
 559
 560         jz_nand_iounmap_resource(nand->mem, nand->base);
 561
 562         kfree(nand);
 563
 564         return 0;
 565 }
 566
 567 static struct platform_driver jz_nand_driver = {
 568         .probe = jz_nand_probe,
 569         .remove = jz_nand_remove,
 570         .driver = {
 571                 .name = "jz4740-nand",
 572         },
 573 };
 574
 575 module_platform_driver(jz_nand_driver);
 576
 577 MODULE_LICENSE("GPL");
 578 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
 579 MODULE_DESCRIPTION("NAND controller driver for JZ4740 SoC");
 580 MODULE_ALIAS("platform:jz4740-nand");