drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *
   8  *      Additional technical information is available on
   9  *      http://www.linux-mtd.infradead.org/doc/nand.html
  10  *
  11  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  12  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  13  *
  14  *  Credits:
  15  *      David Woodhouse for adding multichip support
  16  *
  17  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  18  *      rework for 2K page size chips
  19  *
  20  *  TODO:
  21  *      Enable cached programming for 2k page size chips
  22  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  23  *      if we have HW ECC support.
  24  *      BBT table is not serialized, has to be fixed
  25  *
  26  * This program is free software; you can redistribute it and/or modify
  27  * it under the terms of the GNU General Public License version 2 as
  28  * published by the Free Software Foundation.
  29  *
  30  */
  31
  32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  33
  34 #include <linux/module.h>
  35 #include <linux/delay.h>
  36 #include <linux/errno.h>
  37 #include <linux/err.h>
  38 #include <linux/sched.h>
  39 #include <linux/slab.h>
  40 #include <linux/types.h>
  41 #include <linux/mtd/mtd.h>
  42 #include <linux/mtd/nand.h>
  43 #include <linux/mtd/nand_ecc.h>
  44 #include <linux/mtd/nand_bch.h>
  45 #include <linux/interrupt.h>
  46 #include <linux/bitops.h>
  47 #include <linux/leds.h>
  48 #include <linux/io.h>
  49 #include <linux/mtd/partitions.h>
  50
  51 /* Define default oob placement schemes for large and small page devices */
  52 static struct nand_ecclayout nand_oob_8 = {
  53         .eccbytes = 3,
  54         .eccpos = {0, 1, 2},
  55         .oobfree = {
  56                 {.offset = 3,
  57                  .length = 2},
  58                 {.offset = 6,
  59                  .length = 2} }
  60 };
  61
  62 static struct nand_ecclayout nand_oob_16 = {
  63         .eccbytes = 6,
  64         .eccpos = {0, 1, 2, 3, 6, 7},
  65         .oobfree = {
  66                 {.offset = 8,
  67                  . length = 8} }
  68 };
  69
  70 static struct nand_ecclayout nand_oob_64 = {
  71         .eccbytes = 24,
  72         .eccpos = {
  73                    40, 41, 42, 43, 44, 45, 46, 47,
  74                    48, 49, 50, 51, 52, 53, 54, 55,
  75                    56, 57, 58, 59, 60, 61, 62, 63},
  76         .oobfree = {
  77                 {.offset = 2,
  78                  .length = 38} }
  79 };
  80
  81 static struct nand_ecclayout nand_oob_128 = {
  82         .eccbytes = 48,
  83         .eccpos = {
  84                    80, 81, 82, 83, 84, 85, 86, 87,
  85                    88, 89, 90, 91, 92, 93, 94, 95,
  86                    96, 97, 98, 99, 100, 101, 102, 103,
  87                    104, 105, 106, 107, 108, 109, 110, 111,
  88                    112, 113, 114, 115, 116, 117, 118, 119,
  89                    120, 121, 122, 123, 124, 125, 126, 127},
  90         .oobfree = {
  91                 {.offset = 2,
  92                  .length = 78} }
  93 };
  94
  95 static int nand_get_device(struct mtd_info *mtd, int new_state);
  96
  97 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
  98                              struct mtd_oob_ops *ops);
  99
 100 /*
 101  * For devices which display every fart in the system on a separate LED. Is
 102  * compiled away when LED support is disabled.
 103  */
 104 DEFINE_LED_TRIGGER(nand_led_trigger);
 105
 106 static int check_offs_len(struct mtd_info *mtd,
 107                                         loff_t ofs, uint64_t len)
 108 {
 109         struct nand_chip *chip = mtd->priv;
 110         int ret = 0;
 111
 112         /* Start address must align on block boundary */
 113         if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
 114                 pr_debug("%s: unaligned address\n", __func__);
 115                 ret = -EINVAL;
 116         }
 117
 118         /* Length must align on block boundary */
 119         if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
 120                 pr_debug("%s: length not block aligned\n", __func__);
 121                 ret = -EINVAL;
 122         }
 123
 124         return ret;
 125 }
 126
 127 /**
 128  * nand_release_device - [GENERIC] release chip
 129  * @mtd: MTD device structure
 130  *
 131  * Release chip lock and wake up anyone waiting on the device.
 132  */
 133 static void nand_release_device(struct mtd_info *mtd)
 134 {
 135         struct nand_chip *chip = mtd->priv;
 136
 137         /* Release the controller and the chip */
 138         spin_lock(&chip->controller->lock);
 139         chip->controller->active = NULL;
 140         chip->state = FL_READY;
 141         wake_up(&chip->controller->wq);
 142         spin_unlock(&chip->controller->lock);
 143 }
 144
 145 /**
 146  * nand_read_byte - [DEFAULT] read one byte from the chip
 147  * @mtd: MTD device structure
 148  *
 149  * Default read function for 8bit buswidth
 150  */
 151 static uint8_t nand_read_byte(struct mtd_info *mtd)
 152 {
 153         struct nand_chip *chip = mtd->priv;
 154         return readb(chip->IO_ADDR_R);
 155 }
 156
 157 /**
 158  * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
 159  * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
 160  * @mtd: MTD device structure
 161  *
 162  * Default read function for 16bit buswidth with endianness conversion.
 163  *
 164  */
 165 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 166 {
 167         struct nand_chip *chip = mtd->priv;
 168         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 169 }
 170
 171 /**
 172  * nand_read_word - [DEFAULT] read one word from the chip
 173  * @mtd: MTD device structure
 174  *
 175  * Default read function for 16bit buswidth without endianness conversion.
 176  */
 177 static u16 nand_read_word(struct mtd_info *mtd)
 178 {
 179         struct nand_chip *chip = mtd->priv;
 180         return readw(chip->IO_ADDR_R);
 181 }
 182
 183 /**
 184  * nand_select_chip - [DEFAULT] control CE line
 185  * @mtd: MTD device structure
 186  * @chipnr: chipnumber to select, -1 for deselect
 187  *
 188  * Default select function for 1 chip devices.
 189  */
 190 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 191 {
 192         struct nand_chip *chip = mtd->priv;
 193
 194         switch (chipnr) {
 195         case -1:
 196                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 197                 break;
 198         case 0:
 199                 break;
 200
 201         default:
 202                 BUG();
 203         }
 204 }
 205
 206 /**
 207  * nand_write_byte - [DEFAULT] write single byte to chip
 208  * @mtd: MTD device structure
 209  * @byte: value to write
 210  *
 211  * Default function to write a byte to I/O[7:0]
 212  */
 213 static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
 214 {
 215         struct nand_chip *chip = mtd->priv;
 216
 217         chip->write_buf(mtd, &byte, 1);
 218 }
 219
 220 /**
 221  * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
 222  * @mtd: MTD device structure
 223  * @byte: value to write
 224  *
 225  * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
 226  */
 227 static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
 228 {
 229         struct nand_chip *chip = mtd->priv;
 230         uint16_t word = byte;
 231
 232         /*
 233          * It's not entirely clear what should happen to I/O[15:8] when writing
 234          * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
 235          *
 236          *    When the host supports a 16-bit bus width, only data is
 237          *    transferred at the 16-bit width. All address and command line
 238          *    transfers shall use only the lower 8-bits of the data bus. During
 239          *    command transfers, the host may place any value on the upper
 240          *    8-bits of the data bus. During address transfers, the host shall
 241          *    set the upper 8-bits of the data bus to 00h.
 242          *
 243          * One user of the write_byte callback is nand_onfi_set_features. The
 244          * four parameters are specified to be written to I/O[7:0], but this is
 245          * neither an address nor a command transfer. Let's assume a 0 on the
 246          * upper I/O lines is OK.
 247          */
 248         chip->write_buf(mtd, (uint8_t *)&word, 2);
 249 }
 250
 251 /**
 252  * nand_write_buf - [DEFAULT] write buffer to chip
 253  * @mtd: MTD device structure
 254  * @buf: data buffer
 255  * @len: number of bytes to write
 256  *
 257  * Default write function for 8bit buswidth.
 258  */
 259 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 260 {
 261         struct nand_chip *chip = mtd->priv;
 262
 263         iowrite8_rep(chip->IO_ADDR_W, buf, len);
 264 }
 265
 266 /**
 267  * nand_read_buf - [DEFAULT] read chip data into buffer
 268  * @mtd: MTD device structure
 269  * @buf: buffer to store date
 270  * @len: number of bytes to read
 271  *
 272  * Default read function for 8bit buswidth.
 273  */
 274 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 275 {
 276         struct nand_chip *chip = mtd->priv;
 277
 278         ioread8_rep(chip->IO_ADDR_R, buf, len);
 279 }
 280
 281 /**
 282  * nand_write_buf16 - [DEFAULT] write buffer to chip
 283  * @mtd: MTD device structure
 284  * @buf: data buffer
 285  * @len: number of bytes to write
 286  *
 287  * Default write function for 16bit buswidth.
 288  */
 289 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 290 {
 291         struct nand_chip *chip = mtd->priv;
 292         u16 *p = (u16 *) buf;
 293
 294         iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
 295 }
 296
 297 /**
 298  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 299  * @mtd: MTD device structure
 300  * @buf: buffer to store date
 301  * @len: number of bytes to read
 302  *
 303  * Default read function for 16bit buswidth.
 304  */
 305 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 306 {
 307         struct nand_chip *chip = mtd->priv;
 308         u16 *p = (u16 *) buf;
 309
 310         ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
 311 }
 312
 313 /**
 314  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 315  * @mtd: MTD device structure
 316  * @ofs: offset from device start
 317  * @getchip: 0, if the chip is already selected
 318  *
 319  * Check, if the block is bad.
 320  */
 321 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 322 {
 323         int page, chipnr, res = 0, i = 0;
 324         struct nand_chip *chip = mtd->priv;
 325         u16 bad;
 326
 327         if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 328                 ofs += mtd->erasesize - mtd->writesize;
 329
 330         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 331
 332         if (getchip) {
 333                 chipnr = (int)(ofs >> chip->chip_shift);
 334
 335                 nand_get_device(mtd, FL_READING);
 336
 337                 /* Select the NAND device */
 338                 chip->select_chip(mtd, chipnr);
 339         }
 340
 341         do {
 342                 if (chip->options & NAND_BUSWIDTH_16) {
 343                         chip->cmdfunc(mtd, NAND_CMD_READOOB,
 344                                         chip->badblockpos & 0xFE, page);
 345                         bad = cpu_to_le16(chip->read_word(mtd));
 346                         if (chip->badblockpos & 0x1)
 347                                 bad >>= 8;
 348                         else
 349                                 bad &= 0xFF;
 350                 } else {
 351                         chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
 352                                         page);
 353                         bad = chip->read_byte(mtd);
 354                 }
 355
 356                 if (likely(chip->badblockbits == 8))
 357                         res = bad != 0xFF;
 358                 else
 359                         res = hweight8(bad) < chip->badblockbits;
 360                 ofs += mtd->writesize;
 361                 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 362                 i++;
 363         } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
 364
 365         if (getchip) {
 366                 chip->select_chip(mtd, -1);
 367                 nand_release_device(mtd);
 368         }
 369
 370         return res;
 371 }
 372
 373 /**
 374  * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
 375  * @mtd: MTD device structure
 376  * @ofs: offset from device start
 377  *
 378  * This is the default implementation, which can be overridden by a hardware
 379  * specific driver. It provides the details for writing a bad block marker to a
 380  * block.
 381  */
 382 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 383 {
 384         struct nand_chip *chip = mtd->priv;
 385         struct mtd_oob_ops ops;
 386         uint8_t buf[2] = { 0, 0 };
 387         int ret = 0, res, i = 0;
 388
 389         ops.datbuf = NULL;
 390         ops.oobbuf = buf;
 391         ops.ooboffs = chip->badblockpos;
 392         if (chip->options & NAND_BUSWIDTH_16) {
 393                 ops.ooboffs &= ~0x01;
 394                 ops.len = ops.ooblen = 2;
 395         } else {
 396                 ops.len = ops.ooblen = 1;
 397         }
 398         ops.mode = MTD_OPS_PLACE_OOB;
 399
 400         /* Write to first/last page(s) if necessary */
 401         if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 402                 ofs += mtd->erasesize - mtd->writesize;
 403         do {
 404                 res = nand_do_write_oob(mtd, ofs, &ops);
 405                 if (!ret)
 406                         ret = res;
 407
 408                 i++;
 409                 ofs += mtd->writesize;
 410         } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
 411
 412         return ret;
 413 }
 414
 415 /**
 416  * nand_block_markbad_lowlevel - mark a block bad
 417  * @mtd: MTD device structure
 418  * @ofs: offset from device start
 419  *
 420  * This function performs the generic NAND bad block marking steps (i.e., bad
 421  * block table(s) and/or marker(s)). We only allow the hardware driver to
 422  * specify how to write bad block markers to OOB (chip->block_markbad).
 423  *
 424  * We try operations in the following order:
 425  *  (1) erase the affected block, to allow OOB marker to be written cleanly
 426  *  (2) write bad block marker to OOB area of affected block (unless flag
 427  *      NAND_BBT_NO_OOB_BBM is present)
 428  *  (3) update the BBT
 429  * Note that we retain the first error encountered in (2) or (3), finish the
 430  * procedures, and dump the error in the end.
 431 */
 432 static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
 433 {
 434         struct nand_chip *chip = mtd->priv;
 435         int res, ret = 0;
 436
 437         if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
 438                 struct erase_info einfo;
 439
 440                 /* Attempt erase before marking OOB */
 441                 memset(&einfo, 0, sizeof(einfo));
 442                 einfo.mtd = mtd;
 443                 einfo.addr = ofs;
 444                 einfo.len = 1ULL << chip->phys_erase_shift;
 445                 nand_erase_nand(mtd, &einfo, 0);
 446
 447                 /* Write bad block marker to OOB */
 448                 nand_get_device(mtd, FL_WRITING);
 449                 ret = chip->block_markbad(mtd, ofs);
 450                 nand_release_device(mtd);
 451         }
 452
 453         /* Mark block bad in BBT */
 454         if (chip->bbt) {
 455                 res = nand_markbad_bbt(mtd, ofs);
 456                 if (!ret)
 457                         ret = res;
 458         }
 459
 460         if (!ret)
 461                 mtd->ecc_stats.badblocks++;
 462
 463         return ret;
 464 }
 465
 466 /**
 467  * nand_check_wp - [GENERIC] check if the chip is write protected
 468  * @mtd: MTD device structure
 469  *
 470  * Check, if the device is write protected. The function expects, that the
 471  * device is already selected.
 472  */
 473 static int nand_check_wp(struct mtd_info *mtd)
 474 {
 475         struct nand_chip *chip = mtd->priv;
 476
 477         /* Broken xD cards report WP despite being writable */
 478         if (chip->options & NAND_BROKEN_XD)
 479                 return 0;
 480
 481         /* Check the WP bit */
 482         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 483         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 484 }
 485
 486 /**
 487  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 488  * @mtd: MTD device structure
 489  * @ofs: offset from device start
 490  * @getchip: 0, if the chip is already selected
 491  * @allowbbt: 1, if its allowed to access the bbt area
 492  *
 493  * Check, if the block is bad. Either by reading the bad block table or
 494  * calling of the scan function.
 495  */
 496 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 497                                int allowbbt)
 498 {
 499         struct nand_chip *chip = mtd->priv;
 500
 501         if (!chip->bbt)
 502                 return chip->block_bad(mtd, ofs, getchip);
 503
 504         /* Return info from the table */
 505         return nand_isbad_bbt(mtd, ofs, allowbbt);
 506 }
 507
 508 /**
 509  * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
 510  * @mtd: MTD device structure
 511  * @timeo: Timeout
 512  *
 513  * Helper function for nand_wait_ready used when needing to wait in interrupt
 514  * context.
 515  */
 516 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
 517 {
 518         struct nand_chip *chip = mtd->priv;
 519         int i;
 520
 521         /* Wait for the device to get ready */
 522         for (i = 0; i < timeo; i++) {
 523                 if (chip->dev_ready(mtd))
 524                         break;
 525                 touch_softlockup_watchdog();
 526                 mdelay(1);
 527         }
 528 }
 529
 530 /* Wait for the ready pin, after a command. The timeout is caught later. */
 531 void nand_wait_ready(struct mtd_info *mtd)
 532 {
 533         struct nand_chip *chip = mtd->priv;
 534         unsigned long timeo = jiffies + msecs_to_jiffies(20);
 535
 536         /* 400ms timeout */
 537         if (in_interrupt() || oops_in_progress)
 538                 return panic_nand_wait_ready(mtd, 400);
 539
 540         led_trigger_event(nand_led_trigger, LED_FULL);
 541         /* Wait until command is processed or timeout occurs */
 542         do {
 543                 if (chip->dev_ready(mtd))
 544                         break;
 545                 touch_softlockup_watchdog();
 546         } while (time_before(jiffies, timeo));
 547         led_trigger_event(nand_led_trigger, LED_OFF);
 548 }
 549 EXPORT_SYMBOL_GPL(nand_wait_ready);
 550
 551 /**
 552  * nand_command - [DEFAULT] Send command to NAND device
 553  * @mtd: MTD device structure
 554  * @command: the command to be sent
 555  * @column: the column address for this command, -1 if none
 556  * @page_addr: the page address for this command, -1 if none
 557  *
 558  * Send command to NAND device. This function is used for small page devices
 559  * (512 Bytes per page).
 560  */
 561 static void nand_command(struct mtd_info *mtd, unsigned int command,
 562                          int column, int page_addr)
 563 {
 564         register struct nand_chip *chip = mtd->priv;
 565         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 566
 567         /* Write out the command to the device */
 568         if (command == NAND_CMD_SEQIN) {
 569                 int readcmd;
 570
 571                 if (column >= mtd->writesize) {
 572                         /* OOB area */
 573                         column -= mtd->writesize;
 574                         readcmd = NAND_CMD_READOOB;
 575                 } else if (column < 256) {
 576                         /* First 256 bytes --> READ0 */
 577                         readcmd = NAND_CMD_READ0;
 578                 } else {
 579                         column -= 256;
 580                         readcmd = NAND_CMD_READ1;
 581                 }
 582                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 583                 ctrl &= ~NAND_CTRL_CHANGE;
 584         }
 585         chip->cmd_ctrl(mtd, command, ctrl);
 586
 587         /* Address cycle, when necessary */
 588         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 589         /* Serially input address */
 590         if (column != -1) {
 591                 /* Adjust columns for 16 bit buswidth */
 592                 if (chip->options & NAND_BUSWIDTH_16)
 593                         column >>= 1;
 594                 chip->cmd_ctrl(mtd, column, ctrl);
 595                 ctrl &= ~NAND_CTRL_CHANGE;
 596         }
 597         if (page_addr != -1) {
 598                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 599                 ctrl &= ~NAND_CTRL_CHANGE;
 600                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 601                 /* One more address cycle for devices > 32MiB */
 602                 if (chip->chipsize > (32 << 20))
 603                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 604         }
 605         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 606
 607         /*
 608          * Program and erase have their own busy handlers status and sequential
 609          * in needs no delay
 610          */
 611         switch (command) {
 612
 613         case NAND_CMD_PAGEPROG:
 614         case NAND_CMD_ERASE1:
 615         case NAND_CMD_ERASE2:
 616         case NAND_CMD_SEQIN:
 617         case NAND_CMD_STATUS:
 618                 return;
 619
 620         case NAND_CMD_RESET:
 621                 if (chip->dev_ready)
 622                         break;
 623                 udelay(chip->chip_delay);
 624                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 625                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 626                 chip->cmd_ctrl(mtd,
 627                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 628                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
 629                                 ;
 630                 return;
 631
 632                 /* This applies to read commands */
 633         default:
 634                 /*
 635                  * If we don't have access to the busy pin, we apply the given
 636                  * command delay
 637                  */
 638                 if (!chip->dev_ready) {
 639                         udelay(chip->chip_delay);
 640                         return;
 641                 }
 642         }
 643         /*
 644          * Apply this short delay always to ensure that we do wait tWB in
 645          * any case on any machine.
 646          */
 647         ndelay(100);
 648
 649         nand_wait_ready(mtd);
 650 }
 651
 652 /**
 653  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 654  * @mtd: MTD device structure
 655  * @command: the command to be sent
 656  * @column: the column address for this command, -1 if none
 657  * @page_addr: the page address for this command, -1 if none
 658  *
 659  * Send command to NAND device. This is the version for the new large page
 660  * devices. We don't have the separate regions as we have in the small page
 661  * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
 662  */
 663 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 664                             int column, int page_addr)
 665 {
 666         register struct nand_chip *chip = mtd->priv;
 667
 668         /* Emulate NAND_CMD_READOOB */
 669         if (command == NAND_CMD_READOOB) {
 670                 column += mtd->writesize;
 671                 command = NAND_CMD_READ0;
 672         }
 673
 674         /* Command latch cycle */
 675         chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 676
 677         if (column != -1 || page_addr != -1) {
 678                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 679
 680                 /* Serially input address */
 681                 if (column != -1) {
 682                         /* Adjust columns for 16 bit buswidth */
 683                         if (chip->options & NAND_BUSWIDTH_16)
 684                                 column >>= 1;
 685                         chip->cmd_ctrl(mtd, column, ctrl);
 686                         ctrl &= ~NAND_CTRL_CHANGE;
 687                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 688                 }
 689                 if (page_addr != -1) {
 690                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 691                         chip->cmd_ctrl(mtd, page_addr >> 8,
 692                                        NAND_NCE | NAND_ALE);
 693                         /* One more address cycle for devices > 128MiB */
 694                         if (chip->chipsize > (128 << 20))
 695                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 696                                                NAND_NCE | NAND_ALE);
 697                 }
 698         }
 699         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 700
 701         /*
 702          * Program and erase have their own busy handlers status, sequential
 703          * in, and deplete1 need no delay.
 704          */
 705         switch (command) {
 706
 707         case NAND_CMD_CACHEDPROG:
 708         case NAND_CMD_PAGEPROG:
 709         case NAND_CMD_ERASE1:
 710         case NAND_CMD_ERASE2:
 711         case NAND_CMD_SEQIN:
 712         case NAND_CMD_RNDIN:
 713         case NAND_CMD_STATUS:
 714                 return;
 715
 716         case NAND_CMD_RESET:
 717                 if (chip->dev_ready)
 718                         break;
 719                 udelay(chip->chip_delay);
 720                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 721                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 722                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 723                                NAND_NCE | NAND_CTRL_CHANGE);
 724                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
 725                                 ;
 726                 return;
 727
 728         case NAND_CMD_RNDOUT:
 729                 /* No ready / busy check necessary */
 730                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 731                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 732                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 733                                NAND_NCE | NAND_CTRL_CHANGE);
 734                 return;
 735
 736         case NAND_CMD_READ0:
 737                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 738                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 739                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 740                                NAND_NCE | NAND_CTRL_CHANGE);
 741
 742                 /* This applies to read commands */
 743         default:
 744                 /*
 745                  * If we don't have access to the busy pin, we apply the given
 746                  * command delay.
 747                  */
 748                 if (!chip->dev_ready) {
 749                         udelay(chip->chip_delay);
 750                         return;
 751                 }
 752         }
 753
 754         /*
 755          * Apply this short delay always to ensure that we do wait tWB in
 756          * any case on any machine.
 757          */
 758         ndelay(100);
 759
 760         nand_wait_ready(mtd);
 761 }
 762
 763 /**
 764  * panic_nand_get_device - [GENERIC] Get chip for selected access
 765  * @chip: the nand chip descriptor
 766  * @mtd: MTD device structure
 767  * @new_state: the state which is requested
 768  *
 769  * Used when in panic, no locks are taken.
 770  */
 771 static void panic_nand_get_device(struct nand_chip *chip,
 772                       struct mtd_info *mtd, int new_state)
 773 {
 774         /* Hardware controller shared among independent devices */
 775         chip->controller->active = chip;
 776         chip->state = new_state;
 777 }
 778
 779 /**
 780  * nand_get_device - [GENERIC] Get chip for selected access
 781  * @mtd: MTD device structure
 782  * @new_state: the state which is requested
 783  *
 784  * Get the device and lock it for exclusive access
 785  */
 786 static int
 787 nand_get_device(struct mtd_info *mtd, int new_state)
 788 {
 789         struct nand_chip *chip = mtd->priv;
 790         spinlock_t *lock = &chip->controller->lock;
 791         wait_queue_head_t *wq = &chip->controller->wq;
 792         DECLARE_WAITQUEUE(wait, current);
 793 retry:
 794         spin_lock(lock);
 795
 796         /* Hardware controller shared among independent devices */
 797         if (!chip->controller->active)
 798                 chip->controller->active = chip;
 799
 800         if (chip->controller->active == chip && chip->state == FL_READY) {
 801                 chip->state = new_state;
 802                 spin_unlock(lock);
 803                 return 0;
 804         }
 805         if (new_state == FL_PM_SUSPENDED) {
 806                 if (chip->controller->active->state == FL_PM_SUSPENDED) {
 807                         chip->state = FL_PM_SUSPENDED;
 808                         spin_unlock(lock);
 809                         return 0;
 810                 }
 811         }
 812         set_current_state(TASK_UNINTERRUPTIBLE);
 813         add_wait_queue(wq, &wait);
 814         spin_unlock(lock);
 815         schedule();
 816         remove_wait_queue(wq, &wait);
 817         goto retry;
 818 }
 819
 820 /**
 821  * panic_nand_wait - [GENERIC] wait until the command is done
 822  * @mtd: MTD device structure
 823  * @chip: NAND chip structure
 824  * @timeo: timeout
 825  *
 826  * Wait for command done. This is a helper function for nand_wait used when
 827  * we are in interrupt context. May happen when in panic and trying to write
 828  * an oops through mtdoops.
 829  */
 830 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
 831                             unsigned long timeo)
 832 {
 833         int i;
 834         for (i = 0; i < timeo; i++) {
 835                 if (chip->dev_ready) {
 836                         if (chip->dev_ready(mtd))
 837                                 break;
 838                 } else {
 839                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
 840                                 break;
 841                 }
 842                 mdelay(1);
 843         }
 844 }
 845
 846 /**
 847  * nand_wait - [DEFAULT] wait until the command is done
 848  * @mtd: MTD device structure
 849  * @chip: NAND chip structure
 850  *
 851  * Wait for command done. This applies to erase and program only. Erase can
 852  * take up to 400ms and program up to 20ms according to general NAND and
 853  * SmartMedia specs.
 854  */
 855 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 856 {
 857
 858         int status, state = chip->state;
 859         unsigned long timeo = (state == FL_ERASING ? 400 : 20);
 860
 861         led_trigger_event(nand_led_trigger, LED_FULL);
 862
 863         /*
 864          * Apply this short delay always to ensure that we do wait tWB in any
 865          * case on any machine.
 866          */
 867         ndelay(100);
 868
 869         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 870
 871         if (in_interrupt() || oops_in_progress)
 872                 panic_nand_wait(mtd, chip, timeo);
 873         else {
 874                 timeo = jiffies + msecs_to_jiffies(timeo);
 875                 while (time_before(jiffies, timeo)) {
 876                         if (chip->dev_ready) {
 877                                 if (chip->dev_ready(mtd))
 878                                         break;
 879                         } else {
 880                                 if (chip->read_byte(mtd) & NAND_STATUS_READY)
 881                                         break;
 882                         }
 883                         cond_resched();
 884                 }
 885         }
 886         led_trigger_event(nand_led_trigger, LED_OFF);
 887
 888         status = (int)chip->read_byte(mtd);
 889         /* This can happen if in case of timeout or buggy dev_ready */
 890         WARN_ON(!(status & NAND_STATUS_READY));
 891         return status;
 892 }
 893
 894 /**
 895  * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
 896  * @mtd: mtd info
 897  * @ofs: offset to start unlock from
 898  * @len: length to unlock
 899  * @invert: when = 0, unlock the range of blocks within the lower and
 900  *                    upper boundary address
 901  *          when = 1, unlock the range of blocks outside the boundaries
 902  *                    of the lower and upper boundary address
 903  *
 904  * Returs unlock status.
 905  */
 906 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
 907                                         uint64_t len, int invert)
 908 {
 909         int ret = 0;
 910         int status, page;
 911         struct nand_chip *chip = mtd->priv;
 912
 913         /* Submit address of first page to unlock */
 914         page = ofs >> chip->page_shift;
 915         chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
 916
 917         /* Submit address of last page to unlock */
 918         page = (ofs + len) >> chip->page_shift;
 919         chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
 920                                 (page | invert) & chip->pagemask);
 921
 922         /* Call wait ready function */
 923         status = chip->waitfunc(mtd, chip);
 924         /* See if device thinks it succeeded */
 925         if (status & NAND_STATUS_FAIL) {
 926                 pr_debug("%s: error status = 0x%08x\n",
 927                                         __func__, status);
 928                 ret = -EIO;
 929         }
 930
 931         return ret;
 932 }
 933
 934 /**
 935  * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
 936  * @mtd: mtd info
 937  * @ofs: offset to start unlock from
 938  * @len: length to unlock
 939  *
 940  * Returns unlock status.
 941  */
 942 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 943 {
 944         int ret = 0;
 945         int chipnr;
 946         struct nand_chip *chip = mtd->priv;
 947
 948         pr_debug("%s: start = 0x%012llx, len = %llu\n",
 949                         __func__, (unsigned long long)ofs, len);
 950
 951         if (check_offs_len(mtd, ofs, len))
 952                 ret = -EINVAL;
 953
 954         /* Align to last block address if size addresses end of the device */
 955         if (ofs + len == mtd->size)
 956                 len -= mtd->erasesize;
 957
 958         nand_get_device(mtd, FL_UNLOCKING);
 959
 960         /* Shift to get chip number */
 961         chipnr = ofs >> chip->chip_shift;
 962
 963         chip->select_chip(mtd, chipnr);
 964
 965         /* Check, if it is write protected */
 966         if (nand_check_wp(mtd)) {
 967                 pr_debug("%s: device is write protected!\n",
 968                                         __func__);
 969                 ret = -EIO;
 970                 goto out;
 971         }
 972
 973         ret = __nand_unlock(mtd, ofs, len, 0);
 974
 975 out:
 976         chip->select_chip(mtd, -1);
 977         nand_release_device(mtd);
 978
 979         return ret;
 980 }
 981 EXPORT_SYMBOL(nand_unlock);
 982
 983 /**
 984  * nand_lock - [REPLACEABLE] locks all blocks present in the device
 985  * @mtd: mtd info
 986  * @ofs: offset to start unlock from
 987  * @len: length to unlock
 988  *
 989  * This feature is not supported in many NAND parts. 'Micron' NAND parts do
 990  * have this feature, but it allows only to lock all blocks, not for specified
 991  * range for block. Implementing 'lock' feature by making use of 'unlock', for
 992  * now.
 993  *
 994  * Returns lock status.
 995  */
 996 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 997 {
 998         int ret = 0;
 999         int chipnr, status, page;
1000         struct nand_chip *chip = mtd->priv;
1001
1002         pr_debug("%s: start = 0x%012llx, len = %llu\n",
1003                         __func__, (unsigned long long)ofs, len);
1004
1005         if (check_offs_len(mtd, ofs, len))
1006                 ret = -EINVAL;
1007
1008         nand_get_device(mtd, FL_LOCKING);
1009
1010         /* Shift to get chip number */
1011         chipnr = ofs >> chip->chip_shift;
1012
1013         chip->select_chip(mtd, chipnr);
1014
1015         /* Check, if it is write protected */
1016         if (nand_check_wp(mtd)) {
1017                 pr_debug("%s: device is write protected!\n",
1018                                         __func__);
1019                 status = MTD_ERASE_FAILED;
1020                 ret = -EIO;
1021                 goto out;
1022         }
1023
1024         /* Submit address of first page to lock */
1025         page = ofs >> chip->page_shift;
1026         chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1027
1028         /* Call wait ready function */
1029         status = chip->waitfunc(mtd, chip);
1030         /* See if device thinks it succeeded */
1031         if (status & NAND_STATUS_FAIL) {
1032                 pr_debug("%s: error status = 0x%08x\n",
1033                                         __func__, status);
1034                 ret = -EIO;
1035                 goto out;
1036         }
1037
1038         ret = __nand_unlock(mtd, ofs, len, 0x1);
1039
1040 out:
1041         chip->select_chip(mtd, -1);
1042         nand_release_device(mtd);
1043
1044         return ret;
1045 }
1046 EXPORT_SYMBOL(nand_lock);
1047
1048 /**
1049  * nand_read_page_raw - [INTERN] read raw page data without ecc
1050  * @mtd: mtd info structure
1051  * @chip: nand chip info structure
1052  * @buf: buffer to store read data
1053  * @oob_required: caller requires OOB data read to chip->oob_poi
1054  * @page: page number to read
1055  *
1056  * Not for syndrome calculating ECC controllers, which use a special oob layout.
1057  */
1058 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1059                               uint8_t *buf, int oob_required, int page)
1060 {
1061         chip->read_buf(mtd, buf, mtd->writesize);
1062         if (oob_required)
1063                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1064         return 0;
1065 }
1066
1067 /**
1068  * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1069  * @mtd: mtd info structure
1070  * @chip: nand chip info structure
1071  * @buf: buffer to store read data
1072  * @oob_required: caller requires OOB data read to chip->oob_poi
1073  * @page: page number to read
1074  *
1075  * We need a special oob layout and handling even when OOB isn't used.
1076  */
1077 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1078                                        struct nand_chip *chip, uint8_t *buf,
1079                                        int oob_required, int page)
1080 {
1081         int eccsize = chip->ecc.size;
1082         int eccbytes = chip->ecc.bytes;
1083         uint8_t *oob = chip->oob_poi;
1084         int steps, size;
1085
1086         for (steps = chip->ecc.steps; steps > 0; steps--) {
1087                 chip->read_buf(mtd, buf, eccsize);
1088                 buf += eccsize;
1089
1090                 if (chip->ecc.prepad) {
1091                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1092                         oob += chip->ecc.prepad;
1093                 }
1094
1095                 chip->read_buf(mtd, oob, eccbytes);
1096                 oob += eccbytes;
1097
1098                 if (chip->ecc.postpad) {
1099                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1100                         oob += chip->ecc.postpad;
1101                 }
1102         }
1103
1104         size = mtd->oobsize - (oob - chip->oob_poi);
1105         if (size)
1106                 chip->read_buf(mtd, oob, size);
1107
1108         return 0;
1109 }
1110
1111 /**
1112  * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1113  * @mtd: mtd info structure
1114  * @chip: nand chip info structure
1115  * @buf: buffer to store read data
1116  * @oob_required: caller requires OOB data read to chip->oob_poi
1117  * @page: page number to read
1118  */
1119 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1120                                 uint8_t *buf, int oob_required, int page)
1121 {
1122         int i, eccsize = chip->ecc.size;
1123         int eccbytes = chip->ecc.bytes;
1124         int eccsteps = chip->ecc.steps;
1125         uint8_t *p = buf;
1126         uint8_t *ecc_calc = chip->buffers->ecccalc;
1127         uint8_t *ecc_code = chip->buffers->ecccode;
1128         uint32_t *eccpos = chip->ecc.layout->eccpos;
1129         unsigned int max_bitflips = 0;
1130
1131         chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1132
1133         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1134                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1135
1136         for (i = 0; i < chip->ecc.total; i++)
1137                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1138
1139         eccsteps = chip->ecc.steps;
1140         p = buf;
1141
1142         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1143                 int stat;
1144
1145                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1146                 if (stat < 0) {
1147                         mtd->ecc_stats.failed++;
1148                 } else {
1149                         mtd->ecc_stats.corrected += stat;
1150                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1151                 }
1152         }
1153         return max_bitflips;
1154 }
1155
1156 /**
1157  * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1158  * @mtd: mtd info structure
1159  * @chip: nand chip info structure
1160  * @data_offs: offset of requested data within the page
1161  * @readlen: data length
1162  * @bufpoi: buffer to store read data
1163  */
1164 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1165                         uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
1166 {
1167         int start_step, end_step, num_steps;
1168         uint32_t *eccpos = chip->ecc.layout->eccpos;
1169         uint8_t *p;
1170         int data_col_addr, i, gaps = 0;
1171         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1172         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1173         int index = 0;
1174         unsigned int max_bitflips = 0;
1175
1176         /* Column address within the page aligned to ECC size (256bytes) */
1177         start_step = data_offs / chip->ecc.size;
1178         end_step = (data_offs + readlen - 1) / chip->ecc.size;
1179         num_steps = end_step - start_step + 1;
1180
1181         /* Data size aligned to ECC ecc.size */
1182         datafrag_len = num_steps * chip->ecc.size;
1183         eccfrag_len = num_steps * chip->ecc.bytes;
1184
1185         data_col_addr = start_step * chip->ecc.size;
1186         /* If we read not a page aligned data */
1187         if (data_col_addr != 0)
1188                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1189
1190         p = bufpoi + data_col_addr;
1191         chip->read_buf(mtd, p, datafrag_len);
1192
1193         /* Calculate ECC */
1194         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1195                 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1196
1197         /*
1198          * The performance is faster if we position offsets according to
1199          * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1200          */
1201         for (i = 0; i < eccfrag_len - 1; i++) {
1202                 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1203                         eccpos[i + start_step * chip->ecc.bytes + 1]) {
1204                         gaps = 1;
1205                         break;
1206                 }
1207         }
1208         if (gaps) {
1209                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1210                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1211         } else {
1212                 /*
1213                  * Send the command to read the particular ECC bytes take care
1214                  * about buswidth alignment in read_buf.
1215                  */
1216                 index = start_step * chip->ecc.bytes;
1217
1218                 aligned_pos = eccpos[index] & ~(busw - 1);
1219                 aligned_len = eccfrag_len;
1220                 if (eccpos[index] & (busw - 1))
1221                         aligned_len++;
1222                 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1223                         aligned_len++;
1224
1225                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1226                                         mtd->writesize + aligned_pos, -1);
1227                 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1228         }
1229
1230         for (i = 0; i < eccfrag_len; i++)
1231                 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1232
1233         p = bufpoi + data_col_addr;
1234         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1235                 int stat;
1236
1237                 stat = chip->ecc.correct(mtd, p,
1238                         &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1239                 if (stat < 0) {
1240                         mtd->ecc_stats.failed++;
1241                 } else {
1242                         mtd->ecc_stats.corrected += stat;
1243                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1244                 }
1245         }
1246         return max_bitflips;
1247 }
1248
1249 /**
1250  * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1251  * @mtd: mtd info structure
1252  * @chip: nand chip info structure
1253  * @buf: buffer to store read data
1254  * @oob_required: caller requires OOB data read to chip->oob_poi
1255  * @page: page number to read
1256  *
1257  * Not for syndrome calculating ECC controllers which need a special oob layout.
1258  */
1259 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1260                                 uint8_t *buf, int oob_required, int page)
1261 {
1262         int i, eccsize = chip->ecc.size;
1263         int eccbytes = chip->ecc.bytes;
1264         int eccsteps = chip->ecc.steps;
1265         uint8_t *p = buf;
1266         uint8_t *ecc_calc = chip->buffers->ecccalc;
1267         uint8_t *ecc_code = chip->buffers->ecccode;
1268         uint32_t *eccpos = chip->ecc.layout->eccpos;
1269         unsigned int max_bitflips = 0;
1270
1271         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1272                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1273                 chip->read_buf(mtd, p, eccsize);
1274                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1275         }
1276         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1277
1278         for (i = 0; i < chip->ecc.total; i++)
1279                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1280
1281         eccsteps = chip->ecc.steps;
1282         p = buf;
1283
1284         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1285                 int stat;
1286
1287                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1288                 if (stat < 0) {
1289                         mtd->ecc_stats.failed++;
1290                 } else {
1291                         mtd->ecc_stats.corrected += stat;
1292                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1293                 }
1294         }
1295         return max_bitflips;
1296 }
1297
1298 /**
1299  * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1300  * @mtd: mtd info structure
1301  * @chip: nand chip info structure
1302  * @buf: buffer to store read data
1303  * @oob_required: caller requires OOB data read to chip->oob_poi
1304  * @page: page number to read
1305  *
1306  * Hardware ECC for large page chips, require OOB to be read first. For this
1307  * ECC mode, the write_page method is re-used from ECC_HW. These methods
1308  * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1309  * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1310  * the data area, by overwriting the NAND manufacturer bad block markings.
1311  */
1312 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1313         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1314 {
1315         int i, eccsize = chip->ecc.size;
1316         int eccbytes = chip->ecc.bytes;
1317         int eccsteps = chip->ecc.steps;
1318         uint8_t *p = buf;
1319         uint8_t *ecc_code = chip->buffers->ecccode;
1320         uint32_t *eccpos = chip->ecc.layout->eccpos;
1321         uint8_t *ecc_calc = chip->buffers->ecccalc;
1322         unsigned int max_bitflips = 0;
1323
1324         /* Read the OOB area first */
1325         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1326         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1327         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1328
1329         for (i = 0; i < chip->ecc.total; i++)
1330                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1331
1332         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1333                 int stat;
1334
1335                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1336                 chip->read_buf(mtd, p, eccsize);
1337                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1338
1339                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1340                 if (stat < 0) {
1341                         mtd->ecc_stats.failed++;
1342                 } else {
1343                         mtd->ecc_stats.corrected += stat;
1344                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1345                 }
1346         }
1347         return max_bitflips;
1348 }
1349
1350 /**
1351  * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1352  * @mtd: mtd info structure
1353  * @chip: nand chip info structure
1354  * @buf: buffer to store read data
1355  * @oob_required: caller requires OOB data read to chip->oob_poi
1356  * @page: page number to read
1357  *
1358  * The hw generator calculates the error syndrome automatically. Therefore we
1359  * need a special oob layout and handling.
1360  */
1361 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1362                                    uint8_t *buf, int oob_required, int page)
1363 {
1364         int i, eccsize = chip->ecc.size;
1365         int eccbytes = chip->ecc.bytes;
1366         int eccsteps = chip->ecc.steps;
1367         uint8_t *p = buf;
1368         uint8_t *oob = chip->oob_poi;
1369         unsigned int max_bitflips = 0;
1370
1371         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1372                 int stat;
1373
1374                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1375                 chip->read_buf(mtd, p, eccsize);
1376
1377                 if (chip->ecc.prepad) {
1378                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1379                         oob += chip->ecc.prepad;
1380                 }
1381
1382                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1383                 chip->read_buf(mtd, oob, eccbytes);
1384                 stat = chip->ecc.correct(mtd, p, oob, NULL);
1385
1386                 if (stat < 0) {
1387                         mtd->ecc_stats.failed++;
1388                 } else {
1389                         mtd->ecc_stats.corrected += stat;
1390                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1391                 }
1392
1393                 oob += eccbytes;
1394
1395                 if (chip->ecc.postpad) {
1396                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1397                         oob += chip->ecc.postpad;
1398                 }
1399         }
1400
1401         /* Calculate remaining oob bytes */
1402         i = mtd->oobsize - (oob - chip->oob_poi);
1403         if (i)
1404                 chip->read_buf(mtd, oob, i);
1405
1406         return max_bitflips;
1407 }
1408
1409 /**
1410  * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1411  * @chip: nand chip structure
1412  * @oob: oob destination address
1413  * @ops: oob ops structure
1414  * @len: size of oob to transfer
1415  */
1416 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1417                                   struct mtd_oob_ops *ops, size_t len)
1418 {
1419         switch (ops->mode) {
1420
1421         case MTD_OPS_PLACE_OOB:
1422         case MTD_OPS_RAW:
1423                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1424                 return oob + len;
1425
1426         case MTD_OPS_AUTO_OOB: {
1427                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1428                 uint32_t boffs = 0, roffs = ops->ooboffs;
1429                 size_t bytes = 0;
1430
1431                 for (; free->length && len; free++, len -= bytes) {
1432                         /* Read request not from offset 0? */
1433                         if (unlikely(roffs)) {
1434                                 if (roffs >= free->length) {
1435                                         roffs -= free->length;
1436                                         continue;
1437                                 }
1438                                 boffs = free->offset + roffs;
1439                                 bytes = min_t(size_t, len,
1440                                               (free->length - roffs));
1441                                 roffs = 0;
1442                         } else {
1443                                 bytes = min_t(size_t, len, free->length);
1444                                 boffs = free->offset;
1445                         }
1446                         memcpy(oob, chip->oob_poi + boffs, bytes);
1447                         oob += bytes;
1448                 }
1449                 return oob;
1450         }
1451         default:
1452                 BUG();
1453         }
1454         return NULL;
1455 }
1456
1457 /**
1458  * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1459  * @mtd: MTD device structure
1460  * @retry_mode: the retry mode to use
1461  *
1462  * Some vendors supply a special command to shift the Vt threshold, to be used
1463  * when there are too many bitflips in a page (i.e., ECC error). After setting
1464  * a new threshold, the host should retry reading the page.
1465  */
1466 static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
1467 {
1468         struct nand_chip *chip = mtd->priv;
1469
1470         pr_debug("setting READ RETRY mode %d\n", retry_mode);
1471
1472         if (retry_mode >= chip->read_retries)
1473                 return -EINVAL;
1474
1475         if (!chip->setup_read_retry)
1476                 return -EOPNOTSUPP;
1477
1478         return chip->setup_read_retry(mtd, retry_mode);
1479 }
1480
1481 /**
1482  * nand_do_read_ops - [INTERN] Read data with ECC
1483  * @mtd: MTD device structure
1484  * @from: offset to read from
1485  * @ops: oob ops structure
1486  *
1487  * Internal function. Called with chip held.
1488  */
1489 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1490                             struct mtd_oob_ops *ops)
1491 {
1492         int chipnr, page, realpage, col, bytes, aligned, oob_required;
1493         struct nand_chip *chip = mtd->priv;
1494         int ret = 0;
1495         uint32_t readlen = ops->len;
1496         uint32_t oobreadlen = ops->ooblen;
1497         uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1498                 mtd->oobavail : mtd->oobsize;
1499
1500         uint8_t *bufpoi, *oob, *buf;
1501         unsigned int max_bitflips = 0;
1502         int retry_mode = 0;
1503         bool ecc_fail = false;
1504
1505         chipnr = (int)(from >> chip->chip_shift);
1506         chip->select_chip(mtd, chipnr);
1507
1508         realpage = (int)(from >> chip->page_shift);
1509         page = realpage & chip->pagemask;
1510
1511         col = (int)(from & (mtd->writesize - 1));
1512
1513         buf = ops->datbuf;
1514         oob = ops->oobbuf;
1515         oob_required = oob ? 1 : 0;
1516
1517         while (1) {
1518                 unsigned int ecc_failures = mtd->ecc_stats.failed;
1519
1520                 bytes = min(mtd->writesize - col, readlen);
1521                 aligned = (bytes == mtd->writesize);
1522
1523                 /* Is the current page in the buffer? */
1524                 if (realpage != chip->pagebuf || oob) {
1525                         bufpoi = aligned ? buf : chip->buffers->databuf;
1526
1527 read_retry:
1528                         chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1529
1530                         /*
1531                          * Now read the page into the buffer.  Absent an error,
1532                          * the read methods return max bitflips per ecc step.
1533                          */
1534                         if (unlikely(ops->mode == MTD_OPS_RAW))
1535                                 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1536                                                               oob_required,
1537                                                               page);
1538                         else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1539                                  !oob)
1540                                 ret = chip->ecc.read_subpage(mtd, chip,
1541                                                         col, bytes, bufpoi);
1542                         else
1543                                 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1544                                                           oob_required, page);
1545                         if (ret < 0) {
1546                                 if (!aligned)
1547                                         /* Invalidate page cache */
1548                                         chip->pagebuf = -1;
1549                                 break;
1550                         }
1551
1552                         max_bitflips = max_t(unsigned int, max_bitflips, ret);
1553
1554                         /* Transfer not aligned data */
1555                         if (!aligned) {
1556                                 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1557                                     !(mtd->ecc_stats.failed - ecc_failures) &&
1558                                     (ops->mode != MTD_OPS_RAW)) {
1559                                         chip->pagebuf = realpage;
1560                                         chip->pagebuf_bitflips = ret;
1561                                 } else {
1562                                         /* Invalidate page cache */
1563                                         chip->pagebuf = -1;
1564                                 }
1565                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1566                         }
1567
1568                         if (unlikely(oob)) {
1569                                 int toread = min(oobreadlen, max_oobsize);
1570
1571                                 if (toread) {
1572                                         oob = nand_transfer_oob(chip,
1573                                                 oob, ops, toread);
1574                                         oobreadlen -= toread;
1575                                 }
1576                         }
1577
1578                         if (chip->options & NAND_NEED_READRDY) {
1579                                 /* Apply delay or wait for ready/busy pin */
1580                                 if (!chip->dev_ready)
1581                                         udelay(chip->chip_delay);
1582                                 else
1583                                         nand_wait_ready(mtd);
1584                         }
1585
1586                         if (mtd->ecc_stats.failed - ecc_failures) {
1587                                 if (retry_mode + 1 <= chip->read_retries) {
1588                                         retry_mode++;
1589                                         ret = nand_setup_read_retry(mtd,
1590                                                         retry_mode);
1591                                         if (ret < 0)
1592                                                 break;
1593
1594                                         /* Reset failures; retry */
1595                                         mtd->ecc_stats.failed = ecc_failures;
1596                                         goto read_retry;
1597                                 } else {
1598                                         /* No more retry modes; real failure */
1599                                         ecc_fail = true;
1600                                 }
1601                         }
1602
1603                         buf += bytes;
1604                 } else {
1605                         memcpy(buf, chip->buffers->databuf + col, bytes);
1606                         buf += bytes;
1607                         max_bitflips = max_t(unsigned int, max_bitflips,
1608                                              chip->pagebuf_bitflips);
1609                 }
1610
1611                 readlen -= bytes;
1612
1613                 /* Reset to retry mode 0 */
1614                 if (retry_mode) {
1615                         ret = nand_setup_read_retry(mtd, 0);
1616                         if (ret < 0)
1617                                 break;
1618                         retry_mode = 0;
1619                 }
1620
1621                 if (!readlen)
1622                         break;
1623
1624                 /* For subsequent reads align to page boundary */
1625                 col = 0;
1626                 /* Increment page address */
1627                 realpage++;
1628
1629                 page = realpage & chip->pagemask;
1630                 /* Check, if we cross a chip boundary */
1631                 if (!page) {
1632                         chipnr++;
1633                         chip->select_chip(mtd, -1);
1634                         chip->select_chip(mtd, chipnr);
1635                 }
1636         }
1637         chip->select_chip(mtd, -1);
1638
1639         ops->retlen = ops->len - (size_t) readlen;
1640         if (oob)
1641                 ops->oobretlen = ops->ooblen - oobreadlen;
1642
1643         if (ret < 0)
1644                 return ret;
1645
1646         if (ecc_fail)
1647                 return -EBADMSG;
1648
1649         return max_bitflips;
1650 }
1651
1652 /**
1653  * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1654  * @mtd: MTD device structure
1655  * @from: offset to read from
1656  * @len: number of bytes to read
1657  * @retlen: pointer to variable to store the number of read bytes
1658  * @buf: the databuffer to put data
1659  *
1660  * Get hold of the chip and call nand_do_read.
1661  */
1662 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1663                      size_t *retlen, uint8_t *buf)
1664 {
1665         struct mtd_oob_ops ops;
1666         int ret;
1667
1668         nand_get_device(mtd, FL_READING);
1669         ops.len = len;
1670         ops.datbuf = buf;
1671         ops.oobbuf = NULL;
1672         ops.mode = MTD_OPS_PLACE_OOB;
1673         ret = nand_do_read_ops(mtd, from, &ops);
1674         *retlen = ops.retlen;
1675         nand_release_device(mtd);
1676         return ret;
1677 }
1678
1679 /**
1680  * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1681  * @mtd: mtd info structure
1682  * @chip: nand chip info structure
1683  * @page: page number to read
1684  */
1685 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1686                              int page)
1687 {
1688         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1689         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1690         return 0;
1691 }
1692
1693 /**
1694  * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1695  *                          with syndromes
1696  * @mtd: mtd info structure
1697  * @chip: nand chip info structure
1698  * @page: page number to read
1699  */
1700 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1701                                   int page)
1702 {
1703         uint8_t *buf = chip->oob_poi;
1704         int length = mtd->oobsize;
1705         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1706         int eccsize = chip->ecc.size;
1707         uint8_t *bufpoi = buf;
1708         int i, toread, sndrnd = 0, pos;
1709
1710         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1711         for (i = 0; i < chip->ecc.steps; i++) {
1712                 if (sndrnd) {
1713                         pos = eccsize + i * (eccsize + chunk);
1714                         if (mtd->writesize > 512)
1715                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1716                         else
1717                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1718                 } else
1719                         sndrnd = 1;
1720                 toread = min_t(int, length, chunk);
1721                 chip->read_buf(mtd, bufpoi, toread);
1722                 bufpoi += toread;
1723                 length -= toread;
1724         }
1725         if (length > 0)
1726                 chip->read_buf(mtd, bufpoi, length);
1727
1728         return 0;
1729 }
1730
1731 /**
1732  * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1733  * @mtd: mtd info structure
1734  * @chip: nand chip info structure
1735  * @page: page number to write
1736  */
1737 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1738                               int page)
1739 {
1740         int status = 0;
1741         const uint8_t *buf = chip->oob_poi;
1742         int length = mtd->oobsize;
1743
1744         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1745         chip->write_buf(mtd, buf, length);
1746         /* Send command to program the OOB data */
1747         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1748
1749         status = chip->waitfunc(mtd, chip);
1750
1751         return status & NAND_STATUS_FAIL ? -EIO : 0;
1752 }
1753
1754 /**
1755  * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1756  *                           with syndrome - only for large page flash
1757  * @mtd: mtd info structure
1758  * @chip: nand chip info structure
1759  * @page: page number to write
1760  */
1761 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1762                                    struct nand_chip *chip, int page)
1763 {
1764         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1765         int eccsize = chip->ecc.size, length = mtd->oobsize;
1766         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1767         const uint8_t *bufpoi = chip->oob_poi;
1768
1769         /*
1770          * data-ecc-data-ecc ... ecc-oob
1771          * or
1772          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1773          */
1774         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1775                 pos = steps * (eccsize + chunk);
1776                 steps = 0;
1777         } else
1778                 pos = eccsize;
1779
1780         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1781         for (i = 0; i < steps; i++) {
1782                 if (sndcmd) {
1783                         if (mtd->writesize <= 512) {
1784                                 uint32_t fill = 0xFFFFFFFF;
1785
1786                                 len = eccsize;
1787                                 while (len > 0) {
1788                                         int num = min_t(int, len, 4);
1789                                         chip->write_buf(mtd, (uint8_t *)&fill,
1790                                                         num);
1791                                         len -= num;
1792                                 }
1793                         } else {
1794                                 pos = eccsize + i * (eccsize + chunk);
1795                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1796                         }
1797                 } else
1798                         sndcmd = 1;
1799                 len = min_t(int, length, chunk);
1800                 chip->write_buf(mtd, bufpoi, len);
1801                 bufpoi += len;
1802                 length -= len;
1803         }
1804         if (length > 0)
1805                 chip->write_buf(mtd, bufpoi, length);
1806
1807         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1808         status = chip->waitfunc(mtd, chip);
1809
1810         return status & NAND_STATUS_FAIL ? -EIO : 0;
1811 }
1812
1813 /**
1814  * nand_do_read_oob - [INTERN] NAND read out-of-band
1815  * @mtd: MTD device structure
1816  * @from: offset to read from
1817  * @ops: oob operations description structure
1818  *
1819  * NAND read out-of-band data from the spare area.
1820  */
1821 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1822                             struct mtd_oob_ops *ops)
1823 {
1824         int page, realpage, chipnr;
1825         struct nand_chip *chip = mtd->priv;
1826         struct mtd_ecc_stats stats;
1827         int readlen = ops->ooblen;
1828         int len;
1829         uint8_t *buf = ops->oobbuf;
1830         int ret = 0;
1831
1832         pr_debug("%s: from = 0x%08Lx, len = %i\n",
1833                         __func__, (unsigned long long)from, readlen);
1834
1835         stats = mtd->ecc_stats;
1836
1837         if (ops->mode == MTD_OPS_AUTO_OOB)
1838                 len = chip->ecc.layout->oobavail;
1839         else
1840                 len = mtd->oobsize;
1841
1842         if (unlikely(ops->ooboffs >= len)) {
1843                 pr_debug("%s: attempt to start read outside oob\n",
1844                                 __func__);
1845                 return -EINVAL;
1846         }
1847
1848         /* Do not allow reads past end of device */
1849         if (unlikely(from >= mtd->size ||
1850                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1851                                         (from >> chip->page_shift)) * len)) {
1852                 pr_debug("%s: attempt to read beyond end of device\n",
1853                                 __func__);
1854                 return -EINVAL;
1855         }
1856
1857         chipnr = (int)(from >> chip->chip_shift);
1858         chip->select_chip(mtd, chipnr);
1859
1860         /* Shift to get page */
1861         realpage = (int)(from >> chip->page_shift);
1862         page = realpage & chip->pagemask;
1863
1864         while (1) {
1865                 if (ops->mode == MTD_OPS_RAW)
1866                         ret = chip->ecc.read_oob_raw(mtd, chip, page);
1867                 else
1868                         ret = chip->ecc.read_oob(mtd, chip, page);
1869
1870                 if (ret < 0)
1871                         break;
1872
1873                 len = min(len, readlen);
1874                 buf = nand_transfer_oob(chip, buf, ops, len);
1875
1876                 if (chip->options & NAND_NEED_READRDY) {
1877                         /* Apply delay or wait for ready/busy pin */
1878                         if (!chip->dev_ready)
1879                                 udelay(chip->chip_delay);
1880                         else
1881                                 nand_wait_ready(mtd);
1882                 }
1883
1884                 readlen -= len;
1885                 if (!readlen)
1886                         break;
1887
1888                 /* Increment page address */
1889                 realpage++;
1890
1891                 page = realpage & chip->pagemask;
1892                 /* Check, if we cross a chip boundary */
1893                 if (!page) {
1894                         chipnr++;
1895                         chip->select_chip(mtd, -1);
1896                         chip->select_chip(mtd, chipnr);
1897                 }
1898         }
1899         chip->select_chip(mtd, -1);
1900
1901         ops->oobretlen = ops->ooblen - readlen;
1902
1903         if (ret < 0)
1904                 return ret;
1905
1906         if (mtd->ecc_stats.failed - stats.failed)
1907                 return -EBADMSG;
1908
1909         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1910 }
1911
1912 /**
1913  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1914  * @mtd: MTD device structure
1915  * @from: offset to read from
1916  * @ops: oob operation description structure
1917  *
1918  * NAND read data and/or out-of-band data.
1919  */
1920 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1921                          struct mtd_oob_ops *ops)
1922 {
1923         int ret = -ENOTSUPP;
1924
1925         ops->retlen = 0;
1926
1927         /* Do not allow reads past end of device */
1928         if (ops->datbuf && (from + ops->len) > mtd->size) {
1929                 pr_debug("%s: attempt to read beyond end of device\n",
1930                                 __func__);
1931                 return -EINVAL;
1932         }
1933
1934         nand_get_device(mtd, FL_READING);
1935
1936         switch (ops->mode) {
1937         case MTD_OPS_PLACE_OOB:
1938         case MTD_OPS_AUTO_OOB:
1939         case MTD_OPS_RAW:
1940                 break;
1941
1942         default:
1943                 goto out;
1944         }
1945
1946         if (!ops->datbuf)
1947                 ret = nand_do_read_oob(mtd, from, ops);
1948         else
1949                 ret = nand_do_read_ops(mtd, from, ops);
1950
1951 out:
1952         nand_release_device(mtd);
1953         return ret;
1954 }
1955
1956
1957 /**
1958  * nand_write_page_raw - [INTERN] raw page write function
1959  * @mtd: mtd info structure
1960  * @chip: nand chip info structure
1961  * @buf: data buffer
1962  * @oob_required: must write chip->oob_poi to OOB
1963  *
1964  * Not for syndrome calculating ECC controllers, which use a special oob layout.
1965  */
1966 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1967                                 const uint8_t *buf, int oob_required)
1968 {
1969         chip->write_buf(mtd, buf, mtd->writesize);
1970         if (oob_required)
1971                 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1972
1973         return 0;
1974 }
1975
1976 /**
1977  * nand_write_page_raw_syndrome - [INTERN] raw page write function
1978  * @mtd: mtd info structure
1979  * @chip: nand chip info structure
1980  * @buf: data buffer
1981  * @oob_required: must write chip->oob_poi to OOB
1982  *
1983  * We need a special oob layout and handling even when ECC isn't checked.
1984  */
1985 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
1986                                         struct nand_chip *chip,
1987                                         const uint8_t *buf, int oob_required)
1988 {
1989         int eccsize = chip->ecc.size;
1990         int eccbytes = chip->ecc.bytes;
1991         uint8_t *oob = chip->oob_poi;
1992         int steps, size;
1993
1994         for (steps = chip->ecc.steps; steps > 0; steps--) {
1995                 chip->write_buf(mtd, buf, eccsize);
1996                 buf += eccsize;
1997
1998                 if (chip->ecc.prepad) {
1999                         chip->write_buf(mtd, oob, chip->ecc.prepad);
2000                         oob += chip->ecc.prepad;
2001                 }
2002
2003                 chip->read_buf(mtd, oob, eccbytes);
2004                 oob += eccbytes;
2005
2006                 if (chip->ecc.postpad) {
2007                         chip->write_buf(mtd, oob, chip->ecc.postpad);
2008                         oob += chip->ecc.postpad;
2009                 }
2010         }
2011
2012         size = mtd->oobsize - (oob - chip->oob_poi);
2013         if (size)
2014                 chip->write_buf(mtd, oob, size);
2015
2016         return 0;
2017 }
2018 /**
2019  * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2020  * @mtd: mtd info structure
2021  * @chip: nand chip info structure
2022  * @buf: data buffer
2023  * @oob_required: must write chip->oob_poi to OOB
2024  */
2025 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
2026                                   const uint8_t *buf, int oob_required)
2027 {
2028         int i, eccsize = chip->ecc.size;
2029         int eccbytes = chip->ecc.bytes;
2030         int eccsteps = chip->ecc.steps;
2031         uint8_t *ecc_calc = chip->buffers->ecccalc;
2032         const uint8_t *p = buf;
2033         uint32_t *eccpos = chip->ecc.layout->eccpos;
2034
2035         /* Software ECC calculation */
2036         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2037                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2038
2039         for (i = 0; i < chip->ecc.total; i++)
2040                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2041
2042         return chip->ecc.write_page_raw(mtd, chip, buf, 1);
2043 }
2044
2045 /**
2046  * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2047  * @mtd: mtd info structure
2048  * @chip: nand chip info structure
2049  * @buf: data buffer
2050  * @oob_required: must write chip->oob_poi to OOB
2051  */
2052 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
2053                                   const uint8_t *buf, int oob_required)
2054 {
2055         int i, eccsize = chip->ecc.size;
2056         int eccbytes = chip->ecc.bytes;
2057         int eccsteps = chip->ecc.steps;
2058         uint8_t *ecc_calc = chip->buffers->ecccalc;
2059         const uint8_t *p = buf;
2060         uint32_t *eccpos = chip->ecc.layout->eccpos;
2061
2062         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2063                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2064                 chip->write_buf(mtd, p, eccsize);
2065                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2066         }
2067
2068         for (i = 0; i < chip->ecc.total; i++)
2069                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2070
2071         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2072
2073         return 0;
2074 }
2075
2076
2077 /**
2078  * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write
2079  * @mtd:        mtd info structure
2080  * @chip:       nand chip info structure
2081  * @offset:     column address of subpage within the page
2082  * @data_len:   data length
2083  * @buf:        data buffer
2084  * @oob_required: must write chip->oob_poi to OOB
2085  */
2086 static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2087                                 struct nand_chip *chip, uint32_t offset,
2088                                 uint32_t data_len, const uint8_t *buf,
2089                                 int oob_required)
2090 {
2091         uint8_t *oob_buf  = chip->oob_poi;
2092         uint8_t *ecc_calc = chip->buffers->ecccalc;
2093         int ecc_size      = chip->ecc.size;
2094         int ecc_bytes     = chip->ecc.bytes;
2095         int ecc_steps     = chip->ecc.steps;
2096         uint32_t *eccpos  = chip->ecc.layout->eccpos;
2097         uint32_t start_step = offset / ecc_size;
2098         uint32_t end_step   = (offset + data_len - 1) / ecc_size;
2099         int oob_bytes       = mtd->oobsize / ecc_steps;
2100         int step, i;
2101
2102         for (step = 0; step < ecc_steps; step++) {
2103                 /* configure controller for WRITE access */
2104                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2105
2106                 /* write data (untouched subpages already masked by 0xFF) */
2107                 chip->write_buf(mtd, buf, ecc_size);
2108
2109                 /* mask ECC of un-touched subpages by padding 0xFF */
2110                 if ((step < start_step) || (step > end_step))
2111                         memset(ecc_calc, 0xff, ecc_bytes);
2112                 else
2113                         chip->ecc.calculate(mtd, buf, ecc_calc);
2114
2115                 /* mask OOB of un-touched subpages by padding 0xFF */
2116                 /* if oob_required, preserve OOB metadata of written subpage */
2117                 if (!oob_required || (step < start_step) || (step > end_step))
2118                         memset(oob_buf, 0xff, oob_bytes);
2119
2120                 buf += ecc_size;
2121                 ecc_calc += ecc_bytes;
2122                 oob_buf  += oob_bytes;
2123         }
2124
2125         /* copy calculated ECC for whole page to chip->buffer->oob */
2126         /* this include masked-value(0xFF) for unwritten subpages */
2127         ecc_calc = chip->buffers->ecccalc;
2128         for (i = 0; i < chip->ecc.total; i++)
2129                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2130
2131         /* write OOB buffer to NAND device */
2132         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2133
2134         return 0;
2135 }
2136
2137
2138 /**
2139  * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2140  * @mtd: mtd info structure
2141  * @chip: nand chip info structure
2142  * @buf: data buffer
2143  * @oob_required: must write chip->oob_poi to OOB
2144  *
2145  * The hw generator calculates the error syndrome automatically. Therefore we
2146  * need a special oob layout and handling.
2147  */
2148 static int nand_write_page_syndrome(struct mtd_info *mtd,
2149                                     struct nand_chip *chip,
2150                                     const uint8_t *buf, int oob_required)
2151 {
2152         int i, eccsize = chip->ecc.size;
2153         int eccbytes = chip->ecc.bytes;
2154         int eccsteps = chip->ecc.steps;
2155         const uint8_t *p = buf;
2156         uint8_t *oob = chip->oob_poi;
2157
2158         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2159
2160                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2161                 chip->write_buf(mtd, p, eccsize);
2162
2163                 if (chip->ecc.prepad) {
2164                         chip->write_buf(mtd, oob, chip->ecc.prepad);
2165                         oob += chip->ecc.prepad;
2166                 }
2167
2168                 chip->ecc.calculate(mtd, p, oob);
2169                 chip->write_buf(mtd, oob, eccbytes);
2170                 oob += eccbytes;
2171
2172                 if (chip->ecc.postpad) {
2173                         chip->write_buf(mtd, oob, chip->ecc.postpad);
2174                         oob += chip->ecc.postpad;
2175                 }
2176         }
2177
2178         /* Calculate remaining oob bytes */
2179         i = mtd->oobsize - (oob - chip->oob_poi);
2180         if (i)
2181                 chip->write_buf(mtd, oob, i);
2182
2183         return 0;
2184 }
2185
2186 /**
2187  * nand_write_page - [REPLACEABLE] write one page
2188  * @mtd: MTD device structure
2189  * @chip: NAND chip descriptor
2190  * @offset: address offset within the page
2191  * @data_len: length of actual data to be written
2192  * @buf: the data to write
2193  * @oob_required: must write chip->oob_poi to OOB
2194  * @page: page number to write
2195  * @cached: cached programming
2196  * @raw: use _raw version of write_page
2197  */
2198 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2199                 uint32_t offset, int data_len, const uint8_t *buf,
2200                 int oob_required, int page, int cached, int raw)
2201 {
2202         int status, subpage;
2203
2204         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2205                 chip->ecc.write_subpage)
2206                 subpage = offset || (data_len < mtd->writesize);
2207         else
2208                 subpage = 0;
2209
2210         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2211
2212         if (unlikely(raw))
2213                 status = chip->ecc.write_page_raw(mtd, chip, buf,
2214                                                         oob_required);
2215         else if (subpage)
2216                 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2217                                                          buf, oob_required);
2218         else
2219                 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2220
2221         if (status < 0)
2222                 return status;
2223
2224         /*
2225          * Cached progamming disabled for now. Not sure if it's worth the
2226          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2227          */
2228         cached = 0;
2229
2230         if (!cached || !NAND_HAS_CACHEPROG(chip)) {
2231
2232                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2233                 status = chip->waitfunc(mtd, chip);
2234                 /*
2235                  * See if operation failed and additional status checks are
2236                  * available.
2237                  */
2238                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2239                         status = chip->errstat(mtd, chip, FL_WRITING, status,
2240                                                page);
2241
2242                 if (status & NAND_STATUS_FAIL)
2243                         return -EIO;
2244         } else {
2245                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2246                 status = chip->waitfunc(mtd, chip);
2247         }
2248
2249         return 0;
2250 }
2251
2252 /**
2253  * nand_fill_oob - [INTERN] Transfer client buffer to oob
2254  * @mtd: MTD device structure
2255  * @oob: oob data buffer
2256  * @len: oob data write length
2257  * @ops: oob ops structure
2258  */
2259 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2260                               struct mtd_oob_ops *ops)
2261 {
2262         struct nand_chip *chip = mtd->priv;
2263
2264         /*
2265          * Initialise to all 0xFF, to avoid the possibility of left over OOB
2266          * data from a previous OOB read.
2267          */
2268         memset(chip->oob_poi, 0xff, mtd->oobsize);
2269
2270         switch (ops->mode) {
2271
2272         case MTD_OPS_PLACE_OOB:
2273         case MTD_OPS_RAW:
2274                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2275                 return oob + len;
2276
2277         case MTD_OPS_AUTO_OOB: {
2278                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2279                 uint32_t boffs = 0, woffs = ops->ooboffs;
2280                 size_t bytes = 0;
2281
2282                 for (; free->length && len; free++, len -= bytes) {
2283                         /* Write request not from offset 0? */
2284                         if (unlikely(woffs)) {
2285                                 if (woffs >= free->length) {
2286                                         woffs -= free->length;
2287                                         continue;
2288                                 }
2289                                 boffs = free->offset + woffs;
2290                                 bytes = min_t(size_t, len,
2291                                               (free->length - woffs));
2292                                 woffs = 0;
2293                         } else {
2294                                 bytes = min_t(size_t, len, free->length);
2295                                 boffs = free->offset;
2296                         }
2297                         memcpy(chip->oob_poi + boffs, oob, bytes);
2298                         oob += bytes;
2299                 }
2300                 return oob;
2301         }
2302         default:
2303                 BUG();
2304         }
2305         return NULL;
2306 }
2307
2308 #define NOTALIGNED(x)   ((x & (chip->subpagesize - 1)) != 0)
2309
2310 /**
2311  * nand_do_write_ops - [INTERN] NAND write with ECC
2312  * @mtd: MTD device structure
2313  * @to: offset to write to
2314  * @ops: oob operations description structure
2315  *
2316  * NAND write with ECC.
2317  */
2318 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2319                              struct mtd_oob_ops *ops)
2320 {
2321         int chipnr, realpage, page, blockmask, column;
2322         struct nand_chip *chip = mtd->priv;
2323         uint32_t writelen = ops->len;
2324
2325         uint32_t oobwritelen = ops->ooblen;
2326         uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
2327                                 mtd->oobavail : mtd->oobsize;
2328
2329         uint8_t *oob = ops->oobbuf;
2330         uint8_t *buf = ops->datbuf;
2331         int ret;
2332         int oob_required = oob ? 1 : 0;
2333
2334         ops->retlen = 0;
2335         if (!writelen)
2336                 return 0;
2337
2338         /* Reject writes, which are not page aligned */
2339         if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2340                 pr_notice("%s: attempt to write non page aligned data\n",
2341                            __func__);
2342                 return -EINVAL;
2343         }
2344
2345         column = to & (mtd->writesize - 1);
2346
2347         chipnr = (int)(to >> chip->chip_shift);
2348         chip->select_chip(mtd, chipnr);
2349
2350         /* Check, if it is write protected */
2351         if (nand_check_wp(mtd)) {
2352                 ret = -EIO;
2353                 goto err_out;
2354         }
2355
2356         realpage = (int)(to >> chip->page_shift);
2357         page = realpage & chip->pagemask;
2358         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2359
2360         /* Invalidate the page cache, when we write to the cached page */
2361         if (to <= (chip->pagebuf << chip->page_shift) &&
2362             (chip->pagebuf << chip->page_shift) < (to + ops->len))
2363                 chip->pagebuf = -1;
2364
2365         /* Don't allow multipage oob writes with offset */
2366         if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2367                 ret = -EINVAL;
2368                 goto err_out;
2369         }
2370
2371         while (1) {
2372                 int bytes = mtd->writesize;
2373                 int cached = writelen > bytes && page != blockmask;
2374                 uint8_t *wbuf = buf;
2375
2376                 /* Partial page write? */
2377                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2378                         cached = 0;
2379                         bytes = min_t(int, bytes - column, (int) writelen);
2380                         chip->pagebuf = -1;
2381                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
2382                         memcpy(&chip->buffers->databuf[column], buf, bytes);
2383                         wbuf = chip->buffers->databuf;
2384                 }
2385
2386                 if (unlikely(oob)) {
2387                         size_t len = min(oobwritelen, oobmaxlen);
2388                         oob = nand_fill_oob(mtd, oob, len, ops);
2389                         oobwritelen -= len;
2390                 } else {
2391                         /* We still need to erase leftover OOB data */
2392                         memset(chip->oob_poi, 0xff, mtd->oobsize);
2393                 }
2394                 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2395                                         oob_required, page, cached,
2396                                         (ops->mode == MTD_OPS_RAW));
2397                 if (ret)
2398                         break;
2399
2400                 writelen -= bytes;
2401                 if (!writelen)
2402                         break;
2403
2404                 column = 0;
2405                 buf += bytes;
2406                 realpage++;
2407
2408                 page = realpage & chip->pagemask;
2409                 /* Check, if we cross a chip boundary */
2410                 if (!page) {
2411                         chipnr++;
2412                         chip->select_chip(mtd, -1);
2413                         chip->select_chip(mtd, chipnr);
2414                 }
2415         }
2416
2417         ops->retlen = ops->len - writelen;
2418         if (unlikely(oob))
2419                 ops->oobretlen = ops->ooblen;
2420
2421 err_out:
2422         chip->select_chip(mtd, -1);
2423         return ret;
2424 }
2425
2426 /**
2427  * panic_nand_write - [MTD Interface] NAND write with ECC
2428  * @mtd: MTD device structure
2429  * @to: offset to write to
2430  * @len: number of bytes to write
2431  * @retlen: pointer to variable to store the number of written bytes
2432  * @buf: the data to write
2433  *
2434  * NAND write with ECC. Used when performing writes in interrupt context, this
2435  * may for example be called by mtdoops when writing an oops while in panic.
2436  */
2437 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2438                             size_t *retlen, const uint8_t *buf)
2439 {
2440         struct nand_chip *chip = mtd->priv;
2441         struct mtd_oob_ops ops;
2442         int ret;
2443
2444         /* Wait for the device to get ready */
2445         panic_nand_wait(mtd, chip, 400);
2446
2447         /* Grab the device */
2448         panic_nand_get_device(chip, mtd, FL_WRITING);
2449
2450         ops.len = len;
2451         ops.datbuf = (uint8_t *)buf;
2452         ops.oobbuf = NULL;
2453         ops.mode = MTD_OPS_PLACE_OOB;
2454
2455         ret = nand_do_write_ops(mtd, to, &ops);
2456
2457         *retlen = ops.retlen;
2458         return ret;
2459 }
2460
2461 /**
2462  * nand_write - [MTD Interface] NAND write with ECC
2463  * @mtd: MTD device structure
2464  * @to: offset to write to
2465  * @len: number of bytes to write
2466  * @retlen: pointer to variable to store the number of written bytes
2467  * @buf: the data to write
2468  *
2469  * NAND write with ECC.
2470  */
2471 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2472                           size_t *retlen, const uint8_t *buf)
2473 {
2474         struct mtd_oob_ops ops;
2475         int ret;
2476
2477         nand_get_device(mtd, FL_WRITING);
2478         ops.len = len;
2479         ops.datbuf = (uint8_t *)buf;
2480         ops.oobbuf = NULL;
2481         ops.mode = MTD_OPS_PLACE_OOB;
2482         ret = nand_do_write_ops(mtd, to, &ops);
2483         *retlen = ops.retlen;
2484         nand_release_device(mtd);
2485         return ret;
2486 }
2487
2488 /**
2489  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2490  * @mtd: MTD device structure
2491  * @to: offset to write to
2492  * @ops: oob operation description structure
2493  *
2494  * NAND write out-of-band.
2495  */
2496 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2497                              struct mtd_oob_ops *ops)
2498 {
2499         int chipnr, page, status, len;
2500         struct nand_chip *chip = mtd->priv;
2501
2502         pr_debug("%s: to = 0x%08x, len = %i\n",
2503                          __func__, (unsigned int)to, (int)ops->ooblen);
2504
2505         if (ops->mode == MTD_OPS_AUTO_OOB)
2506                 len = chip->ecc.layout->oobavail;
2507         else
2508                 len = mtd->oobsize;
2509
2510         /* Do not allow write past end of page */
2511         if ((ops->ooboffs + ops->ooblen) > len) {
2512                 pr_debug("%s: attempt to write past end of page\n",
2513                                 __func__);
2514                 return -EINVAL;
2515         }
2516
2517         if (unlikely(ops->ooboffs >= len)) {
2518                 pr_debug("%s: attempt to start write outside oob\n",
2519                                 __func__);
2520                 return -EINVAL;
2521         }
2522
2523         /* Do not allow write past end of device */
2524         if (unlikely(to >= mtd->size ||
2525                      ops->ooboffs + ops->ooblen >
2526                         ((mtd->size >> chip->page_shift) -
2527                          (to >> chip->page_shift)) * len)) {
2528                 pr_debug("%s: attempt to write beyond end of device\n",
2529                                 __func__);
2530                 return -EINVAL;
2531         }
2532
2533         chipnr = (int)(to >> chip->chip_shift);
2534         chip->select_chip(mtd, chipnr);
2535
2536         /* Shift to get page */
2537         page = (int)(to >> chip->page_shift);
2538
2539         /*
2540          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2541          * of my DiskOnChip 2000 test units) will clear the whole data page too
2542          * if we don't do this. I have no clue why, but I seem to have 'fixed'
2543          * it in the doc2000 driver in August 1999.  dwmw2.
2544          */
2545         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2546
2547         /* Check, if it is write protected */
2548         if (nand_check_wp(mtd)) {
2549                 chip->select_chip(mtd, -1);
2550                 return -EROFS;
2551         }
2552
2553         /* Invalidate the page cache, if we write to the cached page */
2554         if (page == chip->pagebuf)
2555                 chip->pagebuf = -1;
2556
2557         nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2558
2559         if (ops->mode == MTD_OPS_RAW)
2560                 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2561         else
2562                 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2563
2564         chip->select_chip(mtd, -1);
2565
2566         if (status)
2567                 return status;
2568
2569         ops->oobretlen = ops->ooblen;
2570
2571         return 0;
2572 }
2573
2574 /**
2575  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2576  * @mtd: MTD device structure
2577  * @to: offset to write to
2578  * @ops: oob operation description structure
2579  */
2580 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2581                           struct mtd_oob_ops *ops)
2582 {
2583         int ret = -ENOTSUPP;
2584
2585         ops->retlen = 0;
2586
2587         /* Do not allow writes past end of device */
2588         if (ops->datbuf && (to + ops->len) > mtd->size) {
2589                 pr_debug("%s: attempt to write beyond end of device\n",
2590                                 __func__);
2591                 return -EINVAL;
2592         }
2593
2594         nand_get_device(mtd, FL_WRITING);
2595
2596         switch (ops->mode) {
2597         case MTD_OPS_PLACE_OOB:
2598         case MTD_OPS_AUTO_OOB:
2599         case MTD_OPS_RAW:
2600                 break;
2601
2602         default:
2603                 goto out;
2604         }
2605
2606         if (!ops->datbuf)
2607                 ret = nand_do_write_oob(mtd, to, ops);
2608         else
2609                 ret = nand_do_write_ops(mtd, to, ops);
2610
2611 out:
2612         nand_release_device(mtd);
2613         return ret;
2614 }
2615
2616 /**
2617  * single_erase_cmd - [GENERIC] NAND standard block erase command function
2618  * @mtd: MTD device structure
2619  * @page: the page address of the block which will be erased
2620  *
2621  * Standard erase command for NAND chips.
2622  */
2623 static void single_erase_cmd(struct mtd_info *mtd, int page)
2624 {
2625         struct nand_chip *chip = mtd->priv;
2626         /* Send commands to erase a block */
2627         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2628         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2629 }
2630
2631 /**
2632  * nand_erase - [MTD Interface] erase block(s)
2633  * @mtd: MTD device structure
2634  * @instr: erase instruction
2635  *
2636  * Erase one ore more blocks.
2637  */
2638 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2639 {
2640         return nand_erase_nand(mtd, instr, 0);
2641 }
2642
2643 /**
2644  * nand_erase_nand - [INTERN] erase block(s)
2645  * @mtd: MTD device structure
2646  * @instr: erase instruction
2647  * @allowbbt: allow erasing the bbt area
2648  *
2649  * Erase one ore more blocks.
2650  */
2651 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2652                     int allowbbt)
2653 {
2654         int page, status, pages_per_block, ret, chipnr;
2655         struct nand_chip *chip = mtd->priv;
2656         loff_t len;
2657
2658         pr_debug("%s: start = 0x%012llx, len = %llu\n",
2659                         __func__, (unsigned long long)instr->addr,
2660                         (unsigned long long)instr->len);
2661
2662         if (check_offs_len(mtd, instr->addr, instr->len))
2663                 return -EINVAL;
2664
2665         /* Grab the lock and see if the device is available */
2666         nand_get_device(mtd, FL_ERASING);
2667
2668         /* Shift to get first page */
2669         page = (int)(instr->addr >> chip->page_shift);
2670         chipnr = (int)(instr->addr >> chip->chip_shift);
2671
2672         /* Calculate pages in each block */
2673         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2674
2675         /* Select the NAND device */
2676         chip->select_chip(mtd, chipnr);
2677
2678         /* Check, if it is write protected */
2679         if (nand_check_wp(mtd)) {
2680                 pr_debug("%s: device is write protected!\n",
2681                                 __func__);
2682                 instr->state = MTD_ERASE_FAILED;
2683                 goto erase_exit;
2684         }
2685
2686         /* Loop through the pages */
2687         len = instr->len;
2688
2689         instr->state = MTD_ERASING;
2690
2691         while (len) {
2692                 /* Check if we have a bad block, we do not erase bad blocks! */
2693                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2694                                         chip->page_shift, 0, allowbbt)) {
2695                         pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2696                                     __func__, page);
2697                         instr->state = MTD_ERASE_FAILED;
2698                         goto erase_exit;
2699                 }
2700
2701                 /*
2702                  * Invalidate the page cache, if we erase the block which
2703                  * contains the current cached page.
2704                  */
2705                 if (page <= chip->pagebuf && chip->pagebuf <
2706                     (page + pages_per_block))
2707                         chip->pagebuf = -1;
2708
2709                 chip->erase_cmd(mtd, page & chip->pagemask);
2710
2711                 status = chip->waitfunc(mtd, chip);
2712
2713                 /*
2714                  * See if operation failed and additional status checks are
2715                  * available
2716                  */
2717                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2718                         status = chip->errstat(mtd, chip, FL_ERASING,
2719                                                status, page);
2720
2721                 /* See if block erase succeeded */
2722                 if (status & NAND_STATUS_FAIL) {
2723                         pr_debug("%s: failed erase, page 0x%08x\n",
2724                                         __func__, page);
2725                         instr->state = MTD_ERASE_FAILED;
2726                         instr->fail_addr =
2727                                 ((loff_t)page << chip->page_shift);
2728                         goto erase_exit;
2729                 }
2730
2731                 /* Increment page address and decrement length */
2732                 len -= (1ULL << chip->phys_erase_shift);
2733                 page += pages_per_block;
2734
2735                 /* Check, if we cross a chip boundary */
2736                 if (len && !(page & chip->pagemask)) {
2737                         chipnr++;
2738                         chip->select_chip(mtd, -1);
2739                         chip->select_chip(mtd, chipnr);
2740                 }
2741         }
2742         instr->state = MTD_ERASE_DONE;
2743
2744 erase_exit:
2745
2746         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2747
2748         /* Deselect and wake up anyone waiting on the device */
2749         chip->select_chip(mtd, -1);
2750         nand_release_device(mtd);
2751
2752         /* Do call back function */
2753         if (!ret)
2754                 mtd_erase_callback(instr);
2755
2756         /* Return more or less happy */
2757         return ret;
2758 }
2759
2760 /**
2761  * nand_sync - [MTD Interface] sync
2762  * @mtd: MTD device structure
2763  *
2764  * Sync is actually a wait for chip ready function.
2765  */
2766 static void nand_sync(struct mtd_info *mtd)
2767 {
2768         pr_debug("%s: called\n", __func__);
2769
2770         /* Grab the lock and see if the device is available */
2771         nand_get_device(mtd, FL_SYNCING);
2772         /* Release it and go back */
2773         nand_release_device(mtd);
2774 }
2775
2776 /**
2777  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2778  * @mtd: MTD device structure
2779  * @offs: offset relative to mtd start
2780  */
2781 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2782 {
2783         return nand_block_checkbad(mtd, offs, 1, 0);
2784 }
2785
2786 /**
2787  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2788  * @mtd: MTD device structure
2789  * @ofs: offset relative to mtd start
2790  */
2791 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2792 {
2793         int ret;
2794
2795         ret = nand_block_isbad(mtd, ofs);
2796         if (ret) {
2797                 /* If it was bad already, return success and do nothing */
2798                 if (ret > 0)
2799                         return 0;
2800                 return ret;
2801         }
2802
2803         return nand_block_markbad_lowlevel(mtd, ofs);
2804 }
2805
2806 /**
2807  * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
2808  * @mtd: MTD device structure
2809  * @chip: nand chip info structure
2810  * @addr: feature address.
2811  * @subfeature_param: the subfeature parameters, a four bytes array.
2812  */
2813 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
2814                         int addr, uint8_t *subfeature_param)
2815 {
2816         int status;
2817         int i;
2818
2819         if (!chip->onfi_version ||
2820             !(le16_to_cpu(chip->onfi_params.opt_cmd)
2821               & ONFI_OPT_CMD_SET_GET_FEATURES))
2822                 return -EINVAL;
2823
2824         chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
2825         for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
2826                 chip->write_byte(mtd, subfeature_param[i]);
2827
2828         status = chip->waitfunc(mtd, chip);
2829         if (status & NAND_STATUS_FAIL)
2830                 return -EIO;
2831         return 0;
2832 }
2833
2834 /**
2835  * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
2836  * @mtd: MTD device structure
2837  * @chip: nand chip info structure
2838  * @addr: feature address.
2839  * @subfeature_param: the subfeature parameters, a four bytes array.
2840  */
2841 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
2842                         int addr, uint8_t *subfeature_param)
2843 {
2844         int i;
2845
2846         if (!chip->onfi_version ||
2847             !(le16_to_cpu(chip->onfi_params.opt_cmd)
2848               & ONFI_OPT_CMD_SET_GET_FEATURES))
2849                 return -EINVAL;
2850
2851         /* clear the sub feature parameters */
2852         memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
2853
2854         chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
2855         for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
2856                 *subfeature_param++ = chip->read_byte(mtd);
2857         return 0;
2858 }
2859
2860 /**
2861  * nand_suspend - [MTD Interface] Suspend the NAND flash
2862  * @mtd: MTD device structure
2863  */
2864 static int nand_suspend(struct mtd_info *mtd)
2865 {
2866         return nand_get_device(mtd, FL_PM_SUSPENDED);
2867 }
2868
2869 /**
2870  * nand_resume - [MTD Interface] Resume the NAND flash
2871  * @mtd: MTD device structure
2872  */
2873 static void nand_resume(struct mtd_info *mtd)
2874 {
2875         struct nand_chip *chip = mtd->priv;
2876
2877         if (chip->state == FL_PM_SUSPENDED)
2878                 nand_release_device(mtd);
2879         else
2880                 pr_err("%s called for a chip which is not in suspended state\n",
2881                         __func__);
2882 }
2883
2884 /* Set default functions */
2885 static void nand_set_defaults(struct nand_chip *chip, int busw)
2886 {
2887         /* check for proper chip_delay setup, set 20us if not */
2888         if (!chip->chip_delay)
2889                 chip->chip_delay = 20;
2890
2891         /* check, if a user supplied command function given */
2892         if (chip->cmdfunc == NULL)
2893                 chip->cmdfunc = nand_command;
2894
2895         /* check, if a user supplied wait function given */
2896         if (chip->waitfunc == NULL)
2897                 chip->waitfunc = nand_wait;
2898
2899         if (!chip->select_chip)
2900                 chip->select_chip = nand_select_chip;
2901
2902         /* set for ONFI nand */
2903         if (!chip->onfi_set_features)
2904                 chip->onfi_set_features = nand_onfi_set_features;
2905         if (!chip->onfi_get_features)
2906                 chip->onfi_get_features = nand_onfi_get_features;
2907
2908         /* If called twice, pointers that depend on busw may need to be reset */
2909         if (!chip->read_byte || chip->read_byte == nand_read_byte)
2910                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2911         if (!chip->read_word)
2912                 chip->read_word = nand_read_word;
2913         if (!chip->block_bad)
2914                 chip->block_bad = nand_block_bad;
2915         if (!chip->block_markbad)
2916                 chip->block_markbad = nand_default_block_markbad;
2917         if (!chip->write_buf || chip->write_buf == nand_write_buf)
2918                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2919         if (!chip->write_byte || chip->write_byte == nand_write_byte)
2920                 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
2921         if (!chip->read_buf || chip->read_buf == nand_read_buf)
2922                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2923         if (!chip->scan_bbt)
2924                 chip->scan_bbt = nand_default_bbt;
2925
2926         if (!chip->controller) {
2927                 chip->controller = &chip->hwcontrol;
2928                 spin_lock_init(&chip->controller->lock);
2929                 init_waitqueue_head(&chip->controller->wq);
2930         }
2931
2932 }
2933
2934 /* Sanitize ONFI strings so we can safely print them */
2935 static void sanitize_string(uint8_t *s, size_t len)
2936 {
2937         ssize_t i;
2938
2939         /* Null terminate */
2940         s[len - 1] = 0;
2941
2942         /* Remove non printable chars */
2943         for (i = 0; i < len - 1; i++) {
2944                 if (s[i] < ' ' || s[i] > 127)
2945                         s[i] = '?';
2946         }
2947
2948         /* Remove trailing spaces */
2949         strim(s);
2950 }
2951
2952 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2953 {
2954         int i;
2955         while (len--) {
2956                 crc ^= *p++ << 8;
2957                 for (i = 0; i < 8; i++)
2958                         crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2959         }
2960
2961         return crc;
2962 }
2963
2964 /* Parse the Extended Parameter Page. */
2965 static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
2966                 struct nand_chip *chip, struct nand_onfi_params *p)
2967 {
2968         struct onfi_ext_param_page *ep;
2969         struct onfi_ext_section *s;
2970         struct onfi_ext_ecc_info *ecc;
2971         uint8_t *cursor;
2972         int ret = -EINVAL;
2973         int len;
2974         int i;
2975
2976         len = le16_to_cpu(p->ext_param_page_length) * 16;
2977         ep = kmalloc(len, GFP_KERNEL);
2978         if (!ep)
2979                 return -ENOMEM;
2980
2981         /* Send our own NAND_CMD_PARAM. */
2982         chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2983
2984         /* Use the Change Read Column command to skip the ONFI param pages. */
2985         chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
2986                         sizeof(*p) * p->num_of_param_pages , -1);
2987
2988         /* Read out the Extended Parameter Page. */
2989         chip->read_buf(mtd, (uint8_t *)ep, len);
2990         if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
2991                 != le16_to_cpu(ep->crc))) {
2992                 pr_debug("fail in the CRC.\n");
2993                 goto ext_out;
2994         }
2995
2996         /*
2997          * Check the signature.
2998          * Do not strictly follow the ONFI spec, maybe changed in future.
2999          */
3000         if (strncmp(ep->sig, "EPPS", 4)) {
3001                 pr_debug("The signature is invalid.\n");
3002                 goto ext_out;
3003         }
3004
3005         /* find the ECC section. */
3006         cursor = (uint8_t *)(ep + 1);
3007         for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
3008                 s = ep->sections + i;
3009                 if (s->type == ONFI_SECTION_TYPE_2)
3010                         break;
3011                 cursor += s->length * 16;
3012         }
3013         if (i == ONFI_EXT_SECTION_MAX) {
3014                 pr_debug("We can not find the ECC section.\n");
3015                 goto ext_out;
3016         }
3017
3018         /* get the info we want. */
3019         ecc = (struct onfi_ext_ecc_info *)cursor;
3020
3021         if (!ecc->codeword_size) {
3022                 pr_debug("Invalid codeword size\n");
3023                 goto ext_out;
3024         }
3025
3026         chip->ecc_strength_ds = ecc->ecc_bits;
3027         chip->ecc_step_ds = 1 << ecc->codeword_size;
3028         ret = 0;
3029
3030 ext_out:
3031         kfree(ep);
3032         return ret;
3033 }
3034
3035 static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
3036 {
3037         struct nand_chip *chip = mtd->priv;
3038         uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
3039
3040         return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
3041                         feature);
3042 }
3043
3044 /*
3045  * Configure chip properties from Micron vendor-specific ONFI table
3046  */
3047 static void nand_onfi_detect_micron(struct nand_chip *chip,
3048                 struct nand_onfi_params *p)
3049 {
3050         struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
3051
3052         if (le16_to_cpu(p->vendor_revision) < 1)
3053                 return;
3054
3055         chip->read_retries = micron->read_retry_options;
3056         chip->setup_read_retry = nand_setup_read_retry_micron;
3057 }
3058
3059 /*
3060  * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3061  */
3062 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3063                                         int *busw)
3064 {
3065         struct nand_onfi_params *p = &chip->onfi_params;
3066         int i;
3067         int val;
3068
3069         /* Try ONFI for unknown chip or LP */
3070         chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
3071         if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
3072                 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
3073                 return 0;
3074
3075         /*
3076          * ONFI must be probed in 8-bit mode or with NAND_BUSWIDTH_AUTO, not
3077          * with NAND_BUSWIDTH_16
3078          */
3079         if (chip->options & NAND_BUSWIDTH_16) {
3080                 pr_err("ONFI cannot be probed in 16-bit mode; aborting\n");
3081                 return 0;
3082         }
3083
3084         chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3085         for (i = 0; i < 3; i++) {
3086                 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
3087                 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3088                                 le16_to_cpu(p->crc)) {
3089                         break;
3090                 }
3091         }
3092
3093         if (i == 3) {
3094                 pr_err("Could not find valid ONFI parameter page; aborting\n");
3095                 return 0;
3096         }
3097
3098         /* Check version */
3099         val = le16_to_cpu(p->revision);
3100         if (val & (1 << 5))
3101                 chip->onfi_version = 23;
3102         else if (val & (1 << 4))
3103                 chip->onfi_version = 22;
3104         else if (val & (1 << 3))
3105                 chip->onfi_version = 21;
3106         else if (val & (1 << 2))
3107                 chip->onfi_version = 20;
3108         else if (val & (1 << 1))
3109                 chip->onfi_version = 10;
3110
3111         if (!chip->onfi_version) {
3112                 pr_info("unsupported ONFI version: %d\n", val);
3113                 return 0;
3114         }
3115
3116         sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3117         sanitize_string(p->model, sizeof(p->model));
3118         if (!mtd->name)
3119                 mtd->name = p->model;
3120
3121         mtd->writesize = le32_to_cpu(p->byte_per_page);
3122
3123         /*
3124          * pages_per_block and blocks_per_lun may not be a power-of-2 size
3125          * (don't ask me who thought of this...). MTD assumes that these
3126          * dimensions will be power-of-2, so just truncate the remaining area.
3127          */
3128         mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3129         mtd->erasesize *= mtd->writesize;
3130
3131         mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3132
3133         /* See erasesize comment */
3134         chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3135         chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3136         chip->bits_per_cell = p->bits_per_cell;
3137
3138         if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
3139                 *busw = NAND_BUSWIDTH_16;
3140         else
3141                 *busw = 0;
3142
3143         if (p->ecc_bits != 0xff) {
3144                 chip->ecc_strength_ds = p->ecc_bits;
3145                 chip->ecc_step_ds = 512;
3146         } else if (chip->onfi_version >= 21 &&
3147                 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3148
3149                 /*
3150                  * The nand_flash_detect_ext_param_page() uses the
3151                  * Change Read Column command which maybe not supported
3152                  * by the chip->cmdfunc. So try to update the chip->cmdfunc
3153                  * now. We do not replace user supplied command function.
3154                  */
3155                 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3156                         chip->cmdfunc = nand_command_lp;
3157
3158                 /* The Extended Parameter Page is supported since ONFI 2.1. */
3159                 if (nand_flash_detect_ext_param_page(mtd, chip, p))
3160                         pr_warn("Failed to detect ONFI extended param page\n");
3161         } else {
3162                 pr_warn("Could not retrieve ONFI ECC requirements\n");
3163         }
3164
3165         if (p->jedec_id == NAND_MFR_MICRON)
3166                 nand_onfi_detect_micron(chip, p);
3167
3168         return 1;
3169 }
3170
3171 /*
3172  * nand_id_has_period - Check if an ID string has a given wraparound period
3173  * @id_data: the ID string
3174  * @arrlen: the length of the @id_data array
3175  * @period: the period of repitition
3176  *
3177  * Check if an ID string is repeated within a given sequence of bytes at
3178  * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3179  * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3180  * if the repetition has a period of @period; otherwise, returns zero.
3181  */
3182 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3183 {
3184         int i, j;
3185         for (i = 0; i < period; i++)
3186                 for (j = i + period; j < arrlen; j += period)
3187                         if (id_data[i] != id_data[j])
3188                                 return 0;
3189         return 1;
3190 }
3191
3192 /*
3193  * nand_id_len - Get the length of an ID string returned by CMD_READID
3194  * @id_data: the ID string
3195  * @arrlen: the length of the @id_data array
3196
3197  * Returns the length of the ID string, according to known wraparound/trailing
3198  * zero patterns. If no pattern exists, returns the length of the array.
3199  */
3200 static int nand_id_len(u8 *id_data, int arrlen)
3201 {
3202         int last_nonzero, period;
3203
3204         /* Find last non-zero byte */
3205         for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3206                 if (id_data[last_nonzero])
3207                         break;
3208
3209         /* All zeros */
3210         if (last_nonzero < 0)
3211                 return 0;
3212
3213         /* Calculate wraparound period */
3214         for (period = 1; period < arrlen; period++)
3215                 if (nand_id_has_period(id_data, arrlen, period))
3216                         break;
3217
3218         /* There's a repeated pattern */
3219         if (period < arrlen)
3220                 return period;
3221
3222         /* There are trailing zeros */
3223         if (last_nonzero < arrlen - 1)
3224                 return last_nonzero + 1;
3225
3226         /* No pattern detected */
3227         return arrlen;
3228 }
3229
3230 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3231 static int nand_get_bits_per_cell(u8 cellinfo)
3232 {
3233         int bits;
3234
3235         bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3236         bits >>= NAND_CI_CELLTYPE_SHIFT;
3237         return bits + 1;
3238 }
3239
3240 /*
3241  * Many new NAND share similar device ID codes, which represent the size of the
3242  * chip. The rest of the parameters must be decoded according to generic or
3243  * manufacturer-specific "extended ID" decoding patterns.
3244  */
3245 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3246                                 u8 id_data[8], int *busw)
3247 {
3248         int extid, id_len;
3249         /* The 3rd id byte holds MLC / multichip data */
3250         chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3251         /* The 4th id byte is the important one */
3252         extid = id_data[3];
3253
3254         id_len = nand_id_len(id_data, 8);
3255
3256         /*
3257          * Field definitions are in the following datasheets:
3258          * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3259          * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3260          * Hynix MLC   (6 byte ID): Hynix H27UBG8T2B (p.22)
3261          *
3262          * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3263          * ID to decide what to do.
3264          */
3265         if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
3266                         !nand_is_slc(chip) && id_data[5] != 0x00) {
3267                 /* Calc pagesize */
3268                 mtd->writesize = 2048 << (extid & 0x03);
3269                 extid >>= 2;
3270                 /* Calc oobsize */
3271                 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3272                 case 1:
3273                         mtd->oobsize = 128;
3274                         break;
3275                 case 2:
3276                         mtd->oobsize = 218;
3277                         break;
3278                 case 3:
3279                         mtd->oobsize = 400;
3280                         break;
3281                 case 4:
3282                         mtd->oobsize = 436;
3283                         break;
3284                 case 5:
3285                         mtd->oobsize = 512;
3286                         break;
3287                 case 6:
3288                         mtd->oobsize = 640;
3289                         break;
3290                 case 7:
3291                 default: /* Other cases are "reserved" (unknown) */
3292                         mtd->oobsize = 1024;
3293                         break;
3294                 }
3295                 extid >>= 2;
3296                 /* Calc blocksize */
3297                 mtd->erasesize = (128 * 1024) <<
3298                         (((extid >> 1) & 0x04) | (extid & 0x03));
3299                 *busw = 0;
3300         } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3301                         !nand_is_slc(chip)) {
3302                 unsigned int tmp;
3303
3304                 /* Calc pagesize */
3305                 mtd->writesize = 2048 << (extid & 0x03);
3306                 extid >>= 2;
3307                 /* Calc oobsize */
3308                 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3309                 case 0:
3310                         mtd->oobsize = 128;
3311                         break;
3312                 case 1:
3313                         mtd->oobsize = 224;
3314                         break;
3315                 case 2:
3316                         mtd->oobsize = 448;
3317                         break;
3318                 case 3:
3319                         mtd->oobsize = 64;
3320                         break;
3321                 case 4:
3322                         mtd->oobsize = 32;
3323                         break;
3324                 case 5:
3325                         mtd->oobsize = 16;
3326                         break;
3327                 default:
3328                         mtd->oobsize = 640;
3329                         break;
3330                 }
3331                 extid >>= 2;
3332                 /* Calc blocksize */
3333                 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3334                 if (tmp < 0x03)
3335                         mtd->erasesize = (128 * 1024) << tmp;
3336                 else if (tmp == 0x03)
3337                         mtd->erasesize = 768 * 1024;
3338                 else
3339                         mtd->erasesize = (64 * 1024) << tmp;
3340                 *busw = 0;
3341         } else {
3342                 /* Calc pagesize */
3343                 mtd->writesize = 1024 << (extid & 0x03);
3344                 extid >>= 2;
3345                 /* Calc oobsize */
3346                 mtd->oobsize = (8 << (extid & 0x01)) *
3347                         (mtd->writesize >> 9);
3348                 extid >>= 2;
3349                 /* Calc blocksize. Blocksize is multiples of 64KiB */
3350                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3351                 extid >>= 2;
3352                 /* Get buswidth information */
3353                 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3354
3355                 /*
3356                  * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3357                  * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3358                  * follows:
3359                  * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3360                  *                         110b -> 24nm
3361                  * - ID byte 5, bit[7]:    1 -> BENAND, 0 -> raw SLC
3362                  */
3363                 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
3364                                 nand_is_slc(chip) &&
3365                                 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3366                                 !(id_data[4] & 0x80) /* !BENAND */) {
3367                         mtd->oobsize = 32 * mtd->writesize >> 9;
3368                 }
3369
3370         }
3371 }
3372
3373 /*
3374  * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3375  * decodes a matching ID table entry and assigns the MTD size parameters for
3376  * the chip.
3377  */
3378 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3379                                 struct nand_flash_dev *type, u8 id_data[8],
3380                                 int *busw)
3381 {
3382         int maf_id = id_data[0];
3383
3384         mtd->erasesize = type->erasesize;
3385         mtd->writesize = type->pagesize;
3386         mtd->oobsize = mtd->writesize / 32;
3387         *busw = type->options & NAND_BUSWIDTH_16;
3388
3389         /* All legacy ID NAND are small-page, SLC */
3390         chip->bits_per_cell = 1;
3391
3392         /*
3393          * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3394          * some Spansion chips have erasesize that conflicts with size
3395          * listed in nand_ids table.
3396          * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3397          */
3398         if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3399                         && id_data[6] == 0x00 && id_data[7] == 0x00
3400                         && mtd->writesize == 512) {
3401                 mtd->erasesize = 128 * 1024;
3402                 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3403         }
3404 }
3405
3406 /*
3407  * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3408  * heuristic patterns using various detected parameters (e.g., manufacturer,
3409  * page size, cell-type information).
3410  */
3411 static void nand_decode_bbm_options(struct mtd_info *mtd,
3412                                     struct nand_chip *chip, u8 id_data[8])
3413 {
3414         int maf_id = id_data[0];
3415
3416         /* Set the bad block position */
3417         if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3418                 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3419         else
3420                 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3421
3422         /*
3423          * Bad block marker is stored in the last page of each block on Samsung
3424          * and Hynix MLC devices; stored in first two pages of each block on
3425          * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3426          * AMD/Spansion, and Macronix.  All others scan only the first page.
3427          */
3428         if (!nand_is_slc(chip) &&
3429                         (maf_id == NAND_MFR_SAMSUNG ||
3430                          maf_id == NAND_MFR_HYNIX))
3431                 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3432         else if ((nand_is_slc(chip) &&
3433                                 (maf_id == NAND_MFR_SAMSUNG ||
3434                                  maf_id == NAND_MFR_HYNIX ||
3435                                  maf_id == NAND_MFR_TOSHIBA ||
3436                                  maf_id == NAND_MFR_AMD ||
3437                                  maf_id == NAND_MFR_MACRONIX)) ||
3438                         (mtd->writesize == 2048 &&
3439                          maf_id == NAND_MFR_MICRON))
3440                 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3441 }
3442
3443 static inline bool is_full_id_nand(struct nand_flash_dev *type)
3444 {
3445         return type->id_len;
3446 }
3447
3448 static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3449                    struct nand_flash_dev *type, u8 *id_data, int *busw)
3450 {
3451         if (!strncmp(type->id, id_data, type->id_len)) {
3452                 mtd->writesize = type->pagesize;
3453                 mtd->erasesize = type->erasesize;
3454                 mtd->oobsize = type->oobsize;
3455
3456                 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3457                 chip->chipsize = (uint64_t)type->chipsize << 20;
3458                 chip->options |= type->options;
3459                 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3460                 chip->ecc_step_ds = NAND_ECC_STEP(type);
3461
3462                 *busw = type->options & NAND_BUSWIDTH_16;
3463
3464                 if (!mtd->name)
3465                         mtd->name = type->name;
3466
3467                 return true;
3468         }
3469         return false;
3470 }
3471
3472 /*
3473  * Get the flash and manufacturer id and lookup if the type is supported.
3474  */
3475 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
3476                                                   struct nand_chip *chip,
3477                                                   int busw,
3478                                                   int *maf_id, int *dev_id,
3479                                                   struct nand_flash_dev *type)
3480 {
3481         int i, maf_idx;
3482         u8 id_data[8];
3483
3484         /* Select the device */
3485         chip->select_chip(mtd, 0);
3486
3487         /*
3488          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3489          * after power-up.
3490          */
3491         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3492
3493         /* Send the command for reading device ID */
3494         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3495
3496         /* Read manufacturer and device IDs */
3497         *maf_id = chip->read_byte(mtd);
3498         *dev_id = chip->read_byte(mtd);
3499
3500         /*
3501          * Try again to make sure, as some systems the bus-hold or other
3502          * interface concerns can cause random data which looks like a
3503          * possibly credible NAND flash to appear. If the two results do
3504          * not match, ignore the device completely.
3505          */
3506
3507         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3508
3509         /* Read entire ID string */
3510         for (i = 0; i < 8; i++)
3511                 id_data[i] = chip->read_byte(mtd);
3512
3513         if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
3514                 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
3515                         *maf_id, *dev_id, id_data[0], id_data[1]);
3516                 return ERR_PTR(-ENODEV);
3517         }
3518
3519         if (!type)
3520                 type = nand_flash_ids;
3521
3522         for (; type->name != NULL; type++) {
3523                 if (is_full_id_nand(type)) {
3524                         if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3525                                 goto ident_done;
3526                 } else if (*dev_id == type->dev_id) {
3527                                 break;
3528                 }
3529         }
3530
3531         chip->onfi_version = 0;
3532         if (!type->name || !type->pagesize) {
3533                 /* Check is chip is ONFI compliant */
3534                 if (nand_flash_detect_onfi(mtd, chip, &busw))
3535                         goto ident_done;
3536         }
3537
3538         if (!type->name)
3539                 return ERR_PTR(-ENODEV);
3540
3541         if (!mtd->name)
3542                 mtd->name = type->name;
3543
3544         chip->chipsize = (uint64_t)type->chipsize << 20;
3545
3546         if (!type->pagesize && chip->init_size) {
3547                 /* Set the pagesize, oobsize, erasesize by the driver */
3548                 busw = chip->init_size(mtd, chip, id_data);
3549         } else if (!type->pagesize) {
3550                 /* Decode parameters from extended ID */
3551                 nand_decode_ext_id(mtd, chip, id_data, &busw);
3552         } else {
3553                 nand_decode_id(mtd, chip, type, id_data, &busw);
3554         }
3555         /* Get chip options */
3556         chip->options |= type->options;
3557
3558         /*
3559          * Check if chip is not a Samsung device. Do not clear the
3560          * options for chips which do not have an extended id.
3561          */
3562         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3563                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3564 ident_done:
3565
3566         /* Try to identify manufacturer */
3567         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3568                 if (nand_manuf_ids[maf_idx].id == *maf_id)
3569                         break;
3570         }
3571
3572         if (chip->options & NAND_BUSWIDTH_AUTO) {
3573                 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3574                 chip->options |= busw;
3575                 nand_set_defaults(chip, busw);
3576         } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3577                 /*
3578                  * Check, if buswidth is correct. Hardware drivers should set
3579                  * chip correct!
3580                  */
3581                 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3582                         *maf_id, *dev_id);
3583                 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
3584                 pr_warn("bus width %d instead %d bit\n",
3585                            (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3586                            busw ? 16 : 8);
3587                 return ERR_PTR(-EINVAL);
3588         }
3589
3590         nand_decode_bbm_options(mtd, chip, id_data);
3591
3592         /* Calculate the address shift from the page size */
3593         chip->page_shift = ffs(mtd->writesize) - 1;
3594         /* Convert chipsize to number of pages per chip -1 */
3595         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3596
3597         chip->bbt_erase_shift = chip->phys_erase_shift =
3598                 ffs(mtd->erasesize) - 1;
3599         if (chip->chipsize & 0xffffffff)
3600                 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3601         else {
3602                 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3603                 chip->chip_shift += 32 - 1;
3604         }
3605
3606         chip->badblockbits = 8;
3607         chip->erase_cmd = single_erase_cmd;
3608
3609         /* Do not replace user supplied command function! */
3610         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3611                 chip->cmdfunc = nand_command_lp;
3612
3613         pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3614                 *maf_id, *dev_id);
3615         pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3616                 chip->onfi_version ? chip->onfi_params.model : type->name);
3617         pr_info("%dMiB, %s, page size: %d, OOB size: %d\n",
3618                 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
3619                 mtd->writesize, mtd->oobsize);
3620         return type;
3621 }
3622
3623 /**
3624  * nand_scan_ident - [NAND Interface] Scan for the NAND device
3625  * @mtd: MTD device structure
3626  * @maxchips: number of chips to scan for
3627  * @table: alternative NAND ID table
3628  *
3629  * This is the first phase of the normal nand_scan() function. It reads the
3630  * flash ID and sets up MTD fields accordingly.
3631  *
3632  * The mtd->owner field must be set to the module of the caller.
3633  */
3634 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3635                     struct nand_flash_dev *table)
3636 {
3637         int i, busw, nand_maf_id, nand_dev_id;
3638         struct nand_chip *chip = mtd->priv;
3639         struct nand_flash_dev *type;
3640
3641         /* Get buswidth to select the correct functions */
3642         busw = chip->options & NAND_BUSWIDTH_16;
3643         /* Set the default functions */
3644         nand_set_defaults(chip, busw);
3645
3646         /* Read the flash type */
3647         type = nand_get_flash_type(mtd, chip, busw,
3648                                 &nand_maf_id, &nand_dev_id, table);
3649
3650         if (IS_ERR(type)) {
3651                 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3652                         pr_warn("No NAND device found\n");
3653                 chip->select_chip(mtd, -1);
3654                 return PTR_ERR(type);
3655         }
3656
3657         chip->select_chip(mtd, -1);
3658
3659         /* Check for a chip array */
3660         for (i = 1; i < maxchips; i++) {
3661                 chip->select_chip(mtd, i);
3662                 /* See comment in nand_get_flash_type for reset */
3663                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3664                 /* Send the command for reading device ID */
3665                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3666                 /* Read manufacturer and device IDs */
3667                 if (nand_maf_id != chip->read_byte(mtd) ||
3668                     nand_dev_id != chip->read_byte(mtd)) {
3669                         chip->select_chip(mtd, -1);
3670                         break;
3671                 }
3672                 chip->select_chip(mtd, -1);
3673         }
3674         if (i > 1)
3675                 pr_info("%d chips detected\n", i);
3676
3677         /* Store the number of chips and calc total size for mtd */
3678         chip->numchips = i;
3679         mtd->size = i * chip->chipsize;
3680
3681         return 0;
3682 }
3683 EXPORT_SYMBOL(nand_scan_ident);
3684
3685
3686 /**
3687  * nand_scan_tail - [NAND Interface] Scan for the NAND device
3688  * @mtd: MTD device structure
3689  *
3690  * This is the second phase of the normal nand_scan() function. It fills out
3691  * all the uninitialized function pointers with the defaults and scans for a
3692  * bad block table if appropriate.
3693  */
3694 int nand_scan_tail(struct mtd_info *mtd)
3695 {
3696         int i;
3697         struct nand_chip *chip = mtd->priv;
3698         struct nand_ecc_ctrl *ecc = &chip->ecc;
3699
3700         /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3701         BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3702                         !(chip->bbt_options & NAND_BBT_USE_FLASH));
3703
3704         if (!(chip->options & NAND_OWN_BUFFERS))
3705                 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3706         if (!chip->buffers)
3707                 return -ENOMEM;
3708
3709         /* Set the internal oob buffer location, just after the page data */
3710         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3711
3712         /*
3713          * If no default placement scheme is given, select an appropriate one.
3714          */
3715         if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
3716                 switch (mtd->oobsize) {
3717                 case 8:
3718                         ecc->layout = &nand_oob_8;
3719                         break;
3720                 case 16:
3721                         ecc->layout = &nand_oob_16;
3722                         break;
3723                 case 64:
3724                         ecc->layout = &nand_oob_64;
3725                         break;
3726                 case 128:
3727                         ecc->layout = &nand_oob_128;
3728                         break;
3729                 default:
3730                         pr_warn("No oob scheme defined for oobsize %d\n",
3731                                    mtd->oobsize);
3732                         BUG();
3733                 }
3734         }
3735
3736         if (!chip->write_page)
3737                 chip->write_page = nand_write_page;
3738
3739         /*
3740          * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3741          * selected and we have 256 byte pagesize fallback to software ECC
3742          */
3743
3744         switch (ecc->mode) {
3745         case NAND_ECC_HW_OOB_FIRST:
3746                 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3747                 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
3748                         pr_warn("No ECC functions supplied; "
3749                                    "hardware ECC not possible\n");
3750                         BUG();
3751                 }
3752                 if (!ecc->read_page)
3753                         ecc->read_page = nand_read_page_hwecc_oob_first;
3754
3755         case NAND_ECC_HW:
3756                 /* Use standard hwecc read page function? */
3757                 if (!ecc->read_page)
3758                         ecc->read_page = nand_read_page_hwecc;
3759                 if (!ecc->write_page)
3760                         ecc->write_page = nand_write_page_hwecc;
3761                 if (!ecc->read_page_raw)
3762                         ecc->read_page_raw = nand_read_page_raw;
3763                 if (!ecc->write_page_raw)
3764                         ecc->write_page_raw = nand_write_page_raw;
3765                 if (!ecc->read_oob)
3766                         ecc->read_oob = nand_read_oob_std;
3767                 if (!ecc->write_oob)
3768                         ecc->write_oob = nand_write_oob_std;
3769                 if (!ecc->read_subpage)
3770                         ecc->read_subpage = nand_read_subpage;
3771                 if (!ecc->write_subpage)
3772                         ecc->write_subpage = nand_write_subpage_hwecc;
3773
3774         case NAND_ECC_HW_SYNDROME:
3775                 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
3776                     (!ecc->read_page ||
3777                      ecc->read_page == nand_read_page_hwecc ||
3778                      !ecc->write_page ||
3779                      ecc->write_page == nand_write_page_hwecc)) {
3780                         pr_warn("No ECC functions supplied; "
3781                                    "hardware ECC not possible\n");
3782                         BUG();
3783                 }
3784                 /* Use standard syndrome read/write page function? */
3785                 if (!ecc->read_page)
3786                         ecc->read_page = nand_read_page_syndrome;
3787                 if (!ecc->write_page)
3788                         ecc->write_page = nand_write_page_syndrome;
3789                 if (!ecc->read_page_raw)
3790                         ecc->read_page_raw = nand_read_page_raw_syndrome;
3791                 if (!ecc->write_page_raw)
3792                         ecc->write_page_raw = nand_write_page_raw_syndrome;
3793                 if (!ecc->read_oob)
3794                         ecc->read_oob = nand_read_oob_syndrome;
3795                 if (!ecc->write_oob)
3796                         ecc->write_oob = nand_write_oob_syndrome;
3797
3798                 if (mtd->writesize >= ecc->size) {
3799                         if (!ecc->strength) {
3800                                 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
3801                                 BUG();
3802                         }
3803                         break;
3804                 }
3805                 pr_warn("%d byte HW ECC not possible on "
3806                            "%d byte page size, fallback to SW ECC\n",
3807                            ecc->size, mtd->writesize);
3808                 ecc->mode = NAND_ECC_SOFT;
3809
3810         case NAND_ECC_SOFT:
3811                 ecc->calculate = nand_calculate_ecc;
3812                 ecc->correct = nand_correct_data;
3813                 ecc->read_page = nand_read_page_swecc;
3814                 ecc->read_subpage = nand_read_subpage;
3815                 ecc->write_page = nand_write_page_swecc;
3816                 ecc->read_page_raw = nand_read_page_raw;
3817                 ecc->write_page_raw = nand_write_page_raw;
3818                 ecc->read_oob = nand_read_oob_std;
3819                 ecc->write_oob = nand_write_oob_std;
3820                 if (!ecc->size)
3821                         ecc->size = 256;
3822                 ecc->bytes = 3;
3823                 ecc->strength = 1;
3824                 break;
3825
3826         case NAND_ECC_SOFT_BCH:
3827                 if (!mtd_nand_has_bch()) {
3828                         pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
3829                         BUG();
3830                 }
3831                 ecc->calculate = nand_bch_calculate_ecc;
3832                 ecc->correct = nand_bch_correct_data;
3833                 ecc->read_page = nand_read_page_swecc;
3834                 ecc->read_subpage = nand_read_subpage;
3835                 ecc->write_page = nand_write_page_swecc;
3836                 ecc->read_page_raw = nand_read_page_raw;
3837                 ecc->write_page_raw = nand_write_page_raw;
3838                 ecc->read_oob = nand_read_oob_std;
3839                 ecc->write_oob = nand_write_oob_std;
3840                 /*
3841                  * Board driver should supply ecc.size and ecc.bytes values to
3842                  * select how many bits are correctable; see nand_bch_init()
3843                  * for details. Otherwise, default to 4 bits for large page
3844                  * devices.
3845                  */
3846                 if (!ecc->size && (mtd->oobsize >= 64)) {
3847                         ecc->size = 512;
3848                         ecc->bytes = 7;
3849                 }
3850                 ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes,
3851                                                &ecc->layout);
3852                 if (!ecc->priv) {
3853                         pr_warn("BCH ECC initialization failed!\n");
3854                         BUG();
3855                 }
3856                 ecc->strength = ecc->bytes * 8 / fls(8 * ecc->size);
3857                 break;
3858
3859         case NAND_ECC_NONE:
3860                 pr_warn("NAND_ECC_NONE selected by board driver. "
3861                            "This is not recommended!\n");
3862                 ecc->read_page = nand_read_page_raw;
3863                 ecc->write_page = nand_write_page_raw;
3864                 ecc->read_oob = nand_read_oob_std;
3865                 ecc->read_page_raw = nand_read_page_raw;
3866                 ecc->write_page_raw = nand_write_page_raw;
3867                 ecc->write_oob = nand_write_oob_std;
3868                 ecc->size = mtd->writesize;
3869                 ecc->bytes = 0;
3870                 ecc->strength = 0;
3871                 break;
3872
3873         default:
3874                 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode);
3875                 BUG();
3876         }
3877
3878         /* For many systems, the standard OOB write also works for raw */
3879         if (!ecc->read_oob_raw)
3880                 ecc->read_oob_raw = ecc->read_oob;
3881         if (!ecc->write_oob_raw)
3882                 ecc->write_oob_raw = ecc->write_oob;
3883
3884         /*
3885          * The number of bytes available for a client to place data into
3886          * the out of band area.
3887          */
3888         ecc->layout->oobavail = 0;
3889         for (i = 0; ecc->layout->oobfree[i].length
3890                         && i < ARRAY_SIZE(ecc->layout->oobfree); i++)
3891                 ecc->layout->oobavail += ecc->layout->oobfree[i].length;
3892         mtd->oobavail = ecc->layout->oobavail;
3893
3894         /*
3895          * Set the number of read / write steps for one page depending on ECC
3896          * mode.
3897          */
3898         ecc->steps = mtd->writesize / ecc->size;
3899         if (ecc->steps * ecc->size != mtd->writesize) {
3900                 pr_warn("Invalid ECC parameters\n");
3901                 BUG();
3902         }
3903         ecc->total = ecc->steps * ecc->bytes;
3904
3905         /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
3906         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
3907                 switch (ecc->steps) {
3908                 case 2:
3909                         mtd->subpage_sft = 1;
3910                         break;
3911                 case 4:
3912                 case 8:
3913                 case 16:
3914                         mtd->subpage_sft = 2;
3915                         break;
3916                 }
3917         }
3918         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3919
3920         /* Initialize state */
3921         chip->state = FL_READY;
3922
3923         /* Invalidate the pagebuffer reference */
3924         chip->pagebuf = -1;
3925
3926         /* Large page NAND with SOFT_ECC should support subpage reads */
3927         if ((ecc->mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
3928                 chip->options |= NAND_SUBPAGE_READ;
3929
3930         /* Fill in remaining MTD driver data */
3931         mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
3932         mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3933                                                 MTD_CAP_NANDFLASH;
3934         mtd->_erase = nand_erase;
3935         mtd->_point = NULL;
3936         mtd->_unpoint = NULL;
3937         mtd->_read = nand_read;
3938         mtd->_write = nand_write;
3939         mtd->_panic_write = panic_nand_write;
3940         mtd->_read_oob = nand_read_oob;
3941         mtd->_write_oob = nand_write_oob;
3942         mtd->_sync = nand_sync;
3943         mtd->_lock = NULL;
3944         mtd->_unlock = NULL;
3945         mtd->_suspend = nand_suspend;
3946         mtd->_resume = nand_resume;
3947         mtd->_block_isbad = nand_block_isbad;
3948         mtd->_block_markbad = nand_block_markbad;
3949         mtd->writebufsize = mtd->writesize;
3950
3951         /* propagate ecc info to mtd_info */
3952         mtd->ecclayout = ecc->layout;
3953         mtd->ecc_strength = ecc->strength;
3954         mtd->ecc_step_size = ecc->size;
3955         /*
3956          * Initialize bitflip_threshold to its default prior scan_bbt() call.
3957          * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
3958          * properly set.
3959          */
3960         if (!mtd->bitflip_threshold)
3961                 mtd->bitflip_threshold = mtd->ecc_strength;
3962
3963         /* Check, if we should skip the bad block table scan */
3964         if (chip->options & NAND_SKIP_BBTSCAN)
3965                 return 0;
3966
3967         /* Build bad block table */
3968         return chip->scan_bbt(mtd);
3969 }
3970 EXPORT_SYMBOL(nand_scan_tail);
3971
3972 /*
3973  * is_module_text_address() isn't exported, and it's mostly a pointless
3974  * test if this is a module _anyway_ -- they'd have to try _really_ hard
3975  * to call us from in-kernel code if the core NAND support is modular.
3976  */
3977 #ifdef MODULE
3978 #define caller_is_module() (1)
3979 #else
3980 #define caller_is_module() \
3981         is_module_text_address((unsigned long)__builtin_return_address(0))
3982 #endif
3983
3984 /**
3985  * nand_scan - [NAND Interface] Scan for the NAND device
3986  * @mtd: MTD device structure
3987  * @maxchips: number of chips to scan for
3988  *
3989  * This fills out all the uninitialized function pointers with the defaults.
3990  * The flash ID is read and the mtd/chip structures are filled with the
3991  * appropriate values. The mtd->owner field must be set to the module of the
3992  * caller.
3993  */
3994 int nand_scan(struct mtd_info *mtd, int maxchips)
3995 {
3996         int ret;
3997
3998         /* Many callers got this wrong, so check for it for a while... */
3999         if (!mtd->owner && caller_is_module()) {
4000                 pr_crit("%s called with NULL mtd->owner!\n", __func__);
4001                 BUG();
4002         }
4003
4004         ret = nand_scan_ident(mtd, maxchips, NULL);
4005         if (!ret)
4006                 ret = nand_scan_tail(mtd);
4007         return ret;
4008 }
4009 EXPORT_SYMBOL(nand_scan);
4010
4011 /**
4012  * nand_release - [NAND Interface] Free resources held by the NAND device
4013  * @mtd: MTD device structure
4014  */
4015 void nand_release(struct mtd_info *mtd)
4016 {
4017         struct nand_chip *chip = mtd->priv;
4018
4019         if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
4020                 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
4021
4022         mtd_device_unregister(mtd);
4023
4024         /* Free bad block table memory */
4025         kfree(chip->bbt);
4026         if (!(chip->options & NAND_OWN_BUFFERS))
4027                 kfree(chip->buffers);
4028
4029         /* Free bad block descriptor memory */
4030         if (chip->badblock_pattern && chip->badblock_pattern->options
4031                         & NAND_BBT_DYNAMICSTRUCT)
4032                 kfree(chip->badblock_pattern);
4033 }
4034 EXPORT_SYMBOL_GPL(nand_release);
4035
4036 static int __init nand_base_init(void)
4037 {
4038         led_trigger_register_simple("nand-disk", &nand_led_trigger);
4039         return 0;
4040 }
4041
4042 static void __exit nand_base_exit(void)
4043 {
4044         led_trigger_unregister_simple(nand_led_trigger);
4045 }
4046
4047 module_init(nand_base_init);
4048 module_exit(nand_base_exit);
4049
4050 MODULE_LICENSE("GPL");
4051 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4052 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4053 MODULE_DESCRIPTION("Generic NAND flash driver code");