drivers/mtd/nand/omap2.c

   1 /*
   2  * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
   3  * Copyright © 2004 Micron Technology Inc.
   4  * Copyright © 2004 David Brownell
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/platform_device.h>
  12 #include <linux/dmaengine.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/delay.h>
  15 #include <linux/module.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/jiffies.h>
  18 #include <linux/sched.h>
  19 #include <linux/mtd/mtd.h>
  20 #include <linux/mtd/nand.h>
  21 #include <linux/mtd/partitions.h>
  22 #include <linux/omap-dma.h>
  23 #include <linux/io.h>
  24 #include <linux/slab.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27
  28 #include <linux/mtd/nand_bch.h>
  29 #include <linux/platform_data/elm.h>
  30
  31 #include <linux/platform_data/mtd-nand-omap2.h>
  32
  33 #define DRIVER_NAME     "omap2-nand"
  34 #define OMAP_NAND_TIMEOUT_MS    5000
  35
  36 #define NAND_Ecc_P1e            (1 << 0)
  37 #define NAND_Ecc_P2e            (1 << 1)
  38 #define NAND_Ecc_P4e            (1 << 2)
  39 #define NAND_Ecc_P8e            (1 << 3)
  40 #define NAND_Ecc_P16e           (1 << 4)
  41 #define NAND_Ecc_P32e           (1 << 5)
  42 #define NAND_Ecc_P64e           (1 << 6)
  43 #define NAND_Ecc_P128e          (1 << 7)
  44 #define NAND_Ecc_P256e          (1 << 8)
  45 #define NAND_Ecc_P512e          (1 << 9)
  46 #define NAND_Ecc_P1024e         (1 << 10)
  47 #define NAND_Ecc_P2048e         (1 << 11)
  48
  49 #define NAND_Ecc_P1o            (1 << 16)
  50 #define NAND_Ecc_P2o            (1 << 17)
  51 #define NAND_Ecc_P4o            (1 << 18)
  52 #define NAND_Ecc_P8o            (1 << 19)
  53 #define NAND_Ecc_P16o           (1 << 20)
  54 #define NAND_Ecc_P32o           (1 << 21)
  55 #define NAND_Ecc_P64o           (1 << 22)
  56 #define NAND_Ecc_P128o          (1 << 23)
  57 #define NAND_Ecc_P256o          (1 << 24)
  58 #define NAND_Ecc_P512o          (1 << 25)
  59 #define NAND_Ecc_P1024o         (1 << 26)
  60 #define NAND_Ecc_P2048o         (1 << 27)
  61
  62 #define TF(value)       (value ? 1 : 0)
  63
  64 #define P2048e(a)       (TF(a & NAND_Ecc_P2048e)        << 0)
  65 #define P2048o(a)       (TF(a & NAND_Ecc_P2048o)        << 1)
  66 #define P1e(a)          (TF(a & NAND_Ecc_P1e)           << 2)
  67 #define P1o(a)          (TF(a & NAND_Ecc_P1o)           << 3)
  68 #define P2e(a)          (TF(a & NAND_Ecc_P2e)           << 4)
  69 #define P2o(a)          (TF(a & NAND_Ecc_P2o)           << 5)
  70 #define P4e(a)          (TF(a & NAND_Ecc_P4e)           << 6)
  71 #define P4o(a)          (TF(a & NAND_Ecc_P4o)           << 7)
  72
  73 #define P8e(a)          (TF(a & NAND_Ecc_P8e)           << 0)
  74 #define P8o(a)          (TF(a & NAND_Ecc_P8o)           << 1)
  75 #define P16e(a)         (TF(a & NAND_Ecc_P16e)          << 2)
  76 #define P16o(a)         (TF(a & NAND_Ecc_P16o)          << 3)
  77 #define P32e(a)         (TF(a & NAND_Ecc_P32e)          << 4)
  78 #define P32o(a)         (TF(a & NAND_Ecc_P32o)          << 5)
  79 #define P64e(a)         (TF(a & NAND_Ecc_P64e)          << 6)
  80 #define P64o(a)         (TF(a & NAND_Ecc_P64o)          << 7)
  81
  82 #define P128e(a)        (TF(a & NAND_Ecc_P128e)         << 0)
  83 #define P128o(a)        (TF(a & NAND_Ecc_P128o)         << 1)
  84 #define P256e(a)        (TF(a & NAND_Ecc_P256e)         << 2)
  85 #define P256o(a)        (TF(a & NAND_Ecc_P256o)         << 3)
  86 #define P512e(a)        (TF(a & NAND_Ecc_P512e)         << 4)
  87 #define P512o(a)        (TF(a & NAND_Ecc_P512o)         << 5)
  88 #define P1024e(a)       (TF(a & NAND_Ecc_P1024e)        << 6)
  89 #define P1024o(a)       (TF(a & NAND_Ecc_P1024o)        << 7)
  90
  91 #define P8e_s(a)        (TF(a & NAND_Ecc_P8e)           << 0)
  92 #define P8o_s(a)        (TF(a & NAND_Ecc_P8o)           << 1)
  93 #define P16e_s(a)       (TF(a & NAND_Ecc_P16e)          << 2)
  94 #define P16o_s(a)       (TF(a & NAND_Ecc_P16o)          << 3)
  95 #define P1e_s(a)        (TF(a & NAND_Ecc_P1e)           << 4)
  96 #define P1o_s(a)        (TF(a & NAND_Ecc_P1o)           << 5)
  97 #define P2e_s(a)        (TF(a & NAND_Ecc_P2e)           << 6)
  98 #define P2o_s(a)        (TF(a & NAND_Ecc_P2o)           << 7)
  99
 100 #define P4e_s(a)        (TF(a & NAND_Ecc_P4e)           << 0)
 101 #define P4o_s(a)        (TF(a & NAND_Ecc_P4o)           << 1)
 102
 103 #define PREFETCH_CONFIG1_CS_SHIFT       24
 104 #define ECC_CONFIG_CS_SHIFT             1
 105 #define CS_MASK                         0x7
 106 #define ENABLE_PREFETCH                 (0x1 << 7)
 107 #define DMA_MPU_MODE_SHIFT              2
 108 #define ECCSIZE0_SHIFT                  12
 109 #define ECCSIZE1_SHIFT                  22
 110 #define ECC1RESULTSIZE                  0x1
 111 #define ECCCLEAR                        0x100
 112 #define ECC1                            0x1
 113 #define PREFETCH_FIFOTHRESHOLD_MAX      0x40
 114 #define PREFETCH_FIFOTHRESHOLD(val)     ((val) << 8)
 115 #define PREFETCH_STATUS_COUNT(val)      (val & 0x00003fff)
 116 #define PREFETCH_STATUS_FIFO_CNT(val)   ((val >> 24) & 0x7F)
 117 #define STATUS_BUFF_EMPTY               0x00000001
 118
 119 #define OMAP24XX_DMA_GPMC               4
 120
 121 #define SECTOR_BYTES            512
 122 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
 123 #define BCH4_BIT_PAD            4
 124
 125 /* GPMC ecc engine settings for read */
 126 #define BCH_WRAPMODE_1          1       /* BCH wrap mode 1 */
 127 #define BCH8R_ECC_SIZE0         0x1a    /* ecc_size0 = 26 */
 128 #define BCH8R_ECC_SIZE1         0x2     /* ecc_size1 = 2 */
 129 #define BCH4R_ECC_SIZE0         0xd     /* ecc_size0 = 13 */
 130 #define BCH4R_ECC_SIZE1         0x3     /* ecc_size1 = 3 */
 131
 132 /* GPMC ecc engine settings for write */
 133 #define BCH_WRAPMODE_6          6       /* BCH wrap mode 6 */
 134 #define BCH_ECC_SIZE0           0x0     /* ecc_size0 = 0, no oob protection */
 135 #define BCH_ECC_SIZE1           0x20    /* ecc_size1 = 32 */
 136
 137 #define BADBLOCK_MARKER_LENGTH          2
 138
 139 static u_char bch16_vector[] = {0xf5, 0x24, 0x1c, 0xd0, 0x61, 0xb3, 0xf1, 0x55,
 140                                 0x2e, 0x2c, 0x86, 0xa3, 0xed, 0x36, 0x1b, 0x78,
 141                                 0x48, 0x76, 0xa9, 0x3b, 0x97, 0xd1, 0x7a, 0x93,
 142                                 0x07, 0x0e};
 143 static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,
 144         0xac, 0x6b, 0xff, 0x99, 0x7b};
 145 static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10};
 146
 147 /* Shared among all NAND instances to synchronize access to the ECC Engine */
 148 static struct nand_hw_control omap_gpmc_controller = {
 149         .lock = __SPIN_LOCK_UNLOCKED(omap_gpmc_controller.lock),
 150         .wq = __WAIT_QUEUE_HEAD_INITIALIZER(omap_gpmc_controller.wq),
 151 };
 152
 153 struct omap_nand_info {
 154         struct omap_nand_platform_data  *pdata;
 155         struct mtd_info                 mtd;
 156         struct nand_chip                nand;
 157         struct platform_device          *pdev;
 158
 159         int                             gpmc_cs;
 160         unsigned long                   phys_base;
 161         enum omap_ecc                   ecc_opt;
 162         struct completion               comp;
 163         struct dma_chan                 *dma;
 164         int                             gpmc_irq_fifo;
 165         int                             gpmc_irq_count;
 166         enum {
 167                 OMAP_NAND_IO_READ = 0,  /* read */
 168                 OMAP_NAND_IO_WRITE,     /* write */
 169         } iomode;
 170         u_char                          *buf;
 171         int                                     buf_len;
 172         struct gpmc_nand_regs           reg;
 173         /* generated at runtime depending on ECC algorithm and layout selected */
 174         struct nand_ecclayout           oobinfo;
 175         /* fields specific for BCHx_HW ECC scheme */
 176         struct device                   *elm_dev;
 177         struct device_node              *of_node;
 178 };
 179
 180 /**
 181  * omap_prefetch_enable - configures and starts prefetch transfer
 182  * @cs: cs (chip select) number
 183  * @fifo_th: fifo threshold to be used for read/ write
 184  * @dma_mode: dma mode enable (1) or disable (0)
 185  * @u32_count: number of bytes to be transferred
 186  * @is_write: prefetch read(0) or write post(1) mode
 187  */
 188 static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode,
 189         unsigned int u32_count, int is_write, struct omap_nand_info *info)
 190 {
 191         u32 val;
 192
 193         if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
 194                 return -1;
 195
 196         if (readl(info->reg.gpmc_prefetch_control))
 197                 return -EBUSY;
 198
 199         /* Set the amount of bytes to be prefetched */
 200         writel(u32_count, info->reg.gpmc_prefetch_config2);
 201
 202         /* Set dma/mpu mode, the prefetch read / post write and
 203          * enable the engine. Set which cs is has requested for.
 204          */
 205         val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) |
 206                 PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH |
 207                 (dma_mode << DMA_MPU_MODE_SHIFT) | (0x1 & is_write));
 208         writel(val, info->reg.gpmc_prefetch_config1);
 209
 210         /*  Start the prefetch engine */
 211         writel(0x1, info->reg.gpmc_prefetch_control);
 212
 213         return 0;
 214 }
 215
 216 /**
 217  * omap_prefetch_reset - disables and stops the prefetch engine
 218  */
 219 static int omap_prefetch_reset(int cs, struct omap_nand_info *info)
 220 {
 221         u32 config1;
 222
 223         /* check if the same module/cs is trying to reset */
 224         config1 = readl(info->reg.gpmc_prefetch_config1);
 225         if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs)
 226                 return -EINVAL;
 227
 228         /* Stop the PFPW engine */
 229         writel(0x0, info->reg.gpmc_prefetch_control);
 230
 231         /* Reset/disable the PFPW engine */
 232         writel(0x0, info->reg.gpmc_prefetch_config1);
 233
 234         return 0;
 235 }
 236
 237 /**
 238  * omap_hwcontrol - hardware specific access to control-lines
 239  * @mtd: MTD device structure
 240  * @cmd: command to device
 241  * @ctrl:
 242  * NAND_NCE: bit 0 -> don't care
 243  * NAND_CLE: bit 1 -> Command Latch
 244  * NAND_ALE: bit 2 -> Address Latch
 245  *
 246  * NOTE: boards may use different bits for these!!
 247  */
 248 static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 249 {
 250         struct omap_nand_info *info = container_of(mtd,
 251                                         struct omap_nand_info, mtd);
 252
 253         if (cmd != NAND_CMD_NONE) {
 254                 if (ctrl & NAND_CLE)
 255                         writeb(cmd, info->reg.gpmc_nand_command);
 256
 257                 else if (ctrl & NAND_ALE)
 258                         writeb(cmd, info->reg.gpmc_nand_address);
 259
 260                 else /* NAND_NCE */
 261                         writeb(cmd, info->reg.gpmc_nand_data);
 262         }
 263 }
 264
 265 /**
 266  * omap_read_buf8 - read data from NAND controller into buffer
 267  * @mtd: MTD device structure
 268  * @buf: buffer to store date
 269  * @len: number of bytes to read
 270  */
 271 static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
 272 {
 273         struct nand_chip *nand = mtd->priv;
 274
 275         ioread8_rep(nand->IO_ADDR_R, buf, len);
 276 }
 277
 278 /**
 279  * omap_write_buf8 - write buffer to NAND controller
 280  * @mtd: MTD device structure
 281  * @buf: data buffer
 282  * @len: number of bytes to write
 283  */
 284 static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
 285 {
 286         struct omap_nand_info *info = container_of(mtd,
 287                                                 struct omap_nand_info, mtd);
 288         u_char *p = (u_char *)buf;
 289         u32     status = 0;
 290
 291         while (len--) {
 292                 iowrite8(*p++, info->nand.IO_ADDR_W);
 293                 /* wait until buffer is available for write */
 294                 do {
 295                         status = readl(info->reg.gpmc_status) &
 296                                         STATUS_BUFF_EMPTY;
 297                 } while (!status);
 298         }
 299 }
 300
 301 /**
 302  * omap_read_buf16 - read data from NAND controller into buffer
 303  * @mtd: MTD device structure
 304  * @buf: buffer to store date
 305  * @len: number of bytes to read
 306  */
 307 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
 308 {
 309         struct nand_chip *nand = mtd->priv;
 310
 311         ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
 312 }
 313
 314 /**
 315  * omap_write_buf16 - write buffer to NAND controller
 316  * @mtd: MTD device structure
 317  * @buf: data buffer
 318  * @len: number of bytes to write
 319  */
 320 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
 321 {
 322         struct omap_nand_info *info = container_of(mtd,
 323                                                 struct omap_nand_info, mtd);
 324         u16 *p = (u16 *) buf;
 325         u32     status = 0;
 326         /* FIXME try bursts of writesw() or DMA ... */
 327         len >>= 1;
 328
 329         while (len--) {
 330                 iowrite16(*p++, info->nand.IO_ADDR_W);
 331                 /* wait until buffer is available for write */
 332                 do {
 333                         status = readl(info->reg.gpmc_status) &
 334                                         STATUS_BUFF_EMPTY;
 335                 } while (!status);
 336         }
 337 }
 338
 339 /**
 340  * omap_read_buf_pref - read data from NAND controller into buffer
 341  * @mtd: MTD device structure
 342  * @buf: buffer to store date
 343  * @len: number of bytes to read
 344  */
 345 static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
 346 {
 347         struct omap_nand_info *info = container_of(mtd,
 348                                                 struct omap_nand_info, mtd);
 349         uint32_t r_count = 0;
 350         int ret = 0;
 351         u32 *p = (u32 *)buf;
 352
 353         /* take care of subpage reads */
 354         if (len % 4) {
 355                 if (info->nand.options & NAND_BUSWIDTH_16)
 356                         omap_read_buf16(mtd, buf, len % 4);
 357                 else
 358                         omap_read_buf8(mtd, buf, len % 4);
 359                 p = (u32 *) (buf + len % 4);
 360                 len -= len % 4;
 361         }
 362
 363         /* configure and start prefetch transfer */
 364         ret = omap_prefetch_enable(info->gpmc_cs,
 365                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info);
 366         if (ret) {
 367                 /* PFPW engine is busy, use cpu copy method */
 368                 if (info->nand.options & NAND_BUSWIDTH_16)
 369                         omap_read_buf16(mtd, (u_char *)p, len);
 370                 else
 371                         omap_read_buf8(mtd, (u_char *)p, len);
 372         } else {
 373                 do {
 374                         r_count = readl(info->reg.gpmc_prefetch_status);
 375                         r_count = PREFETCH_STATUS_FIFO_CNT(r_count);
 376                         r_count = r_count >> 2;
 377                         ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
 378                         p += r_count;
 379                         len -= r_count << 2;
 380                 } while (len);
 381                 /* disable and stop the PFPW engine */
 382                 omap_prefetch_reset(info->gpmc_cs, info);
 383         }
 384 }
 385
 386 /**
 387  * omap_write_buf_pref - write buffer to NAND controller
 388  * @mtd: MTD device structure
 389  * @buf: data buffer
 390  * @len: number of bytes to write
 391  */
 392 static void omap_write_buf_pref(struct mtd_info *mtd,
 393                                         const u_char *buf, int len)
 394 {
 395         struct omap_nand_info *info = container_of(mtd,
 396                                                 struct omap_nand_info, mtd);
 397         uint32_t w_count = 0;
 398         int i = 0, ret = 0;
 399         u16 *p = (u16 *)buf;
 400         unsigned long tim, limit;
 401         u32 val;
 402
 403         /* take care of subpage writes */
 404         if (len % 2 != 0) {
 405                 writeb(*buf, info->nand.IO_ADDR_W);
 406                 p = (u16 *)(buf + 1);
 407                 len--;
 408         }
 409
 410         /*  configure and start prefetch transfer */
 411         ret = omap_prefetch_enable(info->gpmc_cs,
 412                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info);
 413         if (ret) {
 414                 /* PFPW engine is busy, use cpu copy method */
 415                 if (info->nand.options & NAND_BUSWIDTH_16)
 416                         omap_write_buf16(mtd, (u_char *)p, len);
 417                 else
 418                         omap_write_buf8(mtd, (u_char *)p, len);
 419         } else {
 420                 while (len) {
 421                         w_count = readl(info->reg.gpmc_prefetch_status);
 422                         w_count = PREFETCH_STATUS_FIFO_CNT(w_count);
 423                         w_count = w_count >> 1;
 424                         for (i = 0; (i < w_count) && len; i++, len -= 2)
 425                                 iowrite16(*p++, info->nand.IO_ADDR_W);
 426                 }
 427                 /* wait for data to flushed-out before reset the prefetch */
 428                 tim = 0;
 429                 limit = (loops_per_jiffy *
 430                                         msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 431                 do {
 432                         cpu_relax();
 433                         val = readl(info->reg.gpmc_prefetch_status);
 434                         val = PREFETCH_STATUS_COUNT(val);
 435                 } while (val && (tim++ < limit));
 436
 437                 /* disable and stop the PFPW engine */
 438                 omap_prefetch_reset(info->gpmc_cs, info);
 439         }
 440 }
 441
 442 /*
 443  * omap_nand_dma_callback: callback on the completion of dma transfer
 444  * @data: pointer to completion data structure
 445  */
 446 static void omap_nand_dma_callback(void *data)
 447 {
 448         complete((struct completion *) data);
 449 }
 450
 451 /*
 452  * omap_nand_dma_transfer: configure and start dma transfer
 453  * @mtd: MTD device structure
 454  * @addr: virtual address in RAM of source/destination
 455  * @len: number of data bytes to be transferred
 456  * @is_write: flag for read/write operation
 457  */
 458 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
 459                                         unsigned int len, int is_write)
 460 {
 461         struct omap_nand_info *info = container_of(mtd,
 462                                         struct omap_nand_info, mtd);
 463         struct dma_async_tx_descriptor *tx;
 464         enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
 465                                                         DMA_FROM_DEVICE;
 466         struct scatterlist sg;
 467         unsigned long tim, limit;
 468         unsigned n;
 469         int ret;
 470         u32 val;
 471
 472         if (addr >= high_memory) {
 473                 struct page *p1;
 474
 475                 if (((size_t)addr & PAGE_MASK) !=
 476                         ((size_t)(addr + len - 1) & PAGE_MASK))
 477                         goto out_copy;
 478                 p1 = vmalloc_to_page(addr);
 479                 if (!p1)
 480                         goto out_copy;
 481                 addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK);
 482         }
 483
 484         sg_init_one(&sg, addr, len);
 485         n = dma_map_sg(info->dma->device->dev, &sg, 1, dir);
 486         if (n == 0) {
 487                 dev_err(&info->pdev->dev,
 488                         "Couldn't DMA map a %d byte buffer\n", len);
 489                 goto out_copy;
 490         }
 491
 492         tx = dmaengine_prep_slave_sg(info->dma, &sg, n,
 493                 is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
 494                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 495         if (!tx)
 496                 goto out_copy_unmap;
 497
 498         tx->callback = omap_nand_dma_callback;
 499         tx->callback_param = &info->comp;
 500         dmaengine_submit(tx);
 501
 502         /*  configure and start prefetch transfer */
 503         ret = omap_prefetch_enable(info->gpmc_cs,
 504                 PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info);
 505         if (ret)
 506                 /* PFPW engine is busy, use cpu copy method */
 507                 goto out_copy_unmap;
 508
 509         init_completion(&info->comp);
 510         dma_async_issue_pending(info->dma);
 511
 512         /* setup and start DMA using dma_addr */
 513         wait_for_completion(&info->comp);
 514         tim = 0;
 515         limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 516
 517         do {
 518                 cpu_relax();
 519                 val = readl(info->reg.gpmc_prefetch_status);
 520                 val = PREFETCH_STATUS_COUNT(val);
 521         } while (val && (tim++ < limit));
 522
 523         /* disable and stop the PFPW engine */
 524         omap_prefetch_reset(info->gpmc_cs, info);
 525
 526         dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
 527         return 0;
 528
 529 out_copy_unmap:
 530         dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
 531 out_copy:
 532         if (info->nand.options & NAND_BUSWIDTH_16)
 533                 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
 534                         : omap_write_buf16(mtd, (u_char *) addr, len);
 535         else
 536                 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
 537                         : omap_write_buf8(mtd, (u_char *) addr, len);
 538         return 0;
 539 }
 540
 541 /**
 542  * omap_read_buf_dma_pref - read data from NAND controller into buffer
 543  * @mtd: MTD device structure
 544  * @buf: buffer to store date
 545  * @len: number of bytes to read
 546  */
 547 static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
 548 {
 549         if (len <= mtd->oobsize)
 550                 omap_read_buf_pref(mtd, buf, len);
 551         else
 552                 /* start transfer in DMA mode */
 553                 omap_nand_dma_transfer(mtd, buf, len, 0x0);
 554 }
 555
 556 /**
 557  * omap_write_buf_dma_pref - write buffer to NAND controller
 558  * @mtd: MTD device structure
 559  * @buf: data buffer
 560  * @len: number of bytes to write
 561  */
 562 static void omap_write_buf_dma_pref(struct mtd_info *mtd,
 563                                         const u_char *buf, int len)
 564 {
 565         if (len <= mtd->oobsize)
 566                 omap_write_buf_pref(mtd, buf, len);
 567         else
 568                 /* start transfer in DMA mode */
 569                 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
 570 }
 571
 572 /*
 573  * omap_nand_irq - GPMC irq handler
 574  * @this_irq: gpmc irq number
 575  * @dev: omap_nand_info structure pointer is passed here
 576  */
 577 static irqreturn_t omap_nand_irq(int this_irq, void *dev)
 578 {
 579         struct omap_nand_info *info = (struct omap_nand_info *) dev;
 580         u32 bytes;
 581
 582         bytes = readl(info->reg.gpmc_prefetch_status);
 583         bytes = PREFETCH_STATUS_FIFO_CNT(bytes);
 584         bytes = bytes  & 0xFFFC; /* io in multiple of 4 bytes */
 585         if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
 586                 if (this_irq == info->gpmc_irq_count)
 587                         goto done;
 588
 589                 if (info->buf_len && (info->buf_len < bytes))
 590                         bytes = info->buf_len;
 591                 else if (!info->buf_len)
 592                         bytes = 0;
 593                 iowrite32_rep(info->nand.IO_ADDR_W,
 594                                                 (u32 *)info->buf, bytes >> 2);
 595                 info->buf = info->buf + bytes;
 596                 info->buf_len -= bytes;
 597
 598         } else {
 599                 ioread32_rep(info->nand.IO_ADDR_R,
 600                                                 (u32 *)info->buf, bytes >> 2);
 601                 info->buf = info->buf + bytes;
 602
 603                 if (this_irq == info->gpmc_irq_count)
 604                         goto done;
 605         }
 606
 607         return IRQ_HANDLED;
 608
 609 done:
 610         complete(&info->comp);
 611
 612         disable_irq_nosync(info->gpmc_irq_fifo);
 613         disable_irq_nosync(info->gpmc_irq_count);
 614
 615         return IRQ_HANDLED;
 616 }
 617
 618 /*
 619  * omap_read_buf_irq_pref - read data from NAND controller into buffer
 620  * @mtd: MTD device structure
 621  * @buf: buffer to store date
 622  * @len: number of bytes to read
 623  */
 624 static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
 625 {
 626         struct omap_nand_info *info = container_of(mtd,
 627                                                 struct omap_nand_info, mtd);
 628         int ret = 0;
 629
 630         if (len <= mtd->oobsize) {
 631                 omap_read_buf_pref(mtd, buf, len);
 632                 return;
 633         }
 634
 635         info->iomode = OMAP_NAND_IO_READ;
 636         info->buf = buf;
 637         init_completion(&info->comp);
 638
 639         /*  configure and start prefetch transfer */
 640         ret = omap_prefetch_enable(info->gpmc_cs,
 641                         PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info);
 642         if (ret)
 643                 /* PFPW engine is busy, use cpu copy method */
 644                 goto out_copy;
 645
 646         info->buf_len = len;
 647
 648         enable_irq(info->gpmc_irq_count);
 649         enable_irq(info->gpmc_irq_fifo);
 650
 651         /* waiting for read to complete */
 652         wait_for_completion(&info->comp);
 653
 654         /* disable and stop the PFPW engine */
 655         omap_prefetch_reset(info->gpmc_cs, info);
 656         return;
 657
 658 out_copy:
 659         if (info->nand.options & NAND_BUSWIDTH_16)
 660                 omap_read_buf16(mtd, buf, len);
 661         else
 662                 omap_read_buf8(mtd, buf, len);
 663 }
 664
 665 /*
 666  * omap_write_buf_irq_pref - write buffer to NAND controller
 667  * @mtd: MTD device structure
 668  * @buf: data buffer
 669  * @len: number of bytes to write
 670  */
 671 static void omap_write_buf_irq_pref(struct mtd_info *mtd,
 672                                         const u_char *buf, int len)
 673 {
 674         struct omap_nand_info *info = container_of(mtd,
 675                                                 struct omap_nand_info, mtd);
 676         int ret = 0;
 677         unsigned long tim, limit;
 678         u32 val;
 679
 680         if (len <= mtd->oobsize) {
 681                 omap_write_buf_pref(mtd, buf, len);
 682                 return;
 683         }
 684
 685         info->iomode = OMAP_NAND_IO_WRITE;
 686         info->buf = (u_char *) buf;
 687         init_completion(&info->comp);
 688
 689         /* configure and start prefetch transfer : size=24 */
 690         ret = omap_prefetch_enable(info->gpmc_cs,
 691                 (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info);
 692         if (ret)
 693                 /* PFPW engine is busy, use cpu copy method */
 694                 goto out_copy;
 695
 696         info->buf_len = len;
 697
 698         enable_irq(info->gpmc_irq_count);
 699         enable_irq(info->gpmc_irq_fifo);
 700
 701         /* waiting for write to complete */
 702         wait_for_completion(&info->comp);
 703
 704         /* wait for data to flushed-out before reset the prefetch */
 705         tim = 0;
 706         limit = (loops_per_jiffy *  msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 707         do {
 708                 val = readl(info->reg.gpmc_prefetch_status);
 709                 val = PREFETCH_STATUS_COUNT(val);
 710                 cpu_relax();
 711         } while (val && (tim++ < limit));
 712
 713         /* disable and stop the PFPW engine */
 714         omap_prefetch_reset(info->gpmc_cs, info);
 715         return;
 716
 717 out_copy:
 718         if (info->nand.options & NAND_BUSWIDTH_16)
 719                 omap_write_buf16(mtd, buf, len);
 720         else
 721                 omap_write_buf8(mtd, buf, len);
 722 }
 723
 724 /**
 725  * gen_true_ecc - This function will generate true ECC value
 726  * @ecc_buf: buffer to store ecc code
 727  *
 728  * This generated true ECC value can be used when correcting
 729  * data read from NAND flash memory core
 730  */
 731 static void gen_true_ecc(u8 *ecc_buf)
 732 {
 733         u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
 734                 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
 735
 736         ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
 737                         P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
 738         ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
 739                         P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
 740         ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
 741                         P1e(tmp) | P2048o(tmp) | P2048e(tmp));
 742 }
 743
 744 /**
 745  * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
 746  * @ecc_data1:  ecc code from nand spare area
 747  * @ecc_data2:  ecc code from hardware register obtained from hardware ecc
 748  * @page_data:  page data
 749  *
 750  * This function compares two ECC's and indicates if there is an error.
 751  * If the error can be corrected it will be corrected to the buffer.
 752  * If there is no error, %0 is returned. If there is an error but it
 753  * was corrected, %1 is returned. Otherwise, %-1 is returned.
 754  */
 755 static int omap_compare_ecc(u8 *ecc_data1,      /* read from NAND memory */
 756                             u8 *ecc_data2,      /* read from register */
 757                             u8 *page_data)
 758 {
 759         uint    i;
 760         u8      tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
 761         u8      comp0_bit[8], comp1_bit[8], comp2_bit[8];
 762         u8      ecc_bit[24];
 763         u8      ecc_sum = 0;
 764         u8      find_bit = 0;
 765         uint    find_byte = 0;
 766         int     isEccFF;
 767
 768         isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
 769
 770         gen_true_ecc(ecc_data1);
 771         gen_true_ecc(ecc_data2);
 772
 773         for (i = 0; i <= 2; i++) {
 774                 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
 775                 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
 776         }
 777
 778         for (i = 0; i < 8; i++) {
 779                 tmp0_bit[i]     = *ecc_data1 % 2;
 780                 *ecc_data1      = *ecc_data1 / 2;
 781         }
 782
 783         for (i = 0; i < 8; i++) {
 784                 tmp1_bit[i]      = *(ecc_data1 + 1) % 2;
 785                 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
 786         }
 787
 788         for (i = 0; i < 8; i++) {
 789                 tmp2_bit[i]      = *(ecc_data1 + 2) % 2;
 790                 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
 791         }
 792
 793         for (i = 0; i < 8; i++) {
 794                 comp0_bit[i]     = *ecc_data2 % 2;
 795                 *ecc_data2       = *ecc_data2 / 2;
 796         }
 797
 798         for (i = 0; i < 8; i++) {
 799                 comp1_bit[i]     = *(ecc_data2 + 1) % 2;
 800                 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
 801         }
 802
 803         for (i = 0; i < 8; i++) {
 804                 comp2_bit[i]     = *(ecc_data2 + 2) % 2;
 805                 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
 806         }
 807
 808         for (i = 0; i < 6; i++)
 809                 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
 810
 811         for (i = 0; i < 8; i++)
 812                 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
 813
 814         for (i = 0; i < 8; i++)
 815                 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
 816
 817         ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
 818         ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
 819
 820         for (i = 0; i < 24; i++)
 821                 ecc_sum += ecc_bit[i];
 822
 823         switch (ecc_sum) {
 824         case 0:
 825                 /* Not reached because this function is not called if
 826                  *  ECC values are equal
 827                  */
 828                 return 0;
 829
 830         case 1:
 831                 /* Uncorrectable error */
 832                 pr_debug("ECC UNCORRECTED_ERROR 1\n");
 833                 return -1;
 834
 835         case 11:
 836                 /* UN-Correctable error */
 837                 pr_debug("ECC UNCORRECTED_ERROR B\n");
 838                 return -1;
 839
 840         case 12:
 841                 /* Correctable error */
 842                 find_byte = (ecc_bit[23] << 8) +
 843                             (ecc_bit[21] << 7) +
 844                             (ecc_bit[19] << 6) +
 845                             (ecc_bit[17] << 5) +
 846                             (ecc_bit[15] << 4) +
 847                             (ecc_bit[13] << 3) +
 848                             (ecc_bit[11] << 2) +
 849                             (ecc_bit[9]  << 1) +
 850                             ecc_bit[7];
 851
 852                 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
 853
 854                 pr_debug("Correcting single bit ECC error at offset: "
 855                                 "%d, bit: %d\n", find_byte, find_bit);
 856
 857                 page_data[find_byte] ^= (1 << find_bit);
 858
 859                 return 1;
 860         default:
 861                 if (isEccFF) {
 862                         if (ecc_data2[0] == 0 &&
 863                             ecc_data2[1] == 0 &&
 864                             ecc_data2[2] == 0)
 865                                 return 0;
 866                 }
 867                 pr_debug("UNCORRECTED_ERROR default\n");
 868                 return -1;
 869         }
 870 }
 871
 872 /**
 873  * omap_correct_data - Compares the ECC read with HW generated ECC
 874  * @mtd: MTD device structure
 875  * @dat: page data
 876  * @read_ecc: ecc read from nand flash
 877  * @calc_ecc: ecc read from HW ECC registers
 878  *
 879  * Compares the ecc read from nand spare area with ECC registers values
 880  * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
 881  * detection and correction. If there are no errors, %0 is returned. If
 882  * there were errors and all of the errors were corrected, the number of
 883  * corrected errors is returned. If uncorrectable errors exist, %-1 is
 884  * returned.
 885  */
 886 static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
 887                                 u_char *read_ecc, u_char *calc_ecc)
 888 {
 889         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 890                                                         mtd);
 891         int blockCnt = 0, i = 0, ret = 0;
 892         int stat = 0;
 893
 894         /* Ex NAND_ECC_HW12_2048 */
 895         if ((info->nand.ecc.mode == NAND_ECC_HW) &&
 896                         (info->nand.ecc.size  == 2048))
 897                 blockCnt = 4;
 898         else
 899                 blockCnt = 1;
 900
 901         for (i = 0; i < blockCnt; i++) {
 902                 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
 903                         ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
 904                         if (ret < 0)
 905                                 return ret;
 906                         /* keep track of the number of corrected errors */
 907                         stat += ret;
 908                 }
 909                 read_ecc += 3;
 910                 calc_ecc += 3;
 911                 dat      += 512;
 912         }
 913         return stat;
 914 }
 915
 916 /**
 917  * omap_calcuate_ecc - Generate non-inverted ECC bytes.
 918  * @mtd: MTD device structure
 919  * @dat: The pointer to data on which ecc is computed
 920  * @ecc_code: The ecc_code buffer
 921  *
 922  * Using noninverted ECC can be considered ugly since writing a blank
 923  * page ie. padding will clear the ECC bytes. This is no problem as long
 924  * nobody is trying to write data on the seemingly unused page. Reading
 925  * an erased page will produce an ECC mismatch between generated and read
 926  * ECC bytes that has to be dealt with separately.
 927  */
 928 static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 929                                 u_char *ecc_code)
 930 {
 931         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 932                                                         mtd);
 933         u32 val;
 934
 935         val = readl(info->reg.gpmc_ecc_config);
 936         if (((val >> ECC_CONFIG_CS_SHIFT) & CS_MASK) != info->gpmc_cs)
 937                 return -EINVAL;
 938
 939         /* read ecc result */
 940         val = readl(info->reg.gpmc_ecc1_result);
 941         *ecc_code++ = val;          /* P128e, ..., P1e */
 942         *ecc_code++ = val >> 16;    /* P128o, ..., P1o */
 943         /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
 944         *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
 945
 946         return 0;
 947 }
 948
 949 /**
 950  * omap_enable_hwecc - This function enables the hardware ecc functionality
 951  * @mtd: MTD device structure
 952  * @mode: Read/Write mode
 953  */
 954 static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
 955 {
 956         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 957                                                         mtd);
 958         struct nand_chip *chip = mtd->priv;
 959         unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
 960         u32 val;
 961
 962         /* clear ecc and enable bits */
 963         val = ECCCLEAR | ECC1;
 964         writel(val, info->reg.gpmc_ecc_control);
 965
 966         /* program ecc and result sizes */
 967         val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) |
 968                          ECC1RESULTSIZE);
 969         writel(val, info->reg.gpmc_ecc_size_config);
 970
 971         switch (mode) {
 972         case NAND_ECC_READ:
 973         case NAND_ECC_WRITE:
 974                 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
 975                 break;
 976         case NAND_ECC_READSYN:
 977                 writel(ECCCLEAR, info->reg.gpmc_ecc_control);
 978                 break;
 979         default:
 980                 dev_info(&info->pdev->dev,
 981                         "error: unrecognized Mode[%d]!\n", mode);
 982                 break;
 983         }
 984
 985         /* (ECC 16 or 8 bit col) | ( CS  )  | ECC Enable */
 986         val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
 987         writel(val, info->reg.gpmc_ecc_config);
 988 }
 989
 990 /**
 991  * omap_wait - wait until the command is done
 992  * @mtd: MTD device structure
 993  * @chip: NAND Chip structure
 994  *
 995  * Wait function is called during Program and erase operations and
 996  * the way it is called from MTD layer, we should wait till the NAND
 997  * chip is ready after the programming/erase operation has completed.
 998  *
 999  * Erase can take up to 400ms and program up to 20ms according to
1000  * general NAND and SmartMedia specs
1001  */
1002 static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
1003 {
1004         struct nand_chip *this = mtd->priv;
1005         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1006                                                         mtd);
1007         unsigned long timeo = jiffies;
1008         int status, state = this->state;
1009
1010         if (state == FL_ERASING)
1011                 timeo += msecs_to_jiffies(400);
1012         else
1013                 timeo += msecs_to_jiffies(20);
1014
1015         writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command);
1016         while (time_before(jiffies, timeo)) {
1017                 status = readb(info->reg.gpmc_nand_data);
1018                 if (status & NAND_STATUS_READY)
1019                         break;
1020                 cond_resched();
1021         }
1022
1023         status = readb(info->reg.gpmc_nand_data);
1024         return status;
1025 }
1026
1027 /**
1028  * omap_dev_ready - calls the platform specific dev_ready function
1029  * @mtd: MTD device structure
1030  */
1031 static int omap_dev_ready(struct mtd_info *mtd)
1032 {
1033         unsigned int val = 0;
1034         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1035                                                         mtd);
1036
1037         val = readl(info->reg.gpmc_status);
1038
1039         if ((val & 0x100) == 0x100) {
1040                 return 1;
1041         } else {
1042                 return 0;
1043         }
1044 }
1045
1046 /**
1047  * omap_enable_hwecc_bch - Program GPMC to perform BCH ECC calculation
1048  * @mtd: MTD device structure
1049  * @mode: Read/Write mode
1050  *
1051  * When using BCH, sector size is hardcoded to 512 bytes.
1052  * Using wrapping mode 6 both for reading and writing if ELM module not uses
1053  * for error correction.
1054  * On writing,
1055  * eccsize0 = 0  (no additional protected byte in spare area)
1056  * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
1057  */
1058 static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info *mtd, int mode)
1059 {
1060         unsigned int bch_type;
1061         unsigned int dev_width, nsectors;
1062         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1063                                                    mtd);
1064         enum omap_ecc ecc_opt = info->ecc_opt;
1065         struct nand_chip *chip = mtd->priv;
1066         u32 val, wr_mode;
1067         unsigned int ecc_size1, ecc_size0;
1068
1069         /* GPMC configurations for calculating ECC */
1070         switch (ecc_opt) {
1071         case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1072                 bch_type = 0;
1073                 nsectors = 1;
1074                 if (mode == NAND_ECC_READ) {
1075                         wr_mode   = BCH_WRAPMODE_6;
1076                         ecc_size0 = BCH_ECC_SIZE0;
1077                         ecc_size1 = BCH_ECC_SIZE1;
1078                 } else {
1079                         wr_mode   = BCH_WRAPMODE_6;
1080                         ecc_size0 = BCH_ECC_SIZE0;
1081                         ecc_size1 = BCH_ECC_SIZE1;
1082                 }
1083                 break;
1084         case OMAP_ECC_BCH4_CODE_HW:
1085                 bch_type = 0;
1086                 nsectors = chip->ecc.steps;
1087                 if (mode == NAND_ECC_READ) {
1088                         wr_mode   = BCH_WRAPMODE_1;
1089                         ecc_size0 = BCH4R_ECC_SIZE0;
1090                         ecc_size1 = BCH4R_ECC_SIZE1;
1091                 } else {
1092                         wr_mode   = BCH_WRAPMODE_6;
1093                         ecc_size0 = BCH_ECC_SIZE0;
1094                         ecc_size1 = BCH_ECC_SIZE1;
1095                 }
1096                 break;
1097         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1098                 bch_type = 1;
1099                 nsectors = 1;
1100                 if (mode == NAND_ECC_READ) {
1101                         wr_mode   = BCH_WRAPMODE_6;
1102                         ecc_size0 = BCH_ECC_SIZE0;
1103                         ecc_size1 = BCH_ECC_SIZE1;
1104                 } else {
1105                         wr_mode   = BCH_WRAPMODE_6;
1106                         ecc_size0 = BCH_ECC_SIZE0;
1107                         ecc_size1 = BCH_ECC_SIZE1;
1108                 }
1109                 break;
1110         case OMAP_ECC_BCH8_CODE_HW:
1111                 bch_type = 1;
1112                 nsectors = chip->ecc.steps;
1113                 if (mode == NAND_ECC_READ) {
1114                         wr_mode   = BCH_WRAPMODE_1;
1115                         ecc_size0 = BCH8R_ECC_SIZE0;
1116                         ecc_size1 = BCH8R_ECC_SIZE1;
1117                 } else {
1118                         wr_mode   = BCH_WRAPMODE_6;
1119                         ecc_size0 = BCH_ECC_SIZE0;
1120                         ecc_size1 = BCH_ECC_SIZE1;
1121                 }
1122                 break;
1123         case OMAP_ECC_BCH16_CODE_HW:
1124                 bch_type = 0x2;
1125                 nsectors = chip->ecc.steps;
1126                 if (mode == NAND_ECC_READ) {
1127                         wr_mode   = 0x01;
1128                         ecc_size0 = 52; /* ECC bits in nibbles per sector */
1129                         ecc_size1 = 0;  /* non-ECC bits in nibbles per sector */
1130                 } else {
1131                         wr_mode   = 0x01;
1132                         ecc_size0 = 0;  /* extra bits in nibbles per sector */
1133                         ecc_size1 = 52; /* OOB bits in nibbles per sector */
1134                 }
1135                 break;
1136         default:
1137                 return;
1138         }
1139
1140         writel(ECC1, info->reg.gpmc_ecc_control);
1141
1142         /* Configure ecc size for BCH */
1143         val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT);
1144         writel(val, info->reg.gpmc_ecc_size_config);
1145
1146         dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
1147
1148         /* BCH configuration */
1149         val = ((1                        << 16) | /* enable BCH */
1150                (bch_type                 << 12) | /* BCH4/BCH8/BCH16 */
1151                (wr_mode                  <<  8) | /* wrap mode */
1152                (dev_width                <<  7) | /* bus width */
1153                (((nsectors-1) & 0x7)     <<  4) | /* number of sectors */
1154                (info->gpmc_cs            <<  1) | /* ECC CS */
1155                (0x1));                            /* enable ECC */
1156
1157         writel(val, info->reg.gpmc_ecc_config);
1158
1159         /* Clear ecc and enable bits */
1160         writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
1161 }
1162
1163 static u8  bch4_polynomial[] = {0x28, 0x13, 0xcc, 0x39, 0x96, 0xac, 0x7f};
1164 static u8  bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
1165                                 0x97, 0x79, 0xe5, 0x24, 0xb5};
1166
1167 /**
1168  * omap_calculate_ecc_bch - Generate bytes of ECC bytes
1169  * @mtd:        MTD device structure
1170  * @dat:        The pointer to data on which ecc is computed
1171  * @ecc_code:   The ecc_code buffer
1172  *
1173  * Support calculating of BCH4/8 ecc vectors for the page
1174  */
1175 static int __maybe_unused omap_calculate_ecc_bch(struct mtd_info *mtd,
1176                                         const u_char *dat, u_char *ecc_calc)
1177 {
1178         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1179                                                    mtd);
1180         int eccbytes    = info->nand.ecc.bytes;
1181         struct gpmc_nand_regs   *gpmc_regs = &info->reg;
1182         u8 *ecc_code;
1183         unsigned long nsectors, bch_val1, bch_val2, bch_val3, bch_val4;
1184         u32 val;
1185         int i, j;
1186
1187         nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1188         for (i = 0; i < nsectors; i++) {
1189                 ecc_code = ecc_calc;
1190                 switch (info->ecc_opt) {
1191                 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1192                 case OMAP_ECC_BCH8_CODE_HW:
1193                         bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]);
1194                         bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]);
1195                         bch_val3 = readl(gpmc_regs->gpmc_bch_result2[i]);
1196                         bch_val4 = readl(gpmc_regs->gpmc_bch_result3[i]);
1197                         *ecc_code++ = (bch_val4 & 0xFF);
1198                         *ecc_code++ = ((bch_val3 >> 24) & 0xFF);
1199                         *ecc_code++ = ((bch_val3 >> 16) & 0xFF);
1200                         *ecc_code++ = ((bch_val3 >> 8) & 0xFF);
1201                         *ecc_code++ = (bch_val3 & 0xFF);
1202                         *ecc_code++ = ((bch_val2 >> 24) & 0xFF);
1203                         *ecc_code++ = ((bch_val2 >> 16) & 0xFF);
1204                         *ecc_code++ = ((bch_val2 >> 8) & 0xFF);
1205                         *ecc_code++ = (bch_val2 & 0xFF);
1206                         *ecc_code++ = ((bch_val1 >> 24) & 0xFF);
1207                         *ecc_code++ = ((bch_val1 >> 16) & 0xFF);
1208                         *ecc_code++ = ((bch_val1 >> 8) & 0xFF);
1209                         *ecc_code++ = (bch_val1 & 0xFF);
1210                         break;
1211                 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1212                 case OMAP_ECC_BCH4_CODE_HW:
1213                         bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]);
1214                         bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]);
1215                         *ecc_code++ = ((bch_val2 >> 12) & 0xFF);
1216                         *ecc_code++ = ((bch_val2 >> 4) & 0xFF);
1217                         *ecc_code++ = ((bch_val2 & 0xF) << 4) |
1218                                 ((bch_val1 >> 28) & 0xF);
1219                         *ecc_code++ = ((bch_val1 >> 20) & 0xFF);
1220                         *ecc_code++ = ((bch_val1 >> 12) & 0xFF);
1221                         *ecc_code++ = ((bch_val1 >> 4) & 0xFF);
1222                         *ecc_code++ = ((bch_val1 & 0xF) << 4);
1223                         break;
1224                 case OMAP_ECC_BCH16_CODE_HW:
1225                         val = readl(gpmc_regs->gpmc_bch_result6[i]);
1226                         ecc_code[0]  = ((val >>  8) & 0xFF);
1227                         ecc_code[1]  = ((val >>  0) & 0xFF);
1228                         val = readl(gpmc_regs->gpmc_bch_result5[i]);
1229                         ecc_code[2]  = ((val >> 24) & 0xFF);
1230                         ecc_code[3]  = ((val >> 16) & 0xFF);
1231                         ecc_code[4]  = ((val >>  8) & 0xFF);
1232                         ecc_code[5]  = ((val >>  0) & 0xFF);
1233                         val = readl(gpmc_regs->gpmc_bch_result4[i]);
1234                         ecc_code[6]  = ((val >> 24) & 0xFF);
1235                         ecc_code[7]  = ((val >> 16) & 0xFF);
1236                         ecc_code[8]  = ((val >>  8) & 0xFF);
1237                         ecc_code[9]  = ((val >>  0) & 0xFF);
1238                         val = readl(gpmc_regs->gpmc_bch_result3[i]);
1239                         ecc_code[10] = ((val >> 24) & 0xFF);
1240                         ecc_code[11] = ((val >> 16) & 0xFF);
1241                         ecc_code[12] = ((val >>  8) & 0xFF);
1242                         ecc_code[13] = ((val >>  0) & 0xFF);
1243                         val = readl(gpmc_regs->gpmc_bch_result2[i]);
1244                         ecc_code[14] = ((val >> 24) & 0xFF);
1245                         ecc_code[15] = ((val >> 16) & 0xFF);
1246                         ecc_code[16] = ((val >>  8) & 0xFF);
1247                         ecc_code[17] = ((val >>  0) & 0xFF);
1248                         val = readl(gpmc_regs->gpmc_bch_result1[i]);
1249                         ecc_code[18] = ((val >> 24) & 0xFF);
1250                         ecc_code[19] = ((val >> 16) & 0xFF);
1251                         ecc_code[20] = ((val >>  8) & 0xFF);
1252                         ecc_code[21] = ((val >>  0) & 0xFF);
1253                         val = readl(gpmc_regs->gpmc_bch_result0[i]);
1254                         ecc_code[22] = ((val >> 24) & 0xFF);
1255                         ecc_code[23] = ((val >> 16) & 0xFF);
1256                         ecc_code[24] = ((val >>  8) & 0xFF);
1257                         ecc_code[25] = ((val >>  0) & 0xFF);
1258                         break;
1259                 default:
1260                         return -EINVAL;
1261                 }
1262
1263                 /* ECC scheme specific syndrome customizations */
1264                 switch (info->ecc_opt) {
1265                 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1266                         /* Add constant polynomial to remainder, so that
1267                          * ECC of blank pages results in 0x0 on reading back */
1268                         for (j = 0; j < eccbytes; j++)
1269                                 ecc_calc[j] ^= bch4_polynomial[j];
1270                         break;
1271                 case OMAP_ECC_BCH4_CODE_HW:
1272                         /* Set  8th ECC byte as 0x0 for ROM compatibility */
1273                         ecc_calc[eccbytes - 1] = 0x0;
1274                         break;
1275                 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1276                         /* Add constant polynomial to remainder, so that
1277                          * ECC of blank pages results in 0x0 on reading back */
1278                         for (j = 0; j < eccbytes; j++)
1279                                 ecc_calc[j] ^= bch8_polynomial[j];
1280                         break;
1281                 case OMAP_ECC_BCH8_CODE_HW:
1282                         /* Set 14th ECC byte as 0x0 for ROM compatibility */
1283                         ecc_calc[eccbytes - 1] = 0x0;
1284                         break;
1285                 case OMAP_ECC_BCH16_CODE_HW:
1286                         break;
1287                 default:
1288                         return -EINVAL;
1289                 }
1290
1291         ecc_calc += eccbytes;
1292         }
1293
1294         return 0;
1295 }
1296
1297 /**
1298  * erased_sector_bitflips - count bit flips
1299  * @data:       data sector buffer
1300  * @oob:        oob buffer
1301  * @info:       omap_nand_info
1302  *
1303  * Check the bit flips in erased page falls below correctable level.
1304  * If falls below, report the page as erased with correctable bit
1305  * flip, else report as uncorrectable page.
1306  */
1307 static int erased_sector_bitflips(u_char *data, u_char *oob,
1308                 struct omap_nand_info *info)
1309 {
1310         int flip_bits = 0, i;
1311
1312         for (i = 0; i < info->nand.ecc.size; i++) {
1313                 flip_bits += hweight8(~data[i]);
1314                 if (flip_bits > info->nand.ecc.strength)
1315                         return 0;
1316         }
1317
1318         for (i = 0; i < info->nand.ecc.bytes - 1; i++) {
1319                 flip_bits += hweight8(~oob[i]);
1320                 if (flip_bits > info->nand.ecc.strength)
1321                         return 0;
1322         }
1323
1324         /*
1325          * Bit flips falls in correctable level.
1326          * Fill data area with 0xFF
1327          */
1328         if (flip_bits) {
1329                 memset(data, 0xFF, info->nand.ecc.size);
1330                 memset(oob, 0xFF, info->nand.ecc.bytes);
1331         }
1332
1333         return flip_bits;
1334 }
1335
1336 /**
1337  * omap_elm_correct_data - corrects page data area in case error reported
1338  * @mtd:        MTD device structure
1339  * @data:       page data
1340  * @read_ecc:   ecc read from nand flash
1341  * @calc_ecc:   ecc read from HW ECC registers
1342  *
1343  * Calculated ecc vector reported as zero in case of non-error pages.
1344  * In case of non-zero ecc vector, first filter out erased-pages, and
1345  * then process data via ELM to detect bit-flips.
1346  */
1347 static int omap_elm_correct_data(struct mtd_info *mtd, u_char *data,
1348                                 u_char *read_ecc, u_char *calc_ecc)
1349 {
1350         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1351                         mtd);
1352         struct nand_ecc_ctrl *ecc = &info->nand.ecc;
1353         int eccsteps = info->nand.ecc.steps;
1354         int i , j, stat = 0;
1355         int eccflag, actual_eccbytes;
1356         struct elm_errorvec err_vec[ERROR_VECTOR_MAX];
1357         u_char *ecc_vec = calc_ecc;
1358         u_char *spare_ecc = read_ecc;
1359         u_char *erased_ecc_vec;
1360         u_char *buf;
1361         int bitflip_count;
1362         bool is_error_reported = false;
1363         u32 bit_pos, byte_pos, error_max, pos;
1364         int err;
1365
1366         switch (info->ecc_opt) {
1367         case OMAP_ECC_BCH4_CODE_HW:
1368                 /* omit  7th ECC byte reserved for ROM code compatibility */
1369                 actual_eccbytes = ecc->bytes - 1;
1370                 erased_ecc_vec = bch4_vector;
1371                 break;
1372         case OMAP_ECC_BCH8_CODE_HW:
1373                 /* omit 14th ECC byte reserved for ROM code compatibility */
1374                 actual_eccbytes = ecc->bytes - 1;
1375                 erased_ecc_vec = bch8_vector;
1376                 break;
1377         case OMAP_ECC_BCH16_CODE_HW:
1378                 actual_eccbytes = ecc->bytes;
1379                 erased_ecc_vec = bch16_vector;
1380                 break;
1381         default:
1382                 dev_err(&info->pdev->dev, "invalid driver configuration\n");
1383                 return -EINVAL;
1384         }
1385
1386         /* Initialize elm error vector to zero */
1387         memset(err_vec, 0, sizeof(err_vec));
1388
1389         for (i = 0; i < eccsteps ; i++) {
1390                 eccflag = 0;    /* initialize eccflag */
1391
1392                 /*
1393                  * Check any error reported,
1394                  * In case of error, non zero ecc reported.
1395                  */
1396                 for (j = 0; j < actual_eccbytes; j++) {
1397                         if (calc_ecc[j] != 0) {
1398                                 eccflag = 1; /* non zero ecc, error present */
1399                                 break;
1400                         }
1401                 }
1402
1403                 if (eccflag == 1) {
1404                         if (memcmp(calc_ecc, erased_ecc_vec,
1405                                                 actual_eccbytes) == 0) {
1406                                 /*
1407                                  * calc_ecc[] matches pattern for ECC(all 0xff)
1408                                  * so this is definitely an erased-page
1409                                  */
1410                         } else {
1411                                 buf = &data[info->nand.ecc.size * i];
1412                                 /*
1413                                  * count number of 0-bits in read_buf.
1414                                  * This check can be removed once a similar
1415                                  * check is introduced in generic NAND driver
1416                                  */
1417                                 bitflip_count = erased_sector_bitflips(
1418                                                 buf, read_ecc, info);
1419                                 if (bitflip_count) {
1420                                         /*
1421                                          * number of 0-bits within ECC limits
1422                                          * So this may be an erased-page
1423                                          */
1424                                         stat += bitflip_count;
1425                                 } else {
1426                                         /*
1427                                          * Too many 0-bits. It may be a
1428                                          * - programmed-page, OR
1429                                          * - erased-page with many bit-flips
1430                                          * So this page requires check by ELM
1431                                          */
1432                                         err_vec[i].error_reported = true;
1433                                         is_error_reported = true;
1434                                 }
1435                         }
1436                 }
1437
1438                 /* Update the ecc vector */
1439                 calc_ecc += ecc->bytes;
1440                 read_ecc += ecc->bytes;
1441         }
1442
1443         /* Check if any error reported */
1444         if (!is_error_reported)
1445                 return stat;
1446
1447         /* Decode BCH error using ELM module */
1448         elm_decode_bch_error_page(info->elm_dev, ecc_vec, err_vec);
1449
1450         err = 0;
1451         for (i = 0; i < eccsteps; i++) {
1452                 if (err_vec[i].error_uncorrectable) {
1453                         dev_err(&info->pdev->dev,
1454                                 "uncorrectable bit-flips found\n");
1455                         err = -EBADMSG;
1456                 } else if (err_vec[i].error_reported) {
1457                         for (j = 0; j < err_vec[i].error_count; j++) {
1458                                 switch (info->ecc_opt) {
1459                                 case OMAP_ECC_BCH4_CODE_HW:
1460                                         /* Add 4 bits to take care of padding */
1461                                         pos = err_vec[i].error_loc[j] +
1462                                                 BCH4_BIT_PAD;
1463                                         break;
1464                                 case OMAP_ECC_BCH8_CODE_HW:
1465                                 case OMAP_ECC_BCH16_CODE_HW:
1466                                         pos = err_vec[i].error_loc[j];
1467                                         break;
1468                                 default:
1469                                         return -EINVAL;
1470                                 }
1471                                 error_max = (ecc->size + actual_eccbytes) * 8;
1472                                 /* Calculate bit position of error */
1473                                 bit_pos = pos % 8;
1474
1475                                 /* Calculate byte position of error */
1476                                 byte_pos = (error_max - pos - 1) / 8;
1477
1478                                 if (pos < error_max) {
1479                                         if (byte_pos < 512) {
1480                                                 pr_debug("bitflip@dat[%d]=%x\n",
1481                                                      byte_pos, data[byte_pos]);
1482                                                 data[byte_pos] ^= 1 << bit_pos;
1483                                         } else {
1484                                                 pr_debug("bitflip@oob[%d]=%x\n",
1485                                                         (byte_pos - 512),
1486                                                      spare_ecc[byte_pos - 512]);
1487                                                 spare_ecc[byte_pos - 512] ^=
1488                                                         1 << bit_pos;
1489                                         }
1490                                 } else {
1491                                         dev_err(&info->pdev->dev,
1492                                                 "invalid bit-flip @ %d:%d\n",
1493                                                 byte_pos, bit_pos);
1494                                         err = -EBADMSG;
1495                                 }
1496                         }
1497                 }
1498
1499                 /* Update number of correctable errors */
1500                 stat += err_vec[i].error_count;
1501
1502                 /* Update page data with sector size */
1503                 data += ecc->size;
1504                 spare_ecc += ecc->bytes;
1505         }
1506
1507         return (err) ? err : stat;
1508 }
1509
1510 /**
1511  * omap_write_page_bch - BCH ecc based write page function for entire page
1512  * @mtd:                mtd info structure
1513  * @chip:               nand chip info structure
1514  * @buf:                data buffer
1515  * @oob_required:       must write chip->oob_poi to OOB
1516  *
1517  * Custom write page method evolved to support multi sector writing in one shot
1518  */
1519 static int omap_write_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
1520                                   const uint8_t *buf, int oob_required)
1521 {
1522         int i;
1523         uint8_t *ecc_calc = chip->buffers->ecccalc;
1524         uint32_t *eccpos = chip->ecc.layout->eccpos;
1525
1526         /* Enable GPMC ecc engine */
1527         chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1528
1529         /* Write data */
1530         chip->write_buf(mtd, buf, mtd->writesize);
1531
1532         /* Update ecc vector from GPMC result registers */
1533         chip->ecc.calculate(mtd, buf, &ecc_calc[0]);
1534
1535         for (i = 0; i < chip->ecc.total; i++)
1536                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1537
1538         /* Write ecc vector to OOB area */
1539         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1540         return 0;
1541 }
1542
1543 /**
1544  * omap_read_page_bch - BCH ecc based page read function for entire page
1545  * @mtd:                mtd info structure
1546  * @chip:               nand chip info structure
1547  * @buf:                buffer to store read data
1548  * @oob_required:       caller requires OOB data read to chip->oob_poi
1549  * @page:               page number to read
1550  *
1551  * For BCH ecc scheme, GPMC used for syndrome calculation and ELM module
1552  * used for error correction.
1553  * Custom method evolved to support ELM error correction & multi sector
1554  * reading. On reading page data area is read along with OOB data with
1555  * ecc engine enabled. ecc vector updated after read of OOB data.
1556  * For non error pages ecc vector reported as zero.
1557  */
1558 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
1559                                 uint8_t *buf, int oob_required, int page)
1560 {
1561         uint8_t *ecc_calc = chip->buffers->ecccalc;
1562         uint8_t *ecc_code = chip->buffers->ecccode;
1563         uint32_t *eccpos = chip->ecc.layout->eccpos;
1564         uint8_t *oob = &chip->oob_poi[eccpos[0]];
1565         uint32_t oob_pos = mtd->writesize + chip->ecc.layout->eccpos[0];
1566         int stat;
1567         unsigned int max_bitflips = 0;
1568
1569         /* Enable GPMC ecc engine */
1570         chip->ecc.hwctl(mtd, NAND_ECC_READ);
1571
1572         /* Read data */
1573         chip->read_buf(mtd, buf, mtd->writesize);
1574
1575         /* Read oob bytes */
1576         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);
1577         chip->read_buf(mtd, oob, chip->ecc.total);
1578
1579         /* Calculate ecc bytes */
1580         chip->ecc.calculate(mtd, buf, ecc_calc);
1581
1582         memcpy(ecc_code, &chip->oob_poi[eccpos[0]], chip->ecc.total);
1583
1584         stat = chip->ecc.correct(mtd, buf, ecc_code, ecc_calc);
1585
1586         if (stat < 0) {
1587                 mtd->ecc_stats.failed++;
1588         } else {
1589                 mtd->ecc_stats.corrected += stat;
1590                 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1591         }
1592
1593         return max_bitflips;
1594 }
1595
1596 /**
1597  * is_elm_present - checks for presence of ELM module by scanning DT nodes
1598  * @omap_nand_info: NAND device structure containing platform data
1599  */
1600 static bool is_elm_present(struct omap_nand_info *info,
1601                            struct device_node *elm_node)
1602 {
1603         struct platform_device *pdev;
1604
1605         /* check whether elm-id is passed via DT */
1606         if (!elm_node) {
1607                 dev_err(&info->pdev->dev, "ELM devicetree node not found\n");
1608                 return false;
1609         }
1610         pdev = of_find_device_by_node(elm_node);
1611         /* check whether ELM device is registered */
1612         if (!pdev) {
1613                 dev_err(&info->pdev->dev, "ELM device not found\n");
1614                 return false;
1615         }
1616         /* ELM module available, now configure it */
1617         info->elm_dev = &pdev->dev;
1618         return true;
1619 }
1620
1621 static bool omap2_nand_ecc_check(struct omap_nand_info *info,
1622                                  struct omap_nand_platform_data *pdata)
1623 {
1624         bool ecc_needs_bch, ecc_needs_omap_bch, ecc_needs_elm;
1625
1626         switch (info->ecc_opt) {
1627         case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1628         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1629                 ecc_needs_omap_bch = false;
1630                 ecc_needs_bch = true;
1631                 ecc_needs_elm = false;
1632                 break;
1633         case OMAP_ECC_BCH4_CODE_HW:
1634         case OMAP_ECC_BCH8_CODE_HW:
1635         case OMAP_ECC_BCH16_CODE_HW:
1636                 ecc_needs_omap_bch = true;
1637                 ecc_needs_bch = false;
1638                 ecc_needs_elm = true;
1639                 break;
1640         default:
1641                 ecc_needs_omap_bch = false;
1642                 ecc_needs_bch = false;
1643                 ecc_needs_elm = false;
1644                 break;
1645         }
1646
1647         if (ecc_needs_bch && !IS_ENABLED(CONFIG_MTD_NAND_ECC_BCH)) {
1648                 dev_err(&info->pdev->dev,
1649                         "CONFIG_MTD_NAND_ECC_BCH not enabled\n");
1650                 return false;
1651         }
1652         if (ecc_needs_omap_bch && !IS_ENABLED(CONFIG_MTD_NAND_OMAP_BCH)) {
1653                 dev_err(&info->pdev->dev,
1654                         "CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
1655                 return false;
1656         }
1657         if (ecc_needs_elm && !is_elm_present(info, pdata->elm_of_node)) {
1658                 dev_err(&info->pdev->dev, "ELM not available\n");
1659                 return false;
1660         }
1661
1662         return true;
1663 }
1664
1665 static int omap_nand_probe(struct platform_device *pdev)
1666 {
1667         struct omap_nand_info           *info;
1668         struct omap_nand_platform_data  *pdata;
1669         struct mtd_info                 *mtd;
1670         struct nand_chip                *nand_chip;
1671         struct nand_ecclayout           *ecclayout;
1672         int                             err;
1673         int                             i;
1674         dma_cap_mask_t                  mask;
1675         unsigned                        sig;
1676         unsigned                        oob_index;
1677         struct resource                 *res;
1678         struct mtd_part_parser_data     ppdata = {};
1679
1680         pdata = dev_get_platdata(&pdev->dev);
1681         if (pdata == NULL) {
1682                 dev_err(&pdev->dev, "platform data missing\n");
1683                 return -ENODEV;
1684         }
1685
1686         info = devm_kzalloc(&pdev->dev, sizeof(struct omap_nand_info),
1687                                 GFP_KERNEL);
1688         if (!info)
1689                 return -ENOMEM;
1690
1691         platform_set_drvdata(pdev, info);
1692
1693         info->pdev              = pdev;
1694         info->gpmc_cs           = pdata->cs;
1695         info->reg               = pdata->reg;
1696         info->of_node           = pdata->of_node;
1697         info->ecc_opt           = pdata->ecc_opt;
1698         mtd                     = &info->mtd;
1699         mtd->priv               = &info->nand;
1700         mtd->name               = dev_name(&pdev->dev);
1701         mtd->owner              = THIS_MODULE;
1702         nand_chip               = &info->nand;
1703         nand_chip->ecc.priv     = NULL;
1704
1705         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1706         nand_chip->IO_ADDR_R = devm_ioremap_resource(&pdev->dev, res);
1707         if (IS_ERR(nand_chip->IO_ADDR_R))
1708                 return PTR_ERR(nand_chip->IO_ADDR_R);
1709
1710         info->phys_base = res->start;
1711
1712         nand_chip->controller = &omap_gpmc_controller;
1713
1714         nand_chip->IO_ADDR_W = nand_chip->IO_ADDR_R;
1715         nand_chip->cmd_ctrl  = omap_hwcontrol;
1716
1717         /*
1718          * If RDY/BSY line is connected to OMAP then use the omap ready
1719          * function and the generic nand_wait function which reads the status
1720          * register after monitoring the RDY/BSY line. Otherwise use a standard
1721          * chip delay which is slightly more than tR (AC Timing) of the NAND
1722          * device and read status register until you get a failure or success
1723          */
1724         if (pdata->dev_ready) {
1725                 nand_chip->dev_ready = omap_dev_ready;
1726                 nand_chip->chip_delay = 0;
1727         } else {
1728                 nand_chip->waitfunc = omap_wait;
1729                 nand_chip->chip_delay = 50;
1730         }
1731
1732         if (pdata->flash_bbt)
1733                 nand_chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
1734         else
1735                 nand_chip->options |= NAND_SKIP_BBTSCAN;
1736
1737         /* scan NAND device connected to chip controller */
1738         nand_chip->options |= pdata->devsize & NAND_BUSWIDTH_16;
1739         if (nand_scan_ident(mtd, 1, NULL)) {
1740                 dev_err(&info->pdev->dev, "scan failed, may be bus-width mismatch\n");
1741                 err = -ENXIO;
1742                 goto return_error;
1743         }
1744
1745         /* re-populate low-level callbacks based on xfer modes */
1746         switch (pdata->xfer_type) {
1747         case NAND_OMAP_PREFETCH_POLLED:
1748                 nand_chip->read_buf   = omap_read_buf_pref;
1749                 nand_chip->write_buf  = omap_write_buf_pref;
1750                 break;
1751
1752         case NAND_OMAP_POLLED:
1753                 /* Use nand_base defaults for {read,write}_buf */
1754                 break;
1755
1756         case NAND_OMAP_PREFETCH_DMA:
1757                 dma_cap_zero(mask);
1758                 dma_cap_set(DMA_SLAVE, mask);
1759                 sig = OMAP24XX_DMA_GPMC;
1760                 info->dma = dma_request_channel(mask, omap_dma_filter_fn, &sig);
1761                 if (!info->dma) {
1762                         dev_err(&pdev->dev, "DMA engine request failed\n");
1763                         err = -ENXIO;
1764                         goto return_error;
1765                 } else {
1766                         struct dma_slave_config cfg;
1767
1768                         memset(&cfg, 0, sizeof(cfg));
1769                         cfg.src_addr = info->phys_base;
1770                         cfg.dst_addr = info->phys_base;
1771                         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1772                         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1773                         cfg.src_maxburst = 16;
1774                         cfg.dst_maxburst = 16;
1775                         err = dmaengine_slave_config(info->dma, &cfg);
1776                         if (err) {
1777                                 dev_err(&pdev->dev, "DMA engine slave config failed: %d\n",
1778                                         err);
1779                                 goto return_error;
1780                         }
1781                         nand_chip->read_buf   = omap_read_buf_dma_pref;
1782                         nand_chip->write_buf  = omap_write_buf_dma_pref;
1783                 }
1784                 break;
1785
1786         case NAND_OMAP_PREFETCH_IRQ:
1787                 info->gpmc_irq_fifo = platform_get_irq(pdev, 0);
1788                 if (info->gpmc_irq_fifo <= 0) {
1789                         dev_err(&pdev->dev, "error getting fifo irq\n");
1790                         err = -ENODEV;
1791                         goto return_error;
1792                 }
1793                 err = devm_request_irq(&pdev->dev, info->gpmc_irq_fifo,
1794                                         omap_nand_irq, IRQF_SHARED,
1795                                         "gpmc-nand-fifo", info);
1796                 if (err) {
1797                         dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1798                                                 info->gpmc_irq_fifo, err);
1799                         info->gpmc_irq_fifo = 0;
1800                         goto return_error;
1801                 }
1802
1803                 info->gpmc_irq_count = platform_get_irq(pdev, 1);
1804                 if (info->gpmc_irq_count <= 0) {
1805                         dev_err(&pdev->dev, "error getting count irq\n");
1806                         err = -ENODEV;
1807                         goto return_error;
1808                 }
1809                 err = devm_request_irq(&pdev->dev, info->gpmc_irq_count,
1810                                         omap_nand_irq, IRQF_SHARED,
1811                                         "gpmc-nand-count", info);
1812                 if (err) {
1813                         dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1814                                                 info->gpmc_irq_count, err);
1815                         info->gpmc_irq_count = 0;
1816                         goto return_error;
1817                 }
1818
1819                 nand_chip->read_buf  = omap_read_buf_irq_pref;
1820                 nand_chip->write_buf = omap_write_buf_irq_pref;
1821
1822                 break;
1823
1824         default:
1825                 dev_err(&pdev->dev,
1826                         "xfer_type(%d) not supported!\n", pdata->xfer_type);
1827                 err = -EINVAL;
1828                 goto return_error;
1829         }
1830
1831         if (!omap2_nand_ecc_check(info, pdata)) {
1832                 err = -EINVAL;
1833                 goto return_error;
1834         }
1835
1836         /* populate MTD interface based on ECC scheme */
1837         ecclayout               = &info->oobinfo;
1838         switch (info->ecc_opt) {
1839         case OMAP_ECC_HAM1_CODE_SW:
1840                 nand_chip->ecc.mode = NAND_ECC_SOFT;
1841                 break;
1842
1843         case OMAP_ECC_HAM1_CODE_HW:
1844                 pr_info("nand: using OMAP_ECC_HAM1_CODE_HW\n");
1845                 nand_chip->ecc.mode             = NAND_ECC_HW;
1846                 nand_chip->ecc.bytes            = 3;
1847                 nand_chip->ecc.size             = 512;
1848                 nand_chip->ecc.strength         = 1;
1849                 nand_chip->ecc.calculate        = omap_calculate_ecc;
1850                 nand_chip->ecc.hwctl            = omap_enable_hwecc;
1851                 nand_chip->ecc.correct          = omap_correct_data;
1852                 /* define ECC layout */
1853                 ecclayout->eccbytes             = nand_chip->ecc.bytes *
1854                                                         (mtd->writesize /
1855                                                         nand_chip->ecc.size);
1856                 if (nand_chip->options & NAND_BUSWIDTH_16)
1857                         oob_index               = BADBLOCK_MARKER_LENGTH;
1858                 else
1859                         oob_index               = 1;
1860                 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1861                         ecclayout->eccpos[i]    = oob_index;
1862                 /* no reserved-marker in ecclayout for this ecc-scheme */
1863                 ecclayout->oobfree->offset      =
1864                                 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1865                 break;
1866
1867         case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1868                 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n");
1869                 nand_chip->ecc.mode             = NAND_ECC_HW;
1870                 nand_chip->ecc.size             = 512;
1871                 nand_chip->ecc.bytes            = 7;
1872                 nand_chip->ecc.strength         = 4;
1873                 nand_chip->ecc.hwctl            = omap_enable_hwecc_bch;
1874                 nand_chip->ecc.correct          = nand_bch_correct_data;
1875                 nand_chip->ecc.calculate        = omap_calculate_ecc_bch;
1876                 /* define ECC layout */
1877                 ecclayout->eccbytes             = nand_chip->ecc.bytes *
1878                                                         (mtd->writesize /
1879                                                         nand_chip->ecc.size);
1880                 oob_index                       = BADBLOCK_MARKER_LENGTH;
1881                 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) {
1882                         ecclayout->eccpos[i] = oob_index;
1883                         if (((i + 1) % nand_chip->ecc.bytes) == 0)
1884                                 oob_index++;
1885                 }
1886                 /* include reserved-marker in ecclayout->oobfree calculation */
1887                 ecclayout->oobfree->offset      = 1 +
1888                                 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1889                 /* software bch library is used for locating errors */
1890                 nand_chip->ecc.priv             = nand_bch_init(mtd,
1891                                                         nand_chip->ecc.size,
1892                                                         nand_chip->ecc.bytes,
1893                                                         &ecclayout);
1894                 if (!nand_chip->ecc.priv) {
1895                         dev_err(&info->pdev->dev, "unable to use BCH library\n");
1896                         err = -EINVAL;
1897                         goto return_error;
1898                 }
1899                 break;
1900
1901         case OMAP_ECC_BCH4_CODE_HW:
1902                 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n");
1903                 nand_chip->ecc.mode             = NAND_ECC_HW;
1904                 nand_chip->ecc.size             = 512;
1905                 /* 14th bit is kept reserved for ROM-code compatibility */
1906                 nand_chip->ecc.bytes            = 7 + 1;
1907                 nand_chip->ecc.strength         = 4;
1908                 nand_chip->ecc.hwctl            = omap_enable_hwecc_bch;
1909                 nand_chip->ecc.correct          = omap_elm_correct_data;
1910                 nand_chip->ecc.calculate        = omap_calculate_ecc_bch;
1911                 nand_chip->ecc.read_page        = omap_read_page_bch;
1912                 nand_chip->ecc.write_page       = omap_write_page_bch;
1913                 /* define ECC layout */
1914                 ecclayout->eccbytes             = nand_chip->ecc.bytes *
1915                                                         (mtd->writesize /
1916                                                         nand_chip->ecc.size);
1917                 oob_index                       = BADBLOCK_MARKER_LENGTH;
1918                 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1919                         ecclayout->eccpos[i]    = oob_index;
1920                 /* reserved marker already included in ecclayout->eccbytes */
1921                 ecclayout->oobfree->offset      =
1922                                 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1923
1924                 err = elm_config(info->elm_dev, BCH4_ECC,
1925                                  info->mtd.writesize / nand_chip->ecc.size,
1926                                  nand_chip->ecc.size, nand_chip->ecc.bytes);
1927                 if (err < 0)
1928                         goto return_error;
1929                 break;
1930
1931         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1932                 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
1933                 nand_chip->ecc.mode             = NAND_ECC_HW;
1934                 nand_chip->ecc.size             = 512;
1935                 nand_chip->ecc.bytes            = 13;
1936                 nand_chip->ecc.strength         = 8;
1937                 nand_chip->ecc.hwctl            = omap_enable_hwecc_bch;
1938                 nand_chip->ecc.correct          = nand_bch_correct_data;
1939                 nand_chip->ecc.calculate        = omap_calculate_ecc_bch;
1940                 /* define ECC layout */
1941                 ecclayout->eccbytes             = nand_chip->ecc.bytes *
1942                                                         (mtd->writesize /
1943                                                         nand_chip->ecc.size);
1944                 oob_index                       = BADBLOCK_MARKER_LENGTH;
1945                 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) {
1946                         ecclayout->eccpos[i] = oob_index;
1947                         if (((i + 1) % nand_chip->ecc.bytes) == 0)
1948                                 oob_index++;
1949                 }
1950                 /* include reserved-marker in ecclayout->oobfree calculation */
1951                 ecclayout->oobfree->offset      = 1 +
1952                                 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1953                 /* software bch library is used for locating errors */
1954                 nand_chip->ecc.priv             = nand_bch_init(mtd,
1955                                                         nand_chip->ecc.size,
1956                                                         nand_chip->ecc.bytes,
1957                                                         &ecclayout);
1958                 if (!nand_chip->ecc.priv) {
1959                         dev_err(&info->pdev->dev, "unable to use BCH library\n");
1960                         err = -EINVAL;
1961                         goto return_error;
1962                 }
1963                 break;
1964
1965         case OMAP_ECC_BCH8_CODE_HW:
1966                 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n");
1967                 nand_chip->ecc.mode             = NAND_ECC_HW;
1968                 nand_chip->ecc.size             = 512;
1969                 /* 14th bit is kept reserved for ROM-code compatibility */
1970                 nand_chip->ecc.bytes            = 13 + 1;
1971                 nand_chip->ecc.strength         = 8;
1972                 nand_chip->ecc.hwctl            = omap_enable_hwecc_bch;
1973                 nand_chip->ecc.correct          = omap_elm_correct_data;
1974                 nand_chip->ecc.calculate        = omap_calculate_ecc_bch;
1975                 nand_chip->ecc.read_page        = omap_read_page_bch;
1976                 nand_chip->ecc.write_page       = omap_write_page_bch;
1977
1978                 err = elm_config(info->elm_dev, BCH8_ECC,
1979                                  info->mtd.writesize / nand_chip->ecc.size,
1980                                  nand_chip->ecc.size, nand_chip->ecc.bytes);
1981                 if (err < 0)
1982                         goto return_error;
1983
1984                 /* define ECC layout */
1985                 ecclayout->eccbytes             = nand_chip->ecc.bytes *
1986                                                         (mtd->writesize /
1987                                                         nand_chip->ecc.size);
1988                 oob_index                       = BADBLOCK_MARKER_LENGTH;
1989                 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1990                         ecclayout->eccpos[i]    = oob_index;
1991                 /* reserved marker already included in ecclayout->eccbytes */
1992                 ecclayout->oobfree->offset      =
1993                                 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1994                 break;
1995
1996         case OMAP_ECC_BCH16_CODE_HW:
1997                 pr_info("using OMAP_ECC_BCH16_CODE_HW ECC scheme\n");
1998                 nand_chip->ecc.mode             = NAND_ECC_HW;
1999                 nand_chip->ecc.size             = 512;
2000                 nand_chip->ecc.bytes            = 26;
2001                 nand_chip->ecc.strength         = 16;
2002                 nand_chip->ecc.hwctl            = omap_enable_hwecc_bch;
2003                 nand_chip->ecc.correct          = omap_elm_correct_data;
2004                 nand_chip->ecc.calculate        = omap_calculate_ecc_bch;
2005                 nand_chip->ecc.read_page        = omap_read_page_bch;
2006                 nand_chip->ecc.write_page       = omap_write_page_bch;
2007
2008                 err = elm_config(info->elm_dev, BCH16_ECC,
2009                                  info->mtd.writesize / nand_chip->ecc.size,
2010                                  nand_chip->ecc.size, nand_chip->ecc.bytes);
2011                 if (err < 0)
2012                         goto return_error;
2013
2014                 /* define ECC layout */
2015                 ecclayout->eccbytes             = nand_chip->ecc.bytes *
2016                                                         (mtd->writesize /
2017                                                         nand_chip->ecc.size);
2018                 oob_index                       = BADBLOCK_MARKER_LENGTH;
2019                 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
2020                         ecclayout->eccpos[i]    = oob_index;
2021                 /* reserved marker already included in ecclayout->eccbytes */
2022                 ecclayout->oobfree->offset      =
2023                                 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
2024                 break;
2025         default:
2026                 dev_err(&info->pdev->dev, "invalid or unsupported ECC scheme\n");
2027                 err = -EINVAL;
2028                 goto return_error;
2029         }
2030
2031         if (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW)
2032                 goto scan_tail;
2033
2034         /* all OOB bytes from oobfree->offset till end off OOB are free */
2035         ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset;
2036         /* check if NAND device's OOB is enough to store ECC signatures */
2037         if (mtd->oobsize < (ecclayout->eccbytes + BADBLOCK_MARKER_LENGTH)) {
2038                 dev_err(&info->pdev->dev,
2039                         "not enough OOB bytes required = %d, available=%d\n",
2040                         ecclayout->eccbytes, mtd->oobsize);
2041                 err = -EINVAL;
2042                 goto return_error;
2043         }
2044         nand_chip->ecc.layout = ecclayout;
2045
2046 scan_tail:
2047         /* second phase scan */
2048         if (nand_scan_tail(mtd)) {
2049                 err = -ENXIO;
2050                 goto return_error;
2051         }
2052
2053         ppdata.of_node = pdata->of_node;
2054         mtd_device_parse_register(mtd, NULL, &ppdata, pdata->parts,
2055                                   pdata->nr_parts);
2056
2057         platform_set_drvdata(pdev, mtd);
2058
2059         return 0;
2060
2061 return_error:
2062         if (info->dma)
2063                 dma_release_channel(info->dma);
2064         if (nand_chip->ecc.priv) {
2065                 nand_bch_free(nand_chip->ecc.priv);
2066                 nand_chip->ecc.priv = NULL;
2067         }
2068         return err;
2069 }
2070
2071 static int omap_nand_remove(struct platform_device *pdev)
2072 {
2073         struct mtd_info *mtd = platform_get_drvdata(pdev);
2074         struct nand_chip *nand_chip = mtd->priv;
2075         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
2076                                                         mtd);
2077         if (nand_chip->ecc.priv) {
2078                 nand_bch_free(nand_chip->ecc.priv);
2079                 nand_chip->ecc.priv = NULL;
2080         }
2081         if (info->dma)
2082                 dma_release_channel(info->dma);
2083         nand_release(mtd);
2084         return 0;
2085 }
2086
2087 static struct platform_driver omap_nand_driver = {
2088         .probe          = omap_nand_probe,
2089         .remove         = omap_nand_remove,
2090         .driver         = {
2091                 .name   = DRIVER_NAME,
2092         },
2093 };
2094
2095 module_platform_driver(omap_nand_driver);
2096
2097 MODULE_ALIAS("platform:" DRIVER_NAME);
2098 MODULE_LICENSE("GPL");
2099 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");