drivers/mtd/nand/omap2.c

   1 /*
   2  * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
   3  * Copyright © 2004 Micron Technology Inc.
   4  * Copyright © 2004 David Brownell
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/platform_device.h>
  12 #include <linux/dmaengine.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/delay.h>
  15 #include <linux/module.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/jiffies.h>
  18 #include <linux/sched.h>
  19 #include <linux/mtd/mtd.h>
  20 #include <linux/mtd/nand.h>
  21 #include <linux/mtd/partitions.h>
  22 #include <linux/omap-dma.h>
  23 #include <linux/io.h>
  24 #include <linux/slab.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27
  28 #include <linux/mtd/nand_bch.h>
  29 #include <linux/platform_data/elm.h>
  30
  31 #include <linux/platform_data/mtd-nand-omap2.h>
  32
  33 #define DRIVER_NAME     "omap2-nand"
  34 #define OMAP_NAND_TIMEOUT_MS    5000
  35
  36 #define NAND_Ecc_P1e            (1 << 0)
  37 #define NAND_Ecc_P2e            (1 << 1)
  38 #define NAND_Ecc_P4e            (1 << 2)
  39 #define NAND_Ecc_P8e            (1 << 3)
  40 #define NAND_Ecc_P16e           (1 << 4)
  41 #define NAND_Ecc_P32e           (1 << 5)
  42 #define NAND_Ecc_P64e           (1 << 6)
  43 #define NAND_Ecc_P128e          (1 << 7)
  44 #define NAND_Ecc_P256e          (1 << 8)
  45 #define NAND_Ecc_P512e          (1 << 9)
  46 #define NAND_Ecc_P1024e         (1 << 10)
  47 #define NAND_Ecc_P2048e         (1 << 11)
  48
  49 #define NAND_Ecc_P1o            (1 << 16)
  50 #define NAND_Ecc_P2o            (1 << 17)
  51 #define NAND_Ecc_P4o            (1 << 18)
  52 #define NAND_Ecc_P8o            (1 << 19)
  53 #define NAND_Ecc_P16o           (1 << 20)
  54 #define NAND_Ecc_P32o           (1 << 21)
  55 #define NAND_Ecc_P64o           (1 << 22)
  56 #define NAND_Ecc_P128o          (1 << 23)
  57 #define NAND_Ecc_P256o          (1 << 24)
  58 #define NAND_Ecc_P512o          (1 << 25)
  59 #define NAND_Ecc_P1024o         (1 << 26)
  60 #define NAND_Ecc_P2048o         (1 << 27)
  61
  62 #define TF(value)       (value ? 1 : 0)
  63
  64 #define P2048e(a)       (TF(a & NAND_Ecc_P2048e)        << 0)
  65 #define P2048o(a)       (TF(a & NAND_Ecc_P2048o)        << 1)
  66 #define P1e(a)          (TF(a & NAND_Ecc_P1e)           << 2)
  67 #define P1o(a)          (TF(a & NAND_Ecc_P1o)           << 3)
  68 #define P2e(a)          (TF(a & NAND_Ecc_P2e)           << 4)
  69 #define P2o(a)          (TF(a & NAND_Ecc_P2o)           << 5)
  70 #define P4e(a)          (TF(a & NAND_Ecc_P4e)           << 6)
  71 #define P4o(a)          (TF(a & NAND_Ecc_P4o)           << 7)
  72
  73 #define P8e(a)          (TF(a & NAND_Ecc_P8e)           << 0)
  74 #define P8o(a)          (TF(a & NAND_Ecc_P8o)           << 1)
  75 #define P16e(a)         (TF(a & NAND_Ecc_P16e)          << 2)
  76 #define P16o(a)         (TF(a & NAND_Ecc_P16o)          << 3)
  77 #define P32e(a)         (TF(a & NAND_Ecc_P32e)          << 4)
  78 #define P32o(a)         (TF(a & NAND_Ecc_P32o)          << 5)
  79 #define P64e(a)         (TF(a & NAND_Ecc_P64e)          << 6)
  80 #define P64o(a)         (TF(a & NAND_Ecc_P64o)          << 7)
  81
  82 #define P128e(a)        (TF(a & NAND_Ecc_P128e)         << 0)
  83 #define P128o(a)        (TF(a & NAND_Ecc_P128o)         << 1)
  84 #define P256e(a)        (TF(a & NAND_Ecc_P256e)         << 2)
  85 #define P256o(a)        (TF(a & NAND_Ecc_P256o)         << 3)
  86 #define P512e(a)        (TF(a & NAND_Ecc_P512e)         << 4)
  87 #define P512o(a)        (TF(a & NAND_Ecc_P512o)         << 5)
  88 #define P1024e(a)       (TF(a & NAND_Ecc_P1024e)        << 6)
  89 #define P1024o(a)       (TF(a & NAND_Ecc_P1024o)        << 7)
  90
  91 #define P8e_s(a)        (TF(a & NAND_Ecc_P8e)           << 0)
  92 #define P8o_s(a)        (TF(a & NAND_Ecc_P8o)           << 1)
  93 #define P16e_s(a)       (TF(a & NAND_Ecc_P16e)          << 2)
  94 #define P16o_s(a)       (TF(a & NAND_Ecc_P16o)          << 3)
  95 #define P1e_s(a)        (TF(a & NAND_Ecc_P1e)           << 4)
  96 #define P1o_s(a)        (TF(a & NAND_Ecc_P1o)           << 5)
  97 #define P2e_s(a)        (TF(a & NAND_Ecc_P2e)           << 6)
  98 #define P2o_s(a)        (TF(a & NAND_Ecc_P2o)           << 7)
  99
 100 #define P4e_s(a)        (TF(a & NAND_Ecc_P4e)           << 0)
 101 #define P4o_s(a)        (TF(a & NAND_Ecc_P4o)           << 1)
 102
 103 #define PREFETCH_CONFIG1_CS_SHIFT       24
 104 #define ECC_CONFIG_CS_SHIFT             1
 105 #define CS_MASK                         0x7
 106 #define ENABLE_PREFETCH                 (0x1 << 7)
 107 #define DMA_MPU_MODE_SHIFT              2
 108 #define ECCSIZE0_SHIFT                  12
 109 #define ECCSIZE1_SHIFT                  22
 110 #define ECC1RESULTSIZE                  0x1
 111 #define ECCCLEAR                        0x100
 112 #define ECC1                            0x1
 113 #define PREFETCH_FIFOTHRESHOLD_MAX      0x40
 114 #define PREFETCH_FIFOTHRESHOLD(val)     ((val) << 8)
 115 #define PREFETCH_STATUS_COUNT(val)      (val & 0x00003fff)
 116 #define PREFETCH_STATUS_FIFO_CNT(val)   ((val >> 24) & 0x7F)
 117 #define STATUS_BUFF_EMPTY               0x00000001
 118
 119 #define OMAP24XX_DMA_GPMC               4
 120
 121 #define BCH8_MAX_ERROR          8       /* upto 8 bit correctable */
 122 #define BCH4_MAX_ERROR          4       /* upto 4 bit correctable */
 123
 124 #define SECTOR_BYTES            512
 125 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
 126 #define BCH4_BIT_PAD            4
 127 #define BCH8_ECC_MAX            ((SECTOR_BYTES + BCH8_ECC_OOB_BYTES) * 8)
 128 #define BCH4_ECC_MAX            ((SECTOR_BYTES + BCH4_ECC_OOB_BYTES) * 8)
 129
 130 /* GPMC ecc engine settings for read */
 131 #define BCH_WRAPMODE_1          1       /* BCH wrap mode 1 */
 132 #define BCH8R_ECC_SIZE0         0x1a    /* ecc_size0 = 26 */
 133 #define BCH8R_ECC_SIZE1         0x2     /* ecc_size1 = 2 */
 134 #define BCH4R_ECC_SIZE0         0xd     /* ecc_size0 = 13 */
 135 #define BCH4R_ECC_SIZE1         0x3     /* ecc_size1 = 3 */
 136
 137 /* GPMC ecc engine settings for write */
 138 #define BCH_WRAPMODE_6          6       /* BCH wrap mode 6 */
 139 #define BCH_ECC_SIZE0           0x0     /* ecc_size0 = 0, no oob protection */
 140 #define BCH_ECC_SIZE1           0x20    /* ecc_size1 = 32 */
 141
 142 #define BADBLOCK_MARKER_LENGTH          2
 143
 144 #ifdef CONFIG_MTD_NAND_OMAP_BCH
 145 static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,
 146         0xac, 0x6b, 0xff, 0x99, 0x7b};
 147 static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10};
 148 #endif
 149
 150 /* oob info generated runtime depending on ecc algorithm and layout selected */
 151 static struct nand_ecclayout omap_oobinfo;
 152
 153 struct omap_nand_info {
 154         struct nand_hw_control          controller;
 155         struct omap_nand_platform_data  *pdata;
 156         struct mtd_info                 mtd;
 157         struct nand_chip                nand;
 158         struct platform_device          *pdev;
 159
 160         int                             gpmc_cs;
 161         unsigned long                   phys_base;
 162         unsigned long                   mem_size;
 163         struct completion               comp;
 164         struct dma_chan                 *dma;
 165         int                             gpmc_irq_fifo;
 166         int                             gpmc_irq_count;
 167         enum {
 168                 OMAP_NAND_IO_READ = 0,  /* read */
 169                 OMAP_NAND_IO_WRITE,     /* write */
 170         } iomode;
 171         u_char                          *buf;
 172         int                                     buf_len;
 173         struct gpmc_nand_regs           reg;
 174         /* fields specific for BCHx_HW ECC scheme */
 175         bool                            is_elm_used;
 176         struct device                   *elm_dev;
 177         struct device_node              *of_node;
 178 };
 179
 180 /**
 181  * omap_prefetch_enable - configures and starts prefetch transfer
 182  * @cs: cs (chip select) number
 183  * @fifo_th: fifo threshold to be used for read/ write
 184  * @dma_mode: dma mode enable (1) or disable (0)
 185  * @u32_count: number of bytes to be transferred
 186  * @is_write: prefetch read(0) or write post(1) mode
 187  */
 188 static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode,
 189         unsigned int u32_count, int is_write, struct omap_nand_info *info)
 190 {
 191         u32 val;
 192
 193         if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
 194                 return -1;
 195
 196         if (readl(info->reg.gpmc_prefetch_control))
 197                 return -EBUSY;
 198
 199         /* Set the amount of bytes to be prefetched */
 200         writel(u32_count, info->reg.gpmc_prefetch_config2);
 201
 202         /* Set dma/mpu mode, the prefetch read / post write and
 203          * enable the engine. Set which cs is has requested for.
 204          */
 205         val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) |
 206                 PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH |
 207                 (dma_mode << DMA_MPU_MODE_SHIFT) | (0x1 & is_write));
 208         writel(val, info->reg.gpmc_prefetch_config1);
 209
 210         /*  Start the prefetch engine */
 211         writel(0x1, info->reg.gpmc_prefetch_control);
 212
 213         return 0;
 214 }
 215
 216 /**
 217  * omap_prefetch_reset - disables and stops the prefetch engine
 218  */
 219 static int omap_prefetch_reset(int cs, struct omap_nand_info *info)
 220 {
 221         u32 config1;
 222
 223         /* check if the same module/cs is trying to reset */
 224         config1 = readl(info->reg.gpmc_prefetch_config1);
 225         if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs)
 226                 return -EINVAL;
 227
 228         /* Stop the PFPW engine */
 229         writel(0x0, info->reg.gpmc_prefetch_control);
 230
 231         /* Reset/disable the PFPW engine */
 232         writel(0x0, info->reg.gpmc_prefetch_config1);
 233
 234         return 0;
 235 }
 236
 237 /**
 238  * omap_hwcontrol - hardware specific access to control-lines
 239  * @mtd: MTD device structure
 240  * @cmd: command to device
 241  * @ctrl:
 242  * NAND_NCE: bit 0 -> don't care
 243  * NAND_CLE: bit 1 -> Command Latch
 244  * NAND_ALE: bit 2 -> Address Latch
 245  *
 246  * NOTE: boards may use different bits for these!!
 247  */
 248 static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 249 {
 250         struct omap_nand_info *info = container_of(mtd,
 251                                         struct omap_nand_info, mtd);
 252
 253         if (cmd != NAND_CMD_NONE) {
 254                 if (ctrl & NAND_CLE)
 255                         writeb(cmd, info->reg.gpmc_nand_command);
 256
 257                 else if (ctrl & NAND_ALE)
 258                         writeb(cmd, info->reg.gpmc_nand_address);
 259
 260                 else /* NAND_NCE */
 261                         writeb(cmd, info->reg.gpmc_nand_data);
 262         }
 263 }
 264
 265 /**
 266  * omap_read_buf8 - read data from NAND controller into buffer
 267  * @mtd: MTD device structure
 268  * @buf: buffer to store date
 269  * @len: number of bytes to read
 270  */
 271 static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
 272 {
 273         struct nand_chip *nand = mtd->priv;
 274
 275         ioread8_rep(nand->IO_ADDR_R, buf, len);
 276 }
 277
 278 /**
 279  * omap_write_buf8 - write buffer to NAND controller
 280  * @mtd: MTD device structure
 281  * @buf: data buffer
 282  * @len: number of bytes to write
 283  */
 284 static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
 285 {
 286         struct omap_nand_info *info = container_of(mtd,
 287                                                 struct omap_nand_info, mtd);
 288         u_char *p = (u_char *)buf;
 289         u32     status = 0;
 290
 291         while (len--) {
 292                 iowrite8(*p++, info->nand.IO_ADDR_W);
 293                 /* wait until buffer is available for write */
 294                 do {
 295                         status = readl(info->reg.gpmc_status) &
 296                                         STATUS_BUFF_EMPTY;
 297                 } while (!status);
 298         }
 299 }
 300
 301 /**
 302  * omap_read_buf16 - read data from NAND controller into buffer
 303  * @mtd: MTD device structure
 304  * @buf: buffer to store date
 305  * @len: number of bytes to read
 306  */
 307 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
 308 {
 309         struct nand_chip *nand = mtd->priv;
 310
 311         ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
 312 }
 313
 314 /**
 315  * omap_write_buf16 - write buffer to NAND controller
 316  * @mtd: MTD device structure
 317  * @buf: data buffer
 318  * @len: number of bytes to write
 319  */
 320 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
 321 {
 322         struct omap_nand_info *info = container_of(mtd,
 323                                                 struct omap_nand_info, mtd);
 324         u16 *p = (u16 *) buf;
 325         u32     status = 0;
 326         /* FIXME try bursts of writesw() or DMA ... */
 327         len >>= 1;
 328
 329         while (len--) {
 330                 iowrite16(*p++, info->nand.IO_ADDR_W);
 331                 /* wait until buffer is available for write */
 332                 do {
 333                         status = readl(info->reg.gpmc_status) &
 334                                         STATUS_BUFF_EMPTY;
 335                 } while (!status);
 336         }
 337 }
 338
 339 /**
 340  * omap_read_buf_pref - read data from NAND controller into buffer
 341  * @mtd: MTD device structure
 342  * @buf: buffer to store date
 343  * @len: number of bytes to read
 344  */
 345 static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
 346 {
 347         struct omap_nand_info *info = container_of(mtd,
 348                                                 struct omap_nand_info, mtd);
 349         uint32_t r_count = 0;
 350         int ret = 0;
 351         u32 *p = (u32 *)buf;
 352
 353         /* take care of subpage reads */
 354         if (len % 4) {
 355                 if (info->nand.options & NAND_BUSWIDTH_16)
 356                         omap_read_buf16(mtd, buf, len % 4);
 357                 else
 358                         omap_read_buf8(mtd, buf, len % 4);
 359                 p = (u32 *) (buf + len % 4);
 360                 len -= len % 4;
 361         }
 362
 363         /* configure and start prefetch transfer */
 364         ret = omap_prefetch_enable(info->gpmc_cs,
 365                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info);
 366         if (ret) {
 367                 /* PFPW engine is busy, use cpu copy method */
 368                 if (info->nand.options & NAND_BUSWIDTH_16)
 369                         omap_read_buf16(mtd, (u_char *)p, len);
 370                 else
 371                         omap_read_buf8(mtd, (u_char *)p, len);
 372         } else {
 373                 do {
 374                         r_count = readl(info->reg.gpmc_prefetch_status);
 375                         r_count = PREFETCH_STATUS_FIFO_CNT(r_count);
 376                         r_count = r_count >> 2;
 377                         ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
 378                         p += r_count;
 379                         len -= r_count << 2;
 380                 } while (len);
 381                 /* disable and stop the PFPW engine */
 382                 omap_prefetch_reset(info->gpmc_cs, info);
 383         }
 384 }
 385
 386 /**
 387  * omap_write_buf_pref - write buffer to NAND controller
 388  * @mtd: MTD device structure
 389  * @buf: data buffer
 390  * @len: number of bytes to write
 391  */
 392 static void omap_write_buf_pref(struct mtd_info *mtd,
 393                                         const u_char *buf, int len)
 394 {
 395         struct omap_nand_info *info = container_of(mtd,
 396                                                 struct omap_nand_info, mtd);
 397         uint32_t w_count = 0;
 398         int i = 0, ret = 0;
 399         u16 *p = (u16 *)buf;
 400         unsigned long tim, limit;
 401         u32 val;
 402
 403         /* take care of subpage writes */
 404         if (len % 2 != 0) {
 405                 writeb(*buf, info->nand.IO_ADDR_W);
 406                 p = (u16 *)(buf + 1);
 407                 len--;
 408         }
 409
 410         /*  configure and start prefetch transfer */
 411         ret = omap_prefetch_enable(info->gpmc_cs,
 412                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info);
 413         if (ret) {
 414                 /* PFPW engine is busy, use cpu copy method */
 415                 if (info->nand.options & NAND_BUSWIDTH_16)
 416                         omap_write_buf16(mtd, (u_char *)p, len);
 417                 else
 418                         omap_write_buf8(mtd, (u_char *)p, len);
 419         } else {
 420                 while (len) {
 421                         w_count = readl(info->reg.gpmc_prefetch_status);
 422                         w_count = PREFETCH_STATUS_FIFO_CNT(w_count);
 423                         w_count = w_count >> 1;
 424                         for (i = 0; (i < w_count) && len; i++, len -= 2)
 425                                 iowrite16(*p++, info->nand.IO_ADDR_W);
 426                 }
 427                 /* wait for data to flushed-out before reset the prefetch */
 428                 tim = 0;
 429                 limit = (loops_per_jiffy *
 430                                         msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 431                 do {
 432                         cpu_relax();
 433                         val = readl(info->reg.gpmc_prefetch_status);
 434                         val = PREFETCH_STATUS_COUNT(val);
 435                 } while (val && (tim++ < limit));
 436
 437                 /* disable and stop the PFPW engine */
 438                 omap_prefetch_reset(info->gpmc_cs, info);
 439         }
 440 }
 441
 442 /*
 443  * omap_nand_dma_callback: callback on the completion of dma transfer
 444  * @data: pointer to completion data structure
 445  */
 446 static void omap_nand_dma_callback(void *data)
 447 {
 448         complete((struct completion *) data);
 449 }
 450
 451 /*
 452  * omap_nand_dma_transfer: configure and start dma transfer
 453  * @mtd: MTD device structure
 454  * @addr: virtual address in RAM of source/destination
 455  * @len: number of data bytes to be transferred
 456  * @is_write: flag for read/write operation
 457  */
 458 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
 459                                         unsigned int len, int is_write)
 460 {
 461         struct omap_nand_info *info = container_of(mtd,
 462                                         struct omap_nand_info, mtd);
 463         struct dma_async_tx_descriptor *tx;
 464         enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
 465                                                         DMA_FROM_DEVICE;
 466         struct scatterlist sg;
 467         unsigned long tim, limit;
 468         unsigned n;
 469         int ret;
 470         u32 val;
 471
 472         if (addr >= high_memory) {
 473                 struct page *p1;
 474
 475                 if (((size_t)addr & PAGE_MASK) !=
 476                         ((size_t)(addr + len - 1) & PAGE_MASK))
 477                         goto out_copy;
 478                 p1 = vmalloc_to_page(addr);
 479                 if (!p1)
 480                         goto out_copy;
 481                 addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK);
 482         }
 483
 484         sg_init_one(&sg, addr, len);
 485         n = dma_map_sg(info->dma->device->dev, &sg, 1, dir);
 486         if (n == 0) {
 487                 dev_err(&info->pdev->dev,
 488                         "Couldn't DMA map a %d byte buffer\n", len);
 489                 goto out_copy;
 490         }
 491
 492         tx = dmaengine_prep_slave_sg(info->dma, &sg, n,
 493                 is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
 494                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 495         if (!tx)
 496                 goto out_copy_unmap;
 497
 498         tx->callback = omap_nand_dma_callback;
 499         tx->callback_param = &info->comp;
 500         dmaengine_submit(tx);
 501
 502         /*  configure and start prefetch transfer */
 503         ret = omap_prefetch_enable(info->gpmc_cs,
 504                 PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info);
 505         if (ret)
 506                 /* PFPW engine is busy, use cpu copy method */
 507                 goto out_copy_unmap;
 508
 509         init_completion(&info->comp);
 510         dma_async_issue_pending(info->dma);
 511
 512         /* setup and start DMA using dma_addr */
 513         wait_for_completion(&info->comp);
 514         tim = 0;
 515         limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 516
 517         do {
 518                 cpu_relax();
 519                 val = readl(info->reg.gpmc_prefetch_status);
 520                 val = PREFETCH_STATUS_COUNT(val);
 521         } while (val && (tim++ < limit));
 522
 523         /* disable and stop the PFPW engine */
 524         omap_prefetch_reset(info->gpmc_cs, info);
 525
 526         dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
 527         return 0;
 528
 529 out_copy_unmap:
 530         dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
 531 out_copy:
 532         if (info->nand.options & NAND_BUSWIDTH_16)
 533                 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
 534                         : omap_write_buf16(mtd, (u_char *) addr, len);
 535         else
 536                 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
 537                         : omap_write_buf8(mtd, (u_char *) addr, len);
 538         return 0;
 539 }
 540
 541 /**
 542  * omap_read_buf_dma_pref - read data from NAND controller into buffer
 543  * @mtd: MTD device structure
 544  * @buf: buffer to store date
 545  * @len: number of bytes to read
 546  */
 547 static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
 548 {
 549         if (len <= mtd->oobsize)
 550                 omap_read_buf_pref(mtd, buf, len);
 551         else
 552                 /* start transfer in DMA mode */
 553                 omap_nand_dma_transfer(mtd, buf, len, 0x0);
 554 }
 555
 556 /**
 557  * omap_write_buf_dma_pref - write buffer to NAND controller
 558  * @mtd: MTD device structure
 559  * @buf: data buffer
 560  * @len: number of bytes to write
 561  */
 562 static void omap_write_buf_dma_pref(struct mtd_info *mtd,
 563                                         const u_char *buf, int len)
 564 {
 565         if (len <= mtd->oobsize)
 566                 omap_write_buf_pref(mtd, buf, len);
 567         else
 568                 /* start transfer in DMA mode */
 569                 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
 570 }
 571
 572 /*
 573  * omap_nand_irq - GPMC irq handler
 574  * @this_irq: gpmc irq number
 575  * @dev: omap_nand_info structure pointer is passed here
 576  */
 577 static irqreturn_t omap_nand_irq(int this_irq, void *dev)
 578 {
 579         struct omap_nand_info *info = (struct omap_nand_info *) dev;
 580         u32 bytes;
 581
 582         bytes = readl(info->reg.gpmc_prefetch_status);
 583         bytes = PREFETCH_STATUS_FIFO_CNT(bytes);
 584         bytes = bytes  & 0xFFFC; /* io in multiple of 4 bytes */
 585         if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
 586                 if (this_irq == info->gpmc_irq_count)
 587                         goto done;
 588
 589                 if (info->buf_len && (info->buf_len < bytes))
 590                         bytes = info->buf_len;
 591                 else if (!info->buf_len)
 592                         bytes = 0;
 593                 iowrite32_rep(info->nand.IO_ADDR_W,
 594                                                 (u32 *)info->buf, bytes >> 2);
 595                 info->buf = info->buf + bytes;
 596                 info->buf_len -= bytes;
 597
 598         } else {
 599                 ioread32_rep(info->nand.IO_ADDR_R,
 600                                                 (u32 *)info->buf, bytes >> 2);
 601                 info->buf = info->buf + bytes;
 602
 603                 if (this_irq == info->gpmc_irq_count)
 604                         goto done;
 605         }
 606
 607         return IRQ_HANDLED;
 608
 609 done:
 610         complete(&info->comp);
 611
 612         disable_irq_nosync(info->gpmc_irq_fifo);
 613         disable_irq_nosync(info->gpmc_irq_count);
 614
 615         return IRQ_HANDLED;
 616 }
 617
 618 /*
 619  * omap_read_buf_irq_pref - read data from NAND controller into buffer
 620  * @mtd: MTD device structure
 621  * @buf: buffer to store date
 622  * @len: number of bytes to read
 623  */
 624 static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
 625 {
 626         struct omap_nand_info *info = container_of(mtd,
 627                                                 struct omap_nand_info, mtd);
 628         int ret = 0;
 629
 630         if (len <= mtd->oobsize) {
 631                 omap_read_buf_pref(mtd, buf, len);
 632                 return;
 633         }
 634
 635         info->iomode = OMAP_NAND_IO_READ;
 636         info->buf = buf;
 637         init_completion(&info->comp);
 638
 639         /*  configure and start prefetch transfer */
 640         ret = omap_prefetch_enable(info->gpmc_cs,
 641                         PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info);
 642         if (ret)
 643                 /* PFPW engine is busy, use cpu copy method */
 644                 goto out_copy;
 645
 646         info->buf_len = len;
 647
 648         enable_irq(info->gpmc_irq_count);
 649         enable_irq(info->gpmc_irq_fifo);
 650
 651         /* waiting for read to complete */
 652         wait_for_completion(&info->comp);
 653
 654         /* disable and stop the PFPW engine */
 655         omap_prefetch_reset(info->gpmc_cs, info);
 656         return;
 657
 658 out_copy:
 659         if (info->nand.options & NAND_BUSWIDTH_16)
 660                 omap_read_buf16(mtd, buf, len);
 661         else
 662                 omap_read_buf8(mtd, buf, len);
 663 }
 664
 665 /*
 666  * omap_write_buf_irq_pref - write buffer to NAND controller
 667  * @mtd: MTD device structure
 668  * @buf: data buffer
 669  * @len: number of bytes to write
 670  */
 671 static void omap_write_buf_irq_pref(struct mtd_info *mtd,
 672                                         const u_char *buf, int len)
 673 {
 674         struct omap_nand_info *info = container_of(mtd,
 675                                                 struct omap_nand_info, mtd);
 676         int ret = 0;
 677         unsigned long tim, limit;
 678         u32 val;
 679
 680         if (len <= mtd->oobsize) {
 681                 omap_write_buf_pref(mtd, buf, len);
 682                 return;
 683         }
 684
 685         info->iomode = OMAP_NAND_IO_WRITE;
 686         info->buf = (u_char *) buf;
 687         init_completion(&info->comp);
 688
 689         /* configure and start prefetch transfer : size=24 */
 690         ret = omap_prefetch_enable(info->gpmc_cs,
 691                 (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info);
 692         if (ret)
 693                 /* PFPW engine is busy, use cpu copy method */
 694                 goto out_copy;
 695
 696         info->buf_len = len;
 697
 698         enable_irq(info->gpmc_irq_count);
 699         enable_irq(info->gpmc_irq_fifo);
 700
 701         /* waiting for write to complete */
 702         wait_for_completion(&info->comp);
 703
 704         /* wait for data to flushed-out before reset the prefetch */
 705         tim = 0;
 706         limit = (loops_per_jiffy *  msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 707         do {
 708                 val = readl(info->reg.gpmc_prefetch_status);
 709                 val = PREFETCH_STATUS_COUNT(val);
 710                 cpu_relax();
 711         } while (val && (tim++ < limit));
 712
 713         /* disable and stop the PFPW engine */
 714         omap_prefetch_reset(info->gpmc_cs, info);
 715         return;
 716
 717 out_copy:
 718         if (info->nand.options & NAND_BUSWIDTH_16)
 719                 omap_write_buf16(mtd, buf, len);
 720         else
 721                 omap_write_buf8(mtd, buf, len);
 722 }
 723
 724 /**
 725  * gen_true_ecc - This function will generate true ECC value
 726  * @ecc_buf: buffer to store ecc code
 727  *
 728  * This generated true ECC value can be used when correcting
 729  * data read from NAND flash memory core
 730  */
 731 static void gen_true_ecc(u8 *ecc_buf)
 732 {
 733         u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
 734                 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
 735
 736         ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
 737                         P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
 738         ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
 739                         P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
 740         ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
 741                         P1e(tmp) | P2048o(tmp) | P2048e(tmp));
 742 }
 743
 744 /**
 745  * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
 746  * @ecc_data1:  ecc code from nand spare area
 747  * @ecc_data2:  ecc code from hardware register obtained from hardware ecc
 748  * @page_data:  page data
 749  *
 750  * This function compares two ECC's and indicates if there is an error.
 751  * If the error can be corrected it will be corrected to the buffer.
 752  * If there is no error, %0 is returned. If there is an error but it
 753  * was corrected, %1 is returned. Otherwise, %-1 is returned.
 754  */
 755 static int omap_compare_ecc(u8 *ecc_data1,      /* read from NAND memory */
 756                             u8 *ecc_data2,      /* read from register */
 757                             u8 *page_data)
 758 {
 759         uint    i;
 760         u8      tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
 761         u8      comp0_bit[8], comp1_bit[8], comp2_bit[8];
 762         u8      ecc_bit[24];
 763         u8      ecc_sum = 0;
 764         u8      find_bit = 0;
 765         uint    find_byte = 0;
 766         int     isEccFF;
 767
 768         isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
 769
 770         gen_true_ecc(ecc_data1);
 771         gen_true_ecc(ecc_data2);
 772
 773         for (i = 0; i <= 2; i++) {
 774                 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
 775                 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
 776         }
 777
 778         for (i = 0; i < 8; i++) {
 779                 tmp0_bit[i]     = *ecc_data1 % 2;
 780                 *ecc_data1      = *ecc_data1 / 2;
 781         }
 782
 783         for (i = 0; i < 8; i++) {
 784                 tmp1_bit[i]      = *(ecc_data1 + 1) % 2;
 785                 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
 786         }
 787
 788         for (i = 0; i < 8; i++) {
 789                 tmp2_bit[i]      = *(ecc_data1 + 2) % 2;
 790                 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
 791         }
 792
 793         for (i = 0; i < 8; i++) {
 794                 comp0_bit[i]     = *ecc_data2 % 2;
 795                 *ecc_data2       = *ecc_data2 / 2;
 796         }
 797
 798         for (i = 0; i < 8; i++) {
 799                 comp1_bit[i]     = *(ecc_data2 + 1) % 2;
 800                 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
 801         }
 802
 803         for (i = 0; i < 8; i++) {
 804                 comp2_bit[i]     = *(ecc_data2 + 2) % 2;
 805                 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
 806         }
 807
 808         for (i = 0; i < 6; i++)
 809                 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
 810
 811         for (i = 0; i < 8; i++)
 812                 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
 813
 814         for (i = 0; i < 8; i++)
 815                 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
 816
 817         ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
 818         ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
 819
 820         for (i = 0; i < 24; i++)
 821                 ecc_sum += ecc_bit[i];
 822
 823         switch (ecc_sum) {
 824         case 0:
 825                 /* Not reached because this function is not called if
 826                  *  ECC values are equal
 827                  */
 828                 return 0;
 829
 830         case 1:
 831                 /* Uncorrectable error */
 832                 pr_debug("ECC UNCORRECTED_ERROR 1\n");
 833                 return -1;
 834
 835         case 11:
 836                 /* UN-Correctable error */
 837                 pr_debug("ECC UNCORRECTED_ERROR B\n");
 838                 return -1;
 839
 840         case 12:
 841                 /* Correctable error */
 842                 find_byte = (ecc_bit[23] << 8) +
 843                             (ecc_bit[21] << 7) +
 844                             (ecc_bit[19] << 6) +
 845                             (ecc_bit[17] << 5) +
 846                             (ecc_bit[15] << 4) +
 847                             (ecc_bit[13] << 3) +
 848                             (ecc_bit[11] << 2) +
 849                             (ecc_bit[9]  << 1) +
 850                             ecc_bit[7];
 851
 852                 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
 853
 854                 pr_debug("Correcting single bit ECC error at offset: "
 855                                 "%d, bit: %d\n", find_byte, find_bit);
 856
 857                 page_data[find_byte] ^= (1 << find_bit);
 858
 859                 return 1;
 860         default:
 861                 if (isEccFF) {
 862                         if (ecc_data2[0] == 0 &&
 863                             ecc_data2[1] == 0 &&
 864                             ecc_data2[2] == 0)
 865                                 return 0;
 866                 }
 867                 pr_debug("UNCORRECTED_ERROR default\n");
 868                 return -1;
 869         }
 870 }
 871
 872 /**
 873  * omap_correct_data - Compares the ECC read with HW generated ECC
 874  * @mtd: MTD device structure
 875  * @dat: page data
 876  * @read_ecc: ecc read from nand flash
 877  * @calc_ecc: ecc read from HW ECC registers
 878  *
 879  * Compares the ecc read from nand spare area with ECC registers values
 880  * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
 881  * detection and correction. If there are no errors, %0 is returned. If
 882  * there were errors and all of the errors were corrected, the number of
 883  * corrected errors is returned. If uncorrectable errors exist, %-1 is
 884  * returned.
 885  */
 886 static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
 887                                 u_char *read_ecc, u_char *calc_ecc)
 888 {
 889         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 890                                                         mtd);
 891         int blockCnt = 0, i = 0, ret = 0;
 892         int stat = 0;
 893
 894         /* Ex NAND_ECC_HW12_2048 */
 895         if ((info->nand.ecc.mode == NAND_ECC_HW) &&
 896                         (info->nand.ecc.size  == 2048))
 897                 blockCnt = 4;
 898         else
 899                 blockCnt = 1;
 900
 901         for (i = 0; i < blockCnt; i++) {
 902                 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
 903                         ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
 904                         if (ret < 0)
 905                                 return ret;
 906                         /* keep track of the number of corrected errors */
 907                         stat += ret;
 908                 }
 909                 read_ecc += 3;
 910                 calc_ecc += 3;
 911                 dat      += 512;
 912         }
 913         return stat;
 914 }
 915
 916 /**
 917  * omap_calcuate_ecc - Generate non-inverted ECC bytes.
 918  * @mtd: MTD device structure
 919  * @dat: The pointer to data on which ecc is computed
 920  * @ecc_code: The ecc_code buffer
 921  *
 922  * Using noninverted ECC can be considered ugly since writing a blank
 923  * page ie. padding will clear the ECC bytes. This is no problem as long
 924  * nobody is trying to write data on the seemingly unused page. Reading
 925  * an erased page will produce an ECC mismatch between generated and read
 926  * ECC bytes that has to be dealt with separately.
 927  */
 928 static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 929                                 u_char *ecc_code)
 930 {
 931         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 932                                                         mtd);
 933         u32 val;
 934
 935         val = readl(info->reg.gpmc_ecc_config);
 936         if (((val >> ECC_CONFIG_CS_SHIFT)  & ~CS_MASK) != info->gpmc_cs)
 937                 return -EINVAL;
 938
 939         /* read ecc result */
 940         val = readl(info->reg.gpmc_ecc1_result);
 941         *ecc_code++ = val;          /* P128e, ..., P1e */
 942         *ecc_code++ = val >> 16;    /* P128o, ..., P1o */
 943         /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
 944         *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
 945
 946         return 0;
 947 }
 948
 949 /**
 950  * omap_enable_hwecc - This function enables the hardware ecc functionality
 951  * @mtd: MTD device structure
 952  * @mode: Read/Write mode
 953  */
 954 static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
 955 {
 956         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 957                                                         mtd);
 958         struct nand_chip *chip = mtd->priv;
 959         unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
 960         u32 val;
 961
 962         /* clear ecc and enable bits */
 963         val = ECCCLEAR | ECC1;
 964         writel(val, info->reg.gpmc_ecc_control);
 965
 966         /* program ecc and result sizes */
 967         val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) |
 968                          ECC1RESULTSIZE);
 969         writel(val, info->reg.gpmc_ecc_size_config);
 970
 971         switch (mode) {
 972         case NAND_ECC_READ:
 973         case NAND_ECC_WRITE:
 974                 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
 975                 break;
 976         case NAND_ECC_READSYN:
 977                 writel(ECCCLEAR, info->reg.gpmc_ecc_control);
 978                 break;
 979         default:
 980                 dev_info(&info->pdev->dev,
 981                         "error: unrecognized Mode[%d]!\n", mode);
 982                 break;
 983         }
 984
 985         /* (ECC 16 or 8 bit col) | ( CS  )  | ECC Enable */
 986         val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
 987         writel(val, info->reg.gpmc_ecc_config);
 988 }
 989
 990 /**
 991  * omap_wait - wait until the command is done
 992  * @mtd: MTD device structure
 993  * @chip: NAND Chip structure
 994  *
 995  * Wait function is called during Program and erase operations and
 996  * the way it is called from MTD layer, we should wait till the NAND
 997  * chip is ready after the programming/erase operation has completed.
 998  *
 999  * Erase can take up to 400ms and program up to 20ms according to
1000  * general NAND and SmartMedia specs
1001  */
1002 static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
1003 {
1004         struct nand_chip *this = mtd->priv;
1005         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1006                                                         mtd);
1007         unsigned long timeo = jiffies;
1008         int status, state = this->state;
1009
1010         if (state == FL_ERASING)
1011                 timeo += msecs_to_jiffies(400);
1012         else
1013                 timeo += msecs_to_jiffies(20);
1014
1015         writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command);
1016         while (time_before(jiffies, timeo)) {
1017                 status = readb(info->reg.gpmc_nand_data);
1018                 if (status & NAND_STATUS_READY)
1019                         break;
1020                 cond_resched();
1021         }
1022
1023         status = readb(info->reg.gpmc_nand_data);
1024         return status;
1025 }
1026
1027 /**
1028  * omap_dev_ready - calls the platform specific dev_ready function
1029  * @mtd: MTD device structure
1030  */
1031 static int omap_dev_ready(struct mtd_info *mtd)
1032 {
1033         unsigned int val = 0;
1034         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1035                                                         mtd);
1036
1037         val = readl(info->reg.gpmc_status);
1038
1039         if ((val & 0x100) == 0x100) {
1040                 return 1;
1041         } else {
1042                 return 0;
1043         }
1044 }
1045
1046 #if defined(CONFIG_MTD_NAND_ECC_BCH) || defined(CONFIG_MTD_NAND_OMAP_BCH)
1047 /**
1048  * omap3_enable_hwecc_bch - Program OMAP3 GPMC to perform BCH ECC correction
1049  * @mtd: MTD device structure
1050  * @mode: Read/Write mode
1051  *
1052  * When using BCH, sector size is hardcoded to 512 bytes.
1053  * Using wrapping mode 6 both for reading and writing if ELM module not uses
1054  * for error correction.
1055  * On writing,
1056  * eccsize0 = 0  (no additional protected byte in spare area)
1057  * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
1058  */
1059 static void omap3_enable_hwecc_bch(struct mtd_info *mtd, int mode)
1060 {
1061         int nerrors;
1062         unsigned int dev_width, nsectors;
1063         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1064                                                    mtd);
1065         struct nand_chip *chip = mtd->priv;
1066         u32 val, wr_mode;
1067         unsigned int ecc_size1, ecc_size0;
1068
1069         /* Using wrapping mode 6 for writing */
1070         wr_mode = BCH_WRAPMODE_6;
1071
1072         /*
1073          * ECC engine enabled for valid ecc_size0 nibbles
1074          * and disabled for ecc_size1 nibbles.
1075          */
1076         ecc_size0 = BCH_ECC_SIZE0;
1077         ecc_size1 = BCH_ECC_SIZE1;
1078
1079         /* Perform ecc calculation on 512-byte sector */
1080         nsectors = 1;
1081
1082         /* Update number of error correction */
1083         nerrors = info->nand.ecc.strength;
1084
1085         /* Multi sector reading/writing for NAND flash with page size < 4096 */
1086         if (info->is_elm_used && (mtd->writesize <= 4096)) {
1087                 if (mode == NAND_ECC_READ) {
1088                         /* Using wrapping mode 1 for reading */
1089                         wr_mode = BCH_WRAPMODE_1;
1090
1091                         /*
1092                          * ECC engine enabled for ecc_size0 nibbles
1093                          * and disabled for ecc_size1 nibbles.
1094                          */
1095                         ecc_size0 = (nerrors == 8) ?
1096                                 BCH8R_ECC_SIZE0 : BCH4R_ECC_SIZE0;
1097                         ecc_size1 = (nerrors == 8) ?
1098                                 BCH8R_ECC_SIZE1 : BCH4R_ECC_SIZE1;
1099                 }
1100
1101                 /* Perform ecc calculation for one page (< 4096) */
1102                 nsectors = info->nand.ecc.steps;
1103         }
1104
1105         writel(ECC1, info->reg.gpmc_ecc_control);
1106
1107         /* Configure ecc size for BCH */
1108         val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT);
1109         writel(val, info->reg.gpmc_ecc_size_config);
1110
1111         dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
1112
1113         /* BCH configuration */
1114         val = ((1                        << 16) | /* enable BCH */
1115                (((nerrors == 8) ? 1 : 0) << 12) | /* 8 or 4 bits */
1116                (wr_mode                  <<  8) | /* wrap mode */
1117                (dev_width                <<  7) | /* bus width */
1118                (((nsectors-1) & 0x7)     <<  4) | /* number of sectors */
1119                (info->gpmc_cs            <<  1) | /* ECC CS */
1120                (0x1));                            /* enable ECC */
1121
1122         writel(val, info->reg.gpmc_ecc_config);
1123
1124         /* Clear ecc and enable bits */
1125         writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
1126 }
1127 #endif
1128
1129 #ifdef CONFIG_MTD_NAND_ECC_BCH
1130 /**
1131  * omap3_calculate_ecc_bch4 - Generate 7 bytes of ECC bytes
1132  * @mtd: MTD device structure
1133  * @dat: The pointer to data on which ecc is computed
1134  * @ecc_code: The ecc_code buffer
1135  */
1136 static int omap3_calculate_ecc_bch4(struct mtd_info *mtd, const u_char *dat,
1137                                     u_char *ecc_code)
1138 {
1139         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1140                                                    mtd);
1141         unsigned long nsectors, val1, val2;
1142         int i;
1143
1144         nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1145
1146         for (i = 0; i < nsectors; i++) {
1147
1148                 /* Read hw-computed remainder */
1149                 val1 = readl(info->reg.gpmc_bch_result0[i]);
1150                 val2 = readl(info->reg.gpmc_bch_result1[i]);
1151
1152                 /*
1153                  * Add constant polynomial to remainder, in order to get an ecc
1154                  * sequence of 0xFFs for a buffer filled with 0xFFs; and
1155                  * left-justify the resulting polynomial.
1156                  */
1157                 *ecc_code++ = 0x28 ^ ((val2 >> 12) & 0xFF);
1158                 *ecc_code++ = 0x13 ^ ((val2 >>  4) & 0xFF);
1159                 *ecc_code++ = 0xcc ^ (((val2 & 0xF) << 4)|((val1 >> 28) & 0xF));
1160                 *ecc_code++ = 0x39 ^ ((val1 >> 20) & 0xFF);
1161                 *ecc_code++ = 0x96 ^ ((val1 >> 12) & 0xFF);
1162                 *ecc_code++ = 0xac ^ ((val1 >> 4) & 0xFF);
1163                 *ecc_code++ = 0x7f ^ ((val1 & 0xF) << 4);
1164         }
1165
1166         return 0;
1167 }
1168
1169 /**
1170  * omap3_calculate_ecc_bch8 - Generate 13 bytes of ECC bytes
1171  * @mtd: MTD device structure
1172  * @dat: The pointer to data on which ecc is computed
1173  * @ecc_code: The ecc_code buffer
1174  */
1175 static int omap3_calculate_ecc_bch8(struct mtd_info *mtd, const u_char *dat,
1176                                     u_char *ecc_code)
1177 {
1178         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1179                                                    mtd);
1180         unsigned long nsectors, val1, val2, val3, val4;
1181         int i;
1182
1183         nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1184
1185         for (i = 0; i < nsectors; i++) {
1186
1187                 /* Read hw-computed remainder */
1188                 val1 = readl(info->reg.gpmc_bch_result0[i]);
1189                 val2 = readl(info->reg.gpmc_bch_result1[i]);
1190                 val3 = readl(info->reg.gpmc_bch_result2[i]);
1191                 val4 = readl(info->reg.gpmc_bch_result3[i]);
1192
1193                 /*
1194                  * Add constant polynomial to remainder, in order to get an ecc
1195                  * sequence of 0xFFs for a buffer filled with 0xFFs.
1196                  */
1197                 *ecc_code++ = 0xef ^ (val4 & 0xFF);
1198                 *ecc_code++ = 0x51 ^ ((val3 >> 24) & 0xFF);
1199                 *ecc_code++ = 0x2e ^ ((val3 >> 16) & 0xFF);
1200                 *ecc_code++ = 0x09 ^ ((val3 >> 8) & 0xFF);
1201                 *ecc_code++ = 0xed ^ (val3 & 0xFF);
1202                 *ecc_code++ = 0x93 ^ ((val2 >> 24) & 0xFF);
1203                 *ecc_code++ = 0x9a ^ ((val2 >> 16) & 0xFF);
1204                 *ecc_code++ = 0xc2 ^ ((val2 >> 8) & 0xFF);
1205                 *ecc_code++ = 0x97 ^ (val2 & 0xFF);
1206                 *ecc_code++ = 0x79 ^ ((val1 >> 24) & 0xFF);
1207                 *ecc_code++ = 0xe5 ^ ((val1 >> 16) & 0xFF);
1208                 *ecc_code++ = 0x24 ^ ((val1 >> 8) & 0xFF);
1209                 *ecc_code++ = 0xb5 ^ (val1 & 0xFF);
1210         }
1211
1212         return 0;
1213 }
1214 #endif /* CONFIG_MTD_NAND_ECC_BCH */
1215
1216 #ifdef CONFIG_MTD_NAND_OMAP_BCH
1217 /**
1218  * omap3_calculate_ecc_bch - Generate bytes of ECC bytes
1219  * @mtd:        MTD device structure
1220  * @dat:        The pointer to data on which ecc is computed
1221  * @ecc_code:   The ecc_code buffer
1222  *
1223  * Support calculating of BCH4/8 ecc vectors for the page
1224  */
1225 static int omap3_calculate_ecc_bch(struct mtd_info *mtd, const u_char *dat,
1226                                     u_char *ecc_code)
1227 {
1228         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1229                                                    mtd);
1230         unsigned long nsectors, bch_val1, bch_val2, bch_val3, bch_val4;
1231         int i, eccbchtsel;
1232
1233         nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1234         /*
1235          * find BCH scheme used
1236          * 0 -> BCH4
1237          * 1 -> BCH8
1238          */
1239         eccbchtsel = ((readl(info->reg.gpmc_ecc_config) >> 12) & 0x3);
1240
1241         for (i = 0; i < nsectors; i++) {
1242
1243                 /* Read hw-computed remainder */
1244                 bch_val1 = readl(info->reg.gpmc_bch_result0[i]);
1245                 bch_val2 = readl(info->reg.gpmc_bch_result1[i]);
1246                 if (eccbchtsel) {
1247                         bch_val3 = readl(info->reg.gpmc_bch_result2[i]);
1248                         bch_val4 = readl(info->reg.gpmc_bch_result3[i]);
1249                 }
1250
1251                 if (eccbchtsel) {
1252                         /* BCH8 ecc scheme */
1253                         *ecc_code++ = (bch_val4 & 0xFF);
1254                         *ecc_code++ = ((bch_val3 >> 24) & 0xFF);
1255                         *ecc_code++ = ((bch_val3 >> 16) & 0xFF);
1256                         *ecc_code++ = ((bch_val3 >> 8) & 0xFF);
1257                         *ecc_code++ = (bch_val3 & 0xFF);
1258                         *ecc_code++ = ((bch_val2 >> 24) & 0xFF);
1259                         *ecc_code++ = ((bch_val2 >> 16) & 0xFF);
1260                         *ecc_code++ = ((bch_val2 >> 8) & 0xFF);
1261                         *ecc_code++ = (bch_val2 & 0xFF);
1262                         *ecc_code++ = ((bch_val1 >> 24) & 0xFF);
1263                         *ecc_code++ = ((bch_val1 >> 16) & 0xFF);
1264                         *ecc_code++ = ((bch_val1 >> 8) & 0xFF);
1265                         *ecc_code++ = (bch_val1 & 0xFF);
1266                         /*
1267                          * Setting 14th byte to zero to handle
1268                          * erased page & maintain compatibility
1269                          * with RBL
1270                          */
1271                         *ecc_code++ = 0x0;
1272                 } else {
1273                         /* BCH4 ecc scheme */
1274                         *ecc_code++ = ((bch_val2 >> 12) & 0xFF);
1275                         *ecc_code++ = ((bch_val2 >> 4) & 0xFF);
1276                         *ecc_code++ = ((bch_val2 & 0xF) << 4) |
1277                                 ((bch_val1 >> 28) & 0xF);
1278                         *ecc_code++ = ((bch_val1 >> 20) & 0xFF);
1279                         *ecc_code++ = ((bch_val1 >> 12) & 0xFF);
1280                         *ecc_code++ = ((bch_val1 >> 4) & 0xFF);
1281                         *ecc_code++ = ((bch_val1 & 0xF) << 4);
1282                         /*
1283                          * Setting 8th byte to zero to handle
1284                          * erased page
1285                          */
1286                         *ecc_code++ = 0x0;
1287                 }
1288         }
1289
1290         return 0;
1291 }
1292
1293 /**
1294  * erased_sector_bitflips - count bit flips
1295  * @data:       data sector buffer
1296  * @oob:        oob buffer
1297  * @info:       omap_nand_info
1298  *
1299  * Check the bit flips in erased page falls below correctable level.
1300  * If falls below, report the page as erased with correctable bit
1301  * flip, else report as uncorrectable page.
1302  */
1303 static int erased_sector_bitflips(u_char *data, u_char *oob,
1304                 struct omap_nand_info *info)
1305 {
1306         int flip_bits = 0, i;
1307
1308         for (i = 0; i < info->nand.ecc.size; i++) {
1309                 flip_bits += hweight8(~data[i]);
1310                 if (flip_bits > info->nand.ecc.strength)
1311                         return 0;
1312         }
1313
1314         for (i = 0; i < info->nand.ecc.bytes - 1; i++) {
1315                 flip_bits += hweight8(~oob[i]);
1316                 if (flip_bits > info->nand.ecc.strength)
1317                         return 0;
1318         }
1319
1320         /*
1321          * Bit flips falls in correctable level.
1322          * Fill data area with 0xFF
1323          */
1324         if (flip_bits) {
1325                 memset(data, 0xFF, info->nand.ecc.size);
1326                 memset(oob, 0xFF, info->nand.ecc.bytes);
1327         }
1328
1329         return flip_bits;
1330 }
1331
1332 /**
1333  * omap_elm_correct_data - corrects page data area in case error reported
1334  * @mtd:        MTD device structure
1335  * @data:       page data
1336  * @read_ecc:   ecc read from nand flash
1337  * @calc_ecc:   ecc read from HW ECC registers
1338  *
1339  * Calculated ecc vector reported as zero in case of non-error pages.
1340  * In case of error/erased pages non-zero error vector is reported.
1341  * In case of non-zero ecc vector, check read_ecc at fixed offset
1342  * (x = 13/7 in case of BCH8/4 == 0) to find page programmed or not.
1343  * To handle bit flips in this data, count the number of 0's in
1344  * read_ecc[x] and check if it greater than 4. If it is less, it is
1345  * programmed page, else erased page.
1346  *
1347  * 1. If page is erased, check with standard ecc vector (ecc vector
1348  * for erased page to find any bit flip). If check fails, bit flip
1349  * is present in erased page. Count the bit flips in erased page and
1350  * if it falls under correctable level, report page with 0xFF and
1351  * update the correctable bit information.
1352  * 2. If error is reported on programmed page, update elm error
1353  * vector and correct the page with ELM error correction routine.
1354  *
1355  */
1356 static int omap_elm_correct_data(struct mtd_info *mtd, u_char *data,
1357                                 u_char *read_ecc, u_char *calc_ecc)
1358 {
1359         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1360                         mtd);
1361         int eccsteps = info->nand.ecc.steps;
1362         int i , j, stat = 0;
1363         int eccsize, eccflag, ecc_vector_size;
1364         struct elm_errorvec err_vec[ERROR_VECTOR_MAX];
1365         u_char *ecc_vec = calc_ecc;
1366         u_char *spare_ecc = read_ecc;
1367         u_char *erased_ecc_vec;
1368         enum bch_ecc type;
1369         bool is_error_reported = false;
1370
1371         /* Initialize elm error vector to zero */
1372         memset(err_vec, 0, sizeof(err_vec));
1373
1374         if (info->nand.ecc.strength == BCH8_MAX_ERROR) {
1375                 type = BCH8_ECC;
1376                 erased_ecc_vec = bch8_vector;
1377         } else {
1378                 type = BCH4_ECC;
1379                 erased_ecc_vec = bch4_vector;
1380         }
1381
1382         ecc_vector_size = info->nand.ecc.bytes;
1383
1384         /*
1385          * Remove extra byte padding for BCH8 RBL
1386          * compatibility and erased page handling
1387          */
1388         eccsize = ecc_vector_size - 1;
1389
1390         for (i = 0; i < eccsteps ; i++) {
1391                 eccflag = 0;    /* initialize eccflag */
1392
1393                 /*
1394                  * Check any error reported,
1395                  * In case of error, non zero ecc reported.
1396                  */
1397
1398                 for (j = 0; (j < eccsize); j++) {
1399                         if (calc_ecc[j] != 0) {
1400                                 eccflag = 1; /* non zero ecc, error present */
1401                                 break;
1402                         }
1403                 }
1404
1405                 if (eccflag == 1) {
1406                         /*
1407                          * Set threshold to minimum of 4, half of ecc.strength/2
1408                          * to allow max bit flip in byte to 4
1409                          */
1410                         unsigned int threshold = min_t(unsigned int, 4,
1411                                         info->nand.ecc.strength / 2);
1412
1413                         /*
1414                          * Check data area is programmed by counting
1415                          * number of 0's at fixed offset in spare area.
1416                          * Checking count of 0's against threshold.
1417                          * In case programmed page expects at least threshold
1418                          * zeros in byte.
1419                          * If zeros are less than threshold for programmed page/
1420                          * zeros are more than threshold erased page, either
1421                          * case page reported as uncorrectable.
1422                          */
1423                         if (hweight8(~read_ecc[eccsize]) >= threshold) {
1424                                 /*
1425                                  * Update elm error vector as
1426                                  * data area is programmed
1427                                  */
1428                                 err_vec[i].error_reported = true;
1429                                 is_error_reported = true;
1430                         } else {
1431                                 /* Error reported in erased page */
1432                                 int bitflip_count;
1433                                 u_char *buf = &data[info->nand.ecc.size * i];
1434
1435                                 if (memcmp(calc_ecc, erased_ecc_vec, eccsize)) {
1436                                         bitflip_count = erased_sector_bitflips(
1437                                                         buf, read_ecc, info);
1438
1439                                         if (bitflip_count)
1440                                                 stat += bitflip_count;
1441                                         else
1442                                                 return -EINVAL;
1443                                 }
1444                         }
1445                 }
1446
1447                 /* Update the ecc vector */
1448                 calc_ecc += ecc_vector_size;
1449                 read_ecc += ecc_vector_size;
1450         }
1451
1452         /* Check if any error reported */
1453         if (!is_error_reported)
1454                 return 0;
1455
1456         /* Decode BCH error using ELM module */
1457         elm_decode_bch_error_page(info->elm_dev, ecc_vec, err_vec);
1458
1459         for (i = 0; i < eccsteps; i++) {
1460                 if (err_vec[i].error_reported) {
1461                         for (j = 0; j < err_vec[i].error_count; j++) {
1462                                 u32 bit_pos, byte_pos, error_max, pos;
1463
1464                                 if (type == BCH8_ECC)
1465                                         error_max = BCH8_ECC_MAX;
1466                                 else
1467                                         error_max = BCH4_ECC_MAX;
1468
1469                                 if (info->nand.ecc.strength == BCH8_MAX_ERROR)
1470                                         pos = err_vec[i].error_loc[j];
1471                                 else
1472                                         /* Add 4 to take care 4 bit padding */
1473                                         pos = err_vec[i].error_loc[j] +
1474                                                 BCH4_BIT_PAD;
1475
1476                                 /* Calculate bit position of error */
1477                                 bit_pos = pos % 8;
1478
1479                                 /* Calculate byte position of error */
1480                                 byte_pos = (error_max - pos - 1) / 8;
1481
1482                                 if (pos < error_max) {
1483                                         if (byte_pos < 512)
1484                                                 data[byte_pos] ^= 1 << bit_pos;
1485                                         else
1486                                                 spare_ecc[byte_pos - 512] ^=
1487                                                         1 << bit_pos;
1488                                 }
1489                                 /* else, not interested to correct ecc */
1490                         }
1491                 }
1492
1493                 /* Update number of correctable errors */
1494                 stat += err_vec[i].error_count;
1495
1496                 /* Update page data with sector size */
1497                 data += info->nand.ecc.size;
1498                 spare_ecc += ecc_vector_size;
1499         }
1500
1501         for (i = 0; i < eccsteps; i++)
1502                 /* Return error if uncorrectable error present */
1503                 if (err_vec[i].error_uncorrectable)
1504                         return -EINVAL;
1505
1506         return stat;
1507 }
1508
1509 /**
1510  * omap_write_page_bch - BCH ecc based write page function for entire page
1511  * @mtd:                mtd info structure
1512  * @chip:               nand chip info structure
1513  * @buf:                data buffer
1514  * @oob_required:       must write chip->oob_poi to OOB
1515  *
1516  * Custom write page method evolved to support multi sector writing in one shot
1517  */
1518 static int omap_write_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
1519                                   const uint8_t *buf, int oob_required)
1520 {
1521         int i;
1522         uint8_t *ecc_calc = chip->buffers->ecccalc;
1523         uint32_t *eccpos = chip->ecc.layout->eccpos;
1524
1525         /* Enable GPMC ecc engine */
1526         chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1527
1528         /* Write data */
1529         chip->write_buf(mtd, buf, mtd->writesize);
1530
1531         /* Update ecc vector from GPMC result registers */
1532         chip->ecc.calculate(mtd, buf, &ecc_calc[0]);
1533
1534         for (i = 0; i < chip->ecc.total; i++)
1535                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1536
1537         /* Write ecc vector to OOB area */
1538         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1539         return 0;
1540 }
1541
1542 /**
1543  * omap_read_page_bch - BCH ecc based page read function for entire page
1544  * @mtd:                mtd info structure
1545  * @chip:               nand chip info structure
1546  * @buf:                buffer to store read data
1547  * @oob_required:       caller requires OOB data read to chip->oob_poi
1548  * @page:               page number to read
1549  *
1550  * For BCH ecc scheme, GPMC used for syndrome calculation and ELM module
1551  * used for error correction.
1552  * Custom method evolved to support ELM error correction & multi sector
1553  * reading. On reading page data area is read along with OOB data with
1554  * ecc engine enabled. ecc vector updated after read of OOB data.
1555  * For non error pages ecc vector reported as zero.
1556  */
1557 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
1558                                 uint8_t *buf, int oob_required, int page)
1559 {
1560         uint8_t *ecc_calc = chip->buffers->ecccalc;
1561         uint8_t *ecc_code = chip->buffers->ecccode;
1562         uint32_t *eccpos = chip->ecc.layout->eccpos;
1563         uint8_t *oob = &chip->oob_poi[eccpos[0]];
1564         uint32_t oob_pos = mtd->writesize + chip->ecc.layout->eccpos[0];
1565         int stat;
1566         unsigned int max_bitflips = 0;
1567
1568         /* Enable GPMC ecc engine */
1569         chip->ecc.hwctl(mtd, NAND_ECC_READ);
1570
1571         /* Read data */
1572         chip->read_buf(mtd, buf, mtd->writesize);
1573
1574         /* Read oob bytes */
1575         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);
1576         chip->read_buf(mtd, oob, chip->ecc.total);
1577
1578         /* Calculate ecc bytes */
1579         chip->ecc.calculate(mtd, buf, ecc_calc);
1580
1581         memcpy(ecc_code, &chip->oob_poi[eccpos[0]], chip->ecc.total);
1582
1583         stat = chip->ecc.correct(mtd, buf, ecc_code, ecc_calc);
1584
1585         if (stat < 0) {
1586                 mtd->ecc_stats.failed++;
1587         } else {
1588                 mtd->ecc_stats.corrected += stat;
1589                 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1590         }
1591
1592         return max_bitflips;
1593 }
1594
1595 /**
1596  * is_elm_present - checks for presence of ELM module by scanning DT nodes
1597  * @omap_nand_info: NAND device structure containing platform data
1598  * @bch_type: 0x0=BCH4, 0x1=BCH8, 0x2=BCH16
1599  */
1600 static int is_elm_present(struct omap_nand_info *info,
1601                         struct device_node *elm_node, enum bch_ecc bch_type)
1602 {
1603         struct platform_device *pdev;
1604         info->is_elm_used = false;
1605         /* check whether elm-id is passed via DT */
1606         if (!elm_node) {
1607                 pr_err("nand: error: ELM DT node not found\n");
1608                 return -ENODEV;
1609         }
1610         pdev = of_find_device_by_node(elm_node);
1611         /* check whether ELM device is registered */
1612         if (!pdev) {
1613                 pr_err("nand: error: ELM device not found\n");
1614                 return -ENODEV;
1615         }
1616         /* ELM module available, now configure it */
1617         info->elm_dev = &pdev->dev;
1618         if (elm_config(info->elm_dev, bch_type))
1619                 return -ENODEV;
1620         info->is_elm_used = true;
1621         return 0;
1622 }
1623 #endif /* CONFIG_MTD_NAND_ECC_BCH */
1624
1625 static int omap_nand_probe(struct platform_device *pdev)
1626 {
1627         struct omap_nand_info           *info;
1628         struct omap_nand_platform_data  *pdata;
1629         struct mtd_info                 *mtd;
1630         struct nand_chip                *nand_chip;
1631         struct nand_ecclayout           *ecclayout;
1632         int                             err;
1633         int                             i;
1634         dma_cap_mask_t                  mask;
1635         unsigned                        sig;
1636         struct resource                 *res;
1637         struct mtd_part_parser_data     ppdata = {};
1638
1639         pdata = dev_get_platdata(&pdev->dev);
1640         if (pdata == NULL) {
1641                 dev_err(&pdev->dev, "platform data missing\n");
1642                 return -ENODEV;
1643         }
1644
1645         info = devm_kzalloc(&pdev->dev, sizeof(struct omap_nand_info),
1646                                 GFP_KERNEL);
1647         if (!info)
1648                 return -ENOMEM;
1649
1650         platform_set_drvdata(pdev, info);
1651
1652         spin_lock_init(&info->controller.lock);
1653         init_waitqueue_head(&info->controller.wq);
1654
1655         info->pdev              = pdev;
1656         info->gpmc_cs           = pdata->cs;
1657         info->reg               = pdata->reg;
1658         info->of_node           = pdata->of_node;
1659         mtd                     = &info->mtd;
1660         mtd->priv               = &info->nand;
1661         mtd->name               = dev_name(&pdev->dev);
1662         mtd->owner              = THIS_MODULE;
1663         nand_chip               = &info->nand;
1664         nand_chip->ecc.priv     = NULL;
1665         nand_chip->options      |= NAND_SKIP_BBTSCAN;
1666
1667         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1668         if (res == NULL) {
1669                 err = -EINVAL;
1670                 dev_err(&pdev->dev, "error getting memory resource\n");
1671                 goto return_error;
1672         }
1673
1674         info->phys_base = res->start;
1675         info->mem_size = resource_size(res);
1676
1677         if (!devm_request_mem_region(&pdev->dev, info->phys_base,
1678                                 info->mem_size, pdev->dev.driver->name)) {
1679                 err = -EBUSY;
1680                 goto return_error;
1681         }
1682
1683         nand_chip->IO_ADDR_R = devm_ioremap(&pdev->dev, info->phys_base,
1684                                                 info->mem_size);
1685         if (!nand_chip->IO_ADDR_R) {
1686                 err = -ENOMEM;
1687                 goto return_error;
1688         }
1689
1690         nand_chip->controller = &info->controller;
1691
1692         nand_chip->IO_ADDR_W = nand_chip->IO_ADDR_R;
1693         nand_chip->cmd_ctrl  = omap_hwcontrol;
1694
1695         /*
1696          * If RDY/BSY line is connected to OMAP then use the omap ready
1697          * function and the generic nand_wait function which reads the status
1698          * register after monitoring the RDY/BSY line. Otherwise use a standard
1699          * chip delay which is slightly more than tR (AC Timing) of the NAND
1700          * device and read status register until you get a failure or success
1701          */
1702         if (pdata->dev_ready) {
1703                 nand_chip->dev_ready = omap_dev_ready;
1704                 nand_chip->chip_delay = 0;
1705         } else {
1706                 nand_chip->waitfunc = omap_wait;
1707                 nand_chip->chip_delay = 50;
1708         }
1709
1710         /* scan NAND device connected to chip controller */
1711         nand_chip->options |= pdata->devsize & NAND_BUSWIDTH_16;
1712         if (nand_scan_ident(mtd, 1, NULL)) {
1713                 pr_err("nand device scan failed, may be bus-width mismatch\n");
1714                 err = -ENXIO;
1715                 goto return_error;
1716         }
1717
1718         /* check for small page devices */
1719         if ((mtd->oobsize < 64) && (pdata->ecc_opt != OMAP_ECC_HAM1_CODE_HW)) {
1720                 pr_err("small page devices are not supported\n");
1721                 err = -EINVAL;
1722                 goto return_error;
1723         }
1724
1725         /* re-populate low-level callbacks based on xfer modes */
1726         switch (pdata->xfer_type) {
1727         case NAND_OMAP_PREFETCH_POLLED:
1728                 nand_chip->read_buf   = omap_read_buf_pref;
1729                 nand_chip->write_buf  = omap_write_buf_pref;
1730                 break;
1731
1732         case NAND_OMAP_POLLED:
1733                 /* Use nand_base defaults for {read,write}_buf */
1734                 break;
1735
1736         case NAND_OMAP_PREFETCH_DMA:
1737                 dma_cap_zero(mask);
1738                 dma_cap_set(DMA_SLAVE, mask);
1739                 sig = OMAP24XX_DMA_GPMC;
1740                 info->dma = dma_request_channel(mask, omap_dma_filter_fn, &sig);
1741                 if (!info->dma) {
1742                         dev_err(&pdev->dev, "DMA engine request failed\n");
1743                         err = -ENXIO;
1744                         goto return_error;
1745                 } else {
1746                         struct dma_slave_config cfg;
1747
1748                         memset(&cfg, 0, sizeof(cfg));
1749                         cfg.src_addr = info->phys_base;
1750                         cfg.dst_addr = info->phys_base;
1751                         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1752                         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1753                         cfg.src_maxburst = 16;
1754                         cfg.dst_maxburst = 16;
1755                         err = dmaengine_slave_config(info->dma, &cfg);
1756                         if (err) {
1757                                 dev_err(&pdev->dev, "DMA engine slave config failed: %d\n",
1758                                         err);
1759                                 goto return_error;
1760                         }
1761                         nand_chip->read_buf   = omap_read_buf_dma_pref;
1762                         nand_chip->write_buf  = omap_write_buf_dma_pref;
1763                 }
1764                 break;
1765
1766         case NAND_OMAP_PREFETCH_IRQ:
1767                 info->gpmc_irq_fifo = platform_get_irq(pdev, 0);
1768                 if (info->gpmc_irq_fifo <= 0) {
1769                         dev_err(&pdev->dev, "error getting fifo irq\n");
1770                         err = -ENODEV;
1771                         goto return_error;
1772                 }
1773                 err = devm_request_irq(&pdev->dev, info->gpmc_irq_fifo,
1774                                         omap_nand_irq, IRQF_SHARED,
1775                                         "gpmc-nand-fifo", info);
1776                 if (err) {
1777                         dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1778                                                 info->gpmc_irq_fifo, err);
1779                         info->gpmc_irq_fifo = 0;
1780                         goto return_error;
1781                 }
1782
1783                 info->gpmc_irq_count = platform_get_irq(pdev, 1);
1784                 if (info->gpmc_irq_count <= 0) {
1785                         dev_err(&pdev->dev, "error getting count irq\n");
1786                         err = -ENODEV;
1787                         goto return_error;
1788                 }
1789                 err = devm_request_irq(&pdev->dev, info->gpmc_irq_count,
1790                                         omap_nand_irq, IRQF_SHARED,
1791                                         "gpmc-nand-count", info);
1792                 if (err) {
1793                         dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1794                                                 info->gpmc_irq_count, err);
1795                         info->gpmc_irq_count = 0;
1796                         goto return_error;
1797                 }
1798
1799                 nand_chip->read_buf  = omap_read_buf_irq_pref;
1800                 nand_chip->write_buf = omap_write_buf_irq_pref;
1801
1802                 break;
1803
1804         default:
1805                 dev_err(&pdev->dev,
1806                         "xfer_type(%d) not supported!\n", pdata->xfer_type);
1807                 err = -EINVAL;
1808                 goto return_error;
1809         }
1810
1811         /* populate MTD interface based on ECC scheme */
1812         nand_chip->ecc.layout   = &omap_oobinfo;
1813         ecclayout               = &omap_oobinfo;
1814         switch (pdata->ecc_opt) {
1815         case OMAP_ECC_HAM1_CODE_HW:
1816                 pr_info("nand: using OMAP_ECC_HAM1_CODE_HW\n");
1817                 nand_chip->ecc.mode             = NAND_ECC_HW;
1818                 nand_chip->ecc.bytes            = 3;
1819                 nand_chip->ecc.size             = 512;
1820                 nand_chip->ecc.strength         = 1;
1821                 nand_chip->ecc.calculate        = omap_calculate_ecc;
1822                 nand_chip->ecc.hwctl            = omap_enable_hwecc;
1823                 nand_chip->ecc.correct          = omap_correct_data;
1824                 /* define ECC layout */
1825                 ecclayout->eccbytes             = nand_chip->ecc.bytes *
1826                                                         (mtd->writesize /
1827                                                         nand_chip->ecc.size);
1828                 if (nand_chip->options & NAND_BUSWIDTH_16)
1829                         ecclayout->eccpos[0]    = BADBLOCK_MARKER_LENGTH;
1830                 else
1831                         ecclayout->eccpos[0]    = 1;
1832                 ecclayout->oobfree->offset      = ecclayout->eccpos[0] +
1833                                                         ecclayout->eccbytes;
1834                 break;
1835
1836         case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1837 #ifdef CONFIG_MTD_NAND_ECC_BCH
1838                 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n");
1839                 nand_chip->ecc.mode             = NAND_ECC_HW;
1840                 nand_chip->ecc.size             = 512;
1841                 nand_chip->ecc.bytes            = 7;
1842                 nand_chip->ecc.strength         = 4;
1843                 nand_chip->ecc.hwctl            = omap3_enable_hwecc_bch;
1844                 nand_chip->ecc.correct          = nand_bch_correct_data;
1845                 nand_chip->ecc.calculate        = omap3_calculate_ecc_bch4;
1846                 /* define ECC layout */
1847                 ecclayout->eccbytes             = nand_chip->ecc.bytes *
1848                                                         (mtd->writesize /
1849                                                         nand_chip->ecc.size);
1850                 ecclayout->eccpos[0]            = BADBLOCK_MARKER_LENGTH;
1851                 ecclayout->oobfree->offset      = ecclayout->eccpos[0] +
1852                                                         ecclayout->eccbytes;
1853                 /* software bch library is used for locating errors */
1854                 nand_chip->ecc.priv             = nand_bch_init(mtd,
1855                                                         nand_chip->ecc.size,
1856                                                         nand_chip->ecc.bytes,
1857                                                         &nand_chip->ecc.layout);
1858                 if (!nand_chip->ecc.priv) {
1859                         pr_err("nand: error: unable to use s/w BCH library\n");
1860                         err = -EINVAL;
1861                 }
1862                 break;
1863 #else
1864                 pr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n");
1865                 err = -EINVAL;
1866                 goto return_error;
1867 #endif
1868
1869         case OMAP_ECC_BCH4_CODE_HW:
1870 #ifdef CONFIG_MTD_NAND_OMAP_BCH
1871                 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n");
1872                 nand_chip->ecc.mode             = NAND_ECC_HW;
1873                 nand_chip->ecc.size             = 512;
1874                 /* 14th bit is kept reserved for ROM-code compatibility */
1875                 nand_chip->ecc.bytes            = 7 + 1;
1876                 nand_chip->ecc.strength         = 4;
1877                 nand_chip->ecc.hwctl            = omap3_enable_hwecc_bch;
1878                 nand_chip->ecc.correct          = omap_elm_correct_data;
1879                 nand_chip->ecc.calculate        = omap3_calculate_ecc_bch;
1880                 nand_chip->ecc.read_page        = omap_read_page_bch;
1881                 nand_chip->ecc.write_page       = omap_write_page_bch;
1882                 /* define ECC layout */
1883                 ecclayout->eccbytes             = nand_chip->ecc.bytes *
1884                                                         (mtd->writesize /
1885                                                         nand_chip->ecc.size);
1886                 ecclayout->eccpos[0]            = BADBLOCK_MARKER_LENGTH;
1887                 ecclayout->oobfree->offset      = ecclayout->eccpos[0] +
1888                                                         ecclayout->eccbytes;
1889                 /* This ECC scheme requires ELM H/W block */
1890                 if (is_elm_present(info, pdata->elm_of_node, BCH4_ECC) < 0) {
1891                         pr_err("nand: error: could not initialize ELM\n");
1892                         err = -ENODEV;
1893                         goto return_error;
1894                 }
1895                 break;
1896 #else
1897                 pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
1898                 err = -EINVAL;
1899                 goto return_error;
1900 #endif
1901
1902         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1903 #ifdef CONFIG_MTD_NAND_ECC_BCH
1904                 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
1905                 nand_chip->ecc.mode             = NAND_ECC_HW;
1906                 nand_chip->ecc.size             = 512;
1907                 nand_chip->ecc.bytes            = 13;
1908                 nand_chip->ecc.strength         = 8;
1909                 nand_chip->ecc.hwctl            = omap3_enable_hwecc_bch;
1910                 nand_chip->ecc.correct          = nand_bch_correct_data;
1911                 nand_chip->ecc.calculate        = omap3_calculate_ecc_bch8;
1912                 /* define ECC layout */
1913                 ecclayout->eccbytes             = nand_chip->ecc.bytes *
1914                                                         (mtd->writesize /
1915                                                         nand_chip->ecc.size);
1916                 ecclayout->eccpos[0]            = BADBLOCK_MARKER_LENGTH;
1917                 ecclayout->oobfree->offset      = ecclayout->eccpos[0] +
1918                                                         ecclayout->eccbytes;
1919                 /* software bch library is used for locating errors */
1920                 nand_chip->ecc.priv             = nand_bch_init(mtd,
1921                                                         nand_chip->ecc.size,
1922                                                         nand_chip->ecc.bytes,
1923                                                         &nand_chip->ecc.layout);
1924                 if (!nand_chip->ecc.priv) {
1925                         pr_err("nand: error: unable to use s/w BCH library\n");
1926                         err = -EINVAL;
1927                         goto return_error;
1928                 }
1929                 break;
1930 #else
1931                 pr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n");
1932                 err = -EINVAL;
1933                 goto return_error;
1934 #endif
1935
1936         case OMAP_ECC_BCH8_CODE_HW:
1937 #ifdef CONFIG_MTD_NAND_OMAP_BCH
1938                 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n");
1939                 nand_chip->ecc.mode             = NAND_ECC_HW;
1940                 nand_chip->ecc.size             = 512;
1941                 /* 14th bit is kept reserved for ROM-code compatibility */
1942                 nand_chip->ecc.bytes            = 13 + 1;
1943                 nand_chip->ecc.strength         = 8;
1944                 nand_chip->ecc.hwctl            = omap3_enable_hwecc_bch;
1945                 nand_chip->ecc.correct          = omap_elm_correct_data;
1946                 nand_chip->ecc.calculate        = omap3_calculate_ecc_bch;
1947                 nand_chip->ecc.read_page        = omap_read_page_bch;
1948                 nand_chip->ecc.write_page       = omap_write_page_bch;
1949                 /* This ECC scheme requires ELM H/W block */
1950                 err = is_elm_present(info, pdata->elm_of_node, BCH8_ECC);
1951                 if (err < 0) {
1952                         pr_err("nand: error: could not initialize ELM\n");
1953                         goto return_error;
1954                 }
1955                 /* define ECC layout */
1956                 ecclayout->eccbytes             = nand_chip->ecc.bytes *
1957                                                         (mtd->writesize /
1958                                                         nand_chip->ecc.size);
1959                 ecclayout->eccpos[0]            = BADBLOCK_MARKER_LENGTH;
1960                 ecclayout->oobfree->offset      = ecclayout->eccpos[0] +
1961                                                         ecclayout->eccbytes;
1962                 break;
1963 #else
1964                 pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
1965                 err = -EINVAL;
1966                 goto return_error;
1967 #endif
1968
1969         default:
1970                 pr_err("nand: error: invalid or unsupported ECC scheme\n");
1971                 err = -EINVAL;
1972                 goto return_error;
1973         }
1974
1975         /* populate remaining ECC layout data */
1976         ecclayout->oobfree->length = mtd->oobsize - (BADBLOCK_MARKER_LENGTH +
1977                                                         ecclayout->eccbytes);
1978         for (i = 1; i < ecclayout->eccbytes; i++)
1979                 ecclayout->eccpos[i] = ecclayout->eccpos[0] + i;
1980         /* check if NAND device's OOB is enough to store ECC signatures */
1981         if (mtd->oobsize < (ecclayout->eccbytes + BADBLOCK_MARKER_LENGTH)) {
1982                 pr_err("not enough OOB bytes required = %d, available=%d\n",
1983                                            ecclayout->eccbytes, mtd->oobsize);
1984                 err = -EINVAL;
1985                 goto return_error;
1986         }
1987
1988         /* second phase scan */
1989         if (nand_scan_tail(mtd)) {
1990                 err = -ENXIO;
1991                 goto return_error;
1992         }
1993
1994         ppdata.of_node = pdata->of_node;
1995         mtd_device_parse_register(mtd, NULL, &ppdata, pdata->parts,
1996                                   pdata->nr_parts);
1997
1998         platform_set_drvdata(pdev, mtd);
1999
2000         return 0;
2001
2002 return_error:
2003         if (info->dma)
2004                 dma_release_channel(info->dma);
2005         if (nand_chip->ecc.priv) {
2006                 nand_bch_free(nand_chip->ecc.priv);
2007                 nand_chip->ecc.priv = NULL;
2008         }
2009         return err;
2010 }
2011
2012 static int omap_nand_remove(struct platform_device *pdev)
2013 {
2014         struct mtd_info *mtd = platform_get_drvdata(pdev);
2015         struct nand_chip *nand_chip = mtd->priv;
2016         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
2017                                                         mtd);
2018         if (nand_chip->ecc.priv) {
2019                 nand_bch_free(nand_chip->ecc.priv);
2020                 nand_chip->ecc.priv = NULL;
2021         }
2022         if (info->dma)
2023                 dma_release_channel(info->dma);
2024         nand_release(mtd);
2025         return 0;
2026 }
2027
2028 static struct platform_driver omap_nand_driver = {
2029         .probe          = omap_nand_probe,
2030         .remove         = omap_nand_remove,
2031         .driver         = {
2032                 .name   = DRIVER_NAME,
2033                 .owner  = THIS_MODULE,
2034         },
2035 };
2036
2037 module_platform_driver(omap_nand_driver);
2038
2039 MODULE_ALIAS("platform:" DRIVER_NAME);
2040 MODULE_LICENSE("GPL");
2041 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");