drivers/mtd/nand/s3c2410.c

   1 /* linux/drivers/mtd/nand/s3c2410.c
   2  *
   3  * Copyright © 2004-2008 Simtec Electronics
   4  *      http://armlinux.simtec.co.uk/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * Samsung S3C2410/S3C2440/S3C2412 NAND driver
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22 */
  23
  24 #define pr_fmt(fmt) "nand-s3c2410: " fmt
  25
  26 #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
  27 #define DEBUG
  28 #endif
  29
  30 #include <linux/module.h>
  31 #include <linux/types.h>
  32 #include <linux/kernel.h>
  33 #include <linux/string.h>
  34 #include <linux/io.h>
  35 #include <linux/ioport.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/delay.h>
  38 #include <linux/err.h>
  39 #include <linux/slab.h>
  40 #include <linux/clk.h>
  41 #include <linux/cpufreq.h>
  42
  43 #include <linux/mtd/mtd.h>
  44 #include <linux/mtd/nand.h>
  45 #include <linux/mtd/nand_ecc.h>
  46 #include <linux/mtd/partitions.h>
  47
  48 #include <linux/platform_data/mtd-nand-s3c2410.h>
  49
  50 #define S3C2410_NFREG(x) (x)
  51
  52 #define S3C2410_NFCONF          S3C2410_NFREG(0x00)
  53 #define S3C2410_NFCMD           S3C2410_NFREG(0x04)
  54 #define S3C2410_NFADDR          S3C2410_NFREG(0x08)
  55 #define S3C2410_NFDATA          S3C2410_NFREG(0x0C)
  56 #define S3C2410_NFSTAT          S3C2410_NFREG(0x10)
  57 #define S3C2410_NFECC           S3C2410_NFREG(0x14)
  58 #define S3C2440_NFCONT          S3C2410_NFREG(0x04)
  59 #define S3C2440_NFCMD           S3C2410_NFREG(0x08)
  60 #define S3C2440_NFADDR          S3C2410_NFREG(0x0C)
  61 #define S3C2440_NFDATA          S3C2410_NFREG(0x10)
  62 #define S3C2440_NFSTAT          S3C2410_NFREG(0x20)
  63 #define S3C2440_NFMECC0         S3C2410_NFREG(0x2C)
  64 #define S3C2412_NFSTAT          S3C2410_NFREG(0x28)
  65 #define S3C2412_NFMECC0         S3C2410_NFREG(0x34)
  66 #define S3C2410_NFCONF_EN               (1<<15)
  67 #define S3C2410_NFCONF_INITECC          (1<<12)
  68 #define S3C2410_NFCONF_nFCE             (1<<11)
  69 #define S3C2410_NFCONF_TACLS(x)         ((x)<<8)
  70 #define S3C2410_NFCONF_TWRPH0(x)        ((x)<<4)
  71 #define S3C2410_NFCONF_TWRPH1(x)        ((x)<<0)
  72 #define S3C2410_NFSTAT_BUSY             (1<<0)
  73 #define S3C2440_NFCONF_TACLS(x)         ((x)<<12)
  74 #define S3C2440_NFCONF_TWRPH0(x)        ((x)<<8)
  75 #define S3C2440_NFCONF_TWRPH1(x)        ((x)<<4)
  76 #define S3C2440_NFCONT_INITECC          (1<<4)
  77 #define S3C2440_NFCONT_nFCE             (1<<1)
  78 #define S3C2440_NFCONT_ENABLE           (1<<0)
  79 #define S3C2440_NFSTAT_READY            (1<<0)
  80 #define S3C2412_NFCONF_NANDBOOT         (1<<31)
  81 #define S3C2412_NFCONT_INIT_MAIN_ECC    (1<<5)
  82 #define S3C2412_NFCONT_nFCE0            (1<<1)
  83 #define S3C2412_NFSTAT_READY            (1<<0)
  84
  85 /* new oob placement block for use with hardware ecc generation
  86  */
  87 static int s3c2410_ooblayout_ecc(struct mtd_info *mtd, int section,
  88                                  struct mtd_oob_region *oobregion)
  89 {
  90         if (section)
  91                 return -ERANGE;
  92
  93         oobregion->offset = 0;
  94         oobregion->length = 3;
  95
  96         return 0;
  97 }
  98
  99 static int s3c2410_ooblayout_free(struct mtd_info *mtd, int section,
 100                                   struct mtd_oob_region *oobregion)
 101 {
 102         if (section)
 103                 return -ERANGE;
 104
 105         oobregion->offset = 8;
 106         oobregion->length = 8;
 107
 108         return 0;
 109 }
 110
 111 static const struct mtd_ooblayout_ops s3c2410_ooblayout_ops = {
 112         .ecc = s3c2410_ooblayout_ecc,
 113         .free = s3c2410_ooblayout_free,
 114 };
 115
 116 /* controller and mtd information */
 117
 118 struct s3c2410_nand_info;
 119
 120 /**
 121  * struct s3c2410_nand_mtd - driver MTD structure
 122  * @mtd: The MTD instance to pass to the MTD layer.
 123  * @chip: The NAND chip information.
 124  * @set: The platform information supplied for this set of NAND chips.
 125  * @info: Link back to the hardware information.
 126  * @scan_res: The result from calling nand_scan_ident().
 127 */
 128 struct s3c2410_nand_mtd {
 129         struct nand_chip                chip;
 130         struct s3c2410_nand_set         *set;
 131         struct s3c2410_nand_info        *info;
 132         int                             scan_res;
 133 };
 134
 135 enum s3c_cpu_type {
 136         TYPE_S3C2410,
 137         TYPE_S3C2412,
 138         TYPE_S3C2440,
 139 };
 140
 141 enum s3c_nand_clk_state {
 142         CLOCK_DISABLE   = 0,
 143         CLOCK_ENABLE,
 144         CLOCK_SUSPEND,
 145 };
 146
 147 /* overview of the s3c2410 nand state */
 148
 149 /**
 150  * struct s3c2410_nand_info - NAND controller state.
 151  * @mtds: An array of MTD instances on this controoler.
 152  * @platform: The platform data for this board.
 153  * @device: The platform device we bound to.
 154  * @clk: The clock resource for this controller.
 155  * @regs: The area mapped for the hardware registers.
 156  * @sel_reg: Pointer to the register controlling the NAND selection.
 157  * @sel_bit: The bit in @sel_reg to select the NAND chip.
 158  * @mtd_count: The number of MTDs created from this controller.
 159  * @save_sel: The contents of @sel_reg to be saved over suspend.
 160  * @clk_rate: The clock rate from @clk.
 161  * @clk_state: The current clock state.
 162  * @cpu_type: The exact type of this controller.
 163  */
 164 struct s3c2410_nand_info {
 165         /* mtd info */
 166         struct nand_hw_control          controller;
 167         struct s3c2410_nand_mtd         *mtds;
 168         struct s3c2410_platform_nand    *platform;
 169
 170         /* device info */
 171         struct device                   *device;
 172         struct clk                      *clk;
 173         void __iomem                    *regs;
 174         void __iomem                    *sel_reg;
 175         int                             sel_bit;
 176         int                             mtd_count;
 177         unsigned long                   save_sel;
 178         unsigned long                   clk_rate;
 179         enum s3c_nand_clk_state         clk_state;
 180
 181         enum s3c_cpu_type               cpu_type;
 182
 183 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
 184         struct notifier_block   freq_transition;
 185 #endif
 186 };
 187
 188 /* conversion functions */
 189
 190 static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
 191 {
 192         return container_of(mtd_to_nand(mtd), struct s3c2410_nand_mtd,
 193                             chip);
 194 }
 195
 196 static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd)
 197 {
 198         return s3c2410_nand_mtd_toours(mtd)->info;
 199 }
 200
 201 static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev)
 202 {
 203         return platform_get_drvdata(dev);
 204 }
 205
 206 static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev)
 207 {
 208         return dev_get_platdata(&dev->dev);
 209 }
 210
 211 static inline int allow_clk_suspend(struct s3c2410_nand_info *info)
 212 {
 213 #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP
 214         return 1;
 215 #else
 216         return 0;
 217 #endif
 218 }
 219
 220 /**
 221  * s3c2410_nand_clk_set_state - Enable, disable or suspend NAND clock.
 222  * @info: The controller instance.
 223  * @new_state: State to which clock should be set.
 224  */
 225 static void s3c2410_nand_clk_set_state(struct s3c2410_nand_info *info,
 226                 enum s3c_nand_clk_state new_state)
 227 {
 228         if (!allow_clk_suspend(info) && new_state == CLOCK_SUSPEND)
 229                 return;
 230
 231         if (info->clk_state == CLOCK_ENABLE) {
 232                 if (new_state != CLOCK_ENABLE)
 233                         clk_disable_unprepare(info->clk);
 234         } else {
 235                 if (new_state == CLOCK_ENABLE)
 236                         clk_prepare_enable(info->clk);
 237         }
 238
 239         info->clk_state = new_state;
 240 }
 241
 242 /* timing calculations */
 243
 244 #define NS_IN_KHZ 1000000
 245
 246 /**
 247  * s3c_nand_calc_rate - calculate timing data.
 248  * @wanted: The cycle time in nanoseconds.
 249  * @clk: The clock rate in kHz.
 250  * @max: The maximum divider value.
 251  *
 252  * Calculate the timing value from the given parameters.
 253  */
 254 static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max)
 255 {
 256         int result;
 257
 258         result = DIV_ROUND_UP((wanted * clk), NS_IN_KHZ);
 259
 260         pr_debug("result %d from %ld, %d\n", result, clk, wanted);
 261
 262         if (result > max) {
 263                 pr_err("%d ns is too big for current clock rate %ld\n",
 264                         wanted, clk);
 265                 return -1;
 266         }
 267
 268         if (result < 1)
 269                 result = 1;
 270
 271         return result;
 272 }
 273
 274 #define to_ns(ticks, clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk))
 275
 276 /* controller setup */
 277
 278 /**
 279  * s3c2410_nand_setrate - setup controller timing information.
 280  * @info: The controller instance.
 281  *
 282  * Given the information supplied by the platform, calculate and set
 283  * the necessary timing registers in the hardware to generate the
 284  * necessary timing cycles to the hardware.
 285  */
 286 static int s3c2410_nand_setrate(struct s3c2410_nand_info *info)
 287 {
 288         struct s3c2410_platform_nand *plat = info->platform;
 289         int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4;
 290         int tacls, twrph0, twrph1;
 291         unsigned long clkrate = clk_get_rate(info->clk);
 292         unsigned long uninitialized_var(set), cfg, uninitialized_var(mask);
 293         unsigned long flags;
 294
 295         /* calculate the timing information for the controller */
 296
 297         info->clk_rate = clkrate;
 298         clkrate /= 1000;        /* turn clock into kHz for ease of use */
 299
 300         if (plat != NULL) {
 301                 tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max);
 302                 twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8);
 303                 twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8);
 304         } else {
 305                 /* default timings */
 306                 tacls = tacls_max;
 307                 twrph0 = 8;
 308                 twrph1 = 8;
 309         }
 310
 311         if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
 312                 dev_err(info->device, "cannot get suitable timings\n");
 313                 return -EINVAL;
 314         }
 315
 316         dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
 317                 tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate),
 318                                                 twrph1, to_ns(twrph1, clkrate));
 319
 320         switch (info->cpu_type) {
 321         case TYPE_S3C2410:
 322                 mask = (S3C2410_NFCONF_TACLS(3) |
 323                         S3C2410_NFCONF_TWRPH0(7) |
 324                         S3C2410_NFCONF_TWRPH1(7));
 325                 set = S3C2410_NFCONF_EN;
 326                 set |= S3C2410_NFCONF_TACLS(tacls - 1);
 327                 set |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
 328                 set |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
 329                 break;
 330
 331         case TYPE_S3C2440:
 332         case TYPE_S3C2412:
 333                 mask = (S3C2440_NFCONF_TACLS(tacls_max - 1) |
 334                         S3C2440_NFCONF_TWRPH0(7) |
 335                         S3C2440_NFCONF_TWRPH1(7));
 336
 337                 set = S3C2440_NFCONF_TACLS(tacls - 1);
 338                 set |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
 339                 set |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
 340                 break;
 341
 342         default:
 343                 BUG();
 344         }
 345
 346         local_irq_save(flags);
 347
 348         cfg = readl(info->regs + S3C2410_NFCONF);
 349         cfg &= ~mask;
 350         cfg |= set;
 351         writel(cfg, info->regs + S3C2410_NFCONF);
 352
 353         local_irq_restore(flags);
 354
 355         dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
 356
 357         return 0;
 358 }
 359
 360 /**
 361  * s3c2410_nand_inithw - basic hardware initialisation
 362  * @info: The hardware state.
 363  *
 364  * Do the basic initialisation of the hardware, using s3c2410_nand_setrate()
 365  * to setup the hardware access speeds and set the controller to be enabled.
 366 */
 367 static int s3c2410_nand_inithw(struct s3c2410_nand_info *info)
 368 {
 369         int ret;
 370
 371         ret = s3c2410_nand_setrate(info);
 372         if (ret < 0)
 373                 return ret;
 374
 375         switch (info->cpu_type) {
 376         case TYPE_S3C2410:
 377         default:
 378                 break;
 379
 380         case TYPE_S3C2440:
 381         case TYPE_S3C2412:
 382                 /* enable the controller and de-assert nFCE */
 383
 384                 writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT);
 385         }
 386
 387         return 0;
 388 }
 389
 390 /**
 391  * s3c2410_nand_select_chip - select the given nand chip
 392  * @mtd: The MTD instance for this chip.
 393  * @chip: The chip number.
 394  *
 395  * This is called by the MTD layer to either select a given chip for the
 396  * @mtd instance, or to indicate that the access has finished and the
 397  * chip can be de-selected.
 398  *
 399  * The routine ensures that the nFCE line is correctly setup, and any
 400  * platform specific selection code is called to route nFCE to the specific
 401  * chip.
 402  */
 403 static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip)
 404 {
 405         struct s3c2410_nand_info *info;
 406         struct s3c2410_nand_mtd *nmtd;
 407         struct nand_chip *this = mtd_to_nand(mtd);
 408         unsigned long cur;
 409
 410         nmtd = nand_get_controller_data(this);
 411         info = nmtd->info;
 412
 413         if (chip != -1)
 414                 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
 415
 416         cur = readl(info->sel_reg);
 417
 418         if (chip == -1) {
 419                 cur |= info->sel_bit;
 420         } else {
 421                 if (nmtd->set != NULL && chip > nmtd->set->nr_chips) {
 422                         dev_err(info->device, "invalid chip %d\n", chip);
 423                         return;
 424                 }
 425
 426                 if (info->platform != NULL) {
 427                         if (info->platform->select_chip != NULL)
 428                                 (info->platform->select_chip) (nmtd->set, chip);
 429                 }
 430
 431                 cur &= ~info->sel_bit;
 432         }
 433
 434         writel(cur, info->sel_reg);
 435
 436         if (chip == -1)
 437                 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
 438 }
 439
 440 /* s3c2410_nand_hwcontrol
 441  *
 442  * Issue command and address cycles to the chip
 443 */
 444
 445 static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd,
 446                                    unsigned int ctrl)
 447 {
 448         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 449
 450         if (cmd == NAND_CMD_NONE)
 451                 return;
 452
 453         if (ctrl & NAND_CLE)
 454                 writeb(cmd, info->regs + S3C2410_NFCMD);
 455         else
 456                 writeb(cmd, info->regs + S3C2410_NFADDR);
 457 }
 458
 459 /* command and control functions */
 460
 461 static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd,
 462                                    unsigned int ctrl)
 463 {
 464         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 465
 466         if (cmd == NAND_CMD_NONE)
 467                 return;
 468
 469         if (ctrl & NAND_CLE)
 470                 writeb(cmd, info->regs + S3C2440_NFCMD);
 471         else
 472                 writeb(cmd, info->regs + S3C2440_NFADDR);
 473 }
 474
 475 /* s3c2410_nand_devready()
 476  *
 477  * returns 0 if the nand is busy, 1 if it is ready
 478 */
 479
 480 static int s3c2410_nand_devready(struct mtd_info *mtd)
 481 {
 482         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 483         return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
 484 }
 485
 486 static int s3c2440_nand_devready(struct mtd_info *mtd)
 487 {
 488         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 489         return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY;
 490 }
 491
 492 static int s3c2412_nand_devready(struct mtd_info *mtd)
 493 {
 494         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 495         return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY;
 496 }
 497
 498 /* ECC handling functions */
 499
 500 #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
 501 static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 502                                      u_char *read_ecc, u_char *calc_ecc)
 503 {
 504         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 505         unsigned int diff0, diff1, diff2;
 506         unsigned int bit, byte;
 507
 508         pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc);
 509
 510         diff0 = read_ecc[0] ^ calc_ecc[0];
 511         diff1 = read_ecc[1] ^ calc_ecc[1];
 512         diff2 = read_ecc[2] ^ calc_ecc[2];
 513
 514         pr_debug("%s: rd %*phN calc %*phN diff %02x%02x%02x\n",
 515                  __func__, 3, read_ecc, 3, calc_ecc,
 516                  diff0, diff1, diff2);
 517
 518         if (diff0 == 0 && diff1 == 0 && diff2 == 0)
 519                 return 0;               /* ECC is ok */
 520
 521         /* sometimes people do not think about using the ECC, so check
 522          * to see if we have an 0xff,0xff,0xff read ECC and then ignore
 523          * the error, on the assumption that this is an un-eccd page.
 524          */
 525         if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && read_ecc[2] == 0xff
 526             && info->platform->ignore_unset_ecc)
 527                 return 0;
 528
 529         /* Can we correct this ECC (ie, one row and column change).
 530          * Note, this is similar to the 256 error code on smartmedia */
 531
 532         if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 &&
 533             ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 &&
 534             ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) {
 535                 /* calculate the bit position of the error */
 536
 537                 bit  = ((diff2 >> 3) & 1) |
 538                        ((diff2 >> 4) & 2) |
 539                        ((diff2 >> 5) & 4);
 540
 541                 /* calculate the byte position of the error */
 542
 543                 byte = ((diff2 << 7) & 0x100) |
 544                        ((diff1 << 0) & 0x80)  |
 545                        ((diff1 << 1) & 0x40)  |
 546                        ((diff1 << 2) & 0x20)  |
 547                        ((diff1 << 3) & 0x10)  |
 548                        ((diff0 >> 4) & 0x08)  |
 549                        ((diff0 >> 3) & 0x04)  |
 550                        ((diff0 >> 2) & 0x02)  |
 551                        ((diff0 >> 1) & 0x01);
 552
 553                 dev_dbg(info->device, "correcting error bit %d, byte %d\n",
 554                         bit, byte);
 555
 556                 dat[byte] ^= (1 << bit);
 557                 return 1;
 558         }
 559
 560         /* if there is only one bit difference in the ECC, then
 561          * one of only a row or column parity has changed, which
 562          * means the error is most probably in the ECC itself */
 563
 564         diff0 |= (diff1 << 8);
 565         diff0 |= (diff2 << 16);
 566
 567         /* equal to "(diff0 & ~(1 << __ffs(diff0)))" */
 568         if ((diff0 & (diff0 - 1)) == 0)
 569                 return 1;
 570
 571         return -1;
 572 }
 573
 574 /* ECC functions
 575  *
 576  * These allow the s3c2410 and s3c2440 to use the controller's ECC
 577  * generator block to ECC the data as it passes through]
 578 */
 579
 580 static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 581 {
 582         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 583         unsigned long ctrl;
 584
 585         ctrl = readl(info->regs + S3C2410_NFCONF);
 586         ctrl |= S3C2410_NFCONF_INITECC;
 587         writel(ctrl, info->regs + S3C2410_NFCONF);
 588 }
 589
 590 static void s3c2412_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 591 {
 592         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 593         unsigned long ctrl;
 594
 595         ctrl = readl(info->regs + S3C2440_NFCONT);
 596         writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC,
 597                info->regs + S3C2440_NFCONT);
 598 }
 599
 600 static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 601 {
 602         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 603         unsigned long ctrl;
 604
 605         ctrl = readl(info->regs + S3C2440_NFCONT);
 606         writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT);
 607 }
 608
 609 static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 610                                       u_char *ecc_code)
 611 {
 612         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 613
 614         ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
 615         ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
 616         ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
 617
 618         pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code);
 619
 620         return 0;
 621 }
 622
 623 static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 624                                       u_char *ecc_code)
 625 {
 626         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 627         unsigned long ecc = readl(info->regs + S3C2412_NFMECC0);
 628
 629         ecc_code[0] = ecc;
 630         ecc_code[1] = ecc >> 8;
 631         ecc_code[2] = ecc >> 16;
 632
 633         pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code);
 634
 635         return 0;
 636 }
 637
 638 static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 639                                       u_char *ecc_code)
 640 {
 641         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 642         unsigned long ecc = readl(info->regs + S3C2440_NFMECC0);
 643
 644         ecc_code[0] = ecc;
 645         ecc_code[1] = ecc >> 8;
 646         ecc_code[2] = ecc >> 16;
 647
 648         pr_debug("%s: returning ecc %06lx\n", __func__, ecc & 0xffffff);
 649
 650         return 0;
 651 }
 652 #endif
 653
 654 /* over-ride the standard functions for a little more speed. We can
 655  * use read/write block to move the data buffers to/from the controller
 656 */
 657
 658 static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 659 {
 660         struct nand_chip *this = mtd_to_nand(mtd);
 661         readsb(this->IO_ADDR_R, buf, len);
 662 }
 663
 664 static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 665 {
 666         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 667
 668         readsl(info->regs + S3C2440_NFDATA, buf, len >> 2);
 669
 670         /* cleanup if we've got less than a word to do */
 671         if (len & 3) {
 672                 buf += len & ~3;
 673
 674                 for (; len & 3; len--)
 675                         *buf++ = readb(info->regs + S3C2440_NFDATA);
 676         }
 677 }
 678
 679 static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
 680                                    int len)
 681 {
 682         struct nand_chip *this = mtd_to_nand(mtd);
 683         writesb(this->IO_ADDR_W, buf, len);
 684 }
 685
 686 static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
 687                                    int len)
 688 {
 689         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 690
 691         writesl(info->regs + S3C2440_NFDATA, buf, len >> 2);
 692
 693         /* cleanup any fractional write */
 694         if (len & 3) {
 695                 buf += len & ~3;
 696
 697                 for (; len & 3; len--, buf++)
 698                         writeb(*buf, info->regs + S3C2440_NFDATA);
 699         }
 700 }
 701
 702 /* cpufreq driver support */
 703
 704 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
 705
 706 static int s3c2410_nand_cpufreq_transition(struct notifier_block *nb,
 707                                           unsigned long val, void *data)
 708 {
 709         struct s3c2410_nand_info *info;
 710         unsigned long newclk;
 711
 712         info = container_of(nb, struct s3c2410_nand_info, freq_transition);
 713         newclk = clk_get_rate(info->clk);
 714
 715         if ((val == CPUFREQ_POSTCHANGE && newclk < info->clk_rate) ||
 716             (val == CPUFREQ_PRECHANGE && newclk > info->clk_rate)) {
 717                 s3c2410_nand_setrate(info);
 718         }
 719
 720         return 0;
 721 }
 722
 723 static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)
 724 {
 725         info->freq_transition.notifier_call = s3c2410_nand_cpufreq_transition;
 726
 727         return cpufreq_register_notifier(&info->freq_transition,
 728                                          CPUFREQ_TRANSITION_NOTIFIER);
 729 }
 730
 731 static inline void
 732 s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)
 733 {
 734         cpufreq_unregister_notifier(&info->freq_transition,
 735                                     CPUFREQ_TRANSITION_NOTIFIER);
 736 }
 737
 738 #else
 739 static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)
 740 {
 741         return 0;
 742 }
 743
 744 static inline void
 745 s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)
 746 {
 747 }
 748 #endif
 749
 750 /* device management functions */
 751
 752 static int s3c24xx_nand_remove(struct platform_device *pdev)
 753 {
 754         struct s3c2410_nand_info *info = to_nand_info(pdev);
 755
 756         if (info == NULL)
 757                 return 0;
 758
 759         s3c2410_nand_cpufreq_deregister(info);
 760
 761         /* Release all our mtds  and their partitions, then go through
 762          * freeing the resources used
 763          */
 764
 765         if (info->mtds != NULL) {
 766                 struct s3c2410_nand_mtd *ptr = info->mtds;
 767                 int mtdno;
 768
 769                 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
 770                         pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
 771                         nand_release(nand_to_mtd(&ptr->chip));
 772                 }
 773         }
 774
 775         /* free the common resources */
 776
 777         if (!IS_ERR(info->clk))
 778                 s3c2410_nand_clk_set_state(info, CLOCK_DISABLE);
 779
 780         return 0;
 781 }
 782
 783 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
 784                                       struct s3c2410_nand_mtd *mtd,
 785                                       struct s3c2410_nand_set *set)
 786 {
 787         if (set) {
 788                 struct mtd_info *mtdinfo = nand_to_mtd(&mtd->chip);
 789
 790                 mtdinfo->name = set->name;
 791
 792                 return mtd_device_parse_register(mtdinfo, NULL, NULL,
 793                                          set->partitions, set->nr_partitions);
 794         }
 795
 796         return -ENODEV;
 797 }
 798
 799 /**
 800  * s3c2410_nand_init_chip - initialise a single instance of an chip
 801  * @info: The base NAND controller the chip is on.
 802  * @nmtd: The new controller MTD instance to fill in.
 803  * @set: The information passed from the board specific platform data.
 804  *
 805  * Initialise the given @nmtd from the information in @info and @set. This
 806  * readies the structure for use with the MTD layer functions by ensuring
 807  * all pointers are setup and the necessary control routines selected.
 808  */
 809 static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
 810                                    struct s3c2410_nand_mtd *nmtd,
 811                                    struct s3c2410_nand_set *set)
 812 {
 813         struct nand_chip *chip = &nmtd->chip;
 814         void __iomem *regs = info->regs;
 815
 816         chip->write_buf    = s3c2410_nand_write_buf;
 817         chip->read_buf     = s3c2410_nand_read_buf;
 818         chip->select_chip  = s3c2410_nand_select_chip;
 819         chip->chip_delay   = 50;
 820         nand_set_controller_data(chip, nmtd);
 821         chip->options      = set->options;
 822         chip->controller   = &info->controller;
 823
 824         switch (info->cpu_type) {
 825         case TYPE_S3C2410:
 826                 chip->IO_ADDR_W = regs + S3C2410_NFDATA;
 827                 info->sel_reg   = regs + S3C2410_NFCONF;
 828                 info->sel_bit   = S3C2410_NFCONF_nFCE;
 829                 chip->cmd_ctrl  = s3c2410_nand_hwcontrol;
 830                 chip->dev_ready = s3c2410_nand_devready;
 831                 break;
 832
 833         case TYPE_S3C2440:
 834                 chip->IO_ADDR_W = regs + S3C2440_NFDATA;
 835                 info->sel_reg   = regs + S3C2440_NFCONT;
 836                 info->sel_bit   = S3C2440_NFCONT_nFCE;
 837                 chip->cmd_ctrl  = s3c2440_nand_hwcontrol;
 838                 chip->dev_ready = s3c2440_nand_devready;
 839                 chip->read_buf  = s3c2440_nand_read_buf;
 840                 chip->write_buf = s3c2440_nand_write_buf;
 841                 break;
 842
 843         case TYPE_S3C2412:
 844                 chip->IO_ADDR_W = regs + S3C2440_NFDATA;
 845                 info->sel_reg   = regs + S3C2440_NFCONT;
 846                 info->sel_bit   = S3C2412_NFCONT_nFCE0;
 847                 chip->cmd_ctrl  = s3c2440_nand_hwcontrol;
 848                 chip->dev_ready = s3c2412_nand_devready;
 849
 850                 if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT)
 851                         dev_info(info->device, "System booted from NAND\n");
 852
 853                 break;
 854         }
 855
 856         chip->IO_ADDR_R = chip->IO_ADDR_W;
 857
 858         nmtd->info         = info;
 859         nmtd->set          = set;
 860
 861 #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
 862         chip->ecc.calculate = s3c2410_nand_calculate_ecc;
 863         chip->ecc.correct   = s3c2410_nand_correct_data;
 864         chip->ecc.mode      = NAND_ECC_HW;
 865         chip->ecc.strength  = 1;
 866
 867         switch (info->cpu_type) {
 868         case TYPE_S3C2410:
 869                 chip->ecc.hwctl     = s3c2410_nand_enable_hwecc;
 870                 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
 871                 break;
 872
 873         case TYPE_S3C2412:
 874                 chip->ecc.hwctl     = s3c2412_nand_enable_hwecc;
 875                 chip->ecc.calculate = s3c2412_nand_calculate_ecc;
 876                 break;
 877
 878         case TYPE_S3C2440:
 879                 chip->ecc.hwctl     = s3c2440_nand_enable_hwecc;
 880                 chip->ecc.calculate = s3c2440_nand_calculate_ecc;
 881                 break;
 882         }
 883 #else
 884         chip->ecc.mode      = NAND_ECC_SOFT;
 885         chip->ecc.algo  = NAND_ECC_HAMMING;
 886 #endif
 887
 888         if (set->disable_ecc)
 889                 chip->ecc.mode  = NAND_ECC_NONE;
 890
 891         switch (chip->ecc.mode) {
 892         case NAND_ECC_NONE:
 893                 dev_info(info->device, "NAND ECC disabled\n");
 894                 break;
 895         case NAND_ECC_SOFT:
 896                 dev_info(info->device, "NAND soft ECC\n");
 897                 break;
 898         case NAND_ECC_HW:
 899                 dev_info(info->device, "NAND hardware ECC\n");
 900                 break;
 901         default:
 902                 dev_info(info->device, "NAND ECC UNKNOWN\n");
 903                 break;
 904         }
 905
 906         /* If you use u-boot BBT creation code, specifying this flag will
 907          * let the kernel fish out the BBT from the NAND, and also skip the
 908          * full NAND scan that can take 1/2s or so. Little things... */
 909         if (set->flash_bbt) {
 910                 chip->bbt_options |= NAND_BBT_USE_FLASH;
 911                 chip->options |= NAND_SKIP_BBTSCAN;
 912         }
 913 }
 914
 915 /**
 916  * s3c2410_nand_update_chip - post probe update
 917  * @info: The controller instance.
 918  * @nmtd: The driver version of the MTD instance.
 919  *
 920  * This routine is called after the chip probe has successfully completed
 921  * and the relevant per-chip information updated. This call ensure that
 922  * we update the internal state accordingly.
 923  *
 924  * The internal state is currently limited to the ECC state information.
 925 */
 926 static void s3c2410_nand_update_chip(struct s3c2410_nand_info *info,
 927                                      struct s3c2410_nand_mtd *nmtd)
 928 {
 929         struct nand_chip *chip = &nmtd->chip;
 930
 931         dev_dbg(info->device, "chip %p => page shift %d\n",
 932                 chip, chip->page_shift);
 933
 934         if (chip->ecc.mode != NAND_ECC_HW)
 935                 return;
 936
 937                 /* change the behaviour depending on whether we are using
 938                  * the large or small page nand device */
 939
 940         if (chip->page_shift > 10) {
 941                 chip->ecc.size      = 256;
 942                 chip->ecc.bytes     = 3;
 943         } else {
 944                 chip->ecc.size      = 512;
 945                 chip->ecc.bytes     = 3;
 946                 mtd_set_ooblayout(nand_to_mtd(chip), &s3c2410_ooblayout_ops);
 947         }
 948 }
 949
 950 /* s3c24xx_nand_probe
 951  *
 952  * called by device layer when it finds a device matching
 953  * one our driver can handled. This code checks to see if
 954  * it can allocate all necessary resources then calls the
 955  * nand layer to look for devices
 956 */
 957 static int s3c24xx_nand_probe(struct platform_device *pdev)
 958 {
 959         struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
 960         enum s3c_cpu_type cpu_type;
 961         struct s3c2410_nand_info *info;
 962         struct s3c2410_nand_mtd *nmtd;
 963         struct s3c2410_nand_set *sets;
 964         struct resource *res;
 965         int err = 0;
 966         int size;
 967         int nr_sets;
 968         int setno;
 969
 970         cpu_type = platform_get_device_id(pdev)->driver_data;
 971
 972         info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
 973         if (info == NULL) {
 974                 err = -ENOMEM;
 975                 goto exit_error;
 976         }
 977
 978         platform_set_drvdata(pdev, info);
 979
 980         nand_hw_control_init(&info->controller);
 981
 982         /* get the clock source and enable it */
 983
 984         info->clk = devm_clk_get(&pdev->dev, "nand");
 985         if (IS_ERR(info->clk)) {
 986                 dev_err(&pdev->dev, "failed to get clock\n");
 987                 err = -ENOENT;
 988                 goto exit_error;
 989         }
 990
 991         s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
 992
 993         /* allocate and map the resource */
 994
 995         /* currently we assume we have the one resource */
 996         res = pdev->resource;
 997         size = resource_size(res);
 998
 999         info->device    = &pdev->dev;
1000         info->platform  = plat;
1001         info->cpu_type  = cpu_type;
1002
1003         info->regs = devm_ioremap_resource(&pdev->dev, res);
1004         if (IS_ERR(info->regs)) {
1005                 err = PTR_ERR(info->regs);
1006                 goto exit_error;
1007         }
1008
1009         dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs);
1010
1011         /* initialise the hardware */
1012
1013         err = s3c2410_nand_inithw(info);
1014         if (err != 0)
1015                 goto exit_error;
1016
1017         sets = (plat != NULL) ? plat->sets : NULL;
1018         nr_sets = (plat != NULL) ? plat->nr_sets : 1;
1019
1020         info->mtd_count = nr_sets;
1021
1022         /* allocate our information */
1023
1024         size = nr_sets * sizeof(*info->mtds);
1025         info->mtds = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
1026         if (info->mtds == NULL) {
1027                 err = -ENOMEM;
1028                 goto exit_error;
1029         }
1030
1031         /* initialise all possible chips */
1032
1033         nmtd = info->mtds;
1034
1035         for (setno = 0; setno < nr_sets; setno++, nmtd++) {
1036                 struct mtd_info *mtd = nand_to_mtd(&nmtd->chip);
1037
1038                 pr_debug("initialising set %d (%p, info %p)\n",
1039                          setno, nmtd, info);
1040
1041                 mtd->dev.parent = &pdev->dev;
1042                 s3c2410_nand_init_chip(info, nmtd, sets);
1043
1044                 nmtd->scan_res = nand_scan_ident(mtd,
1045                                                  (sets) ? sets->nr_chips : 1,
1046                                                  NULL);
1047
1048                 if (nmtd->scan_res == 0) {
1049                         s3c2410_nand_update_chip(info, nmtd);
1050                         nand_scan_tail(mtd);
1051                         s3c2410_nand_add_partition(info, nmtd, sets);
1052                 }
1053
1054                 if (sets != NULL)
1055                         sets++;
1056         }
1057
1058         err = s3c2410_nand_cpufreq_register(info);
1059         if (err < 0) {
1060                 dev_err(&pdev->dev, "failed to init cpufreq support\n");
1061                 goto exit_error;
1062         }
1063
1064         if (allow_clk_suspend(info)) {
1065                 dev_info(&pdev->dev, "clock idle support enabled\n");
1066                 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
1067         }
1068
1069         return 0;
1070
1071  exit_error:
1072         s3c24xx_nand_remove(pdev);
1073
1074         if (err == 0)
1075                 err = -EINVAL;
1076         return err;
1077 }
1078
1079 /* PM Support */
1080 #ifdef CONFIG_PM
1081
1082 static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
1083 {
1084         struct s3c2410_nand_info *info = platform_get_drvdata(dev);
1085
1086         if (info) {
1087                 info->save_sel = readl(info->sel_reg);
1088
1089                 /* For the moment, we must ensure nFCE is high during
1090                  * the time we are suspended. This really should be
1091                  * handled by suspending the MTDs we are using, but
1092                  * that is currently not the case. */
1093
1094                 writel(info->save_sel | info->sel_bit, info->sel_reg);
1095
1096                 s3c2410_nand_clk_set_state(info, CLOCK_DISABLE);
1097         }
1098
1099         return 0;
1100 }
1101
1102 static int s3c24xx_nand_resume(struct platform_device *dev)
1103 {
1104         struct s3c2410_nand_info *info = platform_get_drvdata(dev);
1105         unsigned long sel;
1106
1107         if (info) {
1108                 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
1109                 s3c2410_nand_inithw(info);
1110
1111                 /* Restore the state of the nFCE line. */
1112
1113                 sel = readl(info->sel_reg);
1114                 sel &= ~info->sel_bit;
1115                 sel |= info->save_sel & info->sel_bit;
1116                 writel(sel, info->sel_reg);
1117
1118                 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
1119         }
1120
1121         return 0;
1122 }
1123
1124 #else
1125 #define s3c24xx_nand_suspend NULL
1126 #define s3c24xx_nand_resume NULL
1127 #endif
1128
1129 /* driver device registration */
1130
1131 static const struct platform_device_id s3c24xx_driver_ids[] = {
1132         {
1133                 .name           = "s3c2410-nand",
1134                 .driver_data    = TYPE_S3C2410,
1135         }, {
1136                 .name           = "s3c2440-nand",
1137                 .driver_data    = TYPE_S3C2440,
1138         }, {
1139                 .name           = "s3c2412-nand",
1140                 .driver_data    = TYPE_S3C2412,
1141         }, {
1142                 .name           = "s3c6400-nand",
1143                 .driver_data    = TYPE_S3C2412, /* compatible with 2412 */
1144         },
1145         { }
1146 };
1147
1148 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
1149
1150 static struct platform_driver s3c24xx_nand_driver = {
1151         .probe          = s3c24xx_nand_probe,
1152         .remove         = s3c24xx_nand_remove,
1153         .suspend        = s3c24xx_nand_suspend,
1154         .resume         = s3c24xx_nand_resume,
1155         .id_table       = s3c24xx_driver_ids,
1156         .driver         = {
1157                 .name   = "s3c24xx-nand",
1158         },
1159 };
1160
1161 module_platform_driver(s3c24xx_nand_driver);
1162
1163 MODULE_LICENSE("GPL");
1164 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1165 MODULE_DESCRIPTION("S3C24XX MTD NAND driver");