drivers/mtd/nand/sunxi_nand.c

   1 /*
   2  * Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev@gmail.com>
   3  *
   4  * Derived from:
   5  *      https://github.com/yuq/sunxi-nfc-mtd
   6  *      Copyright (C) 2013 Qiang Yu <yuq825@gmail.com>
   7  *
   8  *      https://github.com/hno/Allwinner-Info
   9  *      Copyright (C) 2013 Henrik Nordström <Henrik Nordström>
  10  *
  11  *      Copyright (C) 2013 Dmitriy B. <rzk333@gmail.com>
  12  *      Copyright (C) 2013 Sergey Lapin <slapin@ossfans.org>
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  */
  24
  25 #include <linux/dma-mapping.h>
  26 #include <linux/slab.h>
  27 #include <linux/module.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/of.h>
  31 #include <linux/of_device.h>
  32 #include <linux/of_gpio.h>
  33 #include <linux/mtd/mtd.h>
  34 #include <linux/mtd/nand.h>
  35 #include <linux/mtd/partitions.h>
  36 #include <linux/clk.h>
  37 #include <linux/delay.h>
  38 #include <linux/dmaengine.h>
  39 #include <linux/gpio.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/iopoll.h>
  42
  43 #define NFC_REG_CTL             0x0000
  44 #define NFC_REG_ST              0x0004
  45 #define NFC_REG_INT             0x0008
  46 #define NFC_REG_TIMING_CTL      0x000C
  47 #define NFC_REG_TIMING_CFG      0x0010
  48 #define NFC_REG_ADDR_LOW        0x0014
  49 #define NFC_REG_ADDR_HIGH       0x0018
  50 #define NFC_REG_SECTOR_NUM      0x001C
  51 #define NFC_REG_CNT             0x0020
  52 #define NFC_REG_CMD             0x0024
  53 #define NFC_REG_RCMD_SET        0x0028
  54 #define NFC_REG_WCMD_SET        0x002C
  55 #define NFC_REG_IO_DATA         0x0030
  56 #define NFC_REG_ECC_CTL         0x0034
  57 #define NFC_REG_ECC_ST          0x0038
  58 #define NFC_REG_DEBUG           0x003C
  59 #define NFC_REG_ECC_ERR_CNT(x)  ((0x0040 + (x)) & ~0x3)
  60 #define NFC_REG_USER_DATA(x)    (0x0050 + ((x) * 4))
  61 #define NFC_REG_SPARE_AREA      0x00A0
  62 #define NFC_REG_PAT_ID          0x00A4
  63 #define NFC_RAM0_BASE           0x0400
  64 #define NFC_RAM1_BASE           0x0800
  65
  66 /* define bit use in NFC_CTL */
  67 #define NFC_EN                  BIT(0)
  68 #define NFC_RESET               BIT(1)
  69 #define NFC_BUS_WIDTH_MSK       BIT(2)
  70 #define NFC_BUS_WIDTH_8         (0 << 2)
  71 #define NFC_BUS_WIDTH_16        (1 << 2)
  72 #define NFC_RB_SEL_MSK          BIT(3)
  73 #define NFC_RB_SEL(x)           ((x) << 3)
  74 #define NFC_CE_SEL_MSK          GENMASK(26, 24)
  75 #define NFC_CE_SEL(x)           ((x) << 24)
  76 #define NFC_CE_CTL              BIT(6)
  77 #define NFC_PAGE_SHIFT_MSK      GENMASK(11, 8)
  78 #define NFC_PAGE_SHIFT(x)       (((x) < 10 ? 0 : (x) - 10) << 8)
  79 #define NFC_SAM                 BIT(12)
  80 #define NFC_RAM_METHOD          BIT(14)
  81 #define NFC_DEBUG_CTL           BIT(31)
  82
  83 /* define bit use in NFC_ST */
  84 #define NFC_RB_B2R              BIT(0)
  85 #define NFC_CMD_INT_FLAG        BIT(1)
  86 #define NFC_DMA_INT_FLAG        BIT(2)
  87 #define NFC_CMD_FIFO_STATUS     BIT(3)
  88 #define NFC_STA                 BIT(4)
  89 #define NFC_NATCH_INT_FLAG      BIT(5)
  90 #define NFC_RB_STATE(x)         BIT(x + 8)
  91
  92 /* define bit use in NFC_INT */
  93 #define NFC_B2R_INT_ENABLE      BIT(0)
  94 #define NFC_CMD_INT_ENABLE      BIT(1)
  95 #define NFC_DMA_INT_ENABLE      BIT(2)
  96 #define NFC_INT_MASK            (NFC_B2R_INT_ENABLE | \
  97                                  NFC_CMD_INT_ENABLE | \
  98                                  NFC_DMA_INT_ENABLE)
  99
 100 /* define bit use in NFC_TIMING_CTL */
 101 #define NFC_TIMING_CTL_EDO      BIT(8)
 102
 103 /* define NFC_TIMING_CFG register layout */
 104 #define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD)             \
 105         (((tWB) & 0x3) | (((tADL) & 0x3) << 2) |                \
 106         (((tWHR) & 0x3) << 4) | (((tRHW) & 0x3) << 6) |         \
 107         (((tCAD) & 0x7) << 8))
 108
 109 /* define bit use in NFC_CMD */
 110 #define NFC_CMD_LOW_BYTE_MSK    GENMASK(7, 0)
 111 #define NFC_CMD_HIGH_BYTE_MSK   GENMASK(15, 8)
 112 #define NFC_CMD(x)              (x)
 113 #define NFC_ADR_NUM_MSK         GENMASK(18, 16)
 114 #define NFC_ADR_NUM(x)          (((x) - 1) << 16)
 115 #define NFC_SEND_ADR            BIT(19)
 116 #define NFC_ACCESS_DIR          BIT(20)
 117 #define NFC_DATA_TRANS          BIT(21)
 118 #define NFC_SEND_CMD1           BIT(22)
 119 #define NFC_WAIT_FLAG           BIT(23)
 120 #define NFC_SEND_CMD2           BIT(24)
 121 #define NFC_SEQ                 BIT(25)
 122 #define NFC_DATA_SWAP_METHOD    BIT(26)
 123 #define NFC_ROW_AUTO_INC        BIT(27)
 124 #define NFC_SEND_CMD3           BIT(28)
 125 #define NFC_SEND_CMD4           BIT(29)
 126 #define NFC_CMD_TYPE_MSK        GENMASK(31, 30)
 127 #define NFC_NORMAL_OP           (0 << 30)
 128 #define NFC_ECC_OP              (1 << 30)
 129 #define NFC_PAGE_OP             (2 << 30)
 130
 131 /* define bit use in NFC_RCMD_SET */
 132 #define NFC_READ_CMD_MSK        GENMASK(7, 0)
 133 #define NFC_RND_READ_CMD0_MSK   GENMASK(15, 8)
 134 #define NFC_RND_READ_CMD1_MSK   GENMASK(23, 16)
 135
 136 /* define bit use in NFC_WCMD_SET */
 137 #define NFC_PROGRAM_CMD_MSK     GENMASK(7, 0)
 138 #define NFC_RND_WRITE_CMD_MSK   GENMASK(15, 8)
 139 #define NFC_READ_CMD0_MSK       GENMASK(23, 16)
 140 #define NFC_READ_CMD1_MSK       GENMASK(31, 24)
 141
 142 /* define bit use in NFC_ECC_CTL */
 143 #define NFC_ECC_EN              BIT(0)
 144 #define NFC_ECC_PIPELINE        BIT(3)
 145 #define NFC_ECC_EXCEPTION       BIT(4)
 146 #define NFC_ECC_BLOCK_SIZE_MSK  BIT(5)
 147 #define NFC_RANDOM_EN           BIT(9)
 148 #define NFC_RANDOM_DIRECTION    BIT(10)
 149 #define NFC_ECC_MODE_MSK        GENMASK(15, 12)
 150 #define NFC_ECC_MODE(x)         ((x) << 12)
 151 #define NFC_RANDOM_SEED_MSK     GENMASK(30, 16)
 152 #define NFC_RANDOM_SEED(x)      ((x) << 16)
 153
 154 /* define bit use in NFC_ECC_ST */
 155 #define NFC_ECC_ERR(x)          BIT(x)
 156 #define NFC_ECC_PAT_FOUND(x)    BIT(x + 16)
 157 #define NFC_ECC_ERR_CNT(b, x)   (((x) >> (((b) % 4) * 8)) & 0xff)
 158
 159 #define NFC_DEFAULT_TIMEOUT_MS  1000
 160
 161 #define NFC_SRAM_SIZE           1024
 162
 163 #define NFC_MAX_CS              7
 164
 165 /*
 166  * Ready/Busy detection type: describes the Ready/Busy detection modes
 167  *
 168  * @RB_NONE:    no external detection available, rely on STATUS command
 169  *              and software timeouts
 170  * @RB_NATIVE:  use sunxi NAND controller Ready/Busy support. The Ready/Busy
 171  *              pin of the NAND flash chip must be connected to one of the
 172  *              native NAND R/B pins (those which can be muxed to the NAND
 173  *              Controller)
 174  * @RB_GPIO:    use a simple GPIO to handle Ready/Busy status. The Ready/Busy
 175  *              pin of the NAND flash chip must be connected to a GPIO capable
 176  *              pin.
 177  */
 178 enum sunxi_nand_rb_type {
 179         RB_NONE,
 180         RB_NATIVE,
 181         RB_GPIO,
 182 };
 183
 184 /*
 185  * Ready/Busy structure: stores information related to Ready/Busy detection
 186  *
 187  * @type:       the Ready/Busy detection mode
 188  * @info:       information related to the R/B detection mode. Either a gpio
 189  *              id or a native R/B id (those supported by the NAND controller).
 190  */
 191 struct sunxi_nand_rb {
 192         enum sunxi_nand_rb_type type;
 193         union {
 194                 int gpio;
 195                 int nativeid;
 196         } info;
 197 };
 198
 199 /*
 200  * Chip Select structure: stores information related to NAND Chip Select
 201  *
 202  * @cs:         the NAND CS id used to communicate with a NAND Chip
 203  * @rb:         the Ready/Busy description
 204  */
 205 struct sunxi_nand_chip_sel {
 206         u8 cs;
 207         struct sunxi_nand_rb rb;
 208 };
 209
 210 /*
 211  * sunxi HW ECC infos: stores information related to HW ECC support
 212  *
 213  * @mode:       the sunxi ECC mode field deduced from ECC requirements
 214  */
 215 struct sunxi_nand_hw_ecc {
 216         int mode;
 217 };
 218
 219 /*
 220  * NAND chip structure: stores NAND chip device related information
 221  *
 222  * @node:               used to store NAND chips into a list
 223  * @nand:               base NAND chip structure
 224  * @mtd:                base MTD structure
 225  * @clk_rate:           clk_rate required for this NAND chip
 226  * @timing_cfg          TIMING_CFG register value for this NAND chip
 227  * @selected:           current active CS
 228  * @nsels:              number of CS lines required by the NAND chip
 229  * @sels:               array of CS lines descriptions
 230  */
 231 struct sunxi_nand_chip {
 232         struct list_head node;
 233         struct nand_chip nand;
 234         unsigned long clk_rate;
 235         u32 timing_cfg;
 236         u32 timing_ctl;
 237         int selected;
 238         int addr_cycles;
 239         u32 addr[2];
 240         int cmd_cycles;
 241         u8 cmd[2];
 242         int nsels;
 243         struct sunxi_nand_chip_sel sels[0];
 244 };
 245
 246 static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
 247 {
 248         return container_of(nand, struct sunxi_nand_chip, nand);
 249 }
 250
 251 /*
 252  * NAND Controller structure: stores sunxi NAND controller information
 253  *
 254  * @controller:         base controller structure
 255  * @dev:                parent device (used to print error messages)
 256  * @regs:               NAND controller registers
 257  * @ahb_clk:            NAND Controller AHB clock
 258  * @mod_clk:            NAND Controller mod clock
 259  * @assigned_cs:        bitmask describing already assigned CS lines
 260  * @clk_rate:           NAND controller current clock rate
 261  * @chips:              a list containing all the NAND chips attached to
 262  *                      this NAND controller
 263  * @complete:           a completion object used to wait for NAND
 264  *                      controller events
 265  */
 266 struct sunxi_nfc {
 267         struct nand_hw_control controller;
 268         struct device *dev;
 269         void __iomem *regs;
 270         struct clk *ahb_clk;
 271         struct clk *mod_clk;
 272         unsigned long assigned_cs;
 273         unsigned long clk_rate;
 274         struct list_head chips;
 275         struct completion complete;
 276 };
 277
 278 static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_hw_control *ctrl)
 279 {
 280         return container_of(ctrl, struct sunxi_nfc, controller);
 281 }
 282
 283 static irqreturn_t sunxi_nfc_interrupt(int irq, void *dev_id)
 284 {
 285         struct sunxi_nfc *nfc = dev_id;
 286         u32 st = readl(nfc->regs + NFC_REG_ST);
 287         u32 ien = readl(nfc->regs + NFC_REG_INT);
 288
 289         if (!(ien & st))
 290                 return IRQ_NONE;
 291
 292         if ((ien & st) == ien)
 293                 complete(&nfc->complete);
 294
 295         writel(st & NFC_INT_MASK, nfc->regs + NFC_REG_ST);
 296         writel(~st & ien & NFC_INT_MASK, nfc->regs + NFC_REG_INT);
 297
 298         return IRQ_HANDLED;
 299 }
 300
 301 static int sunxi_nfc_wait_events(struct sunxi_nfc *nfc, u32 events,
 302                                  bool use_polling, unsigned int timeout_ms)
 303 {
 304         int ret;
 305
 306         if (events & ~NFC_INT_MASK)
 307                 return -EINVAL;
 308
 309         if (!timeout_ms)
 310                 timeout_ms = NFC_DEFAULT_TIMEOUT_MS;
 311
 312         if (!use_polling) {
 313                 init_completion(&nfc->complete);
 314
 315                 writel(events, nfc->regs + NFC_REG_INT);
 316
 317                 ret = wait_for_completion_timeout(&nfc->complete,
 318                                                 msecs_to_jiffies(timeout_ms));
 319
 320                 writel(0, nfc->regs + NFC_REG_INT);
 321         } else {
 322                 u32 status;
 323
 324                 ret = readl_poll_timeout(nfc->regs + NFC_REG_ST, status,
 325                                          (status & events) == events, 1,
 326                                          timeout_ms * 1000);
 327         }
 328
 329         writel(events & NFC_INT_MASK, nfc->regs + NFC_REG_ST);
 330
 331         if (ret)
 332                 dev_err(nfc->dev, "wait interrupt timedout\n");
 333
 334         return ret;
 335 }
 336
 337 static int sunxi_nfc_wait_cmd_fifo_empty(struct sunxi_nfc *nfc)
 338 {
 339         u32 status;
 340         int ret;
 341
 342         ret = readl_poll_timeout(nfc->regs + NFC_REG_ST, status,
 343                                  !(status & NFC_CMD_FIFO_STATUS), 1,
 344                                  NFC_DEFAULT_TIMEOUT_MS * 1000);
 345         if (ret)
 346                 dev_err(nfc->dev, "wait for empty cmd FIFO timedout\n");
 347
 348         return ret;
 349 }
 350
 351 static int sunxi_nfc_rst(struct sunxi_nfc *nfc)
 352 {
 353         u32 ctl;
 354         int ret;
 355
 356         writel(0, nfc->regs + NFC_REG_ECC_CTL);
 357         writel(NFC_RESET, nfc->regs + NFC_REG_CTL);
 358
 359         ret = readl_poll_timeout(nfc->regs + NFC_REG_CTL, ctl,
 360                                  !(ctl & NFC_RESET), 1,
 361                                  NFC_DEFAULT_TIMEOUT_MS * 1000);
 362         if (ret)
 363                 dev_err(nfc->dev, "wait for NAND controller reset timedout\n");
 364
 365         return ret;
 366 }
 367
 368 static int sunxi_nfc_dev_ready(struct mtd_info *mtd)
 369 {
 370         struct nand_chip *nand = mtd_to_nand(mtd);
 371         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
 372         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
 373         struct sunxi_nand_rb *rb;
 374         int ret;
 375
 376         if (sunxi_nand->selected < 0)
 377                 return 0;
 378
 379         rb = &sunxi_nand->sels[sunxi_nand->selected].rb;
 380
 381         switch (rb->type) {
 382         case RB_NATIVE:
 383                 ret = !!(readl(nfc->regs + NFC_REG_ST) &
 384                          NFC_RB_STATE(rb->info.nativeid));
 385                 break;
 386         case RB_GPIO:
 387                 ret = gpio_get_value(rb->info.gpio);
 388                 break;
 389         case RB_NONE:
 390         default:
 391                 ret = 0;
 392                 dev_err(nfc->dev, "cannot check R/B NAND status!\n");
 393                 break;
 394         }
 395
 396         return ret;
 397 }
 398
 399 static void sunxi_nfc_select_chip(struct mtd_info *mtd, int chip)
 400 {
 401         struct nand_chip *nand = mtd_to_nand(mtd);
 402         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
 403         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
 404         struct sunxi_nand_chip_sel *sel;
 405         u32 ctl;
 406
 407         if (chip > 0 && chip >= sunxi_nand->nsels)
 408                 return;
 409
 410         if (chip == sunxi_nand->selected)
 411                 return;
 412
 413         ctl = readl(nfc->regs + NFC_REG_CTL) &
 414               ~(NFC_PAGE_SHIFT_MSK | NFC_CE_SEL_MSK | NFC_RB_SEL_MSK | NFC_EN);
 415
 416         if (chip >= 0) {
 417                 sel = &sunxi_nand->sels[chip];
 418
 419                 ctl |= NFC_CE_SEL(sel->cs) | NFC_EN |
 420                        NFC_PAGE_SHIFT(nand->page_shift);
 421                 if (sel->rb.type == RB_NONE) {
 422                         nand->dev_ready = NULL;
 423                 } else {
 424                         nand->dev_ready = sunxi_nfc_dev_ready;
 425                         if (sel->rb.type == RB_NATIVE)
 426                                 ctl |= NFC_RB_SEL(sel->rb.info.nativeid);
 427                 }
 428
 429                 writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA);
 430
 431                 if (nfc->clk_rate != sunxi_nand->clk_rate) {
 432                         clk_set_rate(nfc->mod_clk, sunxi_nand->clk_rate);
 433                         nfc->clk_rate = sunxi_nand->clk_rate;
 434                 }
 435         }
 436
 437         writel(sunxi_nand->timing_ctl, nfc->regs + NFC_REG_TIMING_CTL);
 438         writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG);
 439         writel(ctl, nfc->regs + NFC_REG_CTL);
 440
 441         sunxi_nand->selected = chip;
 442 }
 443
 444 static void sunxi_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 445 {
 446         struct nand_chip *nand = mtd_to_nand(mtd);
 447         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
 448         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
 449         int ret;
 450         int cnt;
 451         int offs = 0;
 452         u32 tmp;
 453
 454         while (len > offs) {
 455                 cnt = min(len - offs, NFC_SRAM_SIZE);
 456
 457                 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 458                 if (ret)
 459                         break;
 460
 461                 writel(cnt, nfc->regs + NFC_REG_CNT);
 462                 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD;
 463                 writel(tmp, nfc->regs + NFC_REG_CMD);
 464
 465                 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, true, 0);
 466                 if (ret)
 467                         break;
 468
 469                 if (buf)
 470                         memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE,
 471                                       cnt);
 472                 offs += cnt;
 473         }
 474 }
 475
 476 static void sunxi_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
 477                                 int len)
 478 {
 479         struct nand_chip *nand = mtd_to_nand(mtd);
 480         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
 481         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
 482         int ret;
 483         int cnt;
 484         int offs = 0;
 485         u32 tmp;
 486
 487         while (len > offs) {
 488                 cnt = min(len - offs, NFC_SRAM_SIZE);
 489
 490                 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 491                 if (ret)
 492                         break;
 493
 494                 writel(cnt, nfc->regs + NFC_REG_CNT);
 495                 memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt);
 496                 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
 497                       NFC_ACCESS_DIR;
 498                 writel(tmp, nfc->regs + NFC_REG_CMD);
 499
 500                 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, true, 0);
 501                 if (ret)
 502                         break;
 503
 504                 offs += cnt;
 505         }
 506 }
 507
 508 static uint8_t sunxi_nfc_read_byte(struct mtd_info *mtd)
 509 {
 510         uint8_t ret;
 511
 512         sunxi_nfc_read_buf(mtd, &ret, 1);
 513
 514         return ret;
 515 }
 516
 517 static void sunxi_nfc_cmd_ctrl(struct mtd_info *mtd, int dat,
 518                                unsigned int ctrl)
 519 {
 520         struct nand_chip *nand = mtd_to_nand(mtd);
 521         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
 522         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
 523         int ret;
 524
 525         ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 526         if (ret)
 527                 return;
 528
 529         if (dat == NAND_CMD_NONE && (ctrl & NAND_NCE) &&
 530             !(ctrl & (NAND_CLE | NAND_ALE))) {
 531                 u32 cmd = 0;
 532
 533                 if (!sunxi_nand->addr_cycles && !sunxi_nand->cmd_cycles)
 534                         return;
 535
 536                 if (sunxi_nand->cmd_cycles--)
 537                         cmd |= NFC_SEND_CMD1 | sunxi_nand->cmd[0];
 538
 539                 if (sunxi_nand->cmd_cycles--) {
 540                         cmd |= NFC_SEND_CMD2;
 541                         writel(sunxi_nand->cmd[1],
 542                                nfc->regs + NFC_REG_RCMD_SET);
 543                 }
 544
 545                 sunxi_nand->cmd_cycles = 0;
 546
 547                 if (sunxi_nand->addr_cycles) {
 548                         cmd |= NFC_SEND_ADR |
 549                                NFC_ADR_NUM(sunxi_nand->addr_cycles);
 550                         writel(sunxi_nand->addr[0],
 551                                nfc->regs + NFC_REG_ADDR_LOW);
 552                 }
 553
 554                 if (sunxi_nand->addr_cycles > 4)
 555                         writel(sunxi_nand->addr[1],
 556                                nfc->regs + NFC_REG_ADDR_HIGH);
 557
 558                 writel(cmd, nfc->regs + NFC_REG_CMD);
 559                 sunxi_nand->addr[0] = 0;
 560                 sunxi_nand->addr[1] = 0;
 561                 sunxi_nand->addr_cycles = 0;
 562                 sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, true, 0);
 563         }
 564
 565         if (ctrl & NAND_CLE) {
 566                 sunxi_nand->cmd[sunxi_nand->cmd_cycles++] = dat;
 567         } else if (ctrl & NAND_ALE) {
 568                 sunxi_nand->addr[sunxi_nand->addr_cycles / 4] |=
 569                                 dat << ((sunxi_nand->addr_cycles % 4) * 8);
 570                 sunxi_nand->addr_cycles++;
 571         }
 572 }
 573
 574 /* These seed values have been extracted from Allwinner's BSP */
 575 static const u16 sunxi_nfc_randomizer_page_seeds[] = {
 576         0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
 577         0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
 578         0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
 579         0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
 580         0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
 581         0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
 582         0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
 583         0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
 584         0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
 585         0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
 586         0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
 587         0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
 588         0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
 589         0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
 590         0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
 591         0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
 592 };
 593
 594 /*
 595  * sunxi_nfc_randomizer_ecc512_seeds and sunxi_nfc_randomizer_ecc1024_seeds
 596  * have been generated using
 597  * sunxi_nfc_randomizer_step(seed, (step_size * 8) + 15), which is what
 598  * the randomizer engine does internally before de/scrambling OOB data.
 599  *
 600  * Those tables are statically defined to avoid calculating randomizer state
 601  * at runtime.
 602  */
 603 static const u16 sunxi_nfc_randomizer_ecc512_seeds[] = {
 604         0x3346, 0x367f, 0x1f18, 0x769a, 0x4f64, 0x068c, 0x2ef1, 0x6b64,
 605         0x28a9, 0x15d7, 0x30f8, 0x3659, 0x53db, 0x7c5f, 0x71d4, 0x4409,
 606         0x26eb, 0x03cc, 0x655d, 0x47d4, 0x4daa, 0x0877, 0x712d, 0x3617,
 607         0x3264, 0x49aa, 0x7f9e, 0x588e, 0x4fbc, 0x7176, 0x7f91, 0x6c6d,
 608         0x4b95, 0x5fb7, 0x3844, 0x4037, 0x0184, 0x081b, 0x0ee8, 0x5b91,
 609         0x293d, 0x1f71, 0x0e6f, 0x402b, 0x5122, 0x1e52, 0x22be, 0x3d2d,
 610         0x75bc, 0x7c60, 0x6291, 0x1a2f, 0x61d4, 0x74aa, 0x4140, 0x29ab,
 611         0x472d, 0x2852, 0x017e, 0x15e8, 0x5ec2, 0x17cf, 0x7d0f, 0x06b8,
 612         0x117a, 0x6b94, 0x789b, 0x3126, 0x6ac5, 0x5be7, 0x150f, 0x51f8,
 613         0x7889, 0x0aa5, 0x663d, 0x77e8, 0x0b87, 0x3dcb, 0x360d, 0x218b,
 614         0x512f, 0x7dc9, 0x6a4d, 0x630a, 0x3547, 0x1dd2, 0x5aea, 0x69a5,
 615         0x7bfa, 0x5e4f, 0x1519, 0x6430, 0x3a0e, 0x5eb3, 0x5425, 0x0c7a,
 616         0x5540, 0x3670, 0x63c1, 0x31e9, 0x5a39, 0x2de7, 0x5979, 0x2891,
 617         0x1562, 0x014b, 0x5b05, 0x2756, 0x5a34, 0x13aa, 0x6cb5, 0x2c36,
 618         0x5e72, 0x1306, 0x0861, 0x15ef, 0x1ee8, 0x5a37, 0x7ac4, 0x45dd,
 619         0x44c4, 0x7266, 0x2f41, 0x3ccc, 0x045e, 0x7d40, 0x7c66, 0x0fa0,
 620 };
 621
 622 static const u16 sunxi_nfc_randomizer_ecc1024_seeds[] = {
 623         0x2cf5, 0x35f1, 0x63a4, 0x5274, 0x2bd2, 0x778b, 0x7285, 0x32b6,
 624         0x6a5c, 0x70d6, 0x757d, 0x6769, 0x5375, 0x1e81, 0x0cf3, 0x3982,
 625         0x6787, 0x042a, 0x6c49, 0x1925, 0x56a8, 0x40a9, 0x063e, 0x7bd9,
 626         0x4dbf, 0x55ec, 0x672e, 0x7334, 0x5185, 0x4d00, 0x232a, 0x7e07,
 627         0x445d, 0x6b92, 0x528f, 0x4255, 0x53ba, 0x7d82, 0x2a2e, 0x3a4e,
 628         0x75eb, 0x450c, 0x6844, 0x1b5d, 0x581a, 0x4cc6, 0x0379, 0x37b2,
 629         0x419f, 0x0e92, 0x6b27, 0x5624, 0x01e3, 0x07c1, 0x44a5, 0x130c,
 630         0x13e8, 0x5910, 0x0876, 0x60c5, 0x54e3, 0x5b7f, 0x2269, 0x509f,
 631         0x7665, 0x36fd, 0x3e9a, 0x0579, 0x6295, 0x14ef, 0x0a81, 0x1bcc,
 632         0x4b16, 0x64db, 0x0514, 0x4f07, 0x0591, 0x3576, 0x6853, 0x0d9e,
 633         0x259f, 0x38b7, 0x64fb, 0x3094, 0x4693, 0x6ddd, 0x29bb, 0x0bc8,
 634         0x3f47, 0x490e, 0x0c0e, 0x7933, 0x3c9e, 0x5840, 0x398d, 0x3e68,
 635         0x4af1, 0x71f5, 0x57cf, 0x1121, 0x64eb, 0x3579, 0x15ac, 0x584d,
 636         0x5f2a, 0x47e2, 0x6528, 0x6eac, 0x196e, 0x6b96, 0x0450, 0x0179,
 637         0x609c, 0x06e1, 0x4626, 0x42c7, 0x273e, 0x486f, 0x0705, 0x1601,
 638         0x145b, 0x407e, 0x062b, 0x57a5, 0x53f9, 0x5659, 0x4410, 0x3ccd,
 639 };
 640
 641 static u16 sunxi_nfc_randomizer_step(u16 state, int count)
 642 {
 643         state &= 0x7fff;
 644
 645         /*
 646          * This loop is just a simple implementation of a Fibonacci LFSR using
 647          * the x16 + x15 + 1 polynomial.
 648          */
 649         while (count--)
 650                 state = ((state >> 1) |
 651                          (((state ^ (state >> 1)) & 1) << 14)) & 0x7fff;
 652
 653         return state;
 654 }
 655
 656 static u16 sunxi_nfc_randomizer_state(struct mtd_info *mtd, int page, bool ecc)
 657 {
 658         const u16 *seeds = sunxi_nfc_randomizer_page_seeds;
 659         int mod = mtd_div_by_ws(mtd->erasesize, mtd);
 660
 661         if (mod > ARRAY_SIZE(sunxi_nfc_randomizer_page_seeds))
 662                 mod = ARRAY_SIZE(sunxi_nfc_randomizer_page_seeds);
 663
 664         if (ecc) {
 665                 if (mtd->ecc_step_size == 512)
 666                         seeds = sunxi_nfc_randomizer_ecc512_seeds;
 667                 else
 668                         seeds = sunxi_nfc_randomizer_ecc1024_seeds;
 669         }
 670
 671         return seeds[page % mod];
 672 }
 673
 674 static void sunxi_nfc_randomizer_config(struct mtd_info *mtd,
 675                                         int page, bool ecc)
 676 {
 677         struct nand_chip *nand = mtd_to_nand(mtd);
 678         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 679         u32 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
 680         u16 state;
 681
 682         if (!(nand->options & NAND_NEED_SCRAMBLING))
 683                 return;
 684
 685         ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
 686         state = sunxi_nfc_randomizer_state(mtd, page, ecc);
 687         ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_SEED_MSK;
 688         writel(ecc_ctl | NFC_RANDOM_SEED(state), nfc->regs + NFC_REG_ECC_CTL);
 689 }
 690
 691 static void sunxi_nfc_randomizer_enable(struct mtd_info *mtd)
 692 {
 693         struct nand_chip *nand = mtd_to_nand(mtd);
 694         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 695
 696         if (!(nand->options & NAND_NEED_SCRAMBLING))
 697                 return;
 698
 699         writel(readl(nfc->regs + NFC_REG_ECC_CTL) | NFC_RANDOM_EN,
 700                nfc->regs + NFC_REG_ECC_CTL);
 701 }
 702
 703 static void sunxi_nfc_randomizer_disable(struct mtd_info *mtd)
 704 {
 705         struct nand_chip *nand = mtd_to_nand(mtd);
 706         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 707
 708         if (!(nand->options & NAND_NEED_SCRAMBLING))
 709                 return;
 710
 711         writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_EN,
 712                nfc->regs + NFC_REG_ECC_CTL);
 713 }
 714
 715 static void sunxi_nfc_randomize_bbm(struct mtd_info *mtd, int page, u8 *bbm)
 716 {
 717         u16 state = sunxi_nfc_randomizer_state(mtd, page, true);
 718
 719         bbm[0] ^= state;
 720         bbm[1] ^= sunxi_nfc_randomizer_step(state, 8);
 721 }
 722
 723 static void sunxi_nfc_randomizer_write_buf(struct mtd_info *mtd,
 724                                            const uint8_t *buf, int len,
 725                                            bool ecc, int page)
 726 {
 727         sunxi_nfc_randomizer_config(mtd, page, ecc);
 728         sunxi_nfc_randomizer_enable(mtd);
 729         sunxi_nfc_write_buf(mtd, buf, len);
 730         sunxi_nfc_randomizer_disable(mtd);
 731 }
 732
 733 static void sunxi_nfc_randomizer_read_buf(struct mtd_info *mtd, uint8_t *buf,
 734                                           int len, bool ecc, int page)
 735 {
 736         sunxi_nfc_randomizer_config(mtd, page, ecc);
 737         sunxi_nfc_randomizer_enable(mtd);
 738         sunxi_nfc_read_buf(mtd, buf, len);
 739         sunxi_nfc_randomizer_disable(mtd);
 740 }
 741
 742 static void sunxi_nfc_hw_ecc_enable(struct mtd_info *mtd)
 743 {
 744         struct nand_chip *nand = mtd_to_nand(mtd);
 745         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 746         struct sunxi_nand_hw_ecc *data = nand->ecc.priv;
 747         u32 ecc_ctl;
 748
 749         ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
 750         ecc_ctl &= ~(NFC_ECC_MODE_MSK | NFC_ECC_PIPELINE |
 751                      NFC_ECC_BLOCK_SIZE_MSK);
 752         ecc_ctl |= NFC_ECC_EN | NFC_ECC_MODE(data->mode) | NFC_ECC_EXCEPTION |
 753                    NFC_ECC_PIPELINE;
 754
 755         writel(ecc_ctl, nfc->regs + NFC_REG_ECC_CTL);
 756 }
 757
 758 static void sunxi_nfc_hw_ecc_disable(struct mtd_info *mtd)
 759 {
 760         struct nand_chip *nand = mtd_to_nand(mtd);
 761         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 762
 763         writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_ECC_EN,
 764                nfc->regs + NFC_REG_ECC_CTL);
 765 }
 766
 767 static inline void sunxi_nfc_user_data_to_buf(u32 user_data, u8 *buf)
 768 {
 769         buf[0] = user_data;
 770         buf[1] = user_data >> 8;
 771         buf[2] = user_data >> 16;
 772         buf[3] = user_data >> 24;
 773 }
 774
 775 static inline u32 sunxi_nfc_buf_to_user_data(const u8 *buf)
 776 {
 777         return buf[0] | (buf[1] << 8) | (buf[2] << 16) | (buf[3] << 24);
 778 }
 779
 780 static void sunxi_nfc_hw_ecc_get_prot_oob_bytes(struct mtd_info *mtd, u8 *oob,
 781                                                 int step, bool bbm, int page)
 782 {
 783         struct nand_chip *nand = mtd_to_nand(mtd);
 784         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 785
 786         sunxi_nfc_user_data_to_buf(readl(nfc->regs + NFC_REG_USER_DATA(step)),
 787                                    oob);
 788
 789         /* De-randomize the Bad Block Marker. */
 790         if (bbm && (nand->options & NAND_NEED_SCRAMBLING))
 791                 sunxi_nfc_randomize_bbm(mtd, page, oob);
 792 }
 793
 794 static void sunxi_nfc_hw_ecc_set_prot_oob_bytes(struct mtd_info *mtd,
 795                                                 const u8 *oob, int step,
 796                                                 bool bbm, int page)
 797 {
 798         struct nand_chip *nand = mtd_to_nand(mtd);
 799         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 800         u8 user_data[4];
 801
 802         /* Randomize the Bad Block Marker. */
 803         if (bbm && (nand->options & NAND_NEED_SCRAMBLING)) {
 804                 memcpy(user_data, oob, sizeof(user_data));
 805                 sunxi_nfc_randomize_bbm(mtd, page, user_data);
 806                 oob = user_data;
 807         }
 808
 809         writel(sunxi_nfc_buf_to_user_data(oob),
 810                nfc->regs + NFC_REG_USER_DATA(step));
 811 }
 812
 813 static void sunxi_nfc_hw_ecc_update_stats(struct mtd_info *mtd,
 814                                           unsigned int *max_bitflips, int ret)
 815 {
 816         if (ret < 0) {
 817                 mtd->ecc_stats.failed++;
 818         } else {
 819                 mtd->ecc_stats.corrected += ret;
 820                 *max_bitflips = max_t(unsigned int, *max_bitflips, ret);
 821         }
 822 }
 823
 824 static int sunxi_nfc_hw_ecc_correct(struct mtd_info *mtd, u8 *data, u8 *oob,
 825                                     int step, bool *erased)
 826 {
 827         struct nand_chip *nand = mtd_to_nand(mtd);
 828         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 829         struct nand_ecc_ctrl *ecc = &nand->ecc;
 830         u32 status, tmp;
 831
 832         *erased = false;
 833
 834         status = readl(nfc->regs + NFC_REG_ECC_ST);
 835
 836         if (status & NFC_ECC_ERR(step))
 837                 return -EBADMSG;
 838
 839         if (status & NFC_ECC_PAT_FOUND(step)) {
 840                 u8 pattern;
 841
 842                 if (unlikely(!(readl(nfc->regs + NFC_REG_PAT_ID) & 0x1))) {
 843                         pattern = 0x0;
 844                 } else {
 845                         pattern = 0xff;
 846                         *erased = true;
 847                 }
 848
 849                 if (data)
 850                         memset(data, pattern, ecc->size);
 851
 852                 if (oob)
 853                         memset(oob, pattern, ecc->bytes + 4);
 854
 855                 return 0;
 856         }
 857
 858         tmp = readl(nfc->regs + NFC_REG_ECC_ERR_CNT(step));
 859
 860         return NFC_ECC_ERR_CNT(step, tmp);
 861 }
 862
 863 static int sunxi_nfc_hw_ecc_read_chunk(struct mtd_info *mtd,
 864                                        u8 *data, int data_off,
 865                                        u8 *oob, int oob_off,
 866                                        int *cur_off,
 867                                        unsigned int *max_bitflips,
 868                                        bool bbm, bool oob_required, int page)
 869 {
 870         struct nand_chip *nand = mtd_to_nand(mtd);
 871         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 872         struct nand_ecc_ctrl *ecc = &nand->ecc;
 873         int raw_mode = 0;
 874         bool erased;
 875         int ret;
 876
 877         if (*cur_off != data_off)
 878                 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, data_off, -1);
 879
 880         sunxi_nfc_randomizer_read_buf(mtd, NULL, ecc->size, false, page);
 881
 882         if (data_off + ecc->size != oob_off)
 883                 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
 884
 885         ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 886         if (ret)
 887                 return ret;
 888
 889         sunxi_nfc_randomizer_enable(mtd);
 890         writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ECC_OP,
 891                nfc->regs + NFC_REG_CMD);
 892
 893         ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, true, 0);
 894         sunxi_nfc_randomizer_disable(mtd);
 895         if (ret)
 896                 return ret;
 897
 898         *cur_off = oob_off + ecc->bytes + 4;
 899
 900         ret = sunxi_nfc_hw_ecc_correct(mtd, data, oob_required ? oob : NULL, 0,
 901                                        &erased);
 902         if (erased)
 903                 return 1;
 904
 905         if (ret < 0) {
 906                 /*
 907                  * Re-read the data with the randomizer disabled to identify
 908                  * bitflips in erased pages.
 909                  */
 910                 if (nand->options & NAND_NEED_SCRAMBLING) {
 911                         nand->cmdfunc(mtd, NAND_CMD_RNDOUT, data_off, -1);
 912                         nand->read_buf(mtd, data, ecc->size);
 913                 } else {
 914                         memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE,
 915                                       ecc->size);
 916                 }
 917
 918                 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
 919                 nand->read_buf(mtd, oob, ecc->bytes + 4);
 920
 921                 ret = nand_check_erased_ecc_chunk(data, ecc->size,
 922                                                   oob, ecc->bytes + 4,
 923                                                   NULL, 0, ecc->strength);
 924                 if (ret >= 0)
 925                         raw_mode = 1;
 926         } else {
 927                 memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE, ecc->size);
 928
 929                 if (oob_required) {
 930                         nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
 931                         sunxi_nfc_randomizer_read_buf(mtd, oob, ecc->bytes + 4,
 932                                                       true, page);
 933
 934                         sunxi_nfc_hw_ecc_get_prot_oob_bytes(mtd, oob, 0,
 935                                                             bbm, page);
 936                 }
 937         }
 938
 939         sunxi_nfc_hw_ecc_update_stats(mtd, max_bitflips, ret);
 940
 941         return raw_mode;
 942 }
 943
 944 static void sunxi_nfc_hw_ecc_read_extra_oob(struct mtd_info *mtd,
 945                                             u8 *oob, int *cur_off,
 946                                             bool randomize, int page)
 947 {
 948         struct nand_chip *nand = mtd_to_nand(mtd);
 949         struct nand_ecc_ctrl *ecc = &nand->ecc;
 950         int offset = ((ecc->bytes + 4) * ecc->steps);
 951         int len = mtd->oobsize - offset;
 952
 953         if (len <= 0)
 954                 return;
 955
 956         if (!cur_off || *cur_off != offset)
 957                 nand->cmdfunc(mtd, NAND_CMD_RNDOUT,
 958                               offset + mtd->writesize, -1);
 959
 960         if (!randomize)
 961                 sunxi_nfc_read_buf(mtd, oob + offset, len);
 962         else
 963                 sunxi_nfc_randomizer_read_buf(mtd, oob + offset, len,
 964                                               false, page);
 965
 966         if (cur_off)
 967                 *cur_off = mtd->oobsize + mtd->writesize;
 968 }
 969
 970 static int sunxi_nfc_hw_ecc_write_chunk(struct mtd_info *mtd,
 971                                         const u8 *data, int data_off,
 972                                         const u8 *oob, int oob_off,
 973                                         int *cur_off, bool bbm,
 974                                         int page)
 975 {
 976         struct nand_chip *nand = mtd_to_nand(mtd);
 977         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 978         struct nand_ecc_ctrl *ecc = &nand->ecc;
 979         int ret;
 980
 981         if (data_off != *cur_off)
 982                 nand->cmdfunc(mtd, NAND_CMD_RNDIN, data_off, -1);
 983
 984         sunxi_nfc_randomizer_write_buf(mtd, data, ecc->size, false, page);
 985
 986         if (data_off + ecc->size != oob_off)
 987                 nand->cmdfunc(mtd, NAND_CMD_RNDIN, oob_off, -1);
 988
 989         ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 990         if (ret)
 991                 return ret;
 992
 993         sunxi_nfc_randomizer_enable(mtd);
 994         sunxi_nfc_hw_ecc_set_prot_oob_bytes(mtd, oob, 0, bbm, page);
 995
 996         writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
 997                NFC_ACCESS_DIR | NFC_ECC_OP,
 998                nfc->regs + NFC_REG_CMD);
 999
1000         ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, true, 0);
1001         sunxi_nfc_randomizer_disable(mtd);
1002         if (ret)
1003                 return ret;
1004
1005         *cur_off = oob_off + ecc->bytes + 4;
1006
1007         return 0;
1008 }
1009
1010 static void sunxi_nfc_hw_ecc_write_extra_oob(struct mtd_info *mtd,
1011                                              u8 *oob, int *cur_off,
1012                                              int page)
1013 {
1014         struct nand_chip *nand = mtd_to_nand(mtd);
1015         struct nand_ecc_ctrl *ecc = &nand->ecc;
1016         int offset = ((ecc->bytes + 4) * ecc->steps);
1017         int len = mtd->oobsize - offset;
1018
1019         if (len <= 0)
1020                 return;
1021
1022         if (!cur_off || *cur_off != offset)
1023                 nand->cmdfunc(mtd, NAND_CMD_RNDIN,
1024                               offset + mtd->writesize, -1);
1025
1026         sunxi_nfc_randomizer_write_buf(mtd, oob + offset, len, false, page);
1027
1028         if (cur_off)
1029                 *cur_off = mtd->oobsize + mtd->writesize;
1030 }
1031
1032 static int sunxi_nfc_hw_ecc_read_page(struct mtd_info *mtd,
1033                                       struct nand_chip *chip, uint8_t *buf,
1034                                       int oob_required, int page)
1035 {
1036         struct nand_ecc_ctrl *ecc = &chip->ecc;
1037         unsigned int max_bitflips = 0;
1038         int ret, i, cur_off = 0;
1039         bool raw_mode = false;
1040
1041         sunxi_nfc_hw_ecc_enable(mtd);
1042
1043         for (i = 0; i < ecc->steps; i++) {
1044                 int data_off = i * ecc->size;
1045                 int oob_off = i * (ecc->bytes + 4);
1046                 u8 *data = buf + data_off;
1047                 u8 *oob = chip->oob_poi + oob_off;
1048
1049                 ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob,
1050                                                   oob_off + mtd->writesize,
1051                                                   &cur_off, &max_bitflips,
1052                                                   !i, oob_required, page);
1053                 if (ret < 0)
1054                         return ret;
1055                 else if (ret)
1056                         raw_mode = true;
1057         }
1058
1059         if (oob_required)
1060                 sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off,
1061                                                 !raw_mode, page);
1062
1063         sunxi_nfc_hw_ecc_disable(mtd);
1064
1065         return max_bitflips;
1066 }
1067
1068 static int sunxi_nfc_hw_ecc_read_subpage(struct mtd_info *mtd,
1069                                          struct nand_chip *chip,
1070                                          u32 data_offs, u32 readlen,
1071                                          u8 *bufpoi, int page)
1072 {
1073         struct nand_ecc_ctrl *ecc = &chip->ecc;
1074         int ret, i, cur_off = 0;
1075         unsigned int max_bitflips = 0;
1076
1077         sunxi_nfc_hw_ecc_enable(mtd);
1078
1079         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1080         for (i = data_offs / ecc->size;
1081              i < DIV_ROUND_UP(data_offs + readlen, ecc->size); i++) {
1082                 int data_off = i * ecc->size;
1083                 int oob_off = i * (ecc->bytes + 4);
1084                 u8 *data = bufpoi + data_off;
1085                 u8 *oob = chip->oob_poi + oob_off;
1086
1087                 ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off,
1088                                                   oob,
1089                                                   oob_off + mtd->writesize,
1090                                                   &cur_off, &max_bitflips, !i,
1091                                                   false, page);
1092                 if (ret < 0)
1093                         return ret;
1094         }
1095
1096         sunxi_nfc_hw_ecc_disable(mtd);
1097
1098         return max_bitflips;
1099 }
1100
1101 static int sunxi_nfc_hw_ecc_write_page(struct mtd_info *mtd,
1102                                        struct nand_chip *chip,
1103                                        const uint8_t *buf, int oob_required,
1104                                        int page)
1105 {
1106         struct nand_ecc_ctrl *ecc = &chip->ecc;
1107         int ret, i, cur_off = 0;
1108
1109         sunxi_nfc_hw_ecc_enable(mtd);
1110
1111         for (i = 0; i < ecc->steps; i++) {
1112                 int data_off = i * ecc->size;
1113                 int oob_off = i * (ecc->bytes + 4);
1114                 const u8 *data = buf + data_off;
1115                 const u8 *oob = chip->oob_poi + oob_off;
1116
1117                 ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off, oob,
1118                                                    oob_off + mtd->writesize,
1119                                                    &cur_off, !i, page);
1120                 if (ret)
1121                         return ret;
1122         }
1123
1124         if (oob_required || (chip->options & NAND_NEED_SCRAMBLING))
1125                 sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi,
1126                                                  &cur_off, page);
1127
1128         sunxi_nfc_hw_ecc_disable(mtd);
1129
1130         return 0;
1131 }
1132
1133 static int sunxi_nfc_hw_syndrome_ecc_read_page(struct mtd_info *mtd,
1134                                                struct nand_chip *chip,
1135                                                uint8_t *buf, int oob_required,
1136                                                int page)
1137 {
1138         struct nand_ecc_ctrl *ecc = &chip->ecc;
1139         unsigned int max_bitflips = 0;
1140         int ret, i, cur_off = 0;
1141         bool raw_mode = false;
1142
1143         sunxi_nfc_hw_ecc_enable(mtd);
1144
1145         for (i = 0; i < ecc->steps; i++) {
1146                 int data_off = i * (ecc->size + ecc->bytes + 4);
1147                 int oob_off = data_off + ecc->size;
1148                 u8 *data = buf + (i * ecc->size);
1149                 u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4));
1150
1151                 ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob,
1152                                                   oob_off, &cur_off,
1153                                                   &max_bitflips, !i,
1154                                                   oob_required,
1155                                                   page);
1156                 if (ret < 0)
1157                         return ret;
1158                 else if (ret)
1159                         raw_mode = true;
1160         }
1161
1162         if (oob_required)
1163                 sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off,
1164                                                 !raw_mode, page);
1165
1166         sunxi_nfc_hw_ecc_disable(mtd);
1167
1168         return max_bitflips;
1169 }
1170
1171 static int sunxi_nfc_hw_syndrome_ecc_write_page(struct mtd_info *mtd,
1172                                                 struct nand_chip *chip,
1173                                                 const uint8_t *buf,
1174                                                 int oob_required, int page)
1175 {
1176         struct nand_ecc_ctrl *ecc = &chip->ecc;
1177         int ret, i, cur_off = 0;
1178
1179         sunxi_nfc_hw_ecc_enable(mtd);
1180
1181         for (i = 0; i < ecc->steps; i++) {
1182                 int data_off = i * (ecc->size + ecc->bytes + 4);
1183                 int oob_off = data_off + ecc->size;
1184                 const u8 *data = buf + (i * ecc->size);
1185                 const u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4));
1186
1187                 ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off,
1188                                                    oob, oob_off, &cur_off,
1189                                                    false, page);
1190                 if (ret)
1191                         return ret;
1192         }
1193
1194         if (oob_required || (chip->options & NAND_NEED_SCRAMBLING))
1195                 sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi,
1196                                                  &cur_off, page);
1197
1198         sunxi_nfc_hw_ecc_disable(mtd);
1199
1200         return 0;
1201 }
1202
1203 static int sunxi_nfc_hw_common_ecc_read_oob(struct mtd_info *mtd,
1204                                             struct nand_chip *chip,
1205                                             int page)
1206 {
1207         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1208
1209         chip->pagebuf = -1;
1210
1211         return chip->ecc.read_page(mtd, chip, chip->buffers->databuf, 1, page);
1212 }
1213
1214 static int sunxi_nfc_hw_common_ecc_write_oob(struct mtd_info *mtd,
1215                                              struct nand_chip *chip,
1216                                              int page)
1217 {
1218         int ret, status;
1219
1220         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0, page);
1221
1222         chip->pagebuf = -1;
1223
1224         memset(chip->buffers->databuf, 0xff, mtd->writesize);
1225         ret = chip->ecc.write_page(mtd, chip, chip->buffers->databuf, 1, page);
1226         if (ret)
1227                 return ret;
1228
1229         /* Send command to program the OOB data */
1230         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1231
1232         status = chip->waitfunc(mtd, chip);
1233
1234         return status & NAND_STATUS_FAIL ? -EIO : 0;
1235 }
1236
1237 static const s32 tWB_lut[] = {6, 12, 16, 20};
1238 static const s32 tRHW_lut[] = {4, 8, 12, 20};
1239
1240 static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 duration,
1241                 u32 clk_period)
1242 {
1243         u32 clk_cycles = DIV_ROUND_UP(duration, clk_period);
1244         int i;
1245
1246         for (i = 0; i < lut_size; i++) {
1247                 if (clk_cycles <= lut[i])
1248                         return i;
1249         }
1250
1251         /* Doesn't fit */
1252         return -EINVAL;
1253 }
1254
1255 #define sunxi_nand_lookup_timing(l, p, c) \
1256                         _sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c)
1257
1258 static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
1259                                        const struct nand_sdr_timings *timings)
1260 {
1261         struct sunxi_nfc *nfc = to_sunxi_nfc(chip->nand.controller);
1262         u32 min_clk_period = 0;
1263         s32 tWB, tADL, tWHR, tRHW, tCAD;
1264         long real_clk_rate;
1265
1266         /* T1 <=> tCLS */
1267         if (timings->tCLS_min > min_clk_period)
1268                 min_clk_period = timings->tCLS_min;
1269
1270         /* T2 <=> tCLH */
1271         if (timings->tCLH_min > min_clk_period)
1272                 min_clk_period = timings->tCLH_min;
1273
1274         /* T3 <=> tCS */
1275         if (timings->tCS_min > min_clk_period)
1276                 min_clk_period = timings->tCS_min;
1277
1278         /* T4 <=> tCH */
1279         if (timings->tCH_min > min_clk_period)
1280                 min_clk_period = timings->tCH_min;
1281
1282         /* T5 <=> tWP */
1283         if (timings->tWP_min > min_clk_period)
1284                 min_clk_period = timings->tWP_min;
1285
1286         /* T6 <=> tWH */
1287         if (timings->tWH_min > min_clk_period)
1288                 min_clk_period = timings->tWH_min;
1289
1290         /* T7 <=> tALS */
1291         if (timings->tALS_min > min_clk_period)
1292                 min_clk_period = timings->tALS_min;
1293
1294         /* T8 <=> tDS */
1295         if (timings->tDS_min > min_clk_period)
1296                 min_clk_period = timings->tDS_min;
1297
1298         /* T9 <=> tDH */
1299         if (timings->tDH_min > min_clk_period)
1300                 min_clk_period = timings->tDH_min;
1301
1302         /* T10 <=> tRR */
1303         if (timings->tRR_min > (min_clk_period * 3))
1304                 min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3);
1305
1306         /* T11 <=> tALH */
1307         if (timings->tALH_min > min_clk_period)
1308                 min_clk_period = timings->tALH_min;
1309
1310         /* T12 <=> tRP */
1311         if (timings->tRP_min > min_clk_period)
1312                 min_clk_period = timings->tRP_min;
1313
1314         /* T13 <=> tREH */
1315         if (timings->tREH_min > min_clk_period)
1316                 min_clk_period = timings->tREH_min;
1317
1318         /* T14 <=> tRC */
1319         if (timings->tRC_min > (min_clk_period * 2))
1320                 min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2);
1321
1322         /* T15 <=> tWC */
1323         if (timings->tWC_min > (min_clk_period * 2))
1324                 min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2);
1325
1326         /* T16 - T19 + tCAD */
1327         if (timings->tWB_max > (min_clk_period * 20))
1328                 min_clk_period = DIV_ROUND_UP(timings->tWB_max, 20);
1329
1330         if (timings->tADL_min > (min_clk_period * 32))
1331                 min_clk_period = DIV_ROUND_UP(timings->tADL_min, 32);
1332
1333         if (timings->tWHR_min > (min_clk_period * 32))
1334                 min_clk_period = DIV_ROUND_UP(timings->tWHR_min, 32);
1335
1336         if (timings->tRHW_min > (min_clk_period * 20))
1337                 min_clk_period = DIV_ROUND_UP(timings->tRHW_min, 20);
1338
1339         tWB  = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max,
1340                                         min_clk_period);
1341         if (tWB < 0) {
1342                 dev_err(nfc->dev, "unsupported tWB\n");
1343                 return tWB;
1344         }
1345
1346         tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3;
1347         if (tADL > 3) {
1348                 dev_err(nfc->dev, "unsupported tADL\n");
1349                 return -EINVAL;
1350         }
1351
1352         tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3;
1353         if (tWHR > 3) {
1354                 dev_err(nfc->dev, "unsupported tWHR\n");
1355                 return -EINVAL;
1356         }
1357
1358         tRHW = sunxi_nand_lookup_timing(tRHW_lut, timings->tRHW_min,
1359                                         min_clk_period);
1360         if (tRHW < 0) {
1361                 dev_err(nfc->dev, "unsupported tRHW\n");
1362                 return tRHW;
1363         }
1364
1365         /*
1366          * TODO: according to ONFI specs this value only applies for DDR NAND,
1367          * but Allwinner seems to set this to 0x7. Mimic them for now.
1368          */
1369         tCAD = 0x7;
1370
1371         /* TODO: A83 has some more bits for CDQSS, CS, CLHZ, CCS, WC */
1372         chip->timing_cfg = NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD);
1373
1374         /* Convert min_clk_period from picoseconds to nanoseconds */
1375         min_clk_period = DIV_ROUND_UP(min_clk_period, 1000);
1376
1377         /*
1378          * Unlike what is stated in Allwinner datasheet, the clk_rate should
1379          * be set to (1 / min_clk_period), and not (2 / min_clk_period).
1380          * This new formula was verified with a scope and validated by
1381          * Allwinner engineers.
1382          */
1383         chip->clk_rate = NSEC_PER_SEC / min_clk_period;
1384         real_clk_rate = clk_round_rate(nfc->mod_clk, chip->clk_rate);
1385
1386         /*
1387          * ONFI specification 3.1, paragraph 4.15.2 dictates that EDO data
1388          * output cycle timings shall be used if the host drives tRC less than
1389          * 30 ns.
1390          */
1391         min_clk_period = NSEC_PER_SEC / real_clk_rate;
1392         chip->timing_ctl = ((min_clk_period * 2) < 30) ?
1393                            NFC_TIMING_CTL_EDO : 0;
1394
1395         return 0;
1396 }
1397
1398 static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip,
1399                                         struct device_node *np)
1400 {
1401         struct mtd_info *mtd = nand_to_mtd(&chip->nand);
1402         const struct nand_sdr_timings *timings;
1403         int ret;
1404         int mode;
1405
1406         mode = onfi_get_async_timing_mode(&chip->nand);
1407         if (mode == ONFI_TIMING_MODE_UNKNOWN) {
1408                 mode = chip->nand.onfi_timing_mode_default;
1409         } else {
1410                 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {};
1411                 int i;
1412
1413                 mode = fls(mode) - 1;
1414                 if (mode < 0)
1415                         mode = 0;
1416
1417                 feature[0] = mode;
1418                 for (i = 0; i < chip->nsels; i++) {
1419                         chip->nand.select_chip(mtd, i);
1420                         ret = chip->nand.onfi_set_features(mtd, &chip->nand,
1421                                                 ONFI_FEATURE_ADDR_TIMING_MODE,
1422                                                 feature);
1423                         chip->nand.select_chip(mtd, -1);
1424                         if (ret)
1425                                 return ret;
1426                 }
1427         }
1428
1429         timings = onfi_async_timing_mode_to_sdr_timings(mode);
1430         if (IS_ERR(timings))
1431                 return PTR_ERR(timings);
1432
1433         return sunxi_nand_chip_set_timings(chip, timings);
1434 }
1435
1436 static int sunxi_nand_ooblayout_ecc(struct mtd_info *mtd, int section,
1437                                     struct mtd_oob_region *oobregion)
1438 {
1439         struct nand_chip *nand = mtd_to_nand(mtd);
1440         struct nand_ecc_ctrl *ecc = &nand->ecc;
1441
1442         if (section >= ecc->steps)
1443                 return -ERANGE;
1444
1445         oobregion->offset = section * (ecc->bytes + 4) + 4;
1446         oobregion->length = ecc->bytes;
1447
1448         return 0;
1449 }
1450
1451 static int sunxi_nand_ooblayout_free(struct mtd_info *mtd, int section,
1452                                      struct mtd_oob_region *oobregion)
1453 {
1454         struct nand_chip *nand = mtd_to_nand(mtd);
1455         struct nand_ecc_ctrl *ecc = &nand->ecc;
1456
1457         if (section > ecc->steps)
1458                 return -ERANGE;
1459
1460         /*
1461          * The first 2 bytes are used for BB markers, hence we
1462          * only have 2 bytes available in the first user data
1463          * section.
1464          */
1465         if (!section && ecc->mode == NAND_ECC_HW) {
1466                 oobregion->offset = 2;
1467                 oobregion->length = 2;
1468
1469                 return 0;
1470         }
1471
1472         oobregion->offset = section * (ecc->bytes + 4);
1473
1474         if (section < ecc->steps)
1475                 oobregion->length = 4;
1476         else
1477                 oobregion->offset = mtd->oobsize - oobregion->offset;
1478
1479         return 0;
1480 }
1481
1482 static const struct mtd_ooblayout_ops sunxi_nand_ooblayout_ops = {
1483         .ecc = sunxi_nand_ooblayout_ecc,
1484         .free = sunxi_nand_ooblayout_free,
1485 };
1486
1487 static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd,
1488                                               struct nand_ecc_ctrl *ecc,
1489                                               struct device_node *np)
1490 {
1491         static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
1492         struct nand_chip *nand = mtd_to_nand(mtd);
1493         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
1494         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
1495         struct sunxi_nand_hw_ecc *data;
1496         int nsectors;
1497         int ret;
1498         int i;
1499
1500         data = kzalloc(sizeof(*data), GFP_KERNEL);
1501         if (!data)
1502                 return -ENOMEM;
1503
1504         /* Add ECC info retrieval from DT */
1505         for (i = 0; i < ARRAY_SIZE(strengths); i++) {
1506                 if (ecc->strength <= strengths[i])
1507                         break;
1508         }
1509
1510         if (i >= ARRAY_SIZE(strengths)) {
1511                 dev_err(nfc->dev, "unsupported strength\n");
1512                 ret = -ENOTSUPP;
1513                 goto err;
1514         }
1515
1516         data->mode = i;
1517
1518         /* HW ECC always request ECC bytes for 1024 bytes blocks */
1519         ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * 1024), 8);
1520
1521         /* HW ECC always work with even numbers of ECC bytes */
1522         ecc->bytes = ALIGN(ecc->bytes, 2);
1523
1524         nsectors = mtd->writesize / ecc->size;
1525
1526         if (mtd->oobsize < ((ecc->bytes + 4) * nsectors)) {
1527                 ret = -EINVAL;
1528                 goto err;
1529         }
1530
1531         ecc->read_oob = sunxi_nfc_hw_common_ecc_read_oob;
1532         ecc->write_oob = sunxi_nfc_hw_common_ecc_write_oob;
1533         mtd_set_ooblayout(mtd, &sunxi_nand_ooblayout_ops);
1534         ecc->priv = data;
1535
1536         return 0;
1537
1538 err:
1539         kfree(data);
1540
1541         return ret;
1542 }
1543
1544 static void sunxi_nand_hw_common_ecc_ctrl_cleanup(struct nand_ecc_ctrl *ecc)
1545 {
1546         kfree(ecc->priv);
1547 }
1548
1549 static int sunxi_nand_hw_ecc_ctrl_init(struct mtd_info *mtd,
1550                                        struct nand_ecc_ctrl *ecc,
1551                                        struct device_node *np)
1552 {
1553         int ret;
1554
1555         ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc, np);
1556         if (ret)
1557                 return ret;
1558
1559         ecc->read_page = sunxi_nfc_hw_ecc_read_page;
1560         ecc->write_page = sunxi_nfc_hw_ecc_write_page;
1561         ecc->read_oob_raw = nand_read_oob_std;
1562         ecc->write_oob_raw = nand_write_oob_std;
1563         ecc->read_subpage = sunxi_nfc_hw_ecc_read_subpage;
1564
1565         return 0;
1566 }
1567
1568 static int sunxi_nand_hw_syndrome_ecc_ctrl_init(struct mtd_info *mtd,
1569                                                 struct nand_ecc_ctrl *ecc,
1570                                                 struct device_node *np)
1571 {
1572         int ret;
1573
1574         ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc, np);
1575         if (ret)
1576                 return ret;
1577
1578         ecc->prepad = 4;
1579         ecc->read_page = sunxi_nfc_hw_syndrome_ecc_read_page;
1580         ecc->write_page = sunxi_nfc_hw_syndrome_ecc_write_page;
1581         ecc->read_oob_raw = nand_read_oob_syndrome;
1582         ecc->write_oob_raw = nand_write_oob_syndrome;
1583
1584         return 0;
1585 }
1586
1587 static void sunxi_nand_ecc_cleanup(struct nand_ecc_ctrl *ecc)
1588 {
1589         switch (ecc->mode) {
1590         case NAND_ECC_HW:
1591         case NAND_ECC_HW_SYNDROME:
1592                 sunxi_nand_hw_common_ecc_ctrl_cleanup(ecc);
1593                 break;
1594         case NAND_ECC_NONE:
1595         default:
1596                 break;
1597         }
1598 }
1599
1600 static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc,
1601                                struct device_node *np)
1602 {
1603         struct nand_chip *nand = mtd_to_nand(mtd);
1604         int ret;
1605
1606         if (!ecc->size) {
1607                 ecc->size = nand->ecc_step_ds;
1608                 ecc->strength = nand->ecc_strength_ds;
1609         }
1610
1611         if (!ecc->size || !ecc->strength)
1612                 return -EINVAL;
1613
1614         switch (ecc->mode) {
1615         case NAND_ECC_HW:
1616                 ret = sunxi_nand_hw_ecc_ctrl_init(mtd, ecc, np);
1617                 if (ret)
1618                         return ret;
1619                 break;
1620         case NAND_ECC_HW_SYNDROME:
1621                 ret = sunxi_nand_hw_syndrome_ecc_ctrl_init(mtd, ecc, np);
1622                 if (ret)
1623                         return ret;
1624                 break;
1625         case NAND_ECC_NONE:
1626         case NAND_ECC_SOFT:
1627                 break;
1628         default:
1629                 return -EINVAL;
1630         }
1631
1632         return 0;
1633 }
1634
1635 static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
1636                                 struct device_node *np)
1637 {
1638         const struct nand_sdr_timings *timings;
1639         struct sunxi_nand_chip *chip;
1640         struct mtd_info *mtd;
1641         struct nand_chip *nand;
1642         int nsels;
1643         int ret;
1644         int i;
1645         u32 tmp;
1646
1647         if (!of_get_property(np, "reg", &nsels))
1648                 return -EINVAL;
1649
1650         nsels /= sizeof(u32);
1651         if (!nsels) {
1652                 dev_err(dev, "invalid reg property size\n");
1653                 return -EINVAL;
1654         }
1655
1656         chip = devm_kzalloc(dev,
1657                             sizeof(*chip) +
1658                             (nsels * sizeof(struct sunxi_nand_chip_sel)),
1659                             GFP_KERNEL);
1660         if (!chip) {
1661                 dev_err(dev, "could not allocate chip\n");
1662                 return -ENOMEM;
1663         }
1664
1665         chip->nsels = nsels;
1666         chip->selected = -1;
1667
1668         for (i = 0; i < nsels; i++) {
1669                 ret = of_property_read_u32_index(np, "reg", i, &tmp);
1670                 if (ret) {
1671                         dev_err(dev, "could not retrieve reg property: %d\n",
1672                                 ret);
1673                         return ret;
1674                 }
1675
1676                 if (tmp > NFC_MAX_CS) {
1677                         dev_err(dev,
1678                                 "invalid reg value: %u (max CS = 7)\n",
1679                                 tmp);
1680                         return -EINVAL;
1681                 }
1682
1683                 if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
1684                         dev_err(dev, "CS %d already assigned\n", tmp);
1685                         return -EINVAL;
1686                 }
1687
1688                 chip->sels[i].cs = tmp;
1689
1690                 if (!of_property_read_u32_index(np, "allwinner,rb", i, &tmp) &&
1691                     tmp < 2) {
1692                         chip->sels[i].rb.type = RB_NATIVE;
1693                         chip->sels[i].rb.info.nativeid = tmp;
1694                 } else {
1695                         ret = of_get_named_gpio(np, "rb-gpios", i);
1696                         if (ret >= 0) {
1697                                 tmp = ret;
1698                                 chip->sels[i].rb.type = RB_GPIO;
1699                                 chip->sels[i].rb.info.gpio = tmp;
1700                                 ret = devm_gpio_request(dev, tmp, "nand-rb");
1701                                 if (ret)
1702                                         return ret;
1703
1704                                 ret = gpio_direction_input(tmp);
1705                                 if (ret)
1706                                         return ret;
1707                         } else {
1708                                 chip->sels[i].rb.type = RB_NONE;
1709                         }
1710                 }
1711         }
1712
1713         nand = &chip->nand;
1714         /* Default tR value specified in the ONFI spec (chapter 4.15.1) */
1715         nand->chip_delay = 200;
1716         nand->controller = &nfc->controller;
1717         /*
1718          * Set the ECC mode to the default value in case nothing is specified
1719          * in the DT.
1720          */
1721         nand->ecc.mode = NAND_ECC_HW;
1722         nand_set_flash_node(nand, np);
1723         nand->select_chip = sunxi_nfc_select_chip;
1724         nand->cmd_ctrl = sunxi_nfc_cmd_ctrl;
1725         nand->read_buf = sunxi_nfc_read_buf;
1726         nand->write_buf = sunxi_nfc_write_buf;
1727         nand->read_byte = sunxi_nfc_read_byte;
1728
1729         mtd = nand_to_mtd(nand);
1730         mtd->dev.parent = dev;
1731
1732         timings = onfi_async_timing_mode_to_sdr_timings(0);
1733         if (IS_ERR(timings)) {
1734                 ret = PTR_ERR(timings);
1735                 dev_err(dev,
1736                         "could not retrieve timings for ONFI mode 0: %d\n",
1737                         ret);
1738                 return ret;
1739         }
1740
1741         ret = sunxi_nand_chip_set_timings(chip, timings);
1742         if (ret) {
1743                 dev_err(dev, "could not configure chip timings: %d\n", ret);
1744                 return ret;
1745         }
1746
1747         ret = nand_scan_ident(mtd, nsels, NULL);
1748         if (ret)
1749                 return ret;
1750
1751         if (nand->bbt_options & NAND_BBT_USE_FLASH)
1752                 nand->bbt_options |= NAND_BBT_NO_OOB;
1753
1754         if (nand->options & NAND_NEED_SCRAMBLING)
1755                 nand->options |= NAND_NO_SUBPAGE_WRITE;
1756
1757         nand->options |= NAND_SUBPAGE_READ;
1758
1759         ret = sunxi_nand_chip_init_timings(chip, np);
1760         if (ret) {
1761                 dev_err(dev, "could not configure chip timings: %d\n", ret);
1762                 return ret;
1763         }
1764
1765         ret = sunxi_nand_ecc_init(mtd, &nand->ecc, np);
1766         if (ret) {
1767                 dev_err(dev, "ECC init failed: %d\n", ret);
1768                 return ret;
1769         }
1770
1771         ret = nand_scan_tail(mtd);
1772         if (ret) {
1773                 dev_err(dev, "nand_scan_tail failed: %d\n", ret);
1774                 return ret;
1775         }
1776
1777         ret = mtd_device_register(mtd, NULL, 0);
1778         if (ret) {
1779                 dev_err(dev, "failed to register mtd device: %d\n", ret);
1780                 nand_release(mtd);
1781                 return ret;
1782         }
1783
1784         list_add_tail(&chip->node, &nfc->chips);
1785
1786         return 0;
1787 }
1788
1789 static int sunxi_nand_chips_init(struct device *dev, struct sunxi_nfc *nfc)
1790 {
1791         struct device_node *np = dev->of_node;
1792         struct device_node *nand_np;
1793         int nchips = of_get_child_count(np);
1794         int ret;
1795
1796         if (nchips > 8) {
1797                 dev_err(dev, "too many NAND chips: %d (max = 8)\n", nchips);
1798                 return -EINVAL;
1799         }
1800
1801         for_each_child_of_node(np, nand_np) {
1802                 ret = sunxi_nand_chip_init(dev, nfc, nand_np);
1803                 if (ret) {
1804                         of_node_put(nand_np);
1805                         return ret;
1806                 }
1807         }
1808
1809         return 0;
1810 }
1811
1812 static void sunxi_nand_chips_cleanup(struct sunxi_nfc *nfc)
1813 {
1814         struct sunxi_nand_chip *chip;
1815
1816         while (!list_empty(&nfc->chips)) {
1817                 chip = list_first_entry(&nfc->chips, struct sunxi_nand_chip,
1818                                         node);
1819                 nand_release(nand_to_mtd(&chip->nand));
1820                 sunxi_nand_ecc_cleanup(&chip->nand.ecc);
1821                 list_del(&chip->node);
1822         }
1823 }
1824
1825 static int sunxi_nfc_probe(struct platform_device *pdev)
1826 {
1827         struct device *dev = &pdev->dev;
1828         struct resource *r;
1829         struct sunxi_nfc *nfc;
1830         int irq;
1831         int ret;
1832
1833         nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
1834         if (!nfc)
1835                 return -ENOMEM;
1836
1837         nfc->dev = dev;
1838         spin_lock_init(&nfc->controller.lock);
1839         init_waitqueue_head(&nfc->controller.wq);
1840         INIT_LIST_HEAD(&nfc->chips);
1841
1842         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1843         nfc->regs = devm_ioremap_resource(dev, r);
1844         if (IS_ERR(nfc->regs))
1845                 return PTR_ERR(nfc->regs);
1846
1847         irq = platform_get_irq(pdev, 0);
1848         if (irq < 0) {
1849                 dev_err(dev, "failed to retrieve irq\n");
1850                 return irq;
1851         }
1852
1853         nfc->ahb_clk = devm_clk_get(dev, "ahb");
1854         if (IS_ERR(nfc->ahb_clk)) {
1855                 dev_err(dev, "failed to retrieve ahb clk\n");
1856                 return PTR_ERR(nfc->ahb_clk);
1857         }
1858
1859         ret = clk_prepare_enable(nfc->ahb_clk);
1860         if (ret)
1861                 return ret;
1862
1863         nfc->mod_clk = devm_clk_get(dev, "mod");
1864         if (IS_ERR(nfc->mod_clk)) {
1865                 dev_err(dev, "failed to retrieve mod clk\n");
1866                 ret = PTR_ERR(nfc->mod_clk);
1867                 goto out_ahb_clk_unprepare;
1868         }
1869
1870         ret = clk_prepare_enable(nfc->mod_clk);
1871         if (ret)
1872                 goto out_ahb_clk_unprepare;
1873
1874         ret = sunxi_nfc_rst(nfc);
1875         if (ret)
1876                 goto out_mod_clk_unprepare;
1877
1878         writel(0, nfc->regs + NFC_REG_INT);
1879         ret = devm_request_irq(dev, irq, sunxi_nfc_interrupt,
1880                                0, "sunxi-nand", nfc);
1881         if (ret)
1882                 goto out_mod_clk_unprepare;
1883
1884         platform_set_drvdata(pdev, nfc);
1885
1886         ret = sunxi_nand_chips_init(dev, nfc);
1887         if (ret) {
1888                 dev_err(dev, "failed to init nand chips\n");
1889                 goto out_mod_clk_unprepare;
1890         }
1891
1892         return 0;
1893
1894 out_mod_clk_unprepare:
1895         clk_disable_unprepare(nfc->mod_clk);
1896 out_ahb_clk_unprepare:
1897         clk_disable_unprepare(nfc->ahb_clk);
1898
1899         return ret;
1900 }
1901
1902 static int sunxi_nfc_remove(struct platform_device *pdev)
1903 {
1904         struct sunxi_nfc *nfc = platform_get_drvdata(pdev);
1905
1906         sunxi_nand_chips_cleanup(nfc);
1907         clk_disable_unprepare(nfc->mod_clk);
1908         clk_disable_unprepare(nfc->ahb_clk);
1909
1910         return 0;
1911 }
1912
1913 static const struct of_device_id sunxi_nfc_ids[] = {
1914         { .compatible = "allwinner,sun4i-a10-nand" },
1915         { /* sentinel */ }
1916 };
1917 MODULE_DEVICE_TABLE(of, sunxi_nfc_ids);
1918
1919 static struct platform_driver sunxi_nfc_driver = {
1920         .driver = {
1921                 .name = "sunxi_nand",
1922                 .of_match_table = sunxi_nfc_ids,
1923         },
1924         .probe = sunxi_nfc_probe,
1925         .remove = sunxi_nfc_remove,
1926 };
1927 module_platform_driver(sunxi_nfc_driver);
1928
1929 MODULE_LICENSE("GPL v2");
1930 MODULE_AUTHOR("Boris BREZILLON");
1931 MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver");
1932 MODULE_ALIAS("platform:sunxi_nand");