2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
5 * Copyright (c) 2015 CMC Electronics, Inc.
6 * Added support for VLAN Table Unit operations
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/delay.h>
15 #include <linux/etherdevice.h>
16 #include <linux/ethtool.h>
17 #include <linux/if_bridge.h>
18 #include <linux/jiffies.h>
19 #include <linux/list.h>
20 #include <linux/module.h>
21 #include <linux/netdevice.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/phy.h>
25 #include <net/switchdev.h>
26 #include "mv88e6xxx.h"
28 static void assert_smi_lock(struct dsa_switch *ds)
30 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
32 if (unlikely(!mutex_is_locked(&ps->smi_mutex))) {
33 dev_err(ds->master_dev, "SMI lock not held!\n");
38 /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
39 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
40 * will be directly accessible on some {device address,register address}
41 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
42 * will only respond to SMI transactions to that specific address, and
43 * an indirect addressing mechanism needs to be used to access its
46 static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
51 for (i = 0; i < 16; i++) {
52 ret = mdiobus_read_nested(bus, sw_addr, SMI_CMD);
56 if ((ret & SMI_CMD_BUSY) == 0)
63 static int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr,
69 return mdiobus_read_nested(bus, addr, reg);
71 /* Wait for the bus to become free. */
72 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
76 /* Transmit the read command. */
77 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
78 SMI_CMD_OP_22_READ | (addr << 5) | reg);
82 /* Wait for the read command to complete. */
83 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
88 ret = mdiobus_read_nested(bus, sw_addr, SMI_DATA);
95 static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
97 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
102 ret = __mv88e6xxx_reg_read(ps->bus, ps->sw_addr, addr, reg);
106 dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
112 int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
114 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
117 mutex_lock(&ps->smi_mutex);
118 ret = _mv88e6xxx_reg_read(ds, addr, reg);
119 mutex_unlock(&ps->smi_mutex);
124 static int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
130 return mdiobus_write_nested(bus, addr, reg, val);
132 /* Wait for the bus to become free. */
133 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
137 /* Transmit the data to write. */
138 ret = mdiobus_write_nested(bus, sw_addr, SMI_DATA, val);
142 /* Transmit the write command. */
143 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
144 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
148 /* Wait for the write command to complete. */
149 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
156 static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
159 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
163 dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
166 return __mv88e6xxx_reg_write(ps->bus, ps->sw_addr, addr, reg, val);
169 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
171 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
174 mutex_lock(&ps->smi_mutex);
175 ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
176 mutex_unlock(&ps->smi_mutex);
181 int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
185 err = mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_MAC_01,
186 (addr[0] << 8) | addr[1]);
190 err = mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_MAC_23,
191 (addr[2] << 8) | addr[3]);
195 return mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_MAC_45,
196 (addr[4] << 8) | addr[5]);
199 int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
204 for (i = 0; i < 6; i++) {
207 /* Write the MAC address byte. */
208 ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
209 GLOBAL2_SWITCH_MAC_BUSY |
214 /* Wait for the write to complete. */
215 for (j = 0; j < 16; j++) {
216 ret = mv88e6xxx_reg_read(ds, REG_GLOBAL2,
221 if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
231 static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
234 return _mv88e6xxx_reg_read(ds, addr, regnum);
238 static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum,
242 return _mv88e6xxx_reg_write(ds, addr, regnum, val);
246 #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
247 static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
250 unsigned long timeout;
252 ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_CONTROL);
256 ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_CONTROL,
257 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
261 timeout = jiffies + 1 * HZ;
262 while (time_before(jiffies, timeout)) {
263 ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATUS);
267 usleep_range(1000, 2000);
268 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
269 GLOBAL_STATUS_PPU_POLLING)
276 static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
279 unsigned long timeout;
281 ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_CONTROL);
285 err = mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_CONTROL,
286 ret | GLOBAL_CONTROL_PPU_ENABLE);
290 timeout = jiffies + 1 * HZ;
291 while (time_before(jiffies, timeout)) {
292 ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATUS);
296 usleep_range(1000, 2000);
297 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
298 GLOBAL_STATUS_PPU_POLLING)
305 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
307 struct mv88e6xxx_priv_state *ps;
309 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
310 if (mutex_trylock(&ps->ppu_mutex)) {
311 struct dsa_switch *ds = ps->ds;
313 if (mv88e6xxx_ppu_enable(ds) == 0)
314 ps->ppu_disabled = 0;
315 mutex_unlock(&ps->ppu_mutex);
319 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
321 struct mv88e6xxx_priv_state *ps = (void *)_ps;
323 schedule_work(&ps->ppu_work);
326 static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
328 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
331 mutex_lock(&ps->ppu_mutex);
333 /* If the PHY polling unit is enabled, disable it so that
334 * we can access the PHY registers. If it was already
335 * disabled, cancel the timer that is going to re-enable
338 if (!ps->ppu_disabled) {
339 ret = mv88e6xxx_ppu_disable(ds);
341 mutex_unlock(&ps->ppu_mutex);
344 ps->ppu_disabled = 1;
346 del_timer(&ps->ppu_timer);
353 static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
355 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
357 /* Schedule a timer to re-enable the PHY polling unit. */
358 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
359 mutex_unlock(&ps->ppu_mutex);
362 void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
364 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
366 mutex_init(&ps->ppu_mutex);
367 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
368 init_timer(&ps->ppu_timer);
369 ps->ppu_timer.data = (unsigned long)ps;
370 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
373 int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
377 ret = mv88e6xxx_ppu_access_get(ds);
379 ret = mv88e6xxx_reg_read(ds, addr, regnum);
380 mv88e6xxx_ppu_access_put(ds);
386 int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
391 ret = mv88e6xxx_ppu_access_get(ds);
393 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
394 mv88e6xxx_ppu_access_put(ds);
401 static bool mv88e6xxx_6065_family(struct dsa_switch *ds)
403 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
405 return ps->info->family == MV88E6XXX_FAMILY_6065;
408 static bool mv88e6xxx_6095_family(struct dsa_switch *ds)
410 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
412 return ps->info->family == MV88E6XXX_FAMILY_6095;
415 static bool mv88e6xxx_6097_family(struct dsa_switch *ds)
417 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
419 return ps->info->family == MV88E6XXX_FAMILY_6097;
422 static bool mv88e6xxx_6165_family(struct dsa_switch *ds)
424 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
426 return ps->info->family == MV88E6XXX_FAMILY_6165;
429 static bool mv88e6xxx_6185_family(struct dsa_switch *ds)
431 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
433 return ps->info->family == MV88E6XXX_FAMILY_6185;
436 static bool mv88e6xxx_6320_family(struct dsa_switch *ds)
438 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
440 return ps->info->family == MV88E6XXX_FAMILY_6320;
443 static bool mv88e6xxx_6351_family(struct dsa_switch *ds)
445 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
447 return ps->info->family == MV88E6XXX_FAMILY_6351;
450 static bool mv88e6xxx_6352_family(struct dsa_switch *ds)
452 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
454 return ps->info->family == MV88E6XXX_FAMILY_6352;
457 static unsigned int mv88e6xxx_num_databases(struct dsa_switch *ds)
459 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
461 /* The following devices have 4-bit identifiers for 16 databases */
462 if (ps->id == PORT_SWITCH_ID_6061)
465 /* The following devices have 6-bit identifiers for 64 databases */
466 if (ps->id == PORT_SWITCH_ID_6065)
469 /* The following devices have 8-bit identifiers for 256 databases */
470 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
473 /* The following devices have 12-bit identifiers for 4096 databases */
474 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
475 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds))
481 static bool mv88e6xxx_has_fid_reg(struct dsa_switch *ds)
483 /* Does the device have dedicated FID registers for ATU and VTU ops? */
484 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
485 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds))
491 static bool mv88e6xxx_has_stu(struct dsa_switch *ds)
493 /* Does the device have STU and dedicated SID registers for VTU ops? */
494 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
495 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds))
501 /* We expect the switch to perform auto negotiation if there is a real
502 * phy. However, in the case of a fixed link phy, we force the port
503 * settings from the fixed link settings.
505 void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
506 struct phy_device *phydev)
508 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
512 if (!phy_is_pseudo_fixed_link(phydev))
515 mutex_lock(&ps->smi_mutex);
517 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
521 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
522 PORT_PCS_CTRL_FORCE_LINK |
523 PORT_PCS_CTRL_DUPLEX_FULL |
524 PORT_PCS_CTRL_FORCE_DUPLEX |
525 PORT_PCS_CTRL_UNFORCED);
527 reg |= PORT_PCS_CTRL_FORCE_LINK;
529 reg |= PORT_PCS_CTRL_LINK_UP;
531 if (mv88e6xxx_6065_family(ds) && phydev->speed > SPEED_100)
534 switch (phydev->speed) {
536 reg |= PORT_PCS_CTRL_1000;
539 reg |= PORT_PCS_CTRL_100;
542 reg |= PORT_PCS_CTRL_10;
545 pr_info("Unknown speed");
549 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
550 if (phydev->duplex == DUPLEX_FULL)
551 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
553 if ((mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds)) &&
554 (port >= ps->info->num_ports - 2)) {
555 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
556 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
557 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
558 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
559 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
560 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
561 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
563 _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_PCS_CTRL, reg);
566 mutex_unlock(&ps->smi_mutex);
569 static int _mv88e6xxx_stats_wait(struct dsa_switch *ds)
574 for (i = 0; i < 10; i++) {
575 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_OP);
576 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
583 static int _mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
587 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
588 port = (port + 1) << 5;
590 /* Snapshot the hardware statistics counters for this port. */
591 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
592 GLOBAL_STATS_OP_CAPTURE_PORT |
593 GLOBAL_STATS_OP_HIST_RX_TX | port);
597 /* Wait for the snapshotting to complete. */
598 ret = _mv88e6xxx_stats_wait(ds);
605 static void _mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
612 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
613 GLOBAL_STATS_OP_READ_CAPTURED |
614 GLOBAL_STATS_OP_HIST_RX_TX | stat);
618 ret = _mv88e6xxx_stats_wait(ds);
622 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
628 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
635 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
636 { "in_good_octets", 8, 0x00, BANK0, },
637 { "in_bad_octets", 4, 0x02, BANK0, },
638 { "in_unicast", 4, 0x04, BANK0, },
639 { "in_broadcasts", 4, 0x06, BANK0, },
640 { "in_multicasts", 4, 0x07, BANK0, },
641 { "in_pause", 4, 0x16, BANK0, },
642 { "in_undersize", 4, 0x18, BANK0, },
643 { "in_fragments", 4, 0x19, BANK0, },
644 { "in_oversize", 4, 0x1a, BANK0, },
645 { "in_jabber", 4, 0x1b, BANK0, },
646 { "in_rx_error", 4, 0x1c, BANK0, },
647 { "in_fcs_error", 4, 0x1d, BANK0, },
648 { "out_octets", 8, 0x0e, BANK0, },
649 { "out_unicast", 4, 0x10, BANK0, },
650 { "out_broadcasts", 4, 0x13, BANK0, },
651 { "out_multicasts", 4, 0x12, BANK0, },
652 { "out_pause", 4, 0x15, BANK0, },
653 { "excessive", 4, 0x11, BANK0, },
654 { "collisions", 4, 0x1e, BANK0, },
655 { "deferred", 4, 0x05, BANK0, },
656 { "single", 4, 0x14, BANK0, },
657 { "multiple", 4, 0x17, BANK0, },
658 { "out_fcs_error", 4, 0x03, BANK0, },
659 { "late", 4, 0x1f, BANK0, },
660 { "hist_64bytes", 4, 0x08, BANK0, },
661 { "hist_65_127bytes", 4, 0x09, BANK0, },
662 { "hist_128_255bytes", 4, 0x0a, BANK0, },
663 { "hist_256_511bytes", 4, 0x0b, BANK0, },
664 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
665 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
666 { "sw_in_discards", 4, 0x10, PORT, },
667 { "sw_in_filtered", 2, 0x12, PORT, },
668 { "sw_out_filtered", 2, 0x13, PORT, },
669 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
670 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
671 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
672 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
673 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
674 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
675 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
676 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
677 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
678 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
679 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
680 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
681 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
682 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
683 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
684 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
685 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
686 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
687 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
688 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
689 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
690 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
691 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
692 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
693 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
694 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
697 static bool mv88e6xxx_has_stat(struct dsa_switch *ds,
698 struct mv88e6xxx_hw_stat *stat)
700 switch (stat->type) {
704 return mv88e6xxx_6320_family(ds);
706 return mv88e6xxx_6095_family(ds) ||
707 mv88e6xxx_6185_family(ds) ||
708 mv88e6xxx_6097_family(ds) ||
709 mv88e6xxx_6165_family(ds) ||
710 mv88e6xxx_6351_family(ds) ||
711 mv88e6xxx_6352_family(ds);
716 static uint64_t _mv88e6xxx_get_ethtool_stat(struct dsa_switch *ds,
717 struct mv88e6xxx_hw_stat *s,
727 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), s->reg);
732 if (s->sizeof_stat == 4) {
733 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
742 _mv88e6xxx_stats_read(ds, s->reg, &low);
743 if (s->sizeof_stat == 8)
744 _mv88e6xxx_stats_read(ds, s->reg + 1, &high);
746 value = (((u64)high) << 16) | low;
750 void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
752 struct mv88e6xxx_hw_stat *stat;
755 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
756 stat = &mv88e6xxx_hw_stats[i];
757 if (mv88e6xxx_has_stat(ds, stat)) {
758 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
765 int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
767 struct mv88e6xxx_hw_stat *stat;
770 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
771 stat = &mv88e6xxx_hw_stats[i];
772 if (mv88e6xxx_has_stat(ds, stat))
779 mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
780 int port, uint64_t *data)
782 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
783 struct mv88e6xxx_hw_stat *stat;
787 mutex_lock(&ps->smi_mutex);
789 ret = _mv88e6xxx_stats_snapshot(ds, port);
791 mutex_unlock(&ps->smi_mutex);
794 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
795 stat = &mv88e6xxx_hw_stats[i];
796 if (mv88e6xxx_has_stat(ds, stat)) {
797 data[j] = _mv88e6xxx_get_ethtool_stat(ds, stat, port);
802 mutex_unlock(&ps->smi_mutex);
805 int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
807 return 32 * sizeof(u16);
810 void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
811 struct ethtool_regs *regs, void *_p)
818 memset(p, 0xff, 32 * sizeof(u16));
820 for (i = 0; i < 32; i++) {
823 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
829 static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset,
832 unsigned long timeout = jiffies + HZ / 10;
834 while (time_before(jiffies, timeout)) {
837 ret = _mv88e6xxx_reg_read(ds, reg, offset);
843 usleep_range(1000, 2000);
848 static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
850 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
853 mutex_lock(&ps->smi_mutex);
854 ret = _mv88e6xxx_wait(ds, reg, offset, mask);
855 mutex_unlock(&ps->smi_mutex);
860 static int _mv88e6xxx_phy_wait(struct dsa_switch *ds)
862 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
863 GLOBAL2_SMI_OP_BUSY);
866 int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
868 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
869 GLOBAL2_EEPROM_OP_LOAD);
872 int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
874 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
875 GLOBAL2_EEPROM_OP_BUSY);
878 static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
880 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP,
884 static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr,
889 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
890 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
895 ret = _mv88e6xxx_phy_wait(ds);
899 return _mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA);
902 static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr,
907 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
911 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
912 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
915 return _mv88e6xxx_phy_wait(ds);
918 int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
920 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
923 mutex_lock(&ps->smi_mutex);
925 reg = _mv88e6xxx_phy_read_indirect(ds, port, 16);
929 e->eee_enabled = !!(reg & 0x0200);
930 e->tx_lpi_enabled = !!(reg & 0x0100);
932 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
936 e->eee_active = !!(reg & PORT_STATUS_EEE);
940 mutex_unlock(&ps->smi_mutex);
944 int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
945 struct phy_device *phydev, struct ethtool_eee *e)
947 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
951 mutex_lock(&ps->smi_mutex);
953 ret = _mv88e6xxx_phy_read_indirect(ds, port, 16);
960 if (e->tx_lpi_enabled)
963 ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg);
965 mutex_unlock(&ps->smi_mutex);
970 static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, u16 fid, u16 cmd)
974 if (mv88e6xxx_has_fid_reg(ds)) {
975 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, fid);
978 } else if (mv88e6xxx_num_databases(ds) == 256) {
979 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
980 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_CONTROL);
984 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_CONTROL,
986 ((fid << 8) & 0xf000));
990 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
994 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
998 return _mv88e6xxx_atu_wait(ds);
1001 static int _mv88e6xxx_atu_data_write(struct dsa_switch *ds,
1002 struct mv88e6xxx_atu_entry *entry)
1004 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1006 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1007 unsigned int mask, shift;
1010 data |= GLOBAL_ATU_DATA_TRUNK;
1011 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1012 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1014 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1015 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1018 data |= (entry->portv_trunkid << shift) & mask;
1021 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA, data);
1024 static int _mv88e6xxx_atu_flush_move(struct dsa_switch *ds,
1025 struct mv88e6xxx_atu_entry *entry,
1031 err = _mv88e6xxx_atu_wait(ds);
1035 err = _mv88e6xxx_atu_data_write(ds, entry);
1040 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1041 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1043 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1044 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1047 return _mv88e6xxx_atu_cmd(ds, entry->fid, op);
1050 static int _mv88e6xxx_atu_flush(struct dsa_switch *ds, u16 fid, bool static_too)
1052 struct mv88e6xxx_atu_entry entry = {
1054 .state = 0, /* EntryState bits must be 0 */
1057 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1060 static int _mv88e6xxx_atu_move(struct dsa_switch *ds, u16 fid, int from_port,
1061 int to_port, bool static_too)
1063 struct mv88e6xxx_atu_entry entry = {
1068 /* EntryState bits must be 0xF */
1069 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1071 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1072 entry.portv_trunkid = (to_port & 0x0f) << 4;
1073 entry.portv_trunkid |= from_port & 0x0f;
1075 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1078 static int _mv88e6xxx_atu_remove(struct dsa_switch *ds, u16 fid, int port,
1081 /* Destination port 0xF means remove the entries */
1082 return _mv88e6xxx_atu_move(ds, fid, port, 0x0f, static_too);
1085 static const char * const mv88e6xxx_port_state_names[] = {
1086 [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1087 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1088 [PORT_CONTROL_STATE_LEARNING] = "Learning",
1089 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1092 static int _mv88e6xxx_port_state(struct dsa_switch *ds, int port, u8 state)
1097 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL);
1101 oldstate = reg & PORT_CONTROL_STATE_MASK;
1103 if (oldstate != state) {
1104 /* Flush forwarding database if we're moving a port
1105 * from Learning or Forwarding state to Disabled or
1106 * Blocking or Listening state.
1108 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
1109 oldstate == PORT_CONTROL_STATE_FORWARDING)
1110 && (state == PORT_CONTROL_STATE_DISABLED ||
1111 state == PORT_CONTROL_STATE_BLOCKING)) {
1112 ret = _mv88e6xxx_atu_remove(ds, 0, port, false);
1117 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1118 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL,
1123 netdev_dbg(ds->ports[port], "PortState %s (was %s)\n",
1124 mv88e6xxx_port_state_names[state],
1125 mv88e6xxx_port_state_names[oldstate]);
1131 static int _mv88e6xxx_port_based_vlan_map(struct dsa_switch *ds, int port)
1133 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1134 struct net_device *bridge = ps->ports[port].bridge_dev;
1135 const u16 mask = (1 << ps->info->num_ports) - 1;
1136 u16 output_ports = 0;
1140 /* allow CPU port or DSA link(s) to send frames to every port */
1141 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1142 output_ports = mask;
1144 for (i = 0; i < ps->info->num_ports; ++i) {
1145 /* allow sending frames to every group member */
1146 if (bridge && ps->ports[i].bridge_dev == bridge)
1147 output_ports |= BIT(i);
1149 /* allow sending frames to CPU port and DSA link(s) */
1150 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1151 output_ports |= BIT(i);
1155 /* prevent frames from going back out of the port they came in on */
1156 output_ports &= ~BIT(port);
1158 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_BASE_VLAN);
1163 reg |= output_ports & mask;
1165 return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg);
1168 void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1170 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1174 case BR_STATE_DISABLED:
1175 stp_state = PORT_CONTROL_STATE_DISABLED;
1177 case BR_STATE_BLOCKING:
1178 case BR_STATE_LISTENING:
1179 stp_state = PORT_CONTROL_STATE_BLOCKING;
1181 case BR_STATE_LEARNING:
1182 stp_state = PORT_CONTROL_STATE_LEARNING;
1184 case BR_STATE_FORWARDING:
1186 stp_state = PORT_CONTROL_STATE_FORWARDING;
1190 /* mv88e6xxx_port_stp_state_set may be called with softirqs disabled,
1191 * so we can not update the port state directly but need to schedule it.
1193 ps->ports[port].state = stp_state;
1194 set_bit(port, ps->port_state_update_mask);
1195 schedule_work(&ps->bridge_work);
1198 static int _mv88e6xxx_port_pvid(struct dsa_switch *ds, int port, u16 *new,
1204 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_DEFAULT_VLAN);
1208 pvid = ret & PORT_DEFAULT_VLAN_MASK;
1211 ret &= ~PORT_DEFAULT_VLAN_MASK;
1212 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1214 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1215 PORT_DEFAULT_VLAN, ret);
1219 netdev_dbg(ds->ports[port], "DefaultVID %d (was %d)\n", *new,
1229 static int _mv88e6xxx_port_pvid_get(struct dsa_switch *ds, int port, u16 *pvid)
1231 return _mv88e6xxx_port_pvid(ds, port, NULL, pvid);
1234 static int _mv88e6xxx_port_pvid_set(struct dsa_switch *ds, int port, u16 pvid)
1236 return _mv88e6xxx_port_pvid(ds, port, &pvid, NULL);
1239 static int _mv88e6xxx_vtu_wait(struct dsa_switch *ds)
1241 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_VTU_OP,
1242 GLOBAL_VTU_OP_BUSY);
1245 static int _mv88e6xxx_vtu_cmd(struct dsa_switch *ds, u16 op)
1249 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_OP, op);
1253 return _mv88e6xxx_vtu_wait(ds);
1256 static int _mv88e6xxx_vtu_stu_flush(struct dsa_switch *ds)
1260 ret = _mv88e6xxx_vtu_wait(ds);
1264 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_FLUSH_ALL);
1267 static int _mv88e6xxx_vtu_stu_data_read(struct dsa_switch *ds,
1268 struct mv88e6xxx_vtu_stu_entry *entry,
1269 unsigned int nibble_offset)
1271 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1276 for (i = 0; i < 3; ++i) {
1277 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1278 GLOBAL_VTU_DATA_0_3 + i);
1285 for (i = 0; i < ps->info->num_ports; ++i) {
1286 unsigned int shift = (i % 4) * 4 + nibble_offset;
1287 u16 reg = regs[i / 4];
1289 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1295 static int _mv88e6xxx_vtu_stu_data_write(struct dsa_switch *ds,
1296 struct mv88e6xxx_vtu_stu_entry *entry,
1297 unsigned int nibble_offset)
1299 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1300 u16 regs[3] = { 0 };
1304 for (i = 0; i < ps->info->num_ports; ++i) {
1305 unsigned int shift = (i % 4) * 4 + nibble_offset;
1306 u8 data = entry->data[i];
1308 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1311 for (i = 0; i < 3; ++i) {
1312 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL,
1313 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1321 static int _mv88e6xxx_vtu_vid_write(struct dsa_switch *ds, u16 vid)
1323 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID,
1324 vid & GLOBAL_VTU_VID_MASK);
1327 static int _mv88e6xxx_vtu_getnext(struct dsa_switch *ds,
1328 struct mv88e6xxx_vtu_stu_entry *entry)
1330 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1333 ret = _mv88e6xxx_vtu_wait(ds);
1337 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_GET_NEXT);
1341 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1345 next.vid = ret & GLOBAL_VTU_VID_MASK;
1346 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1349 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 0);
1353 if (mv88e6xxx_has_fid_reg(ds)) {
1354 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1359 next.fid = ret & GLOBAL_VTU_FID_MASK;
1360 } else if (mv88e6xxx_num_databases(ds) == 256) {
1361 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1362 * VTU DBNum[3:0] are located in VTU Operation 3:0
1364 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1369 next.fid = (ret & 0xf00) >> 4;
1370 next.fid |= ret & 0xf;
1373 if (mv88e6xxx_has_stu(ds)) {
1374 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1379 next.sid = ret & GLOBAL_VTU_SID_MASK;
1387 int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1388 struct switchdev_obj_port_vlan *vlan,
1389 int (*cb)(struct switchdev_obj *obj))
1391 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1392 struct mv88e6xxx_vtu_stu_entry next;
1396 mutex_lock(&ps->smi_mutex);
1398 err = _mv88e6xxx_port_pvid_get(ds, port, &pvid);
1402 err = _mv88e6xxx_vtu_vid_write(ds, GLOBAL_VTU_VID_MASK);
1407 err = _mv88e6xxx_vtu_getnext(ds, &next);
1414 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1417 /* reinit and dump this VLAN obj */
1418 vlan->vid_begin = vlan->vid_end = next.vid;
1421 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1422 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1424 if (next.vid == pvid)
1425 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1427 err = cb(&vlan->obj);
1430 } while (next.vid < GLOBAL_VTU_VID_MASK);
1433 mutex_unlock(&ps->smi_mutex);
1438 static int _mv88e6xxx_vtu_loadpurge(struct dsa_switch *ds,
1439 struct mv88e6xxx_vtu_stu_entry *entry)
1441 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
1445 ret = _mv88e6xxx_vtu_wait(ds);
1452 /* Write port member tags */
1453 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 0);
1457 if (mv88e6xxx_has_stu(ds)) {
1458 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1459 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1464 if (mv88e6xxx_has_fid_reg(ds)) {
1465 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1466 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_FID, reg);
1469 } else if (mv88e6xxx_num_databases(ds) == 256) {
1470 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1471 * VTU DBNum[3:0] are located in VTU Operation 3:0
1473 op |= (entry->fid & 0xf0) << 8;
1474 op |= entry->fid & 0xf;
1477 reg = GLOBAL_VTU_VID_VALID;
1479 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1480 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1484 return _mv88e6xxx_vtu_cmd(ds, op);
1487 static int _mv88e6xxx_stu_getnext(struct dsa_switch *ds, u8 sid,
1488 struct mv88e6xxx_vtu_stu_entry *entry)
1490 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1493 ret = _mv88e6xxx_vtu_wait(ds);
1497 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID,
1498 sid & GLOBAL_VTU_SID_MASK);
1502 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_GET_NEXT);
1506 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_SID);
1510 next.sid = ret & GLOBAL_VTU_SID_MASK;
1512 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1516 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1519 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 2);
1528 static int _mv88e6xxx_stu_loadpurge(struct dsa_switch *ds,
1529 struct mv88e6xxx_vtu_stu_entry *entry)
1534 ret = _mv88e6xxx_vtu_wait(ds);
1541 /* Write port states */
1542 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 2);
1546 reg = GLOBAL_VTU_VID_VALID;
1548 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1552 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1553 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1557 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1560 static int _mv88e6xxx_port_fid(struct dsa_switch *ds, int port, u16 *new,
1567 if (mv88e6xxx_num_databases(ds) == 4096)
1569 else if (mv88e6xxx_num_databases(ds) == 256)
1574 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1575 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_BASE_VLAN);
1579 fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1582 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1583 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1585 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN,
1591 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1592 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL_1);
1596 fid |= (ret & upper_mask) << 4;
1600 ret |= (*new >> 4) & upper_mask;
1602 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1,
1607 netdev_dbg(ds->ports[port], "FID %d (was %d)\n", *new, fid);
1616 static int _mv88e6xxx_port_fid_get(struct dsa_switch *ds, int port, u16 *fid)
1618 return _mv88e6xxx_port_fid(ds, port, NULL, fid);
1621 static int _mv88e6xxx_port_fid_set(struct dsa_switch *ds, int port, u16 fid)
1623 return _mv88e6xxx_port_fid(ds, port, &fid, NULL);
1626 static int _mv88e6xxx_fid_new(struct dsa_switch *ds, u16 *fid)
1628 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1629 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1630 struct mv88e6xxx_vtu_stu_entry vlan;
1633 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1635 /* Set every FID bit used by the (un)bridged ports */
1636 for (i = 0; i < ps->info->num_ports; ++i) {
1637 err = _mv88e6xxx_port_fid_get(ds, i, fid);
1641 set_bit(*fid, fid_bitmap);
1644 /* Set every FID bit used by the VLAN entries */
1645 err = _mv88e6xxx_vtu_vid_write(ds, GLOBAL_VTU_VID_MASK);
1650 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1657 set_bit(vlan.fid, fid_bitmap);
1658 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1660 /* The reset value 0x000 is used to indicate that multiple address
1661 * databases are not needed. Return the next positive available.
1663 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1664 if (unlikely(*fid >= mv88e6xxx_num_databases(ds)))
1667 /* Clear the database */
1668 return _mv88e6xxx_atu_flush(ds, *fid, true);
1671 static int _mv88e6xxx_vtu_new(struct dsa_switch *ds, u16 vid,
1672 struct mv88e6xxx_vtu_stu_entry *entry)
1674 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1675 struct mv88e6xxx_vtu_stu_entry vlan = {
1681 err = _mv88e6xxx_fid_new(ds, &vlan.fid);
1685 /* exclude all ports except the CPU and DSA ports */
1686 for (i = 0; i < ps->info->num_ports; ++i)
1687 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1688 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1689 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1691 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1692 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1693 struct mv88e6xxx_vtu_stu_entry vstp;
1695 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1696 * implemented, only one STU entry is needed to cover all VTU
1697 * entries. Thus, validate the SID 0.
1700 err = _mv88e6xxx_stu_getnext(ds, GLOBAL_VTU_SID_MASK, &vstp);
1704 if (vstp.sid != vlan.sid || !vstp.valid) {
1705 memset(&vstp, 0, sizeof(vstp));
1707 vstp.sid = vlan.sid;
1709 err = _mv88e6xxx_stu_loadpurge(ds, &vstp);
1719 static int _mv88e6xxx_vtu_get(struct dsa_switch *ds, u16 vid,
1720 struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1727 err = _mv88e6xxx_vtu_vid_write(ds, vid - 1);
1731 err = _mv88e6xxx_vtu_getnext(ds, entry);
1735 if (entry->vid != vid || !entry->valid) {
1738 /* -ENOENT would've been more appropriate, but switchdev expects
1739 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1742 err = _mv88e6xxx_vtu_new(ds, vid, entry);
1748 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1749 u16 vid_begin, u16 vid_end)
1751 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1752 struct mv88e6xxx_vtu_stu_entry vlan;
1758 mutex_lock(&ps->smi_mutex);
1760 err = _mv88e6xxx_vtu_vid_write(ds, vid_begin - 1);
1765 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1772 if (vlan.vid > vid_end)
1775 for (i = 0; i < ps->info->num_ports; ++i) {
1776 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1780 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1783 if (ps->ports[i].bridge_dev ==
1784 ps->ports[port].bridge_dev)
1785 break; /* same bridge, check next VLAN */
1787 netdev_warn(ds->ports[port],
1788 "hardware VLAN %d already used by %s\n",
1790 netdev_name(ps->ports[i].bridge_dev));
1794 } while (vlan.vid < vid_end);
1797 mutex_unlock(&ps->smi_mutex);
1802 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1803 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
1804 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
1805 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
1806 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
1809 int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1810 bool vlan_filtering)
1812 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1813 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1814 PORT_CONTROL_2_8021Q_DISABLED;
1817 mutex_lock(&ps->smi_mutex);
1819 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL_2);
1823 old = ret & PORT_CONTROL_2_8021Q_MASK;
1826 ret &= ~PORT_CONTROL_2_8021Q_MASK;
1827 ret |= new & PORT_CONTROL_2_8021Q_MASK;
1829 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_2,
1834 netdev_dbg(ds->ports[port], "802.1Q Mode %s (was %s)\n",
1835 mv88e6xxx_port_8021q_mode_names[new],
1836 mv88e6xxx_port_8021q_mode_names[old]);
1841 mutex_unlock(&ps->smi_mutex);
1846 int mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1847 const struct switchdev_obj_port_vlan *vlan,
1848 struct switchdev_trans *trans)
1852 /* If the requested port doesn't belong to the same bridge as the VLAN
1853 * members, do not support it (yet) and fallback to software VLAN.
1855 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1860 /* We don't need any dynamic resource from the kernel (yet),
1861 * so skip the prepare phase.
1866 static int _mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, u16 vid,
1869 struct mv88e6xxx_vtu_stu_entry vlan;
1872 err = _mv88e6xxx_vtu_get(ds, vid, &vlan, true);
1876 vlan.data[port] = untagged ?
1877 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1878 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1880 return _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1883 void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1884 const struct switchdev_obj_port_vlan *vlan,
1885 struct switchdev_trans *trans)
1887 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1888 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1889 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1892 mutex_lock(&ps->smi_mutex);
1894 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1895 if (_mv88e6xxx_port_vlan_add(ds, port, vid, untagged))
1896 netdev_err(ds->ports[port], "failed to add VLAN %d%c\n",
1897 vid, untagged ? 'u' : 't');
1899 if (pvid && _mv88e6xxx_port_pvid_set(ds, port, vlan->vid_end))
1900 netdev_err(ds->ports[port], "failed to set PVID %d\n",
1903 mutex_unlock(&ps->smi_mutex);
1906 static int _mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, u16 vid)
1908 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1909 struct mv88e6xxx_vtu_stu_entry vlan;
1912 err = _mv88e6xxx_vtu_get(ds, vid, &vlan, false);
1916 /* Tell switchdev if this VLAN is handled in software */
1917 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1920 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1922 /* keep the VLAN unless all ports are excluded */
1924 for (i = 0; i < ps->info->num_ports; ++i) {
1925 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1928 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1934 err = _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1938 return _mv88e6xxx_atu_remove(ds, vlan.fid, port, false);
1941 int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1942 const struct switchdev_obj_port_vlan *vlan)
1944 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1948 mutex_lock(&ps->smi_mutex);
1950 err = _mv88e6xxx_port_pvid_get(ds, port, &pvid);
1954 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1955 err = _mv88e6xxx_port_vlan_del(ds, port, vid);
1960 err = _mv88e6xxx_port_pvid_set(ds, port, 0);
1967 mutex_unlock(&ps->smi_mutex);
1972 static int _mv88e6xxx_atu_mac_write(struct dsa_switch *ds,
1973 const unsigned char *addr)
1977 for (i = 0; i < 3; i++) {
1978 ret = _mv88e6xxx_reg_write(
1979 ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
1980 (addr[i * 2] << 8) | addr[i * 2 + 1]);
1988 static int _mv88e6xxx_atu_mac_read(struct dsa_switch *ds, unsigned char *addr)
1992 for (i = 0; i < 3; i++) {
1993 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1994 GLOBAL_ATU_MAC_01 + i);
1997 addr[i * 2] = ret >> 8;
1998 addr[i * 2 + 1] = ret & 0xff;
2004 static int _mv88e6xxx_atu_load(struct dsa_switch *ds,
2005 struct mv88e6xxx_atu_entry *entry)
2009 ret = _mv88e6xxx_atu_wait(ds);
2013 ret = _mv88e6xxx_atu_mac_write(ds, entry->mac);
2017 ret = _mv88e6xxx_atu_data_write(ds, entry);
2021 return _mv88e6xxx_atu_cmd(ds, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
2024 static int _mv88e6xxx_port_fdb_load(struct dsa_switch *ds, int port,
2025 const unsigned char *addr, u16 vid,
2028 struct mv88e6xxx_atu_entry entry = { 0 };
2029 struct mv88e6xxx_vtu_stu_entry vlan;
2032 /* Null VLAN ID corresponds to the port private database */
2034 err = _mv88e6xxx_port_fid_get(ds, port, &vlan.fid);
2036 err = _mv88e6xxx_vtu_get(ds, vid, &vlan, false);
2040 entry.fid = vlan.fid;
2041 entry.state = state;
2042 ether_addr_copy(entry.mac, addr);
2043 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2044 entry.trunk = false;
2045 entry.portv_trunkid = BIT(port);
2048 return _mv88e6xxx_atu_load(ds, &entry);
2051 int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2052 const struct switchdev_obj_port_fdb *fdb,
2053 struct switchdev_trans *trans)
2055 /* We don't need any dynamic resource from the kernel (yet),
2056 * so skip the prepare phase.
2061 void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2062 const struct switchdev_obj_port_fdb *fdb,
2063 struct switchdev_trans *trans)
2065 int state = is_multicast_ether_addr(fdb->addr) ?
2066 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2067 GLOBAL_ATU_DATA_STATE_UC_STATIC;
2068 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2070 mutex_lock(&ps->smi_mutex);
2071 if (_mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid, state))
2072 netdev_err(ds->ports[port], "failed to load MAC address\n");
2073 mutex_unlock(&ps->smi_mutex);
2076 int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2077 const struct switchdev_obj_port_fdb *fdb)
2079 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2082 mutex_lock(&ps->smi_mutex);
2083 ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid,
2084 GLOBAL_ATU_DATA_STATE_UNUSED);
2085 mutex_unlock(&ps->smi_mutex);
2090 static int _mv88e6xxx_atu_getnext(struct dsa_switch *ds, u16 fid,
2091 struct mv88e6xxx_atu_entry *entry)
2093 struct mv88e6xxx_atu_entry next = { 0 };
2098 ret = _mv88e6xxx_atu_wait(ds);
2102 ret = _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2106 ret = _mv88e6xxx_atu_mac_read(ds, next.mac);
2110 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
2114 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2115 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2116 unsigned int mask, shift;
2118 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2120 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2121 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2124 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2125 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2128 next.portv_trunkid = (ret & mask) >> shift;
2135 static int _mv88e6xxx_port_fdb_dump_one(struct dsa_switch *ds, u16 fid, u16 vid,
2137 struct switchdev_obj_port_fdb *fdb,
2138 int (*cb)(struct switchdev_obj *obj))
2140 struct mv88e6xxx_atu_entry addr = {
2141 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2145 err = _mv88e6xxx_atu_mac_write(ds, addr.mac);
2150 err = _mv88e6xxx_atu_getnext(ds, fid, &addr);
2154 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2157 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2158 bool is_static = addr.state ==
2159 (is_multicast_ether_addr(addr.mac) ?
2160 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2161 GLOBAL_ATU_DATA_STATE_UC_STATIC);
2164 ether_addr_copy(fdb->addr, addr.mac);
2165 fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2167 err = cb(&fdb->obj);
2171 } while (!is_broadcast_ether_addr(addr.mac));
2176 int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2177 struct switchdev_obj_port_fdb *fdb,
2178 int (*cb)(struct switchdev_obj *obj))
2180 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2181 struct mv88e6xxx_vtu_stu_entry vlan = {
2182 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2187 mutex_lock(&ps->smi_mutex);
2189 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2190 err = _mv88e6xxx_port_fid_get(ds, port, &fid);
2194 err = _mv88e6xxx_port_fdb_dump_one(ds, fid, 0, port, fdb, cb);
2198 /* Dump VLANs' Filtering Information Databases */
2199 err = _mv88e6xxx_vtu_vid_write(ds, vlan.vid);
2204 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
2211 err = _mv88e6xxx_port_fdb_dump_one(ds, vlan.fid, vlan.vid, port,
2215 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2218 mutex_unlock(&ps->smi_mutex);
2223 int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2224 struct net_device *bridge)
2226 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2230 mutex_lock(&ps->smi_mutex);
2232 /* Get or create the bridge FID and assign it to the port */
2233 for (i = 0; i < ps->info->num_ports; ++i)
2234 if (ps->ports[i].bridge_dev == bridge)
2237 if (i < ps->info->num_ports)
2238 err = _mv88e6xxx_port_fid_get(ds, i, &fid);
2240 err = _mv88e6xxx_fid_new(ds, &fid);
2244 err = _mv88e6xxx_port_fid_set(ds, port, fid);
2248 /* Assign the bridge and remap each port's VLANTable */
2249 ps->ports[port].bridge_dev = bridge;
2251 for (i = 0; i < ps->info->num_ports; ++i) {
2252 if (ps->ports[i].bridge_dev == bridge) {
2253 err = _mv88e6xxx_port_based_vlan_map(ds, i);
2260 mutex_unlock(&ps->smi_mutex);
2265 void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2267 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2268 struct net_device *bridge = ps->ports[port].bridge_dev;
2272 mutex_lock(&ps->smi_mutex);
2274 /* Give the port a fresh Filtering Information Database */
2275 if (_mv88e6xxx_fid_new(ds, &fid) ||
2276 _mv88e6xxx_port_fid_set(ds, port, fid))
2277 netdev_warn(ds->ports[port], "failed to assign a new FID\n");
2279 /* Unassign the bridge and remap each port's VLANTable */
2280 ps->ports[port].bridge_dev = NULL;
2282 for (i = 0; i < ps->info->num_ports; ++i)
2283 if (i == port || ps->ports[i].bridge_dev == bridge)
2284 if (_mv88e6xxx_port_based_vlan_map(ds, i))
2285 netdev_warn(ds->ports[i], "failed to remap\n");
2287 mutex_unlock(&ps->smi_mutex);
2290 static void mv88e6xxx_bridge_work(struct work_struct *work)
2292 struct mv88e6xxx_priv_state *ps;
2293 struct dsa_switch *ds;
2296 ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
2299 mutex_lock(&ps->smi_mutex);
2301 for (port = 0; port < ps->info->num_ports; ++port)
2302 if (test_and_clear_bit(port, ps->port_state_update_mask) &&
2303 _mv88e6xxx_port_state(ds, port, ps->ports[port].state))
2304 netdev_warn(ds->ports[port], "failed to update state to %s\n",
2305 mv88e6xxx_port_state_names[ps->ports[port].state]);
2307 mutex_unlock(&ps->smi_mutex);
2310 static int _mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
2315 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2317 goto restore_page_0;
2319 ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val);
2321 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2326 static int _mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page,
2331 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2333 goto restore_page_0;
2335 ret = _mv88e6xxx_phy_read_indirect(ds, port, reg);
2337 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2342 static int mv88e6xxx_power_on_serdes(struct dsa_switch *ds)
2346 ret = _mv88e6xxx_phy_page_read(ds, REG_FIBER_SERDES, PAGE_FIBER_SERDES,
2351 if (ret & BMCR_PDOWN) {
2353 ret = _mv88e6xxx_phy_page_write(ds, REG_FIBER_SERDES,
2354 PAGE_FIBER_SERDES, MII_BMCR,
2361 static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
2363 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2367 mutex_lock(&ps->smi_mutex);
2369 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2370 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2371 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2372 mv88e6xxx_6065_family(ds) || mv88e6xxx_6320_family(ds)) {
2373 /* MAC Forcing register: don't force link, speed,
2374 * duplex or flow control state to any particular
2375 * values on physical ports, but force the CPU port
2376 * and all DSA ports to their maximum bandwidth and
2379 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
2380 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
2381 reg &= ~PORT_PCS_CTRL_UNFORCED;
2382 reg |= PORT_PCS_CTRL_FORCE_LINK |
2383 PORT_PCS_CTRL_LINK_UP |
2384 PORT_PCS_CTRL_DUPLEX_FULL |
2385 PORT_PCS_CTRL_FORCE_DUPLEX;
2386 if (mv88e6xxx_6065_family(ds))
2387 reg |= PORT_PCS_CTRL_100;
2389 reg |= PORT_PCS_CTRL_1000;
2391 reg |= PORT_PCS_CTRL_UNFORCED;
2394 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2395 PORT_PCS_CTRL, reg);
2400 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2401 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2402 * tunneling, determine priority by looking at 802.1p and IP
2403 * priority fields (IP prio has precedence), and set STP state
2406 * If this is the CPU link, use DSA or EDSA tagging depending
2407 * on which tagging mode was configured.
2409 * If this is a link to another switch, use DSA tagging mode.
2411 * If this is the upstream port for this switch, enable
2412 * forwarding of unknown unicasts and multicasts.
2415 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2416 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2417 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
2418 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds))
2419 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2420 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2421 PORT_CONTROL_STATE_FORWARDING;
2422 if (dsa_is_cpu_port(ds, port)) {
2423 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
2424 reg |= PORT_CONTROL_DSA_TAG;
2425 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2426 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2427 mv88e6xxx_6320_family(ds)) {
2428 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2429 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
2431 reg |= PORT_CONTROL_FRAME_MODE_DSA;
2432 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2433 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2436 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2437 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2438 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
2439 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds)) {
2440 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2441 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2444 if (dsa_is_dsa_port(ds, port)) {
2445 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
2446 reg |= PORT_CONTROL_DSA_TAG;
2447 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2448 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2449 mv88e6xxx_6320_family(ds)) {
2450 reg |= PORT_CONTROL_FRAME_MODE_DSA;
2453 if (port == dsa_upstream_port(ds))
2454 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2455 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2458 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2464 /* If this port is connected to a SerDes, make sure the SerDes is not
2467 if (mv88e6xxx_6352_family(ds)) {
2468 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
2471 ret &= PORT_STATUS_CMODE_MASK;
2472 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2473 (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2474 (ret == PORT_STATUS_CMODE_SGMII)) {
2475 ret = mv88e6xxx_power_on_serdes(ds);
2481 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2482 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2483 * untagged frames on this port, do a destination address lookup on all
2484 * received packets as usual, disable ARP mirroring and don't send a
2485 * copy of all transmitted/received frames on this port to the CPU.
2488 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2489 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2490 mv88e6xxx_6095_family(ds) || mv88e6xxx_6320_family(ds) ||
2491 mv88e6xxx_6185_family(ds))
2492 reg = PORT_CONTROL_2_MAP_DA;
2494 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2495 mv88e6xxx_6165_family(ds) || mv88e6xxx_6320_family(ds))
2496 reg |= PORT_CONTROL_2_JUMBO_10240;
2498 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) {
2499 /* Set the upstream port this port should use */
2500 reg |= dsa_upstream_port(ds);
2501 /* enable forwarding of unknown multicast addresses to
2504 if (port == dsa_upstream_port(ds))
2505 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2508 reg |= PORT_CONTROL_2_8021Q_DISABLED;
2511 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2512 PORT_CONTROL_2, reg);
2517 /* Port Association Vector: when learning source addresses
2518 * of packets, add the address to the address database using
2519 * a port bitmap that has only the bit for this port set and
2520 * the other bits clear.
2523 /* Disable learning for DSA and CPU ports */
2524 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2525 reg = PORT_ASSOC_VECTOR_LOCKED_PORT;
2527 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR, reg);
2531 /* Egress rate control 2: disable egress rate control. */
2532 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2,
2537 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2538 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2539 mv88e6xxx_6320_family(ds)) {
2540 /* Do not limit the period of time that this port can
2541 * be paused for by the remote end or the period of
2542 * time that this port can pause the remote end.
2544 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2545 PORT_PAUSE_CTRL, 0x0000);
2549 /* Port ATU control: disable limiting the number of
2550 * address database entries that this port is allowed
2553 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2554 PORT_ATU_CONTROL, 0x0000);
2555 /* Priority Override: disable DA, SA and VTU priority
2558 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2559 PORT_PRI_OVERRIDE, 0x0000);
2563 /* Port Ethertype: use the Ethertype DSA Ethertype
2566 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2567 PORT_ETH_TYPE, ETH_P_EDSA);
2570 /* Tag Remap: use an identity 802.1p prio -> switch
2573 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2574 PORT_TAG_REGMAP_0123, 0x3210);
2578 /* Tag Remap 2: use an identity 802.1p prio -> switch
2581 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2582 PORT_TAG_REGMAP_4567, 0x7654);
2587 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2588 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2589 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2590 mv88e6xxx_6320_family(ds)) {
2591 /* Rate Control: disable ingress rate limiting. */
2592 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2593 PORT_RATE_CONTROL, 0x0001);
2598 /* Port Control 1: disable trunking, disable sending
2599 * learning messages to this port.
2601 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1, 0x0000);
2605 /* Port based VLAN map: give each port its own address
2606 * database, and allow bidirectional communication between the
2607 * CPU and DSA port(s), and the other ports.
2609 ret = _mv88e6xxx_port_fid_set(ds, port, port + 1);
2613 ret = _mv88e6xxx_port_based_vlan_map(ds, port);
2617 /* Default VLAN ID and priority: don't set a default VLAN
2618 * ID, and set the default packet priority to zero.
2620 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
2623 mutex_unlock(&ps->smi_mutex);
2627 int mv88e6xxx_setup_ports(struct dsa_switch *ds)
2629 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2633 for (i = 0; i < ps->info->num_ports; i++) {
2634 ret = mv88e6xxx_setup_port(ds, i);
2641 int mv88e6xxx_setup_common(struct dsa_switch *ds)
2643 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2646 mutex_init(&ps->smi_mutex);
2648 INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
2653 int mv88e6xxx_setup_global(struct dsa_switch *ds)
2655 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2659 mutex_lock(&ps->smi_mutex);
2660 /* Set the default address aging time to 5 minutes, and
2661 * enable address learn messages to be sent to all message
2664 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_CONTROL,
2665 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
2669 /* Configure the IP ToS mapping registers. */
2670 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2673 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2676 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2679 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2682 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2685 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2688 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2691 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2695 /* Configure the IEEE 802.1p priority mapping register. */
2696 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2700 /* Send all frames with destination addresses matching
2701 * 01:80:c2:00:00:0x to the CPU port.
2703 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
2707 /* Ignore removed tag data on doubly tagged packets, disable
2708 * flow control messages, force flow control priority to the
2709 * highest, and send all special multicast frames to the CPU
2710 * port at the highest priority.
2712 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
2713 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
2714 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
2718 /* Program the DSA routing table. */
2719 for (i = 0; i < 32; i++) {
2722 if (ds->pd->rtable &&
2723 i != ds->index && i < ds->dst->pd->nr_chips)
2724 nexthop = ds->pd->rtable[i] & 0x1f;
2726 err = _mv88e6xxx_reg_write(
2728 GLOBAL2_DEVICE_MAPPING,
2729 GLOBAL2_DEVICE_MAPPING_UPDATE |
2730 (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) | nexthop);
2735 /* Clear all trunk masks. */
2736 for (i = 0; i < 8; i++) {
2737 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
2739 (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
2740 ((1 << ps->info->num_ports) - 1));
2745 /* Clear all trunk mappings. */
2746 for (i = 0; i < 16; i++) {
2747 err = _mv88e6xxx_reg_write(
2749 GLOBAL2_TRUNK_MAPPING,
2750 GLOBAL2_TRUNK_MAPPING_UPDATE |
2751 (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
2756 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2757 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2758 mv88e6xxx_6320_family(ds)) {
2759 /* Send all frames with destination addresses matching
2760 * 01:80:c2:00:00:2x to the CPU port.
2762 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL2,
2763 GLOBAL2_MGMT_EN_2X, 0xffff);
2767 /* Initialise cross-chip port VLAN table to reset
2770 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL2,
2771 GLOBAL2_PVT_ADDR, 0x9000);
2775 /* Clear the priority override table. */
2776 for (i = 0; i < 16; i++) {
2777 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL2,
2778 GLOBAL2_PRIO_OVERRIDE,
2785 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2786 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2787 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2788 mv88e6xxx_6320_family(ds)) {
2789 /* Disable ingress rate limiting by resetting all
2790 * ingress rate limit registers to their initial
2793 for (i = 0; i < ps->info->num_ports; i++) {
2794 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL2,
2802 /* Clear the statistics counters for all ports */
2803 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
2804 GLOBAL_STATS_OP_FLUSH_ALL);
2808 /* Wait for the flush to complete. */
2809 err = _mv88e6xxx_stats_wait(ds);
2813 /* Clear all ATU entries */
2814 err = _mv88e6xxx_atu_flush(ds, 0, true);
2818 /* Clear all the VTU and STU entries */
2819 err = _mv88e6xxx_vtu_stu_flush(ds);
2821 mutex_unlock(&ps->smi_mutex);
2826 int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)
2828 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2829 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2830 struct gpio_desc *gpiod = ds->pd->reset;
2831 unsigned long timeout;
2835 mutex_lock(&ps->smi_mutex);
2837 /* Set all ports to the disabled state. */
2838 for (i = 0; i < ps->info->num_ports; i++) {
2839 ret = _mv88e6xxx_reg_read(ds, REG_PORT(i), PORT_CONTROL);
2843 ret = _mv88e6xxx_reg_write(ds, REG_PORT(i), PORT_CONTROL,
2849 /* Wait for transmit queues to drain. */
2850 usleep_range(2000, 4000);
2852 /* If there is a gpio connected to the reset pin, toggle it */
2854 gpiod_set_value_cansleep(gpiod, 1);
2855 usleep_range(10000, 20000);
2856 gpiod_set_value_cansleep(gpiod, 0);
2857 usleep_range(10000, 20000);
2860 /* Reset the switch. Keep the PPU active if requested. The PPU
2861 * needs to be active to support indirect phy register access
2862 * through global registers 0x18 and 0x19.
2865 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x04, 0xc000);
2867 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x04, 0xc400);
2871 /* Wait up to one second for reset to complete. */
2872 timeout = jiffies + 1 * HZ;
2873 while (time_before(jiffies, timeout)) {
2874 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x00);
2878 if ((ret & is_reset) == is_reset)
2880 usleep_range(1000, 2000);
2882 if (time_after(jiffies, timeout))
2887 mutex_unlock(&ps->smi_mutex);
2892 int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
2894 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2897 mutex_lock(&ps->smi_mutex);
2898 ret = _mv88e6xxx_phy_page_read(ds, port, page, reg);
2899 mutex_unlock(&ps->smi_mutex);
2904 int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
2907 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2910 mutex_lock(&ps->smi_mutex);
2911 ret = _mv88e6xxx_phy_page_write(ds, port, page, reg, val);
2912 mutex_unlock(&ps->smi_mutex);
2917 static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port)
2919 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2921 if (port >= 0 && port < ps->info->num_ports)
2927 mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
2929 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2930 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2936 mutex_lock(&ps->smi_mutex);
2937 ret = _mv88e6xxx_phy_read(ds, addr, regnum);
2938 mutex_unlock(&ps->smi_mutex);
2943 mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
2945 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2946 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2952 mutex_lock(&ps->smi_mutex);
2953 ret = _mv88e6xxx_phy_write(ds, addr, regnum, val);
2954 mutex_unlock(&ps->smi_mutex);
2959 mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum)
2961 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2962 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2968 mutex_lock(&ps->smi_mutex);
2969 ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum);
2970 mutex_unlock(&ps->smi_mutex);
2975 mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
2978 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2979 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2985 mutex_lock(&ps->smi_mutex);
2986 ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val);
2987 mutex_unlock(&ps->smi_mutex);
2991 #ifdef CONFIG_NET_DSA_HWMON
2993 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
2995 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3001 mutex_lock(&ps->smi_mutex);
3003 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
3007 /* Enable temperature sensor */
3008 ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
3012 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
3016 /* Wait for temperature to stabilize */
3017 usleep_range(10000, 12000);
3019 val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
3025 /* Disable temperature sensor */
3026 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
3030 *temp = ((val & 0x1f) - 5) * 5;
3033 _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
3034 mutex_unlock(&ps->smi_mutex);
3038 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3040 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
3045 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 27);
3049 *temp = (ret & 0xff) - 25;
3054 int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3056 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
3057 return mv88e63xx_get_temp(ds, temp);
3059 return mv88e61xx_get_temp(ds, temp);
3062 int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3064 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
3067 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
3072 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3076 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
3081 int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3083 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
3086 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
3089 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3092 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3093 return mv88e6xxx_phy_page_write(ds, phy, 6, 26,
3094 (ret & 0xe0ff) | (temp << 8));
3097 int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3099 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
3102 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
3107 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3111 *alarm = !!(ret & 0x40);
3115 #endif /* CONFIG_NET_DSA_HWMON */
3117 static const struct mv88e6xxx_info *
3118 mv88e6xxx_lookup_info(unsigned int prod_num, const struct mv88e6xxx_info *table,
3123 for (i = 0; i < num; ++i)
3124 if (table[i].prod_num == prod_num)
3130 const char *mv88e6xxx_drv_probe(struct device *dsa_dev, struct device *host_dev,
3131 int sw_addr, void **priv,
3132 const struct mv88e6xxx_info *table,
3135 const struct mv88e6xxx_info *info;
3136 struct mv88e6xxx_priv_state *ps;
3137 struct mii_bus *bus;
3139 int id, prod_num, rev;
3141 bus = dsa_host_dev_to_mii_bus(host_dev);
3145 id = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), PORT_SWITCH_ID);
3149 prod_num = (id & 0xfff0) >> 4;
3152 info = mv88e6xxx_lookup_info(prod_num, table, num);
3158 ps = devm_kzalloc(dsa_dev, sizeof(*ps), GFP_KERNEL);
3163 ps->sw_addr = sw_addr;
3165 ps->id = id & 0xfff0;
3169 dev_info(&ps->bus->dev, "switch 0x%x probed: %s, revision %u\n",
3170 prod_num, name, rev);
3175 static int __init mv88e6xxx_init(void)
3177 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
3178 register_switch_driver(&mv88e6131_switch_driver);
3180 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123)
3181 register_switch_driver(&mv88e6123_switch_driver);
3183 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
3184 register_switch_driver(&mv88e6352_switch_driver);
3186 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
3187 register_switch_driver(&mv88e6171_switch_driver);
3191 module_init(mv88e6xxx_init);
3193 static void __exit mv88e6xxx_cleanup(void)
3195 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
3196 unregister_switch_driver(&mv88e6171_switch_driver);
3198 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
3199 unregister_switch_driver(&mv88e6352_switch_driver);
3201 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123)
3202 unregister_switch_driver(&mv88e6123_switch_driver);
3204 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
3205 unregister_switch_driver(&mv88e6131_switch_driver);
3208 module_exit(mv88e6xxx_cleanup);
3210 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
3211 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
3212 MODULE_LICENSE("GPL");