drivers/net/dsa/mv88e6xxx.c

   1 /*
   2  * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
   3  * Copyright (c) 2008 Marvell Semiconductor
   4  *
   5  * Copyright (c) 2015 CMC Electronics, Inc.
   6  *      Added support for VLAN Table Unit operations
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/delay.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/ethtool.h>
  17 #include <linux/if_bridge.h>
  18 #include <linux/jiffies.h>
  19 #include <linux/list.h>
  20 #include <linux/module.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/gpio/consumer.h>
  23 #include <linux/phy.h>
  24 #include <net/dsa.h>
  25 #include <net/switchdev.h>
  26 #include "mv88e6xxx.h"
  27
  28 static void assert_smi_lock(struct mv88e6xxx_priv_state *ps)
  29 {
  30         if (unlikely(!mutex_is_locked(&ps->smi_mutex))) {
  31                 dev_err(ps->dev, "SMI lock not held!\n");
  32                 dump_stack();
  33         }
  34 }
  35
  36 /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
  37  * use all 32 SMI bus addresses on its SMI bus, and all switch registers
  38  * will be directly accessible on some {device address,register address}
  39  * pair.  If the ADDR[4:0] pins are not strapped to zero, the switch
  40  * will only respond to SMI transactions to that specific address, and
  41  * an indirect addressing mechanism needs to be used to access its
  42  * registers.
  43  */
  44 static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
  45 {
  46         int ret;
  47         int i;
  48
  49         for (i = 0; i < 16; i++) {
  50                 ret = mdiobus_read_nested(bus, sw_addr, SMI_CMD);
  51                 if (ret < 0)
  52                         return ret;
  53
  54                 if ((ret & SMI_CMD_BUSY) == 0)
  55                         return 0;
  56         }
  57
  58         return -ETIMEDOUT;
  59 }
  60
  61 static int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr,
  62                                 int reg)
  63 {
  64         int ret;
  65
  66         if (sw_addr == 0)
  67                 return mdiobus_read_nested(bus, addr, reg);
  68
  69         /* Wait for the bus to become free. */
  70         ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
  71         if (ret < 0)
  72                 return ret;
  73
  74         /* Transmit the read command. */
  75         ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
  76                                    SMI_CMD_OP_22_READ | (addr << 5) | reg);
  77         if (ret < 0)
  78                 return ret;
  79
  80         /* Wait for the read command to complete. */
  81         ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
  82         if (ret < 0)
  83                 return ret;
  84
  85         /* Read the data. */
  86         ret = mdiobus_read_nested(bus, sw_addr, SMI_DATA);
  87         if (ret < 0)
  88                 return ret;
  89
  90         return ret & 0xffff;
  91 }
  92
  93 static int _mv88e6xxx_reg_read(struct mv88e6xxx_priv_state *ps,
  94                                int addr, int reg)
  95 {
  96         int ret;
  97
  98         assert_smi_lock(ps);
  99
 100         ret = __mv88e6xxx_reg_read(ps->bus, ps->sw_addr, addr, reg);
 101         if (ret < 0)
 102                 return ret;
 103
 104         dev_dbg(ps->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
 105                 addr, reg, ret);
 106
 107         return ret;
 108 }
 109
 110 int mv88e6xxx_reg_read(struct mv88e6xxx_priv_state *ps, int addr, int reg)
 111 {
 112         int ret;
 113
 114         mutex_lock(&ps->smi_mutex);
 115         ret = _mv88e6xxx_reg_read(ps, addr, reg);
 116         mutex_unlock(&ps->smi_mutex);
 117
 118         return ret;
 119 }
 120
 121 static int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
 122                                  int reg, u16 val)
 123 {
 124         int ret;
 125
 126         if (sw_addr == 0)
 127                 return mdiobus_write_nested(bus, addr, reg, val);
 128
 129         /* Wait for the bus to become free. */
 130         ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
 131         if (ret < 0)
 132                 return ret;
 133
 134         /* Transmit the data to write. */
 135         ret = mdiobus_write_nested(bus, sw_addr, SMI_DATA, val);
 136         if (ret < 0)
 137                 return ret;
 138
 139         /* Transmit the write command. */
 140         ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
 141                                    SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
 142         if (ret < 0)
 143                 return ret;
 144
 145         /* Wait for the write command to complete. */
 146         ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
 147         if (ret < 0)
 148                 return ret;
 149
 150         return 0;
 151 }
 152
 153 static int _mv88e6xxx_reg_write(struct mv88e6xxx_priv_state *ps, int addr,
 154                                 int reg, u16 val)
 155 {
 156         assert_smi_lock(ps);
 157
 158         dev_dbg(ps->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
 159                 addr, reg, val);
 160
 161         return __mv88e6xxx_reg_write(ps->bus, ps->sw_addr, addr, reg, val);
 162 }
 163
 164 int mv88e6xxx_reg_write(struct mv88e6xxx_priv_state *ps, int addr,
 165                         int reg, u16 val)
 166 {
 167         int ret;
 168
 169         mutex_lock(&ps->smi_mutex);
 170         ret = _mv88e6xxx_reg_write(ps, addr, reg, val);
 171         mutex_unlock(&ps->smi_mutex);
 172
 173         return ret;
 174 }
 175
 176 static int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
 177 {
 178         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 179         int err;
 180
 181         err = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MAC_01,
 182                                   (addr[0] << 8) | addr[1]);
 183         if (err)
 184                 return err;
 185
 186         err = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MAC_23,
 187                                   (addr[2] << 8) | addr[3]);
 188         if (err)
 189                 return err;
 190
 191         return mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MAC_45,
 192                                    (addr[4] << 8) | addr[5]);
 193 }
 194
 195 static int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
 196 {
 197         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 198         int ret;
 199         int i;
 200
 201         for (i = 0; i < 6; i++) {
 202                 int j;
 203
 204                 /* Write the MAC address byte. */
 205                 ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
 206                                           GLOBAL2_SWITCH_MAC_BUSY |
 207                                           (i << 8) | addr[i]);
 208                 if (ret)
 209                         return ret;
 210
 211                 /* Wait for the write to complete. */
 212                 for (j = 0; j < 16; j++) {
 213                         ret = mv88e6xxx_reg_read(ps, REG_GLOBAL2,
 214                                                  GLOBAL2_SWITCH_MAC);
 215                         if (ret < 0)
 216                                 return ret;
 217
 218                         if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
 219                                 break;
 220                 }
 221                 if (j == 16)
 222                         return -ETIMEDOUT;
 223         }
 224
 225         return 0;
 226 }
 227
 228 int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
 229 {
 230         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 231
 232         if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_SWITCH_MAC))
 233                 return mv88e6xxx_set_addr_indirect(ds, addr);
 234         else
 235                 return mv88e6xxx_set_addr_direct(ds, addr);
 236 }
 237
 238 static int _mv88e6xxx_phy_read(struct mv88e6xxx_priv_state *ps, int addr,
 239                                int regnum)
 240 {
 241         if (addr >= 0)
 242                 return _mv88e6xxx_reg_read(ps, addr, regnum);
 243         return 0xffff;
 244 }
 245
 246 static int _mv88e6xxx_phy_write(struct mv88e6xxx_priv_state *ps, int addr,
 247                                 int regnum, u16 val)
 248 {
 249         if (addr >= 0)
 250                 return _mv88e6xxx_reg_write(ps, addr, regnum, val);
 251         return 0;
 252 }
 253
 254 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_priv_state *ps)
 255 {
 256         int ret;
 257         unsigned long timeout;
 258
 259         ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_CONTROL);
 260         if (ret < 0)
 261                 return ret;
 262
 263         ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL,
 264                                    ret & ~GLOBAL_CONTROL_PPU_ENABLE);
 265         if (ret)
 266                 return ret;
 267
 268         timeout = jiffies + 1 * HZ;
 269         while (time_before(jiffies, timeout)) {
 270                 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATUS);
 271                 if (ret < 0)
 272                         return ret;
 273
 274                 usleep_range(1000, 2000);
 275                 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
 276                     GLOBAL_STATUS_PPU_POLLING)
 277                         return 0;
 278         }
 279
 280         return -ETIMEDOUT;
 281 }
 282
 283 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_priv_state *ps)
 284 {
 285         int ret, err;
 286         unsigned long timeout;
 287
 288         ret = mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_CONTROL);
 289         if (ret < 0)
 290                 return ret;
 291
 292         err = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL,
 293                                   ret | GLOBAL_CONTROL_PPU_ENABLE);
 294         if (err)
 295                 return err;
 296
 297         timeout = jiffies + 1 * HZ;
 298         while (time_before(jiffies, timeout)) {
 299                 ret = mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATUS);
 300                 if (ret < 0)
 301                         return ret;
 302
 303                 usleep_range(1000, 2000);
 304                 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
 305                     GLOBAL_STATUS_PPU_POLLING)
 306                         return 0;
 307         }
 308
 309         return -ETIMEDOUT;
 310 }
 311
 312 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
 313 {
 314         struct mv88e6xxx_priv_state *ps;
 315
 316         ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
 317         if (mutex_trylock(&ps->ppu_mutex)) {
 318                 if (mv88e6xxx_ppu_enable(ps) == 0)
 319                         ps->ppu_disabled = 0;
 320                 mutex_unlock(&ps->ppu_mutex);
 321         }
 322 }
 323
 324 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
 325 {
 326         struct mv88e6xxx_priv_state *ps = (void *)_ps;
 327
 328         schedule_work(&ps->ppu_work);
 329 }
 330
 331 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_priv_state *ps)
 332 {
 333         int ret;
 334
 335         mutex_lock(&ps->ppu_mutex);
 336
 337         /* If the PHY polling unit is enabled, disable it so that
 338          * we can access the PHY registers.  If it was already
 339          * disabled, cancel the timer that is going to re-enable
 340          * it.
 341          */
 342         if (!ps->ppu_disabled) {
 343                 ret = mv88e6xxx_ppu_disable(ps);
 344                 if (ret < 0) {
 345                         mutex_unlock(&ps->ppu_mutex);
 346                         return ret;
 347                 }
 348                 ps->ppu_disabled = 1;
 349         } else {
 350                 del_timer(&ps->ppu_timer);
 351                 ret = 0;
 352         }
 353
 354         return ret;
 355 }
 356
 357 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_priv_state *ps)
 358 {
 359         /* Schedule a timer to re-enable the PHY polling unit. */
 360         mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
 361         mutex_unlock(&ps->ppu_mutex);
 362 }
 363
 364 void mv88e6xxx_ppu_state_init(struct mv88e6xxx_priv_state *ps)
 365 {
 366         mutex_init(&ps->ppu_mutex);
 367         INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
 368         init_timer(&ps->ppu_timer);
 369         ps->ppu_timer.data = (unsigned long)ps;
 370         ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
 371 }
 372
 373 static int mv88e6xxx_phy_read_ppu(struct mv88e6xxx_priv_state *ps, int addr,
 374                                   int regnum)
 375 {
 376         int ret;
 377
 378         ret = mv88e6xxx_ppu_access_get(ps);
 379         if (ret >= 0) {
 380                 ret = _mv88e6xxx_reg_read(ps, addr, regnum);
 381                 mv88e6xxx_ppu_access_put(ps);
 382         }
 383
 384         return ret;
 385 }
 386
 387 static int mv88e6xxx_phy_write_ppu(struct mv88e6xxx_priv_state *ps, int addr,
 388                                    int regnum, u16 val)
 389 {
 390         int ret;
 391
 392         ret = mv88e6xxx_ppu_access_get(ps);
 393         if (ret >= 0) {
 394                 ret = _mv88e6xxx_reg_write(ps, addr, regnum, val);
 395                 mv88e6xxx_ppu_access_put(ps);
 396         }
 397
 398         return ret;
 399 }
 400
 401 static bool mv88e6xxx_6065_family(struct mv88e6xxx_priv_state *ps)
 402 {
 403         return ps->info->family == MV88E6XXX_FAMILY_6065;
 404 }
 405
 406 static bool mv88e6xxx_6095_family(struct mv88e6xxx_priv_state *ps)
 407 {
 408         return ps->info->family == MV88E6XXX_FAMILY_6095;
 409 }
 410
 411 static bool mv88e6xxx_6097_family(struct mv88e6xxx_priv_state *ps)
 412 {
 413         return ps->info->family == MV88E6XXX_FAMILY_6097;
 414 }
 415
 416 static bool mv88e6xxx_6165_family(struct mv88e6xxx_priv_state *ps)
 417 {
 418         return ps->info->family == MV88E6XXX_FAMILY_6165;
 419 }
 420
 421 static bool mv88e6xxx_6185_family(struct mv88e6xxx_priv_state *ps)
 422 {
 423         return ps->info->family == MV88E6XXX_FAMILY_6185;
 424 }
 425
 426 static bool mv88e6xxx_6320_family(struct mv88e6xxx_priv_state *ps)
 427 {
 428         return ps->info->family == MV88E6XXX_FAMILY_6320;
 429 }
 430
 431 static bool mv88e6xxx_6351_family(struct mv88e6xxx_priv_state *ps)
 432 {
 433         return ps->info->family == MV88E6XXX_FAMILY_6351;
 434 }
 435
 436 static bool mv88e6xxx_6352_family(struct mv88e6xxx_priv_state *ps)
 437 {
 438         return ps->info->family == MV88E6XXX_FAMILY_6352;
 439 }
 440
 441 static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_priv_state *ps)
 442 {
 443         return ps->info->num_databases;
 444 }
 445
 446 static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_priv_state *ps)
 447 {
 448         /* Does the device have dedicated FID registers for ATU and VTU ops? */
 449         if (mv88e6xxx_6097_family(ps) || mv88e6xxx_6165_family(ps) ||
 450             mv88e6xxx_6351_family(ps) || mv88e6xxx_6352_family(ps))
 451                 return true;
 452
 453         return false;
 454 }
 455
 456 static bool mv88e6xxx_has_stu(struct mv88e6xxx_priv_state *ps)
 457 {
 458         /* Does the device have STU and dedicated SID registers for VTU ops? */
 459         if (mv88e6xxx_6097_family(ps) || mv88e6xxx_6165_family(ps) ||
 460             mv88e6xxx_6351_family(ps) || mv88e6xxx_6352_family(ps))
 461                 return true;
 462
 463         return false;
 464 }
 465
 466 /* We expect the switch to perform auto negotiation if there is a real
 467  * phy. However, in the case of a fixed link phy, we force the port
 468  * settings from the fixed link settings.
 469  */
 470 void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
 471                            struct phy_device *phydev)
 472 {
 473         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 474         u32 reg;
 475         int ret;
 476
 477         if (!phy_is_pseudo_fixed_link(phydev))
 478                 return;
 479
 480         mutex_lock(&ps->smi_mutex);
 481
 482         ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_PCS_CTRL);
 483         if (ret < 0)
 484                 goto out;
 485
 486         reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
 487                       PORT_PCS_CTRL_FORCE_LINK |
 488                       PORT_PCS_CTRL_DUPLEX_FULL |
 489                       PORT_PCS_CTRL_FORCE_DUPLEX |
 490                       PORT_PCS_CTRL_UNFORCED);
 491
 492         reg |= PORT_PCS_CTRL_FORCE_LINK;
 493         if (phydev->link)
 494                         reg |= PORT_PCS_CTRL_LINK_UP;
 495
 496         if (mv88e6xxx_6065_family(ps) && phydev->speed > SPEED_100)
 497                 goto out;
 498
 499         switch (phydev->speed) {
 500         case SPEED_1000:
 501                 reg |= PORT_PCS_CTRL_1000;
 502                 break;
 503         case SPEED_100:
 504                 reg |= PORT_PCS_CTRL_100;
 505                 break;
 506         case SPEED_10:
 507                 reg |= PORT_PCS_CTRL_10;
 508                 break;
 509         default:
 510                 pr_info("Unknown speed");
 511                 goto out;
 512         }
 513
 514         reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
 515         if (phydev->duplex == DUPLEX_FULL)
 516                 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
 517
 518         if ((mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps)) &&
 519             (port >= ps->info->num_ports - 2)) {
 520                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 521                         reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
 522                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 523                         reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
 524                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 525                         reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
 526                                 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
 527         }
 528         _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_PCS_CTRL, reg);
 529
 530 out:
 531         mutex_unlock(&ps->smi_mutex);
 532 }
 533
 534 static int _mv88e6xxx_stats_wait(struct mv88e6xxx_priv_state *ps)
 535 {
 536         int ret;
 537         int i;
 538
 539         for (i = 0; i < 10; i++) {
 540                 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATS_OP);
 541                 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
 542                         return 0;
 543         }
 544
 545         return -ETIMEDOUT;
 546 }
 547
 548 static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_priv_state *ps,
 549                                      int port)
 550 {
 551         int ret;
 552
 553         if (mv88e6xxx_6320_family(ps) || mv88e6xxx_6352_family(ps))
 554                 port = (port + 1) << 5;
 555
 556         /* Snapshot the hardware statistics counters for this port. */
 557         ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_STATS_OP,
 558                                    GLOBAL_STATS_OP_CAPTURE_PORT |
 559                                    GLOBAL_STATS_OP_HIST_RX_TX | port);
 560         if (ret < 0)
 561                 return ret;
 562
 563         /* Wait for the snapshotting to complete. */
 564         ret = _mv88e6xxx_stats_wait(ps);
 565         if (ret < 0)
 566                 return ret;
 567
 568         return 0;
 569 }
 570
 571 static void _mv88e6xxx_stats_read(struct mv88e6xxx_priv_state *ps,
 572                                   int stat, u32 *val)
 573 {
 574         u32 _val;
 575         int ret;
 576
 577         *val = 0;
 578
 579         ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_STATS_OP,
 580                                    GLOBAL_STATS_OP_READ_CAPTURED |
 581                                    GLOBAL_STATS_OP_HIST_RX_TX | stat);
 582         if (ret < 0)
 583                 return;
 584
 585         ret = _mv88e6xxx_stats_wait(ps);
 586         if (ret < 0)
 587                 return;
 588
 589         ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
 590         if (ret < 0)
 591                 return;
 592
 593         _val = ret << 16;
 594
 595         ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
 596         if (ret < 0)
 597                 return;
 598
 599         *val = _val | ret;
 600 }
 601
 602 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
 603         { "in_good_octets",     8, 0x00, BANK0, },
 604         { "in_bad_octets",      4, 0x02, BANK0, },
 605         { "in_unicast",         4, 0x04, BANK0, },
 606         { "in_broadcasts",      4, 0x06, BANK0, },
 607         { "in_multicasts",      4, 0x07, BANK0, },
 608         { "in_pause",           4, 0x16, BANK0, },
 609         { "in_undersize",       4, 0x18, BANK0, },
 610         { "in_fragments",       4, 0x19, BANK0, },
 611         { "in_oversize",        4, 0x1a, BANK0, },
 612         { "in_jabber",          4, 0x1b, BANK0, },
 613         { "in_rx_error",        4, 0x1c, BANK0, },
 614         { "in_fcs_error",       4, 0x1d, BANK0, },
 615         { "out_octets",         8, 0x0e, BANK0, },
 616         { "out_unicast",        4, 0x10, BANK0, },
 617         { "out_broadcasts",     4, 0x13, BANK0, },
 618         { "out_multicasts",     4, 0x12, BANK0, },
 619         { "out_pause",          4, 0x15, BANK0, },
 620         { "excessive",          4, 0x11, BANK0, },
 621         { "collisions",         4, 0x1e, BANK0, },
 622         { "deferred",           4, 0x05, BANK0, },
 623         { "single",             4, 0x14, BANK0, },
 624         { "multiple",           4, 0x17, BANK0, },
 625         { "out_fcs_error",      4, 0x03, BANK0, },
 626         { "late",               4, 0x1f, BANK0, },
 627         { "hist_64bytes",       4, 0x08, BANK0, },
 628         { "hist_65_127bytes",   4, 0x09, BANK0, },
 629         { "hist_128_255bytes",  4, 0x0a, BANK0, },
 630         { "hist_256_511bytes",  4, 0x0b, BANK0, },
 631         { "hist_512_1023bytes", 4, 0x0c, BANK0, },
 632         { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
 633         { "sw_in_discards",     4, 0x10, PORT, },
 634         { "sw_in_filtered",     2, 0x12, PORT, },
 635         { "sw_out_filtered",    2, 0x13, PORT, },
 636         { "in_discards",        4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 637         { "in_filtered",        4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 638         { "in_accepted",        4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 639         { "in_bad_accepted",    4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 640         { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 641         { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 642         { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 643         { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 644         { "tcam_counter_0",     4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 645         { "tcam_counter_1",     4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 646         { "tcam_counter_2",     4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
 647         { "tcam_counter_3",     4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
 648         { "in_da_unknown",      4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
 649         { "in_management",      4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
 650         { "out_queue_0",        4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 651         { "out_queue_1",        4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 652         { "out_queue_2",        4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 653         { "out_queue_3",        4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 654         { "out_queue_4",        4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 655         { "out_queue_5",        4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 656         { "out_queue_6",        4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 657         { "out_queue_7",        4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 658         { "out_cut_through",    4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 659         { "out_octets_a",       4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
 660         { "out_octets_b",       4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
 661         { "out_management",     4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
 662 };
 663
 664 static bool mv88e6xxx_has_stat(struct mv88e6xxx_priv_state *ps,
 665                                struct mv88e6xxx_hw_stat *stat)
 666 {
 667         switch (stat->type) {
 668         case BANK0:
 669                 return true;
 670         case BANK1:
 671                 return mv88e6xxx_6320_family(ps);
 672         case PORT:
 673                 return mv88e6xxx_6095_family(ps) ||
 674                         mv88e6xxx_6185_family(ps) ||
 675                         mv88e6xxx_6097_family(ps) ||
 676                         mv88e6xxx_6165_family(ps) ||
 677                         mv88e6xxx_6351_family(ps) ||
 678                         mv88e6xxx_6352_family(ps);
 679         }
 680         return false;
 681 }
 682
 683 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_priv_state *ps,
 684                                             struct mv88e6xxx_hw_stat *s,
 685                                             int port)
 686 {
 687         u32 low;
 688         u32 high = 0;
 689         int ret;
 690         u64 value;
 691
 692         switch (s->type) {
 693         case PORT:
 694                 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), s->reg);
 695                 if (ret < 0)
 696                         return UINT64_MAX;
 697
 698                 low = ret;
 699                 if (s->sizeof_stat == 4) {
 700                         ret = _mv88e6xxx_reg_read(ps, REG_PORT(port),
 701                                                   s->reg + 1);
 702                         if (ret < 0)
 703                                 return UINT64_MAX;
 704                         high = ret;
 705                 }
 706                 break;
 707         case BANK0:
 708         case BANK1:
 709                 _mv88e6xxx_stats_read(ps, s->reg, &low);
 710                 if (s->sizeof_stat == 8)
 711                         _mv88e6xxx_stats_read(ps, s->reg + 1, &high);
 712         }
 713         value = (((u64)high) << 16) | low;
 714         return value;
 715 }
 716
 717 void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
 718 {
 719         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 720         struct mv88e6xxx_hw_stat *stat;
 721         int i, j;
 722
 723         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 724                 stat = &mv88e6xxx_hw_stats[i];
 725                 if (mv88e6xxx_has_stat(ps, stat)) {
 726                         memcpy(data + j * ETH_GSTRING_LEN, stat->string,
 727                                ETH_GSTRING_LEN);
 728                         j++;
 729                 }
 730         }
 731 }
 732
 733 int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
 734 {
 735         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 736         struct mv88e6xxx_hw_stat *stat;
 737         int i, j;
 738
 739         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 740                 stat = &mv88e6xxx_hw_stats[i];
 741                 if (mv88e6xxx_has_stat(ps, stat))
 742                         j++;
 743         }
 744         return j;
 745 }
 746
 747 void
 748 mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
 749                             int port, uint64_t *data)
 750 {
 751         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 752         struct mv88e6xxx_hw_stat *stat;
 753         int ret;
 754         int i, j;
 755
 756         mutex_lock(&ps->smi_mutex);
 757
 758         ret = _mv88e6xxx_stats_snapshot(ps, port);
 759         if (ret < 0) {
 760                 mutex_unlock(&ps->smi_mutex);
 761                 return;
 762         }
 763         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 764                 stat = &mv88e6xxx_hw_stats[i];
 765                 if (mv88e6xxx_has_stat(ps, stat)) {
 766                         data[j] = _mv88e6xxx_get_ethtool_stat(ps, stat, port);
 767                         j++;
 768                 }
 769         }
 770
 771         mutex_unlock(&ps->smi_mutex);
 772 }
 773
 774 int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
 775 {
 776         return 32 * sizeof(u16);
 777 }
 778
 779 void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
 780                         struct ethtool_regs *regs, void *_p)
 781 {
 782         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 783         u16 *p = _p;
 784         int i;
 785
 786         regs->version = 0;
 787
 788         memset(p, 0xff, 32 * sizeof(u16));
 789
 790         mutex_lock(&ps->smi_mutex);
 791
 792         for (i = 0; i < 32; i++) {
 793                 int ret;
 794
 795                 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), i);
 796                 if (ret >= 0)
 797                         p[i] = ret;
 798         }
 799
 800         mutex_unlock(&ps->smi_mutex);
 801 }
 802
 803 static int _mv88e6xxx_wait(struct mv88e6xxx_priv_state *ps, int reg, int offset,
 804                            u16 mask)
 805 {
 806         unsigned long timeout = jiffies + HZ / 10;
 807
 808         while (time_before(jiffies, timeout)) {
 809                 int ret;
 810
 811                 ret = _mv88e6xxx_reg_read(ps, reg, offset);
 812                 if (ret < 0)
 813                         return ret;
 814                 if (!(ret & mask))
 815                         return 0;
 816
 817                 usleep_range(1000, 2000);
 818         }
 819         return -ETIMEDOUT;
 820 }
 821
 822 static int mv88e6xxx_wait(struct mv88e6xxx_priv_state *ps, int reg,
 823                           int offset, u16 mask)
 824 {
 825         int ret;
 826
 827         mutex_lock(&ps->smi_mutex);
 828         ret = _mv88e6xxx_wait(ps, reg, offset, mask);
 829         mutex_unlock(&ps->smi_mutex);
 830
 831         return ret;
 832 }
 833
 834 static int _mv88e6xxx_phy_wait(struct mv88e6xxx_priv_state *ps)
 835 {
 836         return _mv88e6xxx_wait(ps, REG_GLOBAL2, GLOBAL2_SMI_OP,
 837                                GLOBAL2_SMI_OP_BUSY);
 838 }
 839
 840 static int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
 841 {
 842         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 843
 844         return mv88e6xxx_wait(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
 845                               GLOBAL2_EEPROM_OP_LOAD);
 846 }
 847
 848 static int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
 849 {
 850         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 851
 852         return mv88e6xxx_wait(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
 853                               GLOBAL2_EEPROM_OP_BUSY);
 854 }
 855
 856 static int mv88e6xxx_read_eeprom_word(struct dsa_switch *ds, int addr)
 857 {
 858         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 859         int ret;
 860
 861         mutex_lock(&ps->eeprom_mutex);
 862
 863         ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
 864                                   GLOBAL2_EEPROM_OP_READ |
 865                                   (addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
 866         if (ret < 0)
 867                 goto error;
 868
 869         ret = mv88e6xxx_eeprom_busy_wait(ds);
 870         if (ret < 0)
 871                 goto error;
 872
 873         ret = mv88e6xxx_reg_read(ps, REG_GLOBAL2, GLOBAL2_EEPROM_DATA);
 874 error:
 875         mutex_unlock(&ps->eeprom_mutex);
 876         return ret;
 877 }
 878
 879 int mv88e6xxx_get_eeprom(struct dsa_switch *ds, struct ethtool_eeprom *eeprom,
 880                          u8 *data)
 881 {
 882         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 883         int offset;
 884         int len;
 885         int ret;
 886
 887         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM))
 888                 return -EOPNOTSUPP;
 889
 890         offset = eeprom->offset;
 891         len = eeprom->len;
 892         eeprom->len = 0;
 893
 894         eeprom->magic = 0xc3ec4951;
 895
 896         ret = mv88e6xxx_eeprom_load_wait(ds);
 897         if (ret < 0)
 898                 return ret;
 899
 900         if (offset & 1) {
 901                 int word;
 902
 903                 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
 904                 if (word < 0)
 905                         return word;
 906
 907                 *data++ = (word >> 8) & 0xff;
 908
 909                 offset++;
 910                 len--;
 911                 eeprom->len++;
 912         }
 913
 914         while (len >= 2) {
 915                 int word;
 916
 917                 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
 918                 if (word < 0)
 919                         return word;
 920
 921                 *data++ = word & 0xff;
 922                 *data++ = (word >> 8) & 0xff;
 923
 924                 offset += 2;
 925                 len -= 2;
 926                 eeprom->len += 2;
 927         }
 928
 929         if (len) {
 930                 int word;
 931
 932                 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
 933                 if (word < 0)
 934                         return word;
 935
 936                 *data++ = word & 0xff;
 937
 938                 offset++;
 939                 len--;
 940                 eeprom->len++;
 941         }
 942
 943         return 0;
 944 }
 945
 946 static int mv88e6xxx_eeprom_is_readonly(struct dsa_switch *ds)
 947 {
 948         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 949         int ret;
 950
 951         ret = mv88e6xxx_reg_read(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP);
 952         if (ret < 0)
 953                 return ret;
 954
 955         if (!(ret & GLOBAL2_EEPROM_OP_WRITE_EN))
 956                 return -EROFS;
 957
 958         return 0;
 959 }
 960
 961 static int mv88e6xxx_write_eeprom_word(struct dsa_switch *ds, int addr,
 962                                        u16 data)
 963 {
 964         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 965         int ret;
 966
 967         mutex_lock(&ps->eeprom_mutex);
 968
 969         ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
 970         if (ret < 0)
 971                 goto error;
 972
 973         ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
 974                                   GLOBAL2_EEPROM_OP_WRITE |
 975                                   (addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
 976         if (ret < 0)
 977                 goto error;
 978
 979         ret = mv88e6xxx_eeprom_busy_wait(ds);
 980 error:
 981         mutex_unlock(&ps->eeprom_mutex);
 982         return ret;
 983 }
 984
 985 int mv88e6xxx_set_eeprom(struct dsa_switch *ds, struct ethtool_eeprom *eeprom,
 986                          u8 *data)
 987 {
 988         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 989         int offset;
 990         int ret;
 991         int len;
 992
 993         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM))
 994                 return -EOPNOTSUPP;
 995
 996         if (eeprom->magic != 0xc3ec4951)
 997                 return -EINVAL;
 998
 999         ret = mv88e6xxx_eeprom_is_readonly(ds);
1000         if (ret)
1001                 return ret;
1002
1003         offset = eeprom->offset;
1004         len = eeprom->len;
1005         eeprom->len = 0;
1006
1007         ret = mv88e6xxx_eeprom_load_wait(ds);
1008         if (ret < 0)
1009                 return ret;
1010
1011         if (offset & 1) {
1012                 int word;
1013
1014                 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
1015                 if (word < 0)
1016                         return word;
1017
1018                 word = (*data++ << 8) | (word & 0xff);
1019
1020                 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1021                 if (ret < 0)
1022                         return ret;
1023
1024                 offset++;
1025                 len--;
1026                 eeprom->len++;
1027         }
1028
1029         while (len >= 2) {
1030                 int word;
1031
1032                 word = *data++;
1033                 word |= *data++ << 8;
1034
1035                 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1036                 if (ret < 0)
1037                         return ret;
1038
1039                 offset += 2;
1040                 len -= 2;
1041                 eeprom->len += 2;
1042         }
1043
1044         if (len) {
1045                 int word;
1046
1047                 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
1048                 if (word < 0)
1049                         return word;
1050
1051                 word = (word & 0xff00) | *data++;
1052
1053                 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1054                 if (ret < 0)
1055                         return ret;
1056
1057                 offset++;
1058                 len--;
1059                 eeprom->len++;
1060         }
1061
1062         return 0;
1063 }
1064
1065 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_priv_state *ps)
1066 {
1067         return _mv88e6xxx_wait(ps, REG_GLOBAL, GLOBAL_ATU_OP,
1068                                GLOBAL_ATU_OP_BUSY);
1069 }
1070
1071 static int _mv88e6xxx_phy_read_indirect(struct mv88e6xxx_priv_state *ps,
1072                                         int addr, int regnum)
1073 {
1074         int ret;
1075
1076         ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SMI_OP,
1077                                    GLOBAL2_SMI_OP_22_READ | (addr << 5) |
1078                                    regnum);
1079         if (ret < 0)
1080                 return ret;
1081
1082         ret = _mv88e6xxx_phy_wait(ps);
1083         if (ret < 0)
1084                 return ret;
1085
1086         ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL2, GLOBAL2_SMI_DATA);
1087
1088         return ret;
1089 }
1090
1091 static int _mv88e6xxx_phy_write_indirect(struct mv88e6xxx_priv_state *ps,
1092                                          int addr, int regnum, u16 val)
1093 {
1094         int ret;
1095
1096         ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
1097         if (ret < 0)
1098                 return ret;
1099
1100         ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SMI_OP,
1101                                    GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
1102                                    regnum);
1103
1104         return _mv88e6xxx_phy_wait(ps);
1105 }
1106
1107 int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1108 {
1109         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1110         int reg;
1111
1112         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEE))
1113                 return -EOPNOTSUPP;
1114
1115         mutex_lock(&ps->smi_mutex);
1116
1117         reg = _mv88e6xxx_phy_read_indirect(ps, port, 16);
1118         if (reg < 0)
1119                 goto out;
1120
1121         e->eee_enabled = !!(reg & 0x0200);
1122         e->tx_lpi_enabled = !!(reg & 0x0100);
1123
1124         reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_STATUS);
1125         if (reg < 0)
1126                 goto out;
1127
1128         e->eee_active = !!(reg & PORT_STATUS_EEE);
1129         reg = 0;
1130
1131 out:
1132         mutex_unlock(&ps->smi_mutex);
1133         return reg;
1134 }
1135
1136 int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1137                       struct phy_device *phydev, struct ethtool_eee *e)
1138 {
1139         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1140         int reg;
1141         int ret;
1142
1143         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEE))
1144                 return -EOPNOTSUPP;
1145
1146         mutex_lock(&ps->smi_mutex);
1147
1148         ret = _mv88e6xxx_phy_read_indirect(ps, port, 16);
1149         if (ret < 0)
1150                 goto out;
1151
1152         reg = ret & ~0x0300;
1153         if (e->eee_enabled)
1154                 reg |= 0x0200;
1155         if (e->tx_lpi_enabled)
1156                 reg |= 0x0100;
1157
1158         ret = _mv88e6xxx_phy_write_indirect(ps, port, 16, reg);
1159 out:
1160         mutex_unlock(&ps->smi_mutex);
1161
1162         return ret;
1163 }
1164
1165 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_priv_state *ps, u16 fid, u16 cmd)
1166 {
1167         int ret;
1168
1169         if (mv88e6xxx_has_fid_reg(ps)) {
1170                 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_FID, fid);
1171                 if (ret < 0)
1172                         return ret;
1173         } else if (mv88e6xxx_num_databases(ps) == 256) {
1174                 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
1175                 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_ATU_CONTROL);
1176                 if (ret < 0)
1177                         return ret;
1178
1179                 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_CONTROL,
1180                                            (ret & 0xfff) |
1181                                            ((fid << 8) & 0xf000));
1182                 if (ret < 0)
1183                         return ret;
1184
1185                 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1186                 cmd |= fid & 0xf;
1187         }
1188
1189         ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
1190         if (ret < 0)
1191                 return ret;
1192
1193         return _mv88e6xxx_atu_wait(ps);
1194 }
1195
1196 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_priv_state *ps,
1197                                      struct mv88e6xxx_atu_entry *entry)
1198 {
1199         u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1200
1201         if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1202                 unsigned int mask, shift;
1203
1204                 if (entry->trunk) {
1205                         data |= GLOBAL_ATU_DATA_TRUNK;
1206                         mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1207                         shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1208                 } else {
1209                         mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1210                         shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1211                 }
1212
1213                 data |= (entry->portv_trunkid << shift) & mask;
1214         }
1215
1216         return _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_DATA, data);
1217 }
1218
1219 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_priv_state *ps,
1220                                      struct mv88e6xxx_atu_entry *entry,
1221                                      bool static_too)
1222 {
1223         int op;
1224         int err;
1225
1226         err = _mv88e6xxx_atu_wait(ps);
1227         if (err)
1228                 return err;
1229
1230         err = _mv88e6xxx_atu_data_write(ps, entry);
1231         if (err)
1232                 return err;
1233
1234         if (entry->fid) {
1235                 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1236                         GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1237         } else {
1238                 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1239                         GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1240         }
1241
1242         return _mv88e6xxx_atu_cmd(ps, entry->fid, op);
1243 }
1244
1245 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_priv_state *ps,
1246                                 u16 fid, bool static_too)
1247 {
1248         struct mv88e6xxx_atu_entry entry = {
1249                 .fid = fid,
1250                 .state = 0, /* EntryState bits must be 0 */
1251         };
1252
1253         return _mv88e6xxx_atu_flush_move(ps, &entry, static_too);
1254 }
1255
1256 static int _mv88e6xxx_atu_move(struct mv88e6xxx_priv_state *ps, u16 fid,
1257                                int from_port, int to_port, bool static_too)
1258 {
1259         struct mv88e6xxx_atu_entry entry = {
1260                 .trunk = false,
1261                 .fid = fid,
1262         };
1263
1264         /* EntryState bits must be 0xF */
1265         entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1266
1267         /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1268         entry.portv_trunkid = (to_port & 0x0f) << 4;
1269         entry.portv_trunkid |= from_port & 0x0f;
1270
1271         return _mv88e6xxx_atu_flush_move(ps, &entry, static_too);
1272 }
1273
1274 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_priv_state *ps, u16 fid,
1275                                  int port, bool static_too)
1276 {
1277         /* Destination port 0xF means remove the entries */
1278         return _mv88e6xxx_atu_move(ps, fid, port, 0x0f, static_too);
1279 }
1280
1281 static const char * const mv88e6xxx_port_state_names[] = {
1282         [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1283         [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1284         [PORT_CONTROL_STATE_LEARNING] = "Learning",
1285         [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1286 };
1287
1288 static int _mv88e6xxx_port_state(struct mv88e6xxx_priv_state *ps, int port,
1289                                  u8 state)
1290 {
1291         struct dsa_switch *ds = ps->ds;
1292         int reg, ret = 0;
1293         u8 oldstate;
1294
1295         reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_CONTROL);
1296         if (reg < 0)
1297                 return reg;
1298
1299         oldstate = reg & PORT_CONTROL_STATE_MASK;
1300
1301         if (oldstate != state) {
1302                 /* Flush forwarding database if we're moving a port
1303                  * from Learning or Forwarding state to Disabled or
1304                  * Blocking or Listening state.
1305                  */
1306                 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
1307                      oldstate == PORT_CONTROL_STATE_FORWARDING)
1308                     && (state == PORT_CONTROL_STATE_DISABLED ||
1309                         state == PORT_CONTROL_STATE_BLOCKING)) {
1310                         ret = _mv88e6xxx_atu_remove(ps, 0, port, false);
1311                         if (ret)
1312                                 return ret;
1313                 }
1314
1315                 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1316                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL,
1317                                            reg);
1318                 if (ret)
1319                         return ret;
1320
1321                 netdev_dbg(ds->ports[port], "PortState %s (was %s)\n",
1322                            mv88e6xxx_port_state_names[state],
1323                            mv88e6xxx_port_state_names[oldstate]);
1324         }
1325
1326         return ret;
1327 }
1328
1329 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_priv_state *ps,
1330                                           int port)
1331 {
1332         struct net_device *bridge = ps->ports[port].bridge_dev;
1333         const u16 mask = (1 << ps->info->num_ports) - 1;
1334         struct dsa_switch *ds = ps->ds;
1335         u16 output_ports = 0;
1336         int reg;
1337         int i;
1338
1339         /* allow CPU port or DSA link(s) to send frames to every port */
1340         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1341                 output_ports = mask;
1342         } else {
1343                 for (i = 0; i < ps->info->num_ports; ++i) {
1344                         /* allow sending frames to every group member */
1345                         if (bridge && ps->ports[i].bridge_dev == bridge)
1346                                 output_ports |= BIT(i);
1347
1348                         /* allow sending frames to CPU port and DSA link(s) */
1349                         if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1350                                 output_ports |= BIT(i);
1351                 }
1352         }
1353
1354         /* prevent frames from going back out of the port they came in on */
1355         output_ports &= ~BIT(port);
1356
1357         reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_BASE_VLAN);
1358         if (reg < 0)
1359                 return reg;
1360
1361         reg &= ~mask;
1362         reg |= output_ports & mask;
1363
1364         return _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_BASE_VLAN, reg);
1365 }
1366
1367 void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1368 {
1369         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1370         int stp_state;
1371
1372         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_PORTSTATE))
1373                 return;
1374
1375         switch (state) {
1376         case BR_STATE_DISABLED:
1377                 stp_state = PORT_CONTROL_STATE_DISABLED;
1378                 break;
1379         case BR_STATE_BLOCKING:
1380         case BR_STATE_LISTENING:
1381                 stp_state = PORT_CONTROL_STATE_BLOCKING;
1382                 break;
1383         case BR_STATE_LEARNING:
1384                 stp_state = PORT_CONTROL_STATE_LEARNING;
1385                 break;
1386         case BR_STATE_FORWARDING:
1387         default:
1388                 stp_state = PORT_CONTROL_STATE_FORWARDING;
1389                 break;
1390         }
1391
1392         /* mv88e6xxx_port_stp_state_set may be called with softirqs disabled,
1393          * so we can not update the port state directly but need to schedule it.
1394          */
1395         ps->ports[port].state = stp_state;
1396         set_bit(port, ps->port_state_update_mask);
1397         schedule_work(&ps->bridge_work);
1398 }
1399
1400 static int _mv88e6xxx_port_pvid(struct mv88e6xxx_priv_state *ps, int port,
1401                                 u16 *new, u16 *old)
1402 {
1403         struct dsa_switch *ds = ps->ds;
1404         u16 pvid;
1405         int ret;
1406
1407         ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_DEFAULT_VLAN);
1408         if (ret < 0)
1409                 return ret;
1410
1411         pvid = ret & PORT_DEFAULT_VLAN_MASK;
1412
1413         if (new) {
1414                 ret &= ~PORT_DEFAULT_VLAN_MASK;
1415                 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1416
1417                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
1418                                            PORT_DEFAULT_VLAN, ret);
1419                 if (ret < 0)
1420                         return ret;
1421
1422                 netdev_dbg(ds->ports[port], "DefaultVID %d (was %d)\n", *new,
1423                            pvid);
1424         }
1425
1426         if (old)
1427                 *old = pvid;
1428
1429         return 0;
1430 }
1431
1432 static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_priv_state *ps,
1433                                     int port, u16 *pvid)
1434 {
1435         return _mv88e6xxx_port_pvid(ps, port, NULL, pvid);
1436 }
1437
1438 static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_priv_state *ps,
1439                                     int port, u16 pvid)
1440 {
1441         return _mv88e6xxx_port_pvid(ps, port, &pvid, NULL);
1442 }
1443
1444 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_priv_state *ps)
1445 {
1446         return _mv88e6xxx_wait(ps, REG_GLOBAL, GLOBAL_VTU_OP,
1447                                GLOBAL_VTU_OP_BUSY);
1448 }
1449
1450 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_priv_state *ps, u16 op)
1451 {
1452         int ret;
1453
1454         ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_OP, op);
1455         if (ret < 0)
1456                 return ret;
1457
1458         return _mv88e6xxx_vtu_wait(ps);
1459 }
1460
1461 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_priv_state *ps)
1462 {
1463         int ret;
1464
1465         ret = _mv88e6xxx_vtu_wait(ps);
1466         if (ret < 0)
1467                 return ret;
1468
1469         return _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_FLUSH_ALL);
1470 }
1471
1472 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_priv_state *ps,
1473                                         struct mv88e6xxx_vtu_stu_entry *entry,
1474                                         unsigned int nibble_offset)
1475 {
1476         u16 regs[3];
1477         int i;
1478         int ret;
1479
1480         for (i = 0; i < 3; ++i) {
1481                 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
1482                                           GLOBAL_VTU_DATA_0_3 + i);
1483                 if (ret < 0)
1484                         return ret;
1485
1486                 regs[i] = ret;
1487         }
1488
1489         for (i = 0; i < ps->info->num_ports; ++i) {
1490                 unsigned int shift = (i % 4) * 4 + nibble_offset;
1491                 u16 reg = regs[i / 4];
1492
1493                 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1494         }
1495
1496         return 0;
1497 }
1498
1499 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_priv_state *ps,
1500                                          struct mv88e6xxx_vtu_stu_entry *entry,
1501                                          unsigned int nibble_offset)
1502 {
1503         u16 regs[3] = { 0 };
1504         int i;
1505         int ret;
1506
1507         for (i = 0; i < ps->info->num_ports; ++i) {
1508                 unsigned int shift = (i % 4) * 4 + nibble_offset;
1509                 u8 data = entry->data[i];
1510
1511                 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1512         }
1513
1514         for (i = 0; i < 3; ++i) {
1515                 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL,
1516                                            GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1517                 if (ret < 0)
1518                         return ret;
1519         }
1520
1521         return 0;
1522 }
1523
1524 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_priv_state *ps, u16 vid)
1525 {
1526         return _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_VID,
1527                                     vid & GLOBAL_VTU_VID_MASK);
1528 }
1529
1530 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_priv_state *ps,
1531                                   struct mv88e6xxx_vtu_stu_entry *entry)
1532 {
1533         struct mv88e6xxx_vtu_stu_entry next = { 0 };
1534         int ret;
1535
1536         ret = _mv88e6xxx_vtu_wait(ps);
1537         if (ret < 0)
1538                 return ret;
1539
1540         ret = _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_VTU_GET_NEXT);
1541         if (ret < 0)
1542                 return ret;
1543
1544         ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_VTU_VID);
1545         if (ret < 0)
1546                 return ret;
1547
1548         next.vid = ret & GLOBAL_VTU_VID_MASK;
1549         next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1550
1551         if (next.valid) {
1552                 ret = _mv88e6xxx_vtu_stu_data_read(ps, &next, 0);
1553                 if (ret < 0)
1554                         return ret;
1555
1556                 if (mv88e6xxx_has_fid_reg(ps)) {
1557                         ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
1558                                                   GLOBAL_VTU_FID);
1559                         if (ret < 0)
1560                                 return ret;
1561
1562                         next.fid = ret & GLOBAL_VTU_FID_MASK;
1563                 } else if (mv88e6xxx_num_databases(ps) == 256) {
1564                         /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1565                          * VTU DBNum[3:0] are located in VTU Operation 3:0
1566                          */
1567                         ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
1568                                                   GLOBAL_VTU_OP);
1569                         if (ret < 0)
1570                                 return ret;
1571
1572                         next.fid = (ret & 0xf00) >> 4;
1573                         next.fid |= ret & 0xf;
1574                 }
1575
1576                 if (mv88e6xxx_has_stu(ps)) {
1577                         ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
1578                                                   GLOBAL_VTU_SID);
1579                         if (ret < 0)
1580                                 return ret;
1581
1582                         next.sid = ret & GLOBAL_VTU_SID_MASK;
1583                 }
1584         }
1585
1586         *entry = next;
1587         return 0;
1588 }
1589
1590 int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1591                              struct switchdev_obj_port_vlan *vlan,
1592                              int (*cb)(struct switchdev_obj *obj))
1593 {
1594         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1595         struct mv88e6xxx_vtu_stu_entry next;
1596         u16 pvid;
1597         int err;
1598
1599         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU))
1600                 return -EOPNOTSUPP;
1601
1602         mutex_lock(&ps->smi_mutex);
1603
1604         err = _mv88e6xxx_port_pvid_get(ps, port, &pvid);
1605         if (err)
1606                 goto unlock;
1607
1608         err = _mv88e6xxx_vtu_vid_write(ps, GLOBAL_VTU_VID_MASK);
1609         if (err)
1610                 goto unlock;
1611
1612         do {
1613                 err = _mv88e6xxx_vtu_getnext(ps, &next);
1614                 if (err)
1615                         break;
1616
1617                 if (!next.valid)
1618                         break;
1619
1620                 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1621                         continue;
1622
1623                 /* reinit and dump this VLAN obj */
1624                 vlan->vid_begin = vlan->vid_end = next.vid;
1625                 vlan->flags = 0;
1626
1627                 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1628                         vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1629
1630                 if (next.vid == pvid)
1631                         vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1632
1633                 err = cb(&vlan->obj);
1634                 if (err)
1635                         break;
1636         } while (next.vid < GLOBAL_VTU_VID_MASK);
1637
1638 unlock:
1639         mutex_unlock(&ps->smi_mutex);
1640
1641         return err;
1642 }
1643
1644 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_priv_state *ps,
1645                                     struct mv88e6xxx_vtu_stu_entry *entry)
1646 {
1647         u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
1648         u16 reg = 0;
1649         int ret;
1650
1651         ret = _mv88e6xxx_vtu_wait(ps);
1652         if (ret < 0)
1653                 return ret;
1654
1655         if (!entry->valid)
1656                 goto loadpurge;
1657
1658         /* Write port member tags */
1659         ret = _mv88e6xxx_vtu_stu_data_write(ps, entry, 0);
1660         if (ret < 0)
1661                 return ret;
1662
1663         if (mv88e6xxx_has_stu(ps)) {
1664                 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1665                 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1666                 if (ret < 0)
1667                         return ret;
1668         }
1669
1670         if (mv88e6xxx_has_fid_reg(ps)) {
1671                 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1672                 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_FID, reg);
1673                 if (ret < 0)
1674                         return ret;
1675         } else if (mv88e6xxx_num_databases(ps) == 256) {
1676                 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1677                  * VTU DBNum[3:0] are located in VTU Operation 3:0
1678                  */
1679                 op |= (entry->fid & 0xf0) << 8;
1680                 op |= entry->fid & 0xf;
1681         }
1682
1683         reg = GLOBAL_VTU_VID_VALID;
1684 loadpurge:
1685         reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1686         ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1687         if (ret < 0)
1688                 return ret;
1689
1690         return _mv88e6xxx_vtu_cmd(ps, op);
1691 }
1692
1693 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_priv_state *ps, u8 sid,
1694                                   struct mv88e6xxx_vtu_stu_entry *entry)
1695 {
1696         struct mv88e6xxx_vtu_stu_entry next = { 0 };
1697         int ret;
1698
1699         ret = _mv88e6xxx_vtu_wait(ps);
1700         if (ret < 0)
1701                 return ret;
1702
1703         ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_SID,
1704                                    sid & GLOBAL_VTU_SID_MASK);
1705         if (ret < 0)
1706                 return ret;
1707
1708         ret = _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_STU_GET_NEXT);
1709         if (ret < 0)
1710                 return ret;
1711
1712         ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_VTU_SID);
1713         if (ret < 0)
1714                 return ret;
1715
1716         next.sid = ret & GLOBAL_VTU_SID_MASK;
1717
1718         ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_VTU_VID);
1719         if (ret < 0)
1720                 return ret;
1721
1722         next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1723
1724         if (next.valid) {
1725                 ret = _mv88e6xxx_vtu_stu_data_read(ps, &next, 2);
1726                 if (ret < 0)
1727                         return ret;
1728         }
1729
1730         *entry = next;
1731         return 0;
1732 }
1733
1734 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_priv_state *ps,
1735                                     struct mv88e6xxx_vtu_stu_entry *entry)
1736 {
1737         u16 reg = 0;
1738         int ret;
1739
1740         ret = _mv88e6xxx_vtu_wait(ps);
1741         if (ret < 0)
1742                 return ret;
1743
1744         if (!entry->valid)
1745                 goto loadpurge;
1746
1747         /* Write port states */
1748         ret = _mv88e6xxx_vtu_stu_data_write(ps, entry, 2);
1749         if (ret < 0)
1750                 return ret;
1751
1752         reg = GLOBAL_VTU_VID_VALID;
1753 loadpurge:
1754         ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1755         if (ret < 0)
1756                 return ret;
1757
1758         reg = entry->sid & GLOBAL_VTU_SID_MASK;
1759         ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1760         if (ret < 0)
1761                 return ret;
1762
1763         return _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1764 }
1765
1766 static int _mv88e6xxx_port_fid(struct mv88e6xxx_priv_state *ps, int port,
1767                                u16 *new, u16 *old)
1768 {
1769         struct dsa_switch *ds = ps->ds;
1770         u16 upper_mask;
1771         u16 fid;
1772         int ret;
1773
1774         if (mv88e6xxx_num_databases(ps) == 4096)
1775                 upper_mask = 0xff;
1776         else if (mv88e6xxx_num_databases(ps) == 256)
1777                 upper_mask = 0xf;
1778         else
1779                 return -EOPNOTSUPP;
1780
1781         /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1782         ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_BASE_VLAN);
1783         if (ret < 0)
1784                 return ret;
1785
1786         fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1787
1788         if (new) {
1789                 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1790                 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1791
1792                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_BASE_VLAN,
1793                                            ret);
1794                 if (ret < 0)
1795                         return ret;
1796         }
1797
1798         /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1799         ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_CONTROL_1);
1800         if (ret < 0)
1801                 return ret;
1802
1803         fid |= (ret & upper_mask) << 4;
1804
1805         if (new) {
1806                 ret &= ~upper_mask;
1807                 ret |= (*new >> 4) & upper_mask;
1808
1809                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL_1,
1810                                            ret);
1811                 if (ret < 0)
1812                         return ret;
1813
1814                 netdev_dbg(ds->ports[port], "FID %d (was %d)\n", *new, fid);
1815         }
1816
1817         if (old)
1818                 *old = fid;
1819
1820         return 0;
1821 }
1822
1823 static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_priv_state *ps,
1824                                    int port, u16 *fid)
1825 {
1826         return _mv88e6xxx_port_fid(ps, port, NULL, fid);
1827 }
1828
1829 static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_priv_state *ps,
1830                                    int port, u16 fid)
1831 {
1832         return _mv88e6xxx_port_fid(ps, port, &fid, NULL);
1833 }
1834
1835 static int _mv88e6xxx_fid_new(struct mv88e6xxx_priv_state *ps, u16 *fid)
1836 {
1837         DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1838         struct mv88e6xxx_vtu_stu_entry vlan;
1839         int i, err;
1840
1841         bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1842
1843         /* Set every FID bit used by the (un)bridged ports */
1844         for (i = 0; i < ps->info->num_ports; ++i) {
1845                 err = _mv88e6xxx_port_fid_get(ps, i, fid);
1846                 if (err)
1847                         return err;
1848
1849                 set_bit(*fid, fid_bitmap);
1850         }
1851
1852         /* Set every FID bit used by the VLAN entries */
1853         err = _mv88e6xxx_vtu_vid_write(ps, GLOBAL_VTU_VID_MASK);
1854         if (err)
1855                 return err;
1856
1857         do {
1858                 err = _mv88e6xxx_vtu_getnext(ps, &vlan);
1859                 if (err)
1860                         return err;
1861
1862                 if (!vlan.valid)
1863                         break;
1864
1865                 set_bit(vlan.fid, fid_bitmap);
1866         } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1867
1868         /* The reset value 0x000 is used to indicate that multiple address
1869          * databases are not needed. Return the next positive available.
1870          */
1871         *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1872         if (unlikely(*fid >= mv88e6xxx_num_databases(ps)))
1873                 return -ENOSPC;
1874
1875         /* Clear the database */
1876         return _mv88e6xxx_atu_flush(ps, *fid, true);
1877 }
1878
1879 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_priv_state *ps, u16 vid,
1880                               struct mv88e6xxx_vtu_stu_entry *entry)
1881 {
1882         struct dsa_switch *ds = ps->ds;
1883         struct mv88e6xxx_vtu_stu_entry vlan = {
1884                 .valid = true,
1885                 .vid = vid,
1886         };
1887         int i, err;
1888
1889         err = _mv88e6xxx_fid_new(ps, &vlan.fid);
1890         if (err)
1891                 return err;
1892
1893         /* exclude all ports except the CPU and DSA ports */
1894         for (i = 0; i < ps->info->num_ports; ++i)
1895                 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1896                         ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1897                         : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1898
1899         if (mv88e6xxx_6097_family(ps) || mv88e6xxx_6165_family(ps) ||
1900             mv88e6xxx_6351_family(ps) || mv88e6xxx_6352_family(ps)) {
1901                 struct mv88e6xxx_vtu_stu_entry vstp;
1902
1903                 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1904                  * implemented, only one STU entry is needed to cover all VTU
1905                  * entries. Thus, validate the SID 0.
1906                  */
1907                 vlan.sid = 0;
1908                 err = _mv88e6xxx_stu_getnext(ps, GLOBAL_VTU_SID_MASK, &vstp);
1909                 if (err)
1910                         return err;
1911
1912                 if (vstp.sid != vlan.sid || !vstp.valid) {
1913                         memset(&vstp, 0, sizeof(vstp));
1914                         vstp.valid = true;
1915                         vstp.sid = vlan.sid;
1916
1917                         err = _mv88e6xxx_stu_loadpurge(ps, &vstp);
1918                         if (err)
1919                                 return err;
1920                 }
1921         }
1922
1923         *entry = vlan;
1924         return 0;
1925 }
1926
1927 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_priv_state *ps, u16 vid,
1928                               struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1929 {
1930         int err;
1931
1932         if (!vid)
1933                 return -EINVAL;
1934
1935         err = _mv88e6xxx_vtu_vid_write(ps, vid - 1);
1936         if (err)
1937                 return err;
1938
1939         err = _mv88e6xxx_vtu_getnext(ps, entry);
1940         if (err)
1941                 return err;
1942
1943         if (entry->vid != vid || !entry->valid) {
1944                 if (!creat)
1945                         return -EOPNOTSUPP;
1946                 /* -ENOENT would've been more appropriate, but switchdev expects
1947                  * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1948                  */
1949
1950                 err = _mv88e6xxx_vtu_new(ps, vid, entry);
1951         }
1952
1953         return err;
1954 }
1955
1956 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1957                                         u16 vid_begin, u16 vid_end)
1958 {
1959         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1960         struct mv88e6xxx_vtu_stu_entry vlan;
1961         int i, err;
1962
1963         if (!vid_begin)
1964                 return -EOPNOTSUPP;
1965
1966         mutex_lock(&ps->smi_mutex);
1967
1968         err = _mv88e6xxx_vtu_vid_write(ps, vid_begin - 1);
1969         if (err)
1970                 goto unlock;
1971
1972         do {
1973                 err = _mv88e6xxx_vtu_getnext(ps, &vlan);
1974                 if (err)
1975                         goto unlock;
1976
1977                 if (!vlan.valid)
1978                         break;
1979
1980                 if (vlan.vid > vid_end)
1981                         break;
1982
1983                 for (i = 0; i < ps->info->num_ports; ++i) {
1984                         if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1985                                 continue;
1986
1987                         if (vlan.data[i] ==
1988                             GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1989                                 continue;
1990
1991                         if (ps->ports[i].bridge_dev ==
1992                             ps->ports[port].bridge_dev)
1993                                 break; /* same bridge, check next VLAN */
1994
1995                         netdev_warn(ds->ports[port],
1996                                     "hardware VLAN %d already used by %s\n",
1997                                     vlan.vid,
1998                                     netdev_name(ps->ports[i].bridge_dev));
1999                         err = -EOPNOTSUPP;
2000                         goto unlock;
2001                 }
2002         } while (vlan.vid < vid_end);
2003
2004 unlock:
2005         mutex_unlock(&ps->smi_mutex);
2006
2007         return err;
2008 }
2009
2010 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
2011         [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
2012         [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
2013         [PORT_CONTROL_2_8021Q_CHECK] = "Check",
2014         [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
2015 };
2016
2017 int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
2018                                   bool vlan_filtering)
2019 {
2020         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2021         u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
2022                 PORT_CONTROL_2_8021Q_DISABLED;
2023         int ret;
2024
2025         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU))
2026                 return -EOPNOTSUPP;
2027
2028         mutex_lock(&ps->smi_mutex);
2029
2030         ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_CONTROL_2);
2031         if (ret < 0)
2032                 goto unlock;
2033
2034         old = ret & PORT_CONTROL_2_8021Q_MASK;
2035
2036         if (new != old) {
2037                 ret &= ~PORT_CONTROL_2_8021Q_MASK;
2038                 ret |= new & PORT_CONTROL_2_8021Q_MASK;
2039
2040                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL_2,
2041                                            ret);
2042                 if (ret < 0)
2043                         goto unlock;
2044
2045                 netdev_dbg(ds->ports[port], "802.1Q Mode %s (was %s)\n",
2046                            mv88e6xxx_port_8021q_mode_names[new],
2047                            mv88e6xxx_port_8021q_mode_names[old]);
2048         }
2049
2050         ret = 0;
2051 unlock:
2052         mutex_unlock(&ps->smi_mutex);
2053
2054         return ret;
2055 }
2056
2057 int mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
2058                                 const struct switchdev_obj_port_vlan *vlan,
2059                                 struct switchdev_trans *trans)
2060 {
2061         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2062         int err;
2063
2064         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU))
2065                 return -EOPNOTSUPP;
2066
2067         /* If the requested port doesn't belong to the same bridge as the VLAN
2068          * members, do not support it (yet) and fallback to software VLAN.
2069          */
2070         err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
2071                                            vlan->vid_end);
2072         if (err)
2073                 return err;
2074
2075         /* We don't need any dynamic resource from the kernel (yet),
2076          * so skip the prepare phase.
2077          */
2078         return 0;
2079 }
2080
2081 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_priv_state *ps, int port,
2082                                     u16 vid, bool untagged)
2083 {
2084         struct mv88e6xxx_vtu_stu_entry vlan;
2085         int err;
2086
2087         err = _mv88e6xxx_vtu_get(ps, vid, &vlan, true);
2088         if (err)
2089                 return err;
2090
2091         vlan.data[port] = untagged ?
2092                 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
2093                 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
2094
2095         return _mv88e6xxx_vtu_loadpurge(ps, &vlan);
2096 }
2097
2098 void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2099                              const struct switchdev_obj_port_vlan *vlan,
2100                              struct switchdev_trans *trans)
2101 {
2102         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2103         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2104         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2105         u16 vid;
2106
2107         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU))
2108                 return;
2109
2110         mutex_lock(&ps->smi_mutex);
2111
2112         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
2113                 if (_mv88e6xxx_port_vlan_add(ps, port, vid, untagged))
2114                         netdev_err(ds->ports[port], "failed to add VLAN %d%c\n",
2115                                    vid, untagged ? 'u' : 't');
2116
2117         if (pvid && _mv88e6xxx_port_pvid_set(ps, port, vlan->vid_end))
2118                 netdev_err(ds->ports[port], "failed to set PVID %d\n",
2119                            vlan->vid_end);
2120
2121         mutex_unlock(&ps->smi_mutex);
2122 }
2123
2124 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_priv_state *ps,
2125                                     int port, u16 vid)
2126 {
2127         struct dsa_switch *ds = ps->ds;
2128         struct mv88e6xxx_vtu_stu_entry vlan;
2129         int i, err;
2130
2131         err = _mv88e6xxx_vtu_get(ps, vid, &vlan, false);
2132         if (err)
2133                 return err;
2134
2135         /* Tell switchdev if this VLAN is handled in software */
2136         if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2137                 return -EOPNOTSUPP;
2138
2139         vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2140
2141         /* keep the VLAN unless all ports are excluded */
2142         vlan.valid = false;
2143         for (i = 0; i < ps->info->num_ports; ++i) {
2144                 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
2145                         continue;
2146
2147                 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2148                         vlan.valid = true;
2149                         break;
2150                 }
2151         }
2152
2153         err = _mv88e6xxx_vtu_loadpurge(ps, &vlan);
2154         if (err)
2155                 return err;
2156
2157         return _mv88e6xxx_atu_remove(ps, vlan.fid, port, false);
2158 }
2159
2160 int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2161                             const struct switchdev_obj_port_vlan *vlan)
2162 {
2163         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2164         u16 pvid, vid;
2165         int err = 0;
2166
2167         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU))
2168                 return -EOPNOTSUPP;
2169
2170         mutex_lock(&ps->smi_mutex);
2171
2172         err = _mv88e6xxx_port_pvid_get(ps, port, &pvid);
2173         if (err)
2174                 goto unlock;
2175
2176         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
2177                 err = _mv88e6xxx_port_vlan_del(ps, port, vid);
2178                 if (err)
2179                         goto unlock;
2180
2181                 if (vid == pvid) {
2182                         err = _mv88e6xxx_port_pvid_set(ps, port, 0);
2183                         if (err)
2184                                 goto unlock;
2185                 }
2186         }
2187
2188 unlock:
2189         mutex_unlock(&ps->smi_mutex);
2190
2191         return err;
2192 }
2193
2194 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_priv_state *ps,
2195                                     const unsigned char *addr)
2196 {
2197         int i, ret;
2198
2199         for (i = 0; i < 3; i++) {
2200                 ret = _mv88e6xxx_reg_write(
2201                         ps, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
2202                         (addr[i * 2] << 8) | addr[i * 2 + 1]);
2203                 if (ret < 0)
2204                         return ret;
2205         }
2206
2207         return 0;
2208 }
2209
2210 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_priv_state *ps,
2211                                    unsigned char *addr)
2212 {
2213         int i, ret;
2214
2215         for (i = 0; i < 3; i++) {
2216                 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
2217                                           GLOBAL_ATU_MAC_01 + i);
2218                 if (ret < 0)
2219                         return ret;
2220                 addr[i * 2] = ret >> 8;
2221                 addr[i * 2 + 1] = ret & 0xff;
2222         }
2223
2224         return 0;
2225 }
2226
2227 static int _mv88e6xxx_atu_load(struct mv88e6xxx_priv_state *ps,
2228                                struct mv88e6xxx_atu_entry *entry)
2229 {
2230         int ret;
2231
2232         ret = _mv88e6xxx_atu_wait(ps);
2233         if (ret < 0)
2234                 return ret;
2235
2236         ret = _mv88e6xxx_atu_mac_write(ps, entry->mac);
2237         if (ret < 0)
2238                 return ret;
2239
2240         ret = _mv88e6xxx_atu_data_write(ps, entry);
2241         if (ret < 0)
2242                 return ret;
2243
2244         return _mv88e6xxx_atu_cmd(ps, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
2245 }
2246
2247 static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_priv_state *ps, int port,
2248                                     const unsigned char *addr, u16 vid,
2249                                     u8 state)
2250 {
2251         struct mv88e6xxx_atu_entry entry = { 0 };
2252         struct mv88e6xxx_vtu_stu_entry vlan;
2253         int err;
2254
2255         /* Null VLAN ID corresponds to the port private database */
2256         if (vid == 0)
2257                 err = _mv88e6xxx_port_fid_get(ps, port, &vlan.fid);
2258         else
2259                 err = _mv88e6xxx_vtu_get(ps, vid, &vlan, false);
2260         if (err)
2261                 return err;
2262
2263         entry.fid = vlan.fid;
2264         entry.state = state;
2265         ether_addr_copy(entry.mac, addr);
2266         if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2267                 entry.trunk = false;
2268                 entry.portv_trunkid = BIT(port);
2269         }
2270
2271         return _mv88e6xxx_atu_load(ps, &entry);
2272 }
2273
2274 int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2275                                const struct switchdev_obj_port_fdb *fdb,
2276                                struct switchdev_trans *trans)
2277 {
2278         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2279
2280         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU))
2281                 return -EOPNOTSUPP;
2282
2283         /* We don't need any dynamic resource from the kernel (yet),
2284          * so skip the prepare phase.
2285          */
2286         return 0;
2287 }
2288
2289 void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2290                             const struct switchdev_obj_port_fdb *fdb,
2291                             struct switchdev_trans *trans)
2292 {
2293         int state = is_multicast_ether_addr(fdb->addr) ?
2294                 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2295                 GLOBAL_ATU_DATA_STATE_UC_STATIC;
2296         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2297
2298         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU))
2299                 return;
2300
2301         mutex_lock(&ps->smi_mutex);
2302         if (_mv88e6xxx_port_fdb_load(ps, port, fdb->addr, fdb->vid, state))
2303                 netdev_err(ds->ports[port], "failed to load MAC address\n");
2304         mutex_unlock(&ps->smi_mutex);
2305 }
2306
2307 int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2308                            const struct switchdev_obj_port_fdb *fdb)
2309 {
2310         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2311         int ret;
2312
2313         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU))
2314                 return -EOPNOTSUPP;
2315
2316         mutex_lock(&ps->smi_mutex);
2317         ret = _mv88e6xxx_port_fdb_load(ps, port, fdb->addr, fdb->vid,
2318                                        GLOBAL_ATU_DATA_STATE_UNUSED);
2319         mutex_unlock(&ps->smi_mutex);
2320
2321         return ret;
2322 }
2323
2324 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_priv_state *ps, u16 fid,
2325                                   struct mv88e6xxx_atu_entry *entry)
2326 {
2327         struct mv88e6xxx_atu_entry next = { 0 };
2328         int ret;
2329
2330         next.fid = fid;
2331
2332         ret = _mv88e6xxx_atu_wait(ps);
2333         if (ret < 0)
2334                 return ret;
2335
2336         ret = _mv88e6xxx_atu_cmd(ps, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2337         if (ret < 0)
2338                 return ret;
2339
2340         ret = _mv88e6xxx_atu_mac_read(ps, next.mac);
2341         if (ret < 0)
2342                 return ret;
2343
2344         ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_ATU_DATA);
2345         if (ret < 0)
2346                 return ret;
2347
2348         next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2349         if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2350                 unsigned int mask, shift;
2351
2352                 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2353                         next.trunk = true;
2354                         mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2355                         shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2356                 } else {
2357                         next.trunk = false;
2358                         mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2359                         shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2360                 }
2361
2362                 next.portv_trunkid = (ret & mask) >> shift;
2363         }
2364
2365         *entry = next;
2366         return 0;
2367 }
2368
2369 static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_priv_state *ps,
2370                                         u16 fid, u16 vid, int port,
2371                                         struct switchdev_obj_port_fdb *fdb,
2372                                         int (*cb)(struct switchdev_obj *obj))
2373 {
2374         struct mv88e6xxx_atu_entry addr = {
2375                 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2376         };
2377         int err;
2378
2379         err = _mv88e6xxx_atu_mac_write(ps, addr.mac);
2380         if (err)
2381                 return err;
2382
2383         do {
2384                 err = _mv88e6xxx_atu_getnext(ps, fid, &addr);
2385                 if (err)
2386                         break;
2387
2388                 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2389                         break;
2390
2391                 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2392                         bool is_static = addr.state ==
2393                                 (is_multicast_ether_addr(addr.mac) ?
2394                                  GLOBAL_ATU_DATA_STATE_MC_STATIC :
2395                                  GLOBAL_ATU_DATA_STATE_UC_STATIC);
2396
2397                         fdb->vid = vid;
2398                         ether_addr_copy(fdb->addr, addr.mac);
2399                         fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2400
2401                         err = cb(&fdb->obj);
2402                         if (err)
2403                                 break;
2404                 }
2405         } while (!is_broadcast_ether_addr(addr.mac));
2406
2407         return err;
2408 }
2409
2410 int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2411                             struct switchdev_obj_port_fdb *fdb,
2412                             int (*cb)(struct switchdev_obj *obj))
2413 {
2414         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2415         struct mv88e6xxx_vtu_stu_entry vlan = {
2416                 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2417         };
2418         u16 fid;
2419         int err;
2420
2421         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU))
2422                 return -EOPNOTSUPP;
2423
2424         mutex_lock(&ps->smi_mutex);
2425
2426         /* Dump port's default Filtering Information Database (VLAN ID 0) */
2427         err = _mv88e6xxx_port_fid_get(ps, port, &fid);
2428         if (err)
2429                 goto unlock;
2430
2431         err = _mv88e6xxx_port_fdb_dump_one(ps, fid, 0, port, fdb, cb);
2432         if (err)
2433                 goto unlock;
2434
2435         /* Dump VLANs' Filtering Information Databases */
2436         err = _mv88e6xxx_vtu_vid_write(ps, vlan.vid);
2437         if (err)
2438                 goto unlock;
2439
2440         do {
2441                 err = _mv88e6xxx_vtu_getnext(ps, &vlan);
2442                 if (err)
2443                         break;
2444
2445                 if (!vlan.valid)
2446                         break;
2447
2448                 err = _mv88e6xxx_port_fdb_dump_one(ps, vlan.fid, vlan.vid, port,
2449                                                    fdb, cb);
2450                 if (err)
2451                         break;
2452         } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2453
2454 unlock:
2455         mutex_unlock(&ps->smi_mutex);
2456
2457         return err;
2458 }
2459
2460 int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2461                                struct net_device *bridge)
2462 {
2463         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2464         int i, err = 0;
2465
2466         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VLANTABLE))
2467                 return -EOPNOTSUPP;
2468
2469         mutex_lock(&ps->smi_mutex);
2470
2471         /* Assign the bridge and remap each port's VLANTable */
2472         ps->ports[port].bridge_dev = bridge;
2473
2474         for (i = 0; i < ps->info->num_ports; ++i) {
2475                 if (ps->ports[i].bridge_dev == bridge) {
2476                         err = _mv88e6xxx_port_based_vlan_map(ps, i);
2477                         if (err)
2478                                 break;
2479                 }
2480         }
2481
2482         mutex_unlock(&ps->smi_mutex);
2483
2484         return err;
2485 }
2486
2487 void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2488 {
2489         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2490         struct net_device *bridge = ps->ports[port].bridge_dev;
2491         int i;
2492
2493         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VLANTABLE))
2494                 return;
2495
2496         mutex_lock(&ps->smi_mutex);
2497
2498         /* Unassign the bridge and remap each port's VLANTable */
2499         ps->ports[port].bridge_dev = NULL;
2500
2501         for (i = 0; i < ps->info->num_ports; ++i)
2502                 if (i == port || ps->ports[i].bridge_dev == bridge)
2503                         if (_mv88e6xxx_port_based_vlan_map(ps, i))
2504                                 netdev_warn(ds->ports[i], "failed to remap\n");
2505
2506         mutex_unlock(&ps->smi_mutex);
2507 }
2508
2509 static void mv88e6xxx_bridge_work(struct work_struct *work)
2510 {
2511         struct mv88e6xxx_priv_state *ps;
2512         struct dsa_switch *ds;
2513         int port;
2514
2515         ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
2516         ds = ps->ds;
2517
2518         mutex_lock(&ps->smi_mutex);
2519
2520         for (port = 0; port < ps->info->num_ports; ++port)
2521                 if (test_and_clear_bit(port, ps->port_state_update_mask) &&
2522                     _mv88e6xxx_port_state(ps, port, ps->ports[port].state))
2523                         netdev_warn(ds->ports[port],
2524                                     "failed to update state to %s\n",
2525                                     mv88e6xxx_port_state_names[ps->ports[port].state]);
2526
2527         mutex_unlock(&ps->smi_mutex);
2528 }
2529
2530 static int _mv88e6xxx_phy_page_write(struct mv88e6xxx_priv_state *ps,
2531                                      int port, int page, int reg, int val)
2532 {
2533         int ret;
2534
2535         ret = _mv88e6xxx_phy_write_indirect(ps, port, 0x16, page);
2536         if (ret < 0)
2537                 goto restore_page_0;
2538
2539         ret = _mv88e6xxx_phy_write_indirect(ps, port, reg, val);
2540 restore_page_0:
2541         _mv88e6xxx_phy_write_indirect(ps, port, 0x16, 0x0);
2542
2543         return ret;
2544 }
2545
2546 static int _mv88e6xxx_phy_page_read(struct mv88e6xxx_priv_state *ps,
2547                                     int port, int page, int reg)
2548 {
2549         int ret;
2550
2551         ret = _mv88e6xxx_phy_write_indirect(ps, port, 0x16, page);
2552         if (ret < 0)
2553                 goto restore_page_0;
2554
2555         ret = _mv88e6xxx_phy_read_indirect(ps, port, reg);
2556 restore_page_0:
2557         _mv88e6xxx_phy_write_indirect(ps, port, 0x16, 0x0);
2558
2559         return ret;
2560 }
2561
2562 static int mv88e6xxx_switch_reset(struct mv88e6xxx_priv_state *ps)
2563 {
2564         bool ppu_active = mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU_ACTIVE);
2565         u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2566         struct gpio_desc *gpiod = ps->ds->pd->reset;
2567         unsigned long timeout;
2568         int ret;
2569         int i;
2570
2571         /* Set all ports to the disabled state. */
2572         for (i = 0; i < ps->info->num_ports; i++) {
2573                 ret = _mv88e6xxx_reg_read(ps, REG_PORT(i), PORT_CONTROL);
2574                 if (ret < 0)
2575                         return ret;
2576
2577                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(i), PORT_CONTROL,
2578                                            ret & 0xfffc);
2579                 if (ret)
2580                         return ret;
2581         }
2582
2583         /* Wait for transmit queues to drain. */
2584         usleep_range(2000, 4000);
2585
2586         /* If there is a gpio connected to the reset pin, toggle it */
2587         if (gpiod) {
2588                 gpiod_set_value_cansleep(gpiod, 1);
2589                 usleep_range(10000, 20000);
2590                 gpiod_set_value_cansleep(gpiod, 0);
2591                 usleep_range(10000, 20000);
2592         }
2593
2594         /* Reset the switch. Keep the PPU active if requested. The PPU
2595          * needs to be active to support indirect phy register access
2596          * through global registers 0x18 and 0x19.
2597          */
2598         if (ppu_active)
2599                 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, 0x04, 0xc000);
2600         else
2601                 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, 0x04, 0xc400);
2602         if (ret)
2603                 return ret;
2604
2605         /* Wait up to one second for reset to complete. */
2606         timeout = jiffies + 1 * HZ;
2607         while (time_before(jiffies, timeout)) {
2608                 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, 0x00);
2609                 if (ret < 0)
2610                         return ret;
2611
2612                 if ((ret & is_reset) == is_reset)
2613                         break;
2614                 usleep_range(1000, 2000);
2615         }
2616         if (time_after(jiffies, timeout))
2617                 ret = -ETIMEDOUT;
2618         else
2619                 ret = 0;
2620
2621         return ret;
2622 }
2623
2624 static int mv88e6xxx_power_on_serdes(struct mv88e6xxx_priv_state *ps)
2625 {
2626         int ret;
2627
2628         ret = _mv88e6xxx_phy_page_read(ps, REG_FIBER_SERDES, PAGE_FIBER_SERDES,
2629                                        MII_BMCR);
2630         if (ret < 0)
2631                 return ret;
2632
2633         if (ret & BMCR_PDOWN) {
2634                 ret &= ~BMCR_PDOWN;
2635                 ret = _mv88e6xxx_phy_page_write(ps, REG_FIBER_SERDES,
2636                                                 PAGE_FIBER_SERDES, MII_BMCR,
2637                                                 ret);
2638         }
2639
2640         return ret;
2641 }
2642
2643 static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
2644 {
2645         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2646         int ret;
2647         u16 reg;
2648
2649         mutex_lock(&ps->smi_mutex);
2650
2651         if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2652             mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2653             mv88e6xxx_6185_family(ps) || mv88e6xxx_6095_family(ps) ||
2654             mv88e6xxx_6065_family(ps) || mv88e6xxx_6320_family(ps)) {
2655                 /* MAC Forcing register: don't force link, speed,
2656                  * duplex or flow control state to any particular
2657                  * values on physical ports, but force the CPU port
2658                  * and all DSA ports to their maximum bandwidth and
2659                  * full duplex.
2660                  */
2661                 reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_PCS_CTRL);
2662                 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
2663                         reg &= ~PORT_PCS_CTRL_UNFORCED;
2664                         reg |= PORT_PCS_CTRL_FORCE_LINK |
2665                                 PORT_PCS_CTRL_LINK_UP |
2666                                 PORT_PCS_CTRL_DUPLEX_FULL |
2667                                 PORT_PCS_CTRL_FORCE_DUPLEX;
2668                         if (mv88e6xxx_6065_family(ps))
2669                                 reg |= PORT_PCS_CTRL_100;
2670                         else
2671                                 reg |= PORT_PCS_CTRL_1000;
2672                 } else {
2673                         reg |= PORT_PCS_CTRL_UNFORCED;
2674                 }
2675
2676                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
2677                                            PORT_PCS_CTRL, reg);
2678                 if (ret)
2679                         goto abort;
2680         }
2681
2682         /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2683          * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2684          * tunneling, determine priority by looking at 802.1p and IP
2685          * priority fields (IP prio has precedence), and set STP state
2686          * to Forwarding.
2687          *
2688          * If this is the CPU link, use DSA or EDSA tagging depending
2689          * on which tagging mode was configured.
2690          *
2691          * If this is a link to another switch, use DSA tagging mode.
2692          *
2693          * If this is the upstream port for this switch, enable
2694          * forwarding of unknown unicasts and multicasts.
2695          */
2696         reg = 0;
2697         if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2698             mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2699             mv88e6xxx_6095_family(ps) || mv88e6xxx_6065_family(ps) ||
2700             mv88e6xxx_6185_family(ps) || mv88e6xxx_6320_family(ps))
2701                 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2702                 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2703                 PORT_CONTROL_STATE_FORWARDING;
2704         if (dsa_is_cpu_port(ds, port)) {
2705                 if (mv88e6xxx_6095_family(ps) || mv88e6xxx_6185_family(ps))
2706                         reg |= PORT_CONTROL_DSA_TAG;
2707                 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2708                     mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2709                     mv88e6xxx_6320_family(ps)) {
2710                         if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2711                                 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
2712                         else
2713                                 reg |= PORT_CONTROL_FRAME_MODE_DSA;
2714                         reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2715                                 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2716                 }
2717
2718                 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2719                     mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2720                     mv88e6xxx_6095_family(ps) || mv88e6xxx_6065_family(ps) ||
2721                     mv88e6xxx_6185_family(ps) || mv88e6xxx_6320_family(ps)) {
2722                         if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2723                                 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2724                 }
2725         }
2726         if (dsa_is_dsa_port(ds, port)) {
2727                 if (mv88e6xxx_6095_family(ps) || mv88e6xxx_6185_family(ps))
2728                         reg |= PORT_CONTROL_DSA_TAG;
2729                 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2730                     mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2731                     mv88e6xxx_6320_family(ps)) {
2732                         reg |= PORT_CONTROL_FRAME_MODE_DSA;
2733                 }
2734
2735                 if (port == dsa_upstream_port(ds))
2736                         reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2737                                 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2738         }
2739         if (reg) {
2740                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
2741                                            PORT_CONTROL, reg);
2742                 if (ret)
2743                         goto abort;
2744         }
2745
2746         /* If this port is connected to a SerDes, make sure the SerDes is not
2747          * powered down.
2748          */
2749         if (mv88e6xxx_6352_family(ps)) {
2750                 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_STATUS);
2751                 if (ret < 0)
2752                         goto abort;
2753                 ret &= PORT_STATUS_CMODE_MASK;
2754                 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2755                     (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2756                     (ret == PORT_STATUS_CMODE_SGMII)) {
2757                         ret = mv88e6xxx_power_on_serdes(ps);
2758                         if (ret < 0)
2759                                 goto abort;
2760                 }
2761         }
2762
2763         /* Port Control 2: don't force a good FCS, set the maximum frame size to
2764          * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2765          * untagged frames on this port, do a destination address lookup on all
2766          * received packets as usual, disable ARP mirroring and don't send a
2767          * copy of all transmitted/received frames on this port to the CPU.
2768          */
2769         reg = 0;
2770         if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2771             mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2772             mv88e6xxx_6095_family(ps) || mv88e6xxx_6320_family(ps) ||
2773             mv88e6xxx_6185_family(ps))
2774                 reg = PORT_CONTROL_2_MAP_DA;
2775
2776         if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2777             mv88e6xxx_6165_family(ps) || mv88e6xxx_6320_family(ps))
2778                 reg |= PORT_CONTROL_2_JUMBO_10240;
2779
2780         if (mv88e6xxx_6095_family(ps) || mv88e6xxx_6185_family(ps)) {
2781                 /* Set the upstream port this port should use */
2782                 reg |= dsa_upstream_port(ds);
2783                 /* enable forwarding of unknown multicast addresses to
2784                  * the upstream port
2785                  */
2786                 if (port == dsa_upstream_port(ds))
2787                         reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2788         }
2789
2790         reg |= PORT_CONTROL_2_8021Q_DISABLED;
2791
2792         if (reg) {
2793                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
2794                                            PORT_CONTROL_2, reg);
2795                 if (ret)
2796                         goto abort;
2797         }
2798
2799         /* Port Association Vector: when learning source addresses
2800          * of packets, add the address to the address database using
2801          * a port bitmap that has only the bit for this port set and
2802          * the other bits clear.
2803          */
2804         reg = 1 << port;
2805         /* Disable learning for CPU port */
2806         if (dsa_is_cpu_port(ds, port))
2807                 reg = 0;
2808
2809         ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_ASSOC_VECTOR, reg);
2810         if (ret)
2811                 goto abort;
2812
2813         /* Egress rate control 2: disable egress rate control. */
2814         ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_RATE_CONTROL_2,
2815                                    0x0000);
2816         if (ret)
2817                 goto abort;
2818
2819         if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2820             mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2821             mv88e6xxx_6320_family(ps)) {
2822                 /* Do not limit the period of time that this port can
2823                  * be paused for by the remote end or the period of
2824                  * time that this port can pause the remote end.
2825                  */
2826                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
2827                                            PORT_PAUSE_CTRL, 0x0000);
2828                 if (ret)
2829                         goto abort;
2830
2831                 /* Port ATU control: disable limiting the number of
2832                  * address database entries that this port is allowed
2833                  * to use.
2834                  */
2835                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
2836                                            PORT_ATU_CONTROL, 0x0000);
2837                 /* Priority Override: disable DA, SA and VTU priority
2838                  * override.
2839                  */
2840                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
2841                                            PORT_PRI_OVERRIDE, 0x0000);
2842                 if (ret)
2843                         goto abort;
2844
2845                 /* Port Ethertype: use the Ethertype DSA Ethertype
2846                  * value.
2847                  */
2848                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
2849                                            PORT_ETH_TYPE, ETH_P_EDSA);
2850                 if (ret)
2851                         goto abort;
2852                 /* Tag Remap: use an identity 802.1p prio -> switch
2853                  * prio mapping.
2854                  */
2855                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
2856                                            PORT_TAG_REGMAP_0123, 0x3210);
2857                 if (ret)
2858                         goto abort;
2859
2860                 /* Tag Remap 2: use an identity 802.1p prio -> switch
2861                  * prio mapping.
2862                  */
2863                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
2864                                            PORT_TAG_REGMAP_4567, 0x7654);
2865                 if (ret)
2866                         goto abort;
2867         }
2868
2869         if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2870             mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2871             mv88e6xxx_6185_family(ps) || mv88e6xxx_6095_family(ps) ||
2872             mv88e6xxx_6320_family(ps)) {
2873                 /* Rate Control: disable ingress rate limiting. */
2874                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
2875                                            PORT_RATE_CONTROL, 0x0001);
2876                 if (ret)
2877                         goto abort;
2878         }
2879
2880         /* Port Control 1: disable trunking, disable sending
2881          * learning messages to this port.
2882          */
2883         ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL_1, 0x0000);
2884         if (ret)
2885                 goto abort;
2886
2887         /* Port based VLAN map: give each port the same default address
2888          * database, and allow bidirectional communication between the
2889          * CPU and DSA port(s), and the other ports.
2890          */
2891         ret = _mv88e6xxx_port_fid_set(ps, port, 0);
2892         if (ret)
2893                 goto abort;
2894
2895         ret = _mv88e6xxx_port_based_vlan_map(ps, port);
2896         if (ret)
2897                 goto abort;
2898
2899         /* Default VLAN ID and priority: don't set a default VLAN
2900          * ID, and set the default packet priority to zero.
2901          */
2902         ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_DEFAULT_VLAN,
2903                                    0x0000);
2904 abort:
2905         mutex_unlock(&ps->smi_mutex);
2906         return ret;
2907 }
2908
2909 int mv88e6xxx_setup_ports(struct dsa_switch *ds)
2910 {
2911         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2912         int ret;
2913         int i;
2914
2915         for (i = 0; i < ps->info->num_ports; i++) {
2916                 ret = mv88e6xxx_setup_port(ds, i);
2917                 if (ret < 0)
2918                         return ret;
2919         }
2920         return 0;
2921 }
2922
2923 static int mv88e6xxx_setup_global(struct mv88e6xxx_priv_state *ps)
2924 {
2925         struct dsa_switch *ds = ps->ds;
2926         u32 upstream_port = dsa_upstream_port(ds);
2927         u16 reg;
2928         int err;
2929         int i;
2930
2931         /* Enable the PHY Polling Unit if present, don't discard any packets,
2932          * and mask all interrupt sources.
2933          */
2934         reg = 0;
2935         if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU) ||
2936             mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU_ACTIVE))
2937                 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2938
2939         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL, reg);
2940         if (err)
2941                 return err;
2942
2943         /* Configure the upstream port, and configure it as the port to which
2944          * ingress and egress and ARP monitor frames are to be sent.
2945          */
2946         reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2947                 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2948                 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
2949         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg);
2950         if (err)
2951                 return err;
2952
2953         /* Disable remote management, and set the switch's DSA device number. */
2954         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL_2,
2955                                    GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2956                                    (ds->index & 0x1f));
2957         if (err)
2958                 return err;
2959
2960         /* Set the default address aging time to 5 minutes, and
2961          * enable address learn messages to be sent to all message
2962          * ports.
2963          */
2964         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_CONTROL,
2965                                    0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
2966         if (err)
2967                 return err;
2968
2969         /* Configure the IP ToS mapping registers. */
2970         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2971         if (err)
2972                 return err;
2973         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2974         if (err)
2975                 return err;
2976         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2977         if (err)
2978                 return err;
2979         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2980         if (err)
2981                 return err;
2982         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2983         if (err)
2984                 return err;
2985         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2986         if (err)
2987                 return err;
2988         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2989         if (err)
2990                 return err;
2991         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2992         if (err)
2993                 return err;
2994
2995         /* Configure the IEEE 802.1p priority mapping register. */
2996         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2997         if (err)
2998                 return err;
2999
3000         /* Send all frames with destination addresses matching
3001          * 01:80:c2:00:00:0x to the CPU port.
3002          */
3003         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
3004         if (err)
3005                 return err;
3006
3007         /* Ignore removed tag data on doubly tagged packets, disable
3008          * flow control messages, force flow control priority to the
3009          * highest, and send all special multicast frames to the CPU
3010          * port at the highest priority.
3011          */
3012         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
3013                                    0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
3014                                    GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
3015         if (err)
3016                 return err;
3017
3018         /* Program the DSA routing table. */
3019         for (i = 0; i < 32; i++) {
3020                 int nexthop = 0x1f;
3021
3022                 if (ps->ds->pd->rtable &&
3023                     i != ps->ds->index && i < ps->ds->dst->pd->nr_chips)
3024                         nexthop = ps->ds->pd->rtable[i] & 0x1f;
3025
3026                 err = _mv88e6xxx_reg_write(
3027                         ps, REG_GLOBAL2,
3028                         GLOBAL2_DEVICE_MAPPING,
3029                         GLOBAL2_DEVICE_MAPPING_UPDATE |
3030                         (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) | nexthop);
3031                 if (err)
3032                         return err;
3033         }
3034
3035         /* Clear all trunk masks. */
3036         for (i = 0; i < 8; i++) {
3037                 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
3038                                            0x8000 |
3039                                            (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
3040                                            ((1 << ps->info->num_ports) - 1));
3041                 if (err)
3042                         return err;
3043         }
3044
3045         /* Clear all trunk mappings. */
3046         for (i = 0; i < 16; i++) {
3047                 err = _mv88e6xxx_reg_write(
3048                         ps, REG_GLOBAL2,
3049                         GLOBAL2_TRUNK_MAPPING,
3050                         GLOBAL2_TRUNK_MAPPING_UPDATE |
3051                         (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
3052                 if (err)
3053                         return err;
3054         }
3055
3056         if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
3057             mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
3058             mv88e6xxx_6320_family(ps)) {
3059                 /* Send all frames with destination addresses matching
3060                  * 01:80:c2:00:00:2x to the CPU port.
3061                  */
3062                 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2,
3063                                            GLOBAL2_MGMT_EN_2X, 0xffff);
3064                 if (err)
3065                         return err;
3066
3067                 /* Initialise cross-chip port VLAN table to reset
3068                  * defaults.
3069                  */
3070                 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2,
3071                                            GLOBAL2_PVT_ADDR, 0x9000);
3072                 if (err)
3073                         return err;
3074
3075                 /* Clear the priority override table. */
3076                 for (i = 0; i < 16; i++) {
3077                         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2,
3078                                                    GLOBAL2_PRIO_OVERRIDE,
3079                                                    0x8000 | (i << 8));
3080                         if (err)
3081                                 return err;
3082                 }
3083         }
3084
3085         if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
3086             mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
3087             mv88e6xxx_6185_family(ps) || mv88e6xxx_6095_family(ps) ||
3088             mv88e6xxx_6320_family(ps)) {
3089                 /* Disable ingress rate limiting by resetting all
3090                  * ingress rate limit registers to their initial
3091                  * state.
3092                  */
3093                 for (i = 0; i < ps->info->num_ports; i++) {
3094                         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2,
3095                                                    GLOBAL2_INGRESS_OP,
3096                                                    0x9000 | (i << 8));
3097                         if (err)
3098                                 return err;
3099                 }
3100         }
3101
3102         /* Clear the statistics counters for all ports */
3103         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_STATS_OP,
3104                                    GLOBAL_STATS_OP_FLUSH_ALL);
3105         if (err)
3106                 return err;
3107
3108         /* Wait for the flush to complete. */
3109         err = _mv88e6xxx_stats_wait(ps);
3110         if (err)
3111                 return err;
3112
3113         /* Clear all ATU entries */
3114         err = _mv88e6xxx_atu_flush(ps, 0, true);
3115         if (err)
3116                 return err;
3117
3118         /* Clear all the VTU and STU entries */
3119         err = _mv88e6xxx_vtu_stu_flush(ps);
3120         if (err < 0)
3121                 return err;
3122
3123         return err;
3124 }
3125
3126 int mv88e6xxx_setup_common(struct mv88e6xxx_priv_state *ps)
3127 {
3128         int err;
3129
3130         mutex_init(&ps->smi_mutex);
3131
3132         INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
3133
3134         if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM))
3135                 mutex_init(&ps->eeprom_mutex);
3136
3137         if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU))
3138                 mv88e6xxx_ppu_state_init(ps);
3139
3140         mutex_lock(&ps->smi_mutex);
3141
3142         err = mv88e6xxx_switch_reset(ps);
3143         if (err)
3144                 goto unlock;
3145
3146         err = mv88e6xxx_setup_global(ps);
3147
3148 unlock:
3149         mutex_unlock(&ps->smi_mutex);
3150
3151         return err;
3152 }
3153
3154 int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
3155 {
3156         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3157         int ret;
3158
3159         mutex_lock(&ps->smi_mutex);
3160         ret = _mv88e6xxx_phy_page_read(ps, port, page, reg);
3161         mutex_unlock(&ps->smi_mutex);
3162
3163         return ret;
3164 }
3165
3166 int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
3167                              int reg, int val)
3168 {
3169         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3170         int ret;
3171
3172         mutex_lock(&ps->smi_mutex);
3173         ret = _mv88e6xxx_phy_page_write(ps, port, page, reg, val);
3174         mutex_unlock(&ps->smi_mutex);
3175
3176         return ret;
3177 }
3178
3179 static int mv88e6xxx_port_to_phy_addr(struct mv88e6xxx_priv_state *ps,
3180                                       int port)
3181 {
3182         if (port >= 0 && port < ps->info->num_ports)
3183                 return port;
3184         return -EINVAL;
3185 }
3186
3187 int
3188 mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
3189 {
3190         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3191         int addr = mv88e6xxx_port_to_phy_addr(ps, port);
3192         int ret;
3193
3194         if (addr < 0)
3195                 return 0xffff;
3196
3197         mutex_lock(&ps->smi_mutex);
3198
3199         if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU))
3200                 ret = mv88e6xxx_phy_read_ppu(ps, addr, regnum);
3201         else if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_SMI_PHY))
3202                 ret = _mv88e6xxx_phy_read_indirect(ps, addr, regnum);
3203         else
3204                 ret = _mv88e6xxx_phy_read(ps, addr, regnum);
3205
3206         mutex_unlock(&ps->smi_mutex);
3207         return ret;
3208 }
3209
3210 int
3211 mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
3212 {
3213         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3214         int addr = mv88e6xxx_port_to_phy_addr(ps, port);
3215         int ret;
3216
3217         if (addr < 0)
3218                 return 0xffff;
3219
3220         mutex_lock(&ps->smi_mutex);
3221
3222         if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU))
3223                 ret = mv88e6xxx_phy_write_ppu(ps, addr, regnum, val);
3224         else if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_SMI_PHY))
3225                 ret = _mv88e6xxx_phy_write_indirect(ps, addr, regnum, val);
3226         else
3227                 ret = _mv88e6xxx_phy_write(ps, addr, regnum, val);
3228
3229         mutex_unlock(&ps->smi_mutex);
3230         return ret;
3231 }
3232
3233 #ifdef CONFIG_NET_DSA_HWMON
3234
3235 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3236 {
3237         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3238         int ret;
3239         int val;
3240
3241         *temp = 0;
3242
3243         mutex_lock(&ps->smi_mutex);
3244
3245         ret = _mv88e6xxx_phy_write(ps, 0x0, 0x16, 0x6);
3246         if (ret < 0)
3247                 goto error;
3248
3249         /* Enable temperature sensor */
3250         ret = _mv88e6xxx_phy_read(ps, 0x0, 0x1a);
3251         if (ret < 0)
3252                 goto error;
3253
3254         ret = _mv88e6xxx_phy_write(ps, 0x0, 0x1a, ret | (1 << 5));
3255         if (ret < 0)
3256                 goto error;
3257
3258         /* Wait for temperature to stabilize */
3259         usleep_range(10000, 12000);
3260
3261         val = _mv88e6xxx_phy_read(ps, 0x0, 0x1a);
3262         if (val < 0) {
3263                 ret = val;
3264                 goto error;
3265         }
3266
3267         /* Disable temperature sensor */
3268         ret = _mv88e6xxx_phy_write(ps, 0x0, 0x1a, ret & ~(1 << 5));
3269         if (ret < 0)
3270                 goto error;
3271
3272         *temp = ((val & 0x1f) - 5) * 5;
3273
3274 error:
3275         _mv88e6xxx_phy_write(ps, 0x0, 0x16, 0x0);
3276         mutex_unlock(&ps->smi_mutex);
3277         return ret;
3278 }
3279
3280 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3281 {
3282         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3283         int phy = mv88e6xxx_6320_family(ps) ? 3 : 0;
3284         int ret;
3285
3286         *temp = 0;
3287
3288         ret = mv88e6xxx_phy_page_read(ds, phy, 6, 27);
3289         if (ret < 0)
3290                 return ret;
3291
3292         *temp = (ret & 0xff) - 25;
3293
3294         return 0;
3295 }
3296
3297 int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3298 {
3299         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3300
3301         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP))
3302                 return -EOPNOTSUPP;
3303
3304         if (mv88e6xxx_6320_family(ps) || mv88e6xxx_6352_family(ps))
3305                 return mv88e63xx_get_temp(ds, temp);
3306
3307         return mv88e61xx_get_temp(ds, temp);
3308 }
3309
3310 int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3311 {
3312         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3313         int phy = mv88e6xxx_6320_family(ps) ? 3 : 0;
3314         int ret;
3315
3316         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP_LIMIT))
3317                 return -EOPNOTSUPP;
3318
3319         *temp = 0;
3320
3321         ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3322         if (ret < 0)
3323                 return ret;
3324
3325         *temp = (((ret >> 8) & 0x1f) * 5) - 25;
3326
3327         return 0;
3328 }
3329
3330 int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3331 {
3332         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3333         int phy = mv88e6xxx_6320_family(ps) ? 3 : 0;
3334         int ret;
3335
3336         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP_LIMIT))
3337                 return -EOPNOTSUPP;
3338
3339         ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3340         if (ret < 0)
3341                 return ret;
3342         temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3343         return mv88e6xxx_phy_page_write(ds, phy, 6, 26,
3344                                         (ret & 0xe0ff) | (temp << 8));
3345 }
3346
3347 int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3348 {
3349         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3350         int phy = mv88e6xxx_6320_family(ps) ? 3 : 0;
3351         int ret;
3352
3353         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP_LIMIT))
3354                 return -EOPNOTSUPP;
3355
3356         *alarm = false;
3357
3358         ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3359         if (ret < 0)
3360                 return ret;
3361
3362         *alarm = !!(ret & 0x40);
3363
3364         return 0;
3365 }
3366 #endif /* CONFIG_NET_DSA_HWMON */
3367
3368 static const struct mv88e6xxx_info *
3369 mv88e6xxx_lookup_info(unsigned int prod_num, const struct mv88e6xxx_info *table,
3370                       unsigned int num)
3371 {
3372         int i;
3373
3374         for (i = 0; i < num; ++i)
3375                 if (table[i].prod_num == prod_num)
3376                         return &table[i];
3377
3378         return NULL;
3379 }
3380
3381 const char *mv88e6xxx_drv_probe(struct device *dsa_dev, struct device *host_dev,
3382                                 int sw_addr, void **priv,
3383                                 const struct mv88e6xxx_info *table,
3384                                 unsigned int num)
3385 {
3386         const struct mv88e6xxx_info *info;
3387         struct mv88e6xxx_priv_state *ps;
3388         struct mii_bus *bus;
3389         const char *name;
3390         int id, prod_num, rev;
3391
3392         bus = dsa_host_dev_to_mii_bus(host_dev);
3393         if (!bus)
3394                 return NULL;
3395
3396         id = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), PORT_SWITCH_ID);
3397         if (id < 0)
3398                 return NULL;
3399
3400         prod_num = (id & 0xfff0) >> 4;
3401         rev = id & 0x000f;
3402
3403         info = mv88e6xxx_lookup_info(prod_num, table, num);
3404         if (!info)
3405                 return NULL;
3406
3407         name = info->name;
3408
3409         ps = devm_kzalloc(dsa_dev, sizeof(*ps), GFP_KERNEL);
3410         if (!ps)
3411                 return NULL;
3412
3413         ps->bus = bus;
3414         ps->sw_addr = sw_addr;
3415         ps->info = info;
3416
3417         *priv = ps;
3418
3419         dev_info(&ps->bus->dev, "switch 0x%x probed: %s, revision %u\n",
3420                  prod_num, name, rev);
3421
3422         return name;
3423 }
3424
3425 static int __init mv88e6xxx_init(void)
3426 {
3427 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
3428         register_switch_driver(&mv88e6131_switch_driver);
3429 #endif
3430 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123)
3431         register_switch_driver(&mv88e6123_switch_driver);
3432 #endif
3433 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
3434         register_switch_driver(&mv88e6352_switch_driver);
3435 #endif
3436 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
3437         register_switch_driver(&mv88e6171_switch_driver);
3438 #endif
3439         return 0;
3440 }
3441 module_init(mv88e6xxx_init);
3442
3443 static void __exit mv88e6xxx_cleanup(void)
3444 {
3445 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
3446         unregister_switch_driver(&mv88e6171_switch_driver);
3447 #endif
3448 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
3449         unregister_switch_driver(&mv88e6352_switch_driver);
3450 #endif
3451 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123)
3452         unregister_switch_driver(&mv88e6123_switch_driver);
3453 #endif
3454 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
3455         unregister_switch_driver(&mv88e6131_switch_driver);
3456 #endif
3457 }
3458 module_exit(mv88e6xxx_cleanup);
3459
3460 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
3461 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
3462 MODULE_LICENSE("GPL");