drivers/net/dsa/mv88e6xxx/chip.c

   1 /*
   2  * Marvell 88e6xxx Ethernet switch single-chip support
   3  *
   4  * Copyright (c) 2008 Marvell Semiconductor
   5  *
   6  * Copyright (c) 2015 CMC Electronics, Inc.
   7  *      Added support for VLAN Table Unit operations
   8  *
   9  * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include <linux/delay.h>
  18 #include <linux/etherdevice.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/if_bridge.h>
  21 #include <linux/jiffies.h>
  22 #include <linux/list.h>
  23 #include <linux/mdio.h>
  24 #include <linux/module.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_mdio.h>
  27 #include <linux/netdevice.h>
  28 #include <linux/gpio/consumer.h>
  29 #include <linux/phy.h>
  30 #include <net/dsa.h>
  31 #include <net/switchdev.h>
  32
  33 #include "mv88e6xxx.h"
  34 #include "global1.h"
  35 #include "global2.h"
  36
  37 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
  38 {
  39         if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
  40                 dev_err(chip->dev, "Switch registers lock not held!\n");
  41                 dump_stack();
  42         }
  43 }
  44
  45 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
  46  * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
  47  *
  48  * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
  49  * is the only device connected to the SMI master. In this mode it responds to
  50  * all 32 possible SMI addresses, and thus maps directly the internal devices.
  51  *
  52  * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
  53  * multiple devices to share the SMI interface. In this mode it responds to only
  54  * 2 registers, used to indirectly access the internal SMI devices.
  55  */
  56
  57 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
  58                               int addr, int reg, u16 *val)
  59 {
  60         if (!chip->smi_ops)
  61                 return -EOPNOTSUPP;
  62
  63         return chip->smi_ops->read(chip, addr, reg, val);
  64 }
  65
  66 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
  67                                int addr, int reg, u16 val)
  68 {
  69         if (!chip->smi_ops)
  70                 return -EOPNOTSUPP;
  71
  72         return chip->smi_ops->write(chip, addr, reg, val);
  73 }
  74
  75 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
  76                                           int addr, int reg, u16 *val)
  77 {
  78         int ret;
  79
  80         ret = mdiobus_read_nested(chip->bus, addr, reg);
  81         if (ret < 0)
  82                 return ret;
  83
  84         *val = ret & 0xffff;
  85
  86         return 0;
  87 }
  88
  89 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
  90                                            int addr, int reg, u16 val)
  91 {
  92         int ret;
  93
  94         ret = mdiobus_write_nested(chip->bus, addr, reg, val);
  95         if (ret < 0)
  96                 return ret;
  97
  98         return 0;
  99 }
 100
 101 static const struct mv88e6xxx_ops mv88e6xxx_smi_single_chip_ops = {
 102         .read = mv88e6xxx_smi_single_chip_read,
 103         .write = mv88e6xxx_smi_single_chip_write,
 104 };
 105
 106 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
 107 {
 108         int ret;
 109         int i;
 110
 111         for (i = 0; i < 16; i++) {
 112                 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
 113                 if (ret < 0)
 114                         return ret;
 115
 116                 if ((ret & SMI_CMD_BUSY) == 0)
 117                         return 0;
 118         }
 119
 120         return -ETIMEDOUT;
 121 }
 122
 123 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
 124                                          int addr, int reg, u16 *val)
 125 {
 126         int ret;
 127
 128         /* Wait for the bus to become free. */
 129         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 130         if (ret < 0)
 131                 return ret;
 132
 133         /* Transmit the read command. */
 134         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
 135                                    SMI_CMD_OP_22_READ | (addr << 5) | reg);
 136         if (ret < 0)
 137                 return ret;
 138
 139         /* Wait for the read command to complete. */
 140         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 141         if (ret < 0)
 142                 return ret;
 143
 144         /* Read the data. */
 145         ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
 146         if (ret < 0)
 147                 return ret;
 148
 149         *val = ret & 0xffff;
 150
 151         return 0;
 152 }
 153
 154 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
 155                                           int addr, int reg, u16 val)
 156 {
 157         int ret;
 158
 159         /* Wait for the bus to become free. */
 160         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 161         if (ret < 0)
 162                 return ret;
 163
 164         /* Transmit the data to write. */
 165         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
 166         if (ret < 0)
 167                 return ret;
 168
 169         /* Transmit the write command. */
 170         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
 171                                    SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
 172         if (ret < 0)
 173                 return ret;
 174
 175         /* Wait for the write command to complete. */
 176         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 177         if (ret < 0)
 178                 return ret;
 179
 180         return 0;
 181 }
 182
 183 static const struct mv88e6xxx_ops mv88e6xxx_smi_multi_chip_ops = {
 184         .read = mv88e6xxx_smi_multi_chip_read,
 185         .write = mv88e6xxx_smi_multi_chip_write,
 186 };
 187
 188 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
 189 {
 190         int err;
 191
 192         assert_reg_lock(chip);
 193
 194         err = mv88e6xxx_smi_read(chip, addr, reg, val);
 195         if (err)
 196                 return err;
 197
 198         dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
 199                 addr, reg, *val);
 200
 201         return 0;
 202 }
 203
 204 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
 205 {
 206         int err;
 207
 208         assert_reg_lock(chip);
 209
 210         err = mv88e6xxx_smi_write(chip, addr, reg, val);
 211         if (err)
 212                 return err;
 213
 214         dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
 215                 addr, reg, val);
 216
 217         return 0;
 218 }
 219
 220 static int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
 221                                u16 *val)
 222 {
 223         int addr = chip->info->port_base_addr + port;
 224
 225         return mv88e6xxx_read(chip, addr, reg, val);
 226 }
 227
 228 static int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
 229                                 u16 val)
 230 {
 231         int addr = chip->info->port_base_addr + port;
 232
 233         return mv88e6xxx_write(chip, addr, reg, val);
 234 }
 235
 236 static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
 237                               int reg, u16 *val)
 238 {
 239         int addr = phy; /* PHY devices addresses start at 0x0 */
 240
 241         if (!chip->phy_ops)
 242                 return -EOPNOTSUPP;
 243
 244         return chip->phy_ops->read(chip, addr, reg, val);
 245 }
 246
 247 static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
 248                                int reg, u16 val)
 249 {
 250         int addr = phy; /* PHY devices addresses start at 0x0 */
 251
 252         if (!chip->phy_ops)
 253                 return -EOPNOTSUPP;
 254
 255         return chip->phy_ops->write(chip, addr, reg, val);
 256 }
 257
 258 static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
 259 {
 260         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
 261                 return -EOPNOTSUPP;
 262
 263         return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
 264 }
 265
 266 static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
 267 {
 268         int err;
 269
 270         /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
 271         err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
 272         if (unlikely(err)) {
 273                 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
 274                         phy, err);
 275         }
 276 }
 277
 278 static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
 279                                    u8 page, int reg, u16 *val)
 280 {
 281         int err;
 282
 283         /* There is no paging for registers 22 */
 284         if (reg == PHY_PAGE)
 285                 return -EINVAL;
 286
 287         err = mv88e6xxx_phy_page_get(chip, phy, page);
 288         if (!err) {
 289                 err = mv88e6xxx_phy_read(chip, phy, reg, val);
 290                 mv88e6xxx_phy_page_put(chip, phy);
 291         }
 292
 293         return err;
 294 }
 295
 296 static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
 297                                     u8 page, int reg, u16 val)
 298 {
 299         int err;
 300
 301         /* There is no paging for registers 22 */
 302         if (reg == PHY_PAGE)
 303                 return -EINVAL;
 304
 305         err = mv88e6xxx_phy_page_get(chip, phy, page);
 306         if (!err) {
 307                 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
 308                 mv88e6xxx_phy_page_put(chip, phy);
 309         }
 310
 311         return err;
 312 }
 313
 314 static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
 315 {
 316         return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
 317                                        reg, val);
 318 }
 319
 320 static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
 321 {
 322         return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
 323                                         reg, val);
 324 }
 325
 326 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
 327 {
 328         int i;
 329
 330         for (i = 0; i < 16; i++) {
 331                 u16 val;
 332                 int err;
 333
 334                 err = mv88e6xxx_read(chip, addr, reg, &val);
 335                 if (err)
 336                         return err;
 337
 338                 if (!(val & mask))
 339                         return 0;
 340
 341                 usleep_range(1000, 2000);
 342         }
 343
 344         dev_err(chip->dev, "Timeout while waiting for switch\n");
 345         return -ETIMEDOUT;
 346 }
 347
 348 /* Indirect write to single pointer-data register with an Update bit */
 349 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
 350 {
 351         u16 val;
 352         int err;
 353
 354         /* Wait until the previous operation is completed */
 355         err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
 356         if (err)
 357                 return err;
 358
 359         /* Set the Update bit to trigger a write operation */
 360         val = BIT(15) | update;
 361
 362         return mv88e6xxx_write(chip, addr, reg, val);
 363 }
 364
 365 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
 366 {
 367         u16 val;
 368         int i, err;
 369
 370         err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
 371         if (err)
 372                 return err;
 373
 374         err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
 375                                  val & ~GLOBAL_CONTROL_PPU_ENABLE);
 376         if (err)
 377                 return err;
 378
 379         for (i = 0; i < 16; i++) {
 380                 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
 381                 if (err)
 382                         return err;
 383
 384                 usleep_range(1000, 2000);
 385                 if ((val & GLOBAL_STATUS_PPU_MASK) != GLOBAL_STATUS_PPU_POLLING)
 386                         return 0;
 387         }
 388
 389         return -ETIMEDOUT;
 390 }
 391
 392 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
 393 {
 394         u16 val;
 395         int i, err;
 396
 397         err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
 398         if (err)
 399                 return err;
 400
 401         err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
 402                                  val | GLOBAL_CONTROL_PPU_ENABLE);
 403         if (err)
 404                 return err;
 405
 406         for (i = 0; i < 16; i++) {
 407                 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
 408                 if (err)
 409                         return err;
 410
 411                 usleep_range(1000, 2000);
 412                 if ((val & GLOBAL_STATUS_PPU_MASK) == GLOBAL_STATUS_PPU_POLLING)
 413                         return 0;
 414         }
 415
 416         return -ETIMEDOUT;
 417 }
 418
 419 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
 420 {
 421         struct mv88e6xxx_chip *chip;
 422
 423         chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
 424
 425         mutex_lock(&chip->reg_lock);
 426
 427         if (mutex_trylock(&chip->ppu_mutex)) {
 428                 if (mv88e6xxx_ppu_enable(chip) == 0)
 429                         chip->ppu_disabled = 0;
 430                 mutex_unlock(&chip->ppu_mutex);
 431         }
 432
 433         mutex_unlock(&chip->reg_lock);
 434 }
 435
 436 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
 437 {
 438         struct mv88e6xxx_chip *chip = (void *)_ps;
 439
 440         schedule_work(&chip->ppu_work);
 441 }
 442
 443 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
 444 {
 445         int ret;
 446
 447         mutex_lock(&chip->ppu_mutex);
 448
 449         /* If the PHY polling unit is enabled, disable it so that
 450          * we can access the PHY registers.  If it was already
 451          * disabled, cancel the timer that is going to re-enable
 452          * it.
 453          */
 454         if (!chip->ppu_disabled) {
 455                 ret = mv88e6xxx_ppu_disable(chip);
 456                 if (ret < 0) {
 457                         mutex_unlock(&chip->ppu_mutex);
 458                         return ret;
 459                 }
 460                 chip->ppu_disabled = 1;
 461         } else {
 462                 del_timer(&chip->ppu_timer);
 463                 ret = 0;
 464         }
 465
 466         return ret;
 467 }
 468
 469 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
 470 {
 471         /* Schedule a timer to re-enable the PHY polling unit. */
 472         mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
 473         mutex_unlock(&chip->ppu_mutex);
 474 }
 475
 476 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
 477 {
 478         mutex_init(&chip->ppu_mutex);
 479         INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
 480         init_timer(&chip->ppu_timer);
 481         chip->ppu_timer.data = (unsigned long)chip;
 482         chip->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
 483 }
 484
 485 static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
 486 {
 487         del_timer_sync(&chip->ppu_timer);
 488 }
 489
 490 static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr,
 491                                   int reg, u16 *val)
 492 {
 493         int err;
 494
 495         err = mv88e6xxx_ppu_access_get(chip);
 496         if (!err) {
 497                 err = mv88e6xxx_read(chip, addr, reg, val);
 498                 mv88e6xxx_ppu_access_put(chip);
 499         }
 500
 501         return err;
 502 }
 503
 504 static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr,
 505                                    int reg, u16 val)
 506 {
 507         int err;
 508
 509         err = mv88e6xxx_ppu_access_get(chip);
 510         if (!err) {
 511                 err = mv88e6xxx_write(chip, addr, reg, val);
 512                 mv88e6xxx_ppu_access_put(chip);
 513         }
 514
 515         return err;
 516 }
 517
 518 static const struct mv88e6xxx_ops mv88e6xxx_phy_ppu_ops = {
 519         .read = mv88e6xxx_phy_ppu_read,
 520         .write = mv88e6xxx_phy_ppu_write,
 521 };
 522
 523 static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
 524 {
 525         return chip->info->family == MV88E6XXX_FAMILY_6065;
 526 }
 527
 528 static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
 529 {
 530         return chip->info->family == MV88E6XXX_FAMILY_6095;
 531 }
 532
 533 static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
 534 {
 535         return chip->info->family == MV88E6XXX_FAMILY_6097;
 536 }
 537
 538 static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
 539 {
 540         return chip->info->family == MV88E6XXX_FAMILY_6165;
 541 }
 542
 543 static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
 544 {
 545         return chip->info->family == MV88E6XXX_FAMILY_6185;
 546 }
 547
 548 static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
 549 {
 550         return chip->info->family == MV88E6XXX_FAMILY_6320;
 551 }
 552
 553 static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
 554 {
 555         return chip->info->family == MV88E6XXX_FAMILY_6351;
 556 }
 557
 558 static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
 559 {
 560         return chip->info->family == MV88E6XXX_FAMILY_6352;
 561 }
 562
 563 static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
 564 {
 565         return chip->info->num_databases;
 566 }
 567
 568 static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_chip *chip)
 569 {
 570         /* Does the device have dedicated FID registers for ATU and VTU ops? */
 571         if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
 572             mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip))
 573                 return true;
 574
 575         return false;
 576 }
 577
 578 /* We expect the switch to perform auto negotiation if there is a real
 579  * phy. However, in the case of a fixed link phy, we force the port
 580  * settings from the fixed link settings.
 581  */
 582 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
 583                                   struct phy_device *phydev)
 584 {
 585         struct mv88e6xxx_chip *chip = ds->priv;
 586         u16 reg;
 587         int err;
 588
 589         if (!phy_is_pseudo_fixed_link(phydev))
 590                 return;
 591
 592         mutex_lock(&chip->reg_lock);
 593
 594         err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, &reg);
 595         if (err)
 596                 goto out;
 597
 598         reg &= ~(PORT_PCS_CTRL_LINK_UP |
 599                  PORT_PCS_CTRL_FORCE_LINK |
 600                  PORT_PCS_CTRL_DUPLEX_FULL |
 601                  PORT_PCS_CTRL_FORCE_DUPLEX |
 602                  PORT_PCS_CTRL_UNFORCED);
 603
 604         reg |= PORT_PCS_CTRL_FORCE_LINK;
 605         if (phydev->link)
 606                 reg |= PORT_PCS_CTRL_LINK_UP;
 607
 608         if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100)
 609                 goto out;
 610
 611         switch (phydev->speed) {
 612         case SPEED_1000:
 613                 reg |= PORT_PCS_CTRL_1000;
 614                 break;
 615         case SPEED_100:
 616                 reg |= PORT_PCS_CTRL_100;
 617                 break;
 618         case SPEED_10:
 619                 reg |= PORT_PCS_CTRL_10;
 620                 break;
 621         default:
 622                 pr_info("Unknown speed");
 623                 goto out;
 624         }
 625
 626         reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
 627         if (phydev->duplex == DUPLEX_FULL)
 628                 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
 629
 630         if ((mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip)) &&
 631             (port >= chip->info->num_ports - 2)) {
 632                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 633                         reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
 634                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 635                         reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
 636                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 637                         reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
 638                                 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
 639         }
 640         mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
 641
 642 out:
 643         mutex_unlock(&chip->reg_lock);
 644 }
 645
 646 static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip)
 647 {
 648         u16 val;
 649         int i, err;
 650
 651         for (i = 0; i < 10; i++) {
 652                 err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_OP, &val);
 653                 if ((val & GLOBAL_STATS_OP_BUSY) == 0)
 654                         return 0;
 655         }
 656
 657         return -ETIMEDOUT;
 658 }
 659
 660 static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
 661 {
 662         int err;
 663
 664         if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
 665                 port = (port + 1) << 5;
 666
 667         /* Snapshot the hardware statistics counters for this port. */
 668         err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
 669                                  GLOBAL_STATS_OP_CAPTURE_PORT |
 670                                  GLOBAL_STATS_OP_HIST_RX_TX | port);
 671         if (err)
 672                 return err;
 673
 674         /* Wait for the snapshotting to complete. */
 675         return _mv88e6xxx_stats_wait(chip);
 676 }
 677
 678 static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip,
 679                                   int stat, u32 *val)
 680 {
 681         u32 value;
 682         u16 reg;
 683         int err;
 684
 685         *val = 0;
 686
 687         err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
 688                                  GLOBAL_STATS_OP_READ_CAPTURED |
 689                                  GLOBAL_STATS_OP_HIST_RX_TX | stat);
 690         if (err)
 691                 return;
 692
 693         err = _mv88e6xxx_stats_wait(chip);
 694         if (err)
 695                 return;
 696
 697         err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_32, &reg);
 698         if (err)
 699                 return;
 700
 701         value = reg << 16;
 702
 703         err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_01, &reg);
 704         if (err)
 705                 return;
 706
 707         *val = value | reg;
 708 }
 709
 710 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
 711         { "in_good_octets",     8, 0x00, BANK0, },
 712         { "in_bad_octets",      4, 0x02, BANK0, },
 713         { "in_unicast",         4, 0x04, BANK0, },
 714         { "in_broadcasts",      4, 0x06, BANK0, },
 715         { "in_multicasts",      4, 0x07, BANK0, },
 716         { "in_pause",           4, 0x16, BANK0, },
 717         { "in_undersize",       4, 0x18, BANK0, },
 718         { "in_fragments",       4, 0x19, BANK0, },
 719         { "in_oversize",        4, 0x1a, BANK0, },
 720         { "in_jabber",          4, 0x1b, BANK0, },
 721         { "in_rx_error",        4, 0x1c, BANK0, },
 722         { "in_fcs_error",       4, 0x1d, BANK0, },
 723         { "out_octets",         8, 0x0e, BANK0, },
 724         { "out_unicast",        4, 0x10, BANK0, },
 725         { "out_broadcasts",     4, 0x13, BANK0, },
 726         { "out_multicasts",     4, 0x12, BANK0, },
 727         { "out_pause",          4, 0x15, BANK0, },
 728         { "excessive",          4, 0x11, BANK0, },
 729         { "collisions",         4, 0x1e, BANK0, },
 730         { "deferred",           4, 0x05, BANK0, },
 731         { "single",             4, 0x14, BANK0, },
 732         { "multiple",           4, 0x17, BANK0, },
 733         { "out_fcs_error",      4, 0x03, BANK0, },
 734         { "late",               4, 0x1f, BANK0, },
 735         { "hist_64bytes",       4, 0x08, BANK0, },
 736         { "hist_65_127bytes",   4, 0x09, BANK0, },
 737         { "hist_128_255bytes",  4, 0x0a, BANK0, },
 738         { "hist_256_511bytes",  4, 0x0b, BANK0, },
 739         { "hist_512_1023bytes", 4, 0x0c, BANK0, },
 740         { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
 741         { "sw_in_discards",     4, 0x10, PORT, },
 742         { "sw_in_filtered",     2, 0x12, PORT, },
 743         { "sw_out_filtered",    2, 0x13, PORT, },
 744         { "in_discards",        4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 745         { "in_filtered",        4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 746         { "in_accepted",        4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 747         { "in_bad_accepted",    4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 748         { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 749         { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 750         { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 751         { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 752         { "tcam_counter_0",     4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 753         { "tcam_counter_1",     4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 754         { "tcam_counter_2",     4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
 755         { "tcam_counter_3",     4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
 756         { "in_da_unknown",      4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
 757         { "in_management",      4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
 758         { "out_queue_0",        4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 759         { "out_queue_1",        4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 760         { "out_queue_2",        4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 761         { "out_queue_3",        4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 762         { "out_queue_4",        4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 763         { "out_queue_5",        4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 764         { "out_queue_6",        4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 765         { "out_queue_7",        4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 766         { "out_cut_through",    4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 767         { "out_octets_a",       4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
 768         { "out_octets_b",       4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
 769         { "out_management",     4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
 770 };
 771
 772 static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip,
 773                                struct mv88e6xxx_hw_stat *stat)
 774 {
 775         switch (stat->type) {
 776         case BANK0:
 777                 return true;
 778         case BANK1:
 779                 return mv88e6xxx_6320_family(chip);
 780         case PORT:
 781                 return mv88e6xxx_6095_family(chip) ||
 782                         mv88e6xxx_6185_family(chip) ||
 783                         mv88e6xxx_6097_family(chip) ||
 784                         mv88e6xxx_6165_family(chip) ||
 785                         mv88e6xxx_6351_family(chip) ||
 786                         mv88e6xxx_6352_family(chip);
 787         }
 788         return false;
 789 }
 790
 791 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
 792                                             struct mv88e6xxx_hw_stat *s,
 793                                             int port)
 794 {
 795         u32 low;
 796         u32 high = 0;
 797         int err;
 798         u16 reg;
 799         u64 value;
 800
 801         switch (s->type) {
 802         case PORT:
 803                 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
 804                 if (err)
 805                         return UINT64_MAX;
 806
 807                 low = reg;
 808                 if (s->sizeof_stat == 4) {
 809                         err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
 810                         if (err)
 811                                 return UINT64_MAX;
 812                         high = reg;
 813                 }
 814                 break;
 815         case BANK0:
 816         case BANK1:
 817                 _mv88e6xxx_stats_read(chip, s->reg, &low);
 818                 if (s->sizeof_stat == 8)
 819                         _mv88e6xxx_stats_read(chip, s->reg + 1, &high);
 820         }
 821         value = (((u64)high) << 16) | low;
 822         return value;
 823 }
 824
 825 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
 826                                   uint8_t *data)
 827 {
 828         struct mv88e6xxx_chip *chip = ds->priv;
 829         struct mv88e6xxx_hw_stat *stat;
 830         int i, j;
 831
 832         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 833                 stat = &mv88e6xxx_hw_stats[i];
 834                 if (mv88e6xxx_has_stat(chip, stat)) {
 835                         memcpy(data + j * ETH_GSTRING_LEN, stat->string,
 836                                ETH_GSTRING_LEN);
 837                         j++;
 838                 }
 839         }
 840 }
 841
 842 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
 843 {
 844         struct mv88e6xxx_chip *chip = ds->priv;
 845         struct mv88e6xxx_hw_stat *stat;
 846         int i, j;
 847
 848         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 849                 stat = &mv88e6xxx_hw_stats[i];
 850                 if (mv88e6xxx_has_stat(chip, stat))
 851                         j++;
 852         }
 853         return j;
 854 }
 855
 856 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
 857                                         uint64_t *data)
 858 {
 859         struct mv88e6xxx_chip *chip = ds->priv;
 860         struct mv88e6xxx_hw_stat *stat;
 861         int ret;
 862         int i, j;
 863
 864         mutex_lock(&chip->reg_lock);
 865
 866         ret = _mv88e6xxx_stats_snapshot(chip, port);
 867         if (ret < 0) {
 868                 mutex_unlock(&chip->reg_lock);
 869                 return;
 870         }
 871         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 872                 stat = &mv88e6xxx_hw_stats[i];
 873                 if (mv88e6xxx_has_stat(chip, stat)) {
 874                         data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port);
 875                         j++;
 876                 }
 877         }
 878
 879         mutex_unlock(&chip->reg_lock);
 880 }
 881
 882 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
 883 {
 884         return 32 * sizeof(u16);
 885 }
 886
 887 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
 888                                struct ethtool_regs *regs, void *_p)
 889 {
 890         struct mv88e6xxx_chip *chip = ds->priv;
 891         int err;
 892         u16 reg;
 893         u16 *p = _p;
 894         int i;
 895
 896         regs->version = 0;
 897
 898         memset(p, 0xff, 32 * sizeof(u16));
 899
 900         mutex_lock(&chip->reg_lock);
 901
 902         for (i = 0; i < 32; i++) {
 903
 904                 err = mv88e6xxx_port_read(chip, port, i, &reg);
 905                 if (!err)
 906                         p[i] = reg;
 907         }
 908
 909         mutex_unlock(&chip->reg_lock);
 910 }
 911
 912 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
 913 {
 914         return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY);
 915 }
 916
 917 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
 918                              struct ethtool_eee *e)
 919 {
 920         struct mv88e6xxx_chip *chip = ds->priv;
 921         u16 reg;
 922         int err;
 923
 924         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
 925                 return -EOPNOTSUPP;
 926
 927         mutex_lock(&chip->reg_lock);
 928
 929         err = mv88e6xxx_phy_read(chip, port, 16, &reg);
 930         if (err)
 931                 goto out;
 932
 933         e->eee_enabled = !!(reg & 0x0200);
 934         e->tx_lpi_enabled = !!(reg & 0x0100);
 935
 936         err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
 937         if (err)
 938                 goto out;
 939
 940         e->eee_active = !!(reg & PORT_STATUS_EEE);
 941 out:
 942         mutex_unlock(&chip->reg_lock);
 943
 944         return err;
 945 }
 946
 947 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
 948                              struct phy_device *phydev, struct ethtool_eee *e)
 949 {
 950         struct mv88e6xxx_chip *chip = ds->priv;
 951         u16 reg;
 952         int err;
 953
 954         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
 955                 return -EOPNOTSUPP;
 956
 957         mutex_lock(&chip->reg_lock);
 958
 959         err = mv88e6xxx_phy_read(chip, port, 16, &reg);
 960         if (err)
 961                 goto out;
 962
 963         reg &= ~0x0300;
 964         if (e->eee_enabled)
 965                 reg |= 0x0200;
 966         if (e->tx_lpi_enabled)
 967                 reg |= 0x0100;
 968
 969         err = mv88e6xxx_phy_write(chip, port, 16, reg);
 970 out:
 971         mutex_unlock(&chip->reg_lock);
 972
 973         return err;
 974 }
 975
 976 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
 977 {
 978         u16 val;
 979         int err;
 980
 981         if (mv88e6xxx_has_fid_reg(chip)) {
 982                 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid);
 983                 if (err)
 984                         return err;
 985         } else if (mv88e6xxx_num_databases(chip) == 256) {
 986                 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
 987                 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
 988                 if (err)
 989                         return err;
 990
 991                 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
 992                                          (val & 0xfff) | ((fid << 8) & 0xf000));
 993                 if (err)
 994                         return err;
 995
 996                 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
 997                 cmd |= fid & 0xf;
 998         }
 999
1000         err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, cmd);
1001         if (err)
1002                 return err;
1003
1004         return _mv88e6xxx_atu_wait(chip);
1005 }
1006
1007 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
1008                                      struct mv88e6xxx_atu_entry *entry)
1009 {
1010         u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1011
1012         if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1013                 unsigned int mask, shift;
1014
1015                 if (entry->trunk) {
1016                         data |= GLOBAL_ATU_DATA_TRUNK;
1017                         mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1018                         shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1019                 } else {
1020                         mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1021                         shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1022                 }
1023
1024                 data |= (entry->portv_trunkid << shift) & mask;
1025         }
1026
1027         return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data);
1028 }
1029
1030 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
1031                                      struct mv88e6xxx_atu_entry *entry,
1032                                      bool static_too)
1033 {
1034         int op;
1035         int err;
1036
1037         err = _mv88e6xxx_atu_wait(chip);
1038         if (err)
1039                 return err;
1040
1041         err = _mv88e6xxx_atu_data_write(chip, entry);
1042         if (err)
1043                 return err;
1044
1045         if (entry->fid) {
1046                 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1047                         GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1048         } else {
1049                 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1050                         GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1051         }
1052
1053         return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
1054 }
1055
1056 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
1057                                 u16 fid, bool static_too)
1058 {
1059         struct mv88e6xxx_atu_entry entry = {
1060                 .fid = fid,
1061                 .state = 0, /* EntryState bits must be 0 */
1062         };
1063
1064         return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1065 }
1066
1067 static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
1068                                int from_port, int to_port, bool static_too)
1069 {
1070         struct mv88e6xxx_atu_entry entry = {
1071                 .trunk = false,
1072                 .fid = fid,
1073         };
1074
1075         /* EntryState bits must be 0xF */
1076         entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1077
1078         /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1079         entry.portv_trunkid = (to_port & 0x0f) << 4;
1080         entry.portv_trunkid |= from_port & 0x0f;
1081
1082         return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1083 }
1084
1085 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
1086                                  int port, bool static_too)
1087 {
1088         /* Destination port 0xF means remove the entries */
1089         return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
1090 }
1091
1092 static const char * const mv88e6xxx_port_state_names[] = {
1093         [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1094         [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1095         [PORT_CONTROL_STATE_LEARNING] = "Learning",
1096         [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1097 };
1098
1099 static int _mv88e6xxx_port_state(struct mv88e6xxx_chip *chip, int port,
1100                                  u8 state)
1101 {
1102         struct dsa_switch *ds = chip->ds;
1103         u16 reg;
1104         int err;
1105         u8 oldstate;
1106
1107         err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, &reg);
1108         if (err)
1109                 return err;
1110
1111         oldstate = reg & PORT_CONTROL_STATE_MASK;
1112
1113         reg &= ~PORT_CONTROL_STATE_MASK;
1114         reg |= state;
1115
1116         err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
1117         if (err)
1118                 return err;
1119
1120         netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n",
1121                    mv88e6xxx_port_state_names[state],
1122                    mv88e6xxx_port_state_names[oldstate]);
1123
1124         return 0;
1125 }
1126
1127 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
1128 {
1129         struct net_device *bridge = chip->ports[port].bridge_dev;
1130         const u16 mask = (1 << chip->info->num_ports) - 1;
1131         struct dsa_switch *ds = chip->ds;
1132         u16 output_ports = 0;
1133         u16 reg;
1134         int err;
1135         int i;
1136
1137         /* allow CPU port or DSA link(s) to send frames to every port */
1138         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1139                 output_ports = mask;
1140         } else {
1141                 for (i = 0; i < chip->info->num_ports; ++i) {
1142                         /* allow sending frames to every group member */
1143                         if (bridge && chip->ports[i].bridge_dev == bridge)
1144                                 output_ports |= BIT(i);
1145
1146                         /* allow sending frames to CPU port and DSA link(s) */
1147                         if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1148                                 output_ports |= BIT(i);
1149                 }
1150         }
1151
1152         /* prevent frames from going back out of the port they came in on */
1153         output_ports &= ~BIT(port);
1154
1155         err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, &reg);
1156         if (err)
1157                 return err;
1158
1159         reg &= ~mask;
1160         reg |= output_ports & mask;
1161
1162         return mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg);
1163 }
1164
1165 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1166                                          u8 state)
1167 {
1168         struct mv88e6xxx_chip *chip = ds->priv;
1169         int stp_state;
1170         int err;
1171
1172         switch (state) {
1173         case BR_STATE_DISABLED:
1174                 stp_state = PORT_CONTROL_STATE_DISABLED;
1175                 break;
1176         case BR_STATE_BLOCKING:
1177         case BR_STATE_LISTENING:
1178                 stp_state = PORT_CONTROL_STATE_BLOCKING;
1179                 break;
1180         case BR_STATE_LEARNING:
1181                 stp_state = PORT_CONTROL_STATE_LEARNING;
1182                 break;
1183         case BR_STATE_FORWARDING:
1184         default:
1185                 stp_state = PORT_CONTROL_STATE_FORWARDING;
1186                 break;
1187         }
1188
1189         mutex_lock(&chip->reg_lock);
1190         err = _mv88e6xxx_port_state(chip, port, stp_state);
1191         mutex_unlock(&chip->reg_lock);
1192
1193         if (err)
1194                 netdev_err(ds->ports[port].netdev,
1195                            "failed to update state to %s\n",
1196                            mv88e6xxx_port_state_names[stp_state]);
1197 }
1198
1199 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1200 {
1201         struct mv88e6xxx_chip *chip = ds->priv;
1202         int err;
1203
1204         mutex_lock(&chip->reg_lock);
1205         err = _mv88e6xxx_atu_remove(chip, 0, port, false);
1206         mutex_unlock(&chip->reg_lock);
1207
1208         if (err)
1209                 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
1210 }
1211
1212 static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip *chip, int port,
1213                                 u16 *new, u16 *old)
1214 {
1215         struct dsa_switch *ds = chip->ds;
1216         u16 pvid, reg;
1217         int err;
1218
1219         err = mv88e6xxx_port_read(chip, port, PORT_DEFAULT_VLAN, &reg);
1220         if (err)
1221                 return err;
1222
1223         pvid = reg & PORT_DEFAULT_VLAN_MASK;
1224
1225         if (new) {
1226                 reg &= ~PORT_DEFAULT_VLAN_MASK;
1227                 reg |= *new & PORT_DEFAULT_VLAN_MASK;
1228
1229                 err = mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, reg);
1230                 if (err)
1231                         return err;
1232
1233                 netdev_dbg(ds->ports[port].netdev,
1234                            "DefaultVID %d (was %d)\n", *new, pvid);
1235         }
1236
1237         if (old)
1238                 *old = pvid;
1239
1240         return 0;
1241 }
1242
1243 static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_chip *chip,
1244                                     int port, u16 *pvid)
1245 {
1246         return _mv88e6xxx_port_pvid(chip, port, NULL, pvid);
1247 }
1248
1249 static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip *chip,
1250                                     int port, u16 pvid)
1251 {
1252         return _mv88e6xxx_port_pvid(chip, port, &pvid, NULL);
1253 }
1254
1255 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
1256 {
1257         return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY);
1258 }
1259
1260 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
1261 {
1262         int err;
1263
1264         err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op);
1265         if (err)
1266                 return err;
1267
1268         return _mv88e6xxx_vtu_wait(chip);
1269 }
1270
1271 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
1272 {
1273         int ret;
1274
1275         ret = _mv88e6xxx_vtu_wait(chip);
1276         if (ret < 0)
1277                 return ret;
1278
1279         return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
1280 }
1281
1282 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
1283                                         struct mv88e6xxx_vtu_stu_entry *entry,
1284                                         unsigned int nibble_offset)
1285 {
1286         u16 regs[3];
1287         int i, err;
1288
1289         for (i = 0; i < 3; ++i) {
1290                 u16 *reg = &regs[i];
1291
1292                 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1293                 if (err)
1294                         return err;
1295         }
1296
1297         for (i = 0; i < chip->info->num_ports; ++i) {
1298                 unsigned int shift = (i % 4) * 4 + nibble_offset;
1299                 u16 reg = regs[i / 4];
1300
1301                 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1302         }
1303
1304         return 0;
1305 }
1306
1307 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
1308                                    struct mv88e6xxx_vtu_stu_entry *entry)
1309 {
1310         return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
1311 }
1312
1313 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
1314                                    struct mv88e6xxx_vtu_stu_entry *entry)
1315 {
1316         return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
1317 }
1318
1319 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
1320                                          struct mv88e6xxx_vtu_stu_entry *entry,
1321                                          unsigned int nibble_offset)
1322 {
1323         u16 regs[3] = { 0 };
1324         int i, err;
1325
1326         for (i = 0; i < chip->info->num_ports; ++i) {
1327                 unsigned int shift = (i % 4) * 4 + nibble_offset;
1328                 u8 data = entry->data[i];
1329
1330                 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1331         }
1332
1333         for (i = 0; i < 3; ++i) {
1334                 u16 reg = regs[i];
1335
1336                 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1337                 if (err)
1338                         return err;
1339         }
1340
1341         return 0;
1342 }
1343
1344 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
1345                                     struct mv88e6xxx_vtu_stu_entry *entry)
1346 {
1347         return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
1348 }
1349
1350 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
1351                                     struct mv88e6xxx_vtu_stu_entry *entry)
1352 {
1353         return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
1354 }
1355
1356 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
1357 {
1358         return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID,
1359                                   vid & GLOBAL_VTU_VID_MASK);
1360 }
1361
1362 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1363                                   struct mv88e6xxx_vtu_stu_entry *entry)
1364 {
1365         struct mv88e6xxx_vtu_stu_entry next = { 0 };
1366         u16 val;
1367         int err;
1368
1369         err = _mv88e6xxx_vtu_wait(chip);
1370         if (err)
1371                 return err;
1372
1373         err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1374         if (err)
1375                 return err;
1376
1377         err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1378         if (err)
1379                 return err;
1380
1381         next.vid = val & GLOBAL_VTU_VID_MASK;
1382         next.valid = !!(val & GLOBAL_VTU_VID_VALID);
1383
1384         if (next.valid) {
1385                 err = mv88e6xxx_vtu_data_read(chip, &next);
1386                 if (err)
1387                         return err;
1388
1389                 if (mv88e6xxx_has_fid_reg(chip)) {
1390                         err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val);
1391                         if (err)
1392                                 return err;
1393
1394                         next.fid = val & GLOBAL_VTU_FID_MASK;
1395                 } else if (mv88e6xxx_num_databases(chip) == 256) {
1396                         /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1397                          * VTU DBNum[3:0] are located in VTU Operation 3:0
1398                          */
1399                         err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val);
1400                         if (err)
1401                                 return err;
1402
1403                         next.fid = (val & 0xf00) >> 4;
1404                         next.fid |= val & 0xf;
1405                 }
1406
1407                 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1408                         err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1409                         if (err)
1410                                 return err;
1411
1412                         next.sid = val & GLOBAL_VTU_SID_MASK;
1413                 }
1414         }
1415
1416         *entry = next;
1417         return 0;
1418 }
1419
1420 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1421                                     struct switchdev_obj_port_vlan *vlan,
1422                                     int (*cb)(struct switchdev_obj *obj))
1423 {
1424         struct mv88e6xxx_chip *chip = ds->priv;
1425         struct mv88e6xxx_vtu_stu_entry next;
1426         u16 pvid;
1427         int err;
1428
1429         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1430                 return -EOPNOTSUPP;
1431
1432         mutex_lock(&chip->reg_lock);
1433
1434         err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
1435         if (err)
1436                 goto unlock;
1437
1438         err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1439         if (err)
1440                 goto unlock;
1441
1442         do {
1443                 err = _mv88e6xxx_vtu_getnext(chip, &next);
1444                 if (err)
1445                         break;
1446
1447                 if (!next.valid)
1448                         break;
1449
1450                 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1451                         continue;
1452
1453                 /* reinit and dump this VLAN obj */
1454                 vlan->vid_begin = next.vid;
1455                 vlan->vid_end = next.vid;
1456                 vlan->flags = 0;
1457
1458                 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1459                         vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1460
1461                 if (next.vid == pvid)
1462                         vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1463
1464                 err = cb(&vlan->obj);
1465                 if (err)
1466                         break;
1467         } while (next.vid < GLOBAL_VTU_VID_MASK);
1468
1469 unlock:
1470         mutex_unlock(&chip->reg_lock);
1471
1472         return err;
1473 }
1474
1475 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1476                                     struct mv88e6xxx_vtu_stu_entry *entry)
1477 {
1478         u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
1479         u16 reg = 0;
1480         int err;
1481
1482         err = _mv88e6xxx_vtu_wait(chip);
1483         if (err)
1484                 return err;
1485
1486         if (!entry->valid)
1487                 goto loadpurge;
1488
1489         /* Write port member tags */
1490         err = mv88e6xxx_vtu_data_write(chip, entry);
1491         if (err)
1492                 return err;
1493
1494         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1495                 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1496                 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1497                 if (err)
1498                         return err;
1499         }
1500
1501         if (mv88e6xxx_has_fid_reg(chip)) {
1502                 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1503                 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg);
1504                 if (err)
1505                         return err;
1506         } else if (mv88e6xxx_num_databases(chip) == 256) {
1507                 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1508                  * VTU DBNum[3:0] are located in VTU Operation 3:0
1509                  */
1510                 op |= (entry->fid & 0xf0) << 8;
1511                 op |= entry->fid & 0xf;
1512         }
1513
1514         reg = GLOBAL_VTU_VID_VALID;
1515 loadpurge:
1516         reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1517         err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1518         if (err)
1519                 return err;
1520
1521         return _mv88e6xxx_vtu_cmd(chip, op);
1522 }
1523
1524 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
1525                                   struct mv88e6xxx_vtu_stu_entry *entry)
1526 {
1527         struct mv88e6xxx_vtu_stu_entry next = { 0 };
1528         u16 val;
1529         int err;
1530
1531         err = _mv88e6xxx_vtu_wait(chip);
1532         if (err)
1533                 return err;
1534
1535         err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID,
1536                                  sid & GLOBAL_VTU_SID_MASK);
1537         if (err)
1538                 return err;
1539
1540         err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1541         if (err)
1542                 return err;
1543
1544         err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1545         if (err)
1546                 return err;
1547
1548         next.sid = val & GLOBAL_VTU_SID_MASK;
1549
1550         err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1551         if (err)
1552                 return err;
1553
1554         next.valid = !!(val & GLOBAL_VTU_VID_VALID);
1555
1556         if (next.valid) {
1557                 err = mv88e6xxx_stu_data_read(chip, &next);
1558                 if (err)
1559                         return err;
1560         }
1561
1562         *entry = next;
1563         return 0;
1564 }
1565
1566 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1567                                     struct mv88e6xxx_vtu_stu_entry *entry)
1568 {
1569         u16 reg = 0;
1570         int err;
1571
1572         err = _mv88e6xxx_vtu_wait(chip);
1573         if (err)
1574                 return err;
1575
1576         if (!entry->valid)
1577                 goto loadpurge;
1578
1579         /* Write port states */
1580         err = mv88e6xxx_stu_data_write(chip, entry);
1581         if (err)
1582                 return err;
1583
1584         reg = GLOBAL_VTU_VID_VALID;
1585 loadpurge:
1586         err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1587         if (err)
1588                 return err;
1589
1590         reg = entry->sid & GLOBAL_VTU_SID_MASK;
1591         err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1592         if (err)
1593                 return err;
1594
1595         return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1596 }
1597
1598 static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip *chip, int port,
1599                                u16 *new, u16 *old)
1600 {
1601         struct dsa_switch *ds = chip->ds;
1602         u16 upper_mask;
1603         u16 fid;
1604         u16 reg;
1605         int err;
1606
1607         if (mv88e6xxx_num_databases(chip) == 4096)
1608                 upper_mask = 0xff;
1609         else if (mv88e6xxx_num_databases(chip) == 256)
1610                 upper_mask = 0xf;
1611         else
1612                 return -EOPNOTSUPP;
1613
1614         /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1615         err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, &reg);
1616         if (err)
1617                 return err;
1618
1619         fid = (reg & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1620
1621         if (new) {
1622                 reg &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1623                 reg |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1624
1625                 err = mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg);
1626                 if (err)
1627                         return err;
1628         }
1629
1630         /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1631         err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_1, &reg);
1632         if (err)
1633                 return err;
1634
1635         fid |= (reg & upper_mask) << 4;
1636
1637         if (new) {
1638                 reg &= ~upper_mask;
1639                 reg |= (*new >> 4) & upper_mask;
1640
1641                 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, reg);
1642                 if (err)
1643                         return err;
1644
1645                 netdev_dbg(ds->ports[port].netdev,
1646                            "FID %d (was %d)\n", *new, fid);
1647         }
1648
1649         if (old)
1650                 *old = fid;
1651
1652         return 0;
1653 }
1654
1655 static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_chip *chip,
1656                                    int port, u16 *fid)
1657 {
1658         return _mv88e6xxx_port_fid(chip, port, NULL, fid);
1659 }
1660
1661 static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_chip *chip,
1662                                    int port, u16 fid)
1663 {
1664         return _mv88e6xxx_port_fid(chip, port, &fid, NULL);
1665 }
1666
1667 static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
1668 {
1669         DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1670         struct mv88e6xxx_vtu_stu_entry vlan;
1671         int i, err;
1672
1673         bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1674
1675         /* Set every FID bit used by the (un)bridged ports */
1676         for (i = 0; i < chip->info->num_ports; ++i) {
1677                 err = _mv88e6xxx_port_fid_get(chip, i, fid);
1678                 if (err)
1679                         return err;
1680
1681                 set_bit(*fid, fid_bitmap);
1682         }
1683
1684         /* Set every FID bit used by the VLAN entries */
1685         err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1686         if (err)
1687                 return err;
1688
1689         do {
1690                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1691                 if (err)
1692                         return err;
1693
1694                 if (!vlan.valid)
1695                         break;
1696
1697                 set_bit(vlan.fid, fid_bitmap);
1698         } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1699
1700         /* The reset value 0x000 is used to indicate that multiple address
1701          * databases are not needed. Return the next positive available.
1702          */
1703         *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1704         if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1705                 return -ENOSPC;
1706
1707         /* Clear the database */
1708         return _mv88e6xxx_atu_flush(chip, *fid, true);
1709 }
1710
1711 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
1712                               struct mv88e6xxx_vtu_stu_entry *entry)
1713 {
1714         struct dsa_switch *ds = chip->ds;
1715         struct mv88e6xxx_vtu_stu_entry vlan = {
1716                 .valid = true,
1717                 .vid = vid,
1718         };
1719         int i, err;
1720
1721         err = _mv88e6xxx_fid_new(chip, &vlan.fid);
1722         if (err)
1723                 return err;
1724
1725         /* exclude all ports except the CPU and DSA ports */
1726         for (i = 0; i < chip->info->num_ports; ++i)
1727                 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1728                         ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1729                         : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1730
1731         if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1732             mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
1733                 struct mv88e6xxx_vtu_stu_entry vstp;
1734
1735                 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1736                  * implemented, only one STU entry is needed to cover all VTU
1737                  * entries. Thus, validate the SID 0.
1738                  */
1739                 vlan.sid = 0;
1740                 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
1741                 if (err)
1742                         return err;
1743
1744                 if (vstp.sid != vlan.sid || !vstp.valid) {
1745                         memset(&vstp, 0, sizeof(vstp));
1746                         vstp.valid = true;
1747                         vstp.sid = vlan.sid;
1748
1749                         err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
1750                         if (err)
1751                                 return err;
1752                 }
1753         }
1754
1755         *entry = vlan;
1756         return 0;
1757 }
1758
1759 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1760                               struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1761 {
1762         int err;
1763
1764         if (!vid)
1765                 return -EINVAL;
1766
1767         err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
1768         if (err)
1769                 return err;
1770
1771         err = _mv88e6xxx_vtu_getnext(chip, entry);
1772         if (err)
1773                 return err;
1774
1775         if (entry->vid != vid || !entry->valid) {
1776                 if (!creat)
1777                         return -EOPNOTSUPP;
1778                 /* -ENOENT would've been more appropriate, but switchdev expects
1779                  * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1780                  */
1781
1782                 err = _mv88e6xxx_vtu_new(chip, vid, entry);
1783         }
1784
1785         return err;
1786 }
1787
1788 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1789                                         u16 vid_begin, u16 vid_end)
1790 {
1791         struct mv88e6xxx_chip *chip = ds->priv;
1792         struct mv88e6xxx_vtu_stu_entry vlan;
1793         int i, err;
1794
1795         if (!vid_begin)
1796                 return -EOPNOTSUPP;
1797
1798         mutex_lock(&chip->reg_lock);
1799
1800         err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
1801         if (err)
1802                 goto unlock;
1803
1804         do {
1805                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1806                 if (err)
1807                         goto unlock;
1808
1809                 if (!vlan.valid)
1810                         break;
1811
1812                 if (vlan.vid > vid_end)
1813                         break;
1814
1815                 for (i = 0; i < chip->info->num_ports; ++i) {
1816                         if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1817                                 continue;
1818
1819                         if (vlan.data[i] ==
1820                             GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1821                                 continue;
1822
1823                         if (chip->ports[i].bridge_dev ==
1824                             chip->ports[port].bridge_dev)
1825                                 break; /* same bridge, check next VLAN */
1826
1827                         netdev_warn(ds->ports[port].netdev,
1828                                     "hardware VLAN %d already used by %s\n",
1829                                     vlan.vid,
1830                                     netdev_name(chip->ports[i].bridge_dev));
1831                         err = -EOPNOTSUPP;
1832                         goto unlock;
1833                 }
1834         } while (vlan.vid < vid_end);
1835
1836 unlock:
1837         mutex_unlock(&chip->reg_lock);
1838
1839         return err;
1840 }
1841
1842 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1843         [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
1844         [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
1845         [PORT_CONTROL_2_8021Q_CHECK] = "Check",
1846         [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
1847 };
1848
1849 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1850                                          bool vlan_filtering)
1851 {
1852         struct mv88e6xxx_chip *chip = ds->priv;
1853         u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1854                 PORT_CONTROL_2_8021Q_DISABLED;
1855         u16 reg;
1856         int err;
1857
1858         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1859                 return -EOPNOTSUPP;
1860
1861         mutex_lock(&chip->reg_lock);
1862
1863         err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, &reg);
1864         if (err)
1865                 goto unlock;
1866
1867         old = reg & PORT_CONTROL_2_8021Q_MASK;
1868
1869         if (new != old) {
1870                 reg &= ~PORT_CONTROL_2_8021Q_MASK;
1871                 reg |= new & PORT_CONTROL_2_8021Q_MASK;
1872
1873                 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
1874                 if (err)
1875                         goto unlock;
1876
1877                 netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n",
1878                            mv88e6xxx_port_8021q_mode_names[new],
1879                            mv88e6xxx_port_8021q_mode_names[old]);
1880         }
1881
1882         err = 0;
1883 unlock:
1884         mutex_unlock(&chip->reg_lock);
1885
1886         return err;
1887 }
1888
1889 static int
1890 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1891                             const struct switchdev_obj_port_vlan *vlan,
1892                             struct switchdev_trans *trans)
1893 {
1894         struct mv88e6xxx_chip *chip = ds->priv;
1895         int err;
1896
1897         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1898                 return -EOPNOTSUPP;
1899
1900         /* If the requested port doesn't belong to the same bridge as the VLAN
1901          * members, do not support it (yet) and fallback to software VLAN.
1902          */
1903         err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1904                                            vlan->vid_end);
1905         if (err)
1906                 return err;
1907
1908         /* We don't need any dynamic resource from the kernel (yet),
1909          * so skip the prepare phase.
1910          */
1911         return 0;
1912 }
1913
1914 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1915                                     u16 vid, bool untagged)
1916 {
1917         struct mv88e6xxx_vtu_stu_entry vlan;
1918         int err;
1919
1920         err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1921         if (err)
1922                 return err;
1923
1924         vlan.data[port] = untagged ?
1925                 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1926                 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1927
1928         return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1929 }
1930
1931 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1932                                     const struct switchdev_obj_port_vlan *vlan,
1933                                     struct switchdev_trans *trans)
1934 {
1935         struct mv88e6xxx_chip *chip = ds->priv;
1936         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1937         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1938         u16 vid;
1939
1940         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1941                 return;
1942
1943         mutex_lock(&chip->reg_lock);
1944
1945         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1946                 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
1947                         netdev_err(ds->ports[port].netdev,
1948                                    "failed to add VLAN %d%c\n",
1949                                    vid, untagged ? 'u' : 't');
1950
1951         if (pvid && _mv88e6xxx_port_pvid_set(chip, port, vlan->vid_end))
1952                 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
1953                            vlan->vid_end);
1954
1955         mutex_unlock(&chip->reg_lock);
1956 }
1957
1958 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1959                                     int port, u16 vid)
1960 {
1961         struct dsa_switch *ds = chip->ds;
1962         struct mv88e6xxx_vtu_stu_entry vlan;
1963         int i, err;
1964
1965         err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1966         if (err)
1967                 return err;
1968
1969         /* Tell switchdev if this VLAN is handled in software */
1970         if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1971                 return -EOPNOTSUPP;
1972
1973         vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1974
1975         /* keep the VLAN unless all ports are excluded */
1976         vlan.valid = false;
1977         for (i = 0; i < chip->info->num_ports; ++i) {
1978                 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1979                         continue;
1980
1981                 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1982                         vlan.valid = true;
1983                         break;
1984                 }
1985         }
1986
1987         err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1988         if (err)
1989                 return err;
1990
1991         return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
1992 }
1993
1994 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1995                                    const struct switchdev_obj_port_vlan *vlan)
1996 {
1997         struct mv88e6xxx_chip *chip = ds->priv;
1998         u16 pvid, vid;
1999         int err = 0;
2000
2001         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
2002                 return -EOPNOTSUPP;
2003
2004         mutex_lock(&chip->reg_lock);
2005
2006         err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
2007         if (err)
2008                 goto unlock;
2009
2010         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
2011                 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
2012                 if (err)
2013                         goto unlock;
2014
2015                 if (vid == pvid) {
2016                         err = _mv88e6xxx_port_pvid_set(chip, port, 0);
2017                         if (err)
2018                                 goto unlock;
2019                 }
2020         }
2021
2022 unlock:
2023         mutex_unlock(&chip->reg_lock);
2024
2025         return err;
2026 }
2027
2028 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
2029                                     const unsigned char *addr)
2030 {
2031         int i, err;
2032
2033         for (i = 0; i < 3; i++) {
2034                 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i,
2035                                          (addr[i * 2] << 8) | addr[i * 2 + 1]);
2036                 if (err)
2037                         return err;
2038         }
2039
2040         return 0;
2041 }
2042
2043 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
2044                                    unsigned char *addr)
2045 {
2046         u16 val;
2047         int i, err;
2048
2049         for (i = 0; i < 3; i++) {
2050                 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val);
2051                 if (err)
2052                         return err;
2053
2054                 addr[i * 2] = val >> 8;
2055                 addr[i * 2 + 1] = val & 0xff;
2056         }
2057
2058         return 0;
2059 }
2060
2061 static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
2062                                struct mv88e6xxx_atu_entry *entry)
2063 {
2064         int ret;
2065
2066         ret = _mv88e6xxx_atu_wait(chip);
2067         if (ret < 0)
2068                 return ret;
2069
2070         ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
2071         if (ret < 0)
2072                 return ret;
2073
2074         ret = _mv88e6xxx_atu_data_write(chip, entry);
2075         if (ret < 0)
2076                 return ret;
2077
2078         return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
2079 }
2080
2081 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2082                                   struct mv88e6xxx_atu_entry *entry);
2083
2084 static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid,
2085                              const u8 *addr, struct mv88e6xxx_atu_entry *entry)
2086 {
2087         struct mv88e6xxx_atu_entry next;
2088         int err;
2089
2090         eth_broadcast_addr(next.mac);
2091
2092         err = _mv88e6xxx_atu_mac_write(chip, next.mac);
2093         if (err)
2094                 return err;
2095
2096         do {
2097                 err = _mv88e6xxx_atu_getnext(chip, fid, &next);
2098                 if (err)
2099                         return err;
2100
2101                 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2102                         break;
2103
2104                 if (ether_addr_equal(next.mac, addr)) {
2105                         *entry = next;
2106                         return 0;
2107                 }
2108         } while (!is_broadcast_ether_addr(next.mac));
2109
2110         memset(entry, 0, sizeof(*entry));
2111         entry->fid = fid;
2112         ether_addr_copy(entry->mac, addr);
2113
2114         return 0;
2115 }
2116
2117 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2118                                         const unsigned char *addr, u16 vid,
2119                                         u8 state)
2120 {
2121         struct mv88e6xxx_vtu_stu_entry vlan;
2122         struct mv88e6xxx_atu_entry entry;
2123         int err;
2124
2125         /* Null VLAN ID corresponds to the port private database */
2126         if (vid == 0)
2127                 err = _mv88e6xxx_port_fid_get(chip, port, &vlan.fid);
2128         else
2129                 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
2130         if (err)
2131                 return err;
2132
2133         err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry);
2134         if (err)
2135                 return err;
2136
2137         /* Purge the ATU entry only if no port is using it anymore */
2138         if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
2139                 entry.portv_trunkid &= ~BIT(port);
2140                 if (!entry.portv_trunkid)
2141                         entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
2142         } else {
2143                 entry.portv_trunkid |= BIT(port);
2144                 entry.state = state;
2145         }
2146
2147         return _mv88e6xxx_atu_load(chip, &entry);
2148 }
2149
2150 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2151                                       const struct switchdev_obj_port_fdb *fdb,
2152                                       struct switchdev_trans *trans)
2153 {
2154         /* We don't need any dynamic resource from the kernel (yet),
2155          * so skip the prepare phase.
2156          */
2157         return 0;
2158 }
2159
2160 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2161                                    const struct switchdev_obj_port_fdb *fdb,
2162                                    struct switchdev_trans *trans)
2163 {
2164         struct mv88e6xxx_chip *chip = ds->priv;
2165
2166         mutex_lock(&chip->reg_lock);
2167         if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2168                                          GLOBAL_ATU_DATA_STATE_UC_STATIC))
2169                 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
2170         mutex_unlock(&chip->reg_lock);
2171 }
2172
2173 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2174                                   const struct switchdev_obj_port_fdb *fdb)
2175 {
2176         struct mv88e6xxx_chip *chip = ds->priv;
2177         int err;
2178
2179         mutex_lock(&chip->reg_lock);
2180         err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2181                                            GLOBAL_ATU_DATA_STATE_UNUSED);
2182         mutex_unlock(&chip->reg_lock);
2183
2184         return err;
2185 }
2186
2187 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2188                                   struct mv88e6xxx_atu_entry *entry)
2189 {
2190         struct mv88e6xxx_atu_entry next = { 0 };
2191         u16 val;
2192         int err;
2193
2194         next.fid = fid;
2195
2196         err = _mv88e6xxx_atu_wait(chip);
2197         if (err)
2198                 return err;
2199
2200         err = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2201         if (err)
2202                 return err;
2203
2204         err = _mv88e6xxx_atu_mac_read(chip, next.mac);
2205         if (err)
2206                 return err;
2207
2208         err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val);
2209         if (err)
2210                 return err;
2211
2212         next.state = val & GLOBAL_ATU_DATA_STATE_MASK;
2213         if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2214                 unsigned int mask, shift;
2215
2216                 if (val & GLOBAL_ATU_DATA_TRUNK) {
2217                         next.trunk = true;
2218                         mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2219                         shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2220                 } else {
2221                         next.trunk = false;
2222                         mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2223                         shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2224                 }
2225
2226                 next.portv_trunkid = (val & mask) >> shift;
2227         }
2228
2229         *entry = next;
2230         return 0;
2231 }
2232
2233 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2234                                       u16 fid, u16 vid, int port,
2235                                       struct switchdev_obj *obj,
2236                                       int (*cb)(struct switchdev_obj *obj))
2237 {
2238         struct mv88e6xxx_atu_entry addr = {
2239                 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2240         };
2241         int err;
2242
2243         err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
2244         if (err)
2245                 return err;
2246
2247         do {
2248                 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
2249                 if (err)
2250                         return err;
2251
2252                 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2253                         break;
2254
2255                 if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0)
2256                         continue;
2257
2258                 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
2259                         struct switchdev_obj_port_fdb *fdb;
2260
2261                         if (!is_unicast_ether_addr(addr.mac))
2262                                 continue;
2263
2264                         fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
2265                         fdb->vid = vid;
2266                         ether_addr_copy(fdb->addr, addr.mac);
2267                         if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2268                                 fdb->ndm_state = NUD_NOARP;
2269                         else
2270                                 fdb->ndm_state = NUD_REACHABLE;
2271                 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
2272                         struct switchdev_obj_port_mdb *mdb;
2273
2274                         if (!is_multicast_ether_addr(addr.mac))
2275                                 continue;
2276
2277                         mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
2278                         mdb->vid = vid;
2279                         ether_addr_copy(mdb->addr, addr.mac);
2280                 } else {
2281                         return -EOPNOTSUPP;
2282                 }
2283
2284                 err = cb(obj);
2285                 if (err)
2286                         return err;
2287         } while (!is_broadcast_ether_addr(addr.mac));
2288
2289         return err;
2290 }
2291
2292 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2293                                   struct switchdev_obj *obj,
2294                                   int (*cb)(struct switchdev_obj *obj))
2295 {
2296         struct mv88e6xxx_vtu_stu_entry vlan = {
2297                 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2298         };
2299         u16 fid;
2300         int err;
2301
2302         /* Dump port's default Filtering Information Database (VLAN ID 0) */
2303         err = _mv88e6xxx_port_fid_get(chip, port, &fid);
2304         if (err)
2305                 return err;
2306
2307         err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2308         if (err)
2309                 return err;
2310
2311         /* Dump VLANs' Filtering Information Databases */
2312         err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
2313         if (err)
2314                 return err;
2315
2316         do {
2317                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
2318                 if (err)
2319                         return err;
2320
2321                 if (!vlan.valid)
2322                         break;
2323
2324                 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2325                                                  obj, cb);
2326                 if (err)
2327                         return err;
2328         } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2329
2330         return err;
2331 }
2332
2333 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2334                                    struct switchdev_obj_port_fdb *fdb,
2335                                    int (*cb)(struct switchdev_obj *obj))
2336 {
2337         struct mv88e6xxx_chip *chip = ds->priv;
2338         int err;
2339
2340         mutex_lock(&chip->reg_lock);
2341         err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
2342         mutex_unlock(&chip->reg_lock);
2343
2344         return err;
2345 }
2346
2347 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2348                                       struct net_device *bridge)
2349 {
2350         struct mv88e6xxx_chip *chip = ds->priv;
2351         int i, err = 0;
2352
2353         mutex_lock(&chip->reg_lock);
2354
2355         /* Assign the bridge and remap each port's VLANTable */
2356         chip->ports[port].bridge_dev = bridge;
2357
2358         for (i = 0; i < chip->info->num_ports; ++i) {
2359                 if (chip->ports[i].bridge_dev == bridge) {
2360                         err = _mv88e6xxx_port_based_vlan_map(chip, i);
2361                         if (err)
2362                                 break;
2363                 }
2364         }
2365
2366         mutex_unlock(&chip->reg_lock);
2367
2368         return err;
2369 }
2370
2371 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2372 {
2373         struct mv88e6xxx_chip *chip = ds->priv;
2374         struct net_device *bridge = chip->ports[port].bridge_dev;
2375         int i;
2376
2377         mutex_lock(&chip->reg_lock);
2378
2379         /* Unassign the bridge and remap each port's VLANTable */
2380         chip->ports[port].bridge_dev = NULL;
2381
2382         for (i = 0; i < chip->info->num_ports; ++i)
2383                 if (i == port || chip->ports[i].bridge_dev == bridge)
2384                         if (_mv88e6xxx_port_based_vlan_map(chip, i))
2385                                 netdev_warn(ds->ports[i].netdev,
2386                                             "failed to remap\n");
2387
2388         mutex_unlock(&chip->reg_lock);
2389 }
2390
2391 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2392 {
2393         bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
2394         u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2395         struct gpio_desc *gpiod = chip->reset;
2396         unsigned long timeout;
2397         u16 reg;
2398         int err;
2399         int i;
2400
2401         /* Set all ports to the disabled state. */
2402         for (i = 0; i < chip->info->num_ports; i++) {
2403                 err = mv88e6xxx_port_read(chip, i, PORT_CONTROL, &reg);
2404                 if (err)
2405                         return err;
2406
2407                 err = mv88e6xxx_port_write(chip, i, PORT_CONTROL,
2408                                            reg & 0xfffc);
2409                 if (err)
2410                         return err;
2411         }
2412
2413         /* Wait for transmit queues to drain. */
2414         usleep_range(2000, 4000);
2415
2416         /* If there is a gpio connected to the reset pin, toggle it */
2417         if (gpiod) {
2418                 gpiod_set_value_cansleep(gpiod, 1);
2419                 usleep_range(10000, 20000);
2420                 gpiod_set_value_cansleep(gpiod, 0);
2421                 usleep_range(10000, 20000);
2422         }
2423
2424         /* Reset the switch. Keep the PPU active if requested. The PPU
2425          * needs to be active to support indirect phy register access
2426          * through global registers 0x18 and 0x19.
2427          */
2428         if (ppu_active)
2429                 err = mv88e6xxx_g1_write(chip, 0x04, 0xc000);
2430         else
2431                 err = mv88e6xxx_g1_write(chip, 0x04, 0xc400);
2432         if (err)
2433                 return err;
2434
2435         /* Wait up to one second for reset to complete. */
2436         timeout = jiffies + 1 * HZ;
2437         while (time_before(jiffies, timeout)) {
2438                 err = mv88e6xxx_g1_read(chip, 0x00, &reg);
2439                 if (err)
2440                         return err;
2441
2442                 if ((reg & is_reset) == is_reset)
2443                         break;
2444                 usleep_range(1000, 2000);
2445         }
2446         if (time_after(jiffies, timeout))
2447                 err = -ETIMEDOUT;
2448         else
2449                 err = 0;
2450
2451         return err;
2452 }
2453
2454 static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
2455 {
2456         u16 val;
2457         int err;
2458
2459         /* Clear Power Down bit */
2460         err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2461         if (err)
2462                 return err;
2463
2464         if (val & BMCR_PDOWN) {
2465                 val &= ~BMCR_PDOWN;
2466                 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
2467         }
2468
2469         return err;
2470 }
2471
2472 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2473 {
2474         struct dsa_switch *ds = chip->ds;
2475         int err;
2476         u16 reg;
2477
2478         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2479             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2480             mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2481             mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) {
2482                 /* MAC Forcing register: don't force link, speed,
2483                  * duplex or flow control state to any particular
2484                  * values on physical ports, but force the CPU port
2485                  * and all DSA ports to their maximum bandwidth and
2486                  * full duplex.
2487                  */
2488                 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, &reg);
2489                 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
2490                         reg &= ~PORT_PCS_CTRL_UNFORCED;
2491                         reg |= PORT_PCS_CTRL_FORCE_LINK |
2492                                 PORT_PCS_CTRL_LINK_UP |
2493                                 PORT_PCS_CTRL_DUPLEX_FULL |
2494                                 PORT_PCS_CTRL_FORCE_DUPLEX;
2495                         if (mv88e6xxx_6065_family(chip))
2496                                 reg |= PORT_PCS_CTRL_100;
2497                         else
2498                                 reg |= PORT_PCS_CTRL_1000;
2499                 } else {
2500                         reg |= PORT_PCS_CTRL_UNFORCED;
2501                 }
2502
2503                 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
2504                 if (err)
2505                         return err;
2506         }
2507
2508         /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2509          * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2510          * tunneling, determine priority by looking at 802.1p and IP
2511          * priority fields (IP prio has precedence), and set STP state
2512          * to Forwarding.
2513          *
2514          * If this is the CPU link, use DSA or EDSA tagging depending
2515          * on which tagging mode was configured.
2516          *
2517          * If this is a link to another switch, use DSA tagging mode.
2518          *
2519          * If this is the upstream port for this switch, enable
2520          * forwarding of unknown unicasts and multicasts.
2521          */
2522         reg = 0;
2523         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2524             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2525             mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2526             mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
2527                 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2528                 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2529                 PORT_CONTROL_STATE_FORWARDING;
2530         if (dsa_is_cpu_port(ds, port)) {
2531                 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
2532                         reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
2533                                 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2534                 else
2535                         reg |= PORT_CONTROL_DSA_TAG;
2536                 reg |= PORT_CONTROL_EGRESS_ADD_TAG |
2537                         PORT_CONTROL_FORWARD_UNKNOWN;
2538         }
2539         if (dsa_is_dsa_port(ds, port)) {
2540                 if (mv88e6xxx_6095_family(chip) ||
2541                     mv88e6xxx_6185_family(chip))
2542                         reg |= PORT_CONTROL_DSA_TAG;
2543                 if (mv88e6xxx_6352_family(chip) ||
2544                     mv88e6xxx_6351_family(chip) ||
2545                     mv88e6xxx_6165_family(chip) ||
2546                     mv88e6xxx_6097_family(chip) ||
2547                     mv88e6xxx_6320_family(chip)) {
2548                         reg |= PORT_CONTROL_FRAME_MODE_DSA;
2549                 }
2550
2551                 if (port == dsa_upstream_port(ds))
2552                         reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2553                                 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2554         }
2555         if (reg) {
2556                 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
2557                 if (err)
2558                         return err;
2559         }
2560
2561         /* If this port is connected to a SerDes, make sure the SerDes is not
2562          * powered down.
2563          */
2564         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
2565                 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
2566                 if (err)
2567                         return err;
2568                 reg &= PORT_STATUS_CMODE_MASK;
2569                 if ((reg == PORT_STATUS_CMODE_100BASE_X) ||
2570                     (reg == PORT_STATUS_CMODE_1000BASE_X) ||
2571                     (reg == PORT_STATUS_CMODE_SGMII)) {
2572                         err = mv88e6xxx_serdes_power_on(chip);
2573                         if (err < 0)
2574                                 return err;
2575                 }
2576         }
2577
2578         /* Port Control 2: don't force a good FCS, set the maximum frame size to
2579          * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2580          * untagged frames on this port, do a destination address lookup on all
2581          * received packets as usual, disable ARP mirroring and don't send a
2582          * copy of all transmitted/received frames on this port to the CPU.
2583          */
2584         reg = 0;
2585         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2586             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2587             mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2588             mv88e6xxx_6185_family(chip))
2589                 reg = PORT_CONTROL_2_MAP_DA;
2590
2591         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2592             mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
2593                 reg |= PORT_CONTROL_2_JUMBO_10240;
2594
2595         if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
2596                 /* Set the upstream port this port should use */
2597                 reg |= dsa_upstream_port(ds);
2598                 /* enable forwarding of unknown multicast addresses to
2599                  * the upstream port
2600                  */
2601                 if (port == dsa_upstream_port(ds))
2602                         reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2603         }
2604
2605         reg |= PORT_CONTROL_2_8021Q_DISABLED;
2606
2607         if (reg) {
2608                 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
2609                 if (err)
2610                         return err;
2611         }
2612
2613         /* Port Association Vector: when learning source addresses
2614          * of packets, add the address to the address database using
2615          * a port bitmap that has only the bit for this port set and
2616          * the other bits clear.
2617          */
2618         reg = 1 << port;
2619         /* Disable learning for CPU port */
2620         if (dsa_is_cpu_port(ds, port))
2621                 reg = 0;
2622
2623         err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
2624         if (err)
2625                 return err;
2626
2627         /* Egress rate control 2: disable egress rate control. */
2628         err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
2629         if (err)
2630                 return err;
2631
2632         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2633             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2634             mv88e6xxx_6320_family(chip)) {
2635                 /* Do not limit the period of time that this port can
2636                  * be paused for by the remote end or the period of
2637                  * time that this port can pause the remote end.
2638                  */
2639                 err = mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, 0x0000);
2640                 if (err)
2641                         return err;
2642
2643                 /* Port ATU control: disable limiting the number of
2644                  * address database entries that this port is allowed
2645                  * to use.
2646                  */
2647                 err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL,
2648                                            0x0000);
2649                 /* Priority Override: disable DA, SA and VTU priority
2650                  * override.
2651                  */
2652                 err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE,
2653                                            0x0000);
2654                 if (err)
2655                         return err;
2656
2657                 /* Port Ethertype: use the Ethertype DSA Ethertype
2658                  * value.
2659                  */
2660                 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) {
2661                         err = mv88e6xxx_port_write(chip, port, PORT_ETH_TYPE,
2662                                                    ETH_P_EDSA);
2663                         if (err)
2664                                 return err;
2665                 }
2666
2667                 /* Tag Remap: use an identity 802.1p prio -> switch
2668                  * prio mapping.
2669                  */
2670                 err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_0123,
2671                                            0x3210);
2672                 if (err)
2673                         return err;
2674
2675                 /* Tag Remap 2: use an identity 802.1p prio -> switch
2676                  * prio mapping.
2677                  */
2678                 err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_4567,
2679                                            0x7654);
2680                 if (err)
2681                         return err;
2682         }
2683
2684         /* Rate Control: disable ingress rate limiting. */
2685         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2686             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2687             mv88e6xxx_6320_family(chip)) {
2688                 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL,
2689                                            0x0001);
2690                 if (err)
2691                         return err;
2692         } else if (mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip)) {
2693                 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL,
2694                                            0x0000);
2695                 if (err)
2696                         return err;
2697         }
2698
2699         /* Port Control 1: disable trunking, disable sending
2700          * learning messages to this port.
2701          */
2702         err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, 0x0000);
2703         if (err)
2704                 return err;
2705
2706         /* Port based VLAN map: give each port the same default address
2707          * database, and allow bidirectional communication between the
2708          * CPU and DSA port(s), and the other ports.
2709          */
2710         err = _mv88e6xxx_port_fid_set(chip, port, 0);
2711         if (err)
2712                 return err;
2713
2714         err = _mv88e6xxx_port_based_vlan_map(chip, port);
2715         if (err)
2716                 return err;
2717
2718         /* Default VLAN ID and priority: don't set a default VLAN
2719          * ID, and set the default packet priority to zero.
2720          */
2721         return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
2722 }
2723
2724 int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2725 {
2726         int err;
2727
2728         err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
2729         if (err)
2730                 return err;
2731
2732         err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
2733         if (err)
2734                 return err;
2735
2736         err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2737         if (err)
2738                 return err;
2739
2740         return 0;
2741 }
2742
2743 static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2744                                      unsigned int msecs)
2745 {
2746         const unsigned int coeff = chip->info->age_time_coeff;
2747         const unsigned int min = 0x01 * coeff;
2748         const unsigned int max = 0xff * coeff;
2749         u8 age_time;
2750         u16 val;
2751         int err;
2752
2753         if (msecs < min || msecs > max)
2754                 return -ERANGE;
2755
2756         /* Round to nearest multiple of coeff */
2757         age_time = (msecs + coeff / 2) / coeff;
2758
2759         err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
2760         if (err)
2761                 return err;
2762
2763         /* AgeTime is 11:4 bits */
2764         val &= ~0xff0;
2765         val |= age_time << 4;
2766
2767         return mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val);
2768 }
2769
2770 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2771                                      unsigned int ageing_time)
2772 {
2773         struct mv88e6xxx_chip *chip = ds->priv;
2774         int err;
2775
2776         mutex_lock(&chip->reg_lock);
2777         err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2778         mutex_unlock(&chip->reg_lock);
2779
2780         return err;
2781 }
2782
2783 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
2784 {
2785         struct dsa_switch *ds = chip->ds;
2786         u32 upstream_port = dsa_upstream_port(ds);
2787         u16 reg;
2788         int err;
2789
2790         /* Enable the PHY Polling Unit if present, don't discard any packets,
2791          * and mask all interrupt sources.
2792          */
2793         reg = 0;
2794         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
2795             mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
2796                 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2797
2798         err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
2799         if (err)
2800                 return err;
2801
2802         /* Configure the upstream port, and configure it as the port to which
2803          * ingress and egress and ARP monitor frames are to be sent.
2804          */
2805         reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2806                 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2807                 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
2808         err = mv88e6xxx_g1_write(chip, GLOBAL_MONITOR_CONTROL, reg);
2809         if (err)
2810                 return err;
2811
2812         /* Disable remote management, and set the switch's DSA device number. */
2813         err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
2814                                  GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2815                                  (ds->index & 0x1f));
2816         if (err)
2817                 return err;
2818
2819         /* Clear all the VTU and STU entries */
2820         err = _mv88e6xxx_vtu_stu_flush(chip);
2821         if (err < 0)
2822                 return err;
2823
2824         /* Set the default address aging time to 5 minutes, and
2825          * enable address learn messages to be sent to all message
2826          * ports.
2827          */
2828         err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
2829                                  GLOBAL_ATU_CONTROL_LEARN2ALL);
2830         if (err)
2831                 return err;
2832
2833         err = mv88e6xxx_g1_set_age_time(chip, 300000);
2834         if (err)
2835                 return err;
2836
2837         /* Clear all ATU entries */
2838         err = _mv88e6xxx_atu_flush(chip, 0, true);
2839         if (err)
2840                 return err;
2841
2842         /* Configure the IP ToS mapping registers. */
2843         err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
2844         if (err)
2845                 return err;
2846         err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
2847         if (err)
2848                 return err;
2849         err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
2850         if (err)
2851                 return err;
2852         err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
2853         if (err)
2854                 return err;
2855         err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
2856         if (err)
2857                 return err;
2858         err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
2859         if (err)
2860                 return err;
2861         err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
2862         if (err)
2863                 return err;
2864         err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
2865         if (err)
2866                 return err;
2867
2868         /* Configure the IEEE 802.1p priority mapping register. */
2869         err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
2870         if (err)
2871                 return err;
2872
2873         /* Clear the statistics counters for all ports */
2874         err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
2875                                  GLOBAL_STATS_OP_FLUSH_ALL);
2876         if (err)
2877                 return err;
2878
2879         /* Wait for the flush to complete. */
2880         err = _mv88e6xxx_stats_wait(chip);
2881         if (err)
2882                 return err;
2883
2884         return 0;
2885 }
2886
2887 static int mv88e6xxx_setup(struct dsa_switch *ds)
2888 {
2889         struct mv88e6xxx_chip *chip = ds->priv;
2890         int err;
2891         int i;
2892
2893         chip->ds = ds;
2894         ds->slave_mii_bus = chip->mdio_bus;
2895
2896         mutex_lock(&chip->reg_lock);
2897
2898         err = mv88e6xxx_switch_reset(chip);
2899         if (err)
2900                 goto unlock;
2901
2902         /* Setup Switch Port Registers */
2903         for (i = 0; i < chip->info->num_ports; i++) {
2904                 err = mv88e6xxx_setup_port(chip, i);
2905                 if (err)
2906                         goto unlock;
2907         }
2908
2909         /* Setup Switch Global 1 Registers */
2910         err = mv88e6xxx_g1_setup(chip);
2911         if (err)
2912                 goto unlock;
2913
2914         /* Setup Switch Global 2 Registers */
2915         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2916                 err = mv88e6xxx_g2_setup(chip);
2917                 if (err)
2918                         goto unlock;
2919         }
2920
2921 unlock:
2922         mutex_unlock(&chip->reg_lock);
2923
2924         return err;
2925 }
2926
2927 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2928 {
2929         struct mv88e6xxx_chip *chip = ds->priv;
2930         int err;
2931
2932         mutex_lock(&chip->reg_lock);
2933
2934         /* Has an indirect Switch MAC/WoL/WoF register in Global 2? */
2935         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_SWITCH_MAC))
2936                 err = mv88e6xxx_g2_set_switch_mac(chip, addr);
2937         else
2938                 err = mv88e6xxx_g1_set_switch_mac(chip, addr);
2939
2940         mutex_unlock(&chip->reg_lock);
2941
2942         return err;
2943 }
2944
2945 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2946 {
2947         struct mv88e6xxx_chip *chip = bus->priv;
2948         u16 val;
2949         int err;
2950
2951         if (phy >= chip->info->num_ports)
2952                 return 0xffff;
2953
2954         mutex_lock(&chip->reg_lock);
2955         err = mv88e6xxx_phy_read(chip, phy, reg, &val);
2956         mutex_unlock(&chip->reg_lock);
2957
2958         return err ? err : val;
2959 }
2960
2961 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2962 {
2963         struct mv88e6xxx_chip *chip = bus->priv;
2964         int err;
2965
2966         if (phy >= chip->info->num_ports)
2967                 return 0xffff;
2968
2969         mutex_lock(&chip->reg_lock);
2970         err = mv88e6xxx_phy_write(chip, phy, reg, val);
2971         mutex_unlock(&chip->reg_lock);
2972
2973         return err;
2974 }
2975
2976 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2977                                    struct device_node *np)
2978 {
2979         static int index;
2980         struct mii_bus *bus;
2981         int err;
2982
2983         if (np)
2984                 chip->mdio_np = of_get_child_by_name(np, "mdio");
2985
2986         bus = devm_mdiobus_alloc(chip->dev);
2987         if (!bus)
2988                 return -ENOMEM;
2989
2990         bus->priv = (void *)chip;
2991         if (np) {
2992                 bus->name = np->full_name;
2993                 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2994         } else {
2995                 bus->name = "mv88e6xxx SMI";
2996                 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2997         }
2998
2999         bus->read = mv88e6xxx_mdio_read;
3000         bus->write = mv88e6xxx_mdio_write;
3001         bus->parent = chip->dev;
3002
3003         if (chip->mdio_np)
3004                 err = of_mdiobus_register(bus, chip->mdio_np);
3005         else
3006                 err = mdiobus_register(bus);
3007         if (err) {
3008                 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3009                 goto out;
3010         }
3011         chip->mdio_bus = bus;
3012
3013         return 0;
3014
3015 out:
3016         if (chip->mdio_np)
3017                 of_node_put(chip->mdio_np);
3018
3019         return err;
3020 }
3021
3022 static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
3023
3024 {
3025         struct mii_bus *bus = chip->mdio_bus;
3026
3027         mdiobus_unregister(bus);
3028
3029         if (chip->mdio_np)
3030                 of_node_put(chip->mdio_np);
3031 }
3032
3033 #ifdef CONFIG_NET_DSA_HWMON
3034
3035 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3036 {
3037         struct mv88e6xxx_chip *chip = ds->priv;
3038         u16 val;
3039         int ret;
3040
3041         *temp = 0;
3042
3043         mutex_lock(&chip->reg_lock);
3044
3045         ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6);
3046         if (ret < 0)
3047                 goto error;
3048
3049         /* Enable temperature sensor */
3050         ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
3051         if (ret < 0)
3052                 goto error;
3053
3054         ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5));
3055         if (ret < 0)
3056                 goto error;
3057
3058         /* Wait for temperature to stabilize */
3059         usleep_range(10000, 12000);
3060
3061         ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
3062         if (ret < 0)
3063                 goto error;
3064
3065         /* Disable temperature sensor */
3066         ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5));
3067         if (ret < 0)
3068                 goto error;
3069
3070         *temp = ((val & 0x1f) - 5) * 5;
3071
3072 error:
3073         mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0);
3074         mutex_unlock(&chip->reg_lock);
3075         return ret;
3076 }
3077
3078 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3079 {
3080         struct mv88e6xxx_chip *chip = ds->priv;
3081         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3082         u16 val;
3083         int ret;
3084
3085         *temp = 0;
3086
3087         mutex_lock(&chip->reg_lock);
3088         ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val);
3089         mutex_unlock(&chip->reg_lock);
3090         if (ret < 0)
3091                 return ret;
3092
3093         *temp = (val & 0xff) - 25;
3094
3095         return 0;
3096 }
3097
3098 static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3099 {
3100         struct mv88e6xxx_chip *chip = ds->priv;
3101
3102         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
3103                 return -EOPNOTSUPP;
3104
3105         if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
3106                 return mv88e63xx_get_temp(ds, temp);
3107
3108         return mv88e61xx_get_temp(ds, temp);
3109 }
3110
3111 static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3112 {
3113         struct mv88e6xxx_chip *chip = ds->priv;
3114         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3115         u16 val;
3116         int ret;
3117
3118         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3119                 return -EOPNOTSUPP;
3120
3121         *temp = 0;
3122
3123         mutex_lock(&chip->reg_lock);
3124         ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3125         mutex_unlock(&chip->reg_lock);
3126         if (ret < 0)
3127                 return ret;
3128
3129         *temp = (((val >> 8) & 0x1f) * 5) - 25;
3130
3131         return 0;
3132 }
3133
3134 static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3135 {
3136         struct mv88e6xxx_chip *chip = ds->priv;
3137         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3138         u16 val;
3139         int err;
3140
3141         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3142                 return -EOPNOTSUPP;
3143
3144         mutex_lock(&chip->reg_lock);
3145         err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3146         if (err)
3147                 goto unlock;
3148         temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3149         err = mv88e6xxx_phy_page_write(chip, phy, 6, 26,
3150                                        (val & 0xe0ff) | (temp << 8));
3151 unlock:
3152         mutex_unlock(&chip->reg_lock);
3153
3154         return err;
3155 }
3156
3157 static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3158 {
3159         struct mv88e6xxx_chip *chip = ds->priv;
3160         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3161         u16 val;
3162         int ret;
3163
3164         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3165                 return -EOPNOTSUPP;
3166
3167         *alarm = false;
3168
3169         mutex_lock(&chip->reg_lock);
3170         ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3171         mutex_unlock(&chip->reg_lock);
3172         if (ret < 0)
3173                 return ret;
3174
3175         *alarm = !!(val & 0x40);
3176
3177         return 0;
3178 }
3179 #endif /* CONFIG_NET_DSA_HWMON */
3180
3181 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3182 {
3183         struct mv88e6xxx_chip *chip = ds->priv;
3184
3185         return chip->eeprom_len;
3186 }
3187
3188 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3189                                 struct ethtool_eeprom *eeprom, u8 *data)
3190 {
3191         struct mv88e6xxx_chip *chip = ds->priv;
3192         int err;
3193
3194         mutex_lock(&chip->reg_lock);
3195
3196         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3197                 err = mv88e6xxx_g2_get_eeprom16(chip, eeprom, data);
3198         else
3199                 err = -EOPNOTSUPP;
3200
3201         mutex_unlock(&chip->reg_lock);
3202
3203         if (err)
3204                 return err;
3205
3206         eeprom->magic = 0xc3ec4951;
3207
3208         return 0;
3209 }
3210
3211 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3212                                 struct ethtool_eeprom *eeprom, u8 *data)
3213 {
3214         struct mv88e6xxx_chip *chip = ds->priv;
3215         int err;
3216
3217         if (eeprom->magic != 0xc3ec4951)
3218                 return -EINVAL;
3219
3220         mutex_lock(&chip->reg_lock);
3221
3222         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3223                 err = mv88e6xxx_g2_set_eeprom16(chip, eeprom, data);
3224         else
3225                 err = -EOPNOTSUPP;
3226
3227         mutex_unlock(&chip->reg_lock);
3228
3229         return err;
3230 }
3231
3232 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3233         [MV88E6085] = {
3234                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3235                 .family = MV88E6XXX_FAMILY_6097,
3236                 .name = "Marvell 88E6085",
3237                 .num_databases = 4096,
3238                 .num_ports = 10,
3239                 .port_base_addr = 0x10,
3240                 .global1_addr = 0x1b,
3241                 .age_time_coeff = 15000,
3242                 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3243         },
3244
3245         [MV88E6095] = {
3246                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3247                 .family = MV88E6XXX_FAMILY_6095,
3248                 .name = "Marvell 88E6095/88E6095F",
3249                 .num_databases = 256,
3250                 .num_ports = 11,
3251                 .port_base_addr = 0x10,
3252                 .global1_addr = 0x1b,
3253                 .age_time_coeff = 15000,
3254                 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3255         },
3256
3257         [MV88E6123] = {
3258                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3259                 .family = MV88E6XXX_FAMILY_6165,
3260                 .name = "Marvell 88E6123",
3261                 .num_databases = 4096,
3262                 .num_ports = 3,
3263                 .port_base_addr = 0x10,
3264                 .global1_addr = 0x1b,
3265                 .age_time_coeff = 15000,
3266                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3267         },
3268
3269         [MV88E6131] = {
3270                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3271                 .family = MV88E6XXX_FAMILY_6185,
3272                 .name = "Marvell 88E6131",
3273                 .num_databases = 256,
3274                 .num_ports = 8,
3275                 .port_base_addr = 0x10,
3276                 .global1_addr = 0x1b,
3277                 .age_time_coeff = 15000,
3278                 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3279         },
3280
3281         [MV88E6161] = {
3282                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3283                 .family = MV88E6XXX_FAMILY_6165,
3284                 .name = "Marvell 88E6161",
3285                 .num_databases = 4096,
3286                 .num_ports = 6,
3287                 .port_base_addr = 0x10,
3288                 .global1_addr = 0x1b,
3289                 .age_time_coeff = 15000,
3290                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3291         },
3292
3293         [MV88E6165] = {
3294                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3295                 .family = MV88E6XXX_FAMILY_6165,
3296                 .name = "Marvell 88E6165",
3297                 .num_databases = 4096,
3298                 .num_ports = 6,
3299                 .port_base_addr = 0x10,
3300                 .global1_addr = 0x1b,
3301                 .age_time_coeff = 15000,
3302                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3303         },
3304
3305         [MV88E6171] = {
3306                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3307                 .family = MV88E6XXX_FAMILY_6351,
3308                 .name = "Marvell 88E6171",
3309                 .num_databases = 4096,
3310                 .num_ports = 7,
3311                 .port_base_addr = 0x10,
3312                 .global1_addr = 0x1b,
3313                 .age_time_coeff = 15000,
3314                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3315         },
3316
3317         [MV88E6172] = {
3318                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3319                 .family = MV88E6XXX_FAMILY_6352,
3320                 .name = "Marvell 88E6172",
3321                 .num_databases = 4096,
3322                 .num_ports = 7,
3323                 .port_base_addr = 0x10,
3324                 .global1_addr = 0x1b,
3325                 .age_time_coeff = 15000,
3326                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3327         },
3328
3329         [MV88E6175] = {
3330                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3331                 .family = MV88E6XXX_FAMILY_6351,
3332                 .name = "Marvell 88E6175",
3333                 .num_databases = 4096,
3334                 .num_ports = 7,
3335                 .port_base_addr = 0x10,
3336                 .global1_addr = 0x1b,
3337                 .age_time_coeff = 15000,
3338                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3339         },
3340
3341         [MV88E6176] = {
3342                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3343                 .family = MV88E6XXX_FAMILY_6352,
3344                 .name = "Marvell 88E6176",
3345                 .num_databases = 4096,
3346                 .num_ports = 7,
3347                 .port_base_addr = 0x10,
3348                 .global1_addr = 0x1b,
3349                 .age_time_coeff = 15000,
3350                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3351         },
3352
3353         [MV88E6185] = {
3354                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3355                 .family = MV88E6XXX_FAMILY_6185,
3356                 .name = "Marvell 88E6185",
3357                 .num_databases = 256,
3358                 .num_ports = 10,
3359                 .port_base_addr = 0x10,
3360                 .global1_addr = 0x1b,
3361                 .age_time_coeff = 15000,
3362                 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3363         },
3364
3365         [MV88E6240] = {
3366                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3367                 .family = MV88E6XXX_FAMILY_6352,
3368                 .name = "Marvell 88E6240",
3369                 .num_databases = 4096,
3370                 .num_ports = 7,
3371                 .port_base_addr = 0x10,
3372                 .global1_addr = 0x1b,
3373                 .age_time_coeff = 15000,
3374                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3375         },
3376
3377         [MV88E6320] = {
3378                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3379                 .family = MV88E6XXX_FAMILY_6320,
3380                 .name = "Marvell 88E6320",
3381                 .num_databases = 4096,
3382                 .num_ports = 7,
3383                 .port_base_addr = 0x10,
3384                 .global1_addr = 0x1b,
3385                 .age_time_coeff = 15000,
3386                 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3387         },
3388
3389         [MV88E6321] = {
3390                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3391                 .family = MV88E6XXX_FAMILY_6320,
3392                 .name = "Marvell 88E6321",
3393                 .num_databases = 4096,
3394                 .num_ports = 7,
3395                 .port_base_addr = 0x10,
3396                 .global1_addr = 0x1b,
3397                 .age_time_coeff = 15000,
3398                 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3399         },
3400
3401         [MV88E6350] = {
3402                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3403                 .family = MV88E6XXX_FAMILY_6351,
3404                 .name = "Marvell 88E6350",
3405                 .num_databases = 4096,
3406                 .num_ports = 7,
3407                 .port_base_addr = 0x10,
3408                 .global1_addr = 0x1b,
3409                 .age_time_coeff = 15000,
3410                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3411         },
3412
3413         [MV88E6351] = {
3414                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3415                 .family = MV88E6XXX_FAMILY_6351,
3416                 .name = "Marvell 88E6351",
3417                 .num_databases = 4096,
3418                 .num_ports = 7,
3419                 .port_base_addr = 0x10,
3420                 .global1_addr = 0x1b,
3421                 .age_time_coeff = 15000,
3422                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3423         },
3424
3425         [MV88E6352] = {
3426                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3427                 .family = MV88E6XXX_FAMILY_6352,
3428                 .name = "Marvell 88E6352",
3429                 .num_databases = 4096,
3430                 .num_ports = 7,
3431                 .port_base_addr = 0x10,
3432                 .global1_addr = 0x1b,
3433                 .age_time_coeff = 15000,
3434                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3435         },
3436 };
3437
3438 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3439 {
3440         int i;
3441
3442         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3443                 if (mv88e6xxx_table[i].prod_num == prod_num)
3444                         return &mv88e6xxx_table[i];
3445
3446         return NULL;
3447 }
3448
3449 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3450 {
3451         const struct mv88e6xxx_info *info;
3452         unsigned int prod_num, rev;
3453         u16 id;
3454         int err;
3455
3456         mutex_lock(&chip->reg_lock);
3457         err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
3458         mutex_unlock(&chip->reg_lock);
3459         if (err)
3460                 return err;
3461
3462         prod_num = (id & 0xfff0) >> 4;
3463         rev = id & 0x000f;
3464
3465         info = mv88e6xxx_lookup_info(prod_num);
3466         if (!info)
3467                 return -ENODEV;
3468
3469         /* Update the compatible info with the probed one */
3470         chip->info = info;
3471
3472         err = mv88e6xxx_g2_require(chip);
3473         if (err)
3474                 return err;
3475
3476         dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3477                  chip->info->prod_num, chip->info->name, rev);
3478
3479         return 0;
3480 }
3481
3482 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3483 {
3484         struct mv88e6xxx_chip *chip;
3485
3486         chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3487         if (!chip)
3488                 return NULL;
3489
3490         chip->dev = dev;
3491
3492         mutex_init(&chip->reg_lock);
3493
3494         return chip;
3495 }
3496
3497 static const struct mv88e6xxx_ops mv88e6xxx_g2_smi_phy_ops = {
3498         .read = mv88e6xxx_g2_smi_phy_read,
3499         .write = mv88e6xxx_g2_smi_phy_write,
3500 };
3501
3502 static const struct mv88e6xxx_ops mv88e6xxx_phy_ops = {
3503         .read = mv88e6xxx_read,
3504         .write = mv88e6xxx_write,
3505 };
3506
3507 static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
3508 {
3509         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SMI_PHY)) {
3510                 chip->phy_ops = &mv88e6xxx_g2_smi_phy_ops;
3511         } else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) {
3512                 chip->phy_ops = &mv88e6xxx_phy_ppu_ops;
3513                 mv88e6xxx_ppu_state_init(chip);
3514         } else {
3515                 chip->phy_ops = &mv88e6xxx_phy_ops;
3516         }
3517 }
3518
3519 static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
3520 {
3521         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) {
3522                 mv88e6xxx_ppu_state_destroy(chip);
3523         }
3524 }
3525
3526 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
3527                               struct mii_bus *bus, int sw_addr)
3528 {
3529         /* ADDR[0] pin is unavailable externally and considered zero */
3530         if (sw_addr & 0x1)
3531                 return -EINVAL;
3532
3533         if (sw_addr == 0)
3534                 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3535         else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
3536                 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
3537         else
3538                 return -EINVAL;
3539
3540         chip->bus = bus;
3541         chip->sw_addr = sw_addr;
3542
3543         return 0;
3544 }
3545
3546 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
3547 {
3548         struct mv88e6xxx_chip *chip = ds->priv;
3549
3550         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
3551                 return DSA_TAG_PROTO_EDSA;
3552
3553         return DSA_TAG_PROTO_DSA;
3554 }
3555
3556 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3557                                        struct device *host_dev, int sw_addr,
3558                                        void **priv)
3559 {
3560         struct mv88e6xxx_chip *chip;
3561         struct mii_bus *bus;
3562         int err;
3563
3564         bus = dsa_host_dev_to_mii_bus(host_dev);
3565         if (!bus)
3566                 return NULL;
3567
3568         chip = mv88e6xxx_alloc_chip(dsa_dev);
3569         if (!chip)
3570                 return NULL;
3571
3572         /* Legacy SMI probing will only support chips similar to 88E6085 */
3573         chip->info = &mv88e6xxx_table[MV88E6085];
3574
3575         err = mv88e6xxx_smi_init(chip, bus, sw_addr);
3576         if (err)
3577                 goto free;
3578
3579         err = mv88e6xxx_detect(chip);
3580         if (err)
3581                 goto free;
3582
3583         mv88e6xxx_phy_init(chip);
3584
3585         err = mv88e6xxx_mdio_register(chip, NULL);
3586         if (err)
3587                 goto free;
3588
3589         *priv = chip;
3590
3591         return chip->info->name;
3592 free:
3593         devm_kfree(dsa_dev, chip);
3594
3595         return NULL;
3596 }
3597
3598 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
3599                                       const struct switchdev_obj_port_mdb *mdb,
3600                                       struct switchdev_trans *trans)
3601 {
3602         /* We don't need any dynamic resource from the kernel (yet),
3603          * so skip the prepare phase.
3604          */
3605
3606         return 0;
3607 }
3608
3609 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
3610                                    const struct switchdev_obj_port_mdb *mdb,
3611                                    struct switchdev_trans *trans)
3612 {
3613         struct mv88e6xxx_chip *chip = ds->priv;
3614
3615         mutex_lock(&chip->reg_lock);
3616         if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3617                                          GLOBAL_ATU_DATA_STATE_MC_STATIC))
3618                 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
3619         mutex_unlock(&chip->reg_lock);
3620 }
3621
3622 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
3623                                   const struct switchdev_obj_port_mdb *mdb)
3624 {
3625         struct mv88e6xxx_chip *chip = ds->priv;
3626         int err;
3627
3628         mutex_lock(&chip->reg_lock);
3629         err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3630                                            GLOBAL_ATU_DATA_STATE_UNUSED);
3631         mutex_unlock(&chip->reg_lock);
3632
3633         return err;
3634 }
3635
3636 static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
3637                                    struct switchdev_obj_port_mdb *mdb,
3638                                    int (*cb)(struct switchdev_obj *obj))
3639 {
3640         struct mv88e6xxx_chip *chip = ds->priv;
3641         int err;
3642
3643         mutex_lock(&chip->reg_lock);
3644         err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
3645         mutex_unlock(&chip->reg_lock);
3646
3647         return err;
3648 }
3649
3650 static struct dsa_switch_ops mv88e6xxx_switch_ops = {
3651         .probe                  = mv88e6xxx_drv_probe,
3652         .get_tag_protocol       = mv88e6xxx_get_tag_protocol,
3653         .setup                  = mv88e6xxx_setup,
3654         .set_addr               = mv88e6xxx_set_addr,
3655         .adjust_link            = mv88e6xxx_adjust_link,
3656         .get_strings            = mv88e6xxx_get_strings,
3657         .get_ethtool_stats      = mv88e6xxx_get_ethtool_stats,
3658         .get_sset_count         = mv88e6xxx_get_sset_count,
3659         .set_eee                = mv88e6xxx_set_eee,
3660         .get_eee                = mv88e6xxx_get_eee,
3661 #ifdef CONFIG_NET_DSA_HWMON
3662         .get_temp               = mv88e6xxx_get_temp,
3663         .get_temp_limit         = mv88e6xxx_get_temp_limit,
3664         .set_temp_limit         = mv88e6xxx_set_temp_limit,
3665         .get_temp_alarm         = mv88e6xxx_get_temp_alarm,
3666 #endif
3667         .get_eeprom_len         = mv88e6xxx_get_eeprom_len,
3668         .get_eeprom             = mv88e6xxx_get_eeprom,
3669         .set_eeprom             = mv88e6xxx_set_eeprom,
3670         .get_regs_len           = mv88e6xxx_get_regs_len,
3671         .get_regs               = mv88e6xxx_get_regs,
3672         .set_ageing_time        = mv88e6xxx_set_ageing_time,
3673         .port_bridge_join       = mv88e6xxx_port_bridge_join,
3674         .port_bridge_leave      = mv88e6xxx_port_bridge_leave,
3675         .port_stp_state_set     = mv88e6xxx_port_stp_state_set,
3676         .port_fast_age          = mv88e6xxx_port_fast_age,
3677         .port_vlan_filtering    = mv88e6xxx_port_vlan_filtering,
3678         .port_vlan_prepare      = mv88e6xxx_port_vlan_prepare,
3679         .port_vlan_add          = mv88e6xxx_port_vlan_add,
3680         .port_vlan_del          = mv88e6xxx_port_vlan_del,
3681         .port_vlan_dump         = mv88e6xxx_port_vlan_dump,
3682         .port_fdb_prepare       = mv88e6xxx_port_fdb_prepare,
3683         .port_fdb_add           = mv88e6xxx_port_fdb_add,
3684         .port_fdb_del           = mv88e6xxx_port_fdb_del,
3685         .port_fdb_dump          = mv88e6xxx_port_fdb_dump,
3686         .port_mdb_prepare       = mv88e6xxx_port_mdb_prepare,
3687         .port_mdb_add           = mv88e6xxx_port_mdb_add,
3688         .port_mdb_del           = mv88e6xxx_port_mdb_del,
3689         .port_mdb_dump          = mv88e6xxx_port_mdb_dump,
3690 };
3691
3692 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
3693                                      struct device_node *np)
3694 {
3695         struct device *dev = chip->dev;
3696         struct dsa_switch *ds;
3697
3698         ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
3699         if (!ds)
3700                 return -ENOMEM;
3701
3702         ds->dev = dev;
3703         ds->priv = chip;
3704         ds->ops = &mv88e6xxx_switch_ops;
3705
3706         dev_set_drvdata(dev, ds);
3707
3708         return dsa_register_switch(ds, np);
3709 }
3710
3711 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
3712 {
3713         dsa_unregister_switch(chip->ds);
3714 }
3715
3716 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
3717 {
3718         struct device *dev = &mdiodev->dev;
3719         struct device_node *np = dev->of_node;
3720         const struct mv88e6xxx_info *compat_info;
3721         struct mv88e6xxx_chip *chip;
3722         u32 eeprom_len;
3723         int err;
3724
3725         compat_info = of_device_get_match_data(dev);
3726         if (!compat_info)
3727                 return -EINVAL;
3728
3729         chip = mv88e6xxx_alloc_chip(dev);
3730         if (!chip)
3731                 return -ENOMEM;
3732
3733         chip->info = compat_info;
3734
3735         err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
3736         if (err)
3737                 return err;
3738
3739         err = mv88e6xxx_detect(chip);
3740         if (err)
3741                 return err;
3742
3743         mv88e6xxx_phy_init(chip);
3744
3745         chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
3746         if (IS_ERR(chip->reset))
3747                 return PTR_ERR(chip->reset);
3748
3749         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16) &&
3750             !of_property_read_u32(np, "eeprom-length", &eeprom_len))
3751                 chip->eeprom_len = eeprom_len;
3752
3753         err = mv88e6xxx_mdio_register(chip, np);
3754         if (err)
3755                 return err;
3756
3757         err = mv88e6xxx_register_switch(chip, np);
3758         if (err) {
3759                 mv88e6xxx_mdio_unregister(chip);
3760                 return err;
3761         }
3762
3763         return 0;
3764 }
3765
3766 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
3767 {
3768         struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
3769         struct mv88e6xxx_chip *chip = ds->priv;
3770
3771         mv88e6xxx_phy_destroy(chip);
3772         mv88e6xxx_unregister_switch(chip);
3773         mv88e6xxx_mdio_unregister(chip);
3774 }
3775
3776 static const struct of_device_id mv88e6xxx_of_match[] = {
3777         {
3778                 .compatible = "marvell,mv88e6085",
3779                 .data = &mv88e6xxx_table[MV88E6085],
3780         },
3781         { /* sentinel */ },
3782 };
3783
3784 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
3785
3786 static struct mdio_driver mv88e6xxx_driver = {
3787         .probe  = mv88e6xxx_probe,
3788         .remove = mv88e6xxx_remove,
3789         .mdiodrv.driver = {
3790                 .name = "mv88e6085",
3791                 .of_match_table = mv88e6xxx_of_match,
3792         },
3793 };
3794
3795 static int __init mv88e6xxx_init(void)
3796 {
3797         register_switch_driver(&mv88e6xxx_switch_ops);
3798         return mdio_driver_register(&mv88e6xxx_driver);
3799 }
3800 module_init(mv88e6xxx_init);
3801
3802 static void __exit mv88e6xxx_cleanup(void)
3803 {
3804         mdio_driver_unregister(&mv88e6xxx_driver);
3805         unregister_switch_driver(&mv88e6xxx_switch_ops);
3806 }
3807 module_exit(mv88e6xxx_cleanup);
3808
3809 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
3810 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
3811 MODULE_LICENSE("GPL");