drivers/net/dsa/mv88e6xxx/chip.c

   1 /*
   2  * Marvell 88e6xxx Ethernet switch single-chip support
   3  *
   4  * Copyright (c) 2008 Marvell Semiconductor
   5  *
   6  * Copyright (c) 2015 CMC Electronics, Inc.
   7  *      Added support for VLAN Table Unit operations
   8  *
   9  * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include <linux/delay.h>
  18 #include <linux/etherdevice.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/if_bridge.h>
  21 #include <linux/jiffies.h>
  22 #include <linux/list.h>
  23 #include <linux/mdio.h>
  24 #include <linux/module.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_mdio.h>
  27 #include <linux/netdevice.h>
  28 #include <linux/gpio/consumer.h>
  29 #include <linux/phy.h>
  30 #include <net/dsa.h>
  31 #include <net/switchdev.h>
  32 #include "mv88e6xxx.h"
  33
  34 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
  35 {
  36         if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
  37                 dev_err(chip->dev, "Switch registers lock not held!\n");
  38                 dump_stack();
  39         }
  40 }
  41
  42 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
  43  * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
  44  *
  45  * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
  46  * is the only device connected to the SMI master. In this mode it responds to
  47  * all 32 possible SMI addresses, and thus maps directly the internal devices.
  48  *
  49  * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
  50  * multiple devices to share the SMI interface. In this mode it responds to only
  51  * 2 registers, used to indirectly access the internal SMI devices.
  52  */
  53
  54 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
  55                               int addr, int reg, u16 *val)
  56 {
  57         if (!chip->smi_ops)
  58                 return -EOPNOTSUPP;
  59
  60         return chip->smi_ops->read(chip, addr, reg, val);
  61 }
  62
  63 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
  64                                int addr, int reg, u16 val)
  65 {
  66         if (!chip->smi_ops)
  67                 return -EOPNOTSUPP;
  68
  69         return chip->smi_ops->write(chip, addr, reg, val);
  70 }
  71
  72 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
  73                                           int addr, int reg, u16 *val)
  74 {
  75         int ret;
  76
  77         ret = mdiobus_read_nested(chip->bus, addr, reg);
  78         if (ret < 0)
  79                 return ret;
  80
  81         *val = ret & 0xffff;
  82
  83         return 0;
  84 }
  85
  86 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
  87                                            int addr, int reg, u16 val)
  88 {
  89         int ret;
  90
  91         ret = mdiobus_write_nested(chip->bus, addr, reg, val);
  92         if (ret < 0)
  93                 return ret;
  94
  95         return 0;
  96 }
  97
  98 static const struct mv88e6xxx_ops mv88e6xxx_smi_single_chip_ops = {
  99         .read = mv88e6xxx_smi_single_chip_read,
 100         .write = mv88e6xxx_smi_single_chip_write,
 101 };
 102
 103 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
 104 {
 105         int ret;
 106         int i;
 107
 108         for (i = 0; i < 16; i++) {
 109                 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
 110                 if (ret < 0)
 111                         return ret;
 112
 113                 if ((ret & SMI_CMD_BUSY) == 0)
 114                         return 0;
 115         }
 116
 117         return -ETIMEDOUT;
 118 }
 119
 120 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
 121                                          int addr, int reg, u16 *val)
 122 {
 123         int ret;
 124
 125         /* Wait for the bus to become free. */
 126         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 127         if (ret < 0)
 128                 return ret;
 129
 130         /* Transmit the read command. */
 131         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
 132                                    SMI_CMD_OP_22_READ | (addr << 5) | reg);
 133         if (ret < 0)
 134                 return ret;
 135
 136         /* Wait for the read command to complete. */
 137         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 138         if (ret < 0)
 139                 return ret;
 140
 141         /* Read the data. */
 142         ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
 143         if (ret < 0)
 144                 return ret;
 145
 146         *val = ret & 0xffff;
 147
 148         return 0;
 149 }
 150
 151 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
 152                                           int addr, int reg, u16 val)
 153 {
 154         int ret;
 155
 156         /* Wait for the bus to become free. */
 157         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 158         if (ret < 0)
 159                 return ret;
 160
 161         /* Transmit the data to write. */
 162         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
 163         if (ret < 0)
 164                 return ret;
 165
 166         /* Transmit the write command. */
 167         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
 168                                    SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
 169         if (ret < 0)
 170                 return ret;
 171
 172         /* Wait for the write command to complete. */
 173         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 174         if (ret < 0)
 175                 return ret;
 176
 177         return 0;
 178 }
 179
 180 static const struct mv88e6xxx_ops mv88e6xxx_smi_multi_chip_ops = {
 181         .read = mv88e6xxx_smi_multi_chip_read,
 182         .write = mv88e6xxx_smi_multi_chip_write,
 183 };
 184
 185 static int mv88e6xxx_read(struct mv88e6xxx_chip *chip,
 186                           int addr, int reg, u16 *val)
 187 {
 188         int err;
 189
 190         assert_reg_lock(chip);
 191
 192         err = mv88e6xxx_smi_read(chip, addr, reg, val);
 193         if (err)
 194                 return err;
 195
 196         dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
 197                 addr, reg, *val);
 198
 199         return 0;
 200 }
 201
 202 static int mv88e6xxx_write(struct mv88e6xxx_chip *chip,
 203                            int addr, int reg, u16 val)
 204 {
 205         int err;
 206
 207         assert_reg_lock(chip);
 208
 209         err = mv88e6xxx_smi_write(chip, addr, reg, val);
 210         if (err)
 211                 return err;
 212
 213         dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
 214                 addr, reg, val);
 215
 216         return 0;
 217 }
 218
 219 /* Indirect write to single pointer-data register with an Update bit */
 220 static int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
 221                             u16 update)
 222 {
 223         u16 val;
 224         int i, err;
 225
 226         /* Wait until the previous operation is completed */
 227         for (i = 0; i < 16; ++i) {
 228                 err = mv88e6xxx_read(chip, addr, reg, &val);
 229                 if (err)
 230                         return err;
 231
 232                 if (!(val & BIT(15)))
 233                         break;
 234         }
 235
 236         if (i == 16)
 237                 return -ETIMEDOUT;
 238
 239         /* Set the Update bit to trigger a write operation */
 240         val = BIT(15) | update;
 241
 242         return mv88e6xxx_write(chip, addr, reg, val);
 243 }
 244
 245 static int _mv88e6xxx_reg_read(struct mv88e6xxx_chip *chip, int addr, int reg)
 246 {
 247         u16 val;
 248         int err;
 249
 250         err = mv88e6xxx_read(chip, addr, reg, &val);
 251         if (err)
 252                 return err;
 253
 254         return val;
 255 }
 256
 257 static int mv88e6xxx_reg_read(struct mv88e6xxx_chip *chip, int addr, int reg)
 258 {
 259         int ret;
 260
 261         mutex_lock(&chip->reg_lock);
 262         ret = _mv88e6xxx_reg_read(chip, addr, reg);
 263         mutex_unlock(&chip->reg_lock);
 264
 265         return ret;
 266 }
 267
 268 static int _mv88e6xxx_reg_write(struct mv88e6xxx_chip *chip, int addr,
 269                                 int reg, u16 val)
 270 {
 271         return mv88e6xxx_write(chip, addr, reg, val);
 272 }
 273
 274 static int mv88e6xxx_reg_write(struct mv88e6xxx_chip *chip, int addr,
 275                                int reg, u16 val)
 276 {
 277         int ret;
 278
 279         mutex_lock(&chip->reg_lock);
 280         ret = _mv88e6xxx_reg_write(chip, addr, reg, val);
 281         mutex_unlock(&chip->reg_lock);
 282
 283         return ret;
 284 }
 285
 286 static int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
 287 {
 288         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 289         int err;
 290
 291         err = mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MAC_01,
 292                                   (addr[0] << 8) | addr[1]);
 293         if (err)
 294                 return err;
 295
 296         err = mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MAC_23,
 297                                   (addr[2] << 8) | addr[3]);
 298         if (err)
 299                 return err;
 300
 301         return mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MAC_45,
 302                                    (addr[4] << 8) | addr[5]);
 303 }
 304
 305 static int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
 306 {
 307         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 308         int ret;
 309         int i;
 310
 311         for (i = 0; i < 6; i++) {
 312                 int j;
 313
 314                 /* Write the MAC address byte. */
 315                 ret = mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
 316                                           GLOBAL2_SWITCH_MAC_BUSY |
 317                                           (i << 8) | addr[i]);
 318                 if (ret)
 319                         return ret;
 320
 321                 /* Wait for the write to complete. */
 322                 for (j = 0; j < 16; j++) {
 323                         ret = mv88e6xxx_reg_read(chip, REG_GLOBAL2,
 324                                                  GLOBAL2_SWITCH_MAC);
 325                         if (ret < 0)
 326                                 return ret;
 327
 328                         if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
 329                                 break;
 330                 }
 331                 if (j == 16)
 332                         return -ETIMEDOUT;
 333         }
 334
 335         return 0;
 336 }
 337
 338 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
 339 {
 340         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 341
 342         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_SWITCH_MAC))
 343                 return mv88e6xxx_set_addr_indirect(ds, addr);
 344         else
 345                 return mv88e6xxx_set_addr_direct(ds, addr);
 346 }
 347
 348 static int mv88e6xxx_mdio_read_direct(struct mv88e6xxx_chip *chip,
 349                                       int addr, int regnum)
 350 {
 351         if (addr >= 0)
 352                 return _mv88e6xxx_reg_read(chip, addr, regnum);
 353         return 0xffff;
 354 }
 355
 356 static int mv88e6xxx_mdio_write_direct(struct mv88e6xxx_chip *chip,
 357                                        int addr, int regnum, u16 val)
 358 {
 359         if (addr >= 0)
 360                 return _mv88e6xxx_reg_write(chip, addr, regnum, val);
 361         return 0;
 362 }
 363
 364 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
 365 {
 366         int ret;
 367         unsigned long timeout;
 368
 369         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
 370         if (ret < 0)
 371                 return ret;
 372
 373         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
 374                                    ret & ~GLOBAL_CONTROL_PPU_ENABLE);
 375         if (ret)
 376                 return ret;
 377
 378         timeout = jiffies + 1 * HZ;
 379         while (time_before(jiffies, timeout)) {
 380                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
 381                 if (ret < 0)
 382                         return ret;
 383
 384                 usleep_range(1000, 2000);
 385                 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
 386                     GLOBAL_STATUS_PPU_POLLING)
 387                         return 0;
 388         }
 389
 390         return -ETIMEDOUT;
 391 }
 392
 393 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
 394 {
 395         int ret, err;
 396         unsigned long timeout;
 397
 398         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
 399         if (ret < 0)
 400                 return ret;
 401
 402         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
 403                                    ret | GLOBAL_CONTROL_PPU_ENABLE);
 404         if (err)
 405                 return err;
 406
 407         timeout = jiffies + 1 * HZ;
 408         while (time_before(jiffies, timeout)) {
 409                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
 410                 if (ret < 0)
 411                         return ret;
 412
 413                 usleep_range(1000, 2000);
 414                 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
 415                     GLOBAL_STATUS_PPU_POLLING)
 416                         return 0;
 417         }
 418
 419         return -ETIMEDOUT;
 420 }
 421
 422 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
 423 {
 424         struct mv88e6xxx_chip *chip;
 425
 426         chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
 427
 428         mutex_lock(&chip->reg_lock);
 429
 430         if (mutex_trylock(&chip->ppu_mutex)) {
 431                 if (mv88e6xxx_ppu_enable(chip) == 0)
 432                         chip->ppu_disabled = 0;
 433                 mutex_unlock(&chip->ppu_mutex);
 434         }
 435
 436         mutex_unlock(&chip->reg_lock);
 437 }
 438
 439 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
 440 {
 441         struct mv88e6xxx_chip *chip = (void *)_ps;
 442
 443         schedule_work(&chip->ppu_work);
 444 }
 445
 446 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
 447 {
 448         int ret;
 449
 450         mutex_lock(&chip->ppu_mutex);
 451
 452         /* If the PHY polling unit is enabled, disable it so that
 453          * we can access the PHY registers.  If it was already
 454          * disabled, cancel the timer that is going to re-enable
 455          * it.
 456          */
 457         if (!chip->ppu_disabled) {
 458                 ret = mv88e6xxx_ppu_disable(chip);
 459                 if (ret < 0) {
 460                         mutex_unlock(&chip->ppu_mutex);
 461                         return ret;
 462                 }
 463                 chip->ppu_disabled = 1;
 464         } else {
 465                 del_timer(&chip->ppu_timer);
 466                 ret = 0;
 467         }
 468
 469         return ret;
 470 }
 471
 472 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
 473 {
 474         /* Schedule a timer to re-enable the PHY polling unit. */
 475         mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
 476         mutex_unlock(&chip->ppu_mutex);
 477 }
 478
 479 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
 480 {
 481         mutex_init(&chip->ppu_mutex);
 482         INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
 483         init_timer(&chip->ppu_timer);
 484         chip->ppu_timer.data = (unsigned long)chip;
 485         chip->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
 486 }
 487
 488 static int mv88e6xxx_mdio_read_ppu(struct mv88e6xxx_chip *chip, int addr,
 489                                    int regnum)
 490 {
 491         int ret;
 492
 493         ret = mv88e6xxx_ppu_access_get(chip);
 494         if (ret >= 0) {
 495                 ret = _mv88e6xxx_reg_read(chip, addr, regnum);
 496                 mv88e6xxx_ppu_access_put(chip);
 497         }
 498
 499         return ret;
 500 }
 501
 502 static int mv88e6xxx_mdio_write_ppu(struct mv88e6xxx_chip *chip, int addr,
 503                                     int regnum, u16 val)
 504 {
 505         int ret;
 506
 507         ret = mv88e6xxx_ppu_access_get(chip);
 508         if (ret >= 0) {
 509                 ret = _mv88e6xxx_reg_write(chip, addr, regnum, val);
 510                 mv88e6xxx_ppu_access_put(chip);
 511         }
 512
 513         return ret;
 514 }
 515
 516 static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
 517 {
 518         return chip->info->family == MV88E6XXX_FAMILY_6065;
 519 }
 520
 521 static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
 522 {
 523         return chip->info->family == MV88E6XXX_FAMILY_6095;
 524 }
 525
 526 static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
 527 {
 528         return chip->info->family == MV88E6XXX_FAMILY_6097;
 529 }
 530
 531 static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
 532 {
 533         return chip->info->family == MV88E6XXX_FAMILY_6165;
 534 }
 535
 536 static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
 537 {
 538         return chip->info->family == MV88E6XXX_FAMILY_6185;
 539 }
 540
 541 static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
 542 {
 543         return chip->info->family == MV88E6XXX_FAMILY_6320;
 544 }
 545
 546 static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
 547 {
 548         return chip->info->family == MV88E6XXX_FAMILY_6351;
 549 }
 550
 551 static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
 552 {
 553         return chip->info->family == MV88E6XXX_FAMILY_6352;
 554 }
 555
 556 static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
 557 {
 558         return chip->info->num_databases;
 559 }
 560
 561 static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_chip *chip)
 562 {
 563         /* Does the device have dedicated FID registers for ATU and VTU ops? */
 564         if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
 565             mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip))
 566                 return true;
 567
 568         return false;
 569 }
 570
 571 /* We expect the switch to perform auto negotiation if there is a real
 572  * phy. However, in the case of a fixed link phy, we force the port
 573  * settings from the fixed link settings.
 574  */
 575 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
 576                                   struct phy_device *phydev)
 577 {
 578         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 579         u32 reg;
 580         int ret;
 581
 582         if (!phy_is_pseudo_fixed_link(phydev))
 583                 return;
 584
 585         mutex_lock(&chip->reg_lock);
 586
 587         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
 588         if (ret < 0)
 589                 goto out;
 590
 591         reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
 592                       PORT_PCS_CTRL_FORCE_LINK |
 593                       PORT_PCS_CTRL_DUPLEX_FULL |
 594                       PORT_PCS_CTRL_FORCE_DUPLEX |
 595                       PORT_PCS_CTRL_UNFORCED);
 596
 597         reg |= PORT_PCS_CTRL_FORCE_LINK;
 598         if (phydev->link)
 599                 reg |= PORT_PCS_CTRL_LINK_UP;
 600
 601         if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100)
 602                 goto out;
 603
 604         switch (phydev->speed) {
 605         case SPEED_1000:
 606                 reg |= PORT_PCS_CTRL_1000;
 607                 break;
 608         case SPEED_100:
 609                 reg |= PORT_PCS_CTRL_100;
 610                 break;
 611         case SPEED_10:
 612                 reg |= PORT_PCS_CTRL_10;
 613                 break;
 614         default:
 615                 pr_info("Unknown speed");
 616                 goto out;
 617         }
 618
 619         reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
 620         if (phydev->duplex == DUPLEX_FULL)
 621                 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
 622
 623         if ((mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip)) &&
 624             (port >= chip->info->num_ports - 2)) {
 625                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 626                         reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
 627                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 628                         reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
 629                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 630                         reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
 631                                 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
 632         }
 633         _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_PCS_CTRL, reg);
 634
 635 out:
 636         mutex_unlock(&chip->reg_lock);
 637 }
 638
 639 static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip)
 640 {
 641         int ret;
 642         int i;
 643
 644         for (i = 0; i < 10; i++) {
 645                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_OP);
 646                 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
 647                         return 0;
 648         }
 649
 650         return -ETIMEDOUT;
 651 }
 652
 653 static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
 654 {
 655         int ret;
 656
 657         if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
 658                 port = (port + 1) << 5;
 659
 660         /* Snapshot the hardware statistics counters for this port. */
 661         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
 662                                    GLOBAL_STATS_OP_CAPTURE_PORT |
 663                                    GLOBAL_STATS_OP_HIST_RX_TX | port);
 664         if (ret < 0)
 665                 return ret;
 666
 667         /* Wait for the snapshotting to complete. */
 668         ret = _mv88e6xxx_stats_wait(chip);
 669         if (ret < 0)
 670                 return ret;
 671
 672         return 0;
 673 }
 674
 675 static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip,
 676                                   int stat, u32 *val)
 677 {
 678         u32 _val;
 679         int ret;
 680
 681         *val = 0;
 682
 683         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
 684                                    GLOBAL_STATS_OP_READ_CAPTURED |
 685                                    GLOBAL_STATS_OP_HIST_RX_TX | stat);
 686         if (ret < 0)
 687                 return;
 688
 689         ret = _mv88e6xxx_stats_wait(chip);
 690         if (ret < 0)
 691                 return;
 692
 693         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
 694         if (ret < 0)
 695                 return;
 696
 697         _val = ret << 16;
 698
 699         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
 700         if (ret < 0)
 701                 return;
 702
 703         *val = _val | ret;
 704 }
 705
 706 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
 707         { "in_good_octets",     8, 0x00, BANK0, },
 708         { "in_bad_octets",      4, 0x02, BANK0, },
 709         { "in_unicast",         4, 0x04, BANK0, },
 710         { "in_broadcasts",      4, 0x06, BANK0, },
 711         { "in_multicasts",      4, 0x07, BANK0, },
 712         { "in_pause",           4, 0x16, BANK0, },
 713         { "in_undersize",       4, 0x18, BANK0, },
 714         { "in_fragments",       4, 0x19, BANK0, },
 715         { "in_oversize",        4, 0x1a, BANK0, },
 716         { "in_jabber",          4, 0x1b, BANK0, },
 717         { "in_rx_error",        4, 0x1c, BANK0, },
 718         { "in_fcs_error",       4, 0x1d, BANK0, },
 719         { "out_octets",         8, 0x0e, BANK0, },
 720         { "out_unicast",        4, 0x10, BANK0, },
 721         { "out_broadcasts",     4, 0x13, BANK0, },
 722         { "out_multicasts",     4, 0x12, BANK0, },
 723         { "out_pause",          4, 0x15, BANK0, },
 724         { "excessive",          4, 0x11, BANK0, },
 725         { "collisions",         4, 0x1e, BANK0, },
 726         { "deferred",           4, 0x05, BANK0, },
 727         { "single",             4, 0x14, BANK0, },
 728         { "multiple",           4, 0x17, BANK0, },
 729         { "out_fcs_error",      4, 0x03, BANK0, },
 730         { "late",               4, 0x1f, BANK0, },
 731         { "hist_64bytes",       4, 0x08, BANK0, },
 732         { "hist_65_127bytes",   4, 0x09, BANK0, },
 733         { "hist_128_255bytes",  4, 0x0a, BANK0, },
 734         { "hist_256_511bytes",  4, 0x0b, BANK0, },
 735         { "hist_512_1023bytes", 4, 0x0c, BANK0, },
 736         { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
 737         { "sw_in_discards",     4, 0x10, PORT, },
 738         { "sw_in_filtered",     2, 0x12, PORT, },
 739         { "sw_out_filtered",    2, 0x13, PORT, },
 740         { "in_discards",        4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 741         { "in_filtered",        4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 742         { "in_accepted",        4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 743         { "in_bad_accepted",    4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 744         { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 745         { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 746         { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 747         { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 748         { "tcam_counter_0",     4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 749         { "tcam_counter_1",     4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 750         { "tcam_counter_2",     4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
 751         { "tcam_counter_3",     4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
 752         { "in_da_unknown",      4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
 753         { "in_management",      4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
 754         { "out_queue_0",        4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 755         { "out_queue_1",        4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 756         { "out_queue_2",        4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 757         { "out_queue_3",        4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 758         { "out_queue_4",        4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 759         { "out_queue_5",        4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 760         { "out_queue_6",        4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 761         { "out_queue_7",        4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 762         { "out_cut_through",    4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 763         { "out_octets_a",       4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
 764         { "out_octets_b",       4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
 765         { "out_management",     4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
 766 };
 767
 768 static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip,
 769                                struct mv88e6xxx_hw_stat *stat)
 770 {
 771         switch (stat->type) {
 772         case BANK0:
 773                 return true;
 774         case BANK1:
 775                 return mv88e6xxx_6320_family(chip);
 776         case PORT:
 777                 return mv88e6xxx_6095_family(chip) ||
 778                         mv88e6xxx_6185_family(chip) ||
 779                         mv88e6xxx_6097_family(chip) ||
 780                         mv88e6xxx_6165_family(chip) ||
 781                         mv88e6xxx_6351_family(chip) ||
 782                         mv88e6xxx_6352_family(chip);
 783         }
 784         return false;
 785 }
 786
 787 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
 788                                             struct mv88e6xxx_hw_stat *s,
 789                                             int port)
 790 {
 791         u32 low;
 792         u32 high = 0;
 793         int ret;
 794         u64 value;
 795
 796         switch (s->type) {
 797         case PORT:
 798                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), s->reg);
 799                 if (ret < 0)
 800                         return UINT64_MAX;
 801
 802                 low = ret;
 803                 if (s->sizeof_stat == 4) {
 804                         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port),
 805                                                   s->reg + 1);
 806                         if (ret < 0)
 807                                 return UINT64_MAX;
 808                         high = ret;
 809                 }
 810                 break;
 811         case BANK0:
 812         case BANK1:
 813                 _mv88e6xxx_stats_read(chip, s->reg, &low);
 814                 if (s->sizeof_stat == 8)
 815                         _mv88e6xxx_stats_read(chip, s->reg + 1, &high);
 816         }
 817         value = (((u64)high) << 16) | low;
 818         return value;
 819 }
 820
 821 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
 822                                   uint8_t *data)
 823 {
 824         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 825         struct mv88e6xxx_hw_stat *stat;
 826         int i, j;
 827
 828         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 829                 stat = &mv88e6xxx_hw_stats[i];
 830                 if (mv88e6xxx_has_stat(chip, stat)) {
 831                         memcpy(data + j * ETH_GSTRING_LEN, stat->string,
 832                                ETH_GSTRING_LEN);
 833                         j++;
 834                 }
 835         }
 836 }
 837
 838 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
 839 {
 840         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 841         struct mv88e6xxx_hw_stat *stat;
 842         int i, j;
 843
 844         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 845                 stat = &mv88e6xxx_hw_stats[i];
 846                 if (mv88e6xxx_has_stat(chip, stat))
 847                         j++;
 848         }
 849         return j;
 850 }
 851
 852 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
 853                                         uint64_t *data)
 854 {
 855         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 856         struct mv88e6xxx_hw_stat *stat;
 857         int ret;
 858         int i, j;
 859
 860         mutex_lock(&chip->reg_lock);
 861
 862         ret = _mv88e6xxx_stats_snapshot(chip, port);
 863         if (ret < 0) {
 864                 mutex_unlock(&chip->reg_lock);
 865                 return;
 866         }
 867         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 868                 stat = &mv88e6xxx_hw_stats[i];
 869                 if (mv88e6xxx_has_stat(chip, stat)) {
 870                         data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port);
 871                         j++;
 872                 }
 873         }
 874
 875         mutex_unlock(&chip->reg_lock);
 876 }
 877
 878 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
 879 {
 880         return 32 * sizeof(u16);
 881 }
 882
 883 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
 884                                struct ethtool_regs *regs, void *_p)
 885 {
 886         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 887         u16 *p = _p;
 888         int i;
 889
 890         regs->version = 0;
 891
 892         memset(p, 0xff, 32 * sizeof(u16));
 893
 894         mutex_lock(&chip->reg_lock);
 895
 896         for (i = 0; i < 32; i++) {
 897                 int ret;
 898
 899                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), i);
 900                 if (ret >= 0)
 901                         p[i] = ret;
 902         }
 903
 904         mutex_unlock(&chip->reg_lock);
 905 }
 906
 907 static int _mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int reg, int offset,
 908                            u16 mask)
 909 {
 910         unsigned long timeout = jiffies + HZ / 10;
 911
 912         while (time_before(jiffies, timeout)) {
 913                 int ret;
 914
 915                 ret = _mv88e6xxx_reg_read(chip, reg, offset);
 916                 if (ret < 0)
 917                         return ret;
 918                 if (!(ret & mask))
 919                         return 0;
 920
 921                 usleep_range(1000, 2000);
 922         }
 923         return -ETIMEDOUT;
 924 }
 925
 926 static int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int reg,
 927                           int offset, u16 mask)
 928 {
 929         int ret;
 930
 931         mutex_lock(&chip->reg_lock);
 932         ret = _mv88e6xxx_wait(chip, reg, offset, mask);
 933         mutex_unlock(&chip->reg_lock);
 934
 935         return ret;
 936 }
 937
 938 static int mv88e6xxx_mdio_wait(struct mv88e6xxx_chip *chip)
 939 {
 940         return _mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_SMI_OP,
 941                                GLOBAL2_SMI_OP_BUSY);
 942 }
 943
 944 static int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
 945 {
 946         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 947
 948         return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
 949                               GLOBAL2_EEPROM_OP_LOAD);
 950 }
 951
 952 static int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
 953 {
 954         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 955
 956         return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
 957                               GLOBAL2_EEPROM_OP_BUSY);
 958 }
 959
 960 static int mv88e6xxx_read_eeprom_word(struct dsa_switch *ds, int addr)
 961 {
 962         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 963         int ret;
 964
 965         mutex_lock(&chip->eeprom_mutex);
 966
 967         ret = mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
 968                                   GLOBAL2_EEPROM_OP_READ |
 969                                   (addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
 970         if (ret < 0)
 971                 goto error;
 972
 973         ret = mv88e6xxx_eeprom_busy_wait(ds);
 974         if (ret < 0)
 975                 goto error;
 976
 977         ret = mv88e6xxx_reg_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA);
 978 error:
 979         mutex_unlock(&chip->eeprom_mutex);
 980         return ret;
 981 }
 982
 983 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
 984 {
 985         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 986
 987         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEPROM))
 988                 return chip->eeprom_len;
 989
 990         return 0;
 991 }
 992
 993 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
 994                                 struct ethtool_eeprom *eeprom, u8 *data)
 995 {
 996         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 997         int offset;
 998         int len;
 999         int ret;
1000
1001         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEPROM))
1002                 return -EOPNOTSUPP;
1003
1004         offset = eeprom->offset;
1005         len = eeprom->len;
1006         eeprom->len = 0;
1007
1008         eeprom->magic = 0xc3ec4951;
1009
1010         ret = mv88e6xxx_eeprom_load_wait(ds);
1011         if (ret < 0)
1012                 return ret;
1013
1014         if (offset & 1) {
1015                 int word;
1016
1017                 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
1018                 if (word < 0)
1019                         return word;
1020
1021                 *data++ = (word >> 8) & 0xff;
1022
1023                 offset++;
1024                 len--;
1025                 eeprom->len++;
1026         }
1027
1028         while (len >= 2) {
1029                 int word;
1030
1031                 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
1032                 if (word < 0)
1033                         return word;
1034
1035                 *data++ = word & 0xff;
1036                 *data++ = (word >> 8) & 0xff;
1037
1038                 offset += 2;
1039                 len -= 2;
1040                 eeprom->len += 2;
1041         }
1042
1043         if (len) {
1044                 int word;
1045
1046                 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
1047                 if (word < 0)
1048                         return word;
1049
1050                 *data++ = word & 0xff;
1051
1052                 offset++;
1053                 len--;
1054                 eeprom->len++;
1055         }
1056
1057         return 0;
1058 }
1059
1060 static int mv88e6xxx_eeprom_is_readonly(struct dsa_switch *ds)
1061 {
1062         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1063         int ret;
1064
1065         ret = mv88e6xxx_reg_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_OP);
1066         if (ret < 0)
1067                 return ret;
1068
1069         if (!(ret & GLOBAL2_EEPROM_OP_WRITE_EN))
1070                 return -EROFS;
1071
1072         return 0;
1073 }
1074
1075 static int mv88e6xxx_write_eeprom_word(struct dsa_switch *ds, int addr,
1076                                        u16 data)
1077 {
1078         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1079         int ret;
1080
1081         mutex_lock(&chip->eeprom_mutex);
1082
1083         ret = mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
1084         if (ret < 0)
1085                 goto error;
1086
1087         ret = mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
1088                                   GLOBAL2_EEPROM_OP_WRITE |
1089                                   (addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
1090         if (ret < 0)
1091                 goto error;
1092
1093         ret = mv88e6xxx_eeprom_busy_wait(ds);
1094 error:
1095         mutex_unlock(&chip->eeprom_mutex);
1096         return ret;
1097 }
1098
1099 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
1100                                 struct ethtool_eeprom *eeprom, u8 *data)
1101 {
1102         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1103         int offset;
1104         int ret;
1105         int len;
1106
1107         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEPROM))
1108                 return -EOPNOTSUPP;
1109
1110         if (eeprom->magic != 0xc3ec4951)
1111                 return -EINVAL;
1112
1113         ret = mv88e6xxx_eeprom_is_readonly(ds);
1114         if (ret)
1115                 return ret;
1116
1117         offset = eeprom->offset;
1118         len = eeprom->len;
1119         eeprom->len = 0;
1120
1121         ret = mv88e6xxx_eeprom_load_wait(ds);
1122         if (ret < 0)
1123                 return ret;
1124
1125         if (offset & 1) {
1126                 int word;
1127
1128                 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
1129                 if (word < 0)
1130                         return word;
1131
1132                 word = (*data++ << 8) | (word & 0xff);
1133
1134                 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1135                 if (ret < 0)
1136                         return ret;
1137
1138                 offset++;
1139                 len--;
1140                 eeprom->len++;
1141         }
1142
1143         while (len >= 2) {
1144                 int word;
1145
1146                 word = *data++;
1147                 word |= *data++ << 8;
1148
1149                 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1150                 if (ret < 0)
1151                         return ret;
1152
1153                 offset += 2;
1154                 len -= 2;
1155                 eeprom->len += 2;
1156         }
1157
1158         if (len) {
1159                 int word;
1160
1161                 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
1162                 if (word < 0)
1163                         return word;
1164
1165                 word = (word & 0xff00) | *data++;
1166
1167                 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1168                 if (ret < 0)
1169                         return ret;
1170
1171                 offset++;
1172                 len--;
1173                 eeprom->len++;
1174         }
1175
1176         return 0;
1177 }
1178
1179 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
1180 {
1181         return _mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_ATU_OP,
1182                                GLOBAL_ATU_OP_BUSY);
1183 }
1184
1185 static int mv88e6xxx_mdio_read_indirect(struct mv88e6xxx_chip *chip,
1186                                         int addr, int regnum)
1187 {
1188         int ret;
1189
1190         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_OP,
1191                                    GLOBAL2_SMI_OP_22_READ | (addr << 5) |
1192                                    regnum);
1193         if (ret < 0)
1194                 return ret;
1195
1196         ret = mv88e6xxx_mdio_wait(chip);
1197         if (ret < 0)
1198                 return ret;
1199
1200         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL2, GLOBAL2_SMI_DATA);
1201
1202         return ret;
1203 }
1204
1205 static int mv88e6xxx_mdio_write_indirect(struct mv88e6xxx_chip *chip,
1206                                          int addr, int regnum, u16 val)
1207 {
1208         int ret;
1209
1210         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
1211         if (ret < 0)
1212                 return ret;
1213
1214         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_OP,
1215                                    GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
1216                                    regnum);
1217
1218         return mv88e6xxx_mdio_wait(chip);
1219 }
1220
1221 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1222                              struct ethtool_eee *e)
1223 {
1224         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1225         int reg;
1226
1227         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
1228                 return -EOPNOTSUPP;
1229
1230         mutex_lock(&chip->reg_lock);
1231
1232         reg = mv88e6xxx_mdio_read_indirect(chip, port, 16);
1233         if (reg < 0)
1234                 goto out;
1235
1236         e->eee_enabled = !!(reg & 0x0200);
1237         e->tx_lpi_enabled = !!(reg & 0x0100);
1238
1239         reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
1240         if (reg < 0)
1241                 goto out;
1242
1243         e->eee_active = !!(reg & PORT_STATUS_EEE);
1244         reg = 0;
1245
1246 out:
1247         mutex_unlock(&chip->reg_lock);
1248         return reg;
1249 }
1250
1251 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1252                              struct phy_device *phydev, struct ethtool_eee *e)
1253 {
1254         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1255         int reg;
1256         int ret;
1257
1258         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
1259                 return -EOPNOTSUPP;
1260
1261         mutex_lock(&chip->reg_lock);
1262
1263         ret = mv88e6xxx_mdio_read_indirect(chip, port, 16);
1264         if (ret < 0)
1265                 goto out;
1266
1267         reg = ret & ~0x0300;
1268         if (e->eee_enabled)
1269                 reg |= 0x0200;
1270         if (e->tx_lpi_enabled)
1271                 reg |= 0x0100;
1272
1273         ret = mv88e6xxx_mdio_write_indirect(chip, port, 16, reg);
1274 out:
1275         mutex_unlock(&chip->reg_lock);
1276
1277         return ret;
1278 }
1279
1280 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
1281 {
1282         int ret;
1283
1284         if (mv88e6xxx_has_fid_reg(chip)) {
1285                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_FID,
1286                                            fid);
1287                 if (ret < 0)
1288                         return ret;
1289         } else if (mv88e6xxx_num_databases(chip) == 256) {
1290                 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
1291                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL);
1292                 if (ret < 0)
1293                         return ret;
1294
1295                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
1296                                            (ret & 0xfff) |
1297                                            ((fid << 8) & 0xf000));
1298                 if (ret < 0)
1299                         return ret;
1300
1301                 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1302                 cmd |= fid & 0xf;
1303         }
1304
1305         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
1306         if (ret < 0)
1307                 return ret;
1308
1309         return _mv88e6xxx_atu_wait(chip);
1310 }
1311
1312 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
1313                                      struct mv88e6xxx_atu_entry *entry)
1314 {
1315         u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1316
1317         if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1318                 unsigned int mask, shift;
1319
1320                 if (entry->trunk) {
1321                         data |= GLOBAL_ATU_DATA_TRUNK;
1322                         mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1323                         shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1324                 } else {
1325                         mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1326                         shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1327                 }
1328
1329                 data |= (entry->portv_trunkid << shift) & mask;
1330         }
1331
1332         return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_DATA, data);
1333 }
1334
1335 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
1336                                      struct mv88e6xxx_atu_entry *entry,
1337                                      bool static_too)
1338 {
1339         int op;
1340         int err;
1341
1342         err = _mv88e6xxx_atu_wait(chip);
1343         if (err)
1344                 return err;
1345
1346         err = _mv88e6xxx_atu_data_write(chip, entry);
1347         if (err)
1348                 return err;
1349
1350         if (entry->fid) {
1351                 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1352                         GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1353         } else {
1354                 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1355                         GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1356         }
1357
1358         return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
1359 }
1360
1361 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
1362                                 u16 fid, bool static_too)
1363 {
1364         struct mv88e6xxx_atu_entry entry = {
1365                 .fid = fid,
1366                 .state = 0, /* EntryState bits must be 0 */
1367         };
1368
1369         return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1370 }
1371
1372 static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
1373                                int from_port, int to_port, bool static_too)
1374 {
1375         struct mv88e6xxx_atu_entry entry = {
1376                 .trunk = false,
1377                 .fid = fid,
1378         };
1379
1380         /* EntryState bits must be 0xF */
1381         entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1382
1383         /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1384         entry.portv_trunkid = (to_port & 0x0f) << 4;
1385         entry.portv_trunkid |= from_port & 0x0f;
1386
1387         return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1388 }
1389
1390 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
1391                                  int port, bool static_too)
1392 {
1393         /* Destination port 0xF means remove the entries */
1394         return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
1395 }
1396
1397 static const char * const mv88e6xxx_port_state_names[] = {
1398         [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1399         [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1400         [PORT_CONTROL_STATE_LEARNING] = "Learning",
1401         [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1402 };
1403
1404 static int _mv88e6xxx_port_state(struct mv88e6xxx_chip *chip, int port,
1405                                  u8 state)
1406 {
1407         struct dsa_switch *ds = chip->ds;
1408         int reg, ret = 0;
1409         u8 oldstate;
1410
1411         reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL);
1412         if (reg < 0)
1413                 return reg;
1414
1415         oldstate = reg & PORT_CONTROL_STATE_MASK;
1416
1417         if (oldstate != state) {
1418                 /* Flush forwarding database if we're moving a port
1419                  * from Learning or Forwarding state to Disabled or
1420                  * Blocking or Listening state.
1421                  */
1422                 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
1423                      oldstate == PORT_CONTROL_STATE_FORWARDING) &&
1424                     (state == PORT_CONTROL_STATE_DISABLED ||
1425                      state == PORT_CONTROL_STATE_BLOCKING)) {
1426                         ret = _mv88e6xxx_atu_remove(chip, 0, port, false);
1427                         if (ret)
1428                                 return ret;
1429                 }
1430
1431                 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1432                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL,
1433                                            reg);
1434                 if (ret)
1435                         return ret;
1436
1437                 netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n",
1438                            mv88e6xxx_port_state_names[state],
1439                            mv88e6xxx_port_state_names[oldstate]);
1440         }
1441
1442         return ret;
1443 }
1444
1445 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
1446 {
1447         struct net_device *bridge = chip->ports[port].bridge_dev;
1448         const u16 mask = (1 << chip->info->num_ports) - 1;
1449         struct dsa_switch *ds = chip->ds;
1450         u16 output_ports = 0;
1451         int reg;
1452         int i;
1453
1454         /* allow CPU port or DSA link(s) to send frames to every port */
1455         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1456                 output_ports = mask;
1457         } else {
1458                 for (i = 0; i < chip->info->num_ports; ++i) {
1459                         /* allow sending frames to every group member */
1460                         if (bridge && chip->ports[i].bridge_dev == bridge)
1461                                 output_ports |= BIT(i);
1462
1463                         /* allow sending frames to CPU port and DSA link(s) */
1464                         if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1465                                 output_ports |= BIT(i);
1466                 }
1467         }
1468
1469         /* prevent frames from going back out of the port they came in on */
1470         output_ports &= ~BIT(port);
1471
1472         reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
1473         if (reg < 0)
1474                 return reg;
1475
1476         reg &= ~mask;
1477         reg |= output_ports & mask;
1478
1479         return _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN, reg);
1480 }
1481
1482 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1483                                          u8 state)
1484 {
1485         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1486         int stp_state;
1487         int err;
1488
1489         switch (state) {
1490         case BR_STATE_DISABLED:
1491                 stp_state = PORT_CONTROL_STATE_DISABLED;
1492                 break;
1493         case BR_STATE_BLOCKING:
1494         case BR_STATE_LISTENING:
1495                 stp_state = PORT_CONTROL_STATE_BLOCKING;
1496                 break;
1497         case BR_STATE_LEARNING:
1498                 stp_state = PORT_CONTROL_STATE_LEARNING;
1499                 break;
1500         case BR_STATE_FORWARDING:
1501         default:
1502                 stp_state = PORT_CONTROL_STATE_FORWARDING;
1503                 break;
1504         }
1505
1506         mutex_lock(&chip->reg_lock);
1507         err = _mv88e6xxx_port_state(chip, port, stp_state);
1508         mutex_unlock(&chip->reg_lock);
1509
1510         if (err)
1511                 netdev_err(ds->ports[port].netdev,
1512                            "failed to update state to %s\n",
1513                            mv88e6xxx_port_state_names[stp_state]);
1514 }
1515
1516 static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip *chip, int port,
1517                                 u16 *new, u16 *old)
1518 {
1519         struct dsa_switch *ds = chip->ds;
1520         u16 pvid;
1521         int ret;
1522
1523         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_DEFAULT_VLAN);
1524         if (ret < 0)
1525                 return ret;
1526
1527         pvid = ret & PORT_DEFAULT_VLAN_MASK;
1528
1529         if (new) {
1530                 ret &= ~PORT_DEFAULT_VLAN_MASK;
1531                 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1532
1533                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
1534                                            PORT_DEFAULT_VLAN, ret);
1535                 if (ret < 0)
1536                         return ret;
1537
1538                 netdev_dbg(ds->ports[port].netdev,
1539                            "DefaultVID %d (was %d)\n", *new, pvid);
1540         }
1541
1542         if (old)
1543                 *old = pvid;
1544
1545         return 0;
1546 }
1547
1548 static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_chip *chip,
1549                                     int port, u16 *pvid)
1550 {
1551         return _mv88e6xxx_port_pvid(chip, port, NULL, pvid);
1552 }
1553
1554 static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip *chip,
1555                                     int port, u16 pvid)
1556 {
1557         return _mv88e6xxx_port_pvid(chip, port, &pvid, NULL);
1558 }
1559
1560 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
1561 {
1562         return _mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_VTU_OP,
1563                                GLOBAL_VTU_OP_BUSY);
1564 }
1565
1566 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
1567 {
1568         int ret;
1569
1570         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_OP, op);
1571         if (ret < 0)
1572                 return ret;
1573
1574         return _mv88e6xxx_vtu_wait(chip);
1575 }
1576
1577 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
1578 {
1579         int ret;
1580
1581         ret = _mv88e6xxx_vtu_wait(chip);
1582         if (ret < 0)
1583                 return ret;
1584
1585         return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
1586 }
1587
1588 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
1589                                         struct mv88e6xxx_vtu_stu_entry *entry,
1590                                         unsigned int nibble_offset)
1591 {
1592         u16 regs[3];
1593         int i;
1594         int ret;
1595
1596         for (i = 0; i < 3; ++i) {
1597                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1598                                           GLOBAL_VTU_DATA_0_3 + i);
1599                 if (ret < 0)
1600                         return ret;
1601
1602                 regs[i] = ret;
1603         }
1604
1605         for (i = 0; i < chip->info->num_ports; ++i) {
1606                 unsigned int shift = (i % 4) * 4 + nibble_offset;
1607                 u16 reg = regs[i / 4];
1608
1609                 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1610         }
1611
1612         return 0;
1613 }
1614
1615 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
1616                                    struct mv88e6xxx_vtu_stu_entry *entry)
1617 {
1618         return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
1619 }
1620
1621 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
1622                                    struct mv88e6xxx_vtu_stu_entry *entry)
1623 {
1624         return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
1625 }
1626
1627 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
1628                                          struct mv88e6xxx_vtu_stu_entry *entry,
1629                                          unsigned int nibble_offset)
1630 {
1631         u16 regs[3] = { 0 };
1632         int i;
1633         int ret;
1634
1635         for (i = 0; i < chip->info->num_ports; ++i) {
1636                 unsigned int shift = (i % 4) * 4 + nibble_offset;
1637                 u8 data = entry->data[i];
1638
1639                 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1640         }
1641
1642         for (i = 0; i < 3; ++i) {
1643                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL,
1644                                            GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1645                 if (ret < 0)
1646                         return ret;
1647         }
1648
1649         return 0;
1650 }
1651
1652 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
1653                                     struct mv88e6xxx_vtu_stu_entry *entry)
1654 {
1655         return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
1656 }
1657
1658 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
1659                                     struct mv88e6xxx_vtu_stu_entry *entry)
1660 {
1661         return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
1662 }
1663
1664 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
1665 {
1666         return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID,
1667                                     vid & GLOBAL_VTU_VID_MASK);
1668 }
1669
1670 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1671                                   struct mv88e6xxx_vtu_stu_entry *entry)
1672 {
1673         struct mv88e6xxx_vtu_stu_entry next = { 0 };
1674         int ret;
1675
1676         ret = _mv88e6xxx_vtu_wait(chip);
1677         if (ret < 0)
1678                 return ret;
1679
1680         ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1681         if (ret < 0)
1682                 return ret;
1683
1684         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
1685         if (ret < 0)
1686                 return ret;
1687
1688         next.vid = ret & GLOBAL_VTU_VID_MASK;
1689         next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1690
1691         if (next.valid) {
1692                 ret = mv88e6xxx_vtu_data_read(chip, &next);
1693                 if (ret < 0)
1694                         return ret;
1695
1696                 if (mv88e6xxx_has_fid_reg(chip)) {
1697                         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1698                                                   GLOBAL_VTU_FID);
1699                         if (ret < 0)
1700                                 return ret;
1701
1702                         next.fid = ret & GLOBAL_VTU_FID_MASK;
1703                 } else if (mv88e6xxx_num_databases(chip) == 256) {
1704                         /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1705                          * VTU DBNum[3:0] are located in VTU Operation 3:0
1706                          */
1707                         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1708                                                   GLOBAL_VTU_OP);
1709                         if (ret < 0)
1710                                 return ret;
1711
1712                         next.fid = (ret & 0xf00) >> 4;
1713                         next.fid |= ret & 0xf;
1714                 }
1715
1716                 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1717                         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1718                                                   GLOBAL_VTU_SID);
1719                         if (ret < 0)
1720                                 return ret;
1721
1722                         next.sid = ret & GLOBAL_VTU_SID_MASK;
1723                 }
1724         }
1725
1726         *entry = next;
1727         return 0;
1728 }
1729
1730 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1731                                     struct switchdev_obj_port_vlan *vlan,
1732                                     int (*cb)(struct switchdev_obj *obj))
1733 {
1734         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1735         struct mv88e6xxx_vtu_stu_entry next;
1736         u16 pvid;
1737         int err;
1738
1739         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1740                 return -EOPNOTSUPP;
1741
1742         mutex_lock(&chip->reg_lock);
1743
1744         err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
1745         if (err)
1746                 goto unlock;
1747
1748         err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1749         if (err)
1750                 goto unlock;
1751
1752         do {
1753                 err = _mv88e6xxx_vtu_getnext(chip, &next);
1754                 if (err)
1755                         break;
1756
1757                 if (!next.valid)
1758                         break;
1759
1760                 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1761                         continue;
1762
1763                 /* reinit and dump this VLAN obj */
1764                 vlan->vid_begin = next.vid;
1765                 vlan->vid_end = next.vid;
1766                 vlan->flags = 0;
1767
1768                 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1769                         vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1770
1771                 if (next.vid == pvid)
1772                         vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1773
1774                 err = cb(&vlan->obj);
1775                 if (err)
1776                         break;
1777         } while (next.vid < GLOBAL_VTU_VID_MASK);
1778
1779 unlock:
1780         mutex_unlock(&chip->reg_lock);
1781
1782         return err;
1783 }
1784
1785 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1786                                     struct mv88e6xxx_vtu_stu_entry *entry)
1787 {
1788         u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
1789         u16 reg = 0;
1790         int ret;
1791
1792         ret = _mv88e6xxx_vtu_wait(chip);
1793         if (ret < 0)
1794                 return ret;
1795
1796         if (!entry->valid)
1797                 goto loadpurge;
1798
1799         /* Write port member tags */
1800         ret = mv88e6xxx_vtu_data_write(chip, entry);
1801         if (ret < 0)
1802                 return ret;
1803
1804         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1805                 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1806                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1807                                            reg);
1808                 if (ret < 0)
1809                         return ret;
1810         }
1811
1812         if (mv88e6xxx_has_fid_reg(chip)) {
1813                 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1814                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_FID,
1815                                            reg);
1816                 if (ret < 0)
1817                         return ret;
1818         } else if (mv88e6xxx_num_databases(chip) == 256) {
1819                 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1820                  * VTU DBNum[3:0] are located in VTU Operation 3:0
1821                  */
1822                 op |= (entry->fid & 0xf0) << 8;
1823                 op |= entry->fid & 0xf;
1824         }
1825
1826         reg = GLOBAL_VTU_VID_VALID;
1827 loadpurge:
1828         reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1829         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1830         if (ret < 0)
1831                 return ret;
1832
1833         return _mv88e6xxx_vtu_cmd(chip, op);
1834 }
1835
1836 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
1837                                   struct mv88e6xxx_vtu_stu_entry *entry)
1838 {
1839         struct mv88e6xxx_vtu_stu_entry next = { 0 };
1840         int ret;
1841
1842         ret = _mv88e6xxx_vtu_wait(chip);
1843         if (ret < 0)
1844                 return ret;
1845
1846         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1847                                    sid & GLOBAL_VTU_SID_MASK);
1848         if (ret < 0)
1849                 return ret;
1850
1851         ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1852         if (ret < 0)
1853                 return ret;
1854
1855         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_SID);
1856         if (ret < 0)
1857                 return ret;
1858
1859         next.sid = ret & GLOBAL_VTU_SID_MASK;
1860
1861         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
1862         if (ret < 0)
1863                 return ret;
1864
1865         next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1866
1867         if (next.valid) {
1868                 ret = mv88e6xxx_stu_data_read(chip, &next);
1869                 if (ret < 0)
1870                         return ret;
1871         }
1872
1873         *entry = next;
1874         return 0;
1875 }
1876
1877 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1878                                     struct mv88e6xxx_vtu_stu_entry *entry)
1879 {
1880         u16 reg = 0;
1881         int ret;
1882
1883         ret = _mv88e6xxx_vtu_wait(chip);
1884         if (ret < 0)
1885                 return ret;
1886
1887         if (!entry->valid)
1888                 goto loadpurge;
1889
1890         /* Write port states */
1891         ret = mv88e6xxx_stu_data_write(chip, entry);
1892         if (ret < 0)
1893                 return ret;
1894
1895         reg = GLOBAL_VTU_VID_VALID;
1896 loadpurge:
1897         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1898         if (ret < 0)
1899                 return ret;
1900
1901         reg = entry->sid & GLOBAL_VTU_SID_MASK;
1902         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1903         if (ret < 0)
1904                 return ret;
1905
1906         return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1907 }
1908
1909 static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip *chip, int port,
1910                                u16 *new, u16 *old)
1911 {
1912         struct dsa_switch *ds = chip->ds;
1913         u16 upper_mask;
1914         u16 fid;
1915         int ret;
1916
1917         if (mv88e6xxx_num_databases(chip) == 4096)
1918                 upper_mask = 0xff;
1919         else if (mv88e6xxx_num_databases(chip) == 256)
1920                 upper_mask = 0xf;
1921         else
1922                 return -EOPNOTSUPP;
1923
1924         /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1925         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
1926         if (ret < 0)
1927                 return ret;
1928
1929         fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1930
1931         if (new) {
1932                 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1933                 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1934
1935                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN,
1936                                            ret);
1937                 if (ret < 0)
1938                         return ret;
1939         }
1940
1941         /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1942         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_1);
1943         if (ret < 0)
1944                 return ret;
1945
1946         fid |= (ret & upper_mask) << 4;
1947
1948         if (new) {
1949                 ret &= ~upper_mask;
1950                 ret |= (*new >> 4) & upper_mask;
1951
1952                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
1953                                            ret);
1954                 if (ret < 0)
1955                         return ret;
1956
1957                 netdev_dbg(ds->ports[port].netdev,
1958                            "FID %d (was %d)\n", *new, fid);
1959         }
1960
1961         if (old)
1962                 *old = fid;
1963
1964         return 0;
1965 }
1966
1967 static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_chip *chip,
1968                                    int port, u16 *fid)
1969 {
1970         return _mv88e6xxx_port_fid(chip, port, NULL, fid);
1971 }
1972
1973 static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_chip *chip,
1974                                    int port, u16 fid)
1975 {
1976         return _mv88e6xxx_port_fid(chip, port, &fid, NULL);
1977 }
1978
1979 static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
1980 {
1981         DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1982         struct mv88e6xxx_vtu_stu_entry vlan;
1983         int i, err;
1984
1985         bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1986
1987         /* Set every FID bit used by the (un)bridged ports */
1988         for (i = 0; i < chip->info->num_ports; ++i) {
1989                 err = _mv88e6xxx_port_fid_get(chip, i, fid);
1990                 if (err)
1991                         return err;
1992
1993                 set_bit(*fid, fid_bitmap);
1994         }
1995
1996         /* Set every FID bit used by the VLAN entries */
1997         err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1998         if (err)
1999                 return err;
2000
2001         do {
2002                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
2003                 if (err)
2004                         return err;
2005
2006                 if (!vlan.valid)
2007                         break;
2008
2009                 set_bit(vlan.fid, fid_bitmap);
2010         } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2011
2012         /* The reset value 0x000 is used to indicate that multiple address
2013          * databases are not needed. Return the next positive available.
2014          */
2015         *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
2016         if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
2017                 return -ENOSPC;
2018
2019         /* Clear the database */
2020         return _mv88e6xxx_atu_flush(chip, *fid, true);
2021 }
2022
2023 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
2024                               struct mv88e6xxx_vtu_stu_entry *entry)
2025 {
2026         struct dsa_switch *ds = chip->ds;
2027         struct mv88e6xxx_vtu_stu_entry vlan = {
2028                 .valid = true,
2029                 .vid = vid,
2030         };
2031         int i, err;
2032
2033         err = _mv88e6xxx_fid_new(chip, &vlan.fid);
2034         if (err)
2035                 return err;
2036
2037         /* exclude all ports except the CPU and DSA ports */
2038         for (i = 0; i < chip->info->num_ports; ++i)
2039                 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
2040                         ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
2041                         : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2042
2043         if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
2044             mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
2045                 struct mv88e6xxx_vtu_stu_entry vstp;
2046
2047                 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
2048                  * implemented, only one STU entry is needed to cover all VTU
2049                  * entries. Thus, validate the SID 0.
2050                  */
2051                 vlan.sid = 0;
2052                 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
2053                 if (err)
2054                         return err;
2055
2056                 if (vstp.sid != vlan.sid || !vstp.valid) {
2057                         memset(&vstp, 0, sizeof(vstp));
2058                         vstp.valid = true;
2059                         vstp.sid = vlan.sid;
2060
2061                         err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
2062                         if (err)
2063                                 return err;
2064                 }
2065         }
2066
2067         *entry = vlan;
2068         return 0;
2069 }
2070
2071 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
2072                               struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
2073 {
2074         int err;
2075
2076         if (!vid)
2077                 return -EINVAL;
2078
2079         err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
2080         if (err)
2081                 return err;
2082
2083         err = _mv88e6xxx_vtu_getnext(chip, entry);
2084         if (err)
2085                 return err;
2086
2087         if (entry->vid != vid || !entry->valid) {
2088                 if (!creat)
2089                         return -EOPNOTSUPP;
2090                 /* -ENOENT would've been more appropriate, but switchdev expects
2091                  * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
2092                  */
2093
2094                 err = _mv88e6xxx_vtu_new(chip, vid, entry);
2095         }
2096
2097         return err;
2098 }
2099
2100 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
2101                                         u16 vid_begin, u16 vid_end)
2102 {
2103         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2104         struct mv88e6xxx_vtu_stu_entry vlan;
2105         int i, err;
2106
2107         if (!vid_begin)
2108                 return -EOPNOTSUPP;
2109
2110         mutex_lock(&chip->reg_lock);
2111
2112         err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
2113         if (err)
2114                 goto unlock;
2115
2116         do {
2117                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
2118                 if (err)
2119                         goto unlock;
2120
2121                 if (!vlan.valid)
2122                         break;
2123
2124                 if (vlan.vid > vid_end)
2125                         break;
2126
2127                 for (i = 0; i < chip->info->num_ports; ++i) {
2128                         if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
2129                                 continue;
2130
2131                         if (vlan.data[i] ==
2132                             GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2133                                 continue;
2134
2135                         if (chip->ports[i].bridge_dev ==
2136                             chip->ports[port].bridge_dev)
2137                                 break; /* same bridge, check next VLAN */
2138
2139                         netdev_warn(ds->ports[port].netdev,
2140                                     "hardware VLAN %d already used by %s\n",
2141                                     vlan.vid,
2142                                     netdev_name(chip->ports[i].bridge_dev));
2143                         err = -EOPNOTSUPP;
2144                         goto unlock;
2145                 }
2146         } while (vlan.vid < vid_end);
2147
2148 unlock:
2149         mutex_unlock(&chip->reg_lock);
2150
2151         return err;
2152 }
2153
2154 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
2155         [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
2156         [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
2157         [PORT_CONTROL_2_8021Q_CHECK] = "Check",
2158         [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
2159 };
2160
2161 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
2162                                          bool vlan_filtering)
2163 {
2164         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2165         u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
2166                 PORT_CONTROL_2_8021Q_DISABLED;
2167         int ret;
2168
2169         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
2170                 return -EOPNOTSUPP;
2171
2172         mutex_lock(&chip->reg_lock);
2173
2174         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_2);
2175         if (ret < 0)
2176                 goto unlock;
2177
2178         old = ret & PORT_CONTROL_2_8021Q_MASK;
2179
2180         if (new != old) {
2181                 ret &= ~PORT_CONTROL_2_8021Q_MASK;
2182                 ret |= new & PORT_CONTROL_2_8021Q_MASK;
2183
2184                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_2,
2185                                            ret);
2186                 if (ret < 0)
2187                         goto unlock;
2188
2189                 netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n",
2190                            mv88e6xxx_port_8021q_mode_names[new],
2191                            mv88e6xxx_port_8021q_mode_names[old]);
2192         }
2193
2194         ret = 0;
2195 unlock:
2196         mutex_unlock(&chip->reg_lock);
2197
2198         return ret;
2199 }
2200
2201 static int
2202 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
2203                             const struct switchdev_obj_port_vlan *vlan,
2204                             struct switchdev_trans *trans)
2205 {
2206         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2207         int err;
2208
2209         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
2210                 return -EOPNOTSUPP;
2211
2212         /* If the requested port doesn't belong to the same bridge as the VLAN
2213          * members, do not support it (yet) and fallback to software VLAN.
2214          */
2215         err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
2216                                            vlan->vid_end);
2217         if (err)
2218                 return err;
2219
2220         /* We don't need any dynamic resource from the kernel (yet),
2221          * so skip the prepare phase.
2222          */
2223         return 0;
2224 }
2225
2226 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
2227                                     u16 vid, bool untagged)
2228 {
2229         struct mv88e6xxx_vtu_stu_entry vlan;
2230         int err;
2231
2232         err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
2233         if (err)
2234                 return err;
2235
2236         vlan.data[port] = untagged ?
2237                 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
2238                 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
2239
2240         return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
2241 }
2242
2243 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2244                                     const struct switchdev_obj_port_vlan *vlan,
2245                                     struct switchdev_trans *trans)
2246 {
2247         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2248         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2249         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2250         u16 vid;
2251
2252         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
2253                 return;
2254
2255         mutex_lock(&chip->reg_lock);
2256
2257         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
2258                 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
2259                         netdev_err(ds->ports[port].netdev,
2260                                    "failed to add VLAN %d%c\n",
2261                                    vid, untagged ? 'u' : 't');
2262
2263         if (pvid && _mv88e6xxx_port_pvid_set(chip, port, vlan->vid_end))
2264                 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
2265                            vlan->vid_end);
2266
2267         mutex_unlock(&chip->reg_lock);
2268 }
2269
2270 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
2271                                     int port, u16 vid)
2272 {
2273         struct dsa_switch *ds = chip->ds;
2274         struct mv88e6xxx_vtu_stu_entry vlan;
2275         int i, err;
2276
2277         err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
2278         if (err)
2279                 return err;
2280
2281         /* Tell switchdev if this VLAN is handled in software */
2282         if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2283                 return -EOPNOTSUPP;
2284
2285         vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2286
2287         /* keep the VLAN unless all ports are excluded */
2288         vlan.valid = false;
2289         for (i = 0; i < chip->info->num_ports; ++i) {
2290                 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
2291                         continue;
2292
2293                 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2294                         vlan.valid = true;
2295                         break;
2296                 }
2297         }
2298
2299         err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
2300         if (err)
2301                 return err;
2302
2303         return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
2304 }
2305
2306 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2307                                    const struct switchdev_obj_port_vlan *vlan)
2308 {
2309         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2310         u16 pvid, vid;
2311         int err = 0;
2312
2313         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
2314                 return -EOPNOTSUPP;
2315
2316         mutex_lock(&chip->reg_lock);
2317
2318         err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
2319         if (err)
2320                 goto unlock;
2321
2322         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
2323                 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
2324                 if (err)
2325                         goto unlock;
2326
2327                 if (vid == pvid) {
2328                         err = _mv88e6xxx_port_pvid_set(chip, port, 0);
2329                         if (err)
2330                                 goto unlock;
2331                 }
2332         }
2333
2334 unlock:
2335         mutex_unlock(&chip->reg_lock);
2336
2337         return err;
2338 }
2339
2340 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
2341                                     const unsigned char *addr)
2342 {
2343         int i, ret;
2344
2345         for (i = 0; i < 3; i++) {
2346                 ret = _mv88e6xxx_reg_write(
2347                         chip, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
2348                         (addr[i * 2] << 8) | addr[i * 2 + 1]);
2349                 if (ret < 0)
2350                         return ret;
2351         }
2352
2353         return 0;
2354 }
2355
2356 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
2357                                    unsigned char *addr)
2358 {
2359         int i, ret;
2360
2361         for (i = 0; i < 3; i++) {
2362                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
2363                                           GLOBAL_ATU_MAC_01 + i);
2364                 if (ret < 0)
2365                         return ret;
2366                 addr[i * 2] = ret >> 8;
2367                 addr[i * 2 + 1] = ret & 0xff;
2368         }
2369
2370         return 0;
2371 }
2372
2373 static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
2374                                struct mv88e6xxx_atu_entry *entry)
2375 {
2376         int ret;
2377
2378         ret = _mv88e6xxx_atu_wait(chip);
2379         if (ret < 0)
2380                 return ret;
2381
2382         ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
2383         if (ret < 0)
2384                 return ret;
2385
2386         ret = _mv88e6xxx_atu_data_write(chip, entry);
2387         if (ret < 0)
2388                 return ret;
2389
2390         return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
2391 }
2392
2393 static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_chip *chip, int port,
2394                                     const unsigned char *addr, u16 vid,
2395                                     u8 state)
2396 {
2397         struct mv88e6xxx_atu_entry entry = { 0 };
2398         struct mv88e6xxx_vtu_stu_entry vlan;
2399         int err;
2400
2401         /* Null VLAN ID corresponds to the port private database */
2402         if (vid == 0)
2403                 err = _mv88e6xxx_port_fid_get(chip, port, &vlan.fid);
2404         else
2405                 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
2406         if (err)
2407                 return err;
2408
2409         entry.fid = vlan.fid;
2410         entry.state = state;
2411         ether_addr_copy(entry.mac, addr);
2412         if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2413                 entry.trunk = false;
2414                 entry.portv_trunkid = BIT(port);
2415         }
2416
2417         return _mv88e6xxx_atu_load(chip, &entry);
2418 }
2419
2420 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2421                                       const struct switchdev_obj_port_fdb *fdb,
2422                                       struct switchdev_trans *trans)
2423 {
2424         /* We don't need any dynamic resource from the kernel (yet),
2425          * so skip the prepare phase.
2426          */
2427         return 0;
2428 }
2429
2430 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2431                                    const struct switchdev_obj_port_fdb *fdb,
2432                                    struct switchdev_trans *trans)
2433 {
2434         int state = is_multicast_ether_addr(fdb->addr) ?
2435                 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2436                 GLOBAL_ATU_DATA_STATE_UC_STATIC;
2437         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2438
2439         mutex_lock(&chip->reg_lock);
2440         if (_mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid, state))
2441                 netdev_err(ds->ports[port].netdev,
2442                            "failed to load MAC address\n");
2443         mutex_unlock(&chip->reg_lock);
2444 }
2445
2446 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2447                                   const struct switchdev_obj_port_fdb *fdb)
2448 {
2449         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2450         int ret;
2451
2452         mutex_lock(&chip->reg_lock);
2453         ret = _mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid,
2454                                        GLOBAL_ATU_DATA_STATE_UNUSED);
2455         mutex_unlock(&chip->reg_lock);
2456
2457         return ret;
2458 }
2459
2460 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2461                                   struct mv88e6xxx_atu_entry *entry)
2462 {
2463         struct mv88e6xxx_atu_entry next = { 0 };
2464         int ret;
2465
2466         next.fid = fid;
2467
2468         ret = _mv88e6xxx_atu_wait(chip);
2469         if (ret < 0)
2470                 return ret;
2471
2472         ret = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2473         if (ret < 0)
2474                 return ret;
2475
2476         ret = _mv88e6xxx_atu_mac_read(chip, next.mac);
2477         if (ret < 0)
2478                 return ret;
2479
2480         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_DATA);
2481         if (ret < 0)
2482                 return ret;
2483
2484         next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2485         if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2486                 unsigned int mask, shift;
2487
2488                 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2489                         next.trunk = true;
2490                         mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2491                         shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2492                 } else {
2493                         next.trunk = false;
2494                         mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2495                         shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2496                 }
2497
2498                 next.portv_trunkid = (ret & mask) >> shift;
2499         }
2500
2501         *entry = next;
2502         return 0;
2503 }
2504
2505 static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_chip *chip,
2506                                         u16 fid, u16 vid, int port,
2507                                         struct switchdev_obj_port_fdb *fdb,
2508                                         int (*cb)(struct switchdev_obj *obj))
2509 {
2510         struct mv88e6xxx_atu_entry addr = {
2511                 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2512         };
2513         int err;
2514
2515         err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
2516         if (err)
2517                 return err;
2518
2519         do {
2520                 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
2521                 if (err)
2522                         break;
2523
2524                 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2525                         break;
2526
2527                 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2528                         bool is_static = addr.state ==
2529                                 (is_multicast_ether_addr(addr.mac) ?
2530                                  GLOBAL_ATU_DATA_STATE_MC_STATIC :
2531                                  GLOBAL_ATU_DATA_STATE_UC_STATIC);
2532
2533                         fdb->vid = vid;
2534                         ether_addr_copy(fdb->addr, addr.mac);
2535                         fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2536
2537                         err = cb(&fdb->obj);
2538                         if (err)
2539                                 break;
2540                 }
2541         } while (!is_broadcast_ether_addr(addr.mac));
2542
2543         return err;
2544 }
2545
2546 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2547                                    struct switchdev_obj_port_fdb *fdb,
2548                                    int (*cb)(struct switchdev_obj *obj))
2549 {
2550         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2551         struct mv88e6xxx_vtu_stu_entry vlan = {
2552                 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2553         };
2554         u16 fid;
2555         int err;
2556
2557         mutex_lock(&chip->reg_lock);
2558
2559         /* Dump port's default Filtering Information Database (VLAN ID 0) */
2560         err = _mv88e6xxx_port_fid_get(chip, port, &fid);
2561         if (err)
2562                 goto unlock;
2563
2564         err = _mv88e6xxx_port_fdb_dump_one(chip, fid, 0, port, fdb, cb);
2565         if (err)
2566                 goto unlock;
2567
2568         /* Dump VLANs' Filtering Information Databases */
2569         err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
2570         if (err)
2571                 goto unlock;
2572
2573         do {
2574                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
2575                 if (err)
2576                         break;
2577
2578                 if (!vlan.valid)
2579                         break;
2580
2581                 err = _mv88e6xxx_port_fdb_dump_one(chip, vlan.fid, vlan.vid,
2582                                                    port, fdb, cb);
2583                 if (err)
2584                         break;
2585         } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2586
2587 unlock:
2588         mutex_unlock(&chip->reg_lock);
2589
2590         return err;
2591 }
2592
2593 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2594                                       struct net_device *bridge)
2595 {
2596         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2597         int i, err = 0;
2598
2599         mutex_lock(&chip->reg_lock);
2600
2601         /* Assign the bridge and remap each port's VLANTable */
2602         chip->ports[port].bridge_dev = bridge;
2603
2604         for (i = 0; i < chip->info->num_ports; ++i) {
2605                 if (chip->ports[i].bridge_dev == bridge) {
2606                         err = _mv88e6xxx_port_based_vlan_map(chip, i);
2607                         if (err)
2608                                 break;
2609                 }
2610         }
2611
2612         mutex_unlock(&chip->reg_lock);
2613
2614         return err;
2615 }
2616
2617 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2618 {
2619         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2620         struct net_device *bridge = chip->ports[port].bridge_dev;
2621         int i;
2622
2623         mutex_lock(&chip->reg_lock);
2624
2625         /* Unassign the bridge and remap each port's VLANTable */
2626         chip->ports[port].bridge_dev = NULL;
2627
2628         for (i = 0; i < chip->info->num_ports; ++i)
2629                 if (i == port || chip->ports[i].bridge_dev == bridge)
2630                         if (_mv88e6xxx_port_based_vlan_map(chip, i))
2631                                 netdev_warn(ds->ports[i].netdev,
2632                                             "failed to remap\n");
2633
2634         mutex_unlock(&chip->reg_lock);
2635 }
2636
2637 static int _mv88e6xxx_mdio_page_write(struct mv88e6xxx_chip *chip,
2638                                       int port, int page, int reg, int val)
2639 {
2640         int ret;
2641
2642         ret = mv88e6xxx_mdio_write_indirect(chip, port, 0x16, page);
2643         if (ret < 0)
2644                 goto restore_page_0;
2645
2646         ret = mv88e6xxx_mdio_write_indirect(chip, port, reg, val);
2647 restore_page_0:
2648         mv88e6xxx_mdio_write_indirect(chip, port, 0x16, 0x0);
2649
2650         return ret;
2651 }
2652
2653 static int _mv88e6xxx_mdio_page_read(struct mv88e6xxx_chip *chip,
2654                                      int port, int page, int reg)
2655 {
2656         int ret;
2657
2658         ret = mv88e6xxx_mdio_write_indirect(chip, port, 0x16, page);
2659         if (ret < 0)
2660                 goto restore_page_0;
2661
2662         ret = mv88e6xxx_mdio_read_indirect(chip, port, reg);
2663 restore_page_0:
2664         mv88e6xxx_mdio_write_indirect(chip, port, 0x16, 0x0);
2665
2666         return ret;
2667 }
2668
2669 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2670 {
2671         bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
2672         u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2673         struct gpio_desc *gpiod = chip->reset;
2674         unsigned long timeout;
2675         int ret;
2676         int i;
2677
2678         /* Set all ports to the disabled state. */
2679         for (i = 0; i < chip->info->num_ports; i++) {
2680                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(i), PORT_CONTROL);
2681                 if (ret < 0)
2682                         return ret;
2683
2684                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(i), PORT_CONTROL,
2685                                            ret & 0xfffc);
2686                 if (ret)
2687                         return ret;
2688         }
2689
2690         /* Wait for transmit queues to drain. */
2691         usleep_range(2000, 4000);
2692
2693         /* If there is a gpio connected to the reset pin, toggle it */
2694         if (gpiod) {
2695                 gpiod_set_value_cansleep(gpiod, 1);
2696                 usleep_range(10000, 20000);
2697                 gpiod_set_value_cansleep(gpiod, 0);
2698                 usleep_range(10000, 20000);
2699         }
2700
2701         /* Reset the switch. Keep the PPU active if requested. The PPU
2702          * needs to be active to support indirect phy register access
2703          * through global registers 0x18 and 0x19.
2704          */
2705         if (ppu_active)
2706                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc000);
2707         else
2708                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc400);
2709         if (ret)
2710                 return ret;
2711
2712         /* Wait up to one second for reset to complete. */
2713         timeout = jiffies + 1 * HZ;
2714         while (time_before(jiffies, timeout)) {
2715                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, 0x00);
2716                 if (ret < 0)
2717                         return ret;
2718
2719                 if ((ret & is_reset) == is_reset)
2720                         break;
2721                 usleep_range(1000, 2000);
2722         }
2723         if (time_after(jiffies, timeout))
2724                 ret = -ETIMEDOUT;
2725         else
2726                 ret = 0;
2727
2728         return ret;
2729 }
2730
2731 static int mv88e6xxx_power_on_serdes(struct mv88e6xxx_chip *chip)
2732 {
2733         int ret;
2734
2735         ret = _mv88e6xxx_mdio_page_read(chip, REG_FIBER_SERDES,
2736                                         PAGE_FIBER_SERDES, MII_BMCR);
2737         if (ret < 0)
2738                 return ret;
2739
2740         if (ret & BMCR_PDOWN) {
2741                 ret &= ~BMCR_PDOWN;
2742                 ret = _mv88e6xxx_mdio_page_write(chip, REG_FIBER_SERDES,
2743                                                  PAGE_FIBER_SERDES, MII_BMCR,
2744                                                  ret);
2745         }
2746
2747         return ret;
2748 }
2749
2750 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2751 {
2752         struct dsa_switch *ds = chip->ds;
2753         int ret;
2754         u16 reg;
2755
2756         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2757             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2758             mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2759             mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) {
2760                 /* MAC Forcing register: don't force link, speed,
2761                  * duplex or flow control state to any particular
2762                  * values on physical ports, but force the CPU port
2763                  * and all DSA ports to their maximum bandwidth and
2764                  * full duplex.
2765                  */
2766                 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
2767                 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
2768                         reg &= ~PORT_PCS_CTRL_UNFORCED;
2769                         reg |= PORT_PCS_CTRL_FORCE_LINK |
2770                                 PORT_PCS_CTRL_LINK_UP |
2771                                 PORT_PCS_CTRL_DUPLEX_FULL |
2772                                 PORT_PCS_CTRL_FORCE_DUPLEX;
2773                         if (mv88e6xxx_6065_family(chip))
2774                                 reg |= PORT_PCS_CTRL_100;
2775                         else
2776                                 reg |= PORT_PCS_CTRL_1000;
2777                 } else {
2778                         reg |= PORT_PCS_CTRL_UNFORCED;
2779                 }
2780
2781                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2782                                            PORT_PCS_CTRL, reg);
2783                 if (ret)
2784                         return ret;
2785         }
2786
2787         /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2788          * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2789          * tunneling, determine priority by looking at 802.1p and IP
2790          * priority fields (IP prio has precedence), and set STP state
2791          * to Forwarding.
2792          *
2793          * If this is the CPU link, use DSA or EDSA tagging depending
2794          * on which tagging mode was configured.
2795          *
2796          * If this is a link to another switch, use DSA tagging mode.
2797          *
2798          * If this is the upstream port for this switch, enable
2799          * forwarding of unknown unicasts and multicasts.
2800          */
2801         reg = 0;
2802         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2803             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2804             mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2805             mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
2806                 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2807                 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2808                 PORT_CONTROL_STATE_FORWARDING;
2809         if (dsa_is_cpu_port(ds, port)) {
2810                 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip))
2811                         reg |= PORT_CONTROL_DSA_TAG;
2812                 if (mv88e6xxx_6352_family(chip) ||
2813                     mv88e6xxx_6351_family(chip) ||
2814                     mv88e6xxx_6165_family(chip) ||
2815                     mv88e6xxx_6097_family(chip) ||
2816                     mv88e6xxx_6320_family(chip)) {
2817                         reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
2818                                 PORT_CONTROL_FORWARD_UNKNOWN |
2819                                 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2820                 }
2821
2822                 if (mv88e6xxx_6352_family(chip) ||
2823                     mv88e6xxx_6351_family(chip) ||
2824                     mv88e6xxx_6165_family(chip) ||
2825                     mv88e6xxx_6097_family(chip) ||
2826                     mv88e6xxx_6095_family(chip) ||
2827                     mv88e6xxx_6065_family(chip) ||
2828                     mv88e6xxx_6185_family(chip) ||
2829                     mv88e6xxx_6320_family(chip)) {
2830                         reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2831                 }
2832         }
2833         if (dsa_is_dsa_port(ds, port)) {
2834                 if (mv88e6xxx_6095_family(chip) ||
2835                     mv88e6xxx_6185_family(chip))
2836                         reg |= PORT_CONTROL_DSA_TAG;
2837                 if (mv88e6xxx_6352_family(chip) ||
2838                     mv88e6xxx_6351_family(chip) ||
2839                     mv88e6xxx_6165_family(chip) ||
2840                     mv88e6xxx_6097_family(chip) ||
2841                     mv88e6xxx_6320_family(chip)) {
2842                         reg |= PORT_CONTROL_FRAME_MODE_DSA;
2843                 }
2844
2845                 if (port == dsa_upstream_port(ds))
2846                         reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2847                                 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2848         }
2849         if (reg) {
2850                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2851                                            PORT_CONTROL, reg);
2852                 if (ret)
2853                         return ret;
2854         }
2855
2856         /* If this port is connected to a SerDes, make sure the SerDes is not
2857          * powered down.
2858          */
2859         if (mv88e6xxx_6352_family(chip)) {
2860                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
2861                 if (ret < 0)
2862                         return ret;
2863                 ret &= PORT_STATUS_CMODE_MASK;
2864                 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2865                     (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2866                     (ret == PORT_STATUS_CMODE_SGMII)) {
2867                         ret = mv88e6xxx_power_on_serdes(chip);
2868                         if (ret < 0)
2869                                 return ret;
2870                 }
2871         }
2872
2873         /* Port Control 2: don't force a good FCS, set the maximum frame size to
2874          * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2875          * untagged frames on this port, do a destination address lookup on all
2876          * received packets as usual, disable ARP mirroring and don't send a
2877          * copy of all transmitted/received frames on this port to the CPU.
2878          */
2879         reg = 0;
2880         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2881             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2882             mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2883             mv88e6xxx_6185_family(chip))
2884                 reg = PORT_CONTROL_2_MAP_DA;
2885
2886         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2887             mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
2888                 reg |= PORT_CONTROL_2_JUMBO_10240;
2889
2890         if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
2891                 /* Set the upstream port this port should use */
2892                 reg |= dsa_upstream_port(ds);
2893                 /* enable forwarding of unknown multicast addresses to
2894                  * the upstream port
2895                  */
2896                 if (port == dsa_upstream_port(ds))
2897                         reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2898         }
2899
2900         reg |= PORT_CONTROL_2_8021Q_DISABLED;
2901
2902         if (reg) {
2903                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2904                                            PORT_CONTROL_2, reg);
2905                 if (ret)
2906                         return ret;
2907         }
2908
2909         /* Port Association Vector: when learning source addresses
2910          * of packets, add the address to the address database using
2911          * a port bitmap that has only the bit for this port set and
2912          * the other bits clear.
2913          */
2914         reg = 1 << port;
2915         /* Disable learning for CPU port */
2916         if (dsa_is_cpu_port(ds, port))
2917                 reg = 0;
2918
2919         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_ASSOC_VECTOR,
2920                                    reg);
2921         if (ret)
2922                 return ret;
2923
2924         /* Egress rate control 2: disable egress rate control. */
2925         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_RATE_CONTROL_2,
2926                                    0x0000);
2927         if (ret)
2928                 return ret;
2929
2930         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2931             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2932             mv88e6xxx_6320_family(chip)) {
2933                 /* Do not limit the period of time that this port can
2934                  * be paused for by the remote end or the period of
2935                  * time that this port can pause the remote end.
2936                  */
2937                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2938                                            PORT_PAUSE_CTRL, 0x0000);
2939                 if (ret)
2940                         return ret;
2941
2942                 /* Port ATU control: disable limiting the number of
2943                  * address database entries that this port is allowed
2944                  * to use.
2945                  */
2946                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2947                                            PORT_ATU_CONTROL, 0x0000);
2948                 /* Priority Override: disable DA, SA and VTU priority
2949                  * override.
2950                  */
2951                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2952                                            PORT_PRI_OVERRIDE, 0x0000);
2953                 if (ret)
2954                         return ret;
2955
2956                 /* Port Ethertype: use the Ethertype DSA Ethertype
2957                  * value.
2958                  */
2959                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2960                                            PORT_ETH_TYPE, ETH_P_EDSA);
2961                 if (ret)
2962                         return ret;
2963                 /* Tag Remap: use an identity 802.1p prio -> switch
2964                  * prio mapping.
2965                  */
2966                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2967                                            PORT_TAG_REGMAP_0123, 0x3210);
2968                 if (ret)
2969                         return ret;
2970
2971                 /* Tag Remap 2: use an identity 802.1p prio -> switch
2972                  * prio mapping.
2973                  */
2974                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2975                                            PORT_TAG_REGMAP_4567, 0x7654);
2976                 if (ret)
2977                         return ret;
2978         }
2979
2980         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2981             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2982             mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2983             mv88e6xxx_6320_family(chip)) {
2984                 /* Rate Control: disable ingress rate limiting. */
2985                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2986                                            PORT_RATE_CONTROL, 0x0001);
2987                 if (ret)
2988                         return ret;
2989         }
2990
2991         /* Port Control 1: disable trunking, disable sending
2992          * learning messages to this port.
2993          */
2994         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
2995                                    0x0000);
2996         if (ret)
2997                 return ret;
2998
2999         /* Port based VLAN map: give each port the same default address
3000          * database, and allow bidirectional communication between the
3001          * CPU and DSA port(s), and the other ports.
3002          */
3003         ret = _mv88e6xxx_port_fid_set(chip, port, 0);
3004         if (ret)
3005                 return ret;
3006
3007         ret = _mv88e6xxx_port_based_vlan_map(chip, port);
3008         if (ret)
3009                 return ret;
3010
3011         /* Default VLAN ID and priority: don't set a default VLAN
3012          * ID, and set the default packet priority to zero.
3013          */
3014         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_DEFAULT_VLAN,
3015                                    0x0000);
3016         if (ret)
3017                 return ret;
3018
3019         return 0;
3020 }
3021
3022 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
3023 {
3024         struct dsa_switch *ds = chip->ds;
3025         u32 upstream_port = dsa_upstream_port(ds);
3026         u16 reg;
3027         int err;
3028
3029         /* Enable the PHY Polling Unit if present, don't discard any packets,
3030          * and mask all interrupt sources.
3031          */
3032         reg = 0;
3033         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
3034             mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
3035                 reg |= GLOBAL_CONTROL_PPU_ENABLE;
3036
3037         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL, reg);
3038         if (err)
3039                 return err;
3040
3041         /* Configure the upstream port, and configure it as the port to which
3042          * ingress and egress and ARP monitor frames are to be sent.
3043          */
3044         reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
3045                 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
3046                 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
3047         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MONITOR_CONTROL,
3048                                    reg);
3049         if (err)
3050                 return err;
3051
3052         /* Disable remote management, and set the switch's DSA device number. */
3053         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL_2,
3054                                    GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
3055                                    (ds->index & 0x1f));
3056         if (err)
3057                 return err;
3058
3059         /* Set the default address aging time to 5 minutes, and
3060          * enable address learn messages to be sent to all message
3061          * ports.
3062          */
3063         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
3064                                    0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
3065         if (err)
3066                 return err;
3067
3068         /* Clear all the VTU and STU entries */
3069         err = _mv88e6xxx_vtu_stu_flush(chip);
3070         if (err < 0)
3071                 return err;
3072
3073         /* Clear all ATU entries */
3074         err = _mv88e6xxx_atu_flush(chip, 0, true);
3075         if (err)
3076                 return err;
3077
3078         /* Configure the IP ToS mapping registers. */
3079         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
3080         if (err)
3081                 return err;
3082         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
3083         if (err)
3084                 return err;
3085         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
3086         if (err)
3087                 return err;
3088         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
3089         if (err)
3090                 return err;
3091         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
3092         if (err)
3093                 return err;
3094         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
3095         if (err)
3096                 return err;
3097         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
3098         if (err)
3099                 return err;
3100         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
3101         if (err)
3102                 return err;
3103
3104         /* Configure the IEEE 802.1p priority mapping register. */
3105         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
3106         if (err)
3107                 return err;
3108
3109         /* Clear the statistics counters for all ports */
3110         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
3111                                    GLOBAL_STATS_OP_FLUSH_ALL);
3112         if (err)
3113                 return err;
3114
3115         /* Wait for the flush to complete. */
3116         err = _mv88e6xxx_stats_wait(chip);
3117         if (err)
3118                 return err;
3119
3120         return 0;
3121 }
3122
3123 static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
3124                                              int target, int port)
3125 {
3126         u16 val = (target << 8) | (port & 0xf);
3127
3128         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING, val);
3129 }
3130
3131 static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip *chip)
3132 {
3133         int target, port;
3134         int err;
3135
3136         /* Initialize the routing port to the 32 possible target devices */
3137         for (target = 0; target < 32; ++target) {
3138                 port = 0xf;
3139
3140                 if (target < DSA_MAX_SWITCHES) {
3141                         port = chip->ds->rtable[target];
3142                         if (port == DSA_RTABLE_NONE)
3143                                 port = 0xf;
3144                 }
3145
3146                 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
3147                 if (err)
3148                         break;
3149         }
3150
3151         return err;
3152 }
3153
3154 static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
3155                                          bool hask, u16 mask)
3156 {
3157         const u16 port_mask = BIT(chip->info->num_ports) - 1;
3158         u16 val = (num << 12) | (mask & port_mask);
3159
3160         if (hask)
3161                 val |= GLOBAL2_TRUNK_MASK_HASK;
3162
3163         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MASK, val);
3164 }
3165
3166 static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
3167                                             u16 map)
3168 {
3169         const u16 port_mask = BIT(chip->info->num_ports) - 1;
3170         u16 val = (id << 11) | (map & port_mask);
3171
3172         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING, val);
3173 }
3174
3175 static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip)
3176 {
3177         const u16 port_mask = BIT(chip->info->num_ports) - 1;
3178         int i, err;
3179
3180         /* Clear all eight possible Trunk Mask vectors */
3181         for (i = 0; i < 8; ++i) {
3182                 err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask);
3183                 if (err)
3184                         return err;
3185         }
3186
3187         /* Clear all sixteen possible Trunk ID routing vectors */
3188         for (i = 0; i < 16; ++i) {
3189                 err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0);
3190                 if (err)
3191                         return err;
3192         }
3193
3194         return 0;
3195 }
3196
3197 static int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
3198 {
3199         u16 reg;
3200         int err;
3201         int i;
3202
3203         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) {
3204                 /* Consider the frames with reserved multicast destination
3205                  * addresses matching 01:80:c2:00:00:2x as MGMT.
3206                  */
3207                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_2X,
3208                                       0xffff);
3209                 if (err)
3210                         return err;
3211         }
3212
3213         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X)) {
3214                 /* Consider the frames with reserved multicast destination
3215                  * addresses matching 01:80:c2:00:00:0x as MGMT.
3216                  */
3217                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X,
3218                                       0xffff);
3219                 if (err)
3220                         return err;
3221         }
3222
3223         /* Ignore removed tag data on doubly tagged packets, disable
3224          * flow control messages, force flow control priority to the
3225          * highest, and send all special multicast frames to the CPU
3226          * port at the highest priority.
3227          */
3228         reg = GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI | (0x7 << 4);
3229         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X) ||
3230             mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X))
3231                 reg |= GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x7;
3232         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, reg);
3233         if (err)
3234                 return err;
3235
3236         /* Program the DSA routing table. */
3237         err = mv88e6xxx_g2_set_device_mapping(chip);
3238         if (err)
3239                 return err;
3240
3241         /* Clear all trunk masks and mapping. */
3242         err = mv88e6xxx_g2_clear_trunk(chip);
3243         if (err)
3244                 return err;
3245
3246         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
3247             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
3248             mv88e6xxx_6320_family(chip)) {
3249                 /* Initialise cross-chip port VLAN table to reset
3250                  * defaults.
3251                  */
3252                 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL2,
3253                                            GLOBAL2_PVT_ADDR, 0x9000);
3254                 if (err)
3255                         return err;
3256
3257                 /* Clear the priority override table. */
3258                 for (i = 0; i < 16; i++) {
3259                         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL2,
3260                                                    GLOBAL2_PRIO_OVERRIDE,
3261                                                    0x8000 | (i << 8));
3262                         if (err)
3263                                 return err;
3264                 }
3265         }
3266
3267         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
3268             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
3269             mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
3270             mv88e6xxx_6320_family(chip)) {
3271                 /* Disable ingress rate limiting by resetting all
3272                  * ingress rate limit registers to their initial
3273                  * state.
3274                  */
3275                 for (i = 0; i < chip->info->num_ports; i++) {
3276                         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL2,
3277                                                    GLOBAL2_INGRESS_OP,
3278                                                    0x9000 | (i << 8));
3279                         if (err)
3280                                 return err;
3281                 }
3282         }
3283
3284         return 0;
3285 }
3286
3287 static int mv88e6xxx_setup(struct dsa_switch *ds)
3288 {
3289         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3290         int err;
3291         int i;
3292
3293         chip->ds = ds;
3294         ds->slave_mii_bus = chip->mdio_bus;
3295
3296         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEPROM))
3297                 mutex_init(&chip->eeprom_mutex);
3298
3299         mutex_lock(&chip->reg_lock);
3300
3301         err = mv88e6xxx_switch_reset(chip);
3302         if (err)
3303                 goto unlock;
3304
3305         /* Setup Switch Port Registers */
3306         for (i = 0; i < chip->info->num_ports; i++) {
3307                 err = mv88e6xxx_setup_port(chip, i);
3308                 if (err)
3309                         goto unlock;
3310         }
3311
3312         /* Setup Switch Global 1 Registers */
3313         err = mv88e6xxx_g1_setup(chip);
3314         if (err)
3315                 goto unlock;
3316
3317         /* Setup Switch Global 2 Registers */
3318         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
3319                 err = mv88e6xxx_g2_setup(chip);
3320                 if (err)
3321                         goto unlock;
3322         }
3323
3324 unlock:
3325         mutex_unlock(&chip->reg_lock);
3326
3327         return err;
3328 }
3329
3330 static int mv88e6xxx_mdio_page_read(struct dsa_switch *ds, int port, int page,
3331                                     int reg)
3332 {
3333         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3334         int ret;
3335
3336         mutex_lock(&chip->reg_lock);
3337         ret = _mv88e6xxx_mdio_page_read(chip, port, page, reg);
3338         mutex_unlock(&chip->reg_lock);
3339
3340         return ret;
3341 }
3342
3343 static int mv88e6xxx_mdio_page_write(struct dsa_switch *ds, int port, int page,
3344                                      int reg, int val)
3345 {
3346         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3347         int ret;
3348
3349         mutex_lock(&chip->reg_lock);
3350         ret = _mv88e6xxx_mdio_page_write(chip, port, page, reg, val);
3351         mutex_unlock(&chip->reg_lock);
3352
3353         return ret;
3354 }
3355
3356 static int mv88e6xxx_port_to_mdio_addr(struct mv88e6xxx_chip *chip, int port)
3357 {
3358         if (port >= 0 && port < chip->info->num_ports)
3359                 return port;
3360         return -EINVAL;
3361 }
3362
3363 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int port, int regnum)
3364 {
3365         struct mv88e6xxx_chip *chip = bus->priv;
3366         int addr = mv88e6xxx_port_to_mdio_addr(chip, port);
3367         int ret;
3368
3369         if (addr < 0)
3370                 return 0xffff;
3371
3372         mutex_lock(&chip->reg_lock);
3373
3374         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3375                 ret = mv88e6xxx_mdio_read_ppu(chip, addr, regnum);
3376         else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_SMI_PHY))
3377                 ret = mv88e6xxx_mdio_read_indirect(chip, addr, regnum);
3378         else
3379                 ret = mv88e6xxx_mdio_read_direct(chip, addr, regnum);
3380
3381         mutex_unlock(&chip->reg_lock);
3382         return ret;
3383 }
3384
3385 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int port, int regnum,
3386                                 u16 val)
3387 {
3388         struct mv88e6xxx_chip *chip = bus->priv;
3389         int addr = mv88e6xxx_port_to_mdio_addr(chip, port);
3390         int ret;
3391
3392         if (addr < 0)
3393                 return 0xffff;
3394
3395         mutex_lock(&chip->reg_lock);
3396
3397         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3398                 ret = mv88e6xxx_mdio_write_ppu(chip, addr, regnum, val);
3399         else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_SMI_PHY))
3400                 ret = mv88e6xxx_mdio_write_indirect(chip, addr, regnum, val);
3401         else
3402                 ret = mv88e6xxx_mdio_write_direct(chip, addr, regnum, val);
3403
3404         mutex_unlock(&chip->reg_lock);
3405         return ret;
3406 }
3407
3408 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3409                                    struct device_node *np)
3410 {
3411         static int index;
3412         struct mii_bus *bus;
3413         int err;
3414
3415         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3416                 mv88e6xxx_ppu_state_init(chip);
3417
3418         if (np)
3419                 chip->mdio_np = of_get_child_by_name(np, "mdio");
3420
3421         bus = devm_mdiobus_alloc(chip->dev);
3422         if (!bus)
3423                 return -ENOMEM;
3424
3425         bus->priv = (void *)chip;
3426         if (np) {
3427                 bus->name = np->full_name;
3428                 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
3429         } else {
3430                 bus->name = "mv88e6xxx SMI";
3431                 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3432         }
3433
3434         bus->read = mv88e6xxx_mdio_read;
3435         bus->write = mv88e6xxx_mdio_write;
3436         bus->parent = chip->dev;
3437
3438         if (chip->mdio_np)
3439                 err = of_mdiobus_register(bus, chip->mdio_np);
3440         else
3441                 err = mdiobus_register(bus);
3442         if (err) {
3443                 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3444                 goto out;
3445         }
3446         chip->mdio_bus = bus;
3447
3448         return 0;
3449
3450 out:
3451         if (chip->mdio_np)
3452                 of_node_put(chip->mdio_np);
3453
3454         return err;
3455 }
3456
3457 static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
3458
3459 {
3460         struct mii_bus *bus = chip->mdio_bus;
3461
3462         mdiobus_unregister(bus);
3463
3464         if (chip->mdio_np)
3465                 of_node_put(chip->mdio_np);
3466 }
3467
3468 #ifdef CONFIG_NET_DSA_HWMON
3469
3470 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3471 {
3472         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3473         int ret;
3474         int val;
3475
3476         *temp = 0;
3477
3478         mutex_lock(&chip->reg_lock);
3479
3480         ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x16, 0x6);
3481         if (ret < 0)
3482                 goto error;
3483
3484         /* Enable temperature sensor */
3485         ret = mv88e6xxx_mdio_read_direct(chip, 0x0, 0x1a);
3486         if (ret < 0)
3487                 goto error;
3488
3489         ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x1a, ret | (1 << 5));
3490         if (ret < 0)
3491                 goto error;
3492
3493         /* Wait for temperature to stabilize */
3494         usleep_range(10000, 12000);
3495
3496         val = mv88e6xxx_mdio_read_direct(chip, 0x0, 0x1a);
3497         if (val < 0) {
3498                 ret = val;
3499                 goto error;
3500         }
3501
3502         /* Disable temperature sensor */
3503         ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x1a, ret & ~(1 << 5));
3504         if (ret < 0)
3505                 goto error;
3506
3507         *temp = ((val & 0x1f) - 5) * 5;
3508
3509 error:
3510         mv88e6xxx_mdio_write_direct(chip, 0x0, 0x16, 0x0);
3511         mutex_unlock(&chip->reg_lock);
3512         return ret;
3513 }
3514
3515 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3516 {
3517         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3518         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3519         int ret;
3520
3521         *temp = 0;
3522
3523         ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 27);
3524         if (ret < 0)
3525                 return ret;
3526
3527         *temp = (ret & 0xff) - 25;
3528
3529         return 0;
3530 }
3531
3532 static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3533 {
3534         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3535
3536         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
3537                 return -EOPNOTSUPP;
3538
3539         if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
3540                 return mv88e63xx_get_temp(ds, temp);
3541
3542         return mv88e61xx_get_temp(ds, temp);
3543 }
3544
3545 static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3546 {
3547         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3548         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3549         int ret;
3550
3551         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3552                 return -EOPNOTSUPP;
3553
3554         *temp = 0;
3555
3556         ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
3557         if (ret < 0)
3558                 return ret;
3559
3560         *temp = (((ret >> 8) & 0x1f) * 5) - 25;
3561
3562         return 0;
3563 }
3564
3565 static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3566 {
3567         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3568         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3569         int ret;
3570
3571         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3572                 return -EOPNOTSUPP;
3573
3574         ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
3575         if (ret < 0)
3576                 return ret;
3577         temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3578         return mv88e6xxx_mdio_page_write(ds, phy, 6, 26,
3579                                          (ret & 0xe0ff) | (temp << 8));
3580 }
3581
3582 static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3583 {
3584         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3585         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3586         int ret;
3587
3588         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3589                 return -EOPNOTSUPP;
3590
3591         *alarm = false;
3592
3593         ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
3594         if (ret < 0)
3595                 return ret;
3596
3597         *alarm = !!(ret & 0x40);
3598
3599         return 0;
3600 }
3601 #endif /* CONFIG_NET_DSA_HWMON */
3602
3603 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3604         [MV88E6085] = {
3605                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3606                 .family = MV88E6XXX_FAMILY_6097,
3607                 .name = "Marvell 88E6085",
3608                 .num_databases = 4096,
3609                 .num_ports = 10,
3610                 .port_base_addr = 0x10,
3611                 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3612         },
3613
3614         [MV88E6095] = {
3615                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3616                 .family = MV88E6XXX_FAMILY_6095,
3617                 .name = "Marvell 88E6095/88E6095F",
3618                 .num_databases = 256,
3619                 .num_ports = 11,
3620                 .port_base_addr = 0x10,
3621                 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3622         },
3623
3624         [MV88E6123] = {
3625                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3626                 .family = MV88E6XXX_FAMILY_6165,
3627                 .name = "Marvell 88E6123",
3628                 .num_databases = 4096,
3629                 .num_ports = 3,
3630                 .port_base_addr = 0x10,
3631                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3632         },
3633
3634         [MV88E6131] = {
3635                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3636                 .family = MV88E6XXX_FAMILY_6185,
3637                 .name = "Marvell 88E6131",
3638                 .num_databases = 256,
3639                 .num_ports = 8,
3640                 .port_base_addr = 0x10,
3641                 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3642         },
3643
3644         [MV88E6161] = {
3645                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3646                 .family = MV88E6XXX_FAMILY_6165,
3647                 .name = "Marvell 88E6161",
3648                 .num_databases = 4096,
3649                 .num_ports = 6,
3650                 .port_base_addr = 0x10,
3651                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3652         },
3653
3654         [MV88E6165] = {
3655                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3656                 .family = MV88E6XXX_FAMILY_6165,
3657                 .name = "Marvell 88E6165",
3658                 .num_databases = 4096,
3659                 .num_ports = 6,
3660                 .port_base_addr = 0x10,
3661                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3662         },
3663
3664         [MV88E6171] = {
3665                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3666                 .family = MV88E6XXX_FAMILY_6351,
3667                 .name = "Marvell 88E6171",
3668                 .num_databases = 4096,
3669                 .num_ports = 7,
3670                 .port_base_addr = 0x10,
3671                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3672         },
3673
3674         [MV88E6172] = {
3675                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3676                 .family = MV88E6XXX_FAMILY_6352,
3677                 .name = "Marvell 88E6172",
3678                 .num_databases = 4096,
3679                 .num_ports = 7,
3680                 .port_base_addr = 0x10,
3681                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3682         },
3683
3684         [MV88E6175] = {
3685                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3686                 .family = MV88E6XXX_FAMILY_6351,
3687                 .name = "Marvell 88E6175",
3688                 .num_databases = 4096,
3689                 .num_ports = 7,
3690                 .port_base_addr = 0x10,
3691                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3692         },
3693
3694         [MV88E6176] = {
3695                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3696                 .family = MV88E6XXX_FAMILY_6352,
3697                 .name = "Marvell 88E6176",
3698                 .num_databases = 4096,
3699                 .num_ports = 7,
3700                 .port_base_addr = 0x10,
3701                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3702         },
3703
3704         [MV88E6185] = {
3705                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3706                 .family = MV88E6XXX_FAMILY_6185,
3707                 .name = "Marvell 88E6185",
3708                 .num_databases = 256,
3709                 .num_ports = 10,
3710                 .port_base_addr = 0x10,
3711                 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3712         },
3713
3714         [MV88E6240] = {
3715                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3716                 .family = MV88E6XXX_FAMILY_6352,
3717                 .name = "Marvell 88E6240",
3718                 .num_databases = 4096,
3719                 .num_ports = 7,
3720                 .port_base_addr = 0x10,
3721                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3722         },
3723
3724         [MV88E6320] = {
3725                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3726                 .family = MV88E6XXX_FAMILY_6320,
3727                 .name = "Marvell 88E6320",
3728                 .num_databases = 4096,
3729                 .num_ports = 7,
3730                 .port_base_addr = 0x10,
3731                 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3732         },
3733
3734         [MV88E6321] = {
3735                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3736                 .family = MV88E6XXX_FAMILY_6320,
3737                 .name = "Marvell 88E6321",
3738                 .num_databases = 4096,
3739                 .num_ports = 7,
3740                 .port_base_addr = 0x10,
3741                 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3742         },
3743
3744         [MV88E6350] = {
3745                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3746                 .family = MV88E6XXX_FAMILY_6351,
3747                 .name = "Marvell 88E6350",
3748                 .num_databases = 4096,
3749                 .num_ports = 7,
3750                 .port_base_addr = 0x10,
3751                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3752         },
3753
3754         [MV88E6351] = {
3755                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3756                 .family = MV88E6XXX_FAMILY_6351,
3757                 .name = "Marvell 88E6351",
3758                 .num_databases = 4096,
3759                 .num_ports = 7,
3760                 .port_base_addr = 0x10,
3761                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3762         },
3763
3764         [MV88E6352] = {
3765                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3766                 .family = MV88E6XXX_FAMILY_6352,
3767                 .name = "Marvell 88E6352",
3768                 .num_databases = 4096,
3769                 .num_ports = 7,
3770                 .port_base_addr = 0x10,
3771                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3772         },
3773 };
3774
3775 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3776 {
3777         int i;
3778
3779         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3780                 if (mv88e6xxx_table[i].prod_num == prod_num)
3781                         return &mv88e6xxx_table[i];
3782
3783         return NULL;
3784 }
3785
3786 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3787 {
3788         const struct mv88e6xxx_info *info;
3789         int id, prod_num, rev;
3790
3791         id = mv88e6xxx_reg_read(chip, chip->info->port_base_addr,
3792                                 PORT_SWITCH_ID);
3793         if (id < 0)
3794                 return id;
3795
3796         prod_num = (id & 0xfff0) >> 4;
3797         rev = id & 0x000f;
3798
3799         info = mv88e6xxx_lookup_info(prod_num);
3800         if (!info)
3801                 return -ENODEV;
3802
3803         /* Update the compatible info with the probed one */
3804         chip->info = info;
3805
3806         dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3807                  chip->info->prod_num, chip->info->name, rev);
3808
3809         return 0;
3810 }
3811
3812 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3813 {
3814         struct mv88e6xxx_chip *chip;
3815
3816         chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3817         if (!chip)
3818                 return NULL;
3819
3820         chip->dev = dev;
3821
3822         mutex_init(&chip->reg_lock);
3823
3824         return chip;
3825 }
3826
3827 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
3828                               struct mii_bus *bus, int sw_addr)
3829 {
3830         /* ADDR[0] pin is unavailable externally and considered zero */
3831         if (sw_addr & 0x1)
3832                 return -EINVAL;
3833
3834         if (sw_addr == 0)
3835                 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3836         else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_MULTI_CHIP))
3837                 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
3838         else
3839                 return -EINVAL;
3840
3841         chip->bus = bus;
3842         chip->sw_addr = sw_addr;
3843
3844         return 0;
3845 }
3846
3847 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3848                                        struct device *host_dev, int sw_addr,
3849                                        void **priv)
3850 {
3851         struct mv88e6xxx_chip *chip;
3852         struct mii_bus *bus;
3853         int err;
3854
3855         bus = dsa_host_dev_to_mii_bus(host_dev);
3856         if (!bus)
3857                 return NULL;
3858
3859         chip = mv88e6xxx_alloc_chip(dsa_dev);
3860         if (!chip)
3861                 return NULL;
3862
3863         /* Legacy SMI probing will only support chips similar to 88E6085 */
3864         chip->info = &mv88e6xxx_table[MV88E6085];
3865
3866         err = mv88e6xxx_smi_init(chip, bus, sw_addr);
3867         if (err)
3868                 goto free;
3869
3870         err = mv88e6xxx_detect(chip);
3871         if (err)
3872                 goto free;
3873
3874         err = mv88e6xxx_mdio_register(chip, NULL);
3875         if (err)
3876                 goto free;
3877
3878         *priv = chip;
3879
3880         return chip->info->name;
3881 free:
3882         devm_kfree(dsa_dev, chip);
3883
3884         return NULL;
3885 }
3886
3887 static struct dsa_switch_driver mv88e6xxx_switch_driver = {
3888         .tag_protocol           = DSA_TAG_PROTO_EDSA,
3889         .probe                  = mv88e6xxx_drv_probe,
3890         .setup                  = mv88e6xxx_setup,
3891         .set_addr               = mv88e6xxx_set_addr,
3892         .adjust_link            = mv88e6xxx_adjust_link,
3893         .get_strings            = mv88e6xxx_get_strings,
3894         .get_ethtool_stats      = mv88e6xxx_get_ethtool_stats,
3895         .get_sset_count         = mv88e6xxx_get_sset_count,
3896         .set_eee                = mv88e6xxx_set_eee,
3897         .get_eee                = mv88e6xxx_get_eee,
3898 #ifdef CONFIG_NET_DSA_HWMON
3899         .get_temp               = mv88e6xxx_get_temp,
3900         .get_temp_limit         = mv88e6xxx_get_temp_limit,
3901         .set_temp_limit         = mv88e6xxx_set_temp_limit,
3902         .get_temp_alarm         = mv88e6xxx_get_temp_alarm,
3903 #endif
3904         .get_eeprom_len         = mv88e6xxx_get_eeprom_len,
3905         .get_eeprom             = mv88e6xxx_get_eeprom,
3906         .set_eeprom             = mv88e6xxx_set_eeprom,
3907         .get_regs_len           = mv88e6xxx_get_regs_len,
3908         .get_regs               = mv88e6xxx_get_regs,
3909         .port_bridge_join       = mv88e6xxx_port_bridge_join,
3910         .port_bridge_leave      = mv88e6xxx_port_bridge_leave,
3911         .port_stp_state_set     = mv88e6xxx_port_stp_state_set,
3912         .port_vlan_filtering    = mv88e6xxx_port_vlan_filtering,
3913         .port_vlan_prepare      = mv88e6xxx_port_vlan_prepare,
3914         .port_vlan_add          = mv88e6xxx_port_vlan_add,
3915         .port_vlan_del          = mv88e6xxx_port_vlan_del,
3916         .port_vlan_dump         = mv88e6xxx_port_vlan_dump,
3917         .port_fdb_prepare       = mv88e6xxx_port_fdb_prepare,
3918         .port_fdb_add           = mv88e6xxx_port_fdb_add,
3919         .port_fdb_del           = mv88e6xxx_port_fdb_del,
3920         .port_fdb_dump          = mv88e6xxx_port_fdb_dump,
3921 };
3922
3923 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
3924                                      struct device_node *np)
3925 {
3926         struct device *dev = chip->dev;
3927         struct dsa_switch *ds;
3928
3929         ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
3930         if (!ds)
3931                 return -ENOMEM;
3932
3933         ds->dev = dev;
3934         ds->priv = chip;
3935         ds->drv = &mv88e6xxx_switch_driver;
3936
3937         dev_set_drvdata(dev, ds);
3938
3939         return dsa_register_switch(ds, np);
3940 }
3941
3942 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
3943 {
3944         dsa_unregister_switch(chip->ds);
3945 }
3946
3947 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
3948 {
3949         struct device *dev = &mdiodev->dev;
3950         struct device_node *np = dev->of_node;
3951         const struct mv88e6xxx_info *compat_info;
3952         struct mv88e6xxx_chip *chip;
3953         u32 eeprom_len;
3954         int err;
3955
3956         compat_info = of_device_get_match_data(dev);
3957         if (!compat_info)
3958                 return -EINVAL;
3959
3960         chip = mv88e6xxx_alloc_chip(dev);
3961         if (!chip)
3962                 return -ENOMEM;
3963
3964         chip->info = compat_info;
3965
3966         err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
3967         if (err)
3968                 return err;
3969
3970         err = mv88e6xxx_detect(chip);
3971         if (err)
3972                 return err;
3973
3974         chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
3975         if (IS_ERR(chip->reset))
3976                 return PTR_ERR(chip->reset);
3977
3978         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEPROM) &&
3979             !of_property_read_u32(np, "eeprom-length", &eeprom_len))
3980                 chip->eeprom_len = eeprom_len;
3981
3982         err = mv88e6xxx_mdio_register(chip, np);
3983         if (err)
3984                 return err;
3985
3986         err = mv88e6xxx_register_switch(chip, np);
3987         if (err) {
3988                 mv88e6xxx_mdio_unregister(chip);
3989                 return err;
3990         }
3991
3992         return 0;
3993 }
3994
3995 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
3996 {
3997         struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
3998         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3999
4000         mv88e6xxx_unregister_switch(chip);
4001         mv88e6xxx_mdio_unregister(chip);
4002 }
4003
4004 static const struct of_device_id mv88e6xxx_of_match[] = {
4005         {
4006                 .compatible = "marvell,mv88e6085",
4007                 .data = &mv88e6xxx_table[MV88E6085],
4008         },
4009         { /* sentinel */ },
4010 };
4011
4012 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4013
4014 static struct mdio_driver mv88e6xxx_driver = {
4015         .probe  = mv88e6xxx_probe,
4016         .remove = mv88e6xxx_remove,
4017         .mdiodrv.driver = {
4018                 .name = "mv88e6085",
4019                 .of_match_table = mv88e6xxx_of_match,
4020         },
4021 };
4022
4023 static int __init mv88e6xxx_init(void)
4024 {
4025         register_switch_driver(&mv88e6xxx_switch_driver);
4026         return mdio_driver_register(&mv88e6xxx_driver);
4027 }
4028 module_init(mv88e6xxx_init);
4029
4030 static void __exit mv88e6xxx_cleanup(void)
4031 {
4032         mdio_driver_unregister(&mv88e6xxx_driver);
4033         unregister_switch_driver(&mv88e6xxx_switch_driver);
4034 }
4035 module_exit(mv88e6xxx_cleanup);
4036
4037 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4038 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4039 MODULE_LICENSE("GPL");