drivers/net/dsa/mv88e6xxx/chip.c

   1 /*
   2  * Marvell 88e6xxx Ethernet switch single-chip support
   3  *
   4  * Copyright (c) 2008 Marvell Semiconductor
   5  *
   6  * Copyright (c) 2015 CMC Electronics, Inc.
   7  *      Added support for VLAN Table Unit operations
   8  *
   9  * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include <linux/delay.h>
  18 #include <linux/etherdevice.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/if_bridge.h>
  21 #include <linux/jiffies.h>
  22 #include <linux/list.h>
  23 #include <linux/mdio.h>
  24 #include <linux/module.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_mdio.h>
  27 #include <linux/netdevice.h>
  28 #include <linux/gpio/consumer.h>
  29 #include <linux/phy.h>
  30 #include <net/dsa.h>
  31 #include <net/switchdev.h>
  32 #include "mv88e6xxx.h"
  33
  34 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
  35 {
  36         if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
  37                 dev_err(chip->dev, "Switch registers lock not held!\n");
  38                 dump_stack();
  39         }
  40 }
  41
  42 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
  43  * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
  44  *
  45  * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
  46  * is the only device connected to the SMI master. In this mode it responds to
  47  * all 32 possible SMI addresses, and thus maps directly the internal devices.
  48  *
  49  * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
  50  * multiple devices to share the SMI interface. In this mode it responds to only
  51  * 2 registers, used to indirectly access the internal SMI devices.
  52  */
  53
  54 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
  55                               int addr, int reg, u16 *val)
  56 {
  57         if (!chip->smi_ops)
  58                 return -EOPNOTSUPP;
  59
  60         return chip->smi_ops->read(chip, addr, reg, val);
  61 }
  62
  63 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
  64                                int addr, int reg, u16 val)
  65 {
  66         if (!chip->smi_ops)
  67                 return -EOPNOTSUPP;
  68
  69         return chip->smi_ops->write(chip, addr, reg, val);
  70 }
  71
  72 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
  73                                           int addr, int reg, u16 *val)
  74 {
  75         int ret;
  76
  77         ret = mdiobus_read_nested(chip->bus, addr, reg);
  78         if (ret < 0)
  79                 return ret;
  80
  81         *val = ret & 0xffff;
  82
  83         return 0;
  84 }
  85
  86 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
  87                                            int addr, int reg, u16 val)
  88 {
  89         int ret;
  90
  91         ret = mdiobus_write_nested(chip->bus, addr, reg, val);
  92         if (ret < 0)
  93                 return ret;
  94
  95         return 0;
  96 }
  97
  98 static const struct mv88e6xxx_ops mv88e6xxx_smi_single_chip_ops = {
  99         .read = mv88e6xxx_smi_single_chip_read,
 100         .write = mv88e6xxx_smi_single_chip_write,
 101 };
 102
 103 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
 104 {
 105         int ret;
 106         int i;
 107
 108         for (i = 0; i < 16; i++) {
 109                 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
 110                 if (ret < 0)
 111                         return ret;
 112
 113                 if ((ret & SMI_CMD_BUSY) == 0)
 114                         return 0;
 115         }
 116
 117         return -ETIMEDOUT;
 118 }
 119
 120 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
 121                                          int addr, int reg, u16 *val)
 122 {
 123         int ret;
 124
 125         /* Wait for the bus to become free. */
 126         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 127         if (ret < 0)
 128                 return ret;
 129
 130         /* Transmit the read command. */
 131         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
 132                                    SMI_CMD_OP_22_READ | (addr << 5) | reg);
 133         if (ret < 0)
 134                 return ret;
 135
 136         /* Wait for the read command to complete. */
 137         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 138         if (ret < 0)
 139                 return ret;
 140
 141         /* Read the data. */
 142         ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
 143         if (ret < 0)
 144                 return ret;
 145
 146         *val = ret & 0xffff;
 147
 148         return 0;
 149 }
 150
 151 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
 152                                           int addr, int reg, u16 val)
 153 {
 154         int ret;
 155
 156         /* Wait for the bus to become free. */
 157         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 158         if (ret < 0)
 159                 return ret;
 160
 161         /* Transmit the data to write. */
 162         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
 163         if (ret < 0)
 164                 return ret;
 165
 166         /* Transmit the write command. */
 167         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
 168                                    SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
 169         if (ret < 0)
 170                 return ret;
 171
 172         /* Wait for the write command to complete. */
 173         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 174         if (ret < 0)
 175                 return ret;
 176
 177         return 0;
 178 }
 179
 180 static const struct mv88e6xxx_ops mv88e6xxx_smi_multi_chip_ops = {
 181         .read = mv88e6xxx_smi_multi_chip_read,
 182         .write = mv88e6xxx_smi_multi_chip_write,
 183 };
 184
 185 static int mv88e6xxx_read(struct mv88e6xxx_chip *chip,
 186                           int addr, int reg, u16 *val)
 187 {
 188         int err;
 189
 190         assert_reg_lock(chip);
 191
 192         err = mv88e6xxx_smi_read(chip, addr, reg, val);
 193         if (err)
 194                 return err;
 195
 196         dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
 197                 addr, reg, *val);
 198
 199         return 0;
 200 }
 201
 202 static int mv88e6xxx_write(struct mv88e6xxx_chip *chip,
 203                            int addr, int reg, u16 val)
 204 {
 205         int err;
 206
 207         assert_reg_lock(chip);
 208
 209         err = mv88e6xxx_smi_write(chip, addr, reg, val);
 210         if (err)
 211                 return err;
 212
 213         dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
 214                 addr, reg, val);
 215
 216         return 0;
 217 }
 218
 219 static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
 220                               int reg, u16 *val)
 221 {
 222         int addr = phy; /* PHY devices addresses start at 0x0 */
 223
 224         if (!chip->phy_ops)
 225                 return -EOPNOTSUPP;
 226
 227         return chip->phy_ops->read(chip, addr, reg, val);
 228 }
 229
 230 static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
 231                                int reg, u16 val)
 232 {
 233         int addr = phy; /* PHY devices addresses start at 0x0 */
 234
 235         if (!chip->phy_ops)
 236                 return -EOPNOTSUPP;
 237
 238         return chip->phy_ops->write(chip, addr, reg, val);
 239 }
 240
 241 static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
 242 {
 243         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
 244                 return -EOPNOTSUPP;
 245
 246         return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
 247 }
 248
 249 static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
 250 {
 251         int err;
 252
 253         /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
 254         err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
 255         if (unlikely(err)) {
 256                 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
 257                         phy, err);
 258         }
 259 }
 260
 261 static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
 262                                    u8 page, int reg, u16 *val)
 263 {
 264         int err;
 265
 266         /* There is no paging for registers 22 */
 267         if (reg == PHY_PAGE)
 268                 return -EINVAL;
 269
 270         err = mv88e6xxx_phy_page_get(chip, phy, page);
 271         if (!err) {
 272                 err = mv88e6xxx_phy_read(chip, phy, reg, val);
 273                 mv88e6xxx_phy_page_put(chip, phy);
 274         }
 275
 276         return err;
 277 }
 278
 279 static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
 280                                     u8 page, int reg, u16 val)
 281 {
 282         int err;
 283
 284         /* There is no paging for registers 22 */
 285         if (reg == PHY_PAGE)
 286                 return -EINVAL;
 287
 288         err = mv88e6xxx_phy_page_get(chip, phy, page);
 289         if (!err) {
 290                 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
 291                 mv88e6xxx_phy_page_put(chip, phy);
 292         }
 293
 294         return err;
 295 }
 296
 297 static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
 298 {
 299         return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
 300                                        reg, val);
 301 }
 302
 303 static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
 304 {
 305         return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
 306                                         reg, val);
 307 }
 308
 309 static int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg,
 310                           u16 mask)
 311 {
 312         int i;
 313
 314         for (i = 0; i < 16; i++) {
 315                 u16 val;
 316                 int err;
 317
 318                 err = mv88e6xxx_read(chip, addr, reg, &val);
 319                 if (err)
 320                         return err;
 321
 322                 if (!(val & mask))
 323                         return 0;
 324
 325                 usleep_range(1000, 2000);
 326         }
 327
 328         dev_err(chip->dev, "Timeout while waiting for switch\n");
 329         return -ETIMEDOUT;
 330 }
 331
 332 /* Indirect write to single pointer-data register with an Update bit */
 333 static int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
 334                             u16 update)
 335 {
 336         u16 val;
 337         int err;
 338
 339         /* Wait until the previous operation is completed */
 340         err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
 341         if (err)
 342                 return err;
 343
 344         /* Set the Update bit to trigger a write operation */
 345         val = BIT(15) | update;
 346
 347         return mv88e6xxx_write(chip, addr, reg, val);
 348 }
 349
 350 static int _mv88e6xxx_reg_read(struct mv88e6xxx_chip *chip, int addr, int reg)
 351 {
 352         u16 val;
 353         int err;
 354
 355         err = mv88e6xxx_read(chip, addr, reg, &val);
 356         if (err)
 357                 return err;
 358
 359         return val;
 360 }
 361
 362 static int _mv88e6xxx_reg_write(struct mv88e6xxx_chip *chip, int addr,
 363                                 int reg, u16 val)
 364 {
 365         return mv88e6xxx_write(chip, addr, reg, val);
 366 }
 367
 368 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
 369 {
 370         int ret;
 371         int i;
 372
 373         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
 374         if (ret < 0)
 375                 return ret;
 376
 377         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
 378                                    ret & ~GLOBAL_CONTROL_PPU_ENABLE);
 379         if (ret)
 380                 return ret;
 381
 382         for (i = 0; i < 16; i++) {
 383                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
 384                 if (ret < 0)
 385                         return ret;
 386
 387                 usleep_range(1000, 2000);
 388                 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
 389                     GLOBAL_STATUS_PPU_POLLING)
 390                         return 0;
 391         }
 392
 393         return -ETIMEDOUT;
 394 }
 395
 396 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
 397 {
 398         int ret, err, i;
 399
 400         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
 401         if (ret < 0)
 402                 return ret;
 403
 404         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
 405                                    ret | GLOBAL_CONTROL_PPU_ENABLE);
 406         if (err)
 407                 return err;
 408
 409         for (i = 0; i < 16; i++) {
 410                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
 411                 if (ret < 0)
 412                         return ret;
 413
 414                 usleep_range(1000, 2000);
 415                 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
 416                     GLOBAL_STATUS_PPU_POLLING)
 417                         return 0;
 418         }
 419
 420         return -ETIMEDOUT;
 421 }
 422
 423 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
 424 {
 425         struct mv88e6xxx_chip *chip;
 426
 427         chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
 428
 429         mutex_lock(&chip->reg_lock);
 430
 431         if (mutex_trylock(&chip->ppu_mutex)) {
 432                 if (mv88e6xxx_ppu_enable(chip) == 0)
 433                         chip->ppu_disabled = 0;
 434                 mutex_unlock(&chip->ppu_mutex);
 435         }
 436
 437         mutex_unlock(&chip->reg_lock);
 438 }
 439
 440 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
 441 {
 442         struct mv88e6xxx_chip *chip = (void *)_ps;
 443
 444         schedule_work(&chip->ppu_work);
 445 }
 446
 447 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
 448 {
 449         int ret;
 450
 451         mutex_lock(&chip->ppu_mutex);
 452
 453         /* If the PHY polling unit is enabled, disable it so that
 454          * we can access the PHY registers.  If it was already
 455          * disabled, cancel the timer that is going to re-enable
 456          * it.
 457          */
 458         if (!chip->ppu_disabled) {
 459                 ret = mv88e6xxx_ppu_disable(chip);
 460                 if (ret < 0) {
 461                         mutex_unlock(&chip->ppu_mutex);
 462                         return ret;
 463                 }
 464                 chip->ppu_disabled = 1;
 465         } else {
 466                 del_timer(&chip->ppu_timer);
 467                 ret = 0;
 468         }
 469
 470         return ret;
 471 }
 472
 473 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
 474 {
 475         /* Schedule a timer to re-enable the PHY polling unit. */
 476         mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
 477         mutex_unlock(&chip->ppu_mutex);
 478 }
 479
 480 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
 481 {
 482         mutex_init(&chip->ppu_mutex);
 483         INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
 484         init_timer(&chip->ppu_timer);
 485         chip->ppu_timer.data = (unsigned long)chip;
 486         chip->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
 487 }
 488
 489 static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
 490 {
 491         del_timer_sync(&chip->ppu_timer);
 492 }
 493
 494 static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr,
 495                                   int reg, u16 *val)
 496 {
 497         int err;
 498
 499         err = mv88e6xxx_ppu_access_get(chip);
 500         if (!err) {
 501                 err = mv88e6xxx_read(chip, addr, reg, val);
 502                 mv88e6xxx_ppu_access_put(chip);
 503         }
 504
 505         return err;
 506 }
 507
 508 static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr,
 509                                    int reg, u16 val)
 510 {
 511         int err;
 512
 513         err = mv88e6xxx_ppu_access_get(chip);
 514         if (!err) {
 515                 err = mv88e6xxx_write(chip, addr, reg, val);
 516                 mv88e6xxx_ppu_access_put(chip);
 517         }
 518
 519         return err;
 520 }
 521
 522 static const struct mv88e6xxx_ops mv88e6xxx_phy_ppu_ops = {
 523         .read = mv88e6xxx_phy_ppu_read,
 524         .write = mv88e6xxx_phy_ppu_write,
 525 };
 526
 527 static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
 528 {
 529         return chip->info->family == MV88E6XXX_FAMILY_6065;
 530 }
 531
 532 static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
 533 {
 534         return chip->info->family == MV88E6XXX_FAMILY_6095;
 535 }
 536
 537 static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
 538 {
 539         return chip->info->family == MV88E6XXX_FAMILY_6097;
 540 }
 541
 542 static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
 543 {
 544         return chip->info->family == MV88E6XXX_FAMILY_6165;
 545 }
 546
 547 static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
 548 {
 549         return chip->info->family == MV88E6XXX_FAMILY_6185;
 550 }
 551
 552 static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
 553 {
 554         return chip->info->family == MV88E6XXX_FAMILY_6320;
 555 }
 556
 557 static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
 558 {
 559         return chip->info->family == MV88E6XXX_FAMILY_6351;
 560 }
 561
 562 static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
 563 {
 564         return chip->info->family == MV88E6XXX_FAMILY_6352;
 565 }
 566
 567 static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
 568 {
 569         return chip->info->num_databases;
 570 }
 571
 572 static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_chip *chip)
 573 {
 574         /* Does the device have dedicated FID registers for ATU and VTU ops? */
 575         if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
 576             mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip))
 577                 return true;
 578
 579         return false;
 580 }
 581
 582 /* We expect the switch to perform auto negotiation if there is a real
 583  * phy. However, in the case of a fixed link phy, we force the port
 584  * settings from the fixed link settings.
 585  */
 586 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
 587                                   struct phy_device *phydev)
 588 {
 589         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 590         u32 reg;
 591         int ret;
 592
 593         if (!phy_is_pseudo_fixed_link(phydev))
 594                 return;
 595
 596         mutex_lock(&chip->reg_lock);
 597
 598         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
 599         if (ret < 0)
 600                 goto out;
 601
 602         reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
 603                       PORT_PCS_CTRL_FORCE_LINK |
 604                       PORT_PCS_CTRL_DUPLEX_FULL |
 605                       PORT_PCS_CTRL_FORCE_DUPLEX |
 606                       PORT_PCS_CTRL_UNFORCED);
 607
 608         reg |= PORT_PCS_CTRL_FORCE_LINK;
 609         if (phydev->link)
 610                 reg |= PORT_PCS_CTRL_LINK_UP;
 611
 612         if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100)
 613                 goto out;
 614
 615         switch (phydev->speed) {
 616         case SPEED_1000:
 617                 reg |= PORT_PCS_CTRL_1000;
 618                 break;
 619         case SPEED_100:
 620                 reg |= PORT_PCS_CTRL_100;
 621                 break;
 622         case SPEED_10:
 623                 reg |= PORT_PCS_CTRL_10;
 624                 break;
 625         default:
 626                 pr_info("Unknown speed");
 627                 goto out;
 628         }
 629
 630         reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
 631         if (phydev->duplex == DUPLEX_FULL)
 632                 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
 633
 634         if ((mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip)) &&
 635             (port >= chip->info->num_ports - 2)) {
 636                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 637                         reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
 638                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 639                         reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
 640                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 641                         reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
 642                                 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
 643         }
 644         _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_PCS_CTRL, reg);
 645
 646 out:
 647         mutex_unlock(&chip->reg_lock);
 648 }
 649
 650 static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip)
 651 {
 652         int ret;
 653         int i;
 654
 655         for (i = 0; i < 10; i++) {
 656                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_OP);
 657                 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
 658                         return 0;
 659         }
 660
 661         return -ETIMEDOUT;
 662 }
 663
 664 static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
 665 {
 666         int ret;
 667
 668         if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
 669                 port = (port + 1) << 5;
 670
 671         /* Snapshot the hardware statistics counters for this port. */
 672         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
 673                                    GLOBAL_STATS_OP_CAPTURE_PORT |
 674                                    GLOBAL_STATS_OP_HIST_RX_TX | port);
 675         if (ret < 0)
 676                 return ret;
 677
 678         /* Wait for the snapshotting to complete. */
 679         ret = _mv88e6xxx_stats_wait(chip);
 680         if (ret < 0)
 681                 return ret;
 682
 683         return 0;
 684 }
 685
 686 static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip,
 687                                   int stat, u32 *val)
 688 {
 689         u32 _val;
 690         int ret;
 691
 692         *val = 0;
 693
 694         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
 695                                    GLOBAL_STATS_OP_READ_CAPTURED |
 696                                    GLOBAL_STATS_OP_HIST_RX_TX | stat);
 697         if (ret < 0)
 698                 return;
 699
 700         ret = _mv88e6xxx_stats_wait(chip);
 701         if (ret < 0)
 702                 return;
 703
 704         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
 705         if (ret < 0)
 706                 return;
 707
 708         _val = ret << 16;
 709
 710         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
 711         if (ret < 0)
 712                 return;
 713
 714         *val = _val | ret;
 715 }
 716
 717 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
 718         { "in_good_octets",     8, 0x00, BANK0, },
 719         { "in_bad_octets",      4, 0x02, BANK0, },
 720         { "in_unicast",         4, 0x04, BANK0, },
 721         { "in_broadcasts",      4, 0x06, BANK0, },
 722         { "in_multicasts",      4, 0x07, BANK0, },
 723         { "in_pause",           4, 0x16, BANK0, },
 724         { "in_undersize",       4, 0x18, BANK0, },
 725         { "in_fragments",       4, 0x19, BANK0, },
 726         { "in_oversize",        4, 0x1a, BANK0, },
 727         { "in_jabber",          4, 0x1b, BANK0, },
 728         { "in_rx_error",        4, 0x1c, BANK0, },
 729         { "in_fcs_error",       4, 0x1d, BANK0, },
 730         { "out_octets",         8, 0x0e, BANK0, },
 731         { "out_unicast",        4, 0x10, BANK0, },
 732         { "out_broadcasts",     4, 0x13, BANK0, },
 733         { "out_multicasts",     4, 0x12, BANK0, },
 734         { "out_pause",          4, 0x15, BANK0, },
 735         { "excessive",          4, 0x11, BANK0, },
 736         { "collisions",         4, 0x1e, BANK0, },
 737         { "deferred",           4, 0x05, BANK0, },
 738         { "single",             4, 0x14, BANK0, },
 739         { "multiple",           4, 0x17, BANK0, },
 740         { "out_fcs_error",      4, 0x03, BANK0, },
 741         { "late",               4, 0x1f, BANK0, },
 742         { "hist_64bytes",       4, 0x08, BANK0, },
 743         { "hist_65_127bytes",   4, 0x09, BANK0, },
 744         { "hist_128_255bytes",  4, 0x0a, BANK0, },
 745         { "hist_256_511bytes",  4, 0x0b, BANK0, },
 746         { "hist_512_1023bytes", 4, 0x0c, BANK0, },
 747         { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
 748         { "sw_in_discards",     4, 0x10, PORT, },
 749         { "sw_in_filtered",     2, 0x12, PORT, },
 750         { "sw_out_filtered",    2, 0x13, PORT, },
 751         { "in_discards",        4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 752         { "in_filtered",        4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 753         { "in_accepted",        4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 754         { "in_bad_accepted",    4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 755         { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 756         { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 757         { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 758         { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 759         { "tcam_counter_0",     4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 760         { "tcam_counter_1",     4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 761         { "tcam_counter_2",     4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
 762         { "tcam_counter_3",     4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
 763         { "in_da_unknown",      4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
 764         { "in_management",      4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
 765         { "out_queue_0",        4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 766         { "out_queue_1",        4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 767         { "out_queue_2",        4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 768         { "out_queue_3",        4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 769         { "out_queue_4",        4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 770         { "out_queue_5",        4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 771         { "out_queue_6",        4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 772         { "out_queue_7",        4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 773         { "out_cut_through",    4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 774         { "out_octets_a",       4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
 775         { "out_octets_b",       4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
 776         { "out_management",     4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
 777 };
 778
 779 static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip,
 780                                struct mv88e6xxx_hw_stat *stat)
 781 {
 782         switch (stat->type) {
 783         case BANK0:
 784                 return true;
 785         case BANK1:
 786                 return mv88e6xxx_6320_family(chip);
 787         case PORT:
 788                 return mv88e6xxx_6095_family(chip) ||
 789                         mv88e6xxx_6185_family(chip) ||
 790                         mv88e6xxx_6097_family(chip) ||
 791                         mv88e6xxx_6165_family(chip) ||
 792                         mv88e6xxx_6351_family(chip) ||
 793                         mv88e6xxx_6352_family(chip);
 794         }
 795         return false;
 796 }
 797
 798 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
 799                                             struct mv88e6xxx_hw_stat *s,
 800                                             int port)
 801 {
 802         u32 low;
 803         u32 high = 0;
 804         int ret;
 805         u64 value;
 806
 807         switch (s->type) {
 808         case PORT:
 809                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), s->reg);
 810                 if (ret < 0)
 811                         return UINT64_MAX;
 812
 813                 low = ret;
 814                 if (s->sizeof_stat == 4) {
 815                         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port),
 816                                                   s->reg + 1);
 817                         if (ret < 0)
 818                                 return UINT64_MAX;
 819                         high = ret;
 820                 }
 821                 break;
 822         case BANK0:
 823         case BANK1:
 824                 _mv88e6xxx_stats_read(chip, s->reg, &low);
 825                 if (s->sizeof_stat == 8)
 826                         _mv88e6xxx_stats_read(chip, s->reg + 1, &high);
 827         }
 828         value = (((u64)high) << 16) | low;
 829         return value;
 830 }
 831
 832 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
 833                                   uint8_t *data)
 834 {
 835         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 836         struct mv88e6xxx_hw_stat *stat;
 837         int i, j;
 838
 839         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 840                 stat = &mv88e6xxx_hw_stats[i];
 841                 if (mv88e6xxx_has_stat(chip, stat)) {
 842                         memcpy(data + j * ETH_GSTRING_LEN, stat->string,
 843                                ETH_GSTRING_LEN);
 844                         j++;
 845                 }
 846         }
 847 }
 848
 849 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
 850 {
 851         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 852         struct mv88e6xxx_hw_stat *stat;
 853         int i, j;
 854
 855         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 856                 stat = &mv88e6xxx_hw_stats[i];
 857                 if (mv88e6xxx_has_stat(chip, stat))
 858                         j++;
 859         }
 860         return j;
 861 }
 862
 863 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
 864                                         uint64_t *data)
 865 {
 866         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 867         struct mv88e6xxx_hw_stat *stat;
 868         int ret;
 869         int i, j;
 870
 871         mutex_lock(&chip->reg_lock);
 872
 873         ret = _mv88e6xxx_stats_snapshot(chip, port);
 874         if (ret < 0) {
 875                 mutex_unlock(&chip->reg_lock);
 876                 return;
 877         }
 878         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 879                 stat = &mv88e6xxx_hw_stats[i];
 880                 if (mv88e6xxx_has_stat(chip, stat)) {
 881                         data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port);
 882                         j++;
 883                 }
 884         }
 885
 886         mutex_unlock(&chip->reg_lock);
 887 }
 888
 889 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
 890 {
 891         return 32 * sizeof(u16);
 892 }
 893
 894 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
 895                                struct ethtool_regs *regs, void *_p)
 896 {
 897         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 898         u16 *p = _p;
 899         int i;
 900
 901         regs->version = 0;
 902
 903         memset(p, 0xff, 32 * sizeof(u16));
 904
 905         mutex_lock(&chip->reg_lock);
 906
 907         for (i = 0; i < 32; i++) {
 908                 int ret;
 909
 910                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), i);
 911                 if (ret >= 0)
 912                         p[i] = ret;
 913         }
 914
 915         mutex_unlock(&chip->reg_lock);
 916 }
 917
 918 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
 919 {
 920         return mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_ATU_OP,
 921                               GLOBAL_ATU_OP_BUSY);
 922 }
 923
 924 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
 925                              struct ethtool_eee *e)
 926 {
 927         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 928         u16 reg;
 929         int err;
 930
 931         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
 932                 return -EOPNOTSUPP;
 933
 934         mutex_lock(&chip->reg_lock);
 935
 936         err = mv88e6xxx_phy_read(chip, port, 16, &reg);
 937         if (err)
 938                 goto out;
 939
 940         e->eee_enabled = !!(reg & 0x0200);
 941         e->tx_lpi_enabled = !!(reg & 0x0100);
 942
 943         err = mv88e6xxx_read(chip, REG_PORT(port), PORT_STATUS, &reg);
 944         if (err)
 945                 goto out;
 946
 947         e->eee_active = !!(reg & PORT_STATUS_EEE);
 948 out:
 949         mutex_unlock(&chip->reg_lock);
 950
 951         return err;
 952 }
 953
 954 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
 955                              struct phy_device *phydev, struct ethtool_eee *e)
 956 {
 957         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 958         u16 reg;
 959         int err;
 960
 961         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
 962                 return -EOPNOTSUPP;
 963
 964         mutex_lock(&chip->reg_lock);
 965
 966         err = mv88e6xxx_phy_read(chip, port, 16, &reg);
 967         if (err)
 968                 goto out;
 969
 970         reg &= ~0x0300;
 971         if (e->eee_enabled)
 972                 reg |= 0x0200;
 973         if (e->tx_lpi_enabled)
 974                 reg |= 0x0100;
 975
 976         err = mv88e6xxx_phy_write(chip, port, 16, reg);
 977 out:
 978         mutex_unlock(&chip->reg_lock);
 979
 980         return err;
 981 }
 982
 983 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
 984 {
 985         int ret;
 986
 987         if (mv88e6xxx_has_fid_reg(chip)) {
 988                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_FID,
 989                                            fid);
 990                 if (ret < 0)
 991                         return ret;
 992         } else if (mv88e6xxx_num_databases(chip) == 256) {
 993                 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
 994                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL);
 995                 if (ret < 0)
 996                         return ret;
 997
 998                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
 999                                            (ret & 0xfff) |
1000                                            ((fid << 8) & 0xf000));
1001                 if (ret < 0)
1002                         return ret;
1003
1004                 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1005                 cmd |= fid & 0xf;
1006         }
1007
1008         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
1009         if (ret < 0)
1010                 return ret;
1011
1012         return _mv88e6xxx_atu_wait(chip);
1013 }
1014
1015 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
1016                                      struct mv88e6xxx_atu_entry *entry)
1017 {
1018         u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1019
1020         if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1021                 unsigned int mask, shift;
1022
1023                 if (entry->trunk) {
1024                         data |= GLOBAL_ATU_DATA_TRUNK;
1025                         mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1026                         shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1027                 } else {
1028                         mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1029                         shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1030                 }
1031
1032                 data |= (entry->portv_trunkid << shift) & mask;
1033         }
1034
1035         return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_DATA, data);
1036 }
1037
1038 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
1039                                      struct mv88e6xxx_atu_entry *entry,
1040                                      bool static_too)
1041 {
1042         int op;
1043         int err;
1044
1045         err = _mv88e6xxx_atu_wait(chip);
1046         if (err)
1047                 return err;
1048
1049         err = _mv88e6xxx_atu_data_write(chip, entry);
1050         if (err)
1051                 return err;
1052
1053         if (entry->fid) {
1054                 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1055                         GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1056         } else {
1057                 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1058                         GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1059         }
1060
1061         return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
1062 }
1063
1064 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
1065                                 u16 fid, bool static_too)
1066 {
1067         struct mv88e6xxx_atu_entry entry = {
1068                 .fid = fid,
1069                 .state = 0, /* EntryState bits must be 0 */
1070         };
1071
1072         return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1073 }
1074
1075 static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
1076                                int from_port, int to_port, bool static_too)
1077 {
1078         struct mv88e6xxx_atu_entry entry = {
1079                 .trunk = false,
1080                 .fid = fid,
1081         };
1082
1083         /* EntryState bits must be 0xF */
1084         entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1085
1086         /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1087         entry.portv_trunkid = (to_port & 0x0f) << 4;
1088         entry.portv_trunkid |= from_port & 0x0f;
1089
1090         return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1091 }
1092
1093 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
1094                                  int port, bool static_too)
1095 {
1096         /* Destination port 0xF means remove the entries */
1097         return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
1098 }
1099
1100 static const char * const mv88e6xxx_port_state_names[] = {
1101         [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1102         [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1103         [PORT_CONTROL_STATE_LEARNING] = "Learning",
1104         [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1105 };
1106
1107 static int _mv88e6xxx_port_state(struct mv88e6xxx_chip *chip, int port,
1108                                  u8 state)
1109 {
1110         struct dsa_switch *ds = chip->ds;
1111         int reg, ret = 0;
1112         u8 oldstate;
1113
1114         reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL);
1115         if (reg < 0)
1116                 return reg;
1117
1118         oldstate = reg & PORT_CONTROL_STATE_MASK;
1119
1120         if (oldstate != state) {
1121                 /* Flush forwarding database if we're moving a port
1122                  * from Learning or Forwarding state to Disabled or
1123                  * Blocking or Listening state.
1124                  */
1125                 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
1126                      oldstate == PORT_CONTROL_STATE_FORWARDING) &&
1127                     (state == PORT_CONTROL_STATE_DISABLED ||
1128                      state == PORT_CONTROL_STATE_BLOCKING)) {
1129                         ret = _mv88e6xxx_atu_remove(chip, 0, port, false);
1130                         if (ret)
1131                                 return ret;
1132                 }
1133
1134                 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1135                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL,
1136                                            reg);
1137                 if (ret)
1138                         return ret;
1139
1140                 netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n",
1141                            mv88e6xxx_port_state_names[state],
1142                            mv88e6xxx_port_state_names[oldstate]);
1143         }
1144
1145         return ret;
1146 }
1147
1148 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
1149 {
1150         struct net_device *bridge = chip->ports[port].bridge_dev;
1151         const u16 mask = (1 << chip->info->num_ports) - 1;
1152         struct dsa_switch *ds = chip->ds;
1153         u16 output_ports = 0;
1154         int reg;
1155         int i;
1156
1157         /* allow CPU port or DSA link(s) to send frames to every port */
1158         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1159                 output_ports = mask;
1160         } else {
1161                 for (i = 0; i < chip->info->num_ports; ++i) {
1162                         /* allow sending frames to every group member */
1163                         if (bridge && chip->ports[i].bridge_dev == bridge)
1164                                 output_ports |= BIT(i);
1165
1166                         /* allow sending frames to CPU port and DSA link(s) */
1167                         if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1168                                 output_ports |= BIT(i);
1169                 }
1170         }
1171
1172         /* prevent frames from going back out of the port they came in on */
1173         output_ports &= ~BIT(port);
1174
1175         reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
1176         if (reg < 0)
1177                 return reg;
1178
1179         reg &= ~mask;
1180         reg |= output_ports & mask;
1181
1182         return _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN, reg);
1183 }
1184
1185 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1186                                          u8 state)
1187 {
1188         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1189         int stp_state;
1190         int err;
1191
1192         switch (state) {
1193         case BR_STATE_DISABLED:
1194                 stp_state = PORT_CONTROL_STATE_DISABLED;
1195                 break;
1196         case BR_STATE_BLOCKING:
1197         case BR_STATE_LISTENING:
1198                 stp_state = PORT_CONTROL_STATE_BLOCKING;
1199                 break;
1200         case BR_STATE_LEARNING:
1201                 stp_state = PORT_CONTROL_STATE_LEARNING;
1202                 break;
1203         case BR_STATE_FORWARDING:
1204         default:
1205                 stp_state = PORT_CONTROL_STATE_FORWARDING;
1206                 break;
1207         }
1208
1209         mutex_lock(&chip->reg_lock);
1210         err = _mv88e6xxx_port_state(chip, port, stp_state);
1211         mutex_unlock(&chip->reg_lock);
1212
1213         if (err)
1214                 netdev_err(ds->ports[port].netdev,
1215                            "failed to update state to %s\n",
1216                            mv88e6xxx_port_state_names[stp_state]);
1217 }
1218
1219 static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip *chip, int port,
1220                                 u16 *new, u16 *old)
1221 {
1222         struct dsa_switch *ds = chip->ds;
1223         u16 pvid;
1224         int ret;
1225
1226         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_DEFAULT_VLAN);
1227         if (ret < 0)
1228                 return ret;
1229
1230         pvid = ret & PORT_DEFAULT_VLAN_MASK;
1231
1232         if (new) {
1233                 ret &= ~PORT_DEFAULT_VLAN_MASK;
1234                 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1235
1236                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
1237                                            PORT_DEFAULT_VLAN, ret);
1238                 if (ret < 0)
1239                         return ret;
1240
1241                 netdev_dbg(ds->ports[port].netdev,
1242                            "DefaultVID %d (was %d)\n", *new, pvid);
1243         }
1244
1245         if (old)
1246                 *old = pvid;
1247
1248         return 0;
1249 }
1250
1251 static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_chip *chip,
1252                                     int port, u16 *pvid)
1253 {
1254         return _mv88e6xxx_port_pvid(chip, port, NULL, pvid);
1255 }
1256
1257 static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip *chip,
1258                                     int port, u16 pvid)
1259 {
1260         return _mv88e6xxx_port_pvid(chip, port, &pvid, NULL);
1261 }
1262
1263 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
1264 {
1265         return mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_VTU_OP,
1266                               GLOBAL_VTU_OP_BUSY);
1267 }
1268
1269 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
1270 {
1271         int ret;
1272
1273         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_OP, op);
1274         if (ret < 0)
1275                 return ret;
1276
1277         return _mv88e6xxx_vtu_wait(chip);
1278 }
1279
1280 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
1281 {
1282         int ret;
1283
1284         ret = _mv88e6xxx_vtu_wait(chip);
1285         if (ret < 0)
1286                 return ret;
1287
1288         return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
1289 }
1290
1291 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
1292                                         struct mv88e6xxx_vtu_stu_entry *entry,
1293                                         unsigned int nibble_offset)
1294 {
1295         u16 regs[3];
1296         int i;
1297         int ret;
1298
1299         for (i = 0; i < 3; ++i) {
1300                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1301                                           GLOBAL_VTU_DATA_0_3 + i);
1302                 if (ret < 0)
1303                         return ret;
1304
1305                 regs[i] = ret;
1306         }
1307
1308         for (i = 0; i < chip->info->num_ports; ++i) {
1309                 unsigned int shift = (i % 4) * 4 + nibble_offset;
1310                 u16 reg = regs[i / 4];
1311
1312                 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1313         }
1314
1315         return 0;
1316 }
1317
1318 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
1319                                    struct mv88e6xxx_vtu_stu_entry *entry)
1320 {
1321         return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
1322 }
1323
1324 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
1325                                    struct mv88e6xxx_vtu_stu_entry *entry)
1326 {
1327         return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
1328 }
1329
1330 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
1331                                          struct mv88e6xxx_vtu_stu_entry *entry,
1332                                          unsigned int nibble_offset)
1333 {
1334         u16 regs[3] = { 0 };
1335         int i;
1336         int ret;
1337
1338         for (i = 0; i < chip->info->num_ports; ++i) {
1339                 unsigned int shift = (i % 4) * 4 + nibble_offset;
1340                 u8 data = entry->data[i];
1341
1342                 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1343         }
1344
1345         for (i = 0; i < 3; ++i) {
1346                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL,
1347                                            GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1348                 if (ret < 0)
1349                         return ret;
1350         }
1351
1352         return 0;
1353 }
1354
1355 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
1356                                     struct mv88e6xxx_vtu_stu_entry *entry)
1357 {
1358         return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
1359 }
1360
1361 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
1362                                     struct mv88e6xxx_vtu_stu_entry *entry)
1363 {
1364         return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
1365 }
1366
1367 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
1368 {
1369         return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID,
1370                                     vid & GLOBAL_VTU_VID_MASK);
1371 }
1372
1373 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1374                                   struct mv88e6xxx_vtu_stu_entry *entry)
1375 {
1376         struct mv88e6xxx_vtu_stu_entry next = { 0 };
1377         int ret;
1378
1379         ret = _mv88e6xxx_vtu_wait(chip);
1380         if (ret < 0)
1381                 return ret;
1382
1383         ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1384         if (ret < 0)
1385                 return ret;
1386
1387         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
1388         if (ret < 0)
1389                 return ret;
1390
1391         next.vid = ret & GLOBAL_VTU_VID_MASK;
1392         next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1393
1394         if (next.valid) {
1395                 ret = mv88e6xxx_vtu_data_read(chip, &next);
1396                 if (ret < 0)
1397                         return ret;
1398
1399                 if (mv88e6xxx_has_fid_reg(chip)) {
1400                         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1401                                                   GLOBAL_VTU_FID);
1402                         if (ret < 0)
1403                                 return ret;
1404
1405                         next.fid = ret & GLOBAL_VTU_FID_MASK;
1406                 } else if (mv88e6xxx_num_databases(chip) == 256) {
1407                         /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1408                          * VTU DBNum[3:0] are located in VTU Operation 3:0
1409                          */
1410                         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1411                                                   GLOBAL_VTU_OP);
1412                         if (ret < 0)
1413                                 return ret;
1414
1415                         next.fid = (ret & 0xf00) >> 4;
1416                         next.fid |= ret & 0xf;
1417                 }
1418
1419                 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1420                         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1421                                                   GLOBAL_VTU_SID);
1422                         if (ret < 0)
1423                                 return ret;
1424
1425                         next.sid = ret & GLOBAL_VTU_SID_MASK;
1426                 }
1427         }
1428
1429         *entry = next;
1430         return 0;
1431 }
1432
1433 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1434                                     struct switchdev_obj_port_vlan *vlan,
1435                                     int (*cb)(struct switchdev_obj *obj))
1436 {
1437         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1438         struct mv88e6xxx_vtu_stu_entry next;
1439         u16 pvid;
1440         int err;
1441
1442         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1443                 return -EOPNOTSUPP;
1444
1445         mutex_lock(&chip->reg_lock);
1446
1447         err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
1448         if (err)
1449                 goto unlock;
1450
1451         err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1452         if (err)
1453                 goto unlock;
1454
1455         do {
1456                 err = _mv88e6xxx_vtu_getnext(chip, &next);
1457                 if (err)
1458                         break;
1459
1460                 if (!next.valid)
1461                         break;
1462
1463                 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1464                         continue;
1465
1466                 /* reinit and dump this VLAN obj */
1467                 vlan->vid_begin = next.vid;
1468                 vlan->vid_end = next.vid;
1469                 vlan->flags = 0;
1470
1471                 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1472                         vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1473
1474                 if (next.vid == pvid)
1475                         vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1476
1477                 err = cb(&vlan->obj);
1478                 if (err)
1479                         break;
1480         } while (next.vid < GLOBAL_VTU_VID_MASK);
1481
1482 unlock:
1483         mutex_unlock(&chip->reg_lock);
1484
1485         return err;
1486 }
1487
1488 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1489                                     struct mv88e6xxx_vtu_stu_entry *entry)
1490 {
1491         u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
1492         u16 reg = 0;
1493         int ret;
1494
1495         ret = _mv88e6xxx_vtu_wait(chip);
1496         if (ret < 0)
1497                 return ret;
1498
1499         if (!entry->valid)
1500                 goto loadpurge;
1501
1502         /* Write port member tags */
1503         ret = mv88e6xxx_vtu_data_write(chip, entry);
1504         if (ret < 0)
1505                 return ret;
1506
1507         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1508                 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1509                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1510                                            reg);
1511                 if (ret < 0)
1512                         return ret;
1513         }
1514
1515         if (mv88e6xxx_has_fid_reg(chip)) {
1516                 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1517                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_FID,
1518                                            reg);
1519                 if (ret < 0)
1520                         return ret;
1521         } else if (mv88e6xxx_num_databases(chip) == 256) {
1522                 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1523                  * VTU DBNum[3:0] are located in VTU Operation 3:0
1524                  */
1525                 op |= (entry->fid & 0xf0) << 8;
1526                 op |= entry->fid & 0xf;
1527         }
1528
1529         reg = GLOBAL_VTU_VID_VALID;
1530 loadpurge:
1531         reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1532         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1533         if (ret < 0)
1534                 return ret;
1535
1536         return _mv88e6xxx_vtu_cmd(chip, op);
1537 }
1538
1539 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
1540                                   struct mv88e6xxx_vtu_stu_entry *entry)
1541 {
1542         struct mv88e6xxx_vtu_stu_entry next = { 0 };
1543         int ret;
1544
1545         ret = _mv88e6xxx_vtu_wait(chip);
1546         if (ret < 0)
1547                 return ret;
1548
1549         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1550                                    sid & GLOBAL_VTU_SID_MASK);
1551         if (ret < 0)
1552                 return ret;
1553
1554         ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1555         if (ret < 0)
1556                 return ret;
1557
1558         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_SID);
1559         if (ret < 0)
1560                 return ret;
1561
1562         next.sid = ret & GLOBAL_VTU_SID_MASK;
1563
1564         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
1565         if (ret < 0)
1566                 return ret;
1567
1568         next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1569
1570         if (next.valid) {
1571                 ret = mv88e6xxx_stu_data_read(chip, &next);
1572                 if (ret < 0)
1573                         return ret;
1574         }
1575
1576         *entry = next;
1577         return 0;
1578 }
1579
1580 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1581                                     struct mv88e6xxx_vtu_stu_entry *entry)
1582 {
1583         u16 reg = 0;
1584         int ret;
1585
1586         ret = _mv88e6xxx_vtu_wait(chip);
1587         if (ret < 0)
1588                 return ret;
1589
1590         if (!entry->valid)
1591                 goto loadpurge;
1592
1593         /* Write port states */
1594         ret = mv88e6xxx_stu_data_write(chip, entry);
1595         if (ret < 0)
1596                 return ret;
1597
1598         reg = GLOBAL_VTU_VID_VALID;
1599 loadpurge:
1600         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1601         if (ret < 0)
1602                 return ret;
1603
1604         reg = entry->sid & GLOBAL_VTU_SID_MASK;
1605         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1606         if (ret < 0)
1607                 return ret;
1608
1609         return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1610 }
1611
1612 static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip *chip, int port,
1613                                u16 *new, u16 *old)
1614 {
1615         struct dsa_switch *ds = chip->ds;
1616         u16 upper_mask;
1617         u16 fid;
1618         int ret;
1619
1620         if (mv88e6xxx_num_databases(chip) == 4096)
1621                 upper_mask = 0xff;
1622         else if (mv88e6xxx_num_databases(chip) == 256)
1623                 upper_mask = 0xf;
1624         else
1625                 return -EOPNOTSUPP;
1626
1627         /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1628         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
1629         if (ret < 0)
1630                 return ret;
1631
1632         fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1633
1634         if (new) {
1635                 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1636                 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1637
1638                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN,
1639                                            ret);
1640                 if (ret < 0)
1641                         return ret;
1642         }
1643
1644         /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1645         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_1);
1646         if (ret < 0)
1647                 return ret;
1648
1649         fid |= (ret & upper_mask) << 4;
1650
1651         if (new) {
1652                 ret &= ~upper_mask;
1653                 ret |= (*new >> 4) & upper_mask;
1654
1655                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
1656                                            ret);
1657                 if (ret < 0)
1658                         return ret;
1659
1660                 netdev_dbg(ds->ports[port].netdev,
1661                            "FID %d (was %d)\n", *new, fid);
1662         }
1663
1664         if (old)
1665                 *old = fid;
1666
1667         return 0;
1668 }
1669
1670 static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_chip *chip,
1671                                    int port, u16 *fid)
1672 {
1673         return _mv88e6xxx_port_fid(chip, port, NULL, fid);
1674 }
1675
1676 static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_chip *chip,
1677                                    int port, u16 fid)
1678 {
1679         return _mv88e6xxx_port_fid(chip, port, &fid, NULL);
1680 }
1681
1682 static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
1683 {
1684         DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1685         struct mv88e6xxx_vtu_stu_entry vlan;
1686         int i, err;
1687
1688         bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1689
1690         /* Set every FID bit used by the (un)bridged ports */
1691         for (i = 0; i < chip->info->num_ports; ++i) {
1692                 err = _mv88e6xxx_port_fid_get(chip, i, fid);
1693                 if (err)
1694                         return err;
1695
1696                 set_bit(*fid, fid_bitmap);
1697         }
1698
1699         /* Set every FID bit used by the VLAN entries */
1700         err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1701         if (err)
1702                 return err;
1703
1704         do {
1705                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1706                 if (err)
1707                         return err;
1708
1709                 if (!vlan.valid)
1710                         break;
1711
1712                 set_bit(vlan.fid, fid_bitmap);
1713         } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1714
1715         /* The reset value 0x000 is used to indicate that multiple address
1716          * databases are not needed. Return the next positive available.
1717          */
1718         *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1719         if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1720                 return -ENOSPC;
1721
1722         /* Clear the database */
1723         return _mv88e6xxx_atu_flush(chip, *fid, true);
1724 }
1725
1726 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
1727                               struct mv88e6xxx_vtu_stu_entry *entry)
1728 {
1729         struct dsa_switch *ds = chip->ds;
1730         struct mv88e6xxx_vtu_stu_entry vlan = {
1731                 .valid = true,
1732                 .vid = vid,
1733         };
1734         int i, err;
1735
1736         err = _mv88e6xxx_fid_new(chip, &vlan.fid);
1737         if (err)
1738                 return err;
1739
1740         /* exclude all ports except the CPU and DSA ports */
1741         for (i = 0; i < chip->info->num_ports; ++i)
1742                 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1743                         ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1744                         : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1745
1746         if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1747             mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
1748                 struct mv88e6xxx_vtu_stu_entry vstp;
1749
1750                 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1751                  * implemented, only one STU entry is needed to cover all VTU
1752                  * entries. Thus, validate the SID 0.
1753                  */
1754                 vlan.sid = 0;
1755                 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
1756                 if (err)
1757                         return err;
1758
1759                 if (vstp.sid != vlan.sid || !vstp.valid) {
1760                         memset(&vstp, 0, sizeof(vstp));
1761                         vstp.valid = true;
1762                         vstp.sid = vlan.sid;
1763
1764                         err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
1765                         if (err)
1766                                 return err;
1767                 }
1768         }
1769
1770         *entry = vlan;
1771         return 0;
1772 }
1773
1774 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1775                               struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1776 {
1777         int err;
1778
1779         if (!vid)
1780                 return -EINVAL;
1781
1782         err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
1783         if (err)
1784                 return err;
1785
1786         err = _mv88e6xxx_vtu_getnext(chip, entry);
1787         if (err)
1788                 return err;
1789
1790         if (entry->vid != vid || !entry->valid) {
1791                 if (!creat)
1792                         return -EOPNOTSUPP;
1793                 /* -ENOENT would've been more appropriate, but switchdev expects
1794                  * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1795                  */
1796
1797                 err = _mv88e6xxx_vtu_new(chip, vid, entry);
1798         }
1799
1800         return err;
1801 }
1802
1803 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1804                                         u16 vid_begin, u16 vid_end)
1805 {
1806         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1807         struct mv88e6xxx_vtu_stu_entry vlan;
1808         int i, err;
1809
1810         if (!vid_begin)
1811                 return -EOPNOTSUPP;
1812
1813         mutex_lock(&chip->reg_lock);
1814
1815         err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
1816         if (err)
1817                 goto unlock;
1818
1819         do {
1820                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1821                 if (err)
1822                         goto unlock;
1823
1824                 if (!vlan.valid)
1825                         break;
1826
1827                 if (vlan.vid > vid_end)
1828                         break;
1829
1830                 for (i = 0; i < chip->info->num_ports; ++i) {
1831                         if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1832                                 continue;
1833
1834                         if (vlan.data[i] ==
1835                             GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1836                                 continue;
1837
1838                         if (chip->ports[i].bridge_dev ==
1839                             chip->ports[port].bridge_dev)
1840                                 break; /* same bridge, check next VLAN */
1841
1842                         netdev_warn(ds->ports[port].netdev,
1843                                     "hardware VLAN %d already used by %s\n",
1844                                     vlan.vid,
1845                                     netdev_name(chip->ports[i].bridge_dev));
1846                         err = -EOPNOTSUPP;
1847                         goto unlock;
1848                 }
1849         } while (vlan.vid < vid_end);
1850
1851 unlock:
1852         mutex_unlock(&chip->reg_lock);
1853
1854         return err;
1855 }
1856
1857 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1858         [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
1859         [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
1860         [PORT_CONTROL_2_8021Q_CHECK] = "Check",
1861         [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
1862 };
1863
1864 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1865                                          bool vlan_filtering)
1866 {
1867         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1868         u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1869                 PORT_CONTROL_2_8021Q_DISABLED;
1870         int ret;
1871
1872         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1873                 return -EOPNOTSUPP;
1874
1875         mutex_lock(&chip->reg_lock);
1876
1877         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_2);
1878         if (ret < 0)
1879                 goto unlock;
1880
1881         old = ret & PORT_CONTROL_2_8021Q_MASK;
1882
1883         if (new != old) {
1884                 ret &= ~PORT_CONTROL_2_8021Q_MASK;
1885                 ret |= new & PORT_CONTROL_2_8021Q_MASK;
1886
1887                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_2,
1888                                            ret);
1889                 if (ret < 0)
1890                         goto unlock;
1891
1892                 netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n",
1893                            mv88e6xxx_port_8021q_mode_names[new],
1894                            mv88e6xxx_port_8021q_mode_names[old]);
1895         }
1896
1897         ret = 0;
1898 unlock:
1899         mutex_unlock(&chip->reg_lock);
1900
1901         return ret;
1902 }
1903
1904 static int
1905 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1906                             const struct switchdev_obj_port_vlan *vlan,
1907                             struct switchdev_trans *trans)
1908 {
1909         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1910         int err;
1911
1912         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1913                 return -EOPNOTSUPP;
1914
1915         /* If the requested port doesn't belong to the same bridge as the VLAN
1916          * members, do not support it (yet) and fallback to software VLAN.
1917          */
1918         err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1919                                            vlan->vid_end);
1920         if (err)
1921                 return err;
1922
1923         /* We don't need any dynamic resource from the kernel (yet),
1924          * so skip the prepare phase.
1925          */
1926         return 0;
1927 }
1928
1929 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1930                                     u16 vid, bool untagged)
1931 {
1932         struct mv88e6xxx_vtu_stu_entry vlan;
1933         int err;
1934
1935         err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1936         if (err)
1937                 return err;
1938
1939         vlan.data[port] = untagged ?
1940                 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1941                 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1942
1943         return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1944 }
1945
1946 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1947                                     const struct switchdev_obj_port_vlan *vlan,
1948                                     struct switchdev_trans *trans)
1949 {
1950         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1951         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1952         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1953         u16 vid;
1954
1955         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1956                 return;
1957
1958         mutex_lock(&chip->reg_lock);
1959
1960         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1961                 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
1962                         netdev_err(ds->ports[port].netdev,
1963                                    "failed to add VLAN %d%c\n",
1964                                    vid, untagged ? 'u' : 't');
1965
1966         if (pvid && _mv88e6xxx_port_pvid_set(chip, port, vlan->vid_end))
1967                 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
1968                            vlan->vid_end);
1969
1970         mutex_unlock(&chip->reg_lock);
1971 }
1972
1973 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1974                                     int port, u16 vid)
1975 {
1976         struct dsa_switch *ds = chip->ds;
1977         struct mv88e6xxx_vtu_stu_entry vlan;
1978         int i, err;
1979
1980         err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1981         if (err)
1982                 return err;
1983
1984         /* Tell switchdev if this VLAN is handled in software */
1985         if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1986                 return -EOPNOTSUPP;
1987
1988         vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1989
1990         /* keep the VLAN unless all ports are excluded */
1991         vlan.valid = false;
1992         for (i = 0; i < chip->info->num_ports; ++i) {
1993                 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1994                         continue;
1995
1996                 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1997                         vlan.valid = true;
1998                         break;
1999                 }
2000         }
2001
2002         err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
2003         if (err)
2004                 return err;
2005
2006         return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
2007 }
2008
2009 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2010                                    const struct switchdev_obj_port_vlan *vlan)
2011 {
2012         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2013         u16 pvid, vid;
2014         int err = 0;
2015
2016         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
2017                 return -EOPNOTSUPP;
2018
2019         mutex_lock(&chip->reg_lock);
2020
2021         err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
2022         if (err)
2023                 goto unlock;
2024
2025         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
2026                 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
2027                 if (err)
2028                         goto unlock;
2029
2030                 if (vid == pvid) {
2031                         err = _mv88e6xxx_port_pvid_set(chip, port, 0);
2032                         if (err)
2033                                 goto unlock;
2034                 }
2035         }
2036
2037 unlock:
2038         mutex_unlock(&chip->reg_lock);
2039
2040         return err;
2041 }
2042
2043 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
2044                                     const unsigned char *addr)
2045 {
2046         int i, ret;
2047
2048         for (i = 0; i < 3; i++) {
2049                 ret = _mv88e6xxx_reg_write(
2050                         chip, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
2051                         (addr[i * 2] << 8) | addr[i * 2 + 1]);
2052                 if (ret < 0)
2053                         return ret;
2054         }
2055
2056         return 0;
2057 }
2058
2059 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
2060                                    unsigned char *addr)
2061 {
2062         int i, ret;
2063
2064         for (i = 0; i < 3; i++) {
2065                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
2066                                           GLOBAL_ATU_MAC_01 + i);
2067                 if (ret < 0)
2068                         return ret;
2069                 addr[i * 2] = ret >> 8;
2070                 addr[i * 2 + 1] = ret & 0xff;
2071         }
2072
2073         return 0;
2074 }
2075
2076 static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
2077                                struct mv88e6xxx_atu_entry *entry)
2078 {
2079         int ret;
2080
2081         ret = _mv88e6xxx_atu_wait(chip);
2082         if (ret < 0)
2083                 return ret;
2084
2085         ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
2086         if (ret < 0)
2087                 return ret;
2088
2089         ret = _mv88e6xxx_atu_data_write(chip, entry);
2090         if (ret < 0)
2091                 return ret;
2092
2093         return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
2094 }
2095
2096 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2097                                         const unsigned char *addr, u16 vid,
2098                                         u8 state)
2099 {
2100         struct mv88e6xxx_atu_entry entry = { 0 };
2101         struct mv88e6xxx_vtu_stu_entry vlan;
2102         int err;
2103
2104         /* Null VLAN ID corresponds to the port private database */
2105         if (vid == 0)
2106                 err = _mv88e6xxx_port_fid_get(chip, port, &vlan.fid);
2107         else
2108                 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
2109         if (err)
2110                 return err;
2111
2112         entry.fid = vlan.fid;
2113         entry.state = state;
2114         ether_addr_copy(entry.mac, addr);
2115         if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2116                 entry.trunk = false;
2117                 entry.portv_trunkid = BIT(port);
2118         }
2119
2120         return _mv88e6xxx_atu_load(chip, &entry);
2121 }
2122
2123 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2124                                       const struct switchdev_obj_port_fdb *fdb,
2125                                       struct switchdev_trans *trans)
2126 {
2127         /* We don't need any dynamic resource from the kernel (yet),
2128          * so skip the prepare phase.
2129          */
2130         return 0;
2131 }
2132
2133 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2134                                    const struct switchdev_obj_port_fdb *fdb,
2135                                    struct switchdev_trans *trans)
2136 {
2137         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2138
2139         mutex_lock(&chip->reg_lock);
2140         if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2141                                          GLOBAL_ATU_DATA_STATE_UC_STATIC))
2142                 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
2143         mutex_unlock(&chip->reg_lock);
2144 }
2145
2146 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2147                                   const struct switchdev_obj_port_fdb *fdb)
2148 {
2149         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2150         int err;
2151
2152         mutex_lock(&chip->reg_lock);
2153         err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2154                                            GLOBAL_ATU_DATA_STATE_UNUSED);
2155         mutex_unlock(&chip->reg_lock);
2156
2157         return err;
2158 }
2159
2160 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2161                                   struct mv88e6xxx_atu_entry *entry)
2162 {
2163         struct mv88e6xxx_atu_entry next = { 0 };
2164         int ret;
2165
2166         next.fid = fid;
2167
2168         ret = _mv88e6xxx_atu_wait(chip);
2169         if (ret < 0)
2170                 return ret;
2171
2172         ret = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2173         if (ret < 0)
2174                 return ret;
2175
2176         ret = _mv88e6xxx_atu_mac_read(chip, next.mac);
2177         if (ret < 0)
2178                 return ret;
2179
2180         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_DATA);
2181         if (ret < 0)
2182                 return ret;
2183
2184         next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2185         if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2186                 unsigned int mask, shift;
2187
2188                 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2189                         next.trunk = true;
2190                         mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2191                         shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2192                 } else {
2193                         next.trunk = false;
2194                         mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2195                         shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2196                 }
2197
2198                 next.portv_trunkid = (ret & mask) >> shift;
2199         }
2200
2201         *entry = next;
2202         return 0;
2203 }
2204
2205 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2206                                       u16 fid, u16 vid, int port,
2207                                       struct switchdev_obj *obj,
2208                                       int (*cb)(struct switchdev_obj *obj))
2209 {
2210         struct mv88e6xxx_atu_entry addr = {
2211                 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2212         };
2213         int err;
2214
2215         err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
2216         if (err)
2217                 return err;
2218
2219         do {
2220                 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
2221                 if (err)
2222                         return err;
2223
2224                 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2225                         break;
2226
2227                 if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0)
2228                         continue;
2229
2230                 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
2231                         struct switchdev_obj_port_fdb *fdb;
2232
2233                         if (!is_unicast_ether_addr(addr.mac))
2234                                 continue;
2235
2236                         fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
2237                         fdb->vid = vid;
2238                         ether_addr_copy(fdb->addr, addr.mac);
2239                         if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2240                                 fdb->ndm_state = NUD_NOARP;
2241                         else
2242                                 fdb->ndm_state = NUD_REACHABLE;
2243                 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
2244                         struct switchdev_obj_port_mdb *mdb;
2245
2246                         if (!is_multicast_ether_addr(addr.mac))
2247                                 continue;
2248
2249                         mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
2250                         mdb->vid = vid;
2251                         ether_addr_copy(mdb->addr, addr.mac);
2252                 } else {
2253                         return -EOPNOTSUPP;
2254                 }
2255
2256                 err = cb(obj);
2257                 if (err)
2258                         return err;
2259         } while (!is_broadcast_ether_addr(addr.mac));
2260
2261         return err;
2262 }
2263
2264 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2265                                   struct switchdev_obj *obj,
2266                                   int (*cb)(struct switchdev_obj *obj))
2267 {
2268         struct mv88e6xxx_vtu_stu_entry vlan = {
2269                 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2270         };
2271         u16 fid;
2272         int err;
2273
2274         /* Dump port's default Filtering Information Database (VLAN ID 0) */
2275         err = _mv88e6xxx_port_fid_get(chip, port, &fid);
2276         if (err)
2277                 return err;
2278
2279         err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2280         if (err)
2281                 return err;
2282
2283         /* Dump VLANs' Filtering Information Databases */
2284         err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
2285         if (err)
2286                 return err;
2287
2288         do {
2289                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
2290                 if (err)
2291                         return err;
2292
2293                 if (!vlan.valid)
2294                         break;
2295
2296                 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2297                                                  obj, cb);
2298                 if (err)
2299                         return err;
2300         } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2301
2302         return err;
2303 }
2304
2305 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2306                                    struct switchdev_obj_port_fdb *fdb,
2307                                    int (*cb)(struct switchdev_obj *obj))
2308 {
2309         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2310         int err;
2311
2312         mutex_lock(&chip->reg_lock);
2313         err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
2314         mutex_unlock(&chip->reg_lock);
2315
2316         return err;
2317 }
2318
2319 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2320                                       struct net_device *bridge)
2321 {
2322         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2323         int i, err = 0;
2324
2325         mutex_lock(&chip->reg_lock);
2326
2327         /* Assign the bridge and remap each port's VLANTable */
2328         chip->ports[port].bridge_dev = bridge;
2329
2330         for (i = 0; i < chip->info->num_ports; ++i) {
2331                 if (chip->ports[i].bridge_dev == bridge) {
2332                         err = _mv88e6xxx_port_based_vlan_map(chip, i);
2333                         if (err)
2334                                 break;
2335                 }
2336         }
2337
2338         mutex_unlock(&chip->reg_lock);
2339
2340         return err;
2341 }
2342
2343 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2344 {
2345         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2346         struct net_device *bridge = chip->ports[port].bridge_dev;
2347         int i;
2348
2349         mutex_lock(&chip->reg_lock);
2350
2351         /* Unassign the bridge and remap each port's VLANTable */
2352         chip->ports[port].bridge_dev = NULL;
2353
2354         for (i = 0; i < chip->info->num_ports; ++i)
2355                 if (i == port || chip->ports[i].bridge_dev == bridge)
2356                         if (_mv88e6xxx_port_based_vlan_map(chip, i))
2357                                 netdev_warn(ds->ports[i].netdev,
2358                                             "failed to remap\n");
2359
2360         mutex_unlock(&chip->reg_lock);
2361 }
2362
2363 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2364 {
2365         bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
2366         u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2367         struct gpio_desc *gpiod = chip->reset;
2368         unsigned long timeout;
2369         int ret;
2370         int i;
2371
2372         /* Set all ports to the disabled state. */
2373         for (i = 0; i < chip->info->num_ports; i++) {
2374                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(i), PORT_CONTROL);
2375                 if (ret < 0)
2376                         return ret;
2377
2378                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(i), PORT_CONTROL,
2379                                            ret & 0xfffc);
2380                 if (ret)
2381                         return ret;
2382         }
2383
2384         /* Wait for transmit queues to drain. */
2385         usleep_range(2000, 4000);
2386
2387         /* If there is a gpio connected to the reset pin, toggle it */
2388         if (gpiod) {
2389                 gpiod_set_value_cansleep(gpiod, 1);
2390                 usleep_range(10000, 20000);
2391                 gpiod_set_value_cansleep(gpiod, 0);
2392                 usleep_range(10000, 20000);
2393         }
2394
2395         /* Reset the switch. Keep the PPU active if requested. The PPU
2396          * needs to be active to support indirect phy register access
2397          * through global registers 0x18 and 0x19.
2398          */
2399         if (ppu_active)
2400                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc000);
2401         else
2402                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc400);
2403         if (ret)
2404                 return ret;
2405
2406         /* Wait up to one second for reset to complete. */
2407         timeout = jiffies + 1 * HZ;
2408         while (time_before(jiffies, timeout)) {
2409                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, 0x00);
2410                 if (ret < 0)
2411                         return ret;
2412
2413                 if ((ret & is_reset) == is_reset)
2414                         break;
2415                 usleep_range(1000, 2000);
2416         }
2417         if (time_after(jiffies, timeout))
2418                 ret = -ETIMEDOUT;
2419         else
2420                 ret = 0;
2421
2422         return ret;
2423 }
2424
2425 static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
2426 {
2427         u16 val;
2428         int err;
2429
2430         /* Clear Power Down bit */
2431         err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2432         if (err)
2433                 return err;
2434
2435         if (val & BMCR_PDOWN) {
2436                 val &= ~BMCR_PDOWN;
2437                 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
2438         }
2439
2440         return err;
2441 }
2442
2443 static int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port,
2444                                int reg, u16 *val)
2445 {
2446         int addr = chip->info->port_base_addr + port;
2447
2448         if (port >= chip->info->num_ports)
2449                 return -EINVAL;
2450
2451         return mv88e6xxx_read(chip, addr, reg, val);
2452 }
2453
2454 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2455 {
2456         struct dsa_switch *ds = chip->ds;
2457         int ret;
2458         u16 reg;
2459
2460         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2461             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2462             mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2463             mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) {
2464                 /* MAC Forcing register: don't force link, speed,
2465                  * duplex or flow control state to any particular
2466                  * values on physical ports, but force the CPU port
2467                  * and all DSA ports to their maximum bandwidth and
2468                  * full duplex.
2469                  */
2470                 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
2471                 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
2472                         reg &= ~PORT_PCS_CTRL_UNFORCED;
2473                         reg |= PORT_PCS_CTRL_FORCE_LINK |
2474                                 PORT_PCS_CTRL_LINK_UP |
2475                                 PORT_PCS_CTRL_DUPLEX_FULL |
2476                                 PORT_PCS_CTRL_FORCE_DUPLEX;
2477                         if (mv88e6xxx_6065_family(chip))
2478                                 reg |= PORT_PCS_CTRL_100;
2479                         else
2480                                 reg |= PORT_PCS_CTRL_1000;
2481                 } else {
2482                         reg |= PORT_PCS_CTRL_UNFORCED;
2483                 }
2484
2485                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2486                                            PORT_PCS_CTRL, reg);
2487                 if (ret)
2488                         return ret;
2489         }
2490
2491         /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2492          * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2493          * tunneling, determine priority by looking at 802.1p and IP
2494          * priority fields (IP prio has precedence), and set STP state
2495          * to Forwarding.
2496          *
2497          * If this is the CPU link, use DSA or EDSA tagging depending
2498          * on which tagging mode was configured.
2499          *
2500          * If this is a link to another switch, use DSA tagging mode.
2501          *
2502          * If this is the upstream port for this switch, enable
2503          * forwarding of unknown unicasts and multicasts.
2504          */
2505         reg = 0;
2506         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2507             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2508             mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2509             mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
2510                 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2511                 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2512                 PORT_CONTROL_STATE_FORWARDING;
2513         if (dsa_is_cpu_port(ds, port)) {
2514                 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
2515                         reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
2516                                 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2517                 else
2518                         reg |= PORT_CONTROL_DSA_TAG;
2519                 reg |= PORT_CONTROL_EGRESS_ADD_TAG |
2520                         PORT_CONTROL_FORWARD_UNKNOWN;
2521         }
2522         if (dsa_is_dsa_port(ds, port)) {
2523                 if (mv88e6xxx_6095_family(chip) ||
2524                     mv88e6xxx_6185_family(chip))
2525                         reg |= PORT_CONTROL_DSA_TAG;
2526                 if (mv88e6xxx_6352_family(chip) ||
2527                     mv88e6xxx_6351_family(chip) ||
2528                     mv88e6xxx_6165_family(chip) ||
2529                     mv88e6xxx_6097_family(chip) ||
2530                     mv88e6xxx_6320_family(chip)) {
2531                         reg |= PORT_CONTROL_FRAME_MODE_DSA;
2532                 }
2533
2534                 if (port == dsa_upstream_port(ds))
2535                         reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2536                                 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2537         }
2538         if (reg) {
2539                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2540                                            PORT_CONTROL, reg);
2541                 if (ret)
2542                         return ret;
2543         }
2544
2545         /* If this port is connected to a SerDes, make sure the SerDes is not
2546          * powered down.
2547          */
2548         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
2549                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
2550                 if (ret < 0)
2551                         return ret;
2552                 ret &= PORT_STATUS_CMODE_MASK;
2553                 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2554                     (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2555                     (ret == PORT_STATUS_CMODE_SGMII)) {
2556                         ret = mv88e6xxx_serdes_power_on(chip);
2557                         if (ret < 0)
2558                                 return ret;
2559                 }
2560         }
2561
2562         /* Port Control 2: don't force a good FCS, set the maximum frame size to
2563          * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2564          * untagged frames on this port, do a destination address lookup on all
2565          * received packets as usual, disable ARP mirroring and don't send a
2566          * copy of all transmitted/received frames on this port to the CPU.
2567          */
2568         reg = 0;
2569         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2570             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2571             mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2572             mv88e6xxx_6185_family(chip))
2573                 reg = PORT_CONTROL_2_MAP_DA;
2574
2575         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2576             mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
2577                 reg |= PORT_CONTROL_2_JUMBO_10240;
2578
2579         if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
2580                 /* Set the upstream port this port should use */
2581                 reg |= dsa_upstream_port(ds);
2582                 /* enable forwarding of unknown multicast addresses to
2583                  * the upstream port
2584                  */
2585                 if (port == dsa_upstream_port(ds))
2586                         reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2587         }
2588
2589         reg |= PORT_CONTROL_2_8021Q_DISABLED;
2590
2591         if (reg) {
2592                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2593                                            PORT_CONTROL_2, reg);
2594                 if (ret)
2595                         return ret;
2596         }
2597
2598         /* Port Association Vector: when learning source addresses
2599          * of packets, add the address to the address database using
2600          * a port bitmap that has only the bit for this port set and
2601          * the other bits clear.
2602          */
2603         reg = 1 << port;
2604         /* Disable learning for CPU port */
2605         if (dsa_is_cpu_port(ds, port))
2606                 reg = 0;
2607
2608         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_ASSOC_VECTOR,
2609                                    reg);
2610         if (ret)
2611                 return ret;
2612
2613         /* Egress rate control 2: disable egress rate control. */
2614         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_RATE_CONTROL_2,
2615                                    0x0000);
2616         if (ret)
2617                 return ret;
2618
2619         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2620             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2621             mv88e6xxx_6320_family(chip)) {
2622                 /* Do not limit the period of time that this port can
2623                  * be paused for by the remote end or the period of
2624                  * time that this port can pause the remote end.
2625                  */
2626                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2627                                            PORT_PAUSE_CTRL, 0x0000);
2628                 if (ret)
2629                         return ret;
2630
2631                 /* Port ATU control: disable limiting the number of
2632                  * address database entries that this port is allowed
2633                  * to use.
2634                  */
2635                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2636                                            PORT_ATU_CONTROL, 0x0000);
2637                 /* Priority Override: disable DA, SA and VTU priority
2638                  * override.
2639                  */
2640                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2641                                            PORT_PRI_OVERRIDE, 0x0000);
2642                 if (ret)
2643                         return ret;
2644
2645                 /* Port Ethertype: use the Ethertype DSA Ethertype
2646                  * value.
2647                  */
2648                 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) {
2649                         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2650                                                    PORT_ETH_TYPE, ETH_P_EDSA);
2651                         if (ret)
2652                                 return ret;
2653                 }
2654
2655                 /* Tag Remap: use an identity 802.1p prio -> switch
2656                  * prio mapping.
2657                  */
2658                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2659                                            PORT_TAG_REGMAP_0123, 0x3210);
2660                 if (ret)
2661                         return ret;
2662
2663                 /* Tag Remap 2: use an identity 802.1p prio -> switch
2664                  * prio mapping.
2665                  */
2666                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2667                                            PORT_TAG_REGMAP_4567, 0x7654);
2668                 if (ret)
2669                         return ret;
2670         }
2671
2672         /* Rate Control: disable ingress rate limiting. */
2673         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2674             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2675             mv88e6xxx_6320_family(chip)) {
2676                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2677                                            PORT_RATE_CONTROL, 0x0001);
2678                 if (ret)
2679                         return ret;
2680         } else if (mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip)) {
2681                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2682                                            PORT_RATE_CONTROL, 0x0000);
2683                 if (ret)
2684                         return ret;
2685         }
2686
2687         /* Port Control 1: disable trunking, disable sending
2688          * learning messages to this port.
2689          */
2690         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
2691                                    0x0000);
2692         if (ret)
2693                 return ret;
2694
2695         /* Port based VLAN map: give each port the same default address
2696          * database, and allow bidirectional communication between the
2697          * CPU and DSA port(s), and the other ports.
2698          */
2699         ret = _mv88e6xxx_port_fid_set(chip, port, 0);
2700         if (ret)
2701                 return ret;
2702
2703         ret = _mv88e6xxx_port_based_vlan_map(chip, port);
2704         if (ret)
2705                 return ret;
2706
2707         /* Default VLAN ID and priority: don't set a default VLAN
2708          * ID, and set the default packet priority to zero.
2709          */
2710         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_DEFAULT_VLAN,
2711                                    0x0000);
2712         if (ret)
2713                 return ret;
2714
2715         return 0;
2716 }
2717
2718 static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2719 {
2720         int err;
2721
2722         err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_01,
2723                               (addr[0] << 8) | addr[1]);
2724         if (err)
2725                 return err;
2726
2727         err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_23,
2728                               (addr[2] << 8) | addr[3]);
2729         if (err)
2730                 return err;
2731
2732         return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_45,
2733                                (addr[4] << 8) | addr[5]);
2734 }
2735
2736 static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2737                                      unsigned int msecs)
2738 {
2739         const unsigned int coeff = chip->info->age_time_coeff;
2740         const unsigned int min = 0x01 * coeff;
2741         const unsigned int max = 0xff * coeff;
2742         u8 age_time;
2743         u16 val;
2744         int err;
2745
2746         if (msecs < min || msecs > max)
2747                 return -ERANGE;
2748
2749         /* Round to nearest multiple of coeff */
2750         age_time = (msecs + coeff / 2) / coeff;
2751
2752         err = mv88e6xxx_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, &val);
2753         if (err)
2754                 return err;
2755
2756         /* AgeTime is 11:4 bits */
2757         val &= ~0xff0;
2758         val |= age_time << 4;
2759
2760         return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, val);
2761 }
2762
2763 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2764                                      unsigned int ageing_time)
2765 {
2766         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2767         int err;
2768
2769         mutex_lock(&chip->reg_lock);
2770         err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2771         mutex_unlock(&chip->reg_lock);
2772
2773         return err;
2774 }
2775
2776 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
2777 {
2778         struct dsa_switch *ds = chip->ds;
2779         u32 upstream_port = dsa_upstream_port(ds);
2780         u16 reg;
2781         int err;
2782
2783         /* Enable the PHY Polling Unit if present, don't discard any packets,
2784          * and mask all interrupt sources.
2785          */
2786         reg = 0;
2787         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
2788             mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
2789                 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2790
2791         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL, reg);
2792         if (err)
2793                 return err;
2794
2795         /* Configure the upstream port, and configure it as the port to which
2796          * ingress and egress and ARP monitor frames are to be sent.
2797          */
2798         reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2799                 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2800                 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
2801         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MONITOR_CONTROL,
2802                                    reg);
2803         if (err)
2804                 return err;
2805
2806         /* Disable remote management, and set the switch's DSA device number. */
2807         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL_2,
2808                                    GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2809                                    (ds->index & 0x1f));
2810         if (err)
2811                 return err;
2812
2813         /* Clear all the VTU and STU entries */
2814         err = _mv88e6xxx_vtu_stu_flush(chip);
2815         if (err < 0)
2816                 return err;
2817
2818         /* Set the default address aging time to 5 minutes, and
2819          * enable address learn messages to be sent to all message
2820          * ports.
2821          */
2822         err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
2823                               GLOBAL_ATU_CONTROL_LEARN2ALL);
2824         if (err)
2825                 return err;
2826
2827         err = mv88e6xxx_g1_set_age_time(chip, 300000);
2828         if (err)
2829                 return err;
2830
2831         /* Clear all ATU entries */
2832         err = _mv88e6xxx_atu_flush(chip, 0, true);
2833         if (err)
2834                 return err;
2835
2836         /* Configure the IP ToS mapping registers. */
2837         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2838         if (err)
2839                 return err;
2840         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2841         if (err)
2842                 return err;
2843         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2844         if (err)
2845                 return err;
2846         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2847         if (err)
2848                 return err;
2849         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2850         if (err)
2851                 return err;
2852         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2853         if (err)
2854                 return err;
2855         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2856         if (err)
2857                 return err;
2858         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2859         if (err)
2860                 return err;
2861
2862         /* Configure the IEEE 802.1p priority mapping register. */
2863         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2864         if (err)
2865                 return err;
2866
2867         /* Clear the statistics counters for all ports */
2868         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
2869                                    GLOBAL_STATS_OP_FLUSH_ALL);
2870         if (err)
2871                 return err;
2872
2873         /* Wait for the flush to complete. */
2874         err = _mv88e6xxx_stats_wait(chip);
2875         if (err)
2876                 return err;
2877
2878         return 0;
2879 }
2880
2881 static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
2882                                              int target, int port)
2883 {
2884         u16 val = (target << 8) | (port & 0xf);
2885
2886         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING, val);
2887 }
2888
2889 static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip *chip)
2890 {
2891         int target, port;
2892         int err;
2893
2894         /* Initialize the routing port to the 32 possible target devices */
2895         for (target = 0; target < 32; ++target) {
2896                 port = 0xf;
2897
2898                 if (target < DSA_MAX_SWITCHES) {
2899                         port = chip->ds->rtable[target];
2900                         if (port == DSA_RTABLE_NONE)
2901                                 port = 0xf;
2902                 }
2903
2904                 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
2905                 if (err)
2906                         break;
2907         }
2908
2909         return err;
2910 }
2911
2912 static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
2913                                          bool hask, u16 mask)
2914 {
2915         const u16 port_mask = BIT(chip->info->num_ports) - 1;
2916         u16 val = (num << 12) | (mask & port_mask);
2917
2918         if (hask)
2919                 val |= GLOBAL2_TRUNK_MASK_HASK;
2920
2921         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MASK, val);
2922 }
2923
2924 static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
2925                                             u16 map)
2926 {
2927         const u16 port_mask = BIT(chip->info->num_ports) - 1;
2928         u16 val = (id << 11) | (map & port_mask);
2929
2930         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING, val);
2931 }
2932
2933 static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip)
2934 {
2935         const u16 port_mask = BIT(chip->info->num_ports) - 1;
2936         int i, err;
2937
2938         /* Clear all eight possible Trunk Mask vectors */
2939         for (i = 0; i < 8; ++i) {
2940                 err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask);
2941                 if (err)
2942                         return err;
2943         }
2944
2945         /* Clear all sixteen possible Trunk ID routing vectors */
2946         for (i = 0; i < 16; ++i) {
2947                 err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0);
2948                 if (err)
2949                         return err;
2950         }
2951
2952         return 0;
2953 }
2954
2955 static int mv88e6xxx_g2_clear_irl(struct mv88e6xxx_chip *chip)
2956 {
2957         int port, err;
2958
2959         /* Init all Ingress Rate Limit resources of all ports */
2960         for (port = 0; port < chip->info->num_ports; ++port) {
2961                 /* XXX newer chips (like 88E6390) have different 2-bit ops */
2962                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
2963                                       GLOBAL2_IRL_CMD_OP_INIT_ALL |
2964                                       (port << 8));
2965                 if (err)
2966                         break;
2967
2968                 /* Wait for the operation to complete */
2969                 err = mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
2970                                      GLOBAL2_IRL_CMD_BUSY);
2971                 if (err)
2972                         break;
2973         }
2974
2975         return err;
2976 }
2977
2978 /* Indirect write to the Switch MAC/WoL/WoF register */
2979 static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
2980                                          unsigned int pointer, u8 data)
2981 {
2982         u16 val = (pointer << 8) | data;
2983
2984         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MAC, val);
2985 }
2986
2987 static int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2988 {
2989         int i, err;
2990
2991         for (i = 0; i < 6; i++) {
2992                 err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]);
2993                 if (err)
2994                         break;
2995         }
2996
2997         return err;
2998 }
2999
3000 static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer,
3001                                   u8 data)
3002 {
3003         u16 val = (pointer << 8) | (data & 0x7);
3004
3005         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE, val);
3006 }
3007
3008 static int mv88e6xxx_g2_clear_pot(struct mv88e6xxx_chip *chip)
3009 {
3010         int i, err;
3011
3012         /* Clear all sixteen possible Priority Override entries */
3013         for (i = 0; i < 16; i++) {
3014                 err = mv88e6xxx_g2_pot_write(chip, i, 0);
3015                 if (err)
3016                         break;
3017         }
3018
3019         return err;
3020 }
3021
3022 static int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip)
3023 {
3024         return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD,
3025                               GLOBAL2_EEPROM_CMD_BUSY |
3026                               GLOBAL2_EEPROM_CMD_RUNNING);
3027 }
3028
3029 static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
3030 {
3031         int err;
3032
3033         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, cmd);
3034         if (err)
3035                 return err;
3036
3037         return mv88e6xxx_g2_eeprom_wait(chip);
3038 }
3039
3040 static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip,
3041                                       u8 addr, u16 *data)
3042 {
3043         u16 cmd = GLOBAL2_EEPROM_CMD_OP_READ | addr;
3044         int err;
3045
3046         err = mv88e6xxx_g2_eeprom_wait(chip);
3047         if (err)
3048                 return err;
3049
3050         err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
3051         if (err)
3052                 return err;
3053
3054         return mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
3055 }
3056
3057 static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip,
3058                                        u8 addr, u16 data)
3059 {
3060         u16 cmd = GLOBAL2_EEPROM_CMD_OP_WRITE | addr;
3061         int err;
3062
3063         err = mv88e6xxx_g2_eeprom_wait(chip);
3064         if (err)
3065                 return err;
3066
3067         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
3068         if (err)
3069                 return err;
3070
3071         return mv88e6xxx_g2_eeprom_cmd(chip, cmd);
3072 }
3073
3074 static int mv88e6xxx_g2_smi_phy_wait(struct mv88e6xxx_chip *chip)
3075 {
3076         return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_CMD,
3077                               GLOBAL2_SMI_PHY_CMD_BUSY);
3078 }
3079
3080 static int mv88e6xxx_g2_smi_phy_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
3081 {
3082         int err;
3083
3084         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_CMD, cmd);
3085         if (err)
3086                 return err;
3087
3088         return mv88e6xxx_g2_smi_phy_wait(chip);
3089 }
3090
3091 static int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, int addr,
3092                                      int reg, u16 *val)
3093 {
3094         u16 cmd = GLOBAL2_SMI_PHY_CMD_OP_22_READ_DATA | (addr << 5) | reg;
3095         int err;
3096
3097         err = mv88e6xxx_g2_smi_phy_wait(chip);
3098         if (err)
3099                 return err;
3100
3101         err = mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
3102         if (err)
3103                 return err;
3104
3105         return mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_DATA, val);
3106 }
3107
3108 static int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, int addr,
3109                                       int reg, u16 val)
3110 {
3111         u16 cmd = GLOBAL2_SMI_PHY_CMD_OP_22_WRITE_DATA | (addr << 5) | reg;
3112         int err;
3113
3114         err = mv88e6xxx_g2_smi_phy_wait(chip);
3115         if (err)
3116                 return err;
3117
3118         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_DATA, val);
3119         if (err)
3120                 return err;
3121
3122         return mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
3123 }
3124
3125 static const struct mv88e6xxx_ops mv88e6xxx_g2_smi_phy_ops = {
3126         .read = mv88e6xxx_g2_smi_phy_read,
3127         .write = mv88e6xxx_g2_smi_phy_write,
3128 };
3129
3130 static int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
3131 {
3132         u16 reg;
3133         int err;
3134
3135         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) {
3136                 /* Consider the frames with reserved multicast destination
3137                  * addresses matching 01:80:c2:00:00:2x as MGMT.
3138                  */
3139                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_2X,
3140                                       0xffff);
3141                 if (err)
3142                         return err;
3143         }
3144
3145         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X)) {
3146                 /* Consider the frames with reserved multicast destination
3147                  * addresses matching 01:80:c2:00:00:0x as MGMT.
3148                  */
3149                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X,
3150                                       0xffff);
3151                 if (err)
3152                         return err;
3153         }
3154
3155         /* Ignore removed tag data on doubly tagged packets, disable
3156          * flow control messages, force flow control priority to the
3157          * highest, and send all special multicast frames to the CPU
3158          * port at the highest priority.
3159          */
3160         reg = GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI | (0x7 << 4);
3161         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X) ||
3162             mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X))
3163                 reg |= GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x7;
3164         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, reg);
3165         if (err)
3166                 return err;
3167
3168         /* Program the DSA routing table. */
3169         err = mv88e6xxx_g2_set_device_mapping(chip);
3170         if (err)
3171                 return err;
3172
3173         /* Clear all trunk masks and mapping. */
3174         err = mv88e6xxx_g2_clear_trunk(chip);
3175         if (err)
3176                 return err;
3177
3178         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_IRL)) {
3179                 /* Disable ingress rate limiting by resetting all per port
3180                  * ingress rate limit resources to their initial state.
3181                  */
3182                 err = mv88e6xxx_g2_clear_irl(chip);
3183                         if (err)
3184                                 return err;
3185         }
3186
3187         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_PVT)) {
3188                 /* Initialize Cross-chip Port VLAN Table to reset defaults */
3189                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_PVT_ADDR,
3190                                       GLOBAL2_PVT_ADDR_OP_INIT_ONES);
3191                 if (err)
3192                         return err;
3193         }
3194
3195         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_POT)) {
3196                 /* Clear the priority override table. */
3197                 err = mv88e6xxx_g2_clear_pot(chip);
3198                 if (err)
3199                         return err;
3200         }
3201
3202         return 0;
3203 }
3204
3205 static int mv88e6xxx_setup(struct dsa_switch *ds)
3206 {
3207         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3208         int err;
3209         int i;
3210
3211         chip->ds = ds;
3212         ds->slave_mii_bus = chip->mdio_bus;
3213
3214         mutex_lock(&chip->reg_lock);
3215
3216         err = mv88e6xxx_switch_reset(chip);
3217         if (err)
3218                 goto unlock;
3219
3220         /* Setup Switch Port Registers */
3221         for (i = 0; i < chip->info->num_ports; i++) {
3222                 err = mv88e6xxx_setup_port(chip, i);
3223                 if (err)
3224                         goto unlock;
3225         }
3226
3227         /* Setup Switch Global 1 Registers */
3228         err = mv88e6xxx_g1_setup(chip);
3229         if (err)
3230                 goto unlock;
3231
3232         /* Setup Switch Global 2 Registers */
3233         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
3234                 err = mv88e6xxx_g2_setup(chip);
3235                 if (err)
3236                         goto unlock;
3237         }
3238
3239 unlock:
3240         mutex_unlock(&chip->reg_lock);
3241
3242         return err;
3243 }
3244
3245 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
3246 {
3247         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3248         int err;
3249
3250         mutex_lock(&chip->reg_lock);
3251
3252         /* Has an indirect Switch MAC/WoL/WoF register in Global 2? */
3253         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_SWITCH_MAC))
3254                 err = mv88e6xxx_g2_set_switch_mac(chip, addr);
3255         else
3256                 err = mv88e6xxx_g1_set_switch_mac(chip, addr);
3257
3258         mutex_unlock(&chip->reg_lock);
3259
3260         return err;
3261 }
3262
3263 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3264 {
3265         struct mv88e6xxx_chip *chip = bus->priv;
3266         u16 val;
3267         int err;
3268
3269         if (phy >= chip->info->num_ports)
3270                 return 0xffff;
3271
3272         mutex_lock(&chip->reg_lock);
3273         err = mv88e6xxx_phy_read(chip, phy, reg, &val);
3274         mutex_unlock(&chip->reg_lock);
3275
3276         return err ? err : val;
3277 }
3278
3279 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3280 {
3281         struct mv88e6xxx_chip *chip = bus->priv;
3282         int err;
3283
3284         if (phy >= chip->info->num_ports)
3285                 return 0xffff;
3286
3287         mutex_lock(&chip->reg_lock);
3288         err = mv88e6xxx_phy_write(chip, phy, reg, val);
3289         mutex_unlock(&chip->reg_lock);
3290
3291         return err;
3292 }
3293
3294 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3295                                    struct device_node *np)
3296 {
3297         static int index;
3298         struct mii_bus *bus;
3299         int err;
3300
3301         if (np)
3302                 chip->mdio_np = of_get_child_by_name(np, "mdio");
3303
3304         bus = devm_mdiobus_alloc(chip->dev);
3305         if (!bus)
3306                 return -ENOMEM;
3307
3308         bus->priv = (void *)chip;
3309         if (np) {
3310                 bus->name = np->full_name;
3311                 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
3312         } else {
3313                 bus->name = "mv88e6xxx SMI";
3314                 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3315         }
3316
3317         bus->read = mv88e6xxx_mdio_read;
3318         bus->write = mv88e6xxx_mdio_write;
3319         bus->parent = chip->dev;
3320
3321         if (chip->mdio_np)
3322                 err = of_mdiobus_register(bus, chip->mdio_np);
3323         else
3324                 err = mdiobus_register(bus);
3325         if (err) {
3326                 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3327                 goto out;
3328         }
3329         chip->mdio_bus = bus;
3330
3331         return 0;
3332
3333 out:
3334         if (chip->mdio_np)
3335                 of_node_put(chip->mdio_np);
3336
3337         return err;
3338 }
3339
3340 static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
3341
3342 {
3343         struct mii_bus *bus = chip->mdio_bus;
3344
3345         mdiobus_unregister(bus);
3346
3347         if (chip->mdio_np)
3348                 of_node_put(chip->mdio_np);
3349 }
3350
3351 #ifdef CONFIG_NET_DSA_HWMON
3352
3353 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3354 {
3355         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3356         u16 val;
3357         int ret;
3358
3359         *temp = 0;
3360
3361         mutex_lock(&chip->reg_lock);
3362
3363         ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6);
3364         if (ret < 0)
3365                 goto error;
3366
3367         /* Enable temperature sensor */
3368         ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
3369         if (ret < 0)
3370                 goto error;
3371
3372         ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5));
3373         if (ret < 0)
3374                 goto error;
3375
3376         /* Wait for temperature to stabilize */
3377         usleep_range(10000, 12000);
3378
3379         ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
3380         if (ret < 0)
3381                 goto error;
3382
3383         /* Disable temperature sensor */
3384         ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5));
3385         if (ret < 0)
3386                 goto error;
3387
3388         *temp = ((val & 0x1f) - 5) * 5;
3389
3390 error:
3391         mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0);
3392         mutex_unlock(&chip->reg_lock);
3393         return ret;
3394 }
3395
3396 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3397 {
3398         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3399         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3400         u16 val;
3401         int ret;
3402
3403         *temp = 0;
3404
3405         mutex_lock(&chip->reg_lock);
3406         ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val);
3407         mutex_unlock(&chip->reg_lock);
3408         if (ret < 0)
3409                 return ret;
3410
3411         *temp = (val & 0xff) - 25;
3412
3413         return 0;
3414 }
3415
3416 static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3417 {
3418         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3419
3420         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
3421                 return -EOPNOTSUPP;
3422
3423         if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
3424                 return mv88e63xx_get_temp(ds, temp);
3425
3426         return mv88e61xx_get_temp(ds, temp);
3427 }
3428
3429 static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3430 {
3431         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3432         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3433         u16 val;
3434         int ret;
3435
3436         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3437                 return -EOPNOTSUPP;
3438
3439         *temp = 0;
3440
3441         mutex_lock(&chip->reg_lock);
3442         ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3443         mutex_unlock(&chip->reg_lock);
3444         if (ret < 0)
3445                 return ret;
3446
3447         *temp = (((val >> 8) & 0x1f) * 5) - 25;
3448
3449         return 0;
3450 }
3451
3452 static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3453 {
3454         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3455         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3456         u16 val;
3457         int err;
3458
3459         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3460                 return -EOPNOTSUPP;
3461
3462         mutex_lock(&chip->reg_lock);
3463         err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3464         if (err)
3465                 goto unlock;
3466         temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3467         err = mv88e6xxx_phy_page_write(chip, phy, 6, 26,
3468                                        (val & 0xe0ff) | (temp << 8));
3469 unlock:
3470         mutex_unlock(&chip->reg_lock);
3471
3472         return err;
3473 }
3474
3475 static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3476 {
3477         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3478         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3479         u16 val;
3480         int ret;
3481
3482         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3483                 return -EOPNOTSUPP;
3484
3485         *alarm = false;
3486
3487         mutex_lock(&chip->reg_lock);
3488         ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3489         mutex_unlock(&chip->reg_lock);
3490         if (ret < 0)
3491                 return ret;
3492
3493         *alarm = !!(val & 0x40);
3494
3495         return 0;
3496 }
3497 #endif /* CONFIG_NET_DSA_HWMON */
3498
3499 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3500 {
3501         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3502
3503         return chip->eeprom_len;
3504 }
3505
3506 static int mv88e6xxx_get_eeprom16(struct mv88e6xxx_chip *chip,
3507                                   struct ethtool_eeprom *eeprom, u8 *data)
3508 {
3509         unsigned int offset = eeprom->offset;
3510         unsigned int len = eeprom->len;
3511         u16 val;
3512         int err;
3513
3514         eeprom->len = 0;
3515
3516         if (offset & 1) {
3517                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3518                 if (err)
3519                         return err;
3520
3521                 *data++ = (val >> 8) & 0xff;
3522
3523                 offset++;
3524                 len--;
3525                 eeprom->len++;
3526         }
3527
3528         while (len >= 2) {
3529                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3530                 if (err)
3531                         return err;
3532
3533                 *data++ = val & 0xff;
3534                 *data++ = (val >> 8) & 0xff;
3535
3536                 offset += 2;
3537                 len -= 2;
3538                 eeprom->len += 2;
3539         }
3540
3541         if (len) {
3542                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3543                 if (err)
3544                         return err;
3545
3546                 *data++ = val & 0xff;
3547
3548                 offset++;
3549                 len--;
3550                 eeprom->len++;
3551         }
3552
3553         return 0;
3554 }
3555
3556 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3557                                 struct ethtool_eeprom *eeprom, u8 *data)
3558 {
3559         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3560         int err;
3561
3562         mutex_lock(&chip->reg_lock);
3563
3564         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3565                 err = mv88e6xxx_get_eeprom16(chip, eeprom, data);
3566         else
3567                 err = -EOPNOTSUPP;
3568
3569         mutex_unlock(&chip->reg_lock);
3570
3571         if (err)
3572                 return err;
3573
3574         eeprom->magic = 0xc3ec4951;
3575
3576         return 0;
3577 }
3578
3579 static int mv88e6xxx_set_eeprom16(struct mv88e6xxx_chip *chip,
3580                                   struct ethtool_eeprom *eeprom, u8 *data)
3581 {
3582         unsigned int offset = eeprom->offset;
3583         unsigned int len = eeprom->len;
3584         u16 val;
3585         int err;
3586
3587         /* Ensure the RO WriteEn bit is set */
3588         err = mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, &val);
3589         if (err)
3590                 return err;
3591
3592         if (!(val & GLOBAL2_EEPROM_CMD_WRITE_EN))
3593                 return -EROFS;
3594
3595         eeprom->len = 0;
3596
3597         if (offset & 1) {
3598                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3599                 if (err)
3600                         return err;
3601
3602                 val = (*data++ << 8) | (val & 0xff);
3603
3604                 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3605                 if (err)
3606                         return err;
3607
3608                 offset++;
3609                 len--;
3610                 eeprom->len++;
3611         }
3612
3613         while (len >= 2) {
3614                 val = *data++;
3615                 val |= *data++ << 8;
3616
3617                 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3618                 if (err)
3619                         return err;
3620
3621                 offset += 2;
3622                 len -= 2;
3623                 eeprom->len += 2;
3624         }
3625
3626         if (len) {
3627                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3628                 if (err)
3629                         return err;
3630
3631                 val = (val & 0xff00) | *data++;
3632
3633                 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3634                 if (err)
3635                         return err;
3636
3637                 offset++;
3638                 len--;
3639                 eeprom->len++;
3640         }
3641
3642         return 0;
3643 }
3644
3645 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3646                                 struct ethtool_eeprom *eeprom, u8 *data)
3647 {
3648         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3649         int err;
3650
3651         if (eeprom->magic != 0xc3ec4951)
3652                 return -EINVAL;
3653
3654         mutex_lock(&chip->reg_lock);
3655
3656         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3657                 err = mv88e6xxx_set_eeprom16(chip, eeprom, data);
3658         else
3659                 err = -EOPNOTSUPP;
3660
3661         mutex_unlock(&chip->reg_lock);
3662
3663         return err;
3664 }
3665
3666 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3667         [MV88E6085] = {
3668                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3669                 .family = MV88E6XXX_FAMILY_6097,
3670                 .name = "Marvell 88E6085",
3671                 .num_databases = 4096,
3672                 .num_ports = 10,
3673                 .port_base_addr = 0x10,
3674                 .age_time_coeff = 15000,
3675                 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3676         },
3677
3678         [MV88E6095] = {
3679                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3680                 .family = MV88E6XXX_FAMILY_6095,
3681                 .name = "Marvell 88E6095/88E6095F",
3682                 .num_databases = 256,
3683                 .num_ports = 11,
3684                 .port_base_addr = 0x10,
3685                 .age_time_coeff = 15000,
3686                 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3687         },
3688
3689         [MV88E6123] = {
3690                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3691                 .family = MV88E6XXX_FAMILY_6165,
3692                 .name = "Marvell 88E6123",
3693                 .num_databases = 4096,
3694                 .num_ports = 3,
3695                 .port_base_addr = 0x10,
3696                 .age_time_coeff = 15000,
3697                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3698         },
3699
3700         [MV88E6131] = {
3701                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3702                 .family = MV88E6XXX_FAMILY_6185,
3703                 .name = "Marvell 88E6131",
3704                 .num_databases = 256,
3705                 .num_ports = 8,
3706                 .port_base_addr = 0x10,
3707                 .age_time_coeff = 15000,
3708                 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3709         },
3710
3711         [MV88E6161] = {
3712                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3713                 .family = MV88E6XXX_FAMILY_6165,
3714                 .name = "Marvell 88E6161",
3715                 .num_databases = 4096,
3716                 .num_ports = 6,
3717                 .port_base_addr = 0x10,
3718                 .age_time_coeff = 15000,
3719                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3720         },
3721
3722         [MV88E6165] = {
3723                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3724                 .family = MV88E6XXX_FAMILY_6165,
3725                 .name = "Marvell 88E6165",
3726                 .num_databases = 4096,
3727                 .num_ports = 6,
3728                 .port_base_addr = 0x10,
3729                 .age_time_coeff = 15000,
3730                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3731         },
3732
3733         [MV88E6171] = {
3734                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3735                 .family = MV88E6XXX_FAMILY_6351,
3736                 .name = "Marvell 88E6171",
3737                 .num_databases = 4096,
3738                 .num_ports = 7,
3739                 .port_base_addr = 0x10,
3740                 .age_time_coeff = 15000,
3741                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3742         },
3743
3744         [MV88E6172] = {
3745                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3746                 .family = MV88E6XXX_FAMILY_6352,
3747                 .name = "Marvell 88E6172",
3748                 .num_databases = 4096,
3749                 .num_ports = 7,
3750                 .port_base_addr = 0x10,
3751                 .age_time_coeff = 15000,
3752                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3753         },
3754
3755         [MV88E6175] = {
3756                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3757                 .family = MV88E6XXX_FAMILY_6351,
3758                 .name = "Marvell 88E6175",
3759                 .num_databases = 4096,
3760                 .num_ports = 7,
3761                 .port_base_addr = 0x10,
3762                 .age_time_coeff = 15000,
3763                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3764         },
3765
3766         [MV88E6176] = {
3767                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3768                 .family = MV88E6XXX_FAMILY_6352,
3769                 .name = "Marvell 88E6176",
3770                 .num_databases = 4096,
3771                 .num_ports = 7,
3772                 .port_base_addr = 0x10,
3773                 .age_time_coeff = 15000,
3774                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3775         },
3776
3777         [MV88E6185] = {
3778                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3779                 .family = MV88E6XXX_FAMILY_6185,
3780                 .name = "Marvell 88E6185",
3781                 .num_databases = 256,
3782                 .num_ports = 10,
3783                 .port_base_addr = 0x10,
3784                 .age_time_coeff = 15000,
3785                 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3786         },
3787
3788         [MV88E6240] = {
3789                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3790                 .family = MV88E6XXX_FAMILY_6352,
3791                 .name = "Marvell 88E6240",
3792                 .num_databases = 4096,
3793                 .num_ports = 7,
3794                 .port_base_addr = 0x10,
3795                 .age_time_coeff = 15000,
3796                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3797         },
3798
3799         [MV88E6320] = {
3800                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3801                 .family = MV88E6XXX_FAMILY_6320,
3802                 .name = "Marvell 88E6320",
3803                 .num_databases = 4096,
3804                 .num_ports = 7,
3805                 .port_base_addr = 0x10,
3806                 .age_time_coeff = 15000,
3807                 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3808         },
3809
3810         [MV88E6321] = {
3811                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3812                 .family = MV88E6XXX_FAMILY_6320,
3813                 .name = "Marvell 88E6321",
3814                 .num_databases = 4096,
3815                 .num_ports = 7,
3816                 .port_base_addr = 0x10,
3817                 .age_time_coeff = 15000,
3818                 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3819         },
3820
3821         [MV88E6350] = {
3822                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3823                 .family = MV88E6XXX_FAMILY_6351,
3824                 .name = "Marvell 88E6350",
3825                 .num_databases = 4096,
3826                 .num_ports = 7,
3827                 .port_base_addr = 0x10,
3828                 .age_time_coeff = 15000,
3829                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3830         },
3831
3832         [MV88E6351] = {
3833                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3834                 .family = MV88E6XXX_FAMILY_6351,
3835                 .name = "Marvell 88E6351",
3836                 .num_databases = 4096,
3837                 .num_ports = 7,
3838                 .port_base_addr = 0x10,
3839                 .age_time_coeff = 15000,
3840                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3841         },
3842
3843         [MV88E6352] = {
3844                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3845                 .family = MV88E6XXX_FAMILY_6352,
3846                 .name = "Marvell 88E6352",
3847                 .num_databases = 4096,
3848                 .num_ports = 7,
3849                 .port_base_addr = 0x10,
3850                 .age_time_coeff = 15000,
3851                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3852         },
3853 };
3854
3855 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3856 {
3857         int i;
3858
3859         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3860                 if (mv88e6xxx_table[i].prod_num == prod_num)
3861                         return &mv88e6xxx_table[i];
3862
3863         return NULL;
3864 }
3865
3866 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3867 {
3868         const struct mv88e6xxx_info *info;
3869         unsigned int prod_num, rev;
3870         u16 id;
3871         int err;
3872
3873         mutex_lock(&chip->reg_lock);
3874         err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
3875         mutex_unlock(&chip->reg_lock);
3876         if (err)
3877                 return err;
3878
3879         prod_num = (id & 0xfff0) >> 4;
3880         rev = id & 0x000f;
3881
3882         info = mv88e6xxx_lookup_info(prod_num);
3883         if (!info)
3884                 return -ENODEV;
3885
3886         /* Update the compatible info with the probed one */
3887         chip->info = info;
3888
3889         dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3890                  chip->info->prod_num, chip->info->name, rev);
3891
3892         return 0;
3893 }
3894
3895 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3896 {
3897         struct mv88e6xxx_chip *chip;
3898
3899         chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3900         if (!chip)
3901                 return NULL;
3902
3903         chip->dev = dev;
3904
3905         mutex_init(&chip->reg_lock);
3906
3907         return chip;
3908 }
3909
3910 static const struct mv88e6xxx_ops mv88e6xxx_phy_ops = {
3911         .read = mv88e6xxx_read,
3912         .write = mv88e6xxx_write,
3913 };
3914
3915 static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
3916 {
3917         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SMI_PHY)) {
3918                 chip->phy_ops = &mv88e6xxx_g2_smi_phy_ops;
3919         } else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) {
3920                 chip->phy_ops = &mv88e6xxx_phy_ppu_ops;
3921                 mv88e6xxx_ppu_state_init(chip);
3922         } else {
3923                 chip->phy_ops = &mv88e6xxx_phy_ops;
3924         }
3925 }
3926
3927 static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
3928 {
3929         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) {
3930                 mv88e6xxx_ppu_state_destroy(chip);
3931         }
3932 }
3933
3934 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
3935                               struct mii_bus *bus, int sw_addr)
3936 {
3937         /* ADDR[0] pin is unavailable externally and considered zero */
3938         if (sw_addr & 0x1)
3939                 return -EINVAL;
3940
3941         if (sw_addr == 0)
3942                 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3943         else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
3944                 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
3945         else
3946                 return -EINVAL;
3947
3948         chip->bus = bus;
3949         chip->sw_addr = sw_addr;
3950
3951         return 0;
3952 }
3953
3954 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
3955 {
3956         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3957
3958         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
3959                 return DSA_TAG_PROTO_EDSA;
3960
3961         return DSA_TAG_PROTO_DSA;
3962 }
3963
3964 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3965                                        struct device *host_dev, int sw_addr,
3966                                        void **priv)
3967 {
3968         struct mv88e6xxx_chip *chip;
3969         struct mii_bus *bus;
3970         int err;
3971
3972         bus = dsa_host_dev_to_mii_bus(host_dev);
3973         if (!bus)
3974                 return NULL;
3975
3976         chip = mv88e6xxx_alloc_chip(dsa_dev);
3977         if (!chip)
3978                 return NULL;
3979
3980         /* Legacy SMI probing will only support chips similar to 88E6085 */
3981         chip->info = &mv88e6xxx_table[MV88E6085];
3982
3983         err = mv88e6xxx_smi_init(chip, bus, sw_addr);
3984         if (err)
3985                 goto free;
3986
3987         err = mv88e6xxx_detect(chip);
3988         if (err)
3989                 goto free;
3990
3991         mv88e6xxx_phy_init(chip);
3992
3993         err = mv88e6xxx_mdio_register(chip, NULL);
3994         if (err)
3995                 goto free;
3996
3997         *priv = chip;
3998
3999         return chip->info->name;
4000 free:
4001         devm_kfree(dsa_dev, chip);
4002
4003         return NULL;
4004 }
4005
4006 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4007                                       const struct switchdev_obj_port_mdb *mdb,
4008                                       struct switchdev_trans *trans)
4009 {
4010         /* We don't need any dynamic resource from the kernel (yet),
4011          * so skip the prepare phase.
4012          */
4013
4014         return 0;
4015 }
4016
4017 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4018                                    const struct switchdev_obj_port_mdb *mdb,
4019                                    struct switchdev_trans *trans)
4020 {
4021         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
4022
4023         mutex_lock(&chip->reg_lock);
4024         if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4025                                          GLOBAL_ATU_DATA_STATE_MC_STATIC))
4026                 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
4027         mutex_unlock(&chip->reg_lock);
4028 }
4029
4030 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
4031                                   const struct switchdev_obj_port_mdb *mdb)
4032 {
4033         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
4034         int err;
4035
4036         mutex_lock(&chip->reg_lock);
4037         err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4038                                            GLOBAL_ATU_DATA_STATE_UNUSED);
4039         mutex_unlock(&chip->reg_lock);
4040
4041         return err;
4042 }
4043
4044 static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
4045                                    struct switchdev_obj_port_mdb *mdb,
4046                                    int (*cb)(struct switchdev_obj *obj))
4047 {
4048         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
4049         int err;
4050
4051         mutex_lock(&chip->reg_lock);
4052         err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
4053         mutex_unlock(&chip->reg_lock);
4054
4055         return err;
4056 }
4057
4058 static struct dsa_switch_ops mv88e6xxx_switch_ops = {
4059         .probe                  = mv88e6xxx_drv_probe,
4060         .get_tag_protocol       = mv88e6xxx_get_tag_protocol,
4061         .setup                  = mv88e6xxx_setup,
4062         .set_addr               = mv88e6xxx_set_addr,
4063         .adjust_link            = mv88e6xxx_adjust_link,
4064         .get_strings            = mv88e6xxx_get_strings,
4065         .get_ethtool_stats      = mv88e6xxx_get_ethtool_stats,
4066         .get_sset_count         = mv88e6xxx_get_sset_count,
4067         .set_eee                = mv88e6xxx_set_eee,
4068         .get_eee                = mv88e6xxx_get_eee,
4069 #ifdef CONFIG_NET_DSA_HWMON
4070         .get_temp               = mv88e6xxx_get_temp,
4071         .get_temp_limit         = mv88e6xxx_get_temp_limit,
4072         .set_temp_limit         = mv88e6xxx_set_temp_limit,
4073         .get_temp_alarm         = mv88e6xxx_get_temp_alarm,
4074 #endif
4075         .get_eeprom_len         = mv88e6xxx_get_eeprom_len,
4076         .get_eeprom             = mv88e6xxx_get_eeprom,
4077         .set_eeprom             = mv88e6xxx_set_eeprom,
4078         .get_regs_len           = mv88e6xxx_get_regs_len,
4079         .get_regs               = mv88e6xxx_get_regs,
4080         .set_ageing_time        = mv88e6xxx_set_ageing_time,
4081         .port_bridge_join       = mv88e6xxx_port_bridge_join,
4082         .port_bridge_leave      = mv88e6xxx_port_bridge_leave,
4083         .port_stp_state_set     = mv88e6xxx_port_stp_state_set,
4084         .port_vlan_filtering    = mv88e6xxx_port_vlan_filtering,
4085         .port_vlan_prepare      = mv88e6xxx_port_vlan_prepare,
4086         .port_vlan_add          = mv88e6xxx_port_vlan_add,
4087         .port_vlan_del          = mv88e6xxx_port_vlan_del,
4088         .port_vlan_dump         = mv88e6xxx_port_vlan_dump,
4089         .port_fdb_prepare       = mv88e6xxx_port_fdb_prepare,
4090         .port_fdb_add           = mv88e6xxx_port_fdb_add,
4091         .port_fdb_del           = mv88e6xxx_port_fdb_del,
4092         .port_fdb_dump          = mv88e6xxx_port_fdb_dump,
4093         .port_mdb_prepare       = mv88e6xxx_port_mdb_prepare,
4094         .port_mdb_add           = mv88e6xxx_port_mdb_add,
4095         .port_mdb_del           = mv88e6xxx_port_mdb_del,
4096         .port_mdb_dump          = mv88e6xxx_port_mdb_dump,
4097 };
4098
4099 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
4100                                      struct device_node *np)
4101 {
4102         struct device *dev = chip->dev;
4103         struct dsa_switch *ds;
4104
4105         ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
4106         if (!ds)
4107                 return -ENOMEM;
4108
4109         ds->dev = dev;
4110         ds->priv = chip;
4111         ds->ops = &mv88e6xxx_switch_ops;
4112
4113         dev_set_drvdata(dev, ds);
4114
4115         return dsa_register_switch(ds, np);
4116 }
4117
4118 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
4119 {
4120         dsa_unregister_switch(chip->ds);
4121 }
4122
4123 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4124 {
4125         struct device *dev = &mdiodev->dev;
4126         struct device_node *np = dev->of_node;
4127         const struct mv88e6xxx_info *compat_info;
4128         struct mv88e6xxx_chip *chip;
4129         u32 eeprom_len;
4130         int err;
4131
4132         compat_info = of_device_get_match_data(dev);
4133         if (!compat_info)
4134                 return -EINVAL;
4135
4136         chip = mv88e6xxx_alloc_chip(dev);
4137         if (!chip)
4138                 return -ENOMEM;
4139
4140         chip->info = compat_info;
4141
4142         err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4143         if (err)
4144                 return err;
4145
4146         err = mv88e6xxx_detect(chip);
4147         if (err)
4148                 return err;
4149
4150         mv88e6xxx_phy_init(chip);
4151
4152         chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
4153         if (IS_ERR(chip->reset))
4154                 return PTR_ERR(chip->reset);
4155
4156         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16) &&
4157             !of_property_read_u32(np, "eeprom-length", &eeprom_len))
4158                 chip->eeprom_len = eeprom_len;
4159
4160         err = mv88e6xxx_mdio_register(chip, np);
4161         if (err)
4162                 return err;
4163
4164         err = mv88e6xxx_register_switch(chip, np);
4165         if (err) {
4166                 mv88e6xxx_mdio_unregister(chip);
4167                 return err;
4168         }
4169
4170         return 0;
4171 }
4172
4173 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4174 {
4175         struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
4176         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
4177
4178         mv88e6xxx_phy_destroy(chip);
4179         mv88e6xxx_unregister_switch(chip);
4180         mv88e6xxx_mdio_unregister(chip);
4181 }
4182
4183 static const struct of_device_id mv88e6xxx_of_match[] = {
4184         {
4185                 .compatible = "marvell,mv88e6085",
4186                 .data = &mv88e6xxx_table[MV88E6085],
4187         },
4188         { /* sentinel */ },
4189 };
4190
4191 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4192
4193 static struct mdio_driver mv88e6xxx_driver = {
4194         .probe  = mv88e6xxx_probe,
4195         .remove = mv88e6xxx_remove,
4196         .mdiodrv.driver = {
4197                 .name = "mv88e6085",
4198                 .of_match_table = mv88e6xxx_of_match,
4199         },
4200 };
4201
4202 static int __init mv88e6xxx_init(void)
4203 {
4204         register_switch_driver(&mv88e6xxx_switch_ops);
4205         return mdio_driver_register(&mv88e6xxx_driver);
4206 }
4207 module_init(mv88e6xxx_init);
4208
4209 static void __exit mv88e6xxx_cleanup(void)
4210 {
4211         mdio_driver_unregister(&mv88e6xxx_driver);
4212         unregister_switch_driver(&mv88e6xxx_switch_ops);
4213 }
4214 module_exit(mv88e6xxx_cleanup);
4215
4216 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4217 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4218 MODULE_LICENSE("GPL");