2 * Marvell 88E6xxx Switch Global 2 Registers support (device address 0x1C)
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2016 Vivien Didelot <vivien.didelot@savoirfairelinux.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include "mv88e6xxx.h"
17 /* Offset 0x06: Device Mapping Table register */
19 static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
22 u16 val = (target << 8) | (port & 0xf);
24 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING, val);
27 static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip *chip)
32 /* Initialize the routing port to the 32 possible target devices */
33 for (target = 0; target < 32; ++target) {
36 if (target < DSA_MAX_SWITCHES) {
37 port = chip->ds->rtable[target];
38 if (port == DSA_RTABLE_NONE)
42 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
50 /* Offset 0x07: Trunk Mask Table register */
52 static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
55 const u16 port_mask = BIT(chip->info->num_ports) - 1;
56 u16 val = (num << 12) | (mask & port_mask);
59 val |= GLOBAL2_TRUNK_MASK_HASK;
61 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MASK, val);
64 /* Offset 0x08: Trunk Mapping Table register */
66 static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
69 const u16 port_mask = BIT(chip->info->num_ports) - 1;
70 u16 val = (id << 11) | (map & port_mask);
72 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING, val);
75 static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip)
77 const u16 port_mask = BIT(chip->info->num_ports) - 1;
80 /* Clear all eight possible Trunk Mask vectors */
81 for (i = 0; i < 8; ++i) {
82 err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask);
87 /* Clear all sixteen possible Trunk ID routing vectors */
88 for (i = 0; i < 16; ++i) {
89 err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0);
97 /* Offset 0x09: Ingress Rate Command register
98 * Offset 0x0A: Ingress Rate Data register
101 static int mv88e6xxx_g2_clear_irl(struct mv88e6xxx_chip *chip)
105 /* Init all Ingress Rate Limit resources of all ports */
106 for (port = 0; port < chip->info->num_ports; ++port) {
107 /* XXX newer chips (like 88E6390) have different 2-bit ops */
108 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
109 GLOBAL2_IRL_CMD_OP_INIT_ALL |
114 /* Wait for the operation to complete */
115 err = mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
116 GLOBAL2_IRL_CMD_BUSY);
124 /* Offset 0x0D: Switch MAC/WoL/WoF register */
126 static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
127 unsigned int pointer, u8 data)
129 u16 val = (pointer << 8) | data;
131 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MAC, val);
134 int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
138 for (i = 0; i < 6; i++) {
139 err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]);
147 /* Offset 0x0F: Priority Override Table */
149 static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer,
152 u16 val = (pointer << 8) | (data & 0x7);
154 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE, val);
157 static int mv88e6xxx_g2_clear_pot(struct mv88e6xxx_chip *chip)
161 /* Clear all sixteen possible Priority Override entries */
162 for (i = 0; i < 16; i++) {
163 err = mv88e6xxx_g2_pot_write(chip, i, 0);
171 /* Offset 0x14: EEPROM Command
172 * Offset 0x15: EEPROM Data
175 static int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip)
177 return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD,
178 GLOBAL2_EEPROM_CMD_BUSY |
179 GLOBAL2_EEPROM_CMD_RUNNING);
182 static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
186 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, cmd);
190 return mv88e6xxx_g2_eeprom_wait(chip);
193 static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip,
196 u16 cmd = GLOBAL2_EEPROM_CMD_OP_READ | addr;
199 err = mv88e6xxx_g2_eeprom_wait(chip);
203 err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
207 return mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
210 static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip,
213 u16 cmd = GLOBAL2_EEPROM_CMD_OP_WRITE | addr;
216 err = mv88e6xxx_g2_eeprom_wait(chip);
220 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
224 return mv88e6xxx_g2_eeprom_cmd(chip, cmd);
227 int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip,
228 struct ethtool_eeprom *eeprom, u8 *data)
230 unsigned int offset = eeprom->offset;
231 unsigned int len = eeprom->len;
238 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
242 *data++ = (val >> 8) & 0xff;
250 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
254 *data++ = val & 0xff;
255 *data++ = (val >> 8) & 0xff;
263 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
267 *data++ = val & 0xff;
277 int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
278 struct ethtool_eeprom *eeprom, u8 *data)
280 unsigned int offset = eeprom->offset;
281 unsigned int len = eeprom->len;
285 /* Ensure the RO WriteEn bit is set */
286 err = mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, &val);
290 if (!(val & GLOBAL2_EEPROM_CMD_WRITE_EN))
296 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
300 val = (*data++ << 8) | (val & 0xff);
302 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
315 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
325 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
329 val = (val & 0xff00) | *data++;
331 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
343 /* Offset 0x18: SMI PHY Command Register
344 * Offset 0x19: SMI PHY Data Register
347 static int mv88e6xxx_g2_smi_phy_wait(struct mv88e6xxx_chip *chip)
349 return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_CMD,
350 GLOBAL2_SMI_PHY_CMD_BUSY);
353 static int mv88e6xxx_g2_smi_phy_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
357 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_CMD, cmd);
361 return mv88e6xxx_g2_smi_phy_wait(chip);
364 int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, int addr, int reg,
367 u16 cmd = GLOBAL2_SMI_PHY_CMD_OP_22_READ_DATA | (addr << 5) | reg;
370 err = mv88e6xxx_g2_smi_phy_wait(chip);
374 err = mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
378 return mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_DATA, val);
381 int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, int addr, int reg,
384 u16 cmd = GLOBAL2_SMI_PHY_CMD_OP_22_WRITE_DATA | (addr << 5) | reg;
387 err = mv88e6xxx_g2_smi_phy_wait(chip);
391 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_DATA, val);
395 return mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
398 int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
403 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) {
404 /* Consider the frames with reserved multicast destination
405 * addresses matching 01:80:c2:00:00:2x as MGMT.
407 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_2X,
413 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X)) {
414 /* Consider the frames with reserved multicast destination
415 * addresses matching 01:80:c2:00:00:0x as MGMT.
417 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X,
423 /* Ignore removed tag data on doubly tagged packets, disable
424 * flow control messages, force flow control priority to the
425 * highest, and send all special multicast frames to the CPU
426 * port at the highest priority.
428 reg = GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI | (0x7 << 4);
429 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X) ||
430 mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X))
431 reg |= GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x7;
432 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, reg);
436 /* Program the DSA routing table. */
437 err = mv88e6xxx_g2_set_device_mapping(chip);
441 /* Clear all trunk masks and mapping. */
442 err = mv88e6xxx_g2_clear_trunk(chip);
446 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_IRL)) {
447 /* Disable ingress rate limiting by resetting all per port
448 * ingress rate limit resources to their initial state.
450 err = mv88e6xxx_g2_clear_irl(chip);
455 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_PVT)) {
456 /* Initialize Cross-chip Port VLAN Table to reset defaults */
457 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_PVT_ADDR,
458 GLOBAL2_PVT_ADDR_OP_INIT_ONES);
463 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_POT)) {
464 /* Clear the priority override table. */
465 err = mv88e6xxx_g2_clear_pot(chip);