drivers/net/ethernet/broadcom/bcm63xx_enet.c

   1 /*
   2  * Driver for BCM963xx builtin Ethernet mac
   3  *
   4  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/module.h>
  23 #include <linux/clk.h>
  24 #include <linux/etherdevice.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/ethtool.h>
  28 #include <linux/crc32.h>
  29 #include <linux/err.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/if_vlan.h>
  33
  34 #include <bcm63xx_dev_enet.h>
  35 #include "bcm63xx_enet.h"
  36
  37 static char bcm_enet_driver_name[] = "bcm63xx_enet";
  38 static char bcm_enet_driver_version[] = "1.0";
  39
  40 static int copybreak __read_mostly = 128;
  41 module_param(copybreak, int, 0);
  42 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
  43
  44 /* io registers memory shared between all devices */
  45 static void __iomem *bcm_enet_shared_base[3];
  46
  47 /*
  48  * io helpers to access mac registers
  49  */
  50 static inline u32 enet_readl(struct bcm_enet_priv *priv, u32 off)
  51 {
  52         return bcm_readl(priv->base + off);
  53 }
  54
  55 static inline void enet_writel(struct bcm_enet_priv *priv,
  56                                u32 val, u32 off)
  57 {
  58         bcm_writel(val, priv->base + off);
  59 }
  60
  61 /*
  62  * io helpers to access switch registers
  63  */
  64 static inline u32 enetsw_readl(struct bcm_enet_priv *priv, u32 off)
  65 {
  66         return bcm_readl(priv->base + off);
  67 }
  68
  69 static inline void enetsw_writel(struct bcm_enet_priv *priv,
  70                                  u32 val, u32 off)
  71 {
  72         bcm_writel(val, priv->base + off);
  73 }
  74
  75 static inline u16 enetsw_readw(struct bcm_enet_priv *priv, u32 off)
  76 {
  77         return bcm_readw(priv->base + off);
  78 }
  79
  80 static inline void enetsw_writew(struct bcm_enet_priv *priv,
  81                                  u16 val, u32 off)
  82 {
  83         bcm_writew(val, priv->base + off);
  84 }
  85
  86 static inline u8 enetsw_readb(struct bcm_enet_priv *priv, u32 off)
  87 {
  88         return bcm_readb(priv->base + off);
  89 }
  90
  91 static inline void enetsw_writeb(struct bcm_enet_priv *priv,
  92                                  u8 val, u32 off)
  93 {
  94         bcm_writeb(val, priv->base + off);
  95 }
  96
  97
  98 /* io helpers to access shared registers */
  99 static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
 100 {
 101         return bcm_readl(bcm_enet_shared_base[0] + off);
 102 }
 103
 104 static inline void enet_dma_writel(struct bcm_enet_priv *priv,
 105                                        u32 val, u32 off)
 106 {
 107         bcm_writel(val, bcm_enet_shared_base[0] + off);
 108 }
 109
 110 static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off, int chan)
 111 {
 112         return bcm_readl(bcm_enet_shared_base[1] +
 113                 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
 114 }
 115
 116 static inline void enet_dmac_writel(struct bcm_enet_priv *priv,
 117                                        u32 val, u32 off, int chan)
 118 {
 119         bcm_writel(val, bcm_enet_shared_base[1] +
 120                 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
 121 }
 122
 123 static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off, int chan)
 124 {
 125         return bcm_readl(bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
 126 }
 127
 128 static inline void enet_dmas_writel(struct bcm_enet_priv *priv,
 129                                        u32 val, u32 off, int chan)
 130 {
 131         bcm_writel(val, bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
 132 }
 133
 134 /*
 135  * write given data into mii register and wait for transfer to end
 136  * with timeout (average measured transfer time is 25us)
 137  */
 138 static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data)
 139 {
 140         int limit;
 141
 142         /* make sure mii interrupt status is cleared */
 143         enet_writel(priv, ENET_IR_MII, ENET_IR_REG);
 144
 145         enet_writel(priv, data, ENET_MIIDATA_REG);
 146         wmb();
 147
 148         /* busy wait on mii interrupt bit, with timeout */
 149         limit = 1000;
 150         do {
 151                 if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII)
 152                         break;
 153                 udelay(1);
 154         } while (limit-- > 0);
 155
 156         return (limit < 0) ? 1 : 0;
 157 }
 158
 159 /*
 160  * MII internal read callback
 161  */
 162 static int bcm_enet_mdio_read(struct bcm_enet_priv *priv, int mii_id,
 163                               int regnum)
 164 {
 165         u32 tmp, val;
 166
 167         tmp = regnum << ENET_MIIDATA_REG_SHIFT;
 168         tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
 169         tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
 170         tmp |= ENET_MIIDATA_OP_READ_MASK;
 171
 172         if (do_mdio_op(priv, tmp))
 173                 return -1;
 174
 175         val = enet_readl(priv, ENET_MIIDATA_REG);
 176         val &= 0xffff;
 177         return val;
 178 }
 179
 180 /*
 181  * MII internal write callback
 182  */
 183 static int bcm_enet_mdio_write(struct bcm_enet_priv *priv, int mii_id,
 184                                int regnum, u16 value)
 185 {
 186         u32 tmp;
 187
 188         tmp = (value & 0xffff) << ENET_MIIDATA_DATA_SHIFT;
 189         tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
 190         tmp |= regnum << ENET_MIIDATA_REG_SHIFT;
 191         tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
 192         tmp |= ENET_MIIDATA_OP_WRITE_MASK;
 193
 194         (void)do_mdio_op(priv, tmp);
 195         return 0;
 196 }
 197
 198 /*
 199  * MII read callback from phylib
 200  */
 201 static int bcm_enet_mdio_read_phylib(struct mii_bus *bus, int mii_id,
 202                                      int regnum)
 203 {
 204         return bcm_enet_mdio_read(bus->priv, mii_id, regnum);
 205 }
 206
 207 /*
 208  * MII write callback from phylib
 209  */
 210 static int bcm_enet_mdio_write_phylib(struct mii_bus *bus, int mii_id,
 211                                       int regnum, u16 value)
 212 {
 213         return bcm_enet_mdio_write(bus->priv, mii_id, regnum, value);
 214 }
 215
 216 /*
 217  * MII read callback from mii core
 218  */
 219 static int bcm_enet_mdio_read_mii(struct net_device *dev, int mii_id,
 220                                   int regnum)
 221 {
 222         return bcm_enet_mdio_read(netdev_priv(dev), mii_id, regnum);
 223 }
 224
 225 /*
 226  * MII write callback from mii core
 227  */
 228 static void bcm_enet_mdio_write_mii(struct net_device *dev, int mii_id,
 229                                     int regnum, int value)
 230 {
 231         bcm_enet_mdio_write(netdev_priv(dev), mii_id, regnum, value);
 232 }
 233
 234 /*
 235  * refill rx queue
 236  */
 237 static int bcm_enet_refill_rx(struct net_device *dev)
 238 {
 239         struct bcm_enet_priv *priv;
 240
 241         priv = netdev_priv(dev);
 242
 243         while (priv->rx_desc_count < priv->rx_ring_size) {
 244                 struct bcm_enet_desc *desc;
 245                 struct sk_buff *skb;
 246                 dma_addr_t p;
 247                 int desc_idx;
 248                 u32 len_stat;
 249
 250                 desc_idx = priv->rx_dirty_desc;
 251                 desc = &priv->rx_desc_cpu[desc_idx];
 252
 253                 if (!priv->rx_skb[desc_idx]) {
 254                         skb = netdev_alloc_skb(dev, priv->rx_skb_size);
 255                         if (!skb)
 256                                 break;
 257                         priv->rx_skb[desc_idx] = skb;
 258                         p = dma_map_single(&priv->pdev->dev, skb->data,
 259                                            priv->rx_skb_size,
 260                                            DMA_FROM_DEVICE);
 261                         desc->address = p;
 262                 }
 263
 264                 len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
 265                 len_stat |= DMADESC_OWNER_MASK;
 266                 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
 267                         len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
 268                         priv->rx_dirty_desc = 0;
 269                 } else {
 270                         priv->rx_dirty_desc++;
 271                 }
 272                 wmb();
 273                 desc->len_stat = len_stat;
 274
 275                 priv->rx_desc_count++;
 276
 277                 /* tell dma engine we allocated one buffer */
 278                 if (priv->dma_has_sram)
 279                         enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
 280                 else
 281                         enet_dmac_writel(priv, 1, ENETDMAC_BUFALLOC, priv->rx_chan);
 282         }
 283
 284         /* If rx ring is still empty, set a timer to try allocating
 285          * again at a later time. */
 286         if (priv->rx_desc_count == 0 && netif_running(dev)) {
 287                 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n");
 288                 priv->rx_timeout.expires = jiffies + HZ;
 289                 add_timer(&priv->rx_timeout);
 290         }
 291
 292         return 0;
 293 }
 294
 295 /*
 296  * timer callback to defer refill rx queue in case we're OOM
 297  */
 298 static void bcm_enet_refill_rx_timer(unsigned long data)
 299 {
 300         struct net_device *dev;
 301         struct bcm_enet_priv *priv;
 302
 303         dev = (struct net_device *)data;
 304         priv = netdev_priv(dev);
 305
 306         spin_lock(&priv->rx_lock);
 307         bcm_enet_refill_rx((struct net_device *)data);
 308         spin_unlock(&priv->rx_lock);
 309 }
 310
 311 /*
 312  * extract packet from rx queue
 313  */
 314 static int bcm_enet_receive_queue(struct net_device *dev, int budget)
 315 {
 316         struct bcm_enet_priv *priv;
 317         struct device *kdev;
 318         int processed;
 319
 320         priv = netdev_priv(dev);
 321         kdev = &priv->pdev->dev;
 322         processed = 0;
 323
 324         /* don't scan ring further than number of refilled
 325          * descriptor */
 326         if (budget > priv->rx_desc_count)
 327                 budget = priv->rx_desc_count;
 328
 329         do {
 330                 struct bcm_enet_desc *desc;
 331                 struct sk_buff *skb;
 332                 int desc_idx;
 333                 u32 len_stat;
 334                 unsigned int len;
 335
 336                 desc_idx = priv->rx_curr_desc;
 337                 desc = &priv->rx_desc_cpu[desc_idx];
 338
 339                 /* make sure we actually read the descriptor status at
 340                  * each loop */
 341                 rmb();
 342
 343                 len_stat = desc->len_stat;
 344
 345                 /* break if dma ownership belongs to hw */
 346                 if (len_stat & DMADESC_OWNER_MASK)
 347                         break;
 348
 349                 processed++;
 350                 priv->rx_curr_desc++;
 351                 if (priv->rx_curr_desc == priv->rx_ring_size)
 352                         priv->rx_curr_desc = 0;
 353                 priv->rx_desc_count--;
 354
 355                 /* if the packet does not have start of packet _and_
 356                  * end of packet flag set, then just recycle it */
 357                 if ((len_stat & (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) !=
 358                         (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) {
 359                         dev->stats.rx_dropped++;
 360                         continue;
 361                 }
 362
 363                 /* recycle packet if it's marked as bad */
 364                 if (!priv->enet_is_sw &&
 365                     unlikely(len_stat & DMADESC_ERR_MASK)) {
 366                         dev->stats.rx_errors++;
 367
 368                         if (len_stat & DMADESC_OVSIZE_MASK)
 369                                 dev->stats.rx_length_errors++;
 370                         if (len_stat & DMADESC_CRC_MASK)
 371                                 dev->stats.rx_crc_errors++;
 372                         if (len_stat & DMADESC_UNDER_MASK)
 373                                 dev->stats.rx_frame_errors++;
 374                         if (len_stat & DMADESC_OV_MASK)
 375                                 dev->stats.rx_fifo_errors++;
 376                         continue;
 377                 }
 378
 379                 /* valid packet */
 380                 skb = priv->rx_skb[desc_idx];
 381                 len = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT;
 382                 /* don't include FCS */
 383                 len -= 4;
 384
 385                 if (len < copybreak) {
 386                         struct sk_buff *nskb;
 387
 388                         nskb = napi_alloc_skb(&priv->napi, len);
 389                         if (!nskb) {
 390                                 /* forget packet, just rearm desc */
 391                                 dev->stats.rx_dropped++;
 392                                 continue;
 393                         }
 394
 395                         dma_sync_single_for_cpu(kdev, desc->address,
 396                                                 len, DMA_FROM_DEVICE);
 397                         memcpy(nskb->data, skb->data, len);
 398                         dma_sync_single_for_device(kdev, desc->address,
 399                                                    len, DMA_FROM_DEVICE);
 400                         skb = nskb;
 401                 } else {
 402                         dma_unmap_single(&priv->pdev->dev, desc->address,
 403                                          priv->rx_skb_size, DMA_FROM_DEVICE);
 404                         priv->rx_skb[desc_idx] = NULL;
 405                 }
 406
 407                 skb_put(skb, len);
 408                 skb->protocol = eth_type_trans(skb, dev);
 409                 dev->stats.rx_packets++;
 410                 dev->stats.rx_bytes += len;
 411                 netif_receive_skb(skb);
 412
 413         } while (--budget > 0);
 414
 415         if (processed || !priv->rx_desc_count) {
 416                 bcm_enet_refill_rx(dev);
 417
 418                 /* kick rx dma */
 419                 enet_dmac_writel(priv, priv->dma_chan_en_mask,
 420                                          ENETDMAC_CHANCFG, priv->rx_chan);
 421         }
 422
 423         return processed;
 424 }
 425
 426
 427 /*
 428  * try to or force reclaim of transmitted buffers
 429  */
 430 static int bcm_enet_tx_reclaim(struct net_device *dev, int force)
 431 {
 432         struct bcm_enet_priv *priv;
 433         int released;
 434
 435         priv = netdev_priv(dev);
 436         released = 0;
 437
 438         while (priv->tx_desc_count < priv->tx_ring_size) {
 439                 struct bcm_enet_desc *desc;
 440                 struct sk_buff *skb;
 441
 442                 /* We run in a bh and fight against start_xmit, which
 443                  * is called with bh disabled  */
 444                 spin_lock(&priv->tx_lock);
 445
 446                 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc];
 447
 448                 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {
 449                         spin_unlock(&priv->tx_lock);
 450                         break;
 451                 }
 452
 453                 /* ensure other field of the descriptor were not read
 454                  * before we checked ownership */
 455                 rmb();
 456
 457                 skb = priv->tx_skb[priv->tx_dirty_desc];
 458                 priv->tx_skb[priv->tx_dirty_desc] = NULL;
 459                 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len,
 460                                  DMA_TO_DEVICE);
 461
 462                 priv->tx_dirty_desc++;
 463                 if (priv->tx_dirty_desc == priv->tx_ring_size)
 464                         priv->tx_dirty_desc = 0;
 465                 priv->tx_desc_count++;
 466
 467                 spin_unlock(&priv->tx_lock);
 468
 469                 if (desc->len_stat & DMADESC_UNDER_MASK)
 470                         dev->stats.tx_errors++;
 471
 472                 dev_kfree_skb(skb);
 473                 released++;
 474         }
 475
 476         if (netif_queue_stopped(dev) && released)
 477                 netif_wake_queue(dev);
 478
 479         return released;
 480 }
 481
 482 /*
 483  * poll func, called by network core
 484  */
 485 static int bcm_enet_poll(struct napi_struct *napi, int budget)
 486 {
 487         struct bcm_enet_priv *priv;
 488         struct net_device *dev;
 489         int rx_work_done;
 490
 491         priv = container_of(napi, struct bcm_enet_priv, napi);
 492         dev = priv->net_dev;
 493
 494         /* ack interrupts */
 495         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 496                          ENETDMAC_IR, priv->rx_chan);
 497         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 498                          ENETDMAC_IR, priv->tx_chan);
 499
 500         /* reclaim sent skb */
 501         bcm_enet_tx_reclaim(dev, 0);
 502
 503         spin_lock(&priv->rx_lock);
 504         rx_work_done = bcm_enet_receive_queue(dev, budget);
 505         spin_unlock(&priv->rx_lock);
 506
 507         if (rx_work_done >= budget) {
 508                 /* rx queue is not yet empty/clean */
 509                 return rx_work_done;
 510         }
 511
 512         /* no more packet in rx/tx queue, remove device from poll
 513          * queue */
 514         napi_complete(napi);
 515
 516         /* restore rx/tx interrupt */
 517         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 518                          ENETDMAC_IRMASK, priv->rx_chan);
 519         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 520                          ENETDMAC_IRMASK, priv->tx_chan);
 521
 522         return rx_work_done;
 523 }
 524
 525 /*
 526  * mac interrupt handler
 527  */
 528 static irqreturn_t bcm_enet_isr_mac(int irq, void *dev_id)
 529 {
 530         struct net_device *dev;
 531         struct bcm_enet_priv *priv;
 532         u32 stat;
 533
 534         dev = dev_id;
 535         priv = netdev_priv(dev);
 536
 537         stat = enet_readl(priv, ENET_IR_REG);
 538         if (!(stat & ENET_IR_MIB))
 539                 return IRQ_NONE;
 540
 541         /* clear & mask interrupt */
 542         enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
 543         enet_writel(priv, 0, ENET_IRMASK_REG);
 544
 545         /* read mib registers in workqueue */
 546         schedule_work(&priv->mib_update_task);
 547
 548         return IRQ_HANDLED;
 549 }
 550
 551 /*
 552  * rx/tx dma interrupt handler
 553  */
 554 static irqreturn_t bcm_enet_isr_dma(int irq, void *dev_id)
 555 {
 556         struct net_device *dev;
 557         struct bcm_enet_priv *priv;
 558
 559         dev = dev_id;
 560         priv = netdev_priv(dev);
 561
 562         /* mask rx/tx interrupts */
 563         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 564         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 565
 566         napi_schedule(&priv->napi);
 567
 568         return IRQ_HANDLED;
 569 }
 570
 571 /*
 572  * tx request callback
 573  */
 574 static int bcm_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
 575 {
 576         struct bcm_enet_priv *priv;
 577         struct bcm_enet_desc *desc;
 578         u32 len_stat;
 579         int ret;
 580
 581         priv = netdev_priv(dev);
 582
 583         /* lock against tx reclaim */
 584         spin_lock(&priv->tx_lock);
 585
 586         /* make sure  the tx hw queue  is not full,  should not happen
 587          * since we stop queue before it's the case */
 588         if (unlikely(!priv->tx_desc_count)) {
 589                 netif_stop_queue(dev);
 590                 dev_err(&priv->pdev->dev, "xmit called with no tx desc "
 591                         "available?\n");
 592                 ret = NETDEV_TX_BUSY;
 593                 goto out_unlock;
 594         }
 595
 596         /* pad small packets sent on a switch device */
 597         if (priv->enet_is_sw && skb->len < 64) {
 598                 int needed = 64 - skb->len;
 599                 char *data;
 600
 601                 if (unlikely(skb_tailroom(skb) < needed)) {
 602                         struct sk_buff *nskb;
 603
 604                         nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC);
 605                         if (!nskb) {
 606                                 ret = NETDEV_TX_BUSY;
 607                                 goto out_unlock;
 608                         }
 609                         dev_kfree_skb(skb);
 610                         skb = nskb;
 611                 }
 612                 data = skb_put(skb, needed);
 613                 memset(data, 0, needed);
 614         }
 615
 616         /* point to the next available desc */
 617         desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
 618         priv->tx_skb[priv->tx_curr_desc] = skb;
 619
 620         /* fill descriptor */
 621         desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
 622                                        DMA_TO_DEVICE);
 623
 624         len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
 625         len_stat |= (DMADESC_ESOP_MASK >> priv->dma_desc_shift) |
 626                 DMADESC_APPEND_CRC |
 627                 DMADESC_OWNER_MASK;
 628
 629         priv->tx_curr_desc++;
 630         if (priv->tx_curr_desc == priv->tx_ring_size) {
 631                 priv->tx_curr_desc = 0;
 632                 len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
 633         }
 634         priv->tx_desc_count--;
 635
 636         /* dma might be already polling, make sure we update desc
 637          * fields in correct order */
 638         wmb();
 639         desc->len_stat = len_stat;
 640         wmb();
 641
 642         /* kick tx dma */
 643         enet_dmac_writel(priv, priv->dma_chan_en_mask,
 644                                  ENETDMAC_CHANCFG, priv->tx_chan);
 645
 646         /* stop queue if no more desc available */
 647         if (!priv->tx_desc_count)
 648                 netif_stop_queue(dev);
 649
 650         dev->stats.tx_bytes += skb->len;
 651         dev->stats.tx_packets++;
 652         ret = NETDEV_TX_OK;
 653
 654 out_unlock:
 655         spin_unlock(&priv->tx_lock);
 656         return ret;
 657 }
 658
 659 /*
 660  * Change the interface's mac address.
 661  */
 662 static int bcm_enet_set_mac_address(struct net_device *dev, void *p)
 663 {
 664         struct bcm_enet_priv *priv;
 665         struct sockaddr *addr = p;
 666         u32 val;
 667
 668         priv = netdev_priv(dev);
 669         memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
 670
 671         /* use perfect match register 0 to store my mac address */
 672         val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) |
 673                 (dev->dev_addr[4] << 8) | dev->dev_addr[5];
 674         enet_writel(priv, val, ENET_PML_REG(0));
 675
 676         val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]);
 677         val |= ENET_PMH_DATAVALID_MASK;
 678         enet_writel(priv, val, ENET_PMH_REG(0));
 679
 680         return 0;
 681 }
 682
 683 /*
 684  * Change rx mode (promiscuous/allmulti) and update multicast list
 685  */
 686 static void bcm_enet_set_multicast_list(struct net_device *dev)
 687 {
 688         struct bcm_enet_priv *priv;
 689         struct netdev_hw_addr *ha;
 690         u32 val;
 691         int i;
 692
 693         priv = netdev_priv(dev);
 694
 695         val = enet_readl(priv, ENET_RXCFG_REG);
 696
 697         if (dev->flags & IFF_PROMISC)
 698                 val |= ENET_RXCFG_PROMISC_MASK;
 699         else
 700                 val &= ~ENET_RXCFG_PROMISC_MASK;
 701
 702         /* only 3 perfect match registers left, first one is used for
 703          * own mac address */
 704         if ((dev->flags & IFF_ALLMULTI) || netdev_mc_count(dev) > 3)
 705                 val |= ENET_RXCFG_ALLMCAST_MASK;
 706         else
 707                 val &= ~ENET_RXCFG_ALLMCAST_MASK;
 708
 709         /* no need to set perfect match registers if we catch all
 710          * multicast */
 711         if (val & ENET_RXCFG_ALLMCAST_MASK) {
 712                 enet_writel(priv, val, ENET_RXCFG_REG);
 713                 return;
 714         }
 715
 716         i = 0;
 717         netdev_for_each_mc_addr(ha, dev) {
 718                 u8 *dmi_addr;
 719                 u32 tmp;
 720
 721                 if (i == 3)
 722                         break;
 723                 /* update perfect match registers */
 724                 dmi_addr = ha->addr;
 725                 tmp = (dmi_addr[2] << 24) | (dmi_addr[3] << 16) |
 726                         (dmi_addr[4] << 8) | dmi_addr[5];
 727                 enet_writel(priv, tmp, ENET_PML_REG(i + 1));
 728
 729                 tmp = (dmi_addr[0] << 8 | dmi_addr[1]);
 730                 tmp |= ENET_PMH_DATAVALID_MASK;
 731                 enet_writel(priv, tmp, ENET_PMH_REG(i++ + 1));
 732         }
 733
 734         for (; i < 3; i++) {
 735                 enet_writel(priv, 0, ENET_PML_REG(i + 1));
 736                 enet_writel(priv, 0, ENET_PMH_REG(i + 1));
 737         }
 738
 739         enet_writel(priv, val, ENET_RXCFG_REG);
 740 }
 741
 742 /*
 743  * set mac duplex parameters
 744  */
 745 static void bcm_enet_set_duplex(struct bcm_enet_priv *priv, int fullduplex)
 746 {
 747         u32 val;
 748
 749         val = enet_readl(priv, ENET_TXCTL_REG);
 750         if (fullduplex)
 751                 val |= ENET_TXCTL_FD_MASK;
 752         else
 753                 val &= ~ENET_TXCTL_FD_MASK;
 754         enet_writel(priv, val, ENET_TXCTL_REG);
 755 }
 756
 757 /*
 758  * set mac flow control parameters
 759  */
 760 static void bcm_enet_set_flow(struct bcm_enet_priv *priv, int rx_en, int tx_en)
 761 {
 762         u32 val;
 763
 764         /* rx flow control (pause frame handling) */
 765         val = enet_readl(priv, ENET_RXCFG_REG);
 766         if (rx_en)
 767                 val |= ENET_RXCFG_ENFLOW_MASK;
 768         else
 769                 val &= ~ENET_RXCFG_ENFLOW_MASK;
 770         enet_writel(priv, val, ENET_RXCFG_REG);
 771
 772         if (!priv->dma_has_sram)
 773                 return;
 774
 775         /* tx flow control (pause frame generation) */
 776         val = enet_dma_readl(priv, ENETDMA_CFG_REG);
 777         if (tx_en)
 778                 val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
 779         else
 780                 val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
 781         enet_dma_writel(priv, val, ENETDMA_CFG_REG);
 782 }
 783
 784 /*
 785  * link changed callback (from phylib)
 786  */
 787 static void bcm_enet_adjust_phy_link(struct net_device *dev)
 788 {
 789         struct bcm_enet_priv *priv;
 790         struct phy_device *phydev;
 791         int status_changed;
 792
 793         priv = netdev_priv(dev);
 794         phydev = dev->phydev;
 795         status_changed = 0;
 796
 797         if (priv->old_link != phydev->link) {
 798                 status_changed = 1;
 799                 priv->old_link = phydev->link;
 800         }
 801
 802         /* reflect duplex change in mac configuration */
 803         if (phydev->link && phydev->duplex != priv->old_duplex) {
 804                 bcm_enet_set_duplex(priv,
 805                                     (phydev->duplex == DUPLEX_FULL) ? 1 : 0);
 806                 status_changed = 1;
 807                 priv->old_duplex = phydev->duplex;
 808         }
 809
 810         /* enable flow control if remote advertise it (trust phylib to
 811          * check that duplex is full */
 812         if (phydev->link && phydev->pause != priv->old_pause) {
 813                 int rx_pause_en, tx_pause_en;
 814
 815                 if (phydev->pause) {
 816                         /* pause was advertised by lpa and us */
 817                         rx_pause_en = 1;
 818                         tx_pause_en = 1;
 819                 } else if (!priv->pause_auto) {
 820                         /* pause setting overrided by user */
 821                         rx_pause_en = priv->pause_rx;
 822                         tx_pause_en = priv->pause_tx;
 823                 } else {
 824                         rx_pause_en = 0;
 825                         tx_pause_en = 0;
 826                 }
 827
 828                 bcm_enet_set_flow(priv, rx_pause_en, tx_pause_en);
 829                 status_changed = 1;
 830                 priv->old_pause = phydev->pause;
 831         }
 832
 833         if (status_changed) {
 834                 pr_info("%s: link %s", dev->name, phydev->link ?
 835                         "UP" : "DOWN");
 836                 if (phydev->link)
 837                         pr_cont(" - %d/%s - flow control %s", phydev->speed,
 838                                DUPLEX_FULL == phydev->duplex ? "full" : "half",
 839                                phydev->pause == 1 ? "rx&tx" : "off");
 840
 841                 pr_cont("\n");
 842         }
 843 }
 844
 845 /*
 846  * link changed callback (if phylib is not used)
 847  */
 848 static void bcm_enet_adjust_link(struct net_device *dev)
 849 {
 850         struct bcm_enet_priv *priv;
 851
 852         priv = netdev_priv(dev);
 853         bcm_enet_set_duplex(priv, priv->force_duplex_full);
 854         bcm_enet_set_flow(priv, priv->pause_rx, priv->pause_tx);
 855         netif_carrier_on(dev);
 856
 857         pr_info("%s: link forced UP - %d/%s - flow control %s/%s\n",
 858                 dev->name,
 859                 priv->force_speed_100 ? 100 : 10,
 860                 priv->force_duplex_full ? "full" : "half",
 861                 priv->pause_rx ? "rx" : "off",
 862                 priv->pause_tx ? "tx" : "off");
 863 }
 864
 865 /*
 866  * open callback, allocate dma rings & buffers and start rx operation
 867  */
 868 static int bcm_enet_open(struct net_device *dev)
 869 {
 870         struct bcm_enet_priv *priv;
 871         struct sockaddr addr;
 872         struct device *kdev;
 873         struct phy_device *phydev;
 874         int i, ret;
 875         unsigned int size;
 876         char phy_id[MII_BUS_ID_SIZE + 3];
 877         void *p;
 878         u32 val;
 879
 880         priv = netdev_priv(dev);
 881         kdev = &priv->pdev->dev;
 882
 883         if (priv->has_phy) {
 884                 /* connect to PHY */
 885                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
 886                          priv->mii_bus->id, priv->phy_id);
 887
 888                 phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link,
 889                                      PHY_INTERFACE_MODE_MII);
 890
 891                 if (IS_ERR(phydev)) {
 892                         dev_err(kdev, "could not attach to PHY\n");
 893                         return PTR_ERR(phydev);
 894                 }
 895
 896                 /* mask with MAC supported features */
 897                 phydev->supported &= (SUPPORTED_10baseT_Half |
 898                                       SUPPORTED_10baseT_Full |
 899                                       SUPPORTED_100baseT_Half |
 900                                       SUPPORTED_100baseT_Full |
 901                                       SUPPORTED_Autoneg |
 902                                       SUPPORTED_Pause |
 903                                       SUPPORTED_MII);
 904                 phydev->advertising = phydev->supported;
 905
 906                 if (priv->pause_auto && priv->pause_rx && priv->pause_tx)
 907                         phydev->advertising |= SUPPORTED_Pause;
 908                 else
 909                         phydev->advertising &= ~SUPPORTED_Pause;
 910
 911                 phy_attached_info(phydev);
 912
 913                 priv->old_link = 0;
 914                 priv->old_duplex = -1;
 915                 priv->old_pause = -1;
 916         }
 917
 918         /* mask all interrupts and request them */
 919         enet_writel(priv, 0, ENET_IRMASK_REG);
 920         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 921         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 922
 923         ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
 924         if (ret)
 925                 goto out_phy_disconnect;
 926
 927         ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, 0,
 928                           dev->name, dev);
 929         if (ret)
 930                 goto out_freeirq;
 931
 932         ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
 933                           0, dev->name, dev);
 934         if (ret)
 935                 goto out_freeirq_rx;
 936
 937         /* initialize perfect match registers */
 938         for (i = 0; i < 4; i++) {
 939                 enet_writel(priv, 0, ENET_PML_REG(i));
 940                 enet_writel(priv, 0, ENET_PMH_REG(i));
 941         }
 942
 943         /* write device mac address */
 944         memcpy(addr.sa_data, dev->dev_addr, ETH_ALEN);
 945         bcm_enet_set_mac_address(dev, &addr);
 946
 947         /* allocate rx dma ring */
 948         size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
 949         p = dma_zalloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
 950         if (!p) {
 951                 ret = -ENOMEM;
 952                 goto out_freeirq_tx;
 953         }
 954
 955         priv->rx_desc_alloc_size = size;
 956         priv->rx_desc_cpu = p;
 957
 958         /* allocate tx dma ring */
 959         size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
 960         p = dma_zalloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
 961         if (!p) {
 962                 ret = -ENOMEM;
 963                 goto out_free_rx_ring;
 964         }
 965
 966         priv->tx_desc_alloc_size = size;
 967         priv->tx_desc_cpu = p;
 968
 969         priv->tx_skb = kcalloc(priv->tx_ring_size, sizeof(struct sk_buff *),
 970                                GFP_KERNEL);
 971         if (!priv->tx_skb) {
 972                 ret = -ENOMEM;
 973                 goto out_free_tx_ring;
 974         }
 975
 976         priv->tx_desc_count = priv->tx_ring_size;
 977         priv->tx_dirty_desc = 0;
 978         priv->tx_curr_desc = 0;
 979         spin_lock_init(&priv->tx_lock);
 980
 981         /* init & fill rx ring with skbs */
 982         priv->rx_skb = kcalloc(priv->rx_ring_size, sizeof(struct sk_buff *),
 983                                GFP_KERNEL);
 984         if (!priv->rx_skb) {
 985                 ret = -ENOMEM;
 986                 goto out_free_tx_skb;
 987         }
 988
 989         priv->rx_desc_count = 0;
 990         priv->rx_dirty_desc = 0;
 991         priv->rx_curr_desc = 0;
 992
 993         /* initialize flow control buffer allocation */
 994         if (priv->dma_has_sram)
 995                 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
 996                                 ENETDMA_BUFALLOC_REG(priv->rx_chan));
 997         else
 998                 enet_dmac_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
 999                                 ENETDMAC_BUFALLOC, priv->rx_chan);
1000
1001         if (bcm_enet_refill_rx(dev)) {
1002                 dev_err(kdev, "cannot allocate rx skb queue\n");
1003                 ret = -ENOMEM;
1004                 goto out;
1005         }
1006
1007         /* write rx & tx ring addresses */
1008         if (priv->dma_has_sram) {
1009                 enet_dmas_writel(priv, priv->rx_desc_dma,
1010                                  ENETDMAS_RSTART_REG, priv->rx_chan);
1011                 enet_dmas_writel(priv, priv->tx_desc_dma,
1012                          ENETDMAS_RSTART_REG, priv->tx_chan);
1013         } else {
1014                 enet_dmac_writel(priv, priv->rx_desc_dma,
1015                                 ENETDMAC_RSTART, priv->rx_chan);
1016                 enet_dmac_writel(priv, priv->tx_desc_dma,
1017                                 ENETDMAC_RSTART, priv->tx_chan);
1018         }
1019
1020         /* clear remaining state ram for rx & tx channel */
1021         if (priv->dma_has_sram) {
1022                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
1023                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
1024                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
1025                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
1026                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
1027                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
1028         } else {
1029                 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->rx_chan);
1030                 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->tx_chan);
1031         }
1032
1033         /* set max rx/tx length */
1034         enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
1035         enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
1036
1037         /* set dma maximum burst len */
1038         enet_dmac_writel(priv, priv->dma_maxburst,
1039                          ENETDMAC_MAXBURST, priv->rx_chan);
1040         enet_dmac_writel(priv, priv->dma_maxburst,
1041                          ENETDMAC_MAXBURST, priv->tx_chan);
1042
1043         /* set correct transmit fifo watermark */
1044         enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
1045
1046         /* set flow control low/high threshold to 1/3 / 2/3 */
1047         if (priv->dma_has_sram) {
1048                 val = priv->rx_ring_size / 3;
1049                 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
1050                 val = (priv->rx_ring_size * 2) / 3;
1051                 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
1052         } else {
1053                 enet_dmac_writel(priv, 5, ENETDMAC_FC, priv->rx_chan);
1054                 enet_dmac_writel(priv, priv->rx_ring_size, ENETDMAC_LEN, priv->rx_chan);
1055                 enet_dmac_writel(priv, priv->tx_ring_size, ENETDMAC_LEN, priv->tx_chan);
1056         }
1057
1058         /* all set, enable mac and interrupts, start dma engine and
1059          * kick rx dma channel */
1060         wmb();
1061         val = enet_readl(priv, ENET_CTL_REG);
1062         val |= ENET_CTL_ENABLE_MASK;
1063         enet_writel(priv, val, ENET_CTL_REG);
1064         enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
1065         enet_dmac_writel(priv, priv->dma_chan_en_mask,
1066                          ENETDMAC_CHANCFG, priv->rx_chan);
1067
1068         /* watch "mib counters about to overflow" interrupt */
1069         enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
1070         enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1071
1072         /* watch "packet transferred" interrupt in rx and tx */
1073         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1074                          ENETDMAC_IR, priv->rx_chan);
1075         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1076                          ENETDMAC_IR, priv->tx_chan);
1077
1078         /* make sure we enable napi before rx interrupt  */
1079         napi_enable(&priv->napi);
1080
1081         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1082                          ENETDMAC_IRMASK, priv->rx_chan);
1083         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1084                          ENETDMAC_IRMASK, priv->tx_chan);
1085
1086         if (priv->has_phy)
1087                 phy_start(phydev);
1088         else
1089                 bcm_enet_adjust_link(dev);
1090
1091         netif_start_queue(dev);
1092         return 0;
1093
1094 out:
1095         for (i = 0; i < priv->rx_ring_size; i++) {
1096                 struct bcm_enet_desc *desc;
1097
1098                 if (!priv->rx_skb[i])
1099                         continue;
1100
1101                 desc = &priv->rx_desc_cpu[i];
1102                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1103                                  DMA_FROM_DEVICE);
1104                 kfree_skb(priv->rx_skb[i]);
1105         }
1106         kfree(priv->rx_skb);
1107
1108 out_free_tx_skb:
1109         kfree(priv->tx_skb);
1110
1111 out_free_tx_ring:
1112         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1113                           priv->tx_desc_cpu, priv->tx_desc_dma);
1114
1115 out_free_rx_ring:
1116         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1117                           priv->rx_desc_cpu, priv->rx_desc_dma);
1118
1119 out_freeirq_tx:
1120         free_irq(priv->irq_tx, dev);
1121
1122 out_freeirq_rx:
1123         free_irq(priv->irq_rx, dev);
1124
1125 out_freeirq:
1126         free_irq(dev->irq, dev);
1127
1128 out_phy_disconnect:
1129         if (priv->has_phy)
1130                 phy_disconnect(phydev);
1131
1132         return ret;
1133 }
1134
1135 /*
1136  * disable mac
1137  */
1138 static void bcm_enet_disable_mac(struct bcm_enet_priv *priv)
1139 {
1140         int limit;
1141         u32 val;
1142
1143         val = enet_readl(priv, ENET_CTL_REG);
1144         val |= ENET_CTL_DISABLE_MASK;
1145         enet_writel(priv, val, ENET_CTL_REG);
1146
1147         limit = 1000;
1148         do {
1149                 u32 val;
1150
1151                 val = enet_readl(priv, ENET_CTL_REG);
1152                 if (!(val & ENET_CTL_DISABLE_MASK))
1153                         break;
1154                 udelay(1);
1155         } while (limit--);
1156 }
1157
1158 /*
1159  * disable dma in given channel
1160  */
1161 static void bcm_enet_disable_dma(struct bcm_enet_priv *priv, int chan)
1162 {
1163         int limit;
1164
1165         enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG, chan);
1166
1167         limit = 1000;
1168         do {
1169                 u32 val;
1170
1171                 val = enet_dmac_readl(priv, ENETDMAC_CHANCFG, chan);
1172                 if (!(val & ENETDMAC_CHANCFG_EN_MASK))
1173                         break;
1174                 udelay(1);
1175         } while (limit--);
1176 }
1177
1178 /*
1179  * stop callback
1180  */
1181 static int bcm_enet_stop(struct net_device *dev)
1182 {
1183         struct bcm_enet_priv *priv;
1184         struct device *kdev;
1185         int i;
1186
1187         priv = netdev_priv(dev);
1188         kdev = &priv->pdev->dev;
1189
1190         netif_stop_queue(dev);
1191         napi_disable(&priv->napi);
1192         if (priv->has_phy)
1193                 phy_stop(dev->phydev);
1194         del_timer_sync(&priv->rx_timeout);
1195
1196         /* mask all interrupts */
1197         enet_writel(priv, 0, ENET_IRMASK_REG);
1198         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
1199         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
1200
1201         /* make sure no mib update is scheduled */
1202         cancel_work_sync(&priv->mib_update_task);
1203
1204         /* disable dma & mac */
1205         bcm_enet_disable_dma(priv, priv->tx_chan);
1206         bcm_enet_disable_dma(priv, priv->rx_chan);
1207         bcm_enet_disable_mac(priv);
1208
1209         /* force reclaim of all tx buffers */
1210         bcm_enet_tx_reclaim(dev, 1);
1211
1212         /* free the rx skb ring */
1213         for (i = 0; i < priv->rx_ring_size; i++) {
1214                 struct bcm_enet_desc *desc;
1215
1216                 if (!priv->rx_skb[i])
1217                         continue;
1218
1219                 desc = &priv->rx_desc_cpu[i];
1220                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1221                                  DMA_FROM_DEVICE);
1222                 kfree_skb(priv->rx_skb[i]);
1223         }
1224
1225         /* free remaining allocated memory */
1226         kfree(priv->rx_skb);
1227         kfree(priv->tx_skb);
1228         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1229                           priv->rx_desc_cpu, priv->rx_desc_dma);
1230         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1231                           priv->tx_desc_cpu, priv->tx_desc_dma);
1232         free_irq(priv->irq_tx, dev);
1233         free_irq(priv->irq_rx, dev);
1234         free_irq(dev->irq, dev);
1235
1236         /* release phy */
1237         if (priv->has_phy)
1238                 phy_disconnect(dev->phydev);
1239
1240         return 0;
1241 }
1242
1243 /*
1244  * ethtool callbacks
1245  */
1246 struct bcm_enet_stats {
1247         char stat_string[ETH_GSTRING_LEN];
1248         int sizeof_stat;
1249         int stat_offset;
1250         int mib_reg;
1251 };
1252
1253 #define GEN_STAT(m) sizeof(((struct bcm_enet_priv *)0)->m),             \
1254                      offsetof(struct bcm_enet_priv, m)
1255 #define DEV_STAT(m) sizeof(((struct net_device_stats *)0)->m),          \
1256                      offsetof(struct net_device_stats, m)
1257
1258 static const struct bcm_enet_stats bcm_enet_gstrings_stats[] = {
1259         { "rx_packets", DEV_STAT(rx_packets), -1 },
1260         { "tx_packets", DEV_STAT(tx_packets), -1 },
1261         { "rx_bytes", DEV_STAT(rx_bytes), -1 },
1262         { "tx_bytes", DEV_STAT(tx_bytes), -1 },
1263         { "rx_errors", DEV_STAT(rx_errors), -1 },
1264         { "tx_errors", DEV_STAT(tx_errors), -1 },
1265         { "rx_dropped", DEV_STAT(rx_dropped), -1 },
1266         { "tx_dropped", DEV_STAT(tx_dropped), -1 },
1267
1268         { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETH_MIB_RX_GD_OCTETS},
1269         { "rx_good_pkts", GEN_STAT(mib.rx_gd_pkts), ETH_MIB_RX_GD_PKTS },
1270         { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETH_MIB_RX_BRDCAST },
1271         { "rx_multicast", GEN_STAT(mib.rx_mult), ETH_MIB_RX_MULT },
1272         { "rx_64_octets", GEN_STAT(mib.rx_64), ETH_MIB_RX_64 },
1273         { "rx_65_127_oct", GEN_STAT(mib.rx_65_127), ETH_MIB_RX_65_127 },
1274         { "rx_128_255_oct", GEN_STAT(mib.rx_128_255), ETH_MIB_RX_128_255 },
1275         { "rx_256_511_oct", GEN_STAT(mib.rx_256_511), ETH_MIB_RX_256_511 },
1276         { "rx_512_1023_oct", GEN_STAT(mib.rx_512_1023), ETH_MIB_RX_512_1023 },
1277         { "rx_1024_max_oct", GEN_STAT(mib.rx_1024_max), ETH_MIB_RX_1024_MAX },
1278         { "rx_jabber", GEN_STAT(mib.rx_jab), ETH_MIB_RX_JAB },
1279         { "rx_oversize", GEN_STAT(mib.rx_ovr), ETH_MIB_RX_OVR },
1280         { "rx_fragment", GEN_STAT(mib.rx_frag), ETH_MIB_RX_FRAG },
1281         { "rx_dropped", GEN_STAT(mib.rx_drop), ETH_MIB_RX_DROP },
1282         { "rx_crc_align", GEN_STAT(mib.rx_crc_align), ETH_MIB_RX_CRC_ALIGN },
1283         { "rx_undersize", GEN_STAT(mib.rx_und), ETH_MIB_RX_UND },
1284         { "rx_crc", GEN_STAT(mib.rx_crc), ETH_MIB_RX_CRC },
1285         { "rx_align", GEN_STAT(mib.rx_align), ETH_MIB_RX_ALIGN },
1286         { "rx_symbol_error", GEN_STAT(mib.rx_sym), ETH_MIB_RX_SYM },
1287         { "rx_pause", GEN_STAT(mib.rx_pause), ETH_MIB_RX_PAUSE },
1288         { "rx_control", GEN_STAT(mib.rx_cntrl), ETH_MIB_RX_CNTRL },
1289
1290         { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETH_MIB_TX_GD_OCTETS },
1291         { "tx_good_pkts", GEN_STAT(mib.tx_gd_pkts), ETH_MIB_TX_GD_PKTS },
1292         { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETH_MIB_TX_BRDCAST },
1293         { "tx_multicast", GEN_STAT(mib.tx_mult), ETH_MIB_TX_MULT },
1294         { "tx_64_oct", GEN_STAT(mib.tx_64), ETH_MIB_TX_64 },
1295         { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETH_MIB_TX_65_127 },
1296         { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETH_MIB_TX_128_255 },
1297         { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETH_MIB_TX_256_511 },
1298         { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETH_MIB_TX_512_1023},
1299         { "tx_1024_max_oct", GEN_STAT(mib.tx_1024_max), ETH_MIB_TX_1024_MAX },
1300         { "tx_jabber", GEN_STAT(mib.tx_jab), ETH_MIB_TX_JAB },
1301         { "tx_oversize", GEN_STAT(mib.tx_ovr), ETH_MIB_TX_OVR },
1302         { "tx_fragment", GEN_STAT(mib.tx_frag), ETH_MIB_TX_FRAG },
1303         { "tx_underrun", GEN_STAT(mib.tx_underrun), ETH_MIB_TX_UNDERRUN },
1304         { "tx_collisions", GEN_STAT(mib.tx_col), ETH_MIB_TX_COL },
1305         { "tx_single_collision", GEN_STAT(mib.tx_1_col), ETH_MIB_TX_1_COL },
1306         { "tx_multiple_collision", GEN_STAT(mib.tx_m_col), ETH_MIB_TX_M_COL },
1307         { "tx_excess_collision", GEN_STAT(mib.tx_ex_col), ETH_MIB_TX_EX_COL },
1308         { "tx_late_collision", GEN_STAT(mib.tx_late), ETH_MIB_TX_LATE },
1309         { "tx_deferred", GEN_STAT(mib.tx_def), ETH_MIB_TX_DEF },
1310         { "tx_carrier_sense", GEN_STAT(mib.tx_crs), ETH_MIB_TX_CRS },
1311         { "tx_pause", GEN_STAT(mib.tx_pause), ETH_MIB_TX_PAUSE },
1312
1313 };
1314
1315 #define BCM_ENET_STATS_LEN      ARRAY_SIZE(bcm_enet_gstrings_stats)
1316
1317 static const u32 unused_mib_regs[] = {
1318         ETH_MIB_TX_ALL_OCTETS,
1319         ETH_MIB_TX_ALL_PKTS,
1320         ETH_MIB_RX_ALL_OCTETS,
1321         ETH_MIB_RX_ALL_PKTS,
1322 };
1323
1324
1325 static void bcm_enet_get_drvinfo(struct net_device *netdev,
1326                                  struct ethtool_drvinfo *drvinfo)
1327 {
1328         strlcpy(drvinfo->driver, bcm_enet_driver_name, sizeof(drvinfo->driver));
1329         strlcpy(drvinfo->version, bcm_enet_driver_version,
1330                 sizeof(drvinfo->version));
1331         strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1332         strlcpy(drvinfo->bus_info, "bcm63xx", sizeof(drvinfo->bus_info));
1333 }
1334
1335 static int bcm_enet_get_sset_count(struct net_device *netdev,
1336                                         int string_set)
1337 {
1338         switch (string_set) {
1339         case ETH_SS_STATS:
1340                 return BCM_ENET_STATS_LEN;
1341         default:
1342                 return -EINVAL;
1343         }
1344 }
1345
1346 static void bcm_enet_get_strings(struct net_device *netdev,
1347                                  u32 stringset, u8 *data)
1348 {
1349         int i;
1350
1351         switch (stringset) {
1352         case ETH_SS_STATS:
1353                 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1354                         memcpy(data + i * ETH_GSTRING_LEN,
1355                                bcm_enet_gstrings_stats[i].stat_string,
1356                                ETH_GSTRING_LEN);
1357                 }
1358                 break;
1359         }
1360 }
1361
1362 static void update_mib_counters(struct bcm_enet_priv *priv)
1363 {
1364         int i;
1365
1366         for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1367                 const struct bcm_enet_stats *s;
1368                 u32 val;
1369                 char *p;
1370
1371                 s = &bcm_enet_gstrings_stats[i];
1372                 if (s->mib_reg == -1)
1373                         continue;
1374
1375                 val = enet_readl(priv, ENET_MIB_REG(s->mib_reg));
1376                 p = (char *)priv + s->stat_offset;
1377
1378                 if (s->sizeof_stat == sizeof(u64))
1379                         *(u64 *)p += val;
1380                 else
1381                         *(u32 *)p += val;
1382         }
1383
1384         /* also empty unused mib counters to make sure mib counter
1385          * overflow interrupt is cleared */
1386         for (i = 0; i < ARRAY_SIZE(unused_mib_regs); i++)
1387                 (void)enet_readl(priv, ENET_MIB_REG(unused_mib_regs[i]));
1388 }
1389
1390 static void bcm_enet_update_mib_counters_defer(struct work_struct *t)
1391 {
1392         struct bcm_enet_priv *priv;
1393
1394         priv = container_of(t, struct bcm_enet_priv, mib_update_task);
1395         mutex_lock(&priv->mib_update_lock);
1396         update_mib_counters(priv);
1397         mutex_unlock(&priv->mib_update_lock);
1398
1399         /* reenable mib interrupt */
1400         if (netif_running(priv->net_dev))
1401                 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1402 }
1403
1404 static void bcm_enet_get_ethtool_stats(struct net_device *netdev,
1405                                        struct ethtool_stats *stats,
1406                                        u64 *data)
1407 {
1408         struct bcm_enet_priv *priv;
1409         int i;
1410
1411         priv = netdev_priv(netdev);
1412
1413         mutex_lock(&priv->mib_update_lock);
1414         update_mib_counters(priv);
1415
1416         for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1417                 const struct bcm_enet_stats *s;
1418                 char *p;
1419
1420                 s = &bcm_enet_gstrings_stats[i];
1421                 if (s->mib_reg == -1)
1422                         p = (char *)&netdev->stats;
1423                 else
1424                         p = (char *)priv;
1425                 p += s->stat_offset;
1426                 data[i] = (s->sizeof_stat == sizeof(u64)) ?
1427                         *(u64 *)p : *(u32 *)p;
1428         }
1429         mutex_unlock(&priv->mib_update_lock);
1430 }
1431
1432 static int bcm_enet_nway_reset(struct net_device *dev)
1433 {
1434         struct bcm_enet_priv *priv;
1435
1436         priv = netdev_priv(dev);
1437         if (priv->has_phy) {
1438                 if (!dev->phydev)
1439                         return -ENODEV;
1440                 return genphy_restart_aneg(dev->phydev);
1441         }
1442
1443         return -EOPNOTSUPP;
1444 }
1445
1446 static int bcm_enet_get_link_ksettings(struct net_device *dev,
1447                                        struct ethtool_link_ksettings *cmd)
1448 {
1449         struct bcm_enet_priv *priv;
1450         u32 supported, advertising;
1451
1452         priv = netdev_priv(dev);
1453
1454         if (priv->has_phy) {
1455                 if (!dev->phydev)
1456                         return -ENODEV;
1457                 return phy_ethtool_ksettings_get(dev->phydev, cmd);
1458         } else {
1459                 cmd->base.autoneg = 0;
1460                 cmd->base.speed = (priv->force_speed_100) ?
1461                         SPEED_100 : SPEED_10;
1462                 cmd->base.duplex = (priv->force_duplex_full) ?
1463                         DUPLEX_FULL : DUPLEX_HALF;
1464                 supported = ADVERTISED_10baseT_Half |
1465                         ADVERTISED_10baseT_Full |
1466                         ADVERTISED_100baseT_Half |
1467                         ADVERTISED_100baseT_Full;
1468                 advertising = 0;
1469                 ethtool_convert_legacy_u32_to_link_mode(
1470                         cmd->link_modes.supported, supported);
1471                 ethtool_convert_legacy_u32_to_link_mode(
1472                         cmd->link_modes.advertising, advertising);
1473                 cmd->base.port = PORT_MII;
1474         }
1475         return 0;
1476 }
1477
1478 static int bcm_enet_set_link_ksettings(struct net_device *dev,
1479                                        const struct ethtool_link_ksettings *cmd)
1480 {
1481         struct bcm_enet_priv *priv;
1482
1483         priv = netdev_priv(dev);
1484         if (priv->has_phy) {
1485                 if (!dev->phydev)
1486                         return -ENODEV;
1487                 return phy_ethtool_ksettings_set(dev->phydev, cmd);
1488         } else {
1489
1490                 if (cmd->base.autoneg ||
1491                     (cmd->base.speed != SPEED_100 &&
1492                      cmd->base.speed != SPEED_10) ||
1493                     cmd->base.port != PORT_MII)
1494                         return -EINVAL;
1495
1496                 priv->force_speed_100 =
1497                         (cmd->base.speed == SPEED_100) ? 1 : 0;
1498                 priv->force_duplex_full =
1499                         (cmd->base.duplex == DUPLEX_FULL) ? 1 : 0;
1500
1501                 if (netif_running(dev))
1502                         bcm_enet_adjust_link(dev);
1503                 return 0;
1504         }
1505 }
1506
1507 static void bcm_enet_get_ringparam(struct net_device *dev,
1508                                    struct ethtool_ringparam *ering)
1509 {
1510         struct bcm_enet_priv *priv;
1511
1512         priv = netdev_priv(dev);
1513
1514         /* rx/tx ring is actually only limited by memory */
1515         ering->rx_max_pending = 8192;
1516         ering->tx_max_pending = 8192;
1517         ering->rx_pending = priv->rx_ring_size;
1518         ering->tx_pending = priv->tx_ring_size;
1519 }
1520
1521 static int bcm_enet_set_ringparam(struct net_device *dev,
1522                                   struct ethtool_ringparam *ering)
1523 {
1524         struct bcm_enet_priv *priv;
1525         int was_running;
1526
1527         priv = netdev_priv(dev);
1528
1529         was_running = 0;
1530         if (netif_running(dev)) {
1531                 bcm_enet_stop(dev);
1532                 was_running = 1;
1533         }
1534
1535         priv->rx_ring_size = ering->rx_pending;
1536         priv->tx_ring_size = ering->tx_pending;
1537
1538         if (was_running) {
1539                 int err;
1540
1541                 err = bcm_enet_open(dev);
1542                 if (err)
1543                         dev_close(dev);
1544                 else
1545                         bcm_enet_set_multicast_list(dev);
1546         }
1547         return 0;
1548 }
1549
1550 static void bcm_enet_get_pauseparam(struct net_device *dev,
1551                                     struct ethtool_pauseparam *ecmd)
1552 {
1553         struct bcm_enet_priv *priv;
1554
1555         priv = netdev_priv(dev);
1556         ecmd->autoneg = priv->pause_auto;
1557         ecmd->rx_pause = priv->pause_rx;
1558         ecmd->tx_pause = priv->pause_tx;
1559 }
1560
1561 static int bcm_enet_set_pauseparam(struct net_device *dev,
1562                                    struct ethtool_pauseparam *ecmd)
1563 {
1564         struct bcm_enet_priv *priv;
1565
1566         priv = netdev_priv(dev);
1567
1568         if (priv->has_phy) {
1569                 if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) {
1570                         /* asymetric pause mode not supported,
1571                          * actually possible but integrated PHY has RO
1572                          * asym_pause bit */
1573                         return -EINVAL;
1574                 }
1575         } else {
1576                 /* no pause autoneg on direct mii connection */
1577                 if (ecmd->autoneg)
1578                         return -EINVAL;
1579         }
1580
1581         priv->pause_auto = ecmd->autoneg;
1582         priv->pause_rx = ecmd->rx_pause;
1583         priv->pause_tx = ecmd->tx_pause;
1584
1585         return 0;
1586 }
1587
1588 static const struct ethtool_ops bcm_enet_ethtool_ops = {
1589         .get_strings            = bcm_enet_get_strings,
1590         .get_sset_count         = bcm_enet_get_sset_count,
1591         .get_ethtool_stats      = bcm_enet_get_ethtool_stats,
1592         .nway_reset             = bcm_enet_nway_reset,
1593         .get_drvinfo            = bcm_enet_get_drvinfo,
1594         .get_link               = ethtool_op_get_link,
1595         .get_ringparam          = bcm_enet_get_ringparam,
1596         .set_ringparam          = bcm_enet_set_ringparam,
1597         .get_pauseparam         = bcm_enet_get_pauseparam,
1598         .set_pauseparam         = bcm_enet_set_pauseparam,
1599         .get_link_ksettings     = bcm_enet_get_link_ksettings,
1600         .set_link_ksettings     = bcm_enet_set_link_ksettings,
1601 };
1602
1603 static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1604 {
1605         struct bcm_enet_priv *priv;
1606
1607         priv = netdev_priv(dev);
1608         if (priv->has_phy) {
1609                 if (!dev->phydev)
1610                         return -ENODEV;
1611                 return phy_mii_ioctl(dev->phydev, rq, cmd);
1612         } else {
1613                 struct mii_if_info mii;
1614
1615                 mii.dev = dev;
1616                 mii.mdio_read = bcm_enet_mdio_read_mii;
1617                 mii.mdio_write = bcm_enet_mdio_write_mii;
1618                 mii.phy_id = 0;
1619                 mii.phy_id_mask = 0x3f;
1620                 mii.reg_num_mask = 0x1f;
1621                 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
1622         }
1623 }
1624
1625 /*
1626  * calculate actual hardware mtu
1627  */
1628 static int compute_hw_mtu(struct bcm_enet_priv *priv, int mtu)
1629 {
1630         int actual_mtu;
1631
1632         actual_mtu = mtu;
1633
1634         /* add ethernet header + vlan tag size */
1635         actual_mtu += VLAN_ETH_HLEN;
1636
1637         if (actual_mtu < 64 || actual_mtu > BCMENET_MAX_MTU)
1638                 return -EINVAL;
1639
1640         /*
1641          * setup maximum size before we get overflow mark in
1642          * descriptor, note that this will not prevent reception of
1643          * big frames, they will be split into multiple buffers
1644          * anyway
1645          */
1646         priv->hw_mtu = actual_mtu;
1647
1648         /*
1649          * align rx buffer size to dma burst len, account FCS since
1650          * it's appended
1651          */
1652         priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN,
1653                                   priv->dma_maxburst * 4);
1654         return 0;
1655 }
1656
1657 /*
1658  * adjust mtu, can't be called while device is running
1659  */
1660 static int bcm_enet_change_mtu(struct net_device *dev, int new_mtu)
1661 {
1662         int ret;
1663
1664         if (netif_running(dev))
1665                 return -EBUSY;
1666
1667         ret = compute_hw_mtu(netdev_priv(dev), new_mtu);
1668         if (ret)
1669                 return ret;
1670         dev->mtu = new_mtu;
1671         return 0;
1672 }
1673
1674 /*
1675  * preinit hardware to allow mii operation while device is down
1676  */
1677 static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv)
1678 {
1679         u32 val;
1680         int limit;
1681
1682         /* make sure mac is disabled */
1683         bcm_enet_disable_mac(priv);
1684
1685         /* soft reset mac */
1686         val = ENET_CTL_SRESET_MASK;
1687         enet_writel(priv, val, ENET_CTL_REG);
1688         wmb();
1689
1690         limit = 1000;
1691         do {
1692                 val = enet_readl(priv, ENET_CTL_REG);
1693                 if (!(val & ENET_CTL_SRESET_MASK))
1694                         break;
1695                 udelay(1);
1696         } while (limit--);
1697
1698         /* select correct mii interface */
1699         val = enet_readl(priv, ENET_CTL_REG);
1700         if (priv->use_external_mii)
1701                 val |= ENET_CTL_EPHYSEL_MASK;
1702         else
1703                 val &= ~ENET_CTL_EPHYSEL_MASK;
1704         enet_writel(priv, val, ENET_CTL_REG);
1705
1706         /* turn on mdc clock */
1707         enet_writel(priv, (0x1f << ENET_MIISC_MDCFREQDIV_SHIFT) |
1708                     ENET_MIISC_PREAMBLEEN_MASK, ENET_MIISC_REG);
1709
1710         /* set mib counters to self-clear when read */
1711         val = enet_readl(priv, ENET_MIBCTL_REG);
1712         val |= ENET_MIBCTL_RDCLEAR_MASK;
1713         enet_writel(priv, val, ENET_MIBCTL_REG);
1714 }
1715
1716 static const struct net_device_ops bcm_enet_ops = {
1717         .ndo_open               = bcm_enet_open,
1718         .ndo_stop               = bcm_enet_stop,
1719         .ndo_start_xmit         = bcm_enet_start_xmit,
1720         .ndo_set_mac_address    = bcm_enet_set_mac_address,
1721         .ndo_set_rx_mode        = bcm_enet_set_multicast_list,
1722         .ndo_do_ioctl           = bcm_enet_ioctl,
1723         .ndo_change_mtu         = bcm_enet_change_mtu,
1724 };
1725
1726 /*
1727  * allocate netdevice, request register memory and register device.
1728  */
1729 static int bcm_enet_probe(struct platform_device *pdev)
1730 {
1731         struct bcm_enet_priv *priv;
1732         struct net_device *dev;
1733         struct bcm63xx_enet_platform_data *pd;
1734         struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx;
1735         struct mii_bus *bus;
1736         const char *clk_name;
1737         int i, ret;
1738
1739         /* stop if shared driver failed, assume driver->probe will be
1740          * called in the same order we register devices (correct ?) */
1741         if (!bcm_enet_shared_base[0])
1742                 return -ENODEV;
1743
1744         res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1745         res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1746         res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
1747         if (!res_irq || !res_irq_rx || !res_irq_tx)
1748                 return -ENODEV;
1749
1750         ret = 0;
1751         dev = alloc_etherdev(sizeof(*priv));
1752         if (!dev)
1753                 return -ENOMEM;
1754         priv = netdev_priv(dev);
1755
1756         priv->enet_is_sw = false;
1757         priv->dma_maxburst = BCMENET_DMA_MAXBURST;
1758
1759         ret = compute_hw_mtu(priv, dev->mtu);
1760         if (ret)
1761                 goto out;
1762
1763         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1764         priv->base = devm_ioremap_resource(&pdev->dev, res_mem);
1765         if (IS_ERR(priv->base)) {
1766                 ret = PTR_ERR(priv->base);
1767                 goto out;
1768         }
1769
1770         dev->irq = priv->irq = res_irq->start;
1771         priv->irq_rx = res_irq_rx->start;
1772         priv->irq_tx = res_irq_tx->start;
1773         priv->mac_id = pdev->id;
1774
1775         /* get rx & tx dma channel id for this mac */
1776         if (priv->mac_id == 0) {
1777                 priv->rx_chan = 0;
1778                 priv->tx_chan = 1;
1779                 clk_name = "enet0";
1780         } else {
1781                 priv->rx_chan = 2;
1782                 priv->tx_chan = 3;
1783                 clk_name = "enet1";
1784         }
1785
1786         priv->mac_clk = clk_get(&pdev->dev, clk_name);
1787         if (IS_ERR(priv->mac_clk)) {
1788                 ret = PTR_ERR(priv->mac_clk);
1789                 goto out;
1790         }
1791         clk_prepare_enable(priv->mac_clk);
1792
1793         /* initialize default and fetch platform data */
1794         priv->rx_ring_size = BCMENET_DEF_RX_DESC;
1795         priv->tx_ring_size = BCMENET_DEF_TX_DESC;
1796
1797         pd = dev_get_platdata(&pdev->dev);
1798         if (pd) {
1799                 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
1800                 priv->has_phy = pd->has_phy;
1801                 priv->phy_id = pd->phy_id;
1802                 priv->has_phy_interrupt = pd->has_phy_interrupt;
1803                 priv->phy_interrupt = pd->phy_interrupt;
1804                 priv->use_external_mii = !pd->use_internal_phy;
1805                 priv->pause_auto = pd->pause_auto;
1806                 priv->pause_rx = pd->pause_rx;
1807                 priv->pause_tx = pd->pause_tx;
1808                 priv->force_duplex_full = pd->force_duplex_full;
1809                 priv->force_speed_100 = pd->force_speed_100;
1810                 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
1811                 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
1812                 priv->dma_chan_width = pd->dma_chan_width;
1813                 priv->dma_has_sram = pd->dma_has_sram;
1814                 priv->dma_desc_shift = pd->dma_desc_shift;
1815         }
1816
1817         if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) {
1818                 /* using internal PHY, enable clock */
1819                 priv->phy_clk = clk_get(&pdev->dev, "ephy");
1820                 if (IS_ERR(priv->phy_clk)) {
1821                         ret = PTR_ERR(priv->phy_clk);
1822                         priv->phy_clk = NULL;
1823                         goto out_put_clk_mac;
1824                 }
1825                 clk_prepare_enable(priv->phy_clk);
1826         }
1827
1828         /* do minimal hardware init to be able to probe mii bus */
1829         bcm_enet_hw_preinit(priv);
1830
1831         /* MII bus registration */
1832         if (priv->has_phy) {
1833
1834                 priv->mii_bus = mdiobus_alloc();
1835                 if (!priv->mii_bus) {
1836                         ret = -ENOMEM;
1837                         goto out_uninit_hw;
1838                 }
1839
1840                 bus = priv->mii_bus;
1841                 bus->name = "bcm63xx_enet MII bus";
1842                 bus->parent = &pdev->dev;
1843                 bus->priv = priv;
1844                 bus->read = bcm_enet_mdio_read_phylib;
1845                 bus->write = bcm_enet_mdio_write_phylib;
1846                 sprintf(bus->id, "%s-%d", pdev->name, priv->mac_id);
1847
1848                 /* only probe bus where we think the PHY is, because
1849                  * the mdio read operation return 0 instead of 0xffff
1850                  * if a slave is not present on hw */
1851                 bus->phy_mask = ~(1 << priv->phy_id);
1852
1853                 if (priv->has_phy_interrupt)
1854                         bus->irq[priv->phy_id] = priv->phy_interrupt;
1855
1856                 ret = mdiobus_register(bus);
1857                 if (ret) {
1858                         dev_err(&pdev->dev, "unable to register mdio bus\n");
1859                         goto out_free_mdio;
1860                 }
1861         } else {
1862
1863                 /* run platform code to initialize PHY device */
1864                 if (pd && pd->mii_config &&
1865                     pd->mii_config(dev, 1, bcm_enet_mdio_read_mii,
1866                                    bcm_enet_mdio_write_mii)) {
1867                         dev_err(&pdev->dev, "unable to configure mdio bus\n");
1868                         goto out_uninit_hw;
1869                 }
1870         }
1871
1872         spin_lock_init(&priv->rx_lock);
1873
1874         /* init rx timeout (used for oom) */
1875         init_timer(&priv->rx_timeout);
1876         priv->rx_timeout.function = bcm_enet_refill_rx_timer;
1877         priv->rx_timeout.data = (unsigned long)dev;
1878
1879         /* init the mib update lock&work */
1880         mutex_init(&priv->mib_update_lock);
1881         INIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer);
1882
1883         /* zero mib counters */
1884         for (i = 0; i < ENET_MIB_REG_COUNT; i++)
1885                 enet_writel(priv, 0, ENET_MIB_REG(i));
1886
1887         /* register netdevice */
1888         dev->netdev_ops = &bcm_enet_ops;
1889         netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
1890
1891         dev->ethtool_ops = &bcm_enet_ethtool_ops;
1892         SET_NETDEV_DEV(dev, &pdev->dev);
1893
1894         ret = register_netdev(dev);
1895         if (ret)
1896                 goto out_unregister_mdio;
1897
1898         netif_carrier_off(dev);
1899         platform_set_drvdata(pdev, dev);
1900         priv->pdev = pdev;
1901         priv->net_dev = dev;
1902
1903         return 0;
1904
1905 out_unregister_mdio:
1906         if (priv->mii_bus)
1907                 mdiobus_unregister(priv->mii_bus);
1908
1909 out_free_mdio:
1910         if (priv->mii_bus)
1911                 mdiobus_free(priv->mii_bus);
1912
1913 out_uninit_hw:
1914         /* turn off mdc clock */
1915         enet_writel(priv, 0, ENET_MIISC_REG);
1916         if (priv->phy_clk) {
1917                 clk_disable_unprepare(priv->phy_clk);
1918                 clk_put(priv->phy_clk);
1919         }
1920
1921 out_put_clk_mac:
1922         clk_disable_unprepare(priv->mac_clk);
1923         clk_put(priv->mac_clk);
1924 out:
1925         free_netdev(dev);
1926         return ret;
1927 }
1928
1929
1930 /*
1931  * exit func, stops hardware and unregisters netdevice
1932  */
1933 static int bcm_enet_remove(struct platform_device *pdev)
1934 {
1935         struct bcm_enet_priv *priv;
1936         struct net_device *dev;
1937
1938         /* stop netdevice */
1939         dev = platform_get_drvdata(pdev);
1940         priv = netdev_priv(dev);
1941         unregister_netdev(dev);
1942
1943         /* turn off mdc clock */
1944         enet_writel(priv, 0, ENET_MIISC_REG);
1945
1946         if (priv->has_phy) {
1947                 mdiobus_unregister(priv->mii_bus);
1948                 mdiobus_free(priv->mii_bus);
1949         } else {
1950                 struct bcm63xx_enet_platform_data *pd;
1951
1952                 pd = dev_get_platdata(&pdev->dev);
1953                 if (pd && pd->mii_config)
1954                         pd->mii_config(dev, 0, bcm_enet_mdio_read_mii,
1955                                        bcm_enet_mdio_write_mii);
1956         }
1957
1958         /* disable hw block clocks */
1959         if (priv->phy_clk) {
1960                 clk_disable_unprepare(priv->phy_clk);
1961                 clk_put(priv->phy_clk);
1962         }
1963         clk_disable_unprepare(priv->mac_clk);
1964         clk_put(priv->mac_clk);
1965
1966         free_netdev(dev);
1967         return 0;
1968 }
1969
1970 struct platform_driver bcm63xx_enet_driver = {
1971         .probe  = bcm_enet_probe,
1972         .remove = bcm_enet_remove,
1973         .driver = {
1974                 .name   = "bcm63xx_enet",
1975                 .owner  = THIS_MODULE,
1976         },
1977 };
1978
1979 /*
1980  * switch mii access callbacks
1981  */
1982 static int bcmenet_sw_mdio_read(struct bcm_enet_priv *priv,
1983                                 int ext, int phy_id, int location)
1984 {
1985         u32 reg;
1986         int ret;
1987
1988         spin_lock_bh(&priv->enetsw_mdio_lock);
1989         enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
1990
1991         reg = ENETSW_MDIOC_RD_MASK |
1992                 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
1993                 (location << ENETSW_MDIOC_REG_SHIFT);
1994
1995         if (ext)
1996                 reg |= ENETSW_MDIOC_EXT_MASK;
1997
1998         enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
1999         udelay(50);
2000         ret = enetsw_readw(priv, ENETSW_MDIOD_REG);
2001         spin_unlock_bh(&priv->enetsw_mdio_lock);
2002         return ret;
2003 }
2004
2005 static void bcmenet_sw_mdio_write(struct bcm_enet_priv *priv,
2006                                  int ext, int phy_id, int location,
2007                                  uint16_t data)
2008 {
2009         u32 reg;
2010
2011         spin_lock_bh(&priv->enetsw_mdio_lock);
2012         enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
2013
2014         reg = ENETSW_MDIOC_WR_MASK |
2015                 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
2016                 (location << ENETSW_MDIOC_REG_SHIFT);
2017
2018         if (ext)
2019                 reg |= ENETSW_MDIOC_EXT_MASK;
2020
2021         reg |= data;
2022
2023         enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
2024         udelay(50);
2025         spin_unlock_bh(&priv->enetsw_mdio_lock);
2026 }
2027
2028 static inline int bcm_enet_port_is_rgmii(int portid)
2029 {
2030         return portid >= ENETSW_RGMII_PORT0;
2031 }
2032
2033 /*
2034  * enet sw PHY polling
2035  */
2036 static void swphy_poll_timer(unsigned long data)
2037 {
2038         struct bcm_enet_priv *priv = (struct bcm_enet_priv *)data;
2039         unsigned int i;
2040
2041         for (i = 0; i < priv->num_ports; i++) {
2042                 struct bcm63xx_enetsw_port *port;
2043                 int val, j, up, advertise, lpa, speed, duplex, media;
2044                 int external_phy = bcm_enet_port_is_rgmii(i);
2045                 u8 override;
2046
2047                 port = &priv->used_ports[i];
2048                 if (!port->used)
2049                         continue;
2050
2051                 if (port->bypass_link)
2052                         continue;
2053
2054                 /* dummy read to clear */
2055                 for (j = 0; j < 2; j++)
2056                         val = bcmenet_sw_mdio_read(priv, external_phy,
2057                                                    port->phy_id, MII_BMSR);
2058
2059                 if (val == 0xffff)
2060                         continue;
2061
2062                 up = (val & BMSR_LSTATUS) ? 1 : 0;
2063                 if (!(up ^ priv->sw_port_link[i]))
2064                         continue;
2065
2066                 priv->sw_port_link[i] = up;
2067
2068                 /* link changed */
2069                 if (!up) {
2070                         dev_info(&priv->pdev->dev, "link DOWN on %s\n",
2071                                  port->name);
2072                         enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2073                                       ENETSW_PORTOV_REG(i));
2074                         enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2075                                       ENETSW_PTCTRL_TXDIS_MASK,
2076                                       ENETSW_PTCTRL_REG(i));
2077                         continue;
2078                 }
2079
2080                 advertise = bcmenet_sw_mdio_read(priv, external_phy,
2081                                                  port->phy_id, MII_ADVERTISE);
2082
2083                 lpa = bcmenet_sw_mdio_read(priv, external_phy, port->phy_id,
2084                                            MII_LPA);
2085
2086                 /* figure out media and duplex from advertise and LPA values */
2087                 media = mii_nway_result(lpa & advertise);
2088                 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
2089
2090                 if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF))
2091                         speed = 100;
2092                 else
2093                         speed = 10;
2094
2095                 if (val & BMSR_ESTATEN) {
2096                         advertise = bcmenet_sw_mdio_read(priv, external_phy,
2097                                                 port->phy_id, MII_CTRL1000);
2098
2099                         lpa = bcmenet_sw_mdio_read(priv, external_phy,
2100                                                 port->phy_id, MII_STAT1000);
2101
2102                         if (advertise & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)
2103                                         && lpa & (LPA_1000FULL | LPA_1000HALF)) {
2104                                 speed = 1000;
2105                                 duplex = (lpa & LPA_1000FULL);
2106                         }
2107                 }
2108
2109                 dev_info(&priv->pdev->dev,
2110                          "link UP on %s, %dMbps, %s-duplex\n",
2111                          port->name, speed, duplex ? "full" : "half");
2112
2113                 override = ENETSW_PORTOV_ENABLE_MASK |
2114                         ENETSW_PORTOV_LINKUP_MASK;
2115
2116                 if (speed == 1000)
2117                         override |= ENETSW_IMPOV_1000_MASK;
2118                 else if (speed == 100)
2119                         override |= ENETSW_IMPOV_100_MASK;
2120                 if (duplex)
2121                         override |= ENETSW_IMPOV_FDX_MASK;
2122
2123                 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2124                 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2125         }
2126
2127         priv->swphy_poll.expires = jiffies + HZ;
2128         add_timer(&priv->swphy_poll);
2129 }
2130
2131 /*
2132  * open callback, allocate dma rings & buffers and start rx operation
2133  */
2134 static int bcm_enetsw_open(struct net_device *dev)
2135 {
2136         struct bcm_enet_priv *priv;
2137         struct device *kdev;
2138         int i, ret;
2139         unsigned int size;
2140         void *p;
2141         u32 val;
2142
2143         priv = netdev_priv(dev);
2144         kdev = &priv->pdev->dev;
2145
2146         /* mask all interrupts and request them */
2147         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2148         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
2149
2150         ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
2151                           0, dev->name, dev);
2152         if (ret)
2153                 goto out_freeirq;
2154
2155         if (priv->irq_tx != -1) {
2156                 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
2157                                   0, dev->name, dev);
2158                 if (ret)
2159                         goto out_freeirq_rx;
2160         }
2161
2162         /* allocate rx dma ring */
2163         size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
2164         p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
2165         if (!p) {
2166                 dev_err(kdev, "cannot allocate rx ring %u\n", size);
2167                 ret = -ENOMEM;
2168                 goto out_freeirq_tx;
2169         }
2170
2171         memset(p, 0, size);
2172         priv->rx_desc_alloc_size = size;
2173         priv->rx_desc_cpu = p;
2174
2175         /* allocate tx dma ring */
2176         size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
2177         p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
2178         if (!p) {
2179                 dev_err(kdev, "cannot allocate tx ring\n");
2180                 ret = -ENOMEM;
2181                 goto out_free_rx_ring;
2182         }
2183
2184         memset(p, 0, size);
2185         priv->tx_desc_alloc_size = size;
2186         priv->tx_desc_cpu = p;
2187
2188         priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size,
2189                                GFP_KERNEL);
2190         if (!priv->tx_skb) {
2191                 dev_err(kdev, "cannot allocate rx skb queue\n");
2192                 ret = -ENOMEM;
2193                 goto out_free_tx_ring;
2194         }
2195
2196         priv->tx_desc_count = priv->tx_ring_size;
2197         priv->tx_dirty_desc = 0;
2198         priv->tx_curr_desc = 0;
2199         spin_lock_init(&priv->tx_lock);
2200
2201         /* init & fill rx ring with skbs */
2202         priv->rx_skb = kzalloc(sizeof(struct sk_buff *) * priv->rx_ring_size,
2203                                GFP_KERNEL);
2204         if (!priv->rx_skb) {
2205                 dev_err(kdev, "cannot allocate rx skb queue\n");
2206                 ret = -ENOMEM;
2207                 goto out_free_tx_skb;
2208         }
2209
2210         priv->rx_desc_count = 0;
2211         priv->rx_dirty_desc = 0;
2212         priv->rx_curr_desc = 0;
2213
2214         /* disable all ports */
2215         for (i = 0; i < priv->num_ports; i++) {
2216                 enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2217                               ENETSW_PORTOV_REG(i));
2218                 enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2219                               ENETSW_PTCTRL_TXDIS_MASK,
2220                               ENETSW_PTCTRL_REG(i));
2221
2222                 priv->sw_port_link[i] = 0;
2223         }
2224
2225         /* reset mib */
2226         val = enetsw_readb(priv, ENETSW_GMCR_REG);
2227         val |= ENETSW_GMCR_RST_MIB_MASK;
2228         enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2229         mdelay(1);
2230         val &= ~ENETSW_GMCR_RST_MIB_MASK;
2231         enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2232         mdelay(1);
2233
2234         /* force CPU port state */
2235         val = enetsw_readb(priv, ENETSW_IMPOV_REG);
2236         val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK;
2237         enetsw_writeb(priv, val, ENETSW_IMPOV_REG);
2238
2239         /* enable switch forward engine */
2240         val = enetsw_readb(priv, ENETSW_SWMODE_REG);
2241         val |= ENETSW_SWMODE_FWD_EN_MASK;
2242         enetsw_writeb(priv, val, ENETSW_SWMODE_REG);
2243
2244         /* enable jumbo on all ports */
2245         enetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG);
2246         enetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG);
2247
2248         /* initialize flow control buffer allocation */
2249         enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
2250                         ENETDMA_BUFALLOC_REG(priv->rx_chan));
2251
2252         if (bcm_enet_refill_rx(dev)) {
2253                 dev_err(kdev, "cannot allocate rx skb queue\n");
2254                 ret = -ENOMEM;
2255                 goto out;
2256         }
2257
2258         /* write rx & tx ring addresses */
2259         enet_dmas_writel(priv, priv->rx_desc_dma,
2260                          ENETDMAS_RSTART_REG, priv->rx_chan);
2261         enet_dmas_writel(priv, priv->tx_desc_dma,
2262                          ENETDMAS_RSTART_REG, priv->tx_chan);
2263
2264         /* clear remaining state ram for rx & tx channel */
2265         enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
2266         enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
2267         enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
2268         enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
2269         enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
2270         enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
2271
2272         /* set dma maximum burst len */
2273         enet_dmac_writel(priv, priv->dma_maxburst,
2274                          ENETDMAC_MAXBURST, priv->rx_chan);
2275         enet_dmac_writel(priv, priv->dma_maxburst,
2276                          ENETDMAC_MAXBURST, priv->tx_chan);
2277
2278         /* set flow control low/high threshold to 1/3 / 2/3 */
2279         val = priv->rx_ring_size / 3;
2280         enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
2281         val = (priv->rx_ring_size * 2) / 3;
2282         enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
2283
2284         /* all set, enable mac and interrupts, start dma engine and
2285          * kick rx dma channel
2286          */
2287         wmb();
2288         enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
2289         enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
2290                          ENETDMAC_CHANCFG, priv->rx_chan);
2291
2292         /* watch "packet transferred" interrupt in rx and tx */
2293         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2294                          ENETDMAC_IR, priv->rx_chan);
2295         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2296                          ENETDMAC_IR, priv->tx_chan);
2297
2298         /* make sure we enable napi before rx interrupt  */
2299         napi_enable(&priv->napi);
2300
2301         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2302                          ENETDMAC_IRMASK, priv->rx_chan);
2303         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2304                          ENETDMAC_IRMASK, priv->tx_chan);
2305
2306         netif_carrier_on(dev);
2307         netif_start_queue(dev);
2308
2309         /* apply override config for bypass_link ports here. */
2310         for (i = 0; i < priv->num_ports; i++) {
2311                 struct bcm63xx_enetsw_port *port;
2312                 u8 override;
2313                 port = &priv->used_ports[i];
2314                 if (!port->used)
2315                         continue;
2316
2317                 if (!port->bypass_link)
2318                         continue;
2319
2320                 override = ENETSW_PORTOV_ENABLE_MASK |
2321                         ENETSW_PORTOV_LINKUP_MASK;
2322
2323                 switch (port->force_speed) {
2324                 case 1000:
2325                         override |= ENETSW_IMPOV_1000_MASK;
2326                         break;
2327                 case 100:
2328                         override |= ENETSW_IMPOV_100_MASK;
2329                         break;
2330                 case 10:
2331                         break;
2332                 default:
2333                         pr_warn("invalid forced speed on port %s: assume 10\n",
2334                                port->name);
2335                         break;
2336                 }
2337
2338                 if (port->force_duplex_full)
2339                         override |= ENETSW_IMPOV_FDX_MASK;
2340
2341
2342                 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2343                 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2344         }
2345
2346         /* start phy polling timer */
2347         init_timer(&priv->swphy_poll);
2348         priv->swphy_poll.function = swphy_poll_timer;
2349         priv->swphy_poll.data = (unsigned long)priv;
2350         priv->swphy_poll.expires = jiffies;
2351         add_timer(&priv->swphy_poll);
2352         return 0;
2353
2354 out:
2355         for (i = 0; i < priv->rx_ring_size; i++) {
2356                 struct bcm_enet_desc *desc;
2357
2358                 if (!priv->rx_skb[i])
2359                         continue;
2360
2361                 desc = &priv->rx_desc_cpu[i];
2362                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2363                                  DMA_FROM_DEVICE);
2364                 kfree_skb(priv->rx_skb[i]);
2365         }
2366         kfree(priv->rx_skb);
2367
2368 out_free_tx_skb:
2369         kfree(priv->tx_skb);
2370
2371 out_free_tx_ring:
2372         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2373                           priv->tx_desc_cpu, priv->tx_desc_dma);
2374
2375 out_free_rx_ring:
2376         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2377                           priv->rx_desc_cpu, priv->rx_desc_dma);
2378
2379 out_freeirq_tx:
2380         if (priv->irq_tx != -1)
2381                 free_irq(priv->irq_tx, dev);
2382
2383 out_freeirq_rx:
2384         free_irq(priv->irq_rx, dev);
2385
2386 out_freeirq:
2387         return ret;
2388 }
2389
2390 /* stop callback */
2391 static int bcm_enetsw_stop(struct net_device *dev)
2392 {
2393         struct bcm_enet_priv *priv;
2394         struct device *kdev;
2395         int i;
2396
2397         priv = netdev_priv(dev);
2398         kdev = &priv->pdev->dev;
2399
2400         del_timer_sync(&priv->swphy_poll);
2401         netif_stop_queue(dev);
2402         napi_disable(&priv->napi);
2403         del_timer_sync(&priv->rx_timeout);
2404
2405         /* mask all interrupts */
2406         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2407         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
2408
2409         /* disable dma & mac */
2410         bcm_enet_disable_dma(priv, priv->tx_chan);
2411         bcm_enet_disable_dma(priv, priv->rx_chan);
2412
2413         /* force reclaim of all tx buffers */
2414         bcm_enet_tx_reclaim(dev, 1);
2415
2416         /* free the rx skb ring */
2417         for (i = 0; i < priv->rx_ring_size; i++) {
2418                 struct bcm_enet_desc *desc;
2419
2420                 if (!priv->rx_skb[i])
2421                         continue;
2422
2423                 desc = &priv->rx_desc_cpu[i];
2424                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2425                                  DMA_FROM_DEVICE);
2426                 kfree_skb(priv->rx_skb[i]);
2427         }
2428
2429         /* free remaining allocated memory */
2430         kfree(priv->rx_skb);
2431         kfree(priv->tx_skb);
2432         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2433                           priv->rx_desc_cpu, priv->rx_desc_dma);
2434         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2435                           priv->tx_desc_cpu, priv->tx_desc_dma);
2436         if (priv->irq_tx != -1)
2437                 free_irq(priv->irq_tx, dev);
2438         free_irq(priv->irq_rx, dev);
2439
2440         return 0;
2441 }
2442
2443 /* try to sort out phy external status by walking the used_port field
2444  * in the bcm_enet_priv structure. in case the phy address is not
2445  * assigned to any physical port on the switch, assume it is external
2446  * (and yell at the user).
2447  */
2448 static int bcm_enetsw_phy_is_external(struct bcm_enet_priv *priv, int phy_id)
2449 {
2450         int i;
2451
2452         for (i = 0; i < priv->num_ports; ++i) {
2453                 if (!priv->used_ports[i].used)
2454                         continue;
2455                 if (priv->used_ports[i].phy_id == phy_id)
2456                         return bcm_enet_port_is_rgmii(i);
2457         }
2458
2459         printk_once(KERN_WARNING  "bcm63xx_enet: could not find a used port with phy_id %i, assuming phy is external\n",
2460                     phy_id);
2461         return 1;
2462 }
2463
2464 /* can't use bcmenet_sw_mdio_read directly as we need to sort out
2465  * external/internal status of the given phy_id first.
2466  */
2467 static int bcm_enetsw_mii_mdio_read(struct net_device *dev, int phy_id,
2468                                     int location)
2469 {
2470         struct bcm_enet_priv *priv;
2471
2472         priv = netdev_priv(dev);
2473         return bcmenet_sw_mdio_read(priv,
2474                                     bcm_enetsw_phy_is_external(priv, phy_id),
2475                                     phy_id, location);
2476 }
2477
2478 /* can't use bcmenet_sw_mdio_write directly as we need to sort out
2479  * external/internal status of the given phy_id first.
2480  */
2481 static void bcm_enetsw_mii_mdio_write(struct net_device *dev, int phy_id,
2482                                       int location,
2483                                       int val)
2484 {
2485         struct bcm_enet_priv *priv;
2486
2487         priv = netdev_priv(dev);
2488         bcmenet_sw_mdio_write(priv, bcm_enetsw_phy_is_external(priv, phy_id),
2489                               phy_id, location, val);
2490 }
2491
2492 static int bcm_enetsw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2493 {
2494         struct mii_if_info mii;
2495
2496         mii.dev = dev;
2497         mii.mdio_read = bcm_enetsw_mii_mdio_read;
2498         mii.mdio_write = bcm_enetsw_mii_mdio_write;
2499         mii.phy_id = 0;
2500         mii.phy_id_mask = 0x3f;
2501         mii.reg_num_mask = 0x1f;
2502         return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
2503
2504 }
2505
2506 static const struct net_device_ops bcm_enetsw_ops = {
2507         .ndo_open               = bcm_enetsw_open,
2508         .ndo_stop               = bcm_enetsw_stop,
2509         .ndo_start_xmit         = bcm_enet_start_xmit,
2510         .ndo_change_mtu         = bcm_enet_change_mtu,
2511         .ndo_do_ioctl           = bcm_enetsw_ioctl,
2512 };
2513
2514
2515 static const struct bcm_enet_stats bcm_enetsw_gstrings_stats[] = {
2516         { "rx_packets", DEV_STAT(rx_packets), -1 },
2517         { "tx_packets", DEV_STAT(tx_packets), -1 },
2518         { "rx_bytes", DEV_STAT(rx_bytes), -1 },
2519         { "tx_bytes", DEV_STAT(tx_bytes), -1 },
2520         { "rx_errors", DEV_STAT(rx_errors), -1 },
2521         { "tx_errors", DEV_STAT(tx_errors), -1 },
2522         { "rx_dropped", DEV_STAT(rx_dropped), -1 },
2523         { "tx_dropped", DEV_STAT(tx_dropped), -1 },
2524
2525         { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETHSW_MIB_RX_GD_OCT },
2526         { "tx_unicast", GEN_STAT(mib.tx_unicast), ETHSW_MIB_RX_BRDCAST },
2527         { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETHSW_MIB_RX_BRDCAST },
2528         { "tx_multicast", GEN_STAT(mib.tx_mult), ETHSW_MIB_RX_MULT },
2529         { "tx_64_octets", GEN_STAT(mib.tx_64), ETHSW_MIB_RX_64 },
2530         { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETHSW_MIB_RX_65_127 },
2531         { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETHSW_MIB_RX_128_255 },
2532         { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETHSW_MIB_RX_256_511 },
2533         { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETHSW_MIB_RX_512_1023},
2534         { "tx_1024_1522_oct", GEN_STAT(mib.tx_1024_max),
2535           ETHSW_MIB_RX_1024_1522 },
2536         { "tx_1523_2047_oct", GEN_STAT(mib.tx_1523_2047),
2537           ETHSW_MIB_RX_1523_2047 },
2538         { "tx_2048_4095_oct", GEN_STAT(mib.tx_2048_4095),
2539           ETHSW_MIB_RX_2048_4095 },
2540         { "tx_4096_8191_oct", GEN_STAT(mib.tx_4096_8191),
2541           ETHSW_MIB_RX_4096_8191 },
2542         { "tx_8192_9728_oct", GEN_STAT(mib.tx_8192_9728),
2543           ETHSW_MIB_RX_8192_9728 },
2544         { "tx_oversize", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR },
2545         { "tx_oversize_drop", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR_DISC },
2546         { "tx_dropped", GEN_STAT(mib.tx_drop), ETHSW_MIB_RX_DROP },
2547         { "tx_undersize", GEN_STAT(mib.tx_underrun), ETHSW_MIB_RX_UND },
2548         { "tx_pause", GEN_STAT(mib.tx_pause), ETHSW_MIB_RX_PAUSE },
2549
2550         { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETHSW_MIB_TX_ALL_OCT },
2551         { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETHSW_MIB_TX_BRDCAST },
2552         { "rx_multicast", GEN_STAT(mib.rx_mult), ETHSW_MIB_TX_MULT },
2553         { "rx_unicast", GEN_STAT(mib.rx_unicast), ETHSW_MIB_TX_MULT },
2554         { "rx_pause", GEN_STAT(mib.rx_pause), ETHSW_MIB_TX_PAUSE },
2555         { "rx_dropped", GEN_STAT(mib.rx_drop), ETHSW_MIB_TX_DROP_PKTS },
2556
2557 };
2558
2559 #define BCM_ENETSW_STATS_LEN    \
2560         (sizeof(bcm_enetsw_gstrings_stats) / sizeof(struct bcm_enet_stats))
2561
2562 static void bcm_enetsw_get_strings(struct net_device *netdev,
2563                                    u32 stringset, u8 *data)
2564 {
2565         int i;
2566
2567         switch (stringset) {
2568         case ETH_SS_STATS:
2569                 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2570                         memcpy(data + i * ETH_GSTRING_LEN,
2571                                bcm_enetsw_gstrings_stats[i].stat_string,
2572                                ETH_GSTRING_LEN);
2573                 }
2574                 break;
2575         }
2576 }
2577
2578 static int bcm_enetsw_get_sset_count(struct net_device *netdev,
2579                                      int string_set)
2580 {
2581         switch (string_set) {
2582         case ETH_SS_STATS:
2583                 return BCM_ENETSW_STATS_LEN;
2584         default:
2585                 return -EINVAL;
2586         }
2587 }
2588
2589 static void bcm_enetsw_get_drvinfo(struct net_device *netdev,
2590                                    struct ethtool_drvinfo *drvinfo)
2591 {
2592         strncpy(drvinfo->driver, bcm_enet_driver_name, 32);
2593         strncpy(drvinfo->version, bcm_enet_driver_version, 32);
2594         strncpy(drvinfo->fw_version, "N/A", 32);
2595         strncpy(drvinfo->bus_info, "bcm63xx", 32);
2596 }
2597
2598 static void bcm_enetsw_get_ethtool_stats(struct net_device *netdev,
2599                                          struct ethtool_stats *stats,
2600                                          u64 *data)
2601 {
2602         struct bcm_enet_priv *priv;
2603         int i;
2604
2605         priv = netdev_priv(netdev);
2606
2607         for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2608                 const struct bcm_enet_stats *s;
2609                 u32 lo, hi;
2610                 char *p;
2611                 int reg;
2612
2613                 s = &bcm_enetsw_gstrings_stats[i];
2614
2615                 reg = s->mib_reg;
2616                 if (reg == -1)
2617                         continue;
2618
2619                 lo = enetsw_readl(priv, ENETSW_MIB_REG(reg));
2620                 p = (char *)priv + s->stat_offset;
2621
2622                 if (s->sizeof_stat == sizeof(u64)) {
2623                         hi = enetsw_readl(priv, ENETSW_MIB_REG(reg + 1));
2624                         *(u64 *)p = ((u64)hi << 32 | lo);
2625                 } else {
2626                         *(u32 *)p = lo;
2627                 }
2628         }
2629
2630         for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2631                 const struct bcm_enet_stats *s;
2632                 char *p;
2633
2634                 s = &bcm_enetsw_gstrings_stats[i];
2635
2636                 if (s->mib_reg == -1)
2637                         p = (char *)&netdev->stats + s->stat_offset;
2638                 else
2639                         p = (char *)priv + s->stat_offset;
2640
2641                 data[i] = (s->sizeof_stat == sizeof(u64)) ?
2642                         *(u64 *)p : *(u32 *)p;
2643         }
2644 }
2645
2646 static void bcm_enetsw_get_ringparam(struct net_device *dev,
2647                                      struct ethtool_ringparam *ering)
2648 {
2649         struct bcm_enet_priv *priv;
2650
2651         priv = netdev_priv(dev);
2652
2653         /* rx/tx ring is actually only limited by memory */
2654         ering->rx_max_pending = 8192;
2655         ering->tx_max_pending = 8192;
2656         ering->rx_mini_max_pending = 0;
2657         ering->rx_jumbo_max_pending = 0;
2658         ering->rx_pending = priv->rx_ring_size;
2659         ering->tx_pending = priv->tx_ring_size;
2660 }
2661
2662 static int bcm_enetsw_set_ringparam(struct net_device *dev,
2663                                     struct ethtool_ringparam *ering)
2664 {
2665         struct bcm_enet_priv *priv;
2666         int was_running;
2667
2668         priv = netdev_priv(dev);
2669
2670         was_running = 0;
2671         if (netif_running(dev)) {
2672                 bcm_enetsw_stop(dev);
2673                 was_running = 1;
2674         }
2675
2676         priv->rx_ring_size = ering->rx_pending;
2677         priv->tx_ring_size = ering->tx_pending;
2678
2679         if (was_running) {
2680                 int err;
2681
2682                 err = bcm_enetsw_open(dev);
2683                 if (err)
2684                         dev_close(dev);
2685         }
2686         return 0;
2687 }
2688
2689 static struct ethtool_ops bcm_enetsw_ethtool_ops = {
2690         .get_strings            = bcm_enetsw_get_strings,
2691         .get_sset_count         = bcm_enetsw_get_sset_count,
2692         .get_ethtool_stats      = bcm_enetsw_get_ethtool_stats,
2693         .get_drvinfo            = bcm_enetsw_get_drvinfo,
2694         .get_ringparam          = bcm_enetsw_get_ringparam,
2695         .set_ringparam          = bcm_enetsw_set_ringparam,
2696 };
2697
2698 /* allocate netdevice, request register memory and register device. */
2699 static int bcm_enetsw_probe(struct platform_device *pdev)
2700 {
2701         struct bcm_enet_priv *priv;
2702         struct net_device *dev;
2703         struct bcm63xx_enetsw_platform_data *pd;
2704         struct resource *res_mem;
2705         int ret, irq_rx, irq_tx;
2706
2707         /* stop if shared driver failed, assume driver->probe will be
2708          * called in the same order we register devices (correct ?)
2709          */
2710         if (!bcm_enet_shared_base[0])
2711                 return -ENODEV;
2712
2713         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2714         irq_rx = platform_get_irq(pdev, 0);
2715         irq_tx = platform_get_irq(pdev, 1);
2716         if (!res_mem || irq_rx < 0)
2717                 return -ENODEV;
2718
2719         ret = 0;
2720         dev = alloc_etherdev(sizeof(*priv));
2721         if (!dev)
2722                 return -ENOMEM;
2723         priv = netdev_priv(dev);
2724         memset(priv, 0, sizeof(*priv));
2725
2726         /* initialize default and fetch platform data */
2727         priv->enet_is_sw = true;
2728         priv->irq_rx = irq_rx;
2729         priv->irq_tx = irq_tx;
2730         priv->rx_ring_size = BCMENET_DEF_RX_DESC;
2731         priv->tx_ring_size = BCMENET_DEF_TX_DESC;
2732         priv->dma_maxburst = BCMENETSW_DMA_MAXBURST;
2733
2734         pd = dev_get_platdata(&pdev->dev);
2735         if (pd) {
2736                 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2737                 memcpy(priv->used_ports, pd->used_ports,
2738                        sizeof(pd->used_ports));
2739                 priv->num_ports = pd->num_ports;
2740                 priv->dma_has_sram = pd->dma_has_sram;
2741                 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
2742                 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
2743                 priv->dma_chan_width = pd->dma_chan_width;
2744         }
2745
2746         ret = compute_hw_mtu(priv, dev->mtu);
2747         if (ret)
2748                 goto out;
2749
2750         if (!request_mem_region(res_mem->start, resource_size(res_mem),
2751                                 "bcm63xx_enetsw")) {
2752                 ret = -EBUSY;
2753                 goto out;
2754         }
2755
2756         priv->base = ioremap(res_mem->start, resource_size(res_mem));
2757         if (priv->base == NULL) {
2758                 ret = -ENOMEM;
2759                 goto out_release_mem;
2760         }
2761
2762         priv->mac_clk = clk_get(&pdev->dev, "enetsw");
2763         if (IS_ERR(priv->mac_clk)) {
2764                 ret = PTR_ERR(priv->mac_clk);
2765                 goto out_unmap;
2766         }
2767         clk_enable(priv->mac_clk);
2768
2769         priv->rx_chan = 0;
2770         priv->tx_chan = 1;
2771         spin_lock_init(&priv->rx_lock);
2772
2773         /* init rx timeout (used for oom) */
2774         init_timer(&priv->rx_timeout);
2775         priv->rx_timeout.function = bcm_enet_refill_rx_timer;
2776         priv->rx_timeout.data = (unsigned long)dev;
2777
2778         /* register netdevice */
2779         dev->netdev_ops = &bcm_enetsw_ops;
2780         netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
2781         dev->ethtool_ops = &bcm_enetsw_ethtool_ops;
2782         SET_NETDEV_DEV(dev, &pdev->dev);
2783
2784         spin_lock_init(&priv->enetsw_mdio_lock);
2785
2786         ret = register_netdev(dev);
2787         if (ret)
2788                 goto out_put_clk;
2789
2790         netif_carrier_off(dev);
2791         platform_set_drvdata(pdev, dev);
2792         priv->pdev = pdev;
2793         priv->net_dev = dev;
2794
2795         return 0;
2796
2797 out_put_clk:
2798         clk_put(priv->mac_clk);
2799
2800 out_unmap:
2801         iounmap(priv->base);
2802
2803 out_release_mem:
2804         release_mem_region(res_mem->start, resource_size(res_mem));
2805 out:
2806         free_netdev(dev);
2807         return ret;
2808 }
2809
2810
2811 /* exit func, stops hardware and unregisters netdevice */
2812 static int bcm_enetsw_remove(struct platform_device *pdev)
2813 {
2814         struct bcm_enet_priv *priv;
2815         struct net_device *dev;
2816         struct resource *res;
2817
2818         /* stop netdevice */
2819         dev = platform_get_drvdata(pdev);
2820         priv = netdev_priv(dev);
2821         unregister_netdev(dev);
2822
2823         /* release device resources */
2824         iounmap(priv->base);
2825         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2826         release_mem_region(res->start, resource_size(res));
2827
2828         free_netdev(dev);
2829         return 0;
2830 }
2831
2832 struct platform_driver bcm63xx_enetsw_driver = {
2833         .probe  = bcm_enetsw_probe,
2834         .remove = bcm_enetsw_remove,
2835         .driver = {
2836                 .name   = "bcm63xx_enetsw",
2837                 .owner  = THIS_MODULE,
2838         },
2839 };
2840
2841 /* reserve & remap memory space shared between all macs */
2842 static int bcm_enet_shared_probe(struct platform_device *pdev)
2843 {
2844         struct resource *res;
2845         void __iomem *p[3];
2846         unsigned int i;
2847
2848         memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base));
2849
2850         for (i = 0; i < 3; i++) {
2851                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
2852                 p[i] = devm_ioremap_resource(&pdev->dev, res);
2853                 if (IS_ERR(p[i]))
2854                         return PTR_ERR(p[i]);
2855         }
2856
2857         memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base));
2858
2859         return 0;
2860 }
2861
2862 static int bcm_enet_shared_remove(struct platform_device *pdev)
2863 {
2864         return 0;
2865 }
2866
2867 /* this "shared" driver is needed because both macs share a single
2868  * address space
2869  */
2870 struct platform_driver bcm63xx_enet_shared_driver = {
2871         .probe  = bcm_enet_shared_probe,
2872         .remove = bcm_enet_shared_remove,
2873         .driver = {
2874                 .name   = "bcm63xx_enet_shared",
2875                 .owner  = THIS_MODULE,
2876         },
2877 };
2878
2879 static struct platform_driver * const drivers[] = {
2880         &bcm63xx_enet_shared_driver,
2881         &bcm63xx_enet_driver,
2882         &bcm63xx_enetsw_driver,
2883 };
2884
2885 /* entry point */
2886 static int __init bcm_enet_init(void)
2887 {
2888         return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
2889 }
2890
2891 static void __exit bcm_enet_exit(void)
2892 {
2893         platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
2894 }
2895
2896
2897 module_init(bcm_enet_init);
2898 module_exit(bcm_enet_exit);
2899
2900 MODULE_DESCRIPTION("BCM63xx internal ethernet mac driver");
2901 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
2902 MODULE_LICENSE("GPL");