drivers/net/ethernet/broadcom/bcm63xx_enet.c

   1 /*
   2  * Driver for BCM963xx builtin Ethernet mac
   3  *
   4  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/module.h>
  23 #include <linux/clk.h>
  24 #include <linux/etherdevice.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/ethtool.h>
  28 #include <linux/crc32.h>
  29 #include <linux/err.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/if_vlan.h>
  33
  34 #include <bcm63xx_dev_enet.h>
  35 #include "bcm63xx_enet.h"
  36
  37 static char bcm_enet_driver_name[] = "bcm63xx_enet";
  38 static char bcm_enet_driver_version[] = "1.0";
  39
  40 static int copybreak __read_mostly = 128;
  41 module_param(copybreak, int, 0);
  42 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
  43
  44 /* io registers memory shared between all devices */
  45 static void __iomem *bcm_enet_shared_base[3];
  46
  47 /*
  48  * io helpers to access mac registers
  49  */
  50 static inline u32 enet_readl(struct bcm_enet_priv *priv, u32 off)
  51 {
  52         return bcm_readl(priv->base + off);
  53 }
  54
  55 static inline void enet_writel(struct bcm_enet_priv *priv,
  56                                u32 val, u32 off)
  57 {
  58         bcm_writel(val, priv->base + off);
  59 }
  60
  61 /*
  62  * io helpers to access switch registers
  63  */
  64 static inline u32 enetsw_readl(struct bcm_enet_priv *priv, u32 off)
  65 {
  66         return bcm_readl(priv->base + off);
  67 }
  68
  69 static inline void enetsw_writel(struct bcm_enet_priv *priv,
  70                                  u32 val, u32 off)
  71 {
  72         bcm_writel(val, priv->base + off);
  73 }
  74
  75 static inline u16 enetsw_readw(struct bcm_enet_priv *priv, u32 off)
  76 {
  77         return bcm_readw(priv->base + off);
  78 }
  79
  80 static inline void enetsw_writew(struct bcm_enet_priv *priv,
  81                                  u16 val, u32 off)
  82 {
  83         bcm_writew(val, priv->base + off);
  84 }
  85
  86 static inline u8 enetsw_readb(struct bcm_enet_priv *priv, u32 off)
  87 {
  88         return bcm_readb(priv->base + off);
  89 }
  90
  91 static inline void enetsw_writeb(struct bcm_enet_priv *priv,
  92                                  u8 val, u32 off)
  93 {
  94         bcm_writeb(val, priv->base + off);
  95 }
  96
  97
  98 /* io helpers to access shared registers */
  99 static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
 100 {
 101         return bcm_readl(bcm_enet_shared_base[0] + off);
 102 }
 103
 104 static inline void enet_dma_writel(struct bcm_enet_priv *priv,
 105                                        u32 val, u32 off)
 106 {
 107         bcm_writel(val, bcm_enet_shared_base[0] + off);
 108 }
 109
 110 static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off, int chan)
 111 {
 112         return bcm_readl(bcm_enet_shared_base[1] +
 113                 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
 114 }
 115
 116 static inline void enet_dmac_writel(struct bcm_enet_priv *priv,
 117                                        u32 val, u32 off, int chan)
 118 {
 119         bcm_writel(val, bcm_enet_shared_base[1] +
 120                 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
 121 }
 122
 123 static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off, int chan)
 124 {
 125         return bcm_readl(bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
 126 }
 127
 128 static inline void enet_dmas_writel(struct bcm_enet_priv *priv,
 129                                        u32 val, u32 off, int chan)
 130 {
 131         bcm_writel(val, bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
 132 }
 133
 134 /*
 135  * write given data into mii register and wait for transfer to end
 136  * with timeout (average measured transfer time is 25us)
 137  */
 138 static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data)
 139 {
 140         int limit;
 141
 142         /* make sure mii interrupt status is cleared */
 143         enet_writel(priv, ENET_IR_MII, ENET_IR_REG);
 144
 145         enet_writel(priv, data, ENET_MIIDATA_REG);
 146         wmb();
 147
 148         /* busy wait on mii interrupt bit, with timeout */
 149         limit = 1000;
 150         do {
 151                 if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII)
 152                         break;
 153                 udelay(1);
 154         } while (limit-- > 0);
 155
 156         return (limit < 0) ? 1 : 0;
 157 }
 158
 159 /*
 160  * MII internal read callback
 161  */
 162 static int bcm_enet_mdio_read(struct bcm_enet_priv *priv, int mii_id,
 163                               int regnum)
 164 {
 165         u32 tmp, val;
 166
 167         tmp = regnum << ENET_MIIDATA_REG_SHIFT;
 168         tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
 169         tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
 170         tmp |= ENET_MIIDATA_OP_READ_MASK;
 171
 172         if (do_mdio_op(priv, tmp))
 173                 return -1;
 174
 175         val = enet_readl(priv, ENET_MIIDATA_REG);
 176         val &= 0xffff;
 177         return val;
 178 }
 179
 180 /*
 181  * MII internal write callback
 182  */
 183 static int bcm_enet_mdio_write(struct bcm_enet_priv *priv, int mii_id,
 184                                int regnum, u16 value)
 185 {
 186         u32 tmp;
 187
 188         tmp = (value & 0xffff) << ENET_MIIDATA_DATA_SHIFT;
 189         tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
 190         tmp |= regnum << ENET_MIIDATA_REG_SHIFT;
 191         tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
 192         tmp |= ENET_MIIDATA_OP_WRITE_MASK;
 193
 194         (void)do_mdio_op(priv, tmp);
 195         return 0;
 196 }
 197
 198 /*
 199  * MII read callback from phylib
 200  */
 201 static int bcm_enet_mdio_read_phylib(struct mii_bus *bus, int mii_id,
 202                                      int regnum)
 203 {
 204         return bcm_enet_mdio_read(bus->priv, mii_id, regnum);
 205 }
 206
 207 /*
 208  * MII write callback from phylib
 209  */
 210 static int bcm_enet_mdio_write_phylib(struct mii_bus *bus, int mii_id,
 211                                       int regnum, u16 value)
 212 {
 213         return bcm_enet_mdio_write(bus->priv, mii_id, regnum, value);
 214 }
 215
 216 /*
 217  * MII read callback from mii core
 218  */
 219 static int bcm_enet_mdio_read_mii(struct net_device *dev, int mii_id,
 220                                   int regnum)
 221 {
 222         return bcm_enet_mdio_read(netdev_priv(dev), mii_id, regnum);
 223 }
 224
 225 /*
 226  * MII write callback from mii core
 227  */
 228 static void bcm_enet_mdio_write_mii(struct net_device *dev, int mii_id,
 229                                     int regnum, int value)
 230 {
 231         bcm_enet_mdio_write(netdev_priv(dev), mii_id, regnum, value);
 232 }
 233
 234 /*
 235  * refill rx queue
 236  */
 237 static int bcm_enet_refill_rx(struct net_device *dev)
 238 {
 239         struct bcm_enet_priv *priv;
 240
 241         priv = netdev_priv(dev);
 242
 243         while (priv->rx_desc_count < priv->rx_ring_size) {
 244                 struct bcm_enet_desc *desc;
 245                 struct sk_buff *skb;
 246                 dma_addr_t p;
 247                 int desc_idx;
 248                 u32 len_stat;
 249
 250                 desc_idx = priv->rx_dirty_desc;
 251                 desc = &priv->rx_desc_cpu[desc_idx];
 252
 253                 if (!priv->rx_skb[desc_idx]) {
 254                         skb = netdev_alloc_skb(dev, priv->rx_skb_size);
 255                         if (!skb)
 256                                 break;
 257                         priv->rx_skb[desc_idx] = skb;
 258                         p = dma_map_single(&priv->pdev->dev, skb->data,
 259                                            priv->rx_skb_size,
 260                                            DMA_FROM_DEVICE);
 261                         desc->address = p;
 262                 }
 263
 264                 len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
 265                 len_stat |= DMADESC_OWNER_MASK;
 266                 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
 267                         len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
 268                         priv->rx_dirty_desc = 0;
 269                 } else {
 270                         priv->rx_dirty_desc++;
 271                 }
 272                 wmb();
 273                 desc->len_stat = len_stat;
 274
 275                 priv->rx_desc_count++;
 276
 277                 /* tell dma engine we allocated one buffer */
 278                 if (priv->dma_has_sram)
 279                         enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
 280                 else
 281                         enet_dmac_writel(priv, 1, ENETDMAC_BUFALLOC, priv->rx_chan);
 282         }
 283
 284         /* If rx ring is still empty, set a timer to try allocating
 285          * again at a later time. */
 286         if (priv->rx_desc_count == 0 && netif_running(dev)) {
 287                 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n");
 288                 priv->rx_timeout.expires = jiffies + HZ;
 289                 add_timer(&priv->rx_timeout);
 290         }
 291
 292         return 0;
 293 }
 294
 295 /*
 296  * timer callback to defer refill rx queue in case we're OOM
 297  */
 298 static void bcm_enet_refill_rx_timer(unsigned long data)
 299 {
 300         struct net_device *dev;
 301         struct bcm_enet_priv *priv;
 302
 303         dev = (struct net_device *)data;
 304         priv = netdev_priv(dev);
 305
 306         spin_lock(&priv->rx_lock);
 307         bcm_enet_refill_rx((struct net_device *)data);
 308         spin_unlock(&priv->rx_lock);
 309 }
 310
 311 /*
 312  * extract packet from rx queue
 313  */
 314 static int bcm_enet_receive_queue(struct net_device *dev, int budget)
 315 {
 316         struct bcm_enet_priv *priv;
 317         struct device *kdev;
 318         int processed;
 319
 320         priv = netdev_priv(dev);
 321         kdev = &priv->pdev->dev;
 322         processed = 0;
 323
 324         /* don't scan ring further than number of refilled
 325          * descriptor */
 326         if (budget > priv->rx_desc_count)
 327                 budget = priv->rx_desc_count;
 328
 329         do {
 330                 struct bcm_enet_desc *desc;
 331                 struct sk_buff *skb;
 332                 int desc_idx;
 333                 u32 len_stat;
 334                 unsigned int len;
 335
 336                 desc_idx = priv->rx_curr_desc;
 337                 desc = &priv->rx_desc_cpu[desc_idx];
 338
 339                 /* make sure we actually read the descriptor status at
 340                  * each loop */
 341                 rmb();
 342
 343                 len_stat = desc->len_stat;
 344
 345                 /* break if dma ownership belongs to hw */
 346                 if (len_stat & DMADESC_OWNER_MASK)
 347                         break;
 348
 349                 processed++;
 350                 priv->rx_curr_desc++;
 351                 if (priv->rx_curr_desc == priv->rx_ring_size)
 352                         priv->rx_curr_desc = 0;
 353                 priv->rx_desc_count--;
 354
 355                 /* if the packet does not have start of packet _and_
 356                  * end of packet flag set, then just recycle it */
 357                 if ((len_stat & (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) !=
 358                         (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) {
 359                         dev->stats.rx_dropped++;
 360                         continue;
 361                 }
 362
 363                 /* recycle packet if it's marked as bad */
 364                 if (!priv->enet_is_sw &&
 365                     unlikely(len_stat & DMADESC_ERR_MASK)) {
 366                         dev->stats.rx_errors++;
 367
 368                         if (len_stat & DMADESC_OVSIZE_MASK)
 369                                 dev->stats.rx_length_errors++;
 370                         if (len_stat & DMADESC_CRC_MASK)
 371                                 dev->stats.rx_crc_errors++;
 372                         if (len_stat & DMADESC_UNDER_MASK)
 373                                 dev->stats.rx_frame_errors++;
 374                         if (len_stat & DMADESC_OV_MASK)
 375                                 dev->stats.rx_fifo_errors++;
 376                         continue;
 377                 }
 378
 379                 /* valid packet */
 380                 skb = priv->rx_skb[desc_idx];
 381                 len = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT;
 382                 /* don't include FCS */
 383                 len -= 4;
 384
 385                 if (len < copybreak) {
 386                         struct sk_buff *nskb;
 387
 388                         nskb = napi_alloc_skb(&priv->napi, len);
 389                         if (!nskb) {
 390                                 /* forget packet, just rearm desc */
 391                                 dev->stats.rx_dropped++;
 392                                 continue;
 393                         }
 394
 395                         dma_sync_single_for_cpu(kdev, desc->address,
 396                                                 len, DMA_FROM_DEVICE);
 397                         memcpy(nskb->data, skb->data, len);
 398                         dma_sync_single_for_device(kdev, desc->address,
 399                                                    len, DMA_FROM_DEVICE);
 400                         skb = nskb;
 401                 } else {
 402                         dma_unmap_single(&priv->pdev->dev, desc->address,
 403                                          priv->rx_skb_size, DMA_FROM_DEVICE);
 404                         priv->rx_skb[desc_idx] = NULL;
 405                 }
 406
 407                 skb_put(skb, len);
 408                 skb->protocol = eth_type_trans(skb, dev);
 409                 dev->stats.rx_packets++;
 410                 dev->stats.rx_bytes += len;
 411                 netif_receive_skb(skb);
 412
 413         } while (--budget > 0);
 414
 415         if (processed || !priv->rx_desc_count) {
 416                 bcm_enet_refill_rx(dev);
 417
 418                 /* kick rx dma */
 419                 enet_dmac_writel(priv, priv->dma_chan_en_mask,
 420                                          ENETDMAC_CHANCFG, priv->rx_chan);
 421         }
 422
 423         return processed;
 424 }
 425
 426
 427 /*
 428  * try to or force reclaim of transmitted buffers
 429  */
 430 static int bcm_enet_tx_reclaim(struct net_device *dev, int force)
 431 {
 432         struct bcm_enet_priv *priv;
 433         int released;
 434
 435         priv = netdev_priv(dev);
 436         released = 0;
 437
 438         while (priv->tx_desc_count < priv->tx_ring_size) {
 439                 struct bcm_enet_desc *desc;
 440                 struct sk_buff *skb;
 441
 442                 /* We run in a bh and fight against start_xmit, which
 443                  * is called with bh disabled  */
 444                 spin_lock(&priv->tx_lock);
 445
 446                 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc];
 447
 448                 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {
 449                         spin_unlock(&priv->tx_lock);
 450                         break;
 451                 }
 452
 453                 /* ensure other field of the descriptor were not read
 454                  * before we checked ownership */
 455                 rmb();
 456
 457                 skb = priv->tx_skb[priv->tx_dirty_desc];
 458                 priv->tx_skb[priv->tx_dirty_desc] = NULL;
 459                 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len,
 460                                  DMA_TO_DEVICE);
 461
 462                 priv->tx_dirty_desc++;
 463                 if (priv->tx_dirty_desc == priv->tx_ring_size)
 464                         priv->tx_dirty_desc = 0;
 465                 priv->tx_desc_count++;
 466
 467                 spin_unlock(&priv->tx_lock);
 468
 469                 if (desc->len_stat & DMADESC_UNDER_MASK)
 470                         dev->stats.tx_errors++;
 471
 472                 dev_kfree_skb(skb);
 473                 released++;
 474         }
 475
 476         if (netif_queue_stopped(dev) && released)
 477                 netif_wake_queue(dev);
 478
 479         return released;
 480 }
 481
 482 /*
 483  * poll func, called by network core
 484  */
 485 static int bcm_enet_poll(struct napi_struct *napi, int budget)
 486 {
 487         struct bcm_enet_priv *priv;
 488         struct net_device *dev;
 489         int rx_work_done;
 490
 491         priv = container_of(napi, struct bcm_enet_priv, napi);
 492         dev = priv->net_dev;
 493
 494         /* ack interrupts */
 495         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 496                          ENETDMAC_IR, priv->rx_chan);
 497         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 498                          ENETDMAC_IR, priv->tx_chan);
 499
 500         /* reclaim sent skb */
 501         bcm_enet_tx_reclaim(dev, 0);
 502
 503         spin_lock(&priv->rx_lock);
 504         rx_work_done = bcm_enet_receive_queue(dev, budget);
 505         spin_unlock(&priv->rx_lock);
 506
 507         if (rx_work_done >= budget) {
 508                 /* rx queue is not yet empty/clean */
 509                 return rx_work_done;
 510         }
 511
 512         /* no more packet in rx/tx queue, remove device from poll
 513          * queue */
 514         napi_complete(napi);
 515
 516         /* restore rx/tx interrupt */
 517         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 518                          ENETDMAC_IRMASK, priv->rx_chan);
 519         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 520                          ENETDMAC_IRMASK, priv->tx_chan);
 521
 522         return rx_work_done;
 523 }
 524
 525 /*
 526  * mac interrupt handler
 527  */
 528 static irqreturn_t bcm_enet_isr_mac(int irq, void *dev_id)
 529 {
 530         struct net_device *dev;
 531         struct bcm_enet_priv *priv;
 532         u32 stat;
 533
 534         dev = dev_id;
 535         priv = netdev_priv(dev);
 536
 537         stat = enet_readl(priv, ENET_IR_REG);
 538         if (!(stat & ENET_IR_MIB))
 539                 return IRQ_NONE;
 540
 541         /* clear & mask interrupt */
 542         enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
 543         enet_writel(priv, 0, ENET_IRMASK_REG);
 544
 545         /* read mib registers in workqueue */
 546         schedule_work(&priv->mib_update_task);
 547
 548         return IRQ_HANDLED;
 549 }
 550
 551 /*
 552  * rx/tx dma interrupt handler
 553  */
 554 static irqreturn_t bcm_enet_isr_dma(int irq, void *dev_id)
 555 {
 556         struct net_device *dev;
 557         struct bcm_enet_priv *priv;
 558
 559         dev = dev_id;
 560         priv = netdev_priv(dev);
 561
 562         /* mask rx/tx interrupts */
 563         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 564         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 565
 566         napi_schedule(&priv->napi);
 567
 568         return IRQ_HANDLED;
 569 }
 570
 571 /*
 572  * tx request callback
 573  */
 574 static int bcm_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
 575 {
 576         struct bcm_enet_priv *priv;
 577         struct bcm_enet_desc *desc;
 578         u32 len_stat;
 579         int ret;
 580
 581         priv = netdev_priv(dev);
 582
 583         /* lock against tx reclaim */
 584         spin_lock(&priv->tx_lock);
 585
 586         /* make sure  the tx hw queue  is not full,  should not happen
 587          * since we stop queue before it's the case */
 588         if (unlikely(!priv->tx_desc_count)) {
 589                 netif_stop_queue(dev);
 590                 dev_err(&priv->pdev->dev, "xmit called with no tx desc "
 591                         "available?\n");
 592                 ret = NETDEV_TX_BUSY;
 593                 goto out_unlock;
 594         }
 595
 596         /* pad small packets sent on a switch device */
 597         if (priv->enet_is_sw && skb->len < 64) {
 598                 int needed = 64 - skb->len;
 599                 char *data;
 600
 601                 if (unlikely(skb_tailroom(skb) < needed)) {
 602                         struct sk_buff *nskb;
 603
 604                         nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC);
 605                         if (!nskb) {
 606                                 ret = NETDEV_TX_BUSY;
 607                                 goto out_unlock;
 608                         }
 609                         dev_kfree_skb(skb);
 610                         skb = nskb;
 611                 }
 612                 data = skb_put(skb, needed);
 613                 memset(data, 0, needed);
 614         }
 615
 616         /* point to the next available desc */
 617         desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
 618         priv->tx_skb[priv->tx_curr_desc] = skb;
 619
 620         /* fill descriptor */
 621         desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
 622                                        DMA_TO_DEVICE);
 623
 624         len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
 625         len_stat |= (DMADESC_ESOP_MASK >> priv->dma_desc_shift) |
 626                 DMADESC_APPEND_CRC |
 627                 DMADESC_OWNER_MASK;
 628
 629         priv->tx_curr_desc++;
 630         if (priv->tx_curr_desc == priv->tx_ring_size) {
 631                 priv->tx_curr_desc = 0;
 632                 len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
 633         }
 634         priv->tx_desc_count--;
 635
 636         /* dma might be already polling, make sure we update desc
 637          * fields in correct order */
 638         wmb();
 639         desc->len_stat = len_stat;
 640         wmb();
 641
 642         /* kick tx dma */
 643         enet_dmac_writel(priv, priv->dma_chan_en_mask,
 644                                  ENETDMAC_CHANCFG, priv->tx_chan);
 645
 646         /* stop queue if no more desc available */
 647         if (!priv->tx_desc_count)
 648                 netif_stop_queue(dev);
 649
 650         dev->stats.tx_bytes += skb->len;
 651         dev->stats.tx_packets++;
 652         ret = NETDEV_TX_OK;
 653
 654 out_unlock:
 655         spin_unlock(&priv->tx_lock);
 656         return ret;
 657 }
 658
 659 /*
 660  * Change the interface's mac address.
 661  */
 662 static int bcm_enet_set_mac_address(struct net_device *dev, void *p)
 663 {
 664         struct bcm_enet_priv *priv;
 665         struct sockaddr *addr = p;
 666         u32 val;
 667
 668         priv = netdev_priv(dev);
 669         memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
 670
 671         /* use perfect match register 0 to store my mac address */
 672         val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) |
 673                 (dev->dev_addr[4] << 8) | dev->dev_addr[5];
 674         enet_writel(priv, val, ENET_PML_REG(0));
 675
 676         val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]);
 677         val |= ENET_PMH_DATAVALID_MASK;
 678         enet_writel(priv, val, ENET_PMH_REG(0));
 679
 680         return 0;
 681 }
 682
 683 /*
 684  * Change rx mode (promiscuous/allmulti) and update multicast list
 685  */
 686 static void bcm_enet_set_multicast_list(struct net_device *dev)
 687 {
 688         struct bcm_enet_priv *priv;
 689         struct netdev_hw_addr *ha;
 690         u32 val;
 691         int i;
 692
 693         priv = netdev_priv(dev);
 694
 695         val = enet_readl(priv, ENET_RXCFG_REG);
 696
 697         if (dev->flags & IFF_PROMISC)
 698                 val |= ENET_RXCFG_PROMISC_MASK;
 699         else
 700                 val &= ~ENET_RXCFG_PROMISC_MASK;
 701
 702         /* only 3 perfect match registers left, first one is used for
 703          * own mac address */
 704         if ((dev->flags & IFF_ALLMULTI) || netdev_mc_count(dev) > 3)
 705                 val |= ENET_RXCFG_ALLMCAST_MASK;
 706         else
 707                 val &= ~ENET_RXCFG_ALLMCAST_MASK;
 708
 709         /* no need to set perfect match registers if we catch all
 710          * multicast */
 711         if (val & ENET_RXCFG_ALLMCAST_MASK) {
 712                 enet_writel(priv, val, ENET_RXCFG_REG);
 713                 return;
 714         }
 715
 716         i = 0;
 717         netdev_for_each_mc_addr(ha, dev) {
 718                 u8 *dmi_addr;
 719                 u32 tmp;
 720
 721                 if (i == 3)
 722                         break;
 723                 /* update perfect match registers */
 724                 dmi_addr = ha->addr;
 725                 tmp = (dmi_addr[2] << 24) | (dmi_addr[3] << 16) |
 726                         (dmi_addr[4] << 8) | dmi_addr[5];
 727                 enet_writel(priv, tmp, ENET_PML_REG(i + 1));
 728
 729                 tmp = (dmi_addr[0] << 8 | dmi_addr[1]);
 730                 tmp |= ENET_PMH_DATAVALID_MASK;
 731                 enet_writel(priv, tmp, ENET_PMH_REG(i++ + 1));
 732         }
 733
 734         for (; i < 3; i++) {
 735                 enet_writel(priv, 0, ENET_PML_REG(i + 1));
 736                 enet_writel(priv, 0, ENET_PMH_REG(i + 1));
 737         }
 738
 739         enet_writel(priv, val, ENET_RXCFG_REG);
 740 }
 741
 742 /*
 743  * set mac duplex parameters
 744  */
 745 static void bcm_enet_set_duplex(struct bcm_enet_priv *priv, int fullduplex)
 746 {
 747         u32 val;
 748
 749         val = enet_readl(priv, ENET_TXCTL_REG);
 750         if (fullduplex)
 751                 val |= ENET_TXCTL_FD_MASK;
 752         else
 753                 val &= ~ENET_TXCTL_FD_MASK;
 754         enet_writel(priv, val, ENET_TXCTL_REG);
 755 }
 756
 757 /*
 758  * set mac flow control parameters
 759  */
 760 static void bcm_enet_set_flow(struct bcm_enet_priv *priv, int rx_en, int tx_en)
 761 {
 762         u32 val;
 763
 764         /* rx flow control (pause frame handling) */
 765         val = enet_readl(priv, ENET_RXCFG_REG);
 766         if (rx_en)
 767                 val |= ENET_RXCFG_ENFLOW_MASK;
 768         else
 769                 val &= ~ENET_RXCFG_ENFLOW_MASK;
 770         enet_writel(priv, val, ENET_RXCFG_REG);
 771
 772         if (!priv->dma_has_sram)
 773                 return;
 774
 775         /* tx flow control (pause frame generation) */
 776         val = enet_dma_readl(priv, ENETDMA_CFG_REG);
 777         if (tx_en)
 778                 val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
 779         else
 780                 val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
 781         enet_dma_writel(priv, val, ENETDMA_CFG_REG);
 782 }
 783
 784 /*
 785  * link changed callback (from phylib)
 786  */
 787 static void bcm_enet_adjust_phy_link(struct net_device *dev)
 788 {
 789         struct bcm_enet_priv *priv;
 790         struct phy_device *phydev;
 791         int status_changed;
 792
 793         priv = netdev_priv(dev);
 794         phydev = dev->phydev;
 795         status_changed = 0;
 796
 797         if (priv->old_link != phydev->link) {
 798                 status_changed = 1;
 799                 priv->old_link = phydev->link;
 800         }
 801
 802         /* reflect duplex change in mac configuration */
 803         if (phydev->link && phydev->duplex != priv->old_duplex) {
 804                 bcm_enet_set_duplex(priv,
 805                                     (phydev->duplex == DUPLEX_FULL) ? 1 : 0);
 806                 status_changed = 1;
 807                 priv->old_duplex = phydev->duplex;
 808         }
 809
 810         /* enable flow control if remote advertise it (trust phylib to
 811          * check that duplex is full */
 812         if (phydev->link && phydev->pause != priv->old_pause) {
 813                 int rx_pause_en, tx_pause_en;
 814
 815                 if (phydev->pause) {
 816                         /* pause was advertised by lpa and us */
 817                         rx_pause_en = 1;
 818                         tx_pause_en = 1;
 819                 } else if (!priv->pause_auto) {
 820                         /* pause setting overrided by user */
 821                         rx_pause_en = priv->pause_rx;
 822                         tx_pause_en = priv->pause_tx;
 823                 } else {
 824                         rx_pause_en = 0;
 825                         tx_pause_en = 0;
 826                 }
 827
 828                 bcm_enet_set_flow(priv, rx_pause_en, tx_pause_en);
 829                 status_changed = 1;
 830                 priv->old_pause = phydev->pause;
 831         }
 832
 833         if (status_changed) {
 834                 pr_info("%s: link %s", dev->name, phydev->link ?
 835                         "UP" : "DOWN");
 836                 if (phydev->link)
 837                         pr_cont(" - %d/%s - flow control %s", phydev->speed,
 838                                DUPLEX_FULL == phydev->duplex ? "full" : "half",
 839                                phydev->pause == 1 ? "rx&tx" : "off");
 840
 841                 pr_cont("\n");
 842         }
 843 }
 844
 845 /*
 846  * link changed callback (if phylib is not used)
 847  */
 848 static void bcm_enet_adjust_link(struct net_device *dev)
 849 {
 850         struct bcm_enet_priv *priv;
 851
 852         priv = netdev_priv(dev);
 853         bcm_enet_set_duplex(priv, priv->force_duplex_full);
 854         bcm_enet_set_flow(priv, priv->pause_rx, priv->pause_tx);
 855         netif_carrier_on(dev);
 856
 857         pr_info("%s: link forced UP - %d/%s - flow control %s/%s\n",
 858                 dev->name,
 859                 priv->force_speed_100 ? 100 : 10,
 860                 priv->force_duplex_full ? "full" : "half",
 861                 priv->pause_rx ? "rx" : "off",
 862                 priv->pause_tx ? "tx" : "off");
 863 }
 864
 865 /*
 866  * open callback, allocate dma rings & buffers and start rx operation
 867  */
 868 static int bcm_enet_open(struct net_device *dev)
 869 {
 870         struct bcm_enet_priv *priv;
 871         struct sockaddr addr;
 872         struct device *kdev;
 873         struct phy_device *phydev;
 874         int i, ret;
 875         unsigned int size;
 876         char phy_id[MII_BUS_ID_SIZE + 3];
 877         void *p;
 878         u32 val;
 879
 880         priv = netdev_priv(dev);
 881         kdev = &priv->pdev->dev;
 882
 883         if (priv->has_phy) {
 884                 /* connect to PHY */
 885                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
 886                          priv->mii_bus->id, priv->phy_id);
 887
 888                 phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link,
 889                                      PHY_INTERFACE_MODE_MII);
 890
 891                 if (IS_ERR(phydev)) {
 892                         dev_err(kdev, "could not attach to PHY\n");
 893                         return PTR_ERR(phydev);
 894                 }
 895
 896                 /* mask with MAC supported features */
 897                 phydev->supported &= (SUPPORTED_10baseT_Half |
 898                                       SUPPORTED_10baseT_Full |
 899                                       SUPPORTED_100baseT_Half |
 900                                       SUPPORTED_100baseT_Full |
 901                                       SUPPORTED_Autoneg |
 902                                       SUPPORTED_Pause |
 903                                       SUPPORTED_MII);
 904                 phydev->advertising = phydev->supported;
 905
 906                 if (priv->pause_auto && priv->pause_rx && priv->pause_tx)
 907                         phydev->advertising |= SUPPORTED_Pause;
 908                 else
 909                         phydev->advertising &= ~SUPPORTED_Pause;
 910
 911                 phy_attached_info(phydev);
 912
 913                 priv->old_link = 0;
 914                 priv->old_duplex = -1;
 915                 priv->old_pause = -1;
 916         }
 917
 918         /* mask all interrupts and request them */
 919         enet_writel(priv, 0, ENET_IRMASK_REG);
 920         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 921         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 922
 923         ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
 924         if (ret)
 925                 goto out_phy_disconnect;
 926
 927         ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, 0,
 928                           dev->name, dev);
 929         if (ret)
 930                 goto out_freeirq;
 931
 932         ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
 933                           0, dev->name, dev);
 934         if (ret)
 935                 goto out_freeirq_rx;
 936
 937         /* initialize perfect match registers */
 938         for (i = 0; i < 4; i++) {
 939                 enet_writel(priv, 0, ENET_PML_REG(i));
 940                 enet_writel(priv, 0, ENET_PMH_REG(i));
 941         }
 942
 943         /* write device mac address */
 944         memcpy(addr.sa_data, dev->dev_addr, ETH_ALEN);
 945         bcm_enet_set_mac_address(dev, &addr);
 946
 947         /* allocate rx dma ring */
 948         size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
 949         p = dma_zalloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
 950         if (!p) {
 951                 ret = -ENOMEM;
 952                 goto out_freeirq_tx;
 953         }
 954
 955         priv->rx_desc_alloc_size = size;
 956         priv->rx_desc_cpu = p;
 957
 958         /* allocate tx dma ring */
 959         size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
 960         p = dma_zalloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
 961         if (!p) {
 962                 ret = -ENOMEM;
 963                 goto out_free_rx_ring;
 964         }
 965
 966         priv->tx_desc_alloc_size = size;
 967         priv->tx_desc_cpu = p;
 968
 969         priv->tx_skb = kcalloc(priv->tx_ring_size, sizeof(struct sk_buff *),
 970                                GFP_KERNEL);
 971         if (!priv->tx_skb) {
 972                 ret = -ENOMEM;
 973                 goto out_free_tx_ring;
 974         }
 975
 976         priv->tx_desc_count = priv->tx_ring_size;
 977         priv->tx_dirty_desc = 0;
 978         priv->tx_curr_desc = 0;
 979         spin_lock_init(&priv->tx_lock);
 980
 981         /* init & fill rx ring with skbs */
 982         priv->rx_skb = kcalloc(priv->rx_ring_size, sizeof(struct sk_buff *),
 983                                GFP_KERNEL);
 984         if (!priv->rx_skb) {
 985                 ret = -ENOMEM;
 986                 goto out_free_tx_skb;
 987         }
 988
 989         priv->rx_desc_count = 0;
 990         priv->rx_dirty_desc = 0;
 991         priv->rx_curr_desc = 0;
 992
 993         /* initialize flow control buffer allocation */
 994         if (priv->dma_has_sram)
 995                 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
 996                                 ENETDMA_BUFALLOC_REG(priv->rx_chan));
 997         else
 998                 enet_dmac_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
 999                                 ENETDMAC_BUFALLOC, priv->rx_chan);
1000
1001         if (bcm_enet_refill_rx(dev)) {
1002                 dev_err(kdev, "cannot allocate rx skb queue\n");
1003                 ret = -ENOMEM;
1004                 goto out;
1005         }
1006
1007         /* write rx & tx ring addresses */
1008         if (priv->dma_has_sram) {
1009                 enet_dmas_writel(priv, priv->rx_desc_dma,
1010                                  ENETDMAS_RSTART_REG, priv->rx_chan);
1011                 enet_dmas_writel(priv, priv->tx_desc_dma,
1012                          ENETDMAS_RSTART_REG, priv->tx_chan);
1013         } else {
1014                 enet_dmac_writel(priv, priv->rx_desc_dma,
1015                                 ENETDMAC_RSTART, priv->rx_chan);
1016                 enet_dmac_writel(priv, priv->tx_desc_dma,
1017                                 ENETDMAC_RSTART, priv->tx_chan);
1018         }
1019
1020         /* clear remaining state ram for rx & tx channel */
1021         if (priv->dma_has_sram) {
1022                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
1023                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
1024                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
1025                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
1026                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
1027                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
1028         } else {
1029                 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->rx_chan);
1030                 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->tx_chan);
1031         }
1032
1033         /* set max rx/tx length */
1034         enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
1035         enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
1036
1037         /* set dma maximum burst len */
1038         enet_dmac_writel(priv, priv->dma_maxburst,
1039                          ENETDMAC_MAXBURST, priv->rx_chan);
1040         enet_dmac_writel(priv, priv->dma_maxburst,
1041                          ENETDMAC_MAXBURST, priv->tx_chan);
1042
1043         /* set correct transmit fifo watermark */
1044         enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
1045
1046         /* set flow control low/high threshold to 1/3 / 2/3 */
1047         if (priv->dma_has_sram) {
1048                 val = priv->rx_ring_size / 3;
1049                 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
1050                 val = (priv->rx_ring_size * 2) / 3;
1051                 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
1052         } else {
1053                 enet_dmac_writel(priv, 5, ENETDMAC_FC, priv->rx_chan);
1054                 enet_dmac_writel(priv, priv->rx_ring_size, ENETDMAC_LEN, priv->rx_chan);
1055                 enet_dmac_writel(priv, priv->tx_ring_size, ENETDMAC_LEN, priv->tx_chan);
1056         }
1057
1058         /* all set, enable mac and interrupts, start dma engine and
1059          * kick rx dma channel */
1060         wmb();
1061         val = enet_readl(priv, ENET_CTL_REG);
1062         val |= ENET_CTL_ENABLE_MASK;
1063         enet_writel(priv, val, ENET_CTL_REG);
1064         enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
1065         enet_dmac_writel(priv, priv->dma_chan_en_mask,
1066                          ENETDMAC_CHANCFG, priv->rx_chan);
1067
1068         /* watch "mib counters about to overflow" interrupt */
1069         enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
1070         enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1071
1072         /* watch "packet transferred" interrupt in rx and tx */
1073         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1074                          ENETDMAC_IR, priv->rx_chan);
1075         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1076                          ENETDMAC_IR, priv->tx_chan);
1077
1078         /* make sure we enable napi before rx interrupt  */
1079         napi_enable(&priv->napi);
1080
1081         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1082                          ENETDMAC_IRMASK, priv->rx_chan);
1083         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1084                          ENETDMAC_IRMASK, priv->tx_chan);
1085
1086         if (priv->has_phy)
1087                 phy_start(phydev);
1088         else
1089                 bcm_enet_adjust_link(dev);
1090
1091         netif_start_queue(dev);
1092         return 0;
1093
1094 out:
1095         for (i = 0; i < priv->rx_ring_size; i++) {
1096                 struct bcm_enet_desc *desc;
1097
1098                 if (!priv->rx_skb[i])
1099                         continue;
1100
1101                 desc = &priv->rx_desc_cpu[i];
1102                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1103                                  DMA_FROM_DEVICE);
1104                 kfree_skb(priv->rx_skb[i]);
1105         }
1106         kfree(priv->rx_skb);
1107
1108 out_free_tx_skb:
1109         kfree(priv->tx_skb);
1110
1111 out_free_tx_ring:
1112         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1113                           priv->tx_desc_cpu, priv->tx_desc_dma);
1114
1115 out_free_rx_ring:
1116         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1117                           priv->rx_desc_cpu, priv->rx_desc_dma);
1118
1119 out_freeirq_tx:
1120         free_irq(priv->irq_tx, dev);
1121
1122 out_freeirq_rx:
1123         free_irq(priv->irq_rx, dev);
1124
1125 out_freeirq:
1126         free_irq(dev->irq, dev);
1127
1128 out_phy_disconnect:
1129         phy_disconnect(phydev);
1130
1131         return ret;
1132 }
1133
1134 /*
1135  * disable mac
1136  */
1137 static void bcm_enet_disable_mac(struct bcm_enet_priv *priv)
1138 {
1139         int limit;
1140         u32 val;
1141
1142         val = enet_readl(priv, ENET_CTL_REG);
1143         val |= ENET_CTL_DISABLE_MASK;
1144         enet_writel(priv, val, ENET_CTL_REG);
1145
1146         limit = 1000;
1147         do {
1148                 u32 val;
1149
1150                 val = enet_readl(priv, ENET_CTL_REG);
1151                 if (!(val & ENET_CTL_DISABLE_MASK))
1152                         break;
1153                 udelay(1);
1154         } while (limit--);
1155 }
1156
1157 /*
1158  * disable dma in given channel
1159  */
1160 static void bcm_enet_disable_dma(struct bcm_enet_priv *priv, int chan)
1161 {
1162         int limit;
1163
1164         enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG, chan);
1165
1166         limit = 1000;
1167         do {
1168                 u32 val;
1169
1170                 val = enet_dmac_readl(priv, ENETDMAC_CHANCFG, chan);
1171                 if (!(val & ENETDMAC_CHANCFG_EN_MASK))
1172                         break;
1173                 udelay(1);
1174         } while (limit--);
1175 }
1176
1177 /*
1178  * stop callback
1179  */
1180 static int bcm_enet_stop(struct net_device *dev)
1181 {
1182         struct bcm_enet_priv *priv;
1183         struct device *kdev;
1184         int i;
1185
1186         priv = netdev_priv(dev);
1187         kdev = &priv->pdev->dev;
1188
1189         netif_stop_queue(dev);
1190         napi_disable(&priv->napi);
1191         if (priv->has_phy)
1192                 phy_stop(dev->phydev);
1193         del_timer_sync(&priv->rx_timeout);
1194
1195         /* mask all interrupts */
1196         enet_writel(priv, 0, ENET_IRMASK_REG);
1197         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
1198         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
1199
1200         /* make sure no mib update is scheduled */
1201         cancel_work_sync(&priv->mib_update_task);
1202
1203         /* disable dma & mac */
1204         bcm_enet_disable_dma(priv, priv->tx_chan);
1205         bcm_enet_disable_dma(priv, priv->rx_chan);
1206         bcm_enet_disable_mac(priv);
1207
1208         /* force reclaim of all tx buffers */
1209         bcm_enet_tx_reclaim(dev, 1);
1210
1211         /* free the rx skb ring */
1212         for (i = 0; i < priv->rx_ring_size; i++) {
1213                 struct bcm_enet_desc *desc;
1214
1215                 if (!priv->rx_skb[i])
1216                         continue;
1217
1218                 desc = &priv->rx_desc_cpu[i];
1219                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1220                                  DMA_FROM_DEVICE);
1221                 kfree_skb(priv->rx_skb[i]);
1222         }
1223
1224         /* free remaining allocated memory */
1225         kfree(priv->rx_skb);
1226         kfree(priv->tx_skb);
1227         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1228                           priv->rx_desc_cpu, priv->rx_desc_dma);
1229         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1230                           priv->tx_desc_cpu, priv->tx_desc_dma);
1231         free_irq(priv->irq_tx, dev);
1232         free_irq(priv->irq_rx, dev);
1233         free_irq(dev->irq, dev);
1234
1235         /* release phy */
1236         if (priv->has_phy)
1237                 phy_disconnect(dev->phydev);
1238
1239         return 0;
1240 }
1241
1242 /*
1243  * ethtool callbacks
1244  */
1245 struct bcm_enet_stats {
1246         char stat_string[ETH_GSTRING_LEN];
1247         int sizeof_stat;
1248         int stat_offset;
1249         int mib_reg;
1250 };
1251
1252 #define GEN_STAT(m) sizeof(((struct bcm_enet_priv *)0)->m),             \
1253                      offsetof(struct bcm_enet_priv, m)
1254 #define DEV_STAT(m) sizeof(((struct net_device_stats *)0)->m),          \
1255                      offsetof(struct net_device_stats, m)
1256
1257 static const struct bcm_enet_stats bcm_enet_gstrings_stats[] = {
1258         { "rx_packets", DEV_STAT(rx_packets), -1 },
1259         { "tx_packets", DEV_STAT(tx_packets), -1 },
1260         { "rx_bytes", DEV_STAT(rx_bytes), -1 },
1261         { "tx_bytes", DEV_STAT(tx_bytes), -1 },
1262         { "rx_errors", DEV_STAT(rx_errors), -1 },
1263         { "tx_errors", DEV_STAT(tx_errors), -1 },
1264         { "rx_dropped", DEV_STAT(rx_dropped), -1 },
1265         { "tx_dropped", DEV_STAT(tx_dropped), -1 },
1266
1267         { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETH_MIB_RX_GD_OCTETS},
1268         { "rx_good_pkts", GEN_STAT(mib.rx_gd_pkts), ETH_MIB_RX_GD_PKTS },
1269         { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETH_MIB_RX_BRDCAST },
1270         { "rx_multicast", GEN_STAT(mib.rx_mult), ETH_MIB_RX_MULT },
1271         { "rx_64_octets", GEN_STAT(mib.rx_64), ETH_MIB_RX_64 },
1272         { "rx_65_127_oct", GEN_STAT(mib.rx_65_127), ETH_MIB_RX_65_127 },
1273         { "rx_128_255_oct", GEN_STAT(mib.rx_128_255), ETH_MIB_RX_128_255 },
1274         { "rx_256_511_oct", GEN_STAT(mib.rx_256_511), ETH_MIB_RX_256_511 },
1275         { "rx_512_1023_oct", GEN_STAT(mib.rx_512_1023), ETH_MIB_RX_512_1023 },
1276         { "rx_1024_max_oct", GEN_STAT(mib.rx_1024_max), ETH_MIB_RX_1024_MAX },
1277         { "rx_jabber", GEN_STAT(mib.rx_jab), ETH_MIB_RX_JAB },
1278         { "rx_oversize", GEN_STAT(mib.rx_ovr), ETH_MIB_RX_OVR },
1279         { "rx_fragment", GEN_STAT(mib.rx_frag), ETH_MIB_RX_FRAG },
1280         { "rx_dropped", GEN_STAT(mib.rx_drop), ETH_MIB_RX_DROP },
1281         { "rx_crc_align", GEN_STAT(mib.rx_crc_align), ETH_MIB_RX_CRC_ALIGN },
1282         { "rx_undersize", GEN_STAT(mib.rx_und), ETH_MIB_RX_UND },
1283         { "rx_crc", GEN_STAT(mib.rx_crc), ETH_MIB_RX_CRC },
1284         { "rx_align", GEN_STAT(mib.rx_align), ETH_MIB_RX_ALIGN },
1285         { "rx_symbol_error", GEN_STAT(mib.rx_sym), ETH_MIB_RX_SYM },
1286         { "rx_pause", GEN_STAT(mib.rx_pause), ETH_MIB_RX_PAUSE },
1287         { "rx_control", GEN_STAT(mib.rx_cntrl), ETH_MIB_RX_CNTRL },
1288
1289         { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETH_MIB_TX_GD_OCTETS },
1290         { "tx_good_pkts", GEN_STAT(mib.tx_gd_pkts), ETH_MIB_TX_GD_PKTS },
1291         { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETH_MIB_TX_BRDCAST },
1292         { "tx_multicast", GEN_STAT(mib.tx_mult), ETH_MIB_TX_MULT },
1293         { "tx_64_oct", GEN_STAT(mib.tx_64), ETH_MIB_TX_64 },
1294         { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETH_MIB_TX_65_127 },
1295         { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETH_MIB_TX_128_255 },
1296         { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETH_MIB_TX_256_511 },
1297         { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETH_MIB_TX_512_1023},
1298         { "tx_1024_max_oct", GEN_STAT(mib.tx_1024_max), ETH_MIB_TX_1024_MAX },
1299         { "tx_jabber", GEN_STAT(mib.tx_jab), ETH_MIB_TX_JAB },
1300         { "tx_oversize", GEN_STAT(mib.tx_ovr), ETH_MIB_TX_OVR },
1301         { "tx_fragment", GEN_STAT(mib.tx_frag), ETH_MIB_TX_FRAG },
1302         { "tx_underrun", GEN_STAT(mib.tx_underrun), ETH_MIB_TX_UNDERRUN },
1303         { "tx_collisions", GEN_STAT(mib.tx_col), ETH_MIB_TX_COL },
1304         { "tx_single_collision", GEN_STAT(mib.tx_1_col), ETH_MIB_TX_1_COL },
1305         { "tx_multiple_collision", GEN_STAT(mib.tx_m_col), ETH_MIB_TX_M_COL },
1306         { "tx_excess_collision", GEN_STAT(mib.tx_ex_col), ETH_MIB_TX_EX_COL },
1307         { "tx_late_collision", GEN_STAT(mib.tx_late), ETH_MIB_TX_LATE },
1308         { "tx_deferred", GEN_STAT(mib.tx_def), ETH_MIB_TX_DEF },
1309         { "tx_carrier_sense", GEN_STAT(mib.tx_crs), ETH_MIB_TX_CRS },
1310         { "tx_pause", GEN_STAT(mib.tx_pause), ETH_MIB_TX_PAUSE },
1311
1312 };
1313
1314 #define BCM_ENET_STATS_LEN      ARRAY_SIZE(bcm_enet_gstrings_stats)
1315
1316 static const u32 unused_mib_regs[] = {
1317         ETH_MIB_TX_ALL_OCTETS,
1318         ETH_MIB_TX_ALL_PKTS,
1319         ETH_MIB_RX_ALL_OCTETS,
1320         ETH_MIB_RX_ALL_PKTS,
1321 };
1322
1323
1324 static void bcm_enet_get_drvinfo(struct net_device *netdev,
1325                                  struct ethtool_drvinfo *drvinfo)
1326 {
1327         strlcpy(drvinfo->driver, bcm_enet_driver_name, sizeof(drvinfo->driver));
1328         strlcpy(drvinfo->version, bcm_enet_driver_version,
1329                 sizeof(drvinfo->version));
1330         strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1331         strlcpy(drvinfo->bus_info, "bcm63xx", sizeof(drvinfo->bus_info));
1332 }
1333
1334 static int bcm_enet_get_sset_count(struct net_device *netdev,
1335                                         int string_set)
1336 {
1337         switch (string_set) {
1338         case ETH_SS_STATS:
1339                 return BCM_ENET_STATS_LEN;
1340         default:
1341                 return -EINVAL;
1342         }
1343 }
1344
1345 static void bcm_enet_get_strings(struct net_device *netdev,
1346                                  u32 stringset, u8 *data)
1347 {
1348         int i;
1349
1350         switch (stringset) {
1351         case ETH_SS_STATS:
1352                 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1353                         memcpy(data + i * ETH_GSTRING_LEN,
1354                                bcm_enet_gstrings_stats[i].stat_string,
1355                                ETH_GSTRING_LEN);
1356                 }
1357                 break;
1358         }
1359 }
1360
1361 static void update_mib_counters(struct bcm_enet_priv *priv)
1362 {
1363         int i;
1364
1365         for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1366                 const struct bcm_enet_stats *s;
1367                 u32 val;
1368                 char *p;
1369
1370                 s = &bcm_enet_gstrings_stats[i];
1371                 if (s->mib_reg == -1)
1372                         continue;
1373
1374                 val = enet_readl(priv, ENET_MIB_REG(s->mib_reg));
1375                 p = (char *)priv + s->stat_offset;
1376
1377                 if (s->sizeof_stat == sizeof(u64))
1378                         *(u64 *)p += val;
1379                 else
1380                         *(u32 *)p += val;
1381         }
1382
1383         /* also empty unused mib counters to make sure mib counter
1384          * overflow interrupt is cleared */
1385         for (i = 0; i < ARRAY_SIZE(unused_mib_regs); i++)
1386                 (void)enet_readl(priv, ENET_MIB_REG(unused_mib_regs[i]));
1387 }
1388
1389 static void bcm_enet_update_mib_counters_defer(struct work_struct *t)
1390 {
1391         struct bcm_enet_priv *priv;
1392
1393         priv = container_of(t, struct bcm_enet_priv, mib_update_task);
1394         mutex_lock(&priv->mib_update_lock);
1395         update_mib_counters(priv);
1396         mutex_unlock(&priv->mib_update_lock);
1397
1398         /* reenable mib interrupt */
1399         if (netif_running(priv->net_dev))
1400                 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1401 }
1402
1403 static void bcm_enet_get_ethtool_stats(struct net_device *netdev,
1404                                        struct ethtool_stats *stats,
1405                                        u64 *data)
1406 {
1407         struct bcm_enet_priv *priv;
1408         int i;
1409
1410         priv = netdev_priv(netdev);
1411
1412         mutex_lock(&priv->mib_update_lock);
1413         update_mib_counters(priv);
1414
1415         for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1416                 const struct bcm_enet_stats *s;
1417                 char *p;
1418
1419                 s = &bcm_enet_gstrings_stats[i];
1420                 if (s->mib_reg == -1)
1421                         p = (char *)&netdev->stats;
1422                 else
1423                         p = (char *)priv;
1424                 p += s->stat_offset;
1425                 data[i] = (s->sizeof_stat == sizeof(u64)) ?
1426                         *(u64 *)p : *(u32 *)p;
1427         }
1428         mutex_unlock(&priv->mib_update_lock);
1429 }
1430
1431 static int bcm_enet_nway_reset(struct net_device *dev)
1432 {
1433         struct bcm_enet_priv *priv;
1434
1435         priv = netdev_priv(dev);
1436         if (priv->has_phy) {
1437                 if (!dev->phydev)
1438                         return -ENODEV;
1439                 return genphy_restart_aneg(dev->phydev);
1440         }
1441
1442         return -EOPNOTSUPP;
1443 }
1444
1445 static int bcm_enet_get_link_ksettings(struct net_device *dev,
1446                                        struct ethtool_link_ksettings *cmd)
1447 {
1448         struct bcm_enet_priv *priv;
1449         u32 supported, advertising;
1450
1451         priv = netdev_priv(dev);
1452
1453         if (priv->has_phy) {
1454                 if (!dev->phydev)
1455                         return -ENODEV;
1456                 return phy_ethtool_ksettings_get(dev->phydev, cmd);
1457         } else {
1458                 cmd->base.autoneg = 0;
1459                 cmd->base.speed = (priv->force_speed_100) ?
1460                         SPEED_100 : SPEED_10;
1461                 cmd->base.duplex = (priv->force_duplex_full) ?
1462                         DUPLEX_FULL : DUPLEX_HALF;
1463                 supported = ADVERTISED_10baseT_Half |
1464                         ADVERTISED_10baseT_Full |
1465                         ADVERTISED_100baseT_Half |
1466                         ADVERTISED_100baseT_Full;
1467                 advertising = 0;
1468                 ethtool_convert_legacy_u32_to_link_mode(
1469                         cmd->link_modes.supported, supported);
1470                 ethtool_convert_legacy_u32_to_link_mode(
1471                         cmd->link_modes.advertising, advertising);
1472                 cmd->base.port = PORT_MII;
1473         }
1474         return 0;
1475 }
1476
1477 static int bcm_enet_set_link_ksettings(struct net_device *dev,
1478                                        const struct ethtool_link_ksettings *cmd)
1479 {
1480         struct bcm_enet_priv *priv;
1481
1482         priv = netdev_priv(dev);
1483         if (priv->has_phy) {
1484                 if (!dev->phydev)
1485                         return -ENODEV;
1486                 return phy_ethtool_ksettings_set(dev->phydev, cmd);
1487         } else {
1488
1489                 if (cmd->base.autoneg ||
1490                     (cmd->base.speed != SPEED_100 &&
1491                      cmd->base.speed != SPEED_10) ||
1492                     cmd->base.port != PORT_MII)
1493                         return -EINVAL;
1494
1495                 priv->force_speed_100 =
1496                         (cmd->base.speed == SPEED_100) ? 1 : 0;
1497                 priv->force_duplex_full =
1498                         (cmd->base.duplex == DUPLEX_FULL) ? 1 : 0;
1499
1500                 if (netif_running(dev))
1501                         bcm_enet_adjust_link(dev);
1502                 return 0;
1503         }
1504 }
1505
1506 static void bcm_enet_get_ringparam(struct net_device *dev,
1507                                    struct ethtool_ringparam *ering)
1508 {
1509         struct bcm_enet_priv *priv;
1510
1511         priv = netdev_priv(dev);
1512
1513         /* rx/tx ring is actually only limited by memory */
1514         ering->rx_max_pending = 8192;
1515         ering->tx_max_pending = 8192;
1516         ering->rx_pending = priv->rx_ring_size;
1517         ering->tx_pending = priv->tx_ring_size;
1518 }
1519
1520 static int bcm_enet_set_ringparam(struct net_device *dev,
1521                                   struct ethtool_ringparam *ering)
1522 {
1523         struct bcm_enet_priv *priv;
1524         int was_running;
1525
1526         priv = netdev_priv(dev);
1527
1528         was_running = 0;
1529         if (netif_running(dev)) {
1530                 bcm_enet_stop(dev);
1531                 was_running = 1;
1532         }
1533
1534         priv->rx_ring_size = ering->rx_pending;
1535         priv->tx_ring_size = ering->tx_pending;
1536
1537         if (was_running) {
1538                 int err;
1539
1540                 err = bcm_enet_open(dev);
1541                 if (err)
1542                         dev_close(dev);
1543                 else
1544                         bcm_enet_set_multicast_list(dev);
1545         }
1546         return 0;
1547 }
1548
1549 static void bcm_enet_get_pauseparam(struct net_device *dev,
1550                                     struct ethtool_pauseparam *ecmd)
1551 {
1552         struct bcm_enet_priv *priv;
1553
1554         priv = netdev_priv(dev);
1555         ecmd->autoneg = priv->pause_auto;
1556         ecmd->rx_pause = priv->pause_rx;
1557         ecmd->tx_pause = priv->pause_tx;
1558 }
1559
1560 static int bcm_enet_set_pauseparam(struct net_device *dev,
1561                                    struct ethtool_pauseparam *ecmd)
1562 {
1563         struct bcm_enet_priv *priv;
1564
1565         priv = netdev_priv(dev);
1566
1567         if (priv->has_phy) {
1568                 if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) {
1569                         /* asymetric pause mode not supported,
1570                          * actually possible but integrated PHY has RO
1571                          * asym_pause bit */
1572                         return -EINVAL;
1573                 }
1574         } else {
1575                 /* no pause autoneg on direct mii connection */
1576                 if (ecmd->autoneg)
1577                         return -EINVAL;
1578         }
1579
1580         priv->pause_auto = ecmd->autoneg;
1581         priv->pause_rx = ecmd->rx_pause;
1582         priv->pause_tx = ecmd->tx_pause;
1583
1584         return 0;
1585 }
1586
1587 static const struct ethtool_ops bcm_enet_ethtool_ops = {
1588         .get_strings            = bcm_enet_get_strings,
1589         .get_sset_count         = bcm_enet_get_sset_count,
1590         .get_ethtool_stats      = bcm_enet_get_ethtool_stats,
1591         .nway_reset             = bcm_enet_nway_reset,
1592         .get_drvinfo            = bcm_enet_get_drvinfo,
1593         .get_link               = ethtool_op_get_link,
1594         .get_ringparam          = bcm_enet_get_ringparam,
1595         .set_ringparam          = bcm_enet_set_ringparam,
1596         .get_pauseparam         = bcm_enet_get_pauseparam,
1597         .set_pauseparam         = bcm_enet_set_pauseparam,
1598         .get_link_ksettings     = bcm_enet_get_link_ksettings,
1599         .set_link_ksettings     = bcm_enet_set_link_ksettings,
1600 };
1601
1602 static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1603 {
1604         struct bcm_enet_priv *priv;
1605
1606         priv = netdev_priv(dev);
1607         if (priv->has_phy) {
1608                 if (!dev->phydev)
1609                         return -ENODEV;
1610                 return phy_mii_ioctl(dev->phydev, rq, cmd);
1611         } else {
1612                 struct mii_if_info mii;
1613
1614                 mii.dev = dev;
1615                 mii.mdio_read = bcm_enet_mdio_read_mii;
1616                 mii.mdio_write = bcm_enet_mdio_write_mii;
1617                 mii.phy_id = 0;
1618                 mii.phy_id_mask = 0x3f;
1619                 mii.reg_num_mask = 0x1f;
1620                 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
1621         }
1622 }
1623
1624 /*
1625  * calculate actual hardware mtu
1626  */
1627 static int compute_hw_mtu(struct bcm_enet_priv *priv, int mtu)
1628 {
1629         int actual_mtu;
1630
1631         actual_mtu = mtu;
1632
1633         /* add ethernet header + vlan tag size */
1634         actual_mtu += VLAN_ETH_HLEN;
1635
1636         if (actual_mtu < 64 || actual_mtu > BCMENET_MAX_MTU)
1637                 return -EINVAL;
1638
1639         /*
1640          * setup maximum size before we get overflow mark in
1641          * descriptor, note that this will not prevent reception of
1642          * big frames, they will be split into multiple buffers
1643          * anyway
1644          */
1645         priv->hw_mtu = actual_mtu;
1646
1647         /*
1648          * align rx buffer size to dma burst len, account FCS since
1649          * it's appended
1650          */
1651         priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN,
1652                                   priv->dma_maxburst * 4);
1653         return 0;
1654 }
1655
1656 /*
1657  * adjust mtu, can't be called while device is running
1658  */
1659 static int bcm_enet_change_mtu(struct net_device *dev, int new_mtu)
1660 {
1661         int ret;
1662
1663         if (netif_running(dev))
1664                 return -EBUSY;
1665
1666         ret = compute_hw_mtu(netdev_priv(dev), new_mtu);
1667         if (ret)
1668                 return ret;
1669         dev->mtu = new_mtu;
1670         return 0;
1671 }
1672
1673 /*
1674  * preinit hardware to allow mii operation while device is down
1675  */
1676 static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv)
1677 {
1678         u32 val;
1679         int limit;
1680
1681         /* make sure mac is disabled */
1682         bcm_enet_disable_mac(priv);
1683
1684         /* soft reset mac */
1685         val = ENET_CTL_SRESET_MASK;
1686         enet_writel(priv, val, ENET_CTL_REG);
1687         wmb();
1688
1689         limit = 1000;
1690         do {
1691                 val = enet_readl(priv, ENET_CTL_REG);
1692                 if (!(val & ENET_CTL_SRESET_MASK))
1693                         break;
1694                 udelay(1);
1695         } while (limit--);
1696
1697         /* select correct mii interface */
1698         val = enet_readl(priv, ENET_CTL_REG);
1699         if (priv->use_external_mii)
1700                 val |= ENET_CTL_EPHYSEL_MASK;
1701         else
1702                 val &= ~ENET_CTL_EPHYSEL_MASK;
1703         enet_writel(priv, val, ENET_CTL_REG);
1704
1705         /* turn on mdc clock */
1706         enet_writel(priv, (0x1f << ENET_MIISC_MDCFREQDIV_SHIFT) |
1707                     ENET_MIISC_PREAMBLEEN_MASK, ENET_MIISC_REG);
1708
1709         /* set mib counters to self-clear when read */
1710         val = enet_readl(priv, ENET_MIBCTL_REG);
1711         val |= ENET_MIBCTL_RDCLEAR_MASK;
1712         enet_writel(priv, val, ENET_MIBCTL_REG);
1713 }
1714
1715 static const struct net_device_ops bcm_enet_ops = {
1716         .ndo_open               = bcm_enet_open,
1717         .ndo_stop               = bcm_enet_stop,
1718         .ndo_start_xmit         = bcm_enet_start_xmit,
1719         .ndo_set_mac_address    = bcm_enet_set_mac_address,
1720         .ndo_set_rx_mode        = bcm_enet_set_multicast_list,
1721         .ndo_do_ioctl           = bcm_enet_ioctl,
1722         .ndo_change_mtu         = bcm_enet_change_mtu,
1723 };
1724
1725 /*
1726  * allocate netdevice, request register memory and register device.
1727  */
1728 static int bcm_enet_probe(struct platform_device *pdev)
1729 {
1730         struct bcm_enet_priv *priv;
1731         struct net_device *dev;
1732         struct bcm63xx_enet_platform_data *pd;
1733         struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx;
1734         struct mii_bus *bus;
1735         const char *clk_name;
1736         int i, ret;
1737
1738         /* stop if shared driver failed, assume driver->probe will be
1739          * called in the same order we register devices (correct ?) */
1740         if (!bcm_enet_shared_base[0])
1741                 return -ENODEV;
1742
1743         res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1744         res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1745         res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
1746         if (!res_irq || !res_irq_rx || !res_irq_tx)
1747                 return -ENODEV;
1748
1749         ret = 0;
1750         dev = alloc_etherdev(sizeof(*priv));
1751         if (!dev)
1752                 return -ENOMEM;
1753         priv = netdev_priv(dev);
1754
1755         priv->enet_is_sw = false;
1756         priv->dma_maxburst = BCMENET_DMA_MAXBURST;
1757
1758         ret = compute_hw_mtu(priv, dev->mtu);
1759         if (ret)
1760                 goto out;
1761
1762         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1763         priv->base = devm_ioremap_resource(&pdev->dev, res_mem);
1764         if (IS_ERR(priv->base)) {
1765                 ret = PTR_ERR(priv->base);
1766                 goto out;
1767         }
1768
1769         dev->irq = priv->irq = res_irq->start;
1770         priv->irq_rx = res_irq_rx->start;
1771         priv->irq_tx = res_irq_tx->start;
1772         priv->mac_id = pdev->id;
1773
1774         /* get rx & tx dma channel id for this mac */
1775         if (priv->mac_id == 0) {
1776                 priv->rx_chan = 0;
1777                 priv->tx_chan = 1;
1778                 clk_name = "enet0";
1779         } else {
1780                 priv->rx_chan = 2;
1781                 priv->tx_chan = 3;
1782                 clk_name = "enet1";
1783         }
1784
1785         priv->mac_clk = clk_get(&pdev->dev, clk_name);
1786         if (IS_ERR(priv->mac_clk)) {
1787                 ret = PTR_ERR(priv->mac_clk);
1788                 goto out;
1789         }
1790         clk_prepare_enable(priv->mac_clk);
1791
1792         /* initialize default and fetch platform data */
1793         priv->rx_ring_size = BCMENET_DEF_RX_DESC;
1794         priv->tx_ring_size = BCMENET_DEF_TX_DESC;
1795
1796         pd = dev_get_platdata(&pdev->dev);
1797         if (pd) {
1798                 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
1799                 priv->has_phy = pd->has_phy;
1800                 priv->phy_id = pd->phy_id;
1801                 priv->has_phy_interrupt = pd->has_phy_interrupt;
1802                 priv->phy_interrupt = pd->phy_interrupt;
1803                 priv->use_external_mii = !pd->use_internal_phy;
1804                 priv->pause_auto = pd->pause_auto;
1805                 priv->pause_rx = pd->pause_rx;
1806                 priv->pause_tx = pd->pause_tx;
1807                 priv->force_duplex_full = pd->force_duplex_full;
1808                 priv->force_speed_100 = pd->force_speed_100;
1809                 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
1810                 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
1811                 priv->dma_chan_width = pd->dma_chan_width;
1812                 priv->dma_has_sram = pd->dma_has_sram;
1813                 priv->dma_desc_shift = pd->dma_desc_shift;
1814         }
1815
1816         if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) {
1817                 /* using internal PHY, enable clock */
1818                 priv->phy_clk = clk_get(&pdev->dev, "ephy");
1819                 if (IS_ERR(priv->phy_clk)) {
1820                         ret = PTR_ERR(priv->phy_clk);
1821                         priv->phy_clk = NULL;
1822                         goto out_put_clk_mac;
1823                 }
1824                 clk_prepare_enable(priv->phy_clk);
1825         }
1826
1827         /* do minimal hardware init to be able to probe mii bus */
1828         bcm_enet_hw_preinit(priv);
1829
1830         /* MII bus registration */
1831         if (priv->has_phy) {
1832
1833                 priv->mii_bus = mdiobus_alloc();
1834                 if (!priv->mii_bus) {
1835                         ret = -ENOMEM;
1836                         goto out_uninit_hw;
1837                 }
1838
1839                 bus = priv->mii_bus;
1840                 bus->name = "bcm63xx_enet MII bus";
1841                 bus->parent = &pdev->dev;
1842                 bus->priv = priv;
1843                 bus->read = bcm_enet_mdio_read_phylib;
1844                 bus->write = bcm_enet_mdio_write_phylib;
1845                 sprintf(bus->id, "%s-%d", pdev->name, priv->mac_id);
1846
1847                 /* only probe bus where we think the PHY is, because
1848                  * the mdio read operation return 0 instead of 0xffff
1849                  * if a slave is not present on hw */
1850                 bus->phy_mask = ~(1 << priv->phy_id);
1851
1852                 if (priv->has_phy_interrupt)
1853                         bus->irq[priv->phy_id] = priv->phy_interrupt;
1854
1855                 ret = mdiobus_register(bus);
1856                 if (ret) {
1857                         dev_err(&pdev->dev, "unable to register mdio bus\n");
1858                         goto out_free_mdio;
1859                 }
1860         } else {
1861
1862                 /* run platform code to initialize PHY device */
1863                 if (pd && pd->mii_config &&
1864                     pd->mii_config(dev, 1, bcm_enet_mdio_read_mii,
1865                                    bcm_enet_mdio_write_mii)) {
1866                         dev_err(&pdev->dev, "unable to configure mdio bus\n");
1867                         goto out_uninit_hw;
1868                 }
1869         }
1870
1871         spin_lock_init(&priv->rx_lock);
1872
1873         /* init rx timeout (used for oom) */
1874         init_timer(&priv->rx_timeout);
1875         priv->rx_timeout.function = bcm_enet_refill_rx_timer;
1876         priv->rx_timeout.data = (unsigned long)dev;
1877
1878         /* init the mib update lock&work */
1879         mutex_init(&priv->mib_update_lock);
1880         INIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer);
1881
1882         /* zero mib counters */
1883         for (i = 0; i < ENET_MIB_REG_COUNT; i++)
1884                 enet_writel(priv, 0, ENET_MIB_REG(i));
1885
1886         /* register netdevice */
1887         dev->netdev_ops = &bcm_enet_ops;
1888         netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
1889
1890         dev->ethtool_ops = &bcm_enet_ethtool_ops;
1891         SET_NETDEV_DEV(dev, &pdev->dev);
1892
1893         ret = register_netdev(dev);
1894         if (ret)
1895                 goto out_unregister_mdio;
1896
1897         netif_carrier_off(dev);
1898         platform_set_drvdata(pdev, dev);
1899         priv->pdev = pdev;
1900         priv->net_dev = dev;
1901
1902         return 0;
1903
1904 out_unregister_mdio:
1905         if (priv->mii_bus)
1906                 mdiobus_unregister(priv->mii_bus);
1907
1908 out_free_mdio:
1909         if (priv->mii_bus)
1910                 mdiobus_free(priv->mii_bus);
1911
1912 out_uninit_hw:
1913         /* turn off mdc clock */
1914         enet_writel(priv, 0, ENET_MIISC_REG);
1915         if (priv->phy_clk) {
1916                 clk_disable_unprepare(priv->phy_clk);
1917                 clk_put(priv->phy_clk);
1918         }
1919
1920 out_put_clk_mac:
1921         clk_disable_unprepare(priv->mac_clk);
1922         clk_put(priv->mac_clk);
1923 out:
1924         free_netdev(dev);
1925         return ret;
1926 }
1927
1928
1929 /*
1930  * exit func, stops hardware and unregisters netdevice
1931  */
1932 static int bcm_enet_remove(struct platform_device *pdev)
1933 {
1934         struct bcm_enet_priv *priv;
1935         struct net_device *dev;
1936
1937         /* stop netdevice */
1938         dev = platform_get_drvdata(pdev);
1939         priv = netdev_priv(dev);
1940         unregister_netdev(dev);
1941
1942         /* turn off mdc clock */
1943         enet_writel(priv, 0, ENET_MIISC_REG);
1944
1945         if (priv->has_phy) {
1946                 mdiobus_unregister(priv->mii_bus);
1947                 mdiobus_free(priv->mii_bus);
1948         } else {
1949                 struct bcm63xx_enet_platform_data *pd;
1950
1951                 pd = dev_get_platdata(&pdev->dev);
1952                 if (pd && pd->mii_config)
1953                         pd->mii_config(dev, 0, bcm_enet_mdio_read_mii,
1954                                        bcm_enet_mdio_write_mii);
1955         }
1956
1957         /* disable hw block clocks */
1958         if (priv->phy_clk) {
1959                 clk_disable_unprepare(priv->phy_clk);
1960                 clk_put(priv->phy_clk);
1961         }
1962         clk_disable_unprepare(priv->mac_clk);
1963         clk_put(priv->mac_clk);
1964
1965         free_netdev(dev);
1966         return 0;
1967 }
1968
1969 struct platform_driver bcm63xx_enet_driver = {
1970         .probe  = bcm_enet_probe,
1971         .remove = bcm_enet_remove,
1972         .driver = {
1973                 .name   = "bcm63xx_enet",
1974                 .owner  = THIS_MODULE,
1975         },
1976 };
1977
1978 /*
1979  * switch mii access callbacks
1980  */
1981 static int bcmenet_sw_mdio_read(struct bcm_enet_priv *priv,
1982                                 int ext, int phy_id, int location)
1983 {
1984         u32 reg;
1985         int ret;
1986
1987         spin_lock_bh(&priv->enetsw_mdio_lock);
1988         enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
1989
1990         reg = ENETSW_MDIOC_RD_MASK |
1991                 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
1992                 (location << ENETSW_MDIOC_REG_SHIFT);
1993
1994         if (ext)
1995                 reg |= ENETSW_MDIOC_EXT_MASK;
1996
1997         enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
1998         udelay(50);
1999         ret = enetsw_readw(priv, ENETSW_MDIOD_REG);
2000         spin_unlock_bh(&priv->enetsw_mdio_lock);
2001         return ret;
2002 }
2003
2004 static void bcmenet_sw_mdio_write(struct bcm_enet_priv *priv,
2005                                  int ext, int phy_id, int location,
2006                                  uint16_t data)
2007 {
2008         u32 reg;
2009
2010         spin_lock_bh(&priv->enetsw_mdio_lock);
2011         enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
2012
2013         reg = ENETSW_MDIOC_WR_MASK |
2014                 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
2015                 (location << ENETSW_MDIOC_REG_SHIFT);
2016
2017         if (ext)
2018                 reg |= ENETSW_MDIOC_EXT_MASK;
2019
2020         reg |= data;
2021
2022         enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
2023         udelay(50);
2024         spin_unlock_bh(&priv->enetsw_mdio_lock);
2025 }
2026
2027 static inline int bcm_enet_port_is_rgmii(int portid)
2028 {
2029         return portid >= ENETSW_RGMII_PORT0;
2030 }
2031
2032 /*
2033  * enet sw PHY polling
2034  */
2035 static void swphy_poll_timer(unsigned long data)
2036 {
2037         struct bcm_enet_priv *priv = (struct bcm_enet_priv *)data;
2038         unsigned int i;
2039
2040         for (i = 0; i < priv->num_ports; i++) {
2041                 struct bcm63xx_enetsw_port *port;
2042                 int val, j, up, advertise, lpa, speed, duplex, media;
2043                 int external_phy = bcm_enet_port_is_rgmii(i);
2044                 u8 override;
2045
2046                 port = &priv->used_ports[i];
2047                 if (!port->used)
2048                         continue;
2049
2050                 if (port->bypass_link)
2051                         continue;
2052
2053                 /* dummy read to clear */
2054                 for (j = 0; j < 2; j++)
2055                         val = bcmenet_sw_mdio_read(priv, external_phy,
2056                                                    port->phy_id, MII_BMSR);
2057
2058                 if (val == 0xffff)
2059                         continue;
2060
2061                 up = (val & BMSR_LSTATUS) ? 1 : 0;
2062                 if (!(up ^ priv->sw_port_link[i]))
2063                         continue;
2064
2065                 priv->sw_port_link[i] = up;
2066
2067                 /* link changed */
2068                 if (!up) {
2069                         dev_info(&priv->pdev->dev, "link DOWN on %s\n",
2070                                  port->name);
2071                         enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2072                                       ENETSW_PORTOV_REG(i));
2073                         enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2074                                       ENETSW_PTCTRL_TXDIS_MASK,
2075                                       ENETSW_PTCTRL_REG(i));
2076                         continue;
2077                 }
2078
2079                 advertise = bcmenet_sw_mdio_read(priv, external_phy,
2080                                                  port->phy_id, MII_ADVERTISE);
2081
2082                 lpa = bcmenet_sw_mdio_read(priv, external_phy, port->phy_id,
2083                                            MII_LPA);
2084
2085                 /* figure out media and duplex from advertise and LPA values */
2086                 media = mii_nway_result(lpa & advertise);
2087                 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
2088
2089                 if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF))
2090                         speed = 100;
2091                 else
2092                         speed = 10;
2093
2094                 if (val & BMSR_ESTATEN) {
2095                         advertise = bcmenet_sw_mdio_read(priv, external_phy,
2096                                                 port->phy_id, MII_CTRL1000);
2097
2098                         lpa = bcmenet_sw_mdio_read(priv, external_phy,
2099                                                 port->phy_id, MII_STAT1000);
2100
2101                         if (advertise & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)
2102                                         && lpa & (LPA_1000FULL | LPA_1000HALF)) {
2103                                 speed = 1000;
2104                                 duplex = (lpa & LPA_1000FULL);
2105                         }
2106                 }
2107
2108                 dev_info(&priv->pdev->dev,
2109                          "link UP on %s, %dMbps, %s-duplex\n",
2110                          port->name, speed, duplex ? "full" : "half");
2111
2112                 override = ENETSW_PORTOV_ENABLE_MASK |
2113                         ENETSW_PORTOV_LINKUP_MASK;
2114
2115                 if (speed == 1000)
2116                         override |= ENETSW_IMPOV_1000_MASK;
2117                 else if (speed == 100)
2118                         override |= ENETSW_IMPOV_100_MASK;
2119                 if (duplex)
2120                         override |= ENETSW_IMPOV_FDX_MASK;
2121
2122                 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2123                 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2124         }
2125
2126         priv->swphy_poll.expires = jiffies + HZ;
2127         add_timer(&priv->swphy_poll);
2128 }
2129
2130 /*
2131  * open callback, allocate dma rings & buffers and start rx operation
2132  */
2133 static int bcm_enetsw_open(struct net_device *dev)
2134 {
2135         struct bcm_enet_priv *priv;
2136         struct device *kdev;
2137         int i, ret;
2138         unsigned int size;
2139         void *p;
2140         u32 val;
2141
2142         priv = netdev_priv(dev);
2143         kdev = &priv->pdev->dev;
2144
2145         /* mask all interrupts and request them */
2146         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2147         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
2148
2149         ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
2150                           0, dev->name, dev);
2151         if (ret)
2152                 goto out_freeirq;
2153
2154         if (priv->irq_tx != -1) {
2155                 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
2156                                   0, dev->name, dev);
2157                 if (ret)
2158                         goto out_freeirq_rx;
2159         }
2160
2161         /* allocate rx dma ring */
2162         size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
2163         p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
2164         if (!p) {
2165                 dev_err(kdev, "cannot allocate rx ring %u\n", size);
2166                 ret = -ENOMEM;
2167                 goto out_freeirq_tx;
2168         }
2169
2170         memset(p, 0, size);
2171         priv->rx_desc_alloc_size = size;
2172         priv->rx_desc_cpu = p;
2173
2174         /* allocate tx dma ring */
2175         size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
2176         p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
2177         if (!p) {
2178                 dev_err(kdev, "cannot allocate tx ring\n");
2179                 ret = -ENOMEM;
2180                 goto out_free_rx_ring;
2181         }
2182
2183         memset(p, 0, size);
2184         priv->tx_desc_alloc_size = size;
2185         priv->tx_desc_cpu = p;
2186
2187         priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size,
2188                                GFP_KERNEL);
2189         if (!priv->tx_skb) {
2190                 dev_err(kdev, "cannot allocate rx skb queue\n");
2191                 ret = -ENOMEM;
2192                 goto out_free_tx_ring;
2193         }
2194
2195         priv->tx_desc_count = priv->tx_ring_size;
2196         priv->tx_dirty_desc = 0;
2197         priv->tx_curr_desc = 0;
2198         spin_lock_init(&priv->tx_lock);
2199
2200         /* init & fill rx ring with skbs */
2201         priv->rx_skb = kzalloc(sizeof(struct sk_buff *) * priv->rx_ring_size,
2202                                GFP_KERNEL);
2203         if (!priv->rx_skb) {
2204                 dev_err(kdev, "cannot allocate rx skb queue\n");
2205                 ret = -ENOMEM;
2206                 goto out_free_tx_skb;
2207         }
2208
2209         priv->rx_desc_count = 0;
2210         priv->rx_dirty_desc = 0;
2211         priv->rx_curr_desc = 0;
2212
2213         /* disable all ports */
2214         for (i = 0; i < priv->num_ports; i++) {
2215                 enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2216                               ENETSW_PORTOV_REG(i));
2217                 enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2218                               ENETSW_PTCTRL_TXDIS_MASK,
2219                               ENETSW_PTCTRL_REG(i));
2220
2221                 priv->sw_port_link[i] = 0;
2222         }
2223
2224         /* reset mib */
2225         val = enetsw_readb(priv, ENETSW_GMCR_REG);
2226         val |= ENETSW_GMCR_RST_MIB_MASK;
2227         enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2228         mdelay(1);
2229         val &= ~ENETSW_GMCR_RST_MIB_MASK;
2230         enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2231         mdelay(1);
2232
2233         /* force CPU port state */
2234         val = enetsw_readb(priv, ENETSW_IMPOV_REG);
2235         val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK;
2236         enetsw_writeb(priv, val, ENETSW_IMPOV_REG);
2237
2238         /* enable switch forward engine */
2239         val = enetsw_readb(priv, ENETSW_SWMODE_REG);
2240         val |= ENETSW_SWMODE_FWD_EN_MASK;
2241         enetsw_writeb(priv, val, ENETSW_SWMODE_REG);
2242
2243         /* enable jumbo on all ports */
2244         enetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG);
2245         enetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG);
2246
2247         /* initialize flow control buffer allocation */
2248         enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
2249                         ENETDMA_BUFALLOC_REG(priv->rx_chan));
2250
2251         if (bcm_enet_refill_rx(dev)) {
2252                 dev_err(kdev, "cannot allocate rx skb queue\n");
2253                 ret = -ENOMEM;
2254                 goto out;
2255         }
2256
2257         /* write rx & tx ring addresses */
2258         enet_dmas_writel(priv, priv->rx_desc_dma,
2259                          ENETDMAS_RSTART_REG, priv->rx_chan);
2260         enet_dmas_writel(priv, priv->tx_desc_dma,
2261                          ENETDMAS_RSTART_REG, priv->tx_chan);
2262
2263         /* clear remaining state ram for rx & tx channel */
2264         enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
2265         enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
2266         enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
2267         enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
2268         enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
2269         enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
2270
2271         /* set dma maximum burst len */
2272         enet_dmac_writel(priv, priv->dma_maxburst,
2273                          ENETDMAC_MAXBURST, priv->rx_chan);
2274         enet_dmac_writel(priv, priv->dma_maxburst,
2275                          ENETDMAC_MAXBURST, priv->tx_chan);
2276
2277         /* set flow control low/high threshold to 1/3 / 2/3 */
2278         val = priv->rx_ring_size / 3;
2279         enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
2280         val = (priv->rx_ring_size * 2) / 3;
2281         enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
2282
2283         /* all set, enable mac and interrupts, start dma engine and
2284          * kick rx dma channel
2285          */
2286         wmb();
2287         enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
2288         enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
2289                          ENETDMAC_CHANCFG, priv->rx_chan);
2290
2291         /* watch "packet transferred" interrupt in rx and tx */
2292         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2293                          ENETDMAC_IR, priv->rx_chan);
2294         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2295                          ENETDMAC_IR, priv->tx_chan);
2296
2297         /* make sure we enable napi before rx interrupt  */
2298         napi_enable(&priv->napi);
2299
2300         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2301                          ENETDMAC_IRMASK, priv->rx_chan);
2302         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2303                          ENETDMAC_IRMASK, priv->tx_chan);
2304
2305         netif_carrier_on(dev);
2306         netif_start_queue(dev);
2307
2308         /* apply override config for bypass_link ports here. */
2309         for (i = 0; i < priv->num_ports; i++) {
2310                 struct bcm63xx_enetsw_port *port;
2311                 u8 override;
2312                 port = &priv->used_ports[i];
2313                 if (!port->used)
2314                         continue;
2315
2316                 if (!port->bypass_link)
2317                         continue;
2318
2319                 override = ENETSW_PORTOV_ENABLE_MASK |
2320                         ENETSW_PORTOV_LINKUP_MASK;
2321
2322                 switch (port->force_speed) {
2323                 case 1000:
2324                         override |= ENETSW_IMPOV_1000_MASK;
2325                         break;
2326                 case 100:
2327                         override |= ENETSW_IMPOV_100_MASK;
2328                         break;
2329                 case 10:
2330                         break;
2331                 default:
2332                         pr_warn("invalid forced speed on port %s: assume 10\n",
2333                                port->name);
2334                         break;
2335                 }
2336
2337                 if (port->force_duplex_full)
2338                         override |= ENETSW_IMPOV_FDX_MASK;
2339
2340
2341                 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2342                 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2343         }
2344
2345         /* start phy polling timer */
2346         init_timer(&priv->swphy_poll);
2347         priv->swphy_poll.function = swphy_poll_timer;
2348         priv->swphy_poll.data = (unsigned long)priv;
2349         priv->swphy_poll.expires = jiffies;
2350         add_timer(&priv->swphy_poll);
2351         return 0;
2352
2353 out:
2354         for (i = 0; i < priv->rx_ring_size; i++) {
2355                 struct bcm_enet_desc *desc;
2356
2357                 if (!priv->rx_skb[i])
2358                         continue;
2359
2360                 desc = &priv->rx_desc_cpu[i];
2361                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2362                                  DMA_FROM_DEVICE);
2363                 kfree_skb(priv->rx_skb[i]);
2364         }
2365         kfree(priv->rx_skb);
2366
2367 out_free_tx_skb:
2368         kfree(priv->tx_skb);
2369
2370 out_free_tx_ring:
2371         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2372                           priv->tx_desc_cpu, priv->tx_desc_dma);
2373
2374 out_free_rx_ring:
2375         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2376                           priv->rx_desc_cpu, priv->rx_desc_dma);
2377
2378 out_freeirq_tx:
2379         if (priv->irq_tx != -1)
2380                 free_irq(priv->irq_tx, dev);
2381
2382 out_freeirq_rx:
2383         free_irq(priv->irq_rx, dev);
2384
2385 out_freeirq:
2386         return ret;
2387 }
2388
2389 /* stop callback */
2390 static int bcm_enetsw_stop(struct net_device *dev)
2391 {
2392         struct bcm_enet_priv *priv;
2393         struct device *kdev;
2394         int i;
2395
2396         priv = netdev_priv(dev);
2397         kdev = &priv->pdev->dev;
2398
2399         del_timer_sync(&priv->swphy_poll);
2400         netif_stop_queue(dev);
2401         napi_disable(&priv->napi);
2402         del_timer_sync(&priv->rx_timeout);
2403
2404         /* mask all interrupts */
2405         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2406         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
2407
2408         /* disable dma & mac */
2409         bcm_enet_disable_dma(priv, priv->tx_chan);
2410         bcm_enet_disable_dma(priv, priv->rx_chan);
2411
2412         /* force reclaim of all tx buffers */
2413         bcm_enet_tx_reclaim(dev, 1);
2414
2415         /* free the rx skb ring */
2416         for (i = 0; i < priv->rx_ring_size; i++) {
2417                 struct bcm_enet_desc *desc;
2418
2419                 if (!priv->rx_skb[i])
2420                         continue;
2421
2422                 desc = &priv->rx_desc_cpu[i];
2423                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2424                                  DMA_FROM_DEVICE);
2425                 kfree_skb(priv->rx_skb[i]);
2426         }
2427
2428         /* free remaining allocated memory */
2429         kfree(priv->rx_skb);
2430         kfree(priv->tx_skb);
2431         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2432                           priv->rx_desc_cpu, priv->rx_desc_dma);
2433         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2434                           priv->tx_desc_cpu, priv->tx_desc_dma);
2435         if (priv->irq_tx != -1)
2436                 free_irq(priv->irq_tx, dev);
2437         free_irq(priv->irq_rx, dev);
2438
2439         return 0;
2440 }
2441
2442 /* try to sort out phy external status by walking the used_port field
2443  * in the bcm_enet_priv structure. in case the phy address is not
2444  * assigned to any physical port on the switch, assume it is external
2445  * (and yell at the user).
2446  */
2447 static int bcm_enetsw_phy_is_external(struct bcm_enet_priv *priv, int phy_id)
2448 {
2449         int i;
2450
2451         for (i = 0; i < priv->num_ports; ++i) {
2452                 if (!priv->used_ports[i].used)
2453                         continue;
2454                 if (priv->used_ports[i].phy_id == phy_id)
2455                         return bcm_enet_port_is_rgmii(i);
2456         }
2457
2458         printk_once(KERN_WARNING  "bcm63xx_enet: could not find a used port with phy_id %i, assuming phy is external\n",
2459                     phy_id);
2460         return 1;
2461 }
2462
2463 /* can't use bcmenet_sw_mdio_read directly as we need to sort out
2464  * external/internal status of the given phy_id first.
2465  */
2466 static int bcm_enetsw_mii_mdio_read(struct net_device *dev, int phy_id,
2467                                     int location)
2468 {
2469         struct bcm_enet_priv *priv;
2470
2471         priv = netdev_priv(dev);
2472         return bcmenet_sw_mdio_read(priv,
2473                                     bcm_enetsw_phy_is_external(priv, phy_id),
2474                                     phy_id, location);
2475 }
2476
2477 /* can't use bcmenet_sw_mdio_write directly as we need to sort out
2478  * external/internal status of the given phy_id first.
2479  */
2480 static void bcm_enetsw_mii_mdio_write(struct net_device *dev, int phy_id,
2481                                       int location,
2482                                       int val)
2483 {
2484         struct bcm_enet_priv *priv;
2485
2486         priv = netdev_priv(dev);
2487         bcmenet_sw_mdio_write(priv, bcm_enetsw_phy_is_external(priv, phy_id),
2488                               phy_id, location, val);
2489 }
2490
2491 static int bcm_enetsw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2492 {
2493         struct mii_if_info mii;
2494
2495         mii.dev = dev;
2496         mii.mdio_read = bcm_enetsw_mii_mdio_read;
2497         mii.mdio_write = bcm_enetsw_mii_mdio_write;
2498         mii.phy_id = 0;
2499         mii.phy_id_mask = 0x3f;
2500         mii.reg_num_mask = 0x1f;
2501         return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
2502
2503 }
2504
2505 static const struct net_device_ops bcm_enetsw_ops = {
2506         .ndo_open               = bcm_enetsw_open,
2507         .ndo_stop               = bcm_enetsw_stop,
2508         .ndo_start_xmit         = bcm_enet_start_xmit,
2509         .ndo_change_mtu         = bcm_enet_change_mtu,
2510         .ndo_do_ioctl           = bcm_enetsw_ioctl,
2511 };
2512
2513
2514 static const struct bcm_enet_stats bcm_enetsw_gstrings_stats[] = {
2515         { "rx_packets", DEV_STAT(rx_packets), -1 },
2516         { "tx_packets", DEV_STAT(tx_packets), -1 },
2517         { "rx_bytes", DEV_STAT(rx_bytes), -1 },
2518         { "tx_bytes", DEV_STAT(tx_bytes), -1 },
2519         { "rx_errors", DEV_STAT(rx_errors), -1 },
2520         { "tx_errors", DEV_STAT(tx_errors), -1 },
2521         { "rx_dropped", DEV_STAT(rx_dropped), -1 },
2522         { "tx_dropped", DEV_STAT(tx_dropped), -1 },
2523
2524         { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETHSW_MIB_RX_GD_OCT },
2525         { "tx_unicast", GEN_STAT(mib.tx_unicast), ETHSW_MIB_RX_BRDCAST },
2526         { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETHSW_MIB_RX_BRDCAST },
2527         { "tx_multicast", GEN_STAT(mib.tx_mult), ETHSW_MIB_RX_MULT },
2528         { "tx_64_octets", GEN_STAT(mib.tx_64), ETHSW_MIB_RX_64 },
2529         { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETHSW_MIB_RX_65_127 },
2530         { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETHSW_MIB_RX_128_255 },
2531         { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETHSW_MIB_RX_256_511 },
2532         { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETHSW_MIB_RX_512_1023},
2533         { "tx_1024_1522_oct", GEN_STAT(mib.tx_1024_max),
2534           ETHSW_MIB_RX_1024_1522 },
2535         { "tx_1523_2047_oct", GEN_STAT(mib.tx_1523_2047),
2536           ETHSW_MIB_RX_1523_2047 },
2537         { "tx_2048_4095_oct", GEN_STAT(mib.tx_2048_4095),
2538           ETHSW_MIB_RX_2048_4095 },
2539         { "tx_4096_8191_oct", GEN_STAT(mib.tx_4096_8191),
2540           ETHSW_MIB_RX_4096_8191 },
2541         { "tx_8192_9728_oct", GEN_STAT(mib.tx_8192_9728),
2542           ETHSW_MIB_RX_8192_9728 },
2543         { "tx_oversize", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR },
2544         { "tx_oversize_drop", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR_DISC },
2545         { "tx_dropped", GEN_STAT(mib.tx_drop), ETHSW_MIB_RX_DROP },
2546         { "tx_undersize", GEN_STAT(mib.tx_underrun), ETHSW_MIB_RX_UND },
2547         { "tx_pause", GEN_STAT(mib.tx_pause), ETHSW_MIB_RX_PAUSE },
2548
2549         { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETHSW_MIB_TX_ALL_OCT },
2550         { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETHSW_MIB_TX_BRDCAST },
2551         { "rx_multicast", GEN_STAT(mib.rx_mult), ETHSW_MIB_TX_MULT },
2552         { "rx_unicast", GEN_STAT(mib.rx_unicast), ETHSW_MIB_TX_MULT },
2553         { "rx_pause", GEN_STAT(mib.rx_pause), ETHSW_MIB_TX_PAUSE },
2554         { "rx_dropped", GEN_STAT(mib.rx_drop), ETHSW_MIB_TX_DROP_PKTS },
2555
2556 };
2557
2558 #define BCM_ENETSW_STATS_LEN    \
2559         (sizeof(bcm_enetsw_gstrings_stats) / sizeof(struct bcm_enet_stats))
2560
2561 static void bcm_enetsw_get_strings(struct net_device *netdev,
2562                                    u32 stringset, u8 *data)
2563 {
2564         int i;
2565
2566         switch (stringset) {
2567         case ETH_SS_STATS:
2568                 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2569                         memcpy(data + i * ETH_GSTRING_LEN,
2570                                bcm_enetsw_gstrings_stats[i].stat_string,
2571                                ETH_GSTRING_LEN);
2572                 }
2573                 break;
2574         }
2575 }
2576
2577 static int bcm_enetsw_get_sset_count(struct net_device *netdev,
2578                                      int string_set)
2579 {
2580         switch (string_set) {
2581         case ETH_SS_STATS:
2582                 return BCM_ENETSW_STATS_LEN;
2583         default:
2584                 return -EINVAL;
2585         }
2586 }
2587
2588 static void bcm_enetsw_get_drvinfo(struct net_device *netdev,
2589                                    struct ethtool_drvinfo *drvinfo)
2590 {
2591         strncpy(drvinfo->driver, bcm_enet_driver_name, 32);
2592         strncpy(drvinfo->version, bcm_enet_driver_version, 32);
2593         strncpy(drvinfo->fw_version, "N/A", 32);
2594         strncpy(drvinfo->bus_info, "bcm63xx", 32);
2595 }
2596
2597 static void bcm_enetsw_get_ethtool_stats(struct net_device *netdev,
2598                                          struct ethtool_stats *stats,
2599                                          u64 *data)
2600 {
2601         struct bcm_enet_priv *priv;
2602         int i;
2603
2604         priv = netdev_priv(netdev);
2605
2606         for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2607                 const struct bcm_enet_stats *s;
2608                 u32 lo, hi;
2609                 char *p;
2610                 int reg;
2611
2612                 s = &bcm_enetsw_gstrings_stats[i];
2613
2614                 reg = s->mib_reg;
2615                 if (reg == -1)
2616                         continue;
2617
2618                 lo = enetsw_readl(priv, ENETSW_MIB_REG(reg));
2619                 p = (char *)priv + s->stat_offset;
2620
2621                 if (s->sizeof_stat == sizeof(u64)) {
2622                         hi = enetsw_readl(priv, ENETSW_MIB_REG(reg + 1));
2623                         *(u64 *)p = ((u64)hi << 32 | lo);
2624                 } else {
2625                         *(u32 *)p = lo;
2626                 }
2627         }
2628
2629         for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2630                 const struct bcm_enet_stats *s;
2631                 char *p;
2632
2633                 s = &bcm_enetsw_gstrings_stats[i];
2634
2635                 if (s->mib_reg == -1)
2636                         p = (char *)&netdev->stats + s->stat_offset;
2637                 else
2638                         p = (char *)priv + s->stat_offset;
2639
2640                 data[i] = (s->sizeof_stat == sizeof(u64)) ?
2641                         *(u64 *)p : *(u32 *)p;
2642         }
2643 }
2644
2645 static void bcm_enetsw_get_ringparam(struct net_device *dev,
2646                                      struct ethtool_ringparam *ering)
2647 {
2648         struct bcm_enet_priv *priv;
2649
2650         priv = netdev_priv(dev);
2651
2652         /* rx/tx ring is actually only limited by memory */
2653         ering->rx_max_pending = 8192;
2654         ering->tx_max_pending = 8192;
2655         ering->rx_mini_max_pending = 0;
2656         ering->rx_jumbo_max_pending = 0;
2657         ering->rx_pending = priv->rx_ring_size;
2658         ering->tx_pending = priv->tx_ring_size;
2659 }
2660
2661 static int bcm_enetsw_set_ringparam(struct net_device *dev,
2662                                     struct ethtool_ringparam *ering)
2663 {
2664         struct bcm_enet_priv *priv;
2665         int was_running;
2666
2667         priv = netdev_priv(dev);
2668
2669         was_running = 0;
2670         if (netif_running(dev)) {
2671                 bcm_enetsw_stop(dev);
2672                 was_running = 1;
2673         }
2674
2675         priv->rx_ring_size = ering->rx_pending;
2676         priv->tx_ring_size = ering->tx_pending;
2677
2678         if (was_running) {
2679                 int err;
2680
2681                 err = bcm_enetsw_open(dev);
2682                 if (err)
2683                         dev_close(dev);
2684         }
2685         return 0;
2686 }
2687
2688 static struct ethtool_ops bcm_enetsw_ethtool_ops = {
2689         .get_strings            = bcm_enetsw_get_strings,
2690         .get_sset_count         = bcm_enetsw_get_sset_count,
2691         .get_ethtool_stats      = bcm_enetsw_get_ethtool_stats,
2692         .get_drvinfo            = bcm_enetsw_get_drvinfo,
2693         .get_ringparam          = bcm_enetsw_get_ringparam,
2694         .set_ringparam          = bcm_enetsw_set_ringparam,
2695 };
2696
2697 /* allocate netdevice, request register memory and register device. */
2698 static int bcm_enetsw_probe(struct platform_device *pdev)
2699 {
2700         struct bcm_enet_priv *priv;
2701         struct net_device *dev;
2702         struct bcm63xx_enetsw_platform_data *pd;
2703         struct resource *res_mem;
2704         int ret, irq_rx, irq_tx;
2705
2706         /* stop if shared driver failed, assume driver->probe will be
2707          * called in the same order we register devices (correct ?)
2708          */
2709         if (!bcm_enet_shared_base[0])
2710                 return -ENODEV;
2711
2712         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2713         irq_rx = platform_get_irq(pdev, 0);
2714         irq_tx = platform_get_irq(pdev, 1);
2715         if (!res_mem || irq_rx < 0)
2716                 return -ENODEV;
2717
2718         ret = 0;
2719         dev = alloc_etherdev(sizeof(*priv));
2720         if (!dev)
2721                 return -ENOMEM;
2722         priv = netdev_priv(dev);
2723         memset(priv, 0, sizeof(*priv));
2724
2725         /* initialize default and fetch platform data */
2726         priv->enet_is_sw = true;
2727         priv->irq_rx = irq_rx;
2728         priv->irq_tx = irq_tx;
2729         priv->rx_ring_size = BCMENET_DEF_RX_DESC;
2730         priv->tx_ring_size = BCMENET_DEF_TX_DESC;
2731         priv->dma_maxburst = BCMENETSW_DMA_MAXBURST;
2732
2733         pd = dev_get_platdata(&pdev->dev);
2734         if (pd) {
2735                 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2736                 memcpy(priv->used_ports, pd->used_ports,
2737                        sizeof(pd->used_ports));
2738                 priv->num_ports = pd->num_ports;
2739                 priv->dma_has_sram = pd->dma_has_sram;
2740                 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
2741                 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
2742                 priv->dma_chan_width = pd->dma_chan_width;
2743         }
2744
2745         ret = compute_hw_mtu(priv, dev->mtu);
2746         if (ret)
2747                 goto out;
2748
2749         if (!request_mem_region(res_mem->start, resource_size(res_mem),
2750                                 "bcm63xx_enetsw")) {
2751                 ret = -EBUSY;
2752                 goto out;
2753         }
2754
2755         priv->base = ioremap(res_mem->start, resource_size(res_mem));
2756         if (priv->base == NULL) {
2757                 ret = -ENOMEM;
2758                 goto out_release_mem;
2759         }
2760
2761         priv->mac_clk = clk_get(&pdev->dev, "enetsw");
2762         if (IS_ERR(priv->mac_clk)) {
2763                 ret = PTR_ERR(priv->mac_clk);
2764                 goto out_unmap;
2765         }
2766         clk_enable(priv->mac_clk);
2767
2768         priv->rx_chan = 0;
2769         priv->tx_chan = 1;
2770         spin_lock_init(&priv->rx_lock);
2771
2772         /* init rx timeout (used for oom) */
2773         init_timer(&priv->rx_timeout);
2774         priv->rx_timeout.function = bcm_enet_refill_rx_timer;
2775         priv->rx_timeout.data = (unsigned long)dev;
2776
2777         /* register netdevice */
2778         dev->netdev_ops = &bcm_enetsw_ops;
2779         netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
2780         dev->ethtool_ops = &bcm_enetsw_ethtool_ops;
2781         SET_NETDEV_DEV(dev, &pdev->dev);
2782
2783         spin_lock_init(&priv->enetsw_mdio_lock);
2784
2785         ret = register_netdev(dev);
2786         if (ret)
2787                 goto out_put_clk;
2788
2789         netif_carrier_off(dev);
2790         platform_set_drvdata(pdev, dev);
2791         priv->pdev = pdev;
2792         priv->net_dev = dev;
2793
2794         return 0;
2795
2796 out_put_clk:
2797         clk_put(priv->mac_clk);
2798
2799 out_unmap:
2800         iounmap(priv->base);
2801
2802 out_release_mem:
2803         release_mem_region(res_mem->start, resource_size(res_mem));
2804 out:
2805         free_netdev(dev);
2806         return ret;
2807 }
2808
2809
2810 /* exit func, stops hardware and unregisters netdevice */
2811 static int bcm_enetsw_remove(struct platform_device *pdev)
2812 {
2813         struct bcm_enet_priv *priv;
2814         struct net_device *dev;
2815         struct resource *res;
2816
2817         /* stop netdevice */
2818         dev = platform_get_drvdata(pdev);
2819         priv = netdev_priv(dev);
2820         unregister_netdev(dev);
2821
2822         /* release device resources */
2823         iounmap(priv->base);
2824         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2825         release_mem_region(res->start, resource_size(res));
2826
2827         free_netdev(dev);
2828         return 0;
2829 }
2830
2831 struct platform_driver bcm63xx_enetsw_driver = {
2832         .probe  = bcm_enetsw_probe,
2833         .remove = bcm_enetsw_remove,
2834         .driver = {
2835                 .name   = "bcm63xx_enetsw",
2836                 .owner  = THIS_MODULE,
2837         },
2838 };
2839
2840 /* reserve & remap memory space shared between all macs */
2841 static int bcm_enet_shared_probe(struct platform_device *pdev)
2842 {
2843         struct resource *res;
2844         void __iomem *p[3];
2845         unsigned int i;
2846
2847         memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base));
2848
2849         for (i = 0; i < 3; i++) {
2850                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
2851                 p[i] = devm_ioremap_resource(&pdev->dev, res);
2852                 if (IS_ERR(p[i]))
2853                         return PTR_ERR(p[i]);
2854         }
2855
2856         memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base));
2857
2858         return 0;
2859 }
2860
2861 static int bcm_enet_shared_remove(struct platform_device *pdev)
2862 {
2863         return 0;
2864 }
2865
2866 /* this "shared" driver is needed because both macs share a single
2867  * address space
2868  */
2869 struct platform_driver bcm63xx_enet_shared_driver = {
2870         .probe  = bcm_enet_shared_probe,
2871         .remove = bcm_enet_shared_remove,
2872         .driver = {
2873                 .name   = "bcm63xx_enet_shared",
2874                 .owner  = THIS_MODULE,
2875         },
2876 };
2877
2878 static struct platform_driver * const drivers[] = {
2879         &bcm63xx_enet_shared_driver,
2880         &bcm63xx_enet_driver,
2881         &bcm63xx_enetsw_driver,
2882 };
2883
2884 /* entry point */
2885 static int __init bcm_enet_init(void)
2886 {
2887         return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
2888 }
2889
2890 static void __exit bcm_enet_exit(void)
2891 {
2892         platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
2893 }
2894
2895
2896 module_init(bcm_enet_init);
2897 module_exit(bcm_enet_exit);
2898
2899 MODULE_DESCRIPTION("BCM63xx internal ethernet mac driver");
2900 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
2901 MODULE_LICENSE("GPL");