drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c

   1 /* bnx2x_ethtool.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2011 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/ethtool.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/types.h>
  23 #include <linux/sched.h>
  24 #include <linux/crc32.h>
  25
  26
  27 #include "bnx2x.h"
  28 #include "bnx2x_cmn.h"
  29 #include "bnx2x_dump.h"
  30 #include "bnx2x_init.h"
  31 #include "bnx2x_sp.h"
  32
  33 /* Note: in the format strings below %s is replaced by the queue-name which is
  34  * either its index or 'fcoe' for the fcoe queue. Make sure the format string
  35  * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
  36  */
  37 #define MAX_QUEUE_NAME_LEN      4
  38 static const struct {
  39         long offset;
  40         int size;
  41         char string[ETH_GSTRING_LEN];
  42 } bnx2x_q_stats_arr[] = {
  43 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
  44         { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
  45                                                 8, "[%s]: rx_ucast_packets" },
  46         { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
  47                                                 8, "[%s]: rx_mcast_packets" },
  48         { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
  49                                                 8, "[%s]: rx_bcast_packets" },
  50         { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
  51         { Q_STATS_OFFSET32(rx_err_discard_pkt),
  52                                          4, "[%s]: rx_phy_ip_err_discards"},
  53         { Q_STATS_OFFSET32(rx_skb_alloc_failed),
  54                                          4, "[%s]: rx_skb_alloc_discard" },
  55         { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
  56
  57         { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
  58 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
  59                                                 8, "[%s]: tx_ucast_packets" },
  60         { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
  61                                                 8, "[%s]: tx_mcast_packets" },
  62         { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
  63                                                 8, "[%s]: tx_bcast_packets" },
  64         { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
  65                                                 8, "[%s]: tpa_aggregations" },
  66         { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
  67                                         8, "[%s]: tpa_aggregated_frames"},
  68         { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}
  69 };
  70
  71 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
  72
  73 static const struct {
  74         long offset;
  75         int size;
  76         u32 flags;
  77 #define STATS_FLAGS_PORT                1
  78 #define STATS_FLAGS_FUNC                2
  79 #define STATS_FLAGS_BOTH                (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
  80         char string[ETH_GSTRING_LEN];
  81 } bnx2x_stats_arr[] = {
  82 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
  83                                 8, STATS_FLAGS_BOTH, "rx_bytes" },
  84         { STATS_OFFSET32(error_bytes_received_hi),
  85                                 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
  86         { STATS_OFFSET32(total_unicast_packets_received_hi),
  87                                 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
  88         { STATS_OFFSET32(total_multicast_packets_received_hi),
  89                                 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
  90         { STATS_OFFSET32(total_broadcast_packets_received_hi),
  91                                 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
  92         { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
  93                                 8, STATS_FLAGS_PORT, "rx_crc_errors" },
  94         { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
  95                                 8, STATS_FLAGS_PORT, "rx_align_errors" },
  96         { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
  97                                 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
  98         { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
  99                                 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
 100 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
 101                                 8, STATS_FLAGS_PORT, "rx_fragments" },
 102         { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
 103                                 8, STATS_FLAGS_PORT, "rx_jabbers" },
 104         { STATS_OFFSET32(no_buff_discard_hi),
 105                                 8, STATS_FLAGS_BOTH, "rx_discards" },
 106         { STATS_OFFSET32(mac_filter_discard),
 107                                 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
 108         { STATS_OFFSET32(mf_tag_discard),
 109                                 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
 110         { STATS_OFFSET32(pfc_frames_received_hi),
 111                                 8, STATS_FLAGS_PORT, "pfc_frames_received" },
 112         { STATS_OFFSET32(pfc_frames_sent_hi),
 113                                 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
 114         { STATS_OFFSET32(brb_drop_hi),
 115                                 8, STATS_FLAGS_PORT, "rx_brb_discard" },
 116         { STATS_OFFSET32(brb_truncate_hi),
 117                                 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
 118         { STATS_OFFSET32(pause_frames_received_hi),
 119                                 8, STATS_FLAGS_PORT, "rx_pause_frames" },
 120         { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
 121                                 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
 122         { STATS_OFFSET32(nig_timer_max),
 123                         4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
 124 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
 125                                 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
 126         { STATS_OFFSET32(rx_skb_alloc_failed),
 127                                 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
 128         { STATS_OFFSET32(hw_csum_err),
 129                                 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
 130
 131         { STATS_OFFSET32(total_bytes_transmitted_hi),
 132                                 8, STATS_FLAGS_BOTH, "tx_bytes" },
 133         { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
 134                                 8, STATS_FLAGS_PORT, "tx_error_bytes" },
 135         { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
 136                                 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
 137         { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
 138                                 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
 139         { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
 140                                 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
 141         { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
 142                                 8, STATS_FLAGS_PORT, "tx_mac_errors" },
 143         { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
 144                                 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
 145 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
 146                                 8, STATS_FLAGS_PORT, "tx_single_collisions" },
 147         { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
 148                                 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
 149         { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
 150                                 8, STATS_FLAGS_PORT, "tx_deferred" },
 151         { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
 152                                 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
 153         { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
 154                                 8, STATS_FLAGS_PORT, "tx_late_collisions" },
 155         { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
 156                                 8, STATS_FLAGS_PORT, "tx_total_collisions" },
 157         { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
 158                                 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
 159         { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
 160                         8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
 161         { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
 162                         8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
 163         { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
 164                         8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
 165 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
 166                         8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
 167         { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
 168                         8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
 169         { STATS_OFFSET32(etherstatspktsover1522octets_hi),
 170                         8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
 171         { STATS_OFFSET32(pause_frames_sent_hi),
 172                                 8, STATS_FLAGS_PORT, "tx_pause_frames" },
 173         { STATS_OFFSET32(total_tpa_aggregations_hi),
 174                         8, STATS_FLAGS_FUNC, "tpa_aggregations" },
 175         { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
 176                         8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
 177         { STATS_OFFSET32(total_tpa_bytes_hi),
 178                         8, STATS_FLAGS_FUNC, "tpa_bytes"}
 179 };
 180
 181 #define BNX2X_NUM_STATS         ARRAY_SIZE(bnx2x_stats_arr)
 182 static int bnx2x_get_port_type(struct bnx2x *bp)
 183 {
 184         int port_type;
 185         u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
 186         switch (bp->link_params.phy[phy_idx].media_type) {
 187         case ETH_PHY_SFP_FIBER:
 188         case ETH_PHY_XFP_FIBER:
 189         case ETH_PHY_KR:
 190         case ETH_PHY_CX4:
 191                 port_type = PORT_FIBRE;
 192                 break;
 193         case ETH_PHY_DA_TWINAX:
 194                 port_type = PORT_DA;
 195                 break;
 196         case ETH_PHY_BASE_T:
 197                 port_type = PORT_TP;
 198                 break;
 199         case ETH_PHY_NOT_PRESENT:
 200                 port_type = PORT_NONE;
 201                 break;
 202         case ETH_PHY_UNSPECIFIED:
 203         default:
 204                 port_type = PORT_OTHER;
 205                 break;
 206         }
 207         return port_type;
 208 }
 209
 210 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 211 {
 212         struct bnx2x *bp = netdev_priv(dev);
 213         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
 214
 215         /* Dual Media boards present all available port types */
 216         cmd->supported = bp->port.supported[cfg_idx] |
 217                 (bp->port.supported[cfg_idx ^ 1] &
 218                  (SUPPORTED_TP | SUPPORTED_FIBRE));
 219         cmd->advertising = bp->port.advertising[cfg_idx];
 220
 221         if ((bp->state == BNX2X_STATE_OPEN) &&
 222             !(bp->flags & MF_FUNC_DIS) &&
 223             (bp->link_vars.link_up)) {
 224                 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
 225                 cmd->duplex = bp->link_vars.duplex;
 226         } else {
 227                 ethtool_cmd_speed_set(
 228                         cmd, bp->link_params.req_line_speed[cfg_idx]);
 229                 cmd->duplex = bp->link_params.req_duplex[cfg_idx];
 230         }
 231
 232         if (IS_MF(bp))
 233                 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
 234
 235         cmd->port = bnx2x_get_port_type(bp);
 236
 237         cmd->phy_address = bp->mdio.prtad;
 238         cmd->transceiver = XCVR_INTERNAL;
 239
 240         if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
 241                 cmd->autoneg = AUTONEG_ENABLE;
 242         else
 243                 cmd->autoneg = AUTONEG_DISABLE;
 244
 245         cmd->maxtxpkt = 0;
 246         cmd->maxrxpkt = 0;
 247
 248         DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
 249            "  supported 0x%x  advertising 0x%x  speed %u\n"
 250            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 251            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 252            cmd->cmd, cmd->supported, cmd->advertising,
 253            ethtool_cmd_speed(cmd),
 254            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 255            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 256
 257         return 0;
 258 }
 259
 260 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 261 {
 262         struct bnx2x *bp = netdev_priv(dev);
 263         u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
 264         u32 speed;
 265
 266         if (IS_MF_SD(bp))
 267                 return 0;
 268
 269         DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
 270            "  supported 0x%x  advertising 0x%x  speed %u\n"
 271            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 272            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 273            cmd->cmd, cmd->supported, cmd->advertising,
 274            ethtool_cmd_speed(cmd),
 275            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 276            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 277
 278         speed = ethtool_cmd_speed(cmd);
 279
 280         if (IS_MF_SI(bp)) {
 281                 u32 part;
 282                 u32 line_speed = bp->link_vars.line_speed;
 283
 284                 /* use 10G if no link detected */
 285                 if (!line_speed)
 286                         line_speed = 10000;
 287
 288                 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
 289                         BNX2X_DEV_INFO("To set speed BC %X or higher "
 290                                        "is required, please upgrade BC\n",
 291                                        REQ_BC_VER_4_SET_MF_BW);
 292                         return -EINVAL;
 293                 }
 294
 295                 part = (speed * 100) / line_speed;
 296
 297                 if (line_speed < speed || !part) {
 298                         BNX2X_DEV_INFO("Speed setting should be in a range "
 299                                        "from 1%% to 100%% "
 300                                        "of actual line speed\n");
 301                         return -EINVAL;
 302                 }
 303
 304                 if (bp->state != BNX2X_STATE_OPEN)
 305                         /* store value for following "load" */
 306                         bp->pending_max = part;
 307                 else
 308                         bnx2x_update_max_mf_config(bp, part);
 309
 310                 return 0;
 311         }
 312
 313         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 314         old_multi_phy_config = bp->link_params.multi_phy_config;
 315         switch (cmd->port) {
 316         case PORT_TP:
 317                 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
 318                         break; /* no port change */
 319
 320                 if (!(bp->port.supported[0] & SUPPORTED_TP ||
 321                       bp->port.supported[1] & SUPPORTED_TP)) {
 322                         DP(NETIF_MSG_LINK, "Unsupported port type\n");
 323                         return -EINVAL;
 324                 }
 325                 bp->link_params.multi_phy_config &=
 326                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 327                 if (bp->link_params.multi_phy_config &
 328                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 329                         bp->link_params.multi_phy_config |=
 330                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 331                 else
 332                         bp->link_params.multi_phy_config |=
 333                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 334                 break;
 335         case PORT_FIBRE:
 336         case PORT_DA:
 337                 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
 338                         break; /* no port change */
 339
 340                 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
 341                       bp->port.supported[1] & SUPPORTED_FIBRE)) {
 342                         DP(NETIF_MSG_LINK, "Unsupported port type\n");
 343                         return -EINVAL;
 344                 }
 345                 bp->link_params.multi_phy_config &=
 346                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 347                 if (bp->link_params.multi_phy_config &
 348                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 349                         bp->link_params.multi_phy_config |=
 350                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 351                 else
 352                         bp->link_params.multi_phy_config |=
 353                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 354                 break;
 355         default:
 356                 DP(NETIF_MSG_LINK, "Unsupported port type\n");
 357                 return -EINVAL;
 358         }
 359         /* Save new config in case command complete successully */
 360         new_multi_phy_config = bp->link_params.multi_phy_config;
 361         /* Get the new cfg_idx */
 362         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 363         /* Restore old config in case command failed */
 364         bp->link_params.multi_phy_config = old_multi_phy_config;
 365         DP(NETIF_MSG_LINK, "cfg_idx = %x\n", cfg_idx);
 366
 367         if (cmd->autoneg == AUTONEG_ENABLE) {
 368                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
 369                         DP(NETIF_MSG_LINK, "Autoneg not supported\n");
 370                         return -EINVAL;
 371                 }
 372
 373                 /* advertise the requested speed and duplex if supported */
 374                 if (cmd->advertising & ~(bp->port.supported[cfg_idx])) {
 375                         DP(NETIF_MSG_LINK, "Advertisement parameters "
 376                                            "are not supported\n");
 377                         return -EINVAL;
 378                 }
 379
 380                 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
 381                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 382                 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
 383                                          cmd->advertising);
 384                 if (cmd->advertising) {
 385
 386                         bp->link_params.speed_cap_mask[cfg_idx] = 0;
 387                         if (cmd->advertising & ADVERTISED_10baseT_Half) {
 388                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 389                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
 390                         }
 391                         if (cmd->advertising & ADVERTISED_10baseT_Full)
 392                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 393                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
 394
 395                         if (cmd->advertising & ADVERTISED_100baseT_Full)
 396                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 397                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
 398
 399                         if (cmd->advertising & ADVERTISED_100baseT_Half) {
 400                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 401                                      PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
 402                         }
 403                         if (cmd->advertising & ADVERTISED_1000baseT_Half) {
 404                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 405                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
 406                         }
 407                         if (cmd->advertising & (ADVERTISED_1000baseT_Full |
 408                                                 ADVERTISED_1000baseKX_Full))
 409                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 410                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
 411
 412                         if (cmd->advertising & (ADVERTISED_10000baseT_Full |
 413                                                 ADVERTISED_10000baseKX4_Full |
 414                                                 ADVERTISED_10000baseKR_Full))
 415                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 416                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
 417                 }
 418         } else { /* forced speed */
 419                 /* advertise the requested speed and duplex if supported */
 420                 switch (speed) {
 421                 case SPEED_10:
 422                         if (cmd->duplex == DUPLEX_FULL) {
 423                                 if (!(bp->port.supported[cfg_idx] &
 424                                       SUPPORTED_10baseT_Full)) {
 425                                         DP(NETIF_MSG_LINK,
 426                                            "10M full not supported\n");
 427                                         return -EINVAL;
 428                                 }
 429
 430                                 advertising = (ADVERTISED_10baseT_Full |
 431                                                ADVERTISED_TP);
 432                         } else {
 433                                 if (!(bp->port.supported[cfg_idx] &
 434                                       SUPPORTED_10baseT_Half)) {
 435                                         DP(NETIF_MSG_LINK,
 436                                            "10M half not supported\n");
 437                                         return -EINVAL;
 438                                 }
 439
 440                                 advertising = (ADVERTISED_10baseT_Half |
 441                                                ADVERTISED_TP);
 442                         }
 443                         break;
 444
 445                 case SPEED_100:
 446                         if (cmd->duplex == DUPLEX_FULL) {
 447                                 if (!(bp->port.supported[cfg_idx] &
 448                                                 SUPPORTED_100baseT_Full)) {
 449                                         DP(NETIF_MSG_LINK,
 450                                            "100M full not supported\n");
 451                                         return -EINVAL;
 452                                 }
 453
 454                                 advertising = (ADVERTISED_100baseT_Full |
 455                                                ADVERTISED_TP);
 456                         } else {
 457                                 if (!(bp->port.supported[cfg_idx] &
 458                                                 SUPPORTED_100baseT_Half)) {
 459                                         DP(NETIF_MSG_LINK,
 460                                            "100M half not supported\n");
 461                                         return -EINVAL;
 462                                 }
 463
 464                                 advertising = (ADVERTISED_100baseT_Half |
 465                                                ADVERTISED_TP);
 466                         }
 467                         break;
 468
 469                 case SPEED_1000:
 470                         if (cmd->duplex != DUPLEX_FULL) {
 471                                 DP(NETIF_MSG_LINK, "1G half not supported\n");
 472                                 return -EINVAL;
 473                         }
 474
 475                         if (!(bp->port.supported[cfg_idx] &
 476                               SUPPORTED_1000baseT_Full)) {
 477                                 DP(NETIF_MSG_LINK, "1G full not supported\n");
 478                                 return -EINVAL;
 479                         }
 480
 481                         advertising = (ADVERTISED_1000baseT_Full |
 482                                        ADVERTISED_TP);
 483                         break;
 484
 485                 case SPEED_2500:
 486                         if (cmd->duplex != DUPLEX_FULL) {
 487                                 DP(NETIF_MSG_LINK,
 488                                    "2.5G half not supported\n");
 489                                 return -EINVAL;
 490                         }
 491
 492                         if (!(bp->port.supported[cfg_idx]
 493                               & SUPPORTED_2500baseX_Full)) {
 494                                 DP(NETIF_MSG_LINK,
 495                                    "2.5G full not supported\n");
 496                                 return -EINVAL;
 497                         }
 498
 499                         advertising = (ADVERTISED_2500baseX_Full |
 500                                        ADVERTISED_TP);
 501                         break;
 502
 503                 case SPEED_10000:
 504                         if (cmd->duplex != DUPLEX_FULL) {
 505                                 DP(NETIF_MSG_LINK, "10G half not supported\n");
 506                                 return -EINVAL;
 507                         }
 508
 509                         if (!(bp->port.supported[cfg_idx]
 510                               & SUPPORTED_10000baseT_Full)) {
 511                                 DP(NETIF_MSG_LINK, "10G full not supported\n");
 512                                 return -EINVAL;
 513                         }
 514
 515                         advertising = (ADVERTISED_10000baseT_Full |
 516                                        ADVERTISED_FIBRE);
 517                         break;
 518
 519                 default:
 520                         DP(NETIF_MSG_LINK, "Unsupported speed %u\n", speed);
 521                         return -EINVAL;
 522                 }
 523
 524                 bp->link_params.req_line_speed[cfg_idx] = speed;
 525                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 526                 bp->port.advertising[cfg_idx] = advertising;
 527         }
 528
 529         DP(NETIF_MSG_LINK, "req_line_speed %d\n"
 530            "  req_duplex %d  advertising 0x%x\n",
 531            bp->link_params.req_line_speed[cfg_idx],
 532            bp->link_params.req_duplex[cfg_idx],
 533            bp->port.advertising[cfg_idx]);
 534
 535         /* Set new config */
 536         bp->link_params.multi_phy_config = new_multi_phy_config;
 537         if (netif_running(dev)) {
 538                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 539                 bnx2x_link_set(bp);
 540         }
 541
 542         return 0;
 543 }
 544
 545 #define IS_E1_ONLINE(info)      (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
 546 #define IS_E1H_ONLINE(info)     (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
 547 #define IS_E2_ONLINE(info)      (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
 548 #define IS_E3_ONLINE(info)      (((info) & RI_E3_ONLINE) == RI_E3_ONLINE)
 549 #define IS_E3B0_ONLINE(info)    (((info) & RI_E3B0_ONLINE) == RI_E3B0_ONLINE)
 550
 551 static inline bool bnx2x_is_reg_online(struct bnx2x *bp,
 552                                        const struct reg_addr *reg_info)
 553 {
 554         if (CHIP_IS_E1(bp))
 555                 return IS_E1_ONLINE(reg_info->info);
 556         else if (CHIP_IS_E1H(bp))
 557                 return IS_E1H_ONLINE(reg_info->info);
 558         else if (CHIP_IS_E2(bp))
 559                 return IS_E2_ONLINE(reg_info->info);
 560         else if (CHIP_IS_E3A0(bp))
 561                 return IS_E3_ONLINE(reg_info->info);
 562         else if (CHIP_IS_E3B0(bp))
 563                 return IS_E3B0_ONLINE(reg_info->info);
 564         else
 565                 return false;
 566 }
 567
 568 /******* Paged registers info selectors ********/
 569 static inline const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
 570 {
 571         if (CHIP_IS_E2(bp))
 572                 return page_vals_e2;
 573         else if (CHIP_IS_E3(bp))
 574                 return page_vals_e3;
 575         else
 576                 return NULL;
 577 }
 578
 579 static inline u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
 580 {
 581         if (CHIP_IS_E2(bp))
 582                 return PAGE_MODE_VALUES_E2;
 583         else if (CHIP_IS_E3(bp))
 584                 return PAGE_MODE_VALUES_E3;
 585         else
 586                 return 0;
 587 }
 588
 589 static inline const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
 590 {
 591         if (CHIP_IS_E2(bp))
 592                 return page_write_regs_e2;
 593         else if (CHIP_IS_E3(bp))
 594                 return page_write_regs_e3;
 595         else
 596                 return NULL;
 597 }
 598
 599 static inline u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
 600 {
 601         if (CHIP_IS_E2(bp))
 602                 return PAGE_WRITE_REGS_E2;
 603         else if (CHIP_IS_E3(bp))
 604                 return PAGE_WRITE_REGS_E3;
 605         else
 606                 return 0;
 607 }
 608
 609 static inline const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
 610 {
 611         if (CHIP_IS_E2(bp))
 612                 return page_read_regs_e2;
 613         else if (CHIP_IS_E3(bp))
 614                 return page_read_regs_e3;
 615         else
 616                 return NULL;
 617 }
 618
 619 static inline u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
 620 {
 621         if (CHIP_IS_E2(bp))
 622                 return PAGE_READ_REGS_E2;
 623         else if (CHIP_IS_E3(bp))
 624                 return PAGE_READ_REGS_E3;
 625         else
 626                 return 0;
 627 }
 628
 629 static inline int __bnx2x_get_regs_len(struct bnx2x *bp)
 630 {
 631         int num_pages = __bnx2x_get_page_reg_num(bp);
 632         int page_write_num = __bnx2x_get_page_write_num(bp);
 633         const struct reg_addr *page_read_addr = __bnx2x_get_page_read_ar(bp);
 634         int page_read_num = __bnx2x_get_page_read_num(bp);
 635         int regdump_len = 0;
 636         int i, j, k;
 637
 638         for (i = 0; i < REGS_COUNT; i++)
 639                 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
 640                         regdump_len += reg_addrs[i].size;
 641
 642         for (i = 0; i < num_pages; i++)
 643                 for (j = 0; j < page_write_num; j++)
 644                         for (k = 0; k < page_read_num; k++)
 645                                 if (bnx2x_is_reg_online(bp, &page_read_addr[k]))
 646                                         regdump_len += page_read_addr[k].size;
 647
 648         return regdump_len;
 649 }
 650
 651 static int bnx2x_get_regs_len(struct net_device *dev)
 652 {
 653         struct bnx2x *bp = netdev_priv(dev);
 654         int regdump_len = 0;
 655
 656         regdump_len = __bnx2x_get_regs_len(bp);
 657         regdump_len *= 4;
 658         regdump_len += sizeof(struct dump_hdr);
 659
 660         return regdump_len;
 661 }
 662
 663 /**
 664  * bnx2x_read_pages_regs - read "paged" registers
 665  *
 666  * @bp          device handle
 667  * @p           output buffer
 668  *
 669  * Reads "paged" memories: memories that may only be read by first writing to a
 670  * specific address ("write address") and then reading from a specific address
 671  * ("read address"). There may be more than one write address per "page" and
 672  * more than one read address per write address.
 673  */
 674 static inline void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p)
 675 {
 676         u32 i, j, k, n;
 677         /* addresses of the paged registers */
 678         const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
 679         /* number of paged registers */
 680         int num_pages = __bnx2x_get_page_reg_num(bp);
 681         /* write addresses */
 682         const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
 683         /* number of write addresses */
 684         int write_num = __bnx2x_get_page_write_num(bp);
 685         /* read addresses info */
 686         const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
 687         /* number of read addresses */
 688         int read_num = __bnx2x_get_page_read_num(bp);
 689
 690         for (i = 0; i < num_pages; i++) {
 691                 for (j = 0; j < write_num; j++) {
 692                         REG_WR(bp, write_addr[j], page_addr[i]);
 693                         for (k = 0; k < read_num; k++)
 694                                 if (bnx2x_is_reg_online(bp, &read_addr[k]))
 695                                         for (n = 0; n <
 696                                               read_addr[k].size; n++)
 697                                                 *p++ = REG_RD(bp,
 698                                                        read_addr[k].addr + n*4);
 699                 }
 700         }
 701 }
 702
 703 static inline void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
 704 {
 705         u32 i, j;
 706
 707         /* Read the regular registers */
 708         for (i = 0; i < REGS_COUNT; i++)
 709                 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
 710                         for (j = 0; j < reg_addrs[i].size; j++)
 711                                 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
 712
 713         /* Read "paged" registes */
 714         bnx2x_read_pages_regs(bp, p);
 715 }
 716
 717 static void bnx2x_get_regs(struct net_device *dev,
 718                            struct ethtool_regs *regs, void *_p)
 719 {
 720         u32 *p = _p;
 721         struct bnx2x *bp = netdev_priv(dev);
 722         struct dump_hdr dump_hdr = {0};
 723
 724         regs->version = 0;
 725         memset(p, 0, regs->len);
 726
 727         if (!netif_running(bp->dev))
 728                 return;
 729
 730         /* Disable parity attentions as long as following dump may
 731          * cause false alarms by reading never written registers. We
 732          * will re-enable parity attentions right after the dump.
 733          */
 734         bnx2x_disable_blocks_parity(bp);
 735
 736         dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
 737         dump_hdr.dump_sign = dump_sign_all;
 738         dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
 739         dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
 740         dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
 741         dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
 742
 743         if (CHIP_IS_E1(bp))
 744                 dump_hdr.info = RI_E1_ONLINE;
 745         else if (CHIP_IS_E1H(bp))
 746                 dump_hdr.info = RI_E1H_ONLINE;
 747         else if (!CHIP_IS_E1x(bp))
 748                 dump_hdr.info = RI_E2_ONLINE |
 749                 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
 750
 751         memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
 752         p += dump_hdr.hdr_size + 1;
 753
 754         /* Actually read the registers */
 755         __bnx2x_get_regs(bp, p);
 756
 757         /* Re-enable parity attentions */
 758         bnx2x_clear_blocks_parity(bp);
 759         bnx2x_enable_blocks_parity(bp);
 760 }
 761
 762 static void bnx2x_get_drvinfo(struct net_device *dev,
 763                               struct ethtool_drvinfo *info)
 764 {
 765         struct bnx2x *bp = netdev_priv(dev);
 766         u8 phy_fw_ver[PHY_FW_VER_LEN];
 767
 768         strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
 769         strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
 770
 771         phy_fw_ver[0] = '\0';
 772         if (bp->port.pmf) {
 773                 bnx2x_acquire_phy_lock(bp);
 774                 bnx2x_get_ext_phy_fw_version(&bp->link_params,
 775                                              (bp->state != BNX2X_STATE_CLOSED),
 776                                              phy_fw_ver, PHY_FW_VER_LEN);
 777                 bnx2x_release_phy_lock(bp);
 778         }
 779
 780         strlcpy(info->fw_version, bp->fw_ver, sizeof(info->fw_version));
 781         snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
 782                  "bc %d.%d.%d%s%s",
 783                  (bp->common.bc_ver & 0xff0000) >> 16,
 784                  (bp->common.bc_ver & 0xff00) >> 8,
 785                  (bp->common.bc_ver & 0xff),
 786                  ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
 787         strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
 788         info->n_stats = BNX2X_NUM_STATS;
 789         info->testinfo_len = BNX2X_NUM_TESTS;
 790         info->eedump_len = bp->common.flash_size;
 791         info->regdump_len = bnx2x_get_regs_len(dev);
 792 }
 793
 794 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 795 {
 796         struct bnx2x *bp = netdev_priv(dev);
 797
 798         if (bp->flags & NO_WOL_FLAG) {
 799                 wol->supported = 0;
 800                 wol->wolopts = 0;
 801         } else {
 802                 wol->supported = WAKE_MAGIC;
 803                 if (bp->wol)
 804                         wol->wolopts = WAKE_MAGIC;
 805                 else
 806                         wol->wolopts = 0;
 807         }
 808         memset(&wol->sopass, 0, sizeof(wol->sopass));
 809 }
 810
 811 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 812 {
 813         struct bnx2x *bp = netdev_priv(dev);
 814
 815         if (wol->wolopts & ~WAKE_MAGIC)
 816                 return -EINVAL;
 817
 818         if (wol->wolopts & WAKE_MAGIC) {
 819                 if (bp->flags & NO_WOL_FLAG)
 820                         return -EINVAL;
 821
 822                 bp->wol = 1;
 823         } else
 824                 bp->wol = 0;
 825
 826         return 0;
 827 }
 828
 829 static u32 bnx2x_get_msglevel(struct net_device *dev)
 830 {
 831         struct bnx2x *bp = netdev_priv(dev);
 832
 833         return bp->msg_enable;
 834 }
 835
 836 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
 837 {
 838         struct bnx2x *bp = netdev_priv(dev);
 839
 840         if (capable(CAP_NET_ADMIN)) {
 841                 /* dump MCP trace */
 842                 if (level & BNX2X_MSG_MCP)
 843                         bnx2x_fw_dump_lvl(bp, KERN_INFO);
 844                 bp->msg_enable = level;
 845         }
 846 }
 847
 848 static int bnx2x_nway_reset(struct net_device *dev)
 849 {
 850         struct bnx2x *bp = netdev_priv(dev);
 851
 852         if (!bp->port.pmf)
 853                 return 0;
 854
 855         if (netif_running(dev)) {
 856                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 857                 bnx2x_link_set(bp);
 858         }
 859
 860         return 0;
 861 }
 862
 863 static u32 bnx2x_get_link(struct net_device *dev)
 864 {
 865         struct bnx2x *bp = netdev_priv(dev);
 866
 867         if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
 868                 return 0;
 869
 870         return bp->link_vars.link_up;
 871 }
 872
 873 static int bnx2x_get_eeprom_len(struct net_device *dev)
 874 {
 875         struct bnx2x *bp = netdev_priv(dev);
 876
 877         return bp->common.flash_size;
 878 }
 879
 880 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
 881 {
 882         int port = BP_PORT(bp);
 883         int count, i;
 884         u32 val = 0;
 885
 886         /* adjust timeout for emulation/FPGA */
 887         count = BNX2X_NVRAM_TIMEOUT_COUNT;
 888         if (CHIP_REV_IS_SLOW(bp))
 889                 count *= 100;
 890
 891         /* request access to nvram interface */
 892         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
 893                (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
 894
 895         for (i = 0; i < count*10; i++) {
 896                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
 897                 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
 898                         break;
 899
 900                 udelay(5);
 901         }
 902
 903         if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
 904                 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
 905                 return -EBUSY;
 906         }
 907
 908         return 0;
 909 }
 910
 911 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
 912 {
 913         int port = BP_PORT(bp);
 914         int count, i;
 915         u32 val = 0;
 916
 917         /* adjust timeout for emulation/FPGA */
 918         count = BNX2X_NVRAM_TIMEOUT_COUNT;
 919         if (CHIP_REV_IS_SLOW(bp))
 920                 count *= 100;
 921
 922         /* relinquish nvram interface */
 923         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
 924                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
 925
 926         for (i = 0; i < count*10; i++) {
 927                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
 928                 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
 929                         break;
 930
 931                 udelay(5);
 932         }
 933
 934         if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
 935                 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
 936                 return -EBUSY;
 937         }
 938
 939         return 0;
 940 }
 941
 942 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
 943 {
 944         u32 val;
 945
 946         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
 947
 948         /* enable both bits, even on read */
 949         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
 950                (val | MCPR_NVM_ACCESS_ENABLE_EN |
 951                       MCPR_NVM_ACCESS_ENABLE_WR_EN));
 952 }
 953
 954 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
 955 {
 956         u32 val;
 957
 958         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
 959
 960         /* disable both bits, even after read */
 961         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
 962                (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
 963                         MCPR_NVM_ACCESS_ENABLE_WR_EN)));
 964 }
 965
 966 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
 967                                   u32 cmd_flags)
 968 {
 969         int count, i, rc;
 970         u32 val;
 971
 972         /* build the command word */
 973         cmd_flags |= MCPR_NVM_COMMAND_DOIT;
 974
 975         /* need to clear DONE bit separately */
 976         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
 977
 978         /* address of the NVRAM to read from */
 979         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
 980                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
 981
 982         /* issue a read command */
 983         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
 984
 985         /* adjust timeout for emulation/FPGA */
 986         count = BNX2X_NVRAM_TIMEOUT_COUNT;
 987         if (CHIP_REV_IS_SLOW(bp))
 988                 count *= 100;
 989
 990         /* wait for completion */
 991         *ret_val = 0;
 992         rc = -EBUSY;
 993         for (i = 0; i < count; i++) {
 994                 udelay(5);
 995                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
 996
 997                 if (val & MCPR_NVM_COMMAND_DONE) {
 998                         val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
 999                         /* we read nvram data in cpu order
1000                          * but ethtool sees it as an array of bytes
1001                          * converting to big-endian will do the work */
1002                         *ret_val = cpu_to_be32(val);
1003                         rc = 0;
1004                         break;
1005                 }
1006         }
1007
1008         return rc;
1009 }
1010
1011 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1012                             int buf_size)
1013 {
1014         int rc;
1015         u32 cmd_flags;
1016         __be32 val;
1017
1018         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1019                 DP(BNX2X_MSG_NVM,
1020                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1021                    offset, buf_size);
1022                 return -EINVAL;
1023         }
1024
1025         if (offset + buf_size > bp->common.flash_size) {
1026                 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1027                                   " buf_size (0x%x) > flash_size (0x%x)\n",
1028                    offset, buf_size, bp->common.flash_size);
1029                 return -EINVAL;
1030         }
1031
1032         /* request access to nvram interface */
1033         rc = bnx2x_acquire_nvram_lock(bp);
1034         if (rc)
1035                 return rc;
1036
1037         /* enable access to nvram interface */
1038         bnx2x_enable_nvram_access(bp);
1039
1040         /* read the first word(s) */
1041         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1042         while ((buf_size > sizeof(u32)) && (rc == 0)) {
1043                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1044                 memcpy(ret_buf, &val, 4);
1045
1046                 /* advance to the next dword */
1047                 offset += sizeof(u32);
1048                 ret_buf += sizeof(u32);
1049                 buf_size -= sizeof(u32);
1050                 cmd_flags = 0;
1051         }
1052
1053         if (rc == 0) {
1054                 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1055                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1056                 memcpy(ret_buf, &val, 4);
1057         }
1058
1059         /* disable access to nvram interface */
1060         bnx2x_disable_nvram_access(bp);
1061         bnx2x_release_nvram_lock(bp);
1062
1063         return rc;
1064 }
1065
1066 static int bnx2x_get_eeprom(struct net_device *dev,
1067                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1068 {
1069         struct bnx2x *bp = netdev_priv(dev);
1070         int rc;
1071
1072         if (!netif_running(dev))
1073                 return -EAGAIN;
1074
1075         DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1076            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1077            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1078            eeprom->len, eeprom->len);
1079
1080         /* parameters already validated in ethtool_get_eeprom */
1081
1082         rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1083
1084         return rc;
1085 }
1086
1087 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1088                                    u32 cmd_flags)
1089 {
1090         int count, i, rc;
1091
1092         /* build the command word */
1093         cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1094
1095         /* need to clear DONE bit separately */
1096         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1097
1098         /* write the data */
1099         REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1100
1101         /* address of the NVRAM to write to */
1102         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1103                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1104
1105         /* issue the write command */
1106         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1107
1108         /* adjust timeout for emulation/FPGA */
1109         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1110         if (CHIP_REV_IS_SLOW(bp))
1111                 count *= 100;
1112
1113         /* wait for completion */
1114         rc = -EBUSY;
1115         for (i = 0; i < count; i++) {
1116                 udelay(5);
1117                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1118                 if (val & MCPR_NVM_COMMAND_DONE) {
1119                         rc = 0;
1120                         break;
1121                 }
1122         }
1123
1124         return rc;
1125 }
1126
1127 #define BYTE_OFFSET(offset)             (8 * (offset & 0x03))
1128
1129 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1130                               int buf_size)
1131 {
1132         int rc;
1133         u32 cmd_flags;
1134         u32 align_offset;
1135         __be32 val;
1136
1137         if (offset + buf_size > bp->common.flash_size) {
1138                 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1139                                   " buf_size (0x%x) > flash_size (0x%x)\n",
1140                    offset, buf_size, bp->common.flash_size);
1141                 return -EINVAL;
1142         }
1143
1144         /* request access to nvram interface */
1145         rc = bnx2x_acquire_nvram_lock(bp);
1146         if (rc)
1147                 return rc;
1148
1149         /* enable access to nvram interface */
1150         bnx2x_enable_nvram_access(bp);
1151
1152         cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1153         align_offset = (offset & ~0x03);
1154         rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
1155
1156         if (rc == 0) {
1157                 val &= ~(0xff << BYTE_OFFSET(offset));
1158                 val |= (*data_buf << BYTE_OFFSET(offset));
1159
1160                 /* nvram data is returned as an array of bytes
1161                  * convert it back to cpu order */
1162                 val = be32_to_cpu(val);
1163
1164                 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1165                                              cmd_flags);
1166         }
1167
1168         /* disable access to nvram interface */
1169         bnx2x_disable_nvram_access(bp);
1170         bnx2x_release_nvram_lock(bp);
1171
1172         return rc;
1173 }
1174
1175 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1176                              int buf_size)
1177 {
1178         int rc;
1179         u32 cmd_flags;
1180         u32 val;
1181         u32 written_so_far;
1182
1183         if (buf_size == 1)      /* ethtool */
1184                 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1185
1186         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1187                 DP(BNX2X_MSG_NVM,
1188                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1189                    offset, buf_size);
1190                 return -EINVAL;
1191         }
1192
1193         if (offset + buf_size > bp->common.flash_size) {
1194                 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1195                                   " buf_size (0x%x) > flash_size (0x%x)\n",
1196                    offset, buf_size, bp->common.flash_size);
1197                 return -EINVAL;
1198         }
1199
1200         /* request access to nvram interface */
1201         rc = bnx2x_acquire_nvram_lock(bp);
1202         if (rc)
1203                 return rc;
1204
1205         /* enable access to nvram interface */
1206         bnx2x_enable_nvram_access(bp);
1207
1208         written_so_far = 0;
1209         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1210         while ((written_so_far < buf_size) && (rc == 0)) {
1211                 if (written_so_far == (buf_size - sizeof(u32)))
1212                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1213                 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
1214                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1215                 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
1216                         cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1217
1218                 memcpy(&val, data_buf, 4);
1219
1220                 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1221
1222                 /* advance to the next dword */
1223                 offset += sizeof(u32);
1224                 data_buf += sizeof(u32);
1225                 written_so_far += sizeof(u32);
1226                 cmd_flags = 0;
1227         }
1228
1229         /* disable access to nvram interface */
1230         bnx2x_disable_nvram_access(bp);
1231         bnx2x_release_nvram_lock(bp);
1232
1233         return rc;
1234 }
1235
1236 static int bnx2x_set_eeprom(struct net_device *dev,
1237                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1238 {
1239         struct bnx2x *bp = netdev_priv(dev);
1240         int port = BP_PORT(bp);
1241         int rc = 0;
1242         u32 ext_phy_config;
1243         if (!netif_running(dev))
1244                 return -EAGAIN;
1245
1246         DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1247            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1248            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1249            eeprom->len, eeprom->len);
1250
1251         /* parameters already validated in ethtool_set_eeprom */
1252
1253         /* PHY eeprom can be accessed only by the PMF */
1254         if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1255             !bp->port.pmf)
1256                 return -EINVAL;
1257
1258         ext_phy_config =
1259                 SHMEM_RD(bp,
1260                          dev_info.port_hw_config[port].external_phy_config);
1261
1262         if (eeprom->magic == 0x50485950) {
1263                 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1264                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1265
1266                 bnx2x_acquire_phy_lock(bp);
1267                 rc |= bnx2x_link_reset(&bp->link_params,
1268                                        &bp->link_vars, 0);
1269                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1270                                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1271                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1272                                        MISC_REGISTERS_GPIO_HIGH, port);
1273                 bnx2x_release_phy_lock(bp);
1274                 bnx2x_link_report(bp);
1275
1276         } else if (eeprom->magic == 0x50485952) {
1277                 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1278                 if (bp->state == BNX2X_STATE_OPEN) {
1279                         bnx2x_acquire_phy_lock(bp);
1280                         rc |= bnx2x_link_reset(&bp->link_params,
1281                                                &bp->link_vars, 1);
1282
1283                         rc |= bnx2x_phy_init(&bp->link_params,
1284                                              &bp->link_vars);
1285                         bnx2x_release_phy_lock(bp);
1286                         bnx2x_calc_fc_adv(bp);
1287                 }
1288         } else if (eeprom->magic == 0x53985943) {
1289                 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1290                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1291                                        PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1292
1293                         /* DSP Remove Download Mode */
1294                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1295                                        MISC_REGISTERS_GPIO_LOW, port);
1296
1297                         bnx2x_acquire_phy_lock(bp);
1298
1299                         bnx2x_sfx7101_sp_sw_reset(bp,
1300                                                 &bp->link_params.phy[EXT_PHY1]);
1301
1302                         /* wait 0.5 sec to allow it to run */
1303                         msleep(500);
1304                         bnx2x_ext_phy_hw_reset(bp, port);
1305                         msleep(500);
1306                         bnx2x_release_phy_lock(bp);
1307                 }
1308         } else
1309                 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1310
1311         return rc;
1312 }
1313
1314 static int bnx2x_get_coalesce(struct net_device *dev,
1315                               struct ethtool_coalesce *coal)
1316 {
1317         struct bnx2x *bp = netdev_priv(dev);
1318
1319         memset(coal, 0, sizeof(struct ethtool_coalesce));
1320
1321         coal->rx_coalesce_usecs = bp->rx_ticks;
1322         coal->tx_coalesce_usecs = bp->tx_ticks;
1323
1324         return 0;
1325 }
1326
1327 static int bnx2x_set_coalesce(struct net_device *dev,
1328                               struct ethtool_coalesce *coal)
1329 {
1330         struct bnx2x *bp = netdev_priv(dev);
1331
1332         bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1333         if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1334                 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1335
1336         bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1337         if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1338                 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1339
1340         if (netif_running(dev))
1341                 bnx2x_update_coalesce(bp);
1342
1343         return 0;
1344 }
1345
1346 static void bnx2x_get_ringparam(struct net_device *dev,
1347                                 struct ethtool_ringparam *ering)
1348 {
1349         struct bnx2x *bp = netdev_priv(dev);
1350
1351         ering->rx_max_pending = MAX_RX_AVAIL;
1352
1353         if (bp->rx_ring_size)
1354                 ering->rx_pending = bp->rx_ring_size;
1355         else
1356                 ering->rx_pending = MAX_RX_AVAIL;
1357
1358         ering->tx_max_pending = MAX_TX_AVAIL;
1359         ering->tx_pending = bp->tx_ring_size;
1360 }
1361
1362 static int bnx2x_set_ringparam(struct net_device *dev,
1363                                struct ethtool_ringparam *ering)
1364 {
1365         struct bnx2x *bp = netdev_priv(dev);
1366
1367         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1368                 pr_err("Handling parity error recovery. Try again later\n");
1369                 return -EAGAIN;
1370         }
1371
1372         if ((ering->rx_pending > MAX_RX_AVAIL) ||
1373             (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1374                                                     MIN_RX_SIZE_TPA)) ||
1375             (ering->tx_pending > MAX_TX_AVAIL) ||
1376             (ering->tx_pending <= MAX_SKB_FRAGS + 4))
1377                 return -EINVAL;
1378
1379         bp->rx_ring_size = ering->rx_pending;
1380         bp->tx_ring_size = ering->tx_pending;
1381
1382         return bnx2x_reload_if_running(dev);
1383 }
1384
1385 static void bnx2x_get_pauseparam(struct net_device *dev,
1386                                  struct ethtool_pauseparam *epause)
1387 {
1388         struct bnx2x *bp = netdev_priv(dev);
1389         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1390         epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1391                            BNX2X_FLOW_CTRL_AUTO);
1392
1393         epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) ==
1394                             BNX2X_FLOW_CTRL_RX);
1395         epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) ==
1396                             BNX2X_FLOW_CTRL_TX);
1397
1398         DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1399            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1400            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1401 }
1402
1403 static int bnx2x_set_pauseparam(struct net_device *dev,
1404                                 struct ethtool_pauseparam *epause)
1405 {
1406         struct bnx2x *bp = netdev_priv(dev);
1407         u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1408         if (IS_MF(bp))
1409                 return 0;
1410
1411         DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1412            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1413            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1414
1415         bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1416
1417         if (epause->rx_pause)
1418                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1419
1420         if (epause->tx_pause)
1421                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1422
1423         if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1424                 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1425
1426         if (epause->autoneg) {
1427                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1428                         DP(NETIF_MSG_LINK, "autoneg not supported\n");
1429                         return -EINVAL;
1430                 }
1431
1432                 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1433                         bp->link_params.req_flow_ctrl[cfg_idx] =
1434                                 BNX2X_FLOW_CTRL_AUTO;
1435                 }
1436         }
1437
1438         DP(NETIF_MSG_LINK,
1439            "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1440
1441         if (netif_running(dev)) {
1442                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1443                 bnx2x_link_set(bp);
1444         }
1445
1446         return 0;
1447 }
1448
1449 static const struct {
1450         char string[ETH_GSTRING_LEN];
1451 } bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
1452         { "register_test (offline)" },
1453         { "memory_test (offline)" },
1454         { "loopback_test (offline)" },
1455         { "nvram_test (online)" },
1456         { "interrupt_test (online)" },
1457         { "link_test (online)" },
1458         { "idle check (online)" }
1459 };
1460
1461 enum {
1462         BNX2X_CHIP_E1_OFST = 0,
1463         BNX2X_CHIP_E1H_OFST,
1464         BNX2X_CHIP_E2_OFST,
1465         BNX2X_CHIP_E3_OFST,
1466         BNX2X_CHIP_E3B0_OFST,
1467         BNX2X_CHIP_MAX_OFST
1468 };
1469
1470 #define BNX2X_CHIP_MASK_E1      (1 << BNX2X_CHIP_E1_OFST)
1471 #define BNX2X_CHIP_MASK_E1H     (1 << BNX2X_CHIP_E1H_OFST)
1472 #define BNX2X_CHIP_MASK_E2      (1 << BNX2X_CHIP_E2_OFST)
1473 #define BNX2X_CHIP_MASK_E3      (1 << BNX2X_CHIP_E3_OFST)
1474 #define BNX2X_CHIP_MASK_E3B0    (1 << BNX2X_CHIP_E3B0_OFST)
1475
1476 #define BNX2X_CHIP_MASK_ALL     ((1 << BNX2X_CHIP_MAX_OFST) - 1)
1477 #define BNX2X_CHIP_MASK_E1X     (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
1478
1479 static int bnx2x_test_registers(struct bnx2x *bp)
1480 {
1481         int idx, i, rc = -ENODEV;
1482         u32 wr_val = 0, hw;
1483         int port = BP_PORT(bp);
1484         static const struct {
1485                 u32 hw;
1486                 u32 offset0;
1487                 u32 offset1;
1488                 u32 mask;
1489         } reg_tbl[] = {
1490 /* 0 */         { BNX2X_CHIP_MASK_ALL,
1491                         BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
1492                 { BNX2X_CHIP_MASK_ALL,
1493                         DORQ_REG_DB_ADDR0,              4, 0xffffffff },
1494                 { BNX2X_CHIP_MASK_E1X,
1495                         HC_REG_AGG_INT_0,               4, 0x000003ff },
1496                 { BNX2X_CHIP_MASK_ALL,
1497                         PBF_REG_MAC_IF0_ENABLE,         4, 0x00000001 },
1498                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
1499                         PBF_REG_P0_INIT_CRD,            4, 0x000007ff },
1500                 { BNX2X_CHIP_MASK_E3B0,
1501                         PBF_REG_INIT_CRD_Q0,            4, 0x000007ff },
1502                 { BNX2X_CHIP_MASK_ALL,
1503                         PRS_REG_CID_PORT_0,             4, 0x00ffffff },
1504                 { BNX2X_CHIP_MASK_ALL,
1505                         PXP2_REG_PSWRQ_CDU0_L2P,        4, 0x000fffff },
1506                 { BNX2X_CHIP_MASK_ALL,
1507                         PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1508                 { BNX2X_CHIP_MASK_ALL,
1509                         PXP2_REG_PSWRQ_TM0_L2P,         4, 0x000fffff },
1510 /* 10 */        { BNX2X_CHIP_MASK_ALL,
1511                         PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1512                 { BNX2X_CHIP_MASK_ALL,
1513                         PXP2_REG_PSWRQ_TSDM0_L2P,       4, 0x000fffff },
1514                 { BNX2X_CHIP_MASK_ALL,
1515                         QM_REG_CONNNUM_0,               4, 0x000fffff },
1516                 { BNX2X_CHIP_MASK_ALL,
1517                         TM_REG_LIN0_MAX_ACTIVE_CID,     4, 0x0003ffff },
1518                 { BNX2X_CHIP_MASK_ALL,
1519                         SRC_REG_KEYRSS0_0,              40, 0xffffffff },
1520                 { BNX2X_CHIP_MASK_ALL,
1521                         SRC_REG_KEYRSS0_7,              40, 0xffffffff },
1522                 { BNX2X_CHIP_MASK_ALL,
1523                         XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1524                 { BNX2X_CHIP_MASK_ALL,
1525                         XCM_REG_WU_DA_CNT_CMD00,        4, 0x00000003 },
1526                 { BNX2X_CHIP_MASK_ALL,
1527                         XCM_REG_GLB_DEL_ACK_MAX_CNT_0,  4, 0x000000ff },
1528                 { BNX2X_CHIP_MASK_ALL,
1529                         NIG_REG_LLH0_T_BIT,             4, 0x00000001 },
1530 /* 20 */        { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1531                         NIG_REG_EMAC0_IN_EN,            4, 0x00000001 },
1532                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1533                         NIG_REG_BMAC0_IN_EN,            4, 0x00000001 },
1534                 { BNX2X_CHIP_MASK_ALL,
1535                         NIG_REG_XCM0_OUT_EN,            4, 0x00000001 },
1536                 { BNX2X_CHIP_MASK_ALL,
1537                         NIG_REG_BRB0_OUT_EN,            4, 0x00000001 },
1538                 { BNX2X_CHIP_MASK_ALL,
1539                         NIG_REG_LLH0_XCM_MASK,          4, 0x00000007 },
1540                 { BNX2X_CHIP_MASK_ALL,
1541                         NIG_REG_LLH0_ACPI_PAT_6_LEN,    68, 0x000000ff },
1542                 { BNX2X_CHIP_MASK_ALL,
1543                         NIG_REG_LLH0_ACPI_PAT_0_CRC,    68, 0xffffffff },
1544                 { BNX2X_CHIP_MASK_ALL,
1545                         NIG_REG_LLH0_DEST_MAC_0_0,      160, 0xffffffff },
1546                 { BNX2X_CHIP_MASK_ALL,
1547                         NIG_REG_LLH0_DEST_IP_0_1,       160, 0xffffffff },
1548                 { BNX2X_CHIP_MASK_ALL,
1549                         NIG_REG_LLH0_IPV4_IPV6_0,       160, 0x00000001 },
1550 /* 30 */        { BNX2X_CHIP_MASK_ALL,
1551                         NIG_REG_LLH0_DEST_UDP_0,        160, 0x0000ffff },
1552                 { BNX2X_CHIP_MASK_ALL,
1553                         NIG_REG_LLH0_DEST_TCP_0,        160, 0x0000ffff },
1554                 { BNX2X_CHIP_MASK_ALL,
1555                         NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
1556                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1557                         NIG_REG_XGXS_SERDES0_MODE_SEL,  4, 0x00000001 },
1558                 { BNX2X_CHIP_MASK_ALL,
1559                         NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
1560                 { BNX2X_CHIP_MASK_ALL,
1561                         NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
1562                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1563                         NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1564                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1565                         NIG_REG_SERDES0_CTRL_PHY_ADDR,  16, 0x0000001f },
1566
1567                 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
1568         };
1569
1570         if (!netif_running(bp->dev))
1571                 return rc;
1572
1573         if (CHIP_IS_E1(bp))
1574                 hw = BNX2X_CHIP_MASK_E1;
1575         else if (CHIP_IS_E1H(bp))
1576                 hw = BNX2X_CHIP_MASK_E1H;
1577         else if (CHIP_IS_E2(bp))
1578                 hw = BNX2X_CHIP_MASK_E2;
1579         else if (CHIP_IS_E3B0(bp))
1580                 hw = BNX2X_CHIP_MASK_E3B0;
1581         else /* e3 A0 */
1582                 hw = BNX2X_CHIP_MASK_E3;
1583
1584         /* Repeat the test twice:
1585            First by writing 0x00000000, second by writing 0xffffffff */
1586         for (idx = 0; idx < 2; idx++) {
1587
1588                 switch (idx) {
1589                 case 0:
1590                         wr_val = 0;
1591                         break;
1592                 case 1:
1593                         wr_val = 0xffffffff;
1594                         break;
1595                 }
1596
1597                 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1598                         u32 offset, mask, save_val, val;
1599                         if (!(hw & reg_tbl[i].hw))
1600                                 continue;
1601
1602                         offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1603                         mask = reg_tbl[i].mask;
1604
1605                         save_val = REG_RD(bp, offset);
1606
1607                         REG_WR(bp, offset, wr_val & mask);
1608
1609                         val = REG_RD(bp, offset);
1610
1611                         /* Restore the original register's value */
1612                         REG_WR(bp, offset, save_val);
1613
1614                         /* verify value is as expected */
1615                         if ((val & mask) != (wr_val & mask)) {
1616                                 DP(NETIF_MSG_HW,
1617                                    "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1618                                    offset, val, wr_val, mask);
1619                                 goto test_reg_exit;
1620                         }
1621                 }
1622         }
1623
1624         rc = 0;
1625
1626 test_reg_exit:
1627         return rc;
1628 }
1629
1630 static int bnx2x_test_memory(struct bnx2x *bp)
1631 {
1632         int i, j, rc = -ENODEV;
1633         u32 val, index;
1634         static const struct {
1635                 u32 offset;
1636                 int size;
1637         } mem_tbl[] = {
1638                 { CCM_REG_XX_DESCR_TABLE,   CCM_REG_XX_DESCR_TABLE_SIZE },
1639                 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1640                 { CFC_REG_LINK_LIST,        CFC_REG_LINK_LIST_SIZE },
1641                 { DMAE_REG_CMD_MEM,         DMAE_REG_CMD_MEM_SIZE },
1642                 { TCM_REG_XX_DESCR_TABLE,   TCM_REG_XX_DESCR_TABLE_SIZE },
1643                 { UCM_REG_XX_DESCR_TABLE,   UCM_REG_XX_DESCR_TABLE_SIZE },
1644                 { XCM_REG_XX_DESCR_TABLE,   XCM_REG_XX_DESCR_TABLE_SIZE },
1645
1646                 { 0xffffffff, 0 }
1647         };
1648
1649         static const struct {
1650                 char *name;
1651                 u32 offset;
1652                 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
1653         } prty_tbl[] = {
1654                 { "CCM_PRTY_STS",  CCM_REG_CCM_PRTY_STS,
1655                         {0x3ffc0, 0,   0, 0} },
1656                 { "CFC_PRTY_STS",  CFC_REG_CFC_PRTY_STS,
1657                         {0x2,     0x2, 0, 0} },
1658                 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
1659                         {0,       0,   0, 0} },
1660                 { "TCM_PRTY_STS",  TCM_REG_TCM_PRTY_STS,
1661                         {0x3ffc0, 0,   0, 0} },
1662                 { "UCM_PRTY_STS",  UCM_REG_UCM_PRTY_STS,
1663                         {0x3ffc0, 0,   0, 0} },
1664                 { "XCM_PRTY_STS",  XCM_REG_XCM_PRTY_STS,
1665                         {0x3ffc1, 0,   0, 0} },
1666
1667                 { NULL, 0xffffffff, {0, 0, 0, 0} }
1668         };
1669
1670         if (!netif_running(bp->dev))
1671                 return rc;
1672
1673         if (CHIP_IS_E1(bp))
1674                 index = BNX2X_CHIP_E1_OFST;
1675         else if (CHIP_IS_E1H(bp))
1676                 index = BNX2X_CHIP_E1H_OFST;
1677         else if (CHIP_IS_E2(bp))
1678                 index = BNX2X_CHIP_E2_OFST;
1679         else /* e3 */
1680                 index = BNX2X_CHIP_E3_OFST;
1681
1682         /* pre-Check the parity status */
1683         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1684                 val = REG_RD(bp, prty_tbl[i].offset);
1685                 if (val & ~(prty_tbl[i].hw_mask[index])) {
1686                         DP(NETIF_MSG_HW,
1687                            "%s is 0x%x\n", prty_tbl[i].name, val);
1688                         goto test_mem_exit;
1689                 }
1690         }
1691
1692         /* Go through all the memories */
1693         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1694                 for (j = 0; j < mem_tbl[i].size; j++)
1695                         REG_RD(bp, mem_tbl[i].offset + j*4);
1696
1697         /* Check the parity status */
1698         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1699                 val = REG_RD(bp, prty_tbl[i].offset);
1700                 if (val & ~(prty_tbl[i].hw_mask[index])) {
1701                         DP(NETIF_MSG_HW,
1702                            "%s is 0x%x\n", prty_tbl[i].name, val);
1703                         goto test_mem_exit;
1704                 }
1705         }
1706
1707         rc = 0;
1708
1709 test_mem_exit:
1710         return rc;
1711 }
1712
1713 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
1714 {
1715         int cnt = 1400;
1716
1717         if (link_up) {
1718                 while (bnx2x_link_test(bp, is_serdes) && cnt--)
1719                         msleep(20);
1720
1721                 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
1722                         DP(NETIF_MSG_LINK, "Timeout waiting for link up\n");
1723         }
1724 }
1725
1726 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
1727 {
1728         unsigned int pkt_size, num_pkts, i;
1729         struct sk_buff *skb;
1730         unsigned char *packet;
1731         struct bnx2x_fastpath *fp_rx = &bp->fp[0];
1732         struct bnx2x_fastpath *fp_tx = &bp->fp[0];
1733         struct bnx2x_fp_txdata *txdata = &fp_tx->txdata[0];
1734         u16 tx_start_idx, tx_idx;
1735         u16 rx_start_idx, rx_idx;
1736         u16 pkt_prod, bd_prod, rx_comp_cons;
1737         struct sw_tx_bd *tx_buf;
1738         struct eth_tx_start_bd *tx_start_bd;
1739         struct eth_tx_parse_bd_e1x  *pbd_e1x = NULL;
1740         struct eth_tx_parse_bd_e2  *pbd_e2 = NULL;
1741         dma_addr_t mapping;
1742         union eth_rx_cqe *cqe;
1743         u8 cqe_fp_flags, cqe_fp_type;
1744         struct sw_rx_bd *rx_buf;
1745         u16 len;
1746         int rc = -ENODEV;
1747         u8 *data;
1748         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txdata->txq_index);
1749
1750         /* check the loopback mode */
1751         switch (loopback_mode) {
1752         case BNX2X_PHY_LOOPBACK:
1753                 if (bp->link_params.loopback_mode != LOOPBACK_XGXS)
1754                         return -EINVAL;
1755                 break;
1756         case BNX2X_MAC_LOOPBACK:
1757                 if (CHIP_IS_E3(bp)) {
1758                         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1759                         if (bp->port.supported[cfg_idx] &
1760                             (SUPPORTED_10000baseT_Full |
1761                              SUPPORTED_20000baseMLD2_Full |
1762                              SUPPORTED_20000baseKR2_Full))
1763                                 bp->link_params.loopback_mode = LOOPBACK_XMAC;
1764                         else
1765                                 bp->link_params.loopback_mode = LOOPBACK_UMAC;
1766                 } else
1767                         bp->link_params.loopback_mode = LOOPBACK_BMAC;
1768
1769                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1770                 break;
1771         default:
1772                 return -EINVAL;
1773         }
1774
1775         /* prepare the loopback packet */
1776         pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
1777                      bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
1778         skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
1779         if (!skb) {
1780                 rc = -ENOMEM;
1781                 goto test_loopback_exit;
1782         }
1783         packet = skb_put(skb, pkt_size);
1784         memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
1785         memset(packet + ETH_ALEN, 0, ETH_ALEN);
1786         memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
1787         for (i = ETH_HLEN; i < pkt_size; i++)
1788                 packet[i] = (unsigned char) (i & 0xff);
1789         mapping = dma_map_single(&bp->pdev->dev, skb->data,
1790                                  skb_headlen(skb), DMA_TO_DEVICE);
1791         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
1792                 rc = -ENOMEM;
1793                 dev_kfree_skb(skb);
1794                 BNX2X_ERR("Unable to map SKB\n");
1795                 goto test_loopback_exit;
1796         }
1797
1798         /* send the loopback packet */
1799         num_pkts = 0;
1800         tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
1801         rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1802
1803         netdev_tx_sent_queue(txq, skb->len);
1804
1805         pkt_prod = txdata->tx_pkt_prod++;
1806         tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
1807         tx_buf->first_bd = txdata->tx_bd_prod;
1808         tx_buf->skb = skb;
1809         tx_buf->flags = 0;
1810
1811         bd_prod = TX_BD(txdata->tx_bd_prod);
1812         tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
1813         tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1814         tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1815         tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
1816         tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
1817         tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
1818         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
1819         SET_FLAG(tx_start_bd->general_data,
1820                  ETH_TX_START_BD_ETH_ADDR_TYPE,
1821                  UNICAST_ADDRESS);
1822         SET_FLAG(tx_start_bd->general_data,
1823                  ETH_TX_START_BD_HDR_NBDS,
1824                  1);
1825
1826         /* turn on parsing and get a BD */
1827         bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
1828
1829         pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
1830         pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
1831
1832         memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
1833         memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
1834
1835         wmb();
1836
1837         txdata->tx_db.data.prod += 2;
1838         barrier();
1839         DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
1840
1841         mmiowb();
1842         barrier();
1843
1844         num_pkts++;
1845         txdata->tx_bd_prod += 2; /* start + pbd */
1846
1847         udelay(100);
1848
1849         tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
1850         if (tx_idx != tx_start_idx + num_pkts)
1851                 goto test_loopback_exit;
1852
1853         /* Unlike HC IGU won't generate an interrupt for status block
1854          * updates that have been performed while interrupts were
1855          * disabled.
1856          */
1857         if (bp->common.int_block == INT_BLOCK_IGU) {
1858                 /* Disable local BHes to prevent a dead-lock situation between
1859                  * sch_direct_xmit() and bnx2x_run_loopback() (calling
1860                  * bnx2x_tx_int()), as both are taking netif_tx_lock().
1861                  */
1862                 local_bh_disable();
1863                 bnx2x_tx_int(bp, txdata);
1864                 local_bh_enable();
1865         }
1866
1867         rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1868         if (rx_idx != rx_start_idx + num_pkts)
1869                 goto test_loopback_exit;
1870
1871         rx_comp_cons = le16_to_cpu(fp_rx->rx_comp_cons);
1872         cqe = &fp_rx->rx_comp_ring[RCQ_BD(rx_comp_cons)];
1873         cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
1874         cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1875         if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
1876                 goto test_loopback_rx_exit;
1877
1878         len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1879         if (len != pkt_size)
1880                 goto test_loopback_rx_exit;
1881
1882         rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
1883         dma_sync_single_for_cpu(&bp->pdev->dev,
1884                                    dma_unmap_addr(rx_buf, mapping),
1885                                    fp_rx->rx_buf_size, DMA_FROM_DEVICE);
1886         data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
1887         for (i = ETH_HLEN; i < pkt_size; i++)
1888                 if (*(data + i) != (unsigned char) (i & 0xff))
1889                         goto test_loopback_rx_exit;
1890
1891         rc = 0;
1892
1893 test_loopback_rx_exit:
1894
1895         fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
1896         fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
1897         fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
1898         fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
1899
1900         /* Update producers */
1901         bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
1902                              fp_rx->rx_sge_prod);
1903
1904 test_loopback_exit:
1905         bp->link_params.loopback_mode = LOOPBACK_NONE;
1906
1907         return rc;
1908 }
1909
1910 static int bnx2x_test_loopback(struct bnx2x *bp)
1911 {
1912         int rc = 0, res;
1913
1914         if (BP_NOMCP(bp))
1915                 return rc;
1916
1917         if (!netif_running(bp->dev))
1918                 return BNX2X_LOOPBACK_FAILED;
1919
1920         bnx2x_netif_stop(bp, 1);
1921         bnx2x_acquire_phy_lock(bp);
1922
1923         res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
1924         if (res) {
1925                 DP(NETIF_MSG_PROBE, "  PHY loopback failed  (res %d)\n", res);
1926                 rc |= BNX2X_PHY_LOOPBACK_FAILED;
1927         }
1928
1929         res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
1930         if (res) {
1931                 DP(NETIF_MSG_PROBE, "  MAC loopback failed  (res %d)\n", res);
1932                 rc |= BNX2X_MAC_LOOPBACK_FAILED;
1933         }
1934
1935         bnx2x_release_phy_lock(bp);
1936         bnx2x_netif_start(bp);
1937
1938         return rc;
1939 }
1940
1941 #define CRC32_RESIDUAL                  0xdebb20e3
1942
1943 static int bnx2x_test_nvram(struct bnx2x *bp)
1944 {
1945         static const struct {
1946                 int offset;
1947                 int size;
1948         } nvram_tbl[] = {
1949                 {     0,  0x14 }, /* bootstrap */
1950                 {  0x14,  0xec }, /* dir */
1951                 { 0x100, 0x350 }, /* manuf_info */
1952                 { 0x450,  0xf0 }, /* feature_info */
1953                 { 0x640,  0x64 }, /* upgrade_key_info */
1954                 { 0x708,  0x70 }, /* manuf_key_info */
1955                 {     0,     0 }
1956         };
1957         __be32 buf[0x350 / 4];
1958         u8 *data = (u8 *)buf;
1959         int i, rc;
1960         u32 magic, crc;
1961
1962         if (BP_NOMCP(bp))
1963                 return 0;
1964
1965         rc = bnx2x_nvram_read(bp, 0, data, 4);
1966         if (rc) {
1967                 DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc);
1968                 goto test_nvram_exit;
1969         }
1970
1971         magic = be32_to_cpu(buf[0]);
1972         if (magic != 0x669955aa) {
1973                 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
1974                 rc = -ENODEV;
1975                 goto test_nvram_exit;
1976         }
1977
1978         for (i = 0; nvram_tbl[i].size; i++) {
1979
1980                 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
1981                                       nvram_tbl[i].size);
1982                 if (rc) {
1983                         DP(NETIF_MSG_PROBE,
1984                            "nvram_tbl[%d] read data (rc %d)\n", i, rc);
1985                         goto test_nvram_exit;
1986                 }
1987
1988                 crc = ether_crc_le(nvram_tbl[i].size, data);
1989                 if (crc != CRC32_RESIDUAL) {
1990                         DP(NETIF_MSG_PROBE,
1991                            "nvram_tbl[%d] crc value (0x%08x)\n", i, crc);
1992                         rc = -ENODEV;
1993                         goto test_nvram_exit;
1994                 }
1995         }
1996
1997 test_nvram_exit:
1998         return rc;
1999 }
2000
2001 /* Send an EMPTY ramrod on the first queue */
2002 static int bnx2x_test_intr(struct bnx2x *bp)
2003 {
2004         struct bnx2x_queue_state_params params = {0};
2005
2006         if (!netif_running(bp->dev))
2007                 return -ENODEV;
2008
2009         params.q_obj = &bp->fp->q_obj;
2010         params.cmd = BNX2X_Q_CMD_EMPTY;
2011
2012         __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2013
2014         return bnx2x_queue_state_change(bp, &params);
2015 }
2016
2017 static void bnx2x_self_test(struct net_device *dev,
2018                             struct ethtool_test *etest, u64 *buf)
2019 {
2020         struct bnx2x *bp = netdev_priv(dev);
2021         u8 is_serdes;
2022         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
2023                 pr_err("Handling parity error recovery. Try again later\n");
2024                 etest->flags |= ETH_TEST_FL_FAILED;
2025                 return;
2026         }
2027
2028         memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
2029
2030         if (!netif_running(dev))
2031                 return;
2032
2033         /* offline tests are not supported in MF mode */
2034         if (IS_MF(bp))
2035                 etest->flags &= ~ETH_TEST_FL_OFFLINE;
2036         is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2037
2038         if (etest->flags & ETH_TEST_FL_OFFLINE) {
2039                 int port = BP_PORT(bp);
2040                 u32 val;
2041                 u8 link_up;
2042
2043                 /* save current value of input enable for TX port IF */
2044                 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2045                 /* disable input for TX port IF */
2046                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2047
2048                 link_up = bp->link_vars.link_up;
2049
2050                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2051                 bnx2x_nic_load(bp, LOAD_DIAG);
2052                 /* wait until link state is restored */
2053                 bnx2x_wait_for_link(bp, 1, is_serdes);
2054
2055                 if (bnx2x_test_registers(bp) != 0) {
2056                         buf[0] = 1;
2057                         etest->flags |= ETH_TEST_FL_FAILED;
2058                 }
2059                 if (bnx2x_test_memory(bp) != 0) {
2060                         buf[1] = 1;
2061                         etest->flags |= ETH_TEST_FL_FAILED;
2062                 }
2063
2064                 buf[2] = bnx2x_test_loopback(bp);
2065                 if (buf[2] != 0)
2066                         etest->flags |= ETH_TEST_FL_FAILED;
2067
2068                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2069
2070                 /* restore input for TX port IF */
2071                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
2072
2073                 bnx2x_nic_load(bp, LOAD_NORMAL);
2074                 /* wait until link state is restored */
2075                 bnx2x_wait_for_link(bp, link_up, is_serdes);
2076         }
2077         if (bnx2x_test_nvram(bp) != 0) {
2078                 buf[3] = 1;
2079                 etest->flags |= ETH_TEST_FL_FAILED;
2080         }
2081         if (bnx2x_test_intr(bp) != 0) {
2082                 buf[4] = 1;
2083                 etest->flags |= ETH_TEST_FL_FAILED;
2084         }
2085
2086         if (bnx2x_link_test(bp, is_serdes) != 0) {
2087                 buf[5] = 1;
2088                 etest->flags |= ETH_TEST_FL_FAILED;
2089         }
2090
2091 #ifdef BNX2X_EXTRA_DEBUG
2092         bnx2x_panic_dump(bp);
2093 #endif
2094 }
2095
2096 #define IS_PORT_STAT(i) \
2097         ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
2098 #define IS_FUNC_STAT(i)         (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
2099 #define IS_MF_MODE_STAT(bp) \
2100                         (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
2101
2102 /* ethtool statistics are displayed for all regular ethernet queues and the
2103  * fcoe L2 queue if not disabled
2104  */
2105 static inline int bnx2x_num_stat_queues(struct bnx2x *bp)
2106 {
2107         return BNX2X_NUM_ETH_QUEUES(bp);
2108 }
2109
2110 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
2111 {
2112         struct bnx2x *bp = netdev_priv(dev);
2113         int i, num_stats;
2114
2115         switch (stringset) {
2116         case ETH_SS_STATS:
2117                 if (is_multi(bp)) {
2118                         num_stats = bnx2x_num_stat_queues(bp) *
2119                                 BNX2X_NUM_Q_STATS;
2120                         if (!IS_MF_MODE_STAT(bp))
2121                                 num_stats += BNX2X_NUM_STATS;
2122                 } else {
2123                         if (IS_MF_MODE_STAT(bp)) {
2124                                 num_stats = 0;
2125                                 for (i = 0; i < BNX2X_NUM_STATS; i++)
2126                                         if (IS_FUNC_STAT(i))
2127                                                 num_stats++;
2128                         } else
2129                                 num_stats = BNX2X_NUM_STATS;
2130                 }
2131                 return num_stats;
2132
2133         case ETH_SS_TEST:
2134                 return BNX2X_NUM_TESTS;
2135
2136         default:
2137                 return -EINVAL;
2138         }
2139 }
2140
2141 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
2142 {
2143         struct bnx2x *bp = netdev_priv(dev);
2144         int i, j, k;
2145         char queue_name[MAX_QUEUE_NAME_LEN+1];
2146
2147         switch (stringset) {
2148         case ETH_SS_STATS:
2149                 if (is_multi(bp)) {
2150                         k = 0;
2151                         for_each_eth_queue(bp, i) {
2152                                 memset(queue_name, 0, sizeof(queue_name));
2153                                 sprintf(queue_name, "%d", i);
2154                                 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
2155                                         snprintf(buf + (k + j)*ETH_GSTRING_LEN,
2156                                                 ETH_GSTRING_LEN,
2157                                                 bnx2x_q_stats_arr[j].string,
2158                                                 queue_name);
2159                                 k += BNX2X_NUM_Q_STATS;
2160                         }
2161                         if (IS_MF_MODE_STAT(bp))
2162                                 break;
2163                         for (j = 0; j < BNX2X_NUM_STATS; j++)
2164                                 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
2165                                        bnx2x_stats_arr[j].string);
2166                 } else {
2167                         for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2168                                 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2169                                         continue;
2170                                 strcpy(buf + j*ETH_GSTRING_LEN,
2171                                        bnx2x_stats_arr[i].string);
2172                                 j++;
2173                         }
2174                 }
2175                 break;
2176
2177         case ETH_SS_TEST:
2178                 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
2179                 break;
2180         }
2181 }
2182
2183 static void bnx2x_get_ethtool_stats(struct net_device *dev,
2184                                     struct ethtool_stats *stats, u64 *buf)
2185 {
2186         struct bnx2x *bp = netdev_priv(dev);
2187         u32 *hw_stats, *offset;
2188         int i, j, k;
2189
2190         if (is_multi(bp)) {
2191                 k = 0;
2192                 for_each_eth_queue(bp, i) {
2193                         hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
2194                         for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
2195                                 if (bnx2x_q_stats_arr[j].size == 0) {
2196                                         /* skip this counter */
2197                                         buf[k + j] = 0;
2198                                         continue;
2199                                 }
2200                                 offset = (hw_stats +
2201                                           bnx2x_q_stats_arr[j].offset);
2202                                 if (bnx2x_q_stats_arr[j].size == 4) {
2203                                         /* 4-byte counter */
2204                                         buf[k + j] = (u64) *offset;
2205                                         continue;
2206                                 }
2207                                 /* 8-byte counter */
2208                                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2209                         }
2210                         k += BNX2X_NUM_Q_STATS;
2211                 }
2212                 if (IS_MF_MODE_STAT(bp))
2213                         return;
2214                 hw_stats = (u32 *)&bp->eth_stats;
2215                 for (j = 0; j < BNX2X_NUM_STATS; j++) {
2216                         if (bnx2x_stats_arr[j].size == 0) {
2217                                 /* skip this counter */
2218                                 buf[k + j] = 0;
2219                                 continue;
2220                         }
2221                         offset = (hw_stats + bnx2x_stats_arr[j].offset);
2222                         if (bnx2x_stats_arr[j].size == 4) {
2223                                 /* 4-byte counter */
2224                                 buf[k + j] = (u64) *offset;
2225                                 continue;
2226                         }
2227                         /* 8-byte counter */
2228                         buf[k + j] = HILO_U64(*offset, *(offset + 1));
2229                 }
2230         } else {
2231                 hw_stats = (u32 *)&bp->eth_stats;
2232                 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2233                         if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2234                                 continue;
2235                         if (bnx2x_stats_arr[i].size == 0) {
2236                                 /* skip this counter */
2237                                 buf[j] = 0;
2238                                 j++;
2239                                 continue;
2240                         }
2241                         offset = (hw_stats + bnx2x_stats_arr[i].offset);
2242                         if (bnx2x_stats_arr[i].size == 4) {
2243                                 /* 4-byte counter */
2244                                 buf[j] = (u64) *offset;
2245                                 j++;
2246                                 continue;
2247                         }
2248                         /* 8-byte counter */
2249                         buf[j] = HILO_U64(*offset, *(offset + 1));
2250                         j++;
2251                 }
2252         }
2253 }
2254
2255 static int bnx2x_set_phys_id(struct net_device *dev,
2256                              enum ethtool_phys_id_state state)
2257 {
2258         struct bnx2x *bp = netdev_priv(dev);
2259
2260         if (!netif_running(dev))
2261                 return -EAGAIN;
2262
2263         if (!bp->port.pmf)
2264                 return -EOPNOTSUPP;
2265
2266         switch (state) {
2267         case ETHTOOL_ID_ACTIVE:
2268                 return 1;       /* cycle on/off once per second */
2269
2270         case ETHTOOL_ID_ON:
2271                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2272                               LED_MODE_ON, SPEED_1000);
2273                 break;
2274
2275         case ETHTOOL_ID_OFF:
2276                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2277                               LED_MODE_FRONT_PANEL_OFF, 0);
2278
2279                 break;
2280
2281         case ETHTOOL_ID_INACTIVE:
2282                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2283                               LED_MODE_OPER,
2284                               bp->link_vars.line_speed);
2285         }
2286
2287         return 0;
2288 }
2289
2290 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2291                            u32 *rules __always_unused)
2292 {
2293         struct bnx2x *bp = netdev_priv(dev);
2294
2295         switch (info->cmd) {
2296         case ETHTOOL_GRXRINGS:
2297                 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2298                 return 0;
2299
2300         default:
2301                 return -EOPNOTSUPP;
2302         }
2303 }
2304
2305 static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
2306 {
2307         struct bnx2x *bp = netdev_priv(dev);
2308
2309         return (bp->multi_mode == ETH_RSS_MODE_DISABLED ?
2310                 0 : T_ETH_INDIRECTION_TABLE_SIZE);
2311 }
2312
2313 static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir)
2314 {
2315         struct bnx2x *bp = netdev_priv(dev);
2316         u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
2317         size_t i;
2318
2319         /* Get the current configuration of the RSS indirection table */
2320         bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
2321
2322         /*
2323          * We can't use a memcpy() as an internal storage of an
2324          * indirection table is a u8 array while indir->ring_index
2325          * points to an array of u32.
2326          *
2327          * Indirection table contains the FW Client IDs, so we need to
2328          * align the returned table to the Client ID of the leading RSS
2329          * queue.
2330          */
2331         for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
2332                 indir[i] = ind_table[i] - bp->fp->cl_id;
2333
2334         return 0;
2335 }
2336
2337 static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir)
2338 {
2339         struct bnx2x *bp = netdev_priv(dev);
2340         size_t i;
2341         u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
2342
2343         for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
2344                 /*
2345                  * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
2346                  * as an internal storage of an indirection table is a u8 array
2347                  * while indir->ring_index points to an array of u32.
2348                  *
2349                  * Indirection table contains the FW Client IDs, so we need to
2350                  * align the received table to the Client ID of the leading RSS
2351                  * queue
2352                  */
2353                 ind_table[i] = indir[i] + bp->fp->cl_id;
2354         }
2355
2356         return bnx2x_config_rss_pf(bp, ind_table, false);
2357 }
2358
2359 static const struct ethtool_ops bnx2x_ethtool_ops = {
2360         .get_settings           = bnx2x_get_settings,
2361         .set_settings           = bnx2x_set_settings,
2362         .get_drvinfo            = bnx2x_get_drvinfo,
2363         .get_regs_len           = bnx2x_get_regs_len,
2364         .get_regs               = bnx2x_get_regs,
2365         .get_wol                = bnx2x_get_wol,
2366         .set_wol                = bnx2x_set_wol,
2367         .get_msglevel           = bnx2x_get_msglevel,
2368         .set_msglevel           = bnx2x_set_msglevel,
2369         .nway_reset             = bnx2x_nway_reset,
2370         .get_link               = bnx2x_get_link,
2371         .get_eeprom_len         = bnx2x_get_eeprom_len,
2372         .get_eeprom             = bnx2x_get_eeprom,
2373         .set_eeprom             = bnx2x_set_eeprom,
2374         .get_coalesce           = bnx2x_get_coalesce,
2375         .set_coalesce           = bnx2x_set_coalesce,
2376         .get_ringparam          = bnx2x_get_ringparam,
2377         .set_ringparam          = bnx2x_set_ringparam,
2378         .get_pauseparam         = bnx2x_get_pauseparam,
2379         .set_pauseparam         = bnx2x_set_pauseparam,
2380         .self_test              = bnx2x_self_test,
2381         .get_sset_count         = bnx2x_get_sset_count,
2382         .get_strings            = bnx2x_get_strings,
2383         .set_phys_id            = bnx2x_set_phys_id,
2384         .get_ethtool_stats      = bnx2x_get_ethtool_stats,
2385         .get_rxnfc              = bnx2x_get_rxnfc,
2386         .get_rxfh_indir_size    = bnx2x_get_rxfh_indir_size,
2387         .get_rxfh_indir         = bnx2x_get_rxfh_indir,
2388         .set_rxfh_indir         = bnx2x_set_rxfh_indir,
2389 };
2390
2391 void bnx2x_set_ethtool_ops(struct net_device *netdev)
2392 {
2393         SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2394 }