drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

   1 /* bnx2x_main.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/kernel.h>
  23 #include <linux/device.h>  /* for dev_info() */
  24 #include <linux/timer.h>
  25 #include <linux/errno.h>
  26 #include <linux/ioport.h>
  27 #include <linux/slab.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/pci.h>
  30 #include <linux/init.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/bitops.h>
  36 #include <linux/irq.h>
  37 #include <linux/delay.h>
  38 #include <asm/byteorder.h>
  39 #include <linux/time.h>
  40 #include <linux/ethtool.h>
  41 #include <linux/mii.h>
  42 #include <linux/if_vlan.h>
  43 #include <net/ip.h>
  44 #include <net/ipv6.h>
  45 #include <net/tcp.h>
  46 #include <net/checksum.h>
  47 #include <net/ip6_checksum.h>
  48 #include <linux/workqueue.h>
  49 #include <linux/crc32.h>
  50 #include <linux/crc32c.h>
  51 #include <linux/prefetch.h>
  52 #include <linux/zlib.h>
  53 #include <linux/io.h>
  54 #include <linux/semaphore.h>
  55 #include <linux/stringify.h>
  56 #include <linux/vmalloc.h>
  57
  58 #include "bnx2x.h"
  59 #include "bnx2x_init.h"
  60 #include "bnx2x_init_ops.h"
  61 #include "bnx2x_cmn.h"
  62 #include "bnx2x_vfpf.h"
  63 #include "bnx2x_dcb.h"
  64 #include "bnx2x_sp.h"
  65
  66 #include <linux/firmware.h>
  67 #include "bnx2x_fw_file_hdr.h"
  68 /* FW files */
  69 #define FW_FILE_VERSION                                 \
  70         __stringify(BCM_5710_FW_MAJOR_VERSION) "."      \
  71         __stringify(BCM_5710_FW_MINOR_VERSION) "."      \
  72         __stringify(BCM_5710_FW_REVISION_VERSION) "."   \
  73         __stringify(BCM_5710_FW_ENGINEERING_VERSION)
  74 #define FW_FILE_NAME_E1         "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
  75 #define FW_FILE_NAME_E1H        "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
  76 #define FW_FILE_NAME_E2         "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
  77
  78 /* Time in jiffies before concluding the transmitter is hung */
  79 #define TX_TIMEOUT              (5*HZ)
  80
  81 static char version[] =
  82         "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
  83         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  84
  85 MODULE_AUTHOR("Eliezer Tamir");
  86 MODULE_DESCRIPTION("Broadcom NetXtreme II "
  87                    "BCM57710/57711/57711E/"
  88                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
  89                    "57840/57840_MF Driver");
  90 MODULE_LICENSE("GPL");
  91 MODULE_VERSION(DRV_MODULE_VERSION);
  92 MODULE_FIRMWARE(FW_FILE_NAME_E1);
  93 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
  94 MODULE_FIRMWARE(FW_FILE_NAME_E2);
  95
  96 int num_queues;
  97 module_param(num_queues, int, 0);
  98 MODULE_PARM_DESC(num_queues,
  99                  " Set number of queues (default is as a number of CPUs)");
 100
 101 static int disable_tpa;
 102 module_param(disable_tpa, int, 0);
 103 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
 104
 105 int int_mode;
 106 module_param(int_mode, int, 0);
 107 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
 108                                 "(1 INT#x; 2 MSI)");
 109
 110 static int dropless_fc;
 111 module_param(dropless_fc, int, 0);
 112 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
 113
 114 static int mrrs = -1;
 115 module_param(mrrs, int, 0);
 116 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
 117
 118 static int debug;
 119 module_param(debug, int, 0);
 120 MODULE_PARM_DESC(debug, " Default debug msglevel");
 121
 122 struct workqueue_struct *bnx2x_wq;
 123
 124 struct bnx2x_mac_vals {
 125         u32 xmac_addr;
 126         u32 xmac_val;
 127         u32 emac_addr;
 128         u32 emac_val;
 129         u32 umac_addr;
 130         u32 umac_val;
 131         u32 bmac_addr;
 132         u32 bmac_val[2];
 133 };
 134
 135 enum bnx2x_board_type {
 136         BCM57710 = 0,
 137         BCM57711,
 138         BCM57711E,
 139         BCM57712,
 140         BCM57712_MF,
 141         BCM57712_VF,
 142         BCM57800,
 143         BCM57800_MF,
 144         BCM57800_VF,
 145         BCM57810,
 146         BCM57810_MF,
 147         BCM57810_VF,
 148         BCM57840_4_10,
 149         BCM57840_2_20,
 150         BCM57840_MF,
 151         BCM57840_VF,
 152         BCM57811,
 153         BCM57811_MF,
 154         BCM57840_O,
 155         BCM57840_MFO,
 156         BCM57811_VF
 157 };
 158
 159 /* indexed by board_type, above */
 160 static struct {
 161         char *name;
 162 } board_info[] = {
 163         [BCM57710]      = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
 164         [BCM57711]      = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
 165         [BCM57711E]     = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
 166         [BCM57712]      = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
 167         [BCM57712_MF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
 168         [BCM57712_VF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
 169         [BCM57800]      = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
 170         [BCM57800_MF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
 171         [BCM57800_VF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
 172         [BCM57810]      = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
 173         [BCM57810_MF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
 174         [BCM57810_VF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
 175         [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
 176         [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
 177         [BCM57840_MF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 178         [BCM57840_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
 179         [BCM57811]      = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
 180         [BCM57811_MF]   = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
 181         [BCM57840_O]    = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
 182         [BCM57840_MFO]  = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 183         [BCM57811_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
 184 };
 185
 186 #ifndef PCI_DEVICE_ID_NX2_57710
 187 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
 188 #endif
 189 #ifndef PCI_DEVICE_ID_NX2_57711
 190 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
 191 #endif
 192 #ifndef PCI_DEVICE_ID_NX2_57711E
 193 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
 194 #endif
 195 #ifndef PCI_DEVICE_ID_NX2_57712
 196 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
 197 #endif
 198 #ifndef PCI_DEVICE_ID_NX2_57712_MF
 199 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
 200 #endif
 201 #ifndef PCI_DEVICE_ID_NX2_57712_VF
 202 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
 203 #endif
 204 #ifndef PCI_DEVICE_ID_NX2_57800
 205 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
 206 #endif
 207 #ifndef PCI_DEVICE_ID_NX2_57800_MF
 208 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
 209 #endif
 210 #ifndef PCI_DEVICE_ID_NX2_57800_VF
 211 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
 212 #endif
 213 #ifndef PCI_DEVICE_ID_NX2_57810
 214 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
 215 #endif
 216 #ifndef PCI_DEVICE_ID_NX2_57810_MF
 217 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
 218 #endif
 219 #ifndef PCI_DEVICE_ID_NX2_57840_O
 220 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
 221 #endif
 222 #ifndef PCI_DEVICE_ID_NX2_57810_VF
 223 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
 224 #endif
 225 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
 226 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
 227 #endif
 228 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
 229 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
 230 #endif
 231 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
 232 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
 233 #endif
 234 #ifndef PCI_DEVICE_ID_NX2_57840_MF
 235 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
 236 #endif
 237 #ifndef PCI_DEVICE_ID_NX2_57840_VF
 238 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
 239 #endif
 240 #ifndef PCI_DEVICE_ID_NX2_57811
 241 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
 242 #endif
 243 #ifndef PCI_DEVICE_ID_NX2_57811_MF
 244 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
 245 #endif
 246 #ifndef PCI_DEVICE_ID_NX2_57811_VF
 247 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
 248 #endif
 249
 250 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
 251         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
 252         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
 253         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
 254         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
 255         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
 256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
 257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
 258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
 259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
 260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
 261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
 262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
 263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
 265         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
 266         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
 267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 268         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 269         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
 270         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
 271         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
 272         { 0 }
 273 };
 274
 275 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 276
 277 /* Global resources for unloading a previously loaded device */
 278 #define BNX2X_PREV_WAIT_NEEDED 1
 279 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
 280 static LIST_HEAD(bnx2x_prev_list);
 281 /****************************************************************************
 282 * General service functions
 283 ****************************************************************************/
 284
 285 static void __storm_memset_dma_mapping(struct bnx2x *bp,
 286                                        u32 addr, dma_addr_t mapping)
 287 {
 288         REG_WR(bp,  addr, U64_LO(mapping));
 289         REG_WR(bp,  addr + 4, U64_HI(mapping));
 290 }
 291
 292 static void storm_memset_spq_addr(struct bnx2x *bp,
 293                                   dma_addr_t mapping, u16 abs_fid)
 294 {
 295         u32 addr = XSEM_REG_FAST_MEMORY +
 296                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
 297
 298         __storm_memset_dma_mapping(bp, addr, mapping);
 299 }
 300
 301 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
 302                                   u16 pf_id)
 303 {
 304         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
 305                 pf_id);
 306         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
 307                 pf_id);
 308         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
 309                 pf_id);
 310         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
 311                 pf_id);
 312 }
 313
 314 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
 315                                  u8 enable)
 316 {
 317         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
 318                 enable);
 319         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
 320                 enable);
 321         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
 322                 enable);
 323         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
 324                 enable);
 325 }
 326
 327 static void storm_memset_eq_data(struct bnx2x *bp,
 328                                  struct event_ring_data *eq_data,
 329                                 u16 pfid)
 330 {
 331         size_t size = sizeof(struct event_ring_data);
 332
 333         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
 334
 335         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
 336 }
 337
 338 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
 339                                  u16 pfid)
 340 {
 341         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
 342         REG_WR16(bp, addr, eq_prod);
 343 }
 344
 345 /* used only at init
 346  * locking is done by mcp
 347  */
 348 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 349 {
 350         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 351         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
 352         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 353                                PCICFG_VENDOR_ID_OFFSET);
 354 }
 355
 356 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
 357 {
 358         u32 val;
 359
 360         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 361         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
 362         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 363                                PCICFG_VENDOR_ID_OFFSET);
 364
 365         return val;
 366 }
 367
 368 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
 369 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
 370 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
 371 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
 372 #define DMAE_DP_DST_NONE        "dst_addr [none]"
 373
 374 static void bnx2x_dp_dmae(struct bnx2x *bp,
 375                           struct dmae_command *dmae, int msglvl)
 376 {
 377         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
 378         int i;
 379
 380         switch (dmae->opcode & DMAE_COMMAND_DST) {
 381         case DMAE_CMD_DST_PCI:
 382                 if (src_type == DMAE_CMD_SRC_PCI)
 383                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 384                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
 385                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 386                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 387                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 388                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 389                            dmae->comp_val);
 390                 else
 391                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 392                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
 393                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 394                            dmae->opcode, dmae->src_addr_lo >> 2,
 395                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 396                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 397                            dmae->comp_val);
 398                 break;
 399         case DMAE_CMD_DST_GRC:
 400                 if (src_type == DMAE_CMD_SRC_PCI)
 401                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 402                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
 403                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 404                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 405                            dmae->len, dmae->dst_addr_lo >> 2,
 406                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 407                            dmae->comp_val);
 408                 else
 409                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 410                            "src [%08x], len [%d*4], dst [%08x]\n"
 411                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 412                            dmae->opcode, dmae->src_addr_lo >> 2,
 413                            dmae->len, dmae->dst_addr_lo >> 2,
 414                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 415                            dmae->comp_val);
 416                 break;
 417         default:
 418                 if (src_type == DMAE_CMD_SRC_PCI)
 419                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 420                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
 421                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 422                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 423                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 424                            dmae->comp_val);
 425                 else
 426                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 427                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
 428                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 429                            dmae->opcode, dmae->src_addr_lo >> 2,
 430                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 431                            dmae->comp_val);
 432                 break;
 433         }
 434
 435         for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
 436                 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
 437                    i, *(((u32 *)dmae) + i));
 438 }
 439
 440 /* copy command into DMAE command memory and set DMAE command go */
 441 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
 442 {
 443         u32 cmd_offset;
 444         int i;
 445
 446         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
 447         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
 448                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
 449         }
 450         REG_WR(bp, dmae_reg_go_c[idx], 1);
 451 }
 452
 453 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
 454 {
 455         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 456                            DMAE_CMD_C_ENABLE);
 457 }
 458
 459 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
 460 {
 461         return opcode & ~DMAE_CMD_SRC_RESET;
 462 }
 463
 464 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
 465                              bool with_comp, u8 comp_type)
 466 {
 467         u32 opcode = 0;
 468
 469         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 470                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 471
 472         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
 473
 474         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 475         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
 476                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
 477         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 478
 479 #ifdef __BIG_ENDIAN
 480         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 481 #else
 482         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 483 #endif
 484         if (with_comp)
 485                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 486         return opcode;
 487 }
 488
 489 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
 490                                       struct dmae_command *dmae,
 491                                       u8 src_type, u8 dst_type)
 492 {
 493         memset(dmae, 0, sizeof(struct dmae_command));
 494
 495         /* set the opcode */
 496         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
 497                                          true, DMAE_COMP_PCI);
 498
 499         /* fill in the completion parameters */
 500         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 501         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 502         dmae->comp_val = DMAE_COMP_VAL;
 503 }
 504
 505 /* issue a dmae command over the init-channel and wait for completion */
 506 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
 507                                u32 *comp)
 508 {
 509         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
 510         int rc = 0;
 511
 512         bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
 513
 514         /* Lock the dmae channel. Disable BHs to prevent a dead-lock
 515          * as long as this code is called both from syscall context and
 516          * from ndo_set_rx_mode() flow that may be called from BH.
 517          */
 518         spin_lock_bh(&bp->dmae_lock);
 519
 520         /* reset completion */
 521         *comp = 0;
 522
 523         /* post the command on the channel used for initializations */
 524         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 525
 526         /* wait for completion */
 527         udelay(5);
 528         while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 529
 530                 if (!cnt ||
 531                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
 532                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 533                         BNX2X_ERR("DMAE timeout!\n");
 534                         rc = DMAE_TIMEOUT;
 535                         goto unlock;
 536                 }
 537                 cnt--;
 538                 udelay(50);
 539         }
 540         if (*comp & DMAE_PCI_ERR_FLAG) {
 541                 BNX2X_ERR("DMAE PCI error!\n");
 542                 rc = DMAE_PCI_ERROR;
 543         }
 544
 545 unlock:
 546         spin_unlock_bh(&bp->dmae_lock);
 547         return rc;
 548 }
 549
 550 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 551                       u32 len32)
 552 {
 553         int rc;
 554         struct dmae_command dmae;
 555
 556         if (!bp->dmae_ready) {
 557                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 558
 559                 if (CHIP_IS_E1(bp))
 560                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
 561                 else
 562                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
 563                 return;
 564         }
 565
 566         /* set opcode and fixed command fields */
 567         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 568
 569         /* fill in addresses and len */
 570         dmae.src_addr_lo = U64_LO(dma_addr);
 571         dmae.src_addr_hi = U64_HI(dma_addr);
 572         dmae.dst_addr_lo = dst_addr >> 2;
 573         dmae.dst_addr_hi = 0;
 574         dmae.len = len32;
 575
 576         /* issue the command and wait for completion */
 577         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 578         if (rc) {
 579                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 580                 bnx2x_panic();
 581         }
 582 }
 583
 584 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 585 {
 586         int rc;
 587         struct dmae_command dmae;
 588
 589         if (!bp->dmae_ready) {
 590                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 591                 int i;
 592
 593                 if (CHIP_IS_E1(bp))
 594                         for (i = 0; i < len32; i++)
 595                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
 596                 else
 597                         for (i = 0; i < len32; i++)
 598                                 data[i] = REG_RD(bp, src_addr + i*4);
 599
 600                 return;
 601         }
 602
 603         /* set opcode and fixed command fields */
 604         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 605
 606         /* fill in addresses and len */
 607         dmae.src_addr_lo = src_addr >> 2;
 608         dmae.src_addr_hi = 0;
 609         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
 610         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
 611         dmae.len = len32;
 612
 613         /* issue the command and wait for completion */
 614         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 615         if (rc) {
 616                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 617                 bnx2x_panic();
 618         }
 619 }
 620
 621 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
 622                                       u32 addr, u32 len)
 623 {
 624         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
 625         int offset = 0;
 626
 627         while (len > dmae_wr_max) {
 628                 bnx2x_write_dmae(bp, phys_addr + offset,
 629                                  addr + offset, dmae_wr_max);
 630                 offset += dmae_wr_max * 4;
 631                 len -= dmae_wr_max;
 632         }
 633
 634         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
 635 }
 636
 637 static int bnx2x_mc_assert(struct bnx2x *bp)
 638 {
 639         char last_idx;
 640         int i, rc = 0;
 641         u32 row0, row1, row2, row3;
 642
 643         /* XSTORM */
 644         last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
 645                            XSTORM_ASSERT_LIST_INDEX_OFFSET);
 646         if (last_idx)
 647                 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 648
 649         /* print the asserts */
 650         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 651
 652                 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 653                               XSTORM_ASSERT_LIST_OFFSET(i));
 654                 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 655                               XSTORM_ASSERT_LIST_OFFSET(i) + 4);
 656                 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 657                               XSTORM_ASSERT_LIST_OFFSET(i) + 8);
 658                 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 659                               XSTORM_ASSERT_LIST_OFFSET(i) + 12);
 660
 661                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 662                         BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 663                                   i, row3, row2, row1, row0);
 664                         rc++;
 665                 } else {
 666                         break;
 667                 }
 668         }
 669
 670         /* TSTORM */
 671         last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
 672                            TSTORM_ASSERT_LIST_INDEX_OFFSET);
 673         if (last_idx)
 674                 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 675
 676         /* print the asserts */
 677         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 678
 679                 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 680                               TSTORM_ASSERT_LIST_OFFSET(i));
 681                 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 682                               TSTORM_ASSERT_LIST_OFFSET(i) + 4);
 683                 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 684                               TSTORM_ASSERT_LIST_OFFSET(i) + 8);
 685                 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 686                               TSTORM_ASSERT_LIST_OFFSET(i) + 12);
 687
 688                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 689                         BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 690                                   i, row3, row2, row1, row0);
 691                         rc++;
 692                 } else {
 693                         break;
 694                 }
 695         }
 696
 697         /* CSTORM */
 698         last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
 699                            CSTORM_ASSERT_LIST_INDEX_OFFSET);
 700         if (last_idx)
 701                 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 702
 703         /* print the asserts */
 704         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 705
 706                 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 707                               CSTORM_ASSERT_LIST_OFFSET(i));
 708                 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 709                               CSTORM_ASSERT_LIST_OFFSET(i) + 4);
 710                 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 711                               CSTORM_ASSERT_LIST_OFFSET(i) + 8);
 712                 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 713                               CSTORM_ASSERT_LIST_OFFSET(i) + 12);
 714
 715                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 716                         BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 717                                   i, row3, row2, row1, row0);
 718                         rc++;
 719                 } else {
 720                         break;
 721                 }
 722         }
 723
 724         /* USTORM */
 725         last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
 726                            USTORM_ASSERT_LIST_INDEX_OFFSET);
 727         if (last_idx)
 728                 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 729
 730         /* print the asserts */
 731         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 732
 733                 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
 734                               USTORM_ASSERT_LIST_OFFSET(i));
 735                 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
 736                               USTORM_ASSERT_LIST_OFFSET(i) + 4);
 737                 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
 738                               USTORM_ASSERT_LIST_OFFSET(i) + 8);
 739                 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
 740                               USTORM_ASSERT_LIST_OFFSET(i) + 12);
 741
 742                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 743                         BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 744                                   i, row3, row2, row1, row0);
 745                         rc++;
 746                 } else {
 747                         break;
 748                 }
 749         }
 750
 751         return rc;
 752 }
 753
 754 #define MCPR_TRACE_BUFFER_SIZE  (0x800)
 755 #define SCRATCH_BUFFER_SIZE(bp) \
 756         (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
 757
 758 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
 759 {
 760         u32 addr, val;
 761         u32 mark, offset;
 762         __be32 data[9];
 763         int word;
 764         u32 trace_shmem_base;
 765         if (BP_NOMCP(bp)) {
 766                 BNX2X_ERR("NO MCP - can not dump\n");
 767                 return;
 768         }
 769         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
 770                 (bp->common.bc_ver & 0xff0000) >> 16,
 771                 (bp->common.bc_ver & 0xff00) >> 8,
 772                 (bp->common.bc_ver & 0xff));
 773
 774         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
 775         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
 776                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
 777
 778         if (BP_PATH(bp) == 0)
 779                 trace_shmem_base = bp->common.shmem_base;
 780         else
 781                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
 782
 783         /* sanity */
 784         if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
 785             trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
 786                                 SCRATCH_BUFFER_SIZE(bp)) {
 787                 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
 788                           trace_shmem_base);
 789                 return;
 790         }
 791
 792         addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
 793
 794         /* validate TRCB signature */
 795         mark = REG_RD(bp, addr);
 796         if (mark != MFW_TRACE_SIGNATURE) {
 797                 BNX2X_ERR("Trace buffer signature is missing.");
 798                 return ;
 799         }
 800
 801         /* read cyclic buffer pointer */
 802         addr += 4;
 803         mark = REG_RD(bp, addr);
 804         mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
 805         if (mark >= trace_shmem_base || mark < addr + 4) {
 806                 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
 807                 return;
 808         }
 809         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
 810
 811         printk("%s", lvl);
 812
 813         /* dump buffer after the mark */
 814         for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
 815                 for (word = 0; word < 8; word++)
 816                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 817                 data[8] = 0x0;
 818                 pr_cont("%s", (char *)data);
 819         }
 820
 821         /* dump buffer before the mark */
 822         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
 823                 for (word = 0; word < 8; word++)
 824                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 825                 data[8] = 0x0;
 826                 pr_cont("%s", (char *)data);
 827         }
 828         printk("%s" "end of fw dump\n", lvl);
 829 }
 830
 831 static void bnx2x_fw_dump(struct bnx2x *bp)
 832 {
 833         bnx2x_fw_dump_lvl(bp, KERN_ERR);
 834 }
 835
 836 static void bnx2x_hc_int_disable(struct bnx2x *bp)
 837 {
 838         int port = BP_PORT(bp);
 839         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
 840         u32 val = REG_RD(bp, addr);
 841
 842         /* in E1 we must use only PCI configuration space to disable
 843          * MSI/MSIX capability
 844          * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
 845          */
 846         if (CHIP_IS_E1(bp)) {
 847                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
 848                  * Use mask register to prevent from HC sending interrupts
 849                  * after we exit the function
 850                  */
 851                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
 852
 853                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 854                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 855                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 856         } else
 857                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 858                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
 859                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 860                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 861
 862         DP(NETIF_MSG_IFDOWN,
 863            "write %x to HC %d (addr 0x%x)\n",
 864            val, port, addr);
 865
 866         /* flush all outstanding writes */
 867         mmiowb();
 868
 869         REG_WR(bp, addr, val);
 870         if (REG_RD(bp, addr) != val)
 871                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 872 }
 873
 874 static void bnx2x_igu_int_disable(struct bnx2x *bp)
 875 {
 876         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
 877
 878         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
 879                  IGU_PF_CONF_INT_LINE_EN |
 880                  IGU_PF_CONF_ATTN_BIT_EN);
 881
 882         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
 883
 884         /* flush all outstanding writes */
 885         mmiowb();
 886
 887         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
 888         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
 889                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 890 }
 891
 892 static void bnx2x_int_disable(struct bnx2x *bp)
 893 {
 894         if (bp->common.int_block == INT_BLOCK_HC)
 895                 bnx2x_hc_int_disable(bp);
 896         else
 897                 bnx2x_igu_int_disable(bp);
 898 }
 899
 900 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
 901 {
 902         int i;
 903         u16 j;
 904         struct hc_sp_status_block_data sp_sb_data;
 905         int func = BP_FUNC(bp);
 906 #ifdef BNX2X_STOP_ON_ERROR
 907         u16 start = 0, end = 0;
 908         u8 cos;
 909 #endif
 910         if (disable_int)
 911                 bnx2x_int_disable(bp);
 912
 913         bp->stats_state = STATS_STATE_DISABLED;
 914         bp->eth_stats.unrecoverable_error++;
 915         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
 916
 917         BNX2X_ERR("begin crash dump -----------------\n");
 918
 919         /* Indices */
 920         /* Common */
 921         BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
 922                   bp->def_idx, bp->def_att_idx, bp->attn_state,
 923                   bp->spq_prod_idx, bp->stats_counter);
 924         BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
 925                   bp->def_status_blk->atten_status_block.attn_bits,
 926                   bp->def_status_blk->atten_status_block.attn_bits_ack,
 927                   bp->def_status_blk->atten_status_block.status_block_id,
 928                   bp->def_status_blk->atten_status_block.attn_bits_index);
 929         BNX2X_ERR("     def (");
 930         for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
 931                 pr_cont("0x%x%s",
 932                         bp->def_status_blk->sp_sb.index_values[i],
 933                         (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
 934
 935         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
 936                 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
 937                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
 938                         i*sizeof(u32));
 939
 940         pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
 941                sp_sb_data.igu_sb_id,
 942                sp_sb_data.igu_seg_id,
 943                sp_sb_data.p_func.pf_id,
 944                sp_sb_data.p_func.vnic_id,
 945                sp_sb_data.p_func.vf_id,
 946                sp_sb_data.p_func.vf_valid,
 947                sp_sb_data.state);
 948
 949         for_each_eth_queue(bp, i) {
 950                 struct bnx2x_fastpath *fp = &bp->fp[i];
 951                 int loop;
 952                 struct hc_status_block_data_e2 sb_data_e2;
 953                 struct hc_status_block_data_e1x sb_data_e1x;
 954                 struct hc_status_block_sm  *hc_sm_p =
 955                         CHIP_IS_E1x(bp) ?
 956                         sb_data_e1x.common.state_machine :
 957                         sb_data_e2.common.state_machine;
 958                 struct hc_index_data *hc_index_p =
 959                         CHIP_IS_E1x(bp) ?
 960                         sb_data_e1x.index_data :
 961                         sb_data_e2.index_data;
 962                 u8 data_size, cos;
 963                 u32 *sb_data_p;
 964                 struct bnx2x_fp_txdata txdata;
 965
 966                 /* Rx */
 967                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
 968                           i, fp->rx_bd_prod, fp->rx_bd_cons,
 969                           fp->rx_comp_prod,
 970                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
 971                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
 972                           fp->rx_sge_prod, fp->last_max_sge,
 973                           le16_to_cpu(fp->fp_hc_idx));
 974
 975                 /* Tx */
 976                 for_each_cos_in_tx_queue(fp, cos)
 977                 {
 978                         txdata = *fp->txdata_ptr[cos];
 979                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
 980                                   i, txdata.tx_pkt_prod,
 981                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
 982                                   txdata.tx_bd_cons,
 983                                   le16_to_cpu(*txdata.tx_cons_sb));
 984                 }
 985
 986                 loop = CHIP_IS_E1x(bp) ?
 987                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
 988
 989                 /* host sb data */
 990
 991                 if (IS_FCOE_FP(fp))
 992                         continue;
 993
 994                 BNX2X_ERR("     run indexes (");
 995                 for (j = 0; j < HC_SB_MAX_SM; j++)
 996                         pr_cont("0x%x%s",
 997                                fp->sb_running_index[j],
 998                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
 999
1000                 BNX2X_ERR("     indexes (");
1001                 for (j = 0; j < loop; j++)
1002                         pr_cont("0x%x%s",
1003                                fp->sb_index_values[j],
1004                                (j == loop - 1) ? ")" : " ");
1005                 /* fw sb data */
1006                 data_size = CHIP_IS_E1x(bp) ?
1007                         sizeof(struct hc_status_block_data_e1x) :
1008                         sizeof(struct hc_status_block_data_e2);
1009                 data_size /= sizeof(u32);
1010                 sb_data_p = CHIP_IS_E1x(bp) ?
1011                         (u32 *)&sb_data_e1x :
1012                         (u32 *)&sb_data_e2;
1013                 /* copy sb data in here */
1014                 for (j = 0; j < data_size; j++)
1015                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1016                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1017                                 j * sizeof(u32));
1018
1019                 if (!CHIP_IS_E1x(bp)) {
1020                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1021                                 sb_data_e2.common.p_func.pf_id,
1022                                 sb_data_e2.common.p_func.vf_id,
1023                                 sb_data_e2.common.p_func.vf_valid,
1024                                 sb_data_e2.common.p_func.vnic_id,
1025                                 sb_data_e2.common.same_igu_sb_1b,
1026                                 sb_data_e2.common.state);
1027                 } else {
1028                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1029                                 sb_data_e1x.common.p_func.pf_id,
1030                                 sb_data_e1x.common.p_func.vf_id,
1031                                 sb_data_e1x.common.p_func.vf_valid,
1032                                 sb_data_e1x.common.p_func.vnic_id,
1033                                 sb_data_e1x.common.same_igu_sb_1b,
1034                                 sb_data_e1x.common.state);
1035                 }
1036
1037                 /* SB_SMs data */
1038                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1039                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1040                                 j, hc_sm_p[j].__flags,
1041                                 hc_sm_p[j].igu_sb_id,
1042                                 hc_sm_p[j].igu_seg_id,
1043                                 hc_sm_p[j].time_to_expire,
1044                                 hc_sm_p[j].timer_value);
1045                 }
1046
1047                 /* Indices data */
1048                 for (j = 0; j < loop; j++) {
1049                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1050                                hc_index_p[j].flags,
1051                                hc_index_p[j].timeout);
1052                 }
1053         }
1054
1055 #ifdef BNX2X_STOP_ON_ERROR
1056
1057         /* event queue */
1058         BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1059         for (i = 0; i < NUM_EQ_DESC; i++) {
1060                 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1061
1062                 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1063                           i, bp->eq_ring[i].message.opcode,
1064                           bp->eq_ring[i].message.error);
1065                 BNX2X_ERR("data: %x %x %x\n", data[0], data[1], data[2]);
1066         }
1067
1068         /* Rings */
1069         /* Rx */
1070         for_each_valid_rx_queue(bp, i) {
1071                 struct bnx2x_fastpath *fp = &bp->fp[i];
1072
1073                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1074                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1075                 for (j = start; j != end; j = RX_BD(j + 1)) {
1076                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1077                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1078
1079                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1080                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1081                 }
1082
1083                 start = RX_SGE(fp->rx_sge_prod);
1084                 end = RX_SGE(fp->last_max_sge);
1085                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1086                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1087                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1088
1089                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1090                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1091                 }
1092
1093                 start = RCQ_BD(fp->rx_comp_cons - 10);
1094                 end = RCQ_BD(fp->rx_comp_cons + 503);
1095                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1096                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1097
1098                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1099                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1100                 }
1101         }
1102
1103         /* Tx */
1104         for_each_valid_tx_queue(bp, i) {
1105                 struct bnx2x_fastpath *fp = &bp->fp[i];
1106                 for_each_cos_in_tx_queue(fp, cos) {
1107                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1108
1109                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1110                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1111                         for (j = start; j != end; j = TX_BD(j + 1)) {
1112                                 struct sw_tx_bd *sw_bd =
1113                                         &txdata->tx_buf_ring[j];
1114
1115                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1116                                           i, cos, j, sw_bd->skb,
1117                                           sw_bd->first_bd);
1118                         }
1119
1120                         start = TX_BD(txdata->tx_bd_cons - 10);
1121                         end = TX_BD(txdata->tx_bd_cons + 254);
1122                         for (j = start; j != end; j = TX_BD(j + 1)) {
1123                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1124
1125                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1126                                           i, cos, j, tx_bd[0], tx_bd[1],
1127                                           tx_bd[2], tx_bd[3]);
1128                         }
1129                 }
1130         }
1131 #endif
1132         bnx2x_fw_dump(bp);
1133         bnx2x_mc_assert(bp);
1134         BNX2X_ERR("end crash dump -----------------\n");
1135 }
1136
1137 /*
1138  * FLR Support for E2
1139  *
1140  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1141  * initialization.
1142  */
1143 #define FLR_WAIT_USEC           10000   /* 10 milliseconds */
1144 #define FLR_WAIT_INTERVAL       50      /* usec */
1145 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1146
1147 struct pbf_pN_buf_regs {
1148         int pN;
1149         u32 init_crd;
1150         u32 crd;
1151         u32 crd_freed;
1152 };
1153
1154 struct pbf_pN_cmd_regs {
1155         int pN;
1156         u32 lines_occup;
1157         u32 lines_freed;
1158 };
1159
1160 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1161                                      struct pbf_pN_buf_regs *regs,
1162                                      u32 poll_count)
1163 {
1164         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1165         u32 cur_cnt = poll_count;
1166
1167         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1168         crd = crd_start = REG_RD(bp, regs->crd);
1169         init_crd = REG_RD(bp, regs->init_crd);
1170
1171         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1172         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1173         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1174
1175         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1176                (init_crd - crd_start))) {
1177                 if (cur_cnt--) {
1178                         udelay(FLR_WAIT_INTERVAL);
1179                         crd = REG_RD(bp, regs->crd);
1180                         crd_freed = REG_RD(bp, regs->crd_freed);
1181                 } else {
1182                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1183                            regs->pN);
1184                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1185                            regs->pN, crd);
1186                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1187                            regs->pN, crd_freed);
1188                         break;
1189                 }
1190         }
1191         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1192            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1193 }
1194
1195 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1196                                      struct pbf_pN_cmd_regs *regs,
1197                                      u32 poll_count)
1198 {
1199         u32 occup, to_free, freed, freed_start;
1200         u32 cur_cnt = poll_count;
1201
1202         occup = to_free = REG_RD(bp, regs->lines_occup);
1203         freed = freed_start = REG_RD(bp, regs->lines_freed);
1204
1205         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1206         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1207
1208         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1209                 if (cur_cnt--) {
1210                         udelay(FLR_WAIT_INTERVAL);
1211                         occup = REG_RD(bp, regs->lines_occup);
1212                         freed = REG_RD(bp, regs->lines_freed);
1213                 } else {
1214                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1215                            regs->pN);
1216                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1217                            regs->pN, occup);
1218                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1219                            regs->pN, freed);
1220                         break;
1221                 }
1222         }
1223         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1224            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1225 }
1226
1227 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1228                                     u32 expected, u32 poll_count)
1229 {
1230         u32 cur_cnt = poll_count;
1231         u32 val;
1232
1233         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1234                 udelay(FLR_WAIT_INTERVAL);
1235
1236         return val;
1237 }
1238
1239 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1240                                     char *msg, u32 poll_cnt)
1241 {
1242         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1243         if (val != 0) {
1244                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1245                 return 1;
1246         }
1247         return 0;
1248 }
1249
1250 /* Common routines with VF FLR cleanup */
1251 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1252 {
1253         /* adjust polling timeout */
1254         if (CHIP_REV_IS_EMUL(bp))
1255                 return FLR_POLL_CNT * 2000;
1256
1257         if (CHIP_REV_IS_FPGA(bp))
1258                 return FLR_POLL_CNT * 120;
1259
1260         return FLR_POLL_CNT;
1261 }
1262
1263 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1264 {
1265         struct pbf_pN_cmd_regs cmd_regs[] = {
1266                 {0, (CHIP_IS_E3B0(bp)) ?
1267                         PBF_REG_TQ_OCCUPANCY_Q0 :
1268                         PBF_REG_P0_TQ_OCCUPANCY,
1269                     (CHIP_IS_E3B0(bp)) ?
1270                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1271                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1272                 {1, (CHIP_IS_E3B0(bp)) ?
1273                         PBF_REG_TQ_OCCUPANCY_Q1 :
1274                         PBF_REG_P1_TQ_OCCUPANCY,
1275                     (CHIP_IS_E3B0(bp)) ?
1276                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1277                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1278                 {4, (CHIP_IS_E3B0(bp)) ?
1279                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1280                         PBF_REG_P4_TQ_OCCUPANCY,
1281                     (CHIP_IS_E3B0(bp)) ?
1282                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1283                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1284         };
1285
1286         struct pbf_pN_buf_regs buf_regs[] = {
1287                 {0, (CHIP_IS_E3B0(bp)) ?
1288                         PBF_REG_INIT_CRD_Q0 :
1289                         PBF_REG_P0_INIT_CRD ,
1290                     (CHIP_IS_E3B0(bp)) ?
1291                         PBF_REG_CREDIT_Q0 :
1292                         PBF_REG_P0_CREDIT,
1293                     (CHIP_IS_E3B0(bp)) ?
1294                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1295                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1296                 {1, (CHIP_IS_E3B0(bp)) ?
1297                         PBF_REG_INIT_CRD_Q1 :
1298                         PBF_REG_P1_INIT_CRD,
1299                     (CHIP_IS_E3B0(bp)) ?
1300                         PBF_REG_CREDIT_Q1 :
1301                         PBF_REG_P1_CREDIT,
1302                     (CHIP_IS_E3B0(bp)) ?
1303                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1304                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1305                 {4, (CHIP_IS_E3B0(bp)) ?
1306                         PBF_REG_INIT_CRD_LB_Q :
1307                         PBF_REG_P4_INIT_CRD,
1308                     (CHIP_IS_E3B0(bp)) ?
1309                         PBF_REG_CREDIT_LB_Q :
1310                         PBF_REG_P4_CREDIT,
1311                     (CHIP_IS_E3B0(bp)) ?
1312                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1313                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1314         };
1315
1316         int i;
1317
1318         /* Verify the command queues are flushed P0, P1, P4 */
1319         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1320                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1321
1322         /* Verify the transmission buffers are flushed P0, P1, P4 */
1323         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1324                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1325 }
1326
1327 #define OP_GEN_PARAM(param) \
1328         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1329
1330 #define OP_GEN_TYPE(type) \
1331         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1332
1333 #define OP_GEN_AGG_VECT(index) \
1334         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1335
1336 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1337 {
1338         u32 op_gen_command = 0;
1339         u32 comp_addr = BAR_CSTRORM_INTMEM +
1340                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1341         int ret = 0;
1342
1343         if (REG_RD(bp, comp_addr)) {
1344                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1345                 return 1;
1346         }
1347
1348         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1349         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1350         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1351         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1352
1353         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1354         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1355
1356         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1357                 BNX2X_ERR("FW final cleanup did not succeed\n");
1358                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1359                    (REG_RD(bp, comp_addr)));
1360                 bnx2x_panic();
1361                 return 1;
1362         }
1363         /* Zero completion for next FLR */
1364         REG_WR(bp, comp_addr, 0);
1365
1366         return ret;
1367 }
1368
1369 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1370 {
1371         u16 status;
1372
1373         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1374         return status & PCI_EXP_DEVSTA_TRPND;
1375 }
1376
1377 /* PF FLR specific routines
1378 */
1379 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1380 {
1381         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1382         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1383                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1384                         "CFC PF usage counter timed out",
1385                         poll_cnt))
1386                 return 1;
1387
1388         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1389         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1390                         DORQ_REG_PF_USAGE_CNT,
1391                         "DQ PF usage counter timed out",
1392                         poll_cnt))
1393                 return 1;
1394
1395         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1396         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1397                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1398                         "QM PF usage counter timed out",
1399                         poll_cnt))
1400                 return 1;
1401
1402         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1403         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1404                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1405                         "Timers VNIC usage counter timed out",
1406                         poll_cnt))
1407                 return 1;
1408         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1409                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1410                         "Timers NUM_SCANS usage counter timed out",
1411                         poll_cnt))
1412                 return 1;
1413
1414         /* Wait DMAE PF usage counter to zero */
1415         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1416                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1417                         "DMAE command register timed out",
1418                         poll_cnt))
1419                 return 1;
1420
1421         return 0;
1422 }
1423
1424 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1425 {
1426         u32 val;
1427
1428         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1429         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1430
1431         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1432         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1433
1434         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1435         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1436
1437         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1438         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1439
1440         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1441         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1442
1443         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1444         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1445
1446         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1447         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1448
1449         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1450         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1451            val);
1452 }
1453
1454 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1455 {
1456         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1457
1458         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1459
1460         /* Re-enable PF target read access */
1461         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1462
1463         /* Poll HW usage counters */
1464         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1465         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1466                 return -EBUSY;
1467
1468         /* Zero the igu 'trailing edge' and 'leading edge' */
1469
1470         /* Send the FW cleanup command */
1471         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1472                 return -EBUSY;
1473
1474         /* ATC cleanup */
1475
1476         /* Verify TX hw is flushed */
1477         bnx2x_tx_hw_flushed(bp, poll_cnt);
1478
1479         /* Wait 100ms (not adjusted according to platform) */
1480         msleep(100);
1481
1482         /* Verify no pending pci transactions */
1483         if (bnx2x_is_pcie_pending(bp->pdev))
1484                 BNX2X_ERR("PCIE Transactions still pending\n");
1485
1486         /* Debug */
1487         bnx2x_hw_enable_status(bp);
1488
1489         /*
1490          * Master enable - Due to WB DMAE writes performed before this
1491          * register is re-initialized as part of the regular function init
1492          */
1493         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1494
1495         return 0;
1496 }
1497
1498 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1499 {
1500         int port = BP_PORT(bp);
1501         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1502         u32 val = REG_RD(bp, addr);
1503         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1504         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1505         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1506
1507         if (msix) {
1508                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1509                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1510                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1511                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1512                 if (single_msix)
1513                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1514         } else if (msi) {
1515                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1516                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1517                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1518                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1519         } else {
1520                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1521                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1522                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1523                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1524
1525                 if (!CHIP_IS_E1(bp)) {
1526                         DP(NETIF_MSG_IFUP,
1527                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1528
1529                         REG_WR(bp, addr, val);
1530
1531                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1532                 }
1533         }
1534
1535         if (CHIP_IS_E1(bp))
1536                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1537
1538         DP(NETIF_MSG_IFUP,
1539            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1540            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1541
1542         REG_WR(bp, addr, val);
1543         /*
1544          * Ensure that HC_CONFIG is written before leading/trailing edge config
1545          */
1546         mmiowb();
1547         barrier();
1548
1549         if (!CHIP_IS_E1(bp)) {
1550                 /* init leading/trailing edge */
1551                 if (IS_MF(bp)) {
1552                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1553                         if (bp->port.pmf)
1554                                 /* enable nig and gpio3 attention */
1555                                 val |= 0x1100;
1556                 } else
1557                         val = 0xffff;
1558
1559                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1560                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1561         }
1562
1563         /* Make sure that interrupts are indeed enabled from here on */
1564         mmiowb();
1565 }
1566
1567 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1568 {
1569         u32 val;
1570         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1571         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1572         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1573
1574         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1575
1576         if (msix) {
1577                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1578                          IGU_PF_CONF_SINGLE_ISR_EN);
1579                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1580                         IGU_PF_CONF_ATTN_BIT_EN);
1581
1582                 if (single_msix)
1583                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1584         } else if (msi) {
1585                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1586                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1587                         IGU_PF_CONF_ATTN_BIT_EN |
1588                         IGU_PF_CONF_SINGLE_ISR_EN);
1589         } else {
1590                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1591                 val |= (IGU_PF_CONF_INT_LINE_EN |
1592                         IGU_PF_CONF_ATTN_BIT_EN |
1593                         IGU_PF_CONF_SINGLE_ISR_EN);
1594         }
1595
1596         /* Clean previous status - need to configure igu prior to ack*/
1597         if ((!msix) || single_msix) {
1598                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1599                 bnx2x_ack_int(bp);
1600         }
1601
1602         val |= IGU_PF_CONF_FUNC_EN;
1603
1604         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1605            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1606
1607         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1608
1609         if (val & IGU_PF_CONF_INT_LINE_EN)
1610                 pci_intx(bp->pdev, true);
1611
1612         barrier();
1613
1614         /* init leading/trailing edge */
1615         if (IS_MF(bp)) {
1616                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1617                 if (bp->port.pmf)
1618                         /* enable nig and gpio3 attention */
1619                         val |= 0x1100;
1620         } else
1621                 val = 0xffff;
1622
1623         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1624         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1625
1626         /* Make sure that interrupts are indeed enabled from here on */
1627         mmiowb();
1628 }
1629
1630 void bnx2x_int_enable(struct bnx2x *bp)
1631 {
1632         if (bp->common.int_block == INT_BLOCK_HC)
1633                 bnx2x_hc_int_enable(bp);
1634         else
1635                 bnx2x_igu_int_enable(bp);
1636 }
1637
1638 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1639 {
1640         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1641         int i, offset;
1642
1643         if (disable_hw)
1644                 /* prevent the HW from sending interrupts */
1645                 bnx2x_int_disable(bp);
1646
1647         /* make sure all ISRs are done */
1648         if (msix) {
1649                 synchronize_irq(bp->msix_table[0].vector);
1650                 offset = 1;
1651                 if (CNIC_SUPPORT(bp))
1652                         offset++;
1653                 for_each_eth_queue(bp, i)
1654                         synchronize_irq(bp->msix_table[offset++].vector);
1655         } else
1656                 synchronize_irq(bp->pdev->irq);
1657
1658         /* make sure sp_task is not running */
1659         cancel_delayed_work(&bp->sp_task);
1660         cancel_delayed_work(&bp->period_task);
1661         flush_workqueue(bnx2x_wq);
1662 }
1663
1664 /* fast path */
1665
1666 /*
1667  * General service functions
1668  */
1669
1670 /* Return true if succeeded to acquire the lock */
1671 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1672 {
1673         u32 lock_status;
1674         u32 resource_bit = (1 << resource);
1675         int func = BP_FUNC(bp);
1676         u32 hw_lock_control_reg;
1677
1678         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1679            "Trying to take a lock on resource %d\n", resource);
1680
1681         /* Validating that the resource is within range */
1682         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1683                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1684                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1685                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1686                 return false;
1687         }
1688
1689         if (func <= 5)
1690                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1691         else
1692                 hw_lock_control_reg =
1693                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1694
1695         /* Try to acquire the lock */
1696         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1697         lock_status = REG_RD(bp, hw_lock_control_reg);
1698         if (lock_status & resource_bit)
1699                 return true;
1700
1701         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1702            "Failed to get a lock on resource %d\n", resource);
1703         return false;
1704 }
1705
1706 /**
1707  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1708  *
1709  * @bp: driver handle
1710  *
1711  * Returns the recovery leader resource id according to the engine this function
1712  * belongs to. Currently only only 2 engines is supported.
1713  */
1714 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1715 {
1716         if (BP_PATH(bp))
1717                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1718         else
1719                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1720 }
1721
1722 /**
1723  * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1724  *
1725  * @bp: driver handle
1726  *
1727  * Tries to acquire a leader lock for current engine.
1728  */
1729 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1730 {
1731         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1732 }
1733
1734 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1735
1736 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1737 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1738 {
1739         /* Set the interrupt occurred bit for the sp-task to recognize it
1740          * must ack the interrupt and transition according to the IGU
1741          * state machine.
1742          */
1743         atomic_set(&bp->interrupt_occurred, 1);
1744
1745         /* The sp_task must execute only after this bit
1746          * is set, otherwise we will get out of sync and miss all
1747          * further interrupts. Hence, the barrier.
1748          */
1749         smp_wmb();
1750
1751         /* schedule sp_task to workqueue */
1752         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1753 }
1754
1755 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1756 {
1757         struct bnx2x *bp = fp->bp;
1758         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1759         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1760         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1761         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1762
1763         DP(BNX2X_MSG_SP,
1764            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1765            fp->index, cid, command, bp->state,
1766            rr_cqe->ramrod_cqe.ramrod_type);
1767
1768         /* If cid is within VF range, replace the slowpath object with the
1769          * one corresponding to this VF
1770          */
1771         if (cid >= BNX2X_FIRST_VF_CID  &&
1772             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1773                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1774
1775         switch (command) {
1776         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1777                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1778                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1779                 break;
1780
1781         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1782                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1783                 drv_cmd = BNX2X_Q_CMD_SETUP;
1784                 break;
1785
1786         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1787                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1788                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1789                 break;
1790
1791         case (RAMROD_CMD_ID_ETH_HALT):
1792                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1793                 drv_cmd = BNX2X_Q_CMD_HALT;
1794                 break;
1795
1796         case (RAMROD_CMD_ID_ETH_TERMINATE):
1797                 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1798                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1799                 break;
1800
1801         case (RAMROD_CMD_ID_ETH_EMPTY):
1802                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1803                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1804                 break;
1805
1806         default:
1807                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1808                           command, fp->index);
1809                 return;
1810         }
1811
1812         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1813             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1814                 /* q_obj->complete_cmd() failure means that this was
1815                  * an unexpected completion.
1816                  *
1817                  * In this case we don't want to increase the bp->spq_left
1818                  * because apparently we haven't sent this command the first
1819                  * place.
1820                  */
1821 #ifdef BNX2X_STOP_ON_ERROR
1822                 bnx2x_panic();
1823 #else
1824                 return;
1825 #endif
1826         /* SRIOV: reschedule any 'in_progress' operations */
1827         bnx2x_iov_sp_event(bp, cid, true);
1828
1829         smp_mb__before_atomic_inc();
1830         atomic_inc(&bp->cq_spq_left);
1831         /* push the change in bp->spq_left and towards the memory */
1832         smp_mb__after_atomic_inc();
1833
1834         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1835
1836         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1837             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1838                 /* if Q update ramrod is completed for last Q in AFEX vif set
1839                  * flow, then ACK MCP at the end
1840                  *
1841                  * mark pending ACK to MCP bit.
1842                  * prevent case that both bits are cleared.
1843                  * At the end of load/unload driver checks that
1844                  * sp_state is cleared, and this order prevents
1845                  * races
1846                  */
1847                 smp_mb__before_clear_bit();
1848                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1849                 wmb();
1850                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1851                 smp_mb__after_clear_bit();
1852
1853                 /* schedule the sp task as mcp ack is required */
1854                 bnx2x_schedule_sp_task(bp);
1855         }
1856
1857         return;
1858 }
1859
1860 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1861 {
1862         struct bnx2x *bp = netdev_priv(dev_instance);
1863         u16 status = bnx2x_ack_int(bp);
1864         u16 mask;
1865         int i;
1866         u8 cos;
1867
1868         /* Return here if interrupt is shared and it's not for us */
1869         if (unlikely(status == 0)) {
1870                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1871                 return IRQ_NONE;
1872         }
1873         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1874
1875 #ifdef BNX2X_STOP_ON_ERROR
1876         if (unlikely(bp->panic))
1877                 return IRQ_HANDLED;
1878 #endif
1879
1880         for_each_eth_queue(bp, i) {
1881                 struct bnx2x_fastpath *fp = &bp->fp[i];
1882
1883                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1884                 if (status & mask) {
1885                         /* Handle Rx or Tx according to SB id */
1886                         for_each_cos_in_tx_queue(fp, cos)
1887                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1888                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1889                         napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1890                         status &= ~mask;
1891                 }
1892         }
1893
1894         if (CNIC_SUPPORT(bp)) {
1895                 mask = 0x2;
1896                 if (status & (mask | 0x1)) {
1897                         struct cnic_ops *c_ops = NULL;
1898
1899                         rcu_read_lock();
1900                         c_ops = rcu_dereference(bp->cnic_ops);
1901                         if (c_ops && (bp->cnic_eth_dev.drv_state &
1902                                       CNIC_DRV_STATE_HANDLES_IRQ))
1903                                 c_ops->cnic_handler(bp->cnic_data, NULL);
1904                         rcu_read_unlock();
1905
1906                         status &= ~mask;
1907                 }
1908         }
1909
1910         if (unlikely(status & 0x1)) {
1911
1912                 /* schedule sp task to perform default status block work, ack
1913                  * attentions and enable interrupts.
1914                  */
1915                 bnx2x_schedule_sp_task(bp);
1916
1917                 status &= ~0x1;
1918                 if (!status)
1919                         return IRQ_HANDLED;
1920         }
1921
1922         if (unlikely(status))
1923                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1924                    status);
1925
1926         return IRQ_HANDLED;
1927 }
1928
1929 /* Link */
1930
1931 /*
1932  * General service functions
1933  */
1934
1935 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1936 {
1937         u32 lock_status;
1938         u32 resource_bit = (1 << resource);
1939         int func = BP_FUNC(bp);
1940         u32 hw_lock_control_reg;
1941         int cnt;
1942
1943         /* Validating that the resource is within range */
1944         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1945                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1946                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1947                 return -EINVAL;
1948         }
1949
1950         if (func <= 5) {
1951                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1952         } else {
1953                 hw_lock_control_reg =
1954                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1955         }
1956
1957         /* Validating that the resource is not already taken */
1958         lock_status = REG_RD(bp, hw_lock_control_reg);
1959         if (lock_status & resource_bit) {
1960                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
1961                    lock_status, resource_bit);
1962                 return -EEXIST;
1963         }
1964
1965         /* Try for 5 second every 5ms */
1966         for (cnt = 0; cnt < 1000; cnt++) {
1967                 /* Try to acquire the lock */
1968                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1969                 lock_status = REG_RD(bp, hw_lock_control_reg);
1970                 if (lock_status & resource_bit)
1971                         return 0;
1972
1973                 usleep_range(5000, 10000);
1974         }
1975         BNX2X_ERR("Timeout\n");
1976         return -EAGAIN;
1977 }
1978
1979 int bnx2x_release_leader_lock(struct bnx2x *bp)
1980 {
1981         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1982 }
1983
1984 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1985 {
1986         u32 lock_status;
1987         u32 resource_bit = (1 << resource);
1988         int func = BP_FUNC(bp);
1989         u32 hw_lock_control_reg;
1990
1991         /* Validating that the resource is within range */
1992         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1993                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1994                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1995                 return -EINVAL;
1996         }
1997
1998         if (func <= 5) {
1999                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2000         } else {
2001                 hw_lock_control_reg =
2002                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2003         }
2004
2005         /* Validating that the resource is currently taken */
2006         lock_status = REG_RD(bp, hw_lock_control_reg);
2007         if (!(lock_status & resource_bit)) {
2008                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2009                           lock_status, resource_bit);
2010                 return -EFAULT;
2011         }
2012
2013         REG_WR(bp, hw_lock_control_reg, resource_bit);
2014         return 0;
2015 }
2016
2017 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2018 {
2019         /* The GPIO should be swapped if swap register is set and active */
2020         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2021                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2022         int gpio_shift = gpio_num +
2023                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2024         u32 gpio_mask = (1 << gpio_shift);
2025         u32 gpio_reg;
2026         int value;
2027
2028         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2029                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2030                 return -EINVAL;
2031         }
2032
2033         /* read GPIO value */
2034         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2035
2036         /* get the requested pin value */
2037         if ((gpio_reg & gpio_mask) == gpio_mask)
2038                 value = 1;
2039         else
2040                 value = 0;
2041
2042         DP(NETIF_MSG_LINK, "pin %d  value 0x%x\n", gpio_num, value);
2043
2044         return value;
2045 }
2046
2047 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2048 {
2049         /* The GPIO should be swapped if swap register is set and active */
2050         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2051                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2052         int gpio_shift = gpio_num +
2053                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2054         u32 gpio_mask = (1 << gpio_shift);
2055         u32 gpio_reg;
2056
2057         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2058                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2059                 return -EINVAL;
2060         }
2061
2062         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2063         /* read GPIO and mask except the float bits */
2064         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2065
2066         switch (mode) {
2067         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2068                 DP(NETIF_MSG_LINK,
2069                    "Set GPIO %d (shift %d) -> output low\n",
2070                    gpio_num, gpio_shift);
2071                 /* clear FLOAT and set CLR */
2072                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2073                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2074                 break;
2075
2076         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2077                 DP(NETIF_MSG_LINK,
2078                    "Set GPIO %d (shift %d) -> output high\n",
2079                    gpio_num, gpio_shift);
2080                 /* clear FLOAT and set SET */
2081                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2082                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2083                 break;
2084
2085         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2086                 DP(NETIF_MSG_LINK,
2087                    "Set GPIO %d (shift %d) -> input\n",
2088                    gpio_num, gpio_shift);
2089                 /* set FLOAT */
2090                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2091                 break;
2092
2093         default:
2094                 break;
2095         }
2096
2097         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2098         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2099
2100         return 0;
2101 }
2102
2103 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2104 {
2105         u32 gpio_reg = 0;
2106         int rc = 0;
2107
2108         /* Any port swapping should be handled by caller. */
2109
2110         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2111         /* read GPIO and mask except the float bits */
2112         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2113         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2114         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2115         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2116
2117         switch (mode) {
2118         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2119                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2120                 /* set CLR */
2121                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2122                 break;
2123
2124         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2125                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2126                 /* set SET */
2127                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2128                 break;
2129
2130         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2131                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2132                 /* set FLOAT */
2133                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2134                 break;
2135
2136         default:
2137                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2138                 rc = -EINVAL;
2139                 break;
2140         }
2141
2142         if (rc == 0)
2143                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2144
2145         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2146
2147         return rc;
2148 }
2149
2150 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2151 {
2152         /* The GPIO should be swapped if swap register is set and active */
2153         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2154                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2155         int gpio_shift = gpio_num +
2156                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2157         u32 gpio_mask = (1 << gpio_shift);
2158         u32 gpio_reg;
2159
2160         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2161                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2162                 return -EINVAL;
2163         }
2164
2165         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2166         /* read GPIO int */
2167         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2168
2169         switch (mode) {
2170         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2171                 DP(NETIF_MSG_LINK,
2172                    "Clear GPIO INT %d (shift %d) -> output low\n",
2173                    gpio_num, gpio_shift);
2174                 /* clear SET and set CLR */
2175                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2176                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2177                 break;
2178
2179         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2180                 DP(NETIF_MSG_LINK,
2181                    "Set GPIO INT %d (shift %d) -> output high\n",
2182                    gpio_num, gpio_shift);
2183                 /* clear CLR and set SET */
2184                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2185                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2186                 break;
2187
2188         default:
2189                 break;
2190         }
2191
2192         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2193         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2194
2195         return 0;
2196 }
2197
2198 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2199 {
2200         u32 spio_reg;
2201
2202         /* Only 2 SPIOs are configurable */
2203         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2204                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2205                 return -EINVAL;
2206         }
2207
2208         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2209         /* read SPIO and mask except the float bits */
2210         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2211
2212         switch (mode) {
2213         case MISC_SPIO_OUTPUT_LOW:
2214                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2215                 /* clear FLOAT and set CLR */
2216                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2217                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2218                 break;
2219
2220         case MISC_SPIO_OUTPUT_HIGH:
2221                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2222                 /* clear FLOAT and set SET */
2223                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2224                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2225                 break;
2226
2227         case MISC_SPIO_INPUT_HI_Z:
2228                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2229                 /* set FLOAT */
2230                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2231                 break;
2232
2233         default:
2234                 break;
2235         }
2236
2237         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2238         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2239
2240         return 0;
2241 }
2242
2243 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2244 {
2245         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2246         switch (bp->link_vars.ieee_fc &
2247                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2248         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2249                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2250                                                    ADVERTISED_Pause);
2251                 break;
2252
2253         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2254                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2255                                                   ADVERTISED_Pause);
2256                 break;
2257
2258         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2259                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2260                 break;
2261
2262         default:
2263                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2264                                                    ADVERTISED_Pause);
2265                 break;
2266         }
2267 }
2268
2269 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2270 {
2271         /* Initialize link parameters structure variables
2272          * It is recommended to turn off RX FC for jumbo frames
2273          *  for better performance
2274          */
2275         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2276                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2277         else
2278                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2279 }
2280
2281 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2282 {
2283         u32 pause_enabled = 0;
2284
2285         if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2286                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2287                         pause_enabled = 1;
2288
2289                 REG_WR(bp, BAR_USTRORM_INTMEM +
2290                            USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2291                        pause_enabled);
2292         }
2293
2294         DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2295            pause_enabled ? "enabled" : "disabled");
2296 }
2297
2298 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2299 {
2300         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2301         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2302
2303         if (!BP_NOMCP(bp)) {
2304                 bnx2x_set_requested_fc(bp);
2305                 bnx2x_acquire_phy_lock(bp);
2306
2307                 if (load_mode == LOAD_DIAG) {
2308                         struct link_params *lp = &bp->link_params;
2309                         lp->loopback_mode = LOOPBACK_XGXS;
2310                         /* do PHY loopback at 10G speed, if possible */
2311                         if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2312                                 if (lp->speed_cap_mask[cfx_idx] &
2313                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2314                                         lp->req_line_speed[cfx_idx] =
2315                                         SPEED_10000;
2316                                 else
2317                                         lp->req_line_speed[cfx_idx] =
2318                                         SPEED_1000;
2319                         }
2320                 }
2321
2322                 if (load_mode == LOAD_LOOPBACK_EXT) {
2323                         struct link_params *lp = &bp->link_params;
2324                         lp->loopback_mode = LOOPBACK_EXT;
2325                 }
2326
2327                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2328
2329                 bnx2x_release_phy_lock(bp);
2330
2331                 bnx2x_init_dropless_fc(bp);
2332
2333                 bnx2x_calc_fc_adv(bp);
2334
2335                 if (bp->link_vars.link_up) {
2336                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2337                         bnx2x_link_report(bp);
2338                 }
2339                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2340                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2341                 return rc;
2342         }
2343         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2344         return -EINVAL;
2345 }
2346
2347 void bnx2x_link_set(struct bnx2x *bp)
2348 {
2349         if (!BP_NOMCP(bp)) {
2350                 bnx2x_acquire_phy_lock(bp);
2351                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2352                 bnx2x_release_phy_lock(bp);
2353
2354                 bnx2x_init_dropless_fc(bp);
2355
2356                 bnx2x_calc_fc_adv(bp);
2357         } else
2358                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2359 }
2360
2361 static void bnx2x__link_reset(struct bnx2x *bp)
2362 {
2363         if (!BP_NOMCP(bp)) {
2364                 bnx2x_acquire_phy_lock(bp);
2365                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2366                 bnx2x_release_phy_lock(bp);
2367         } else
2368                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2369 }
2370
2371 void bnx2x_force_link_reset(struct bnx2x *bp)
2372 {
2373         bnx2x_acquire_phy_lock(bp);
2374         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2375         bnx2x_release_phy_lock(bp);
2376 }
2377
2378 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2379 {
2380         u8 rc = 0;
2381
2382         if (!BP_NOMCP(bp)) {
2383                 bnx2x_acquire_phy_lock(bp);
2384                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2385                                      is_serdes);
2386                 bnx2x_release_phy_lock(bp);
2387         } else
2388                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2389
2390         return rc;
2391 }
2392
2393 /* Calculates the sum of vn_min_rates.
2394    It's needed for further normalizing of the min_rates.
2395    Returns:
2396      sum of vn_min_rates.
2397        or
2398      0 - if all the min_rates are 0.
2399      In the later case fairness algorithm should be deactivated.
2400      If not all min_rates are zero then those that are zeroes will be set to 1.
2401  */
2402 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2403                                       struct cmng_init_input *input)
2404 {
2405         int all_zero = 1;
2406         int vn;
2407
2408         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2409                 u32 vn_cfg = bp->mf_config[vn];
2410                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2411                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2412
2413                 /* Skip hidden vns */
2414                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2415                         vn_min_rate = 0;
2416                 /* If min rate is zero - set it to 1 */
2417                 else if (!vn_min_rate)
2418                         vn_min_rate = DEF_MIN_RATE;
2419                 else
2420                         all_zero = 0;
2421
2422                 input->vnic_min_rate[vn] = vn_min_rate;
2423         }
2424
2425         /* if ETS or all min rates are zeros - disable fairness */
2426         if (BNX2X_IS_ETS_ENABLED(bp)) {
2427                 input->flags.cmng_enables &=
2428                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2429                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2430         } else if (all_zero) {
2431                 input->flags.cmng_enables &=
2432                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2433                 DP(NETIF_MSG_IFUP,
2434                    "All MIN values are zeroes fairness will be disabled\n");
2435         } else
2436                 input->flags.cmng_enables |=
2437                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2438 }
2439
2440 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2441                                     struct cmng_init_input *input)
2442 {
2443         u16 vn_max_rate;
2444         u32 vn_cfg = bp->mf_config[vn];
2445
2446         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2447                 vn_max_rate = 0;
2448         else {
2449                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2450
2451                 if (IS_MF_SI(bp)) {
2452                         /* maxCfg in percents of linkspeed */
2453                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2454                 } else /* SD modes */
2455                         /* maxCfg is absolute in 100Mb units */
2456                         vn_max_rate = maxCfg * 100;
2457         }
2458
2459         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2460
2461         input->vnic_max_rate[vn] = vn_max_rate;
2462 }
2463
2464 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2465 {
2466         if (CHIP_REV_IS_SLOW(bp))
2467                 return CMNG_FNS_NONE;
2468         if (IS_MF(bp))
2469                 return CMNG_FNS_MINMAX;
2470
2471         return CMNG_FNS_NONE;
2472 }
2473
2474 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2475 {
2476         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2477
2478         if (BP_NOMCP(bp))
2479                 return; /* what should be the default value in this case */
2480
2481         /* For 2 port configuration the absolute function number formula
2482          * is:
2483          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2484          *
2485          *      and there are 4 functions per port
2486          *
2487          * For 4 port configuration it is
2488          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2489          *
2490          *      and there are 2 functions per port
2491          */
2492         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2493                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2494
2495                 if (func >= E1H_FUNC_MAX)
2496                         break;
2497
2498                 bp->mf_config[vn] =
2499                         MF_CFG_RD(bp, func_mf_config[func].config);
2500         }
2501         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2502                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2503                 bp->flags |= MF_FUNC_DIS;
2504         } else {
2505                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2506                 bp->flags &= ~MF_FUNC_DIS;
2507         }
2508 }
2509
2510 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2511 {
2512         struct cmng_init_input input;
2513         memset(&input, 0, sizeof(struct cmng_init_input));
2514
2515         input.port_rate = bp->link_vars.line_speed;
2516
2517         if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2518                 int vn;
2519
2520                 /* read mf conf from shmem */
2521                 if (read_cfg)
2522                         bnx2x_read_mf_cfg(bp);
2523
2524                 /* vn_weight_sum and enable fairness if not 0 */
2525                 bnx2x_calc_vn_min(bp, &input);
2526
2527                 /* calculate and set min-max rate for each vn */
2528                 if (bp->port.pmf)
2529                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2530                                 bnx2x_calc_vn_max(bp, vn, &input);
2531
2532                 /* always enable rate shaping and fairness */
2533                 input.flags.cmng_enables |=
2534                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2535
2536                 bnx2x_init_cmng(&input, &bp->cmng);
2537                 return;
2538         }
2539
2540         /* rate shaping and fairness are disabled */
2541         DP(NETIF_MSG_IFUP,
2542            "rate shaping and fairness are disabled\n");
2543 }
2544
2545 static void storm_memset_cmng(struct bnx2x *bp,
2546                               struct cmng_init *cmng,
2547                               u8 port)
2548 {
2549         int vn;
2550         size_t size = sizeof(struct cmng_struct_per_port);
2551
2552         u32 addr = BAR_XSTRORM_INTMEM +
2553                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2554
2555         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2556
2557         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2558                 int func = func_by_vn(bp, vn);
2559
2560                 addr = BAR_XSTRORM_INTMEM +
2561                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2562                 size = sizeof(struct rate_shaping_vars_per_vn);
2563                 __storm_memset_struct(bp, addr, size,
2564                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2565
2566                 addr = BAR_XSTRORM_INTMEM +
2567                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2568                 size = sizeof(struct fairness_vars_per_vn);
2569                 __storm_memset_struct(bp, addr, size,
2570                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2571         }
2572 }
2573
2574 /* init cmng mode in HW according to local configuration */
2575 void bnx2x_set_local_cmng(struct bnx2x *bp)
2576 {
2577         int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2578
2579         if (cmng_fns != CMNG_FNS_NONE) {
2580                 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2581                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2582         } else {
2583                 /* rate shaping and fairness are disabled */
2584                 DP(NETIF_MSG_IFUP,
2585                    "single function mode without fairness\n");
2586         }
2587 }
2588
2589 /* This function is called upon link interrupt */
2590 static void bnx2x_link_attn(struct bnx2x *bp)
2591 {
2592         /* Make sure that we are synced with the current statistics */
2593         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2594
2595         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2596
2597         bnx2x_init_dropless_fc(bp);
2598
2599         if (bp->link_vars.link_up) {
2600
2601                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2602                         struct host_port_stats *pstats;
2603
2604                         pstats = bnx2x_sp(bp, port_stats);
2605                         /* reset old mac stats */
2606                         memset(&(pstats->mac_stx[0]), 0,
2607                                sizeof(struct mac_stx));
2608                 }
2609                 if (bp->state == BNX2X_STATE_OPEN)
2610                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2611         }
2612
2613         if (bp->link_vars.link_up && bp->link_vars.line_speed)
2614                 bnx2x_set_local_cmng(bp);
2615
2616         __bnx2x_link_report(bp);
2617
2618         if (IS_MF(bp))
2619                 bnx2x_link_sync_notify(bp);
2620 }
2621
2622 void bnx2x__link_status_update(struct bnx2x *bp)
2623 {
2624         if (bp->state != BNX2X_STATE_OPEN)
2625                 return;
2626
2627         /* read updated dcb configuration */
2628         if (IS_PF(bp)) {
2629                 bnx2x_dcbx_pmf_update(bp);
2630                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2631                 if (bp->link_vars.link_up)
2632                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2633                 else
2634                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2635                         /* indicate link status */
2636                 bnx2x_link_report(bp);
2637
2638         } else { /* VF */
2639                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2640                                           SUPPORTED_10baseT_Full |
2641                                           SUPPORTED_100baseT_Half |
2642                                           SUPPORTED_100baseT_Full |
2643                                           SUPPORTED_1000baseT_Full |
2644                                           SUPPORTED_2500baseX_Full |
2645                                           SUPPORTED_10000baseT_Full |
2646                                           SUPPORTED_TP |
2647                                           SUPPORTED_FIBRE |
2648                                           SUPPORTED_Autoneg |
2649                                           SUPPORTED_Pause |
2650                                           SUPPORTED_Asym_Pause);
2651                 bp->port.advertising[0] = bp->port.supported[0];
2652
2653                 bp->link_params.bp = bp;
2654                 bp->link_params.port = BP_PORT(bp);
2655                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2656                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2657                 bp->link_params.req_line_speed[0] = SPEED_10000;
2658                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2659                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2660                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2661                 bp->link_vars.line_speed = SPEED_10000;
2662                 bp->link_vars.link_status =
2663                         (LINK_STATUS_LINK_UP |
2664                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2665                 bp->link_vars.link_up = 1;
2666                 bp->link_vars.duplex = DUPLEX_FULL;
2667                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2668                 __bnx2x_link_report(bp);
2669                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2670         }
2671 }
2672
2673 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2674                                   u16 vlan_val, u8 allowed_prio)
2675 {
2676         struct bnx2x_func_state_params func_params = {NULL};
2677         struct bnx2x_func_afex_update_params *f_update_params =
2678                 &func_params.params.afex_update;
2679
2680         func_params.f_obj = &bp->func_obj;
2681         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2682
2683         /* no need to wait for RAMROD completion, so don't
2684          * set RAMROD_COMP_WAIT flag
2685          */
2686
2687         f_update_params->vif_id = vifid;
2688         f_update_params->afex_default_vlan = vlan_val;
2689         f_update_params->allowed_priorities = allowed_prio;
2690
2691         /* if ramrod can not be sent, response to MCP immediately */
2692         if (bnx2x_func_state_change(bp, &func_params) < 0)
2693                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2694
2695         return 0;
2696 }
2697
2698 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2699                                           u16 vif_index, u8 func_bit_map)
2700 {
2701         struct bnx2x_func_state_params func_params = {NULL};
2702         struct bnx2x_func_afex_viflists_params *update_params =
2703                 &func_params.params.afex_viflists;
2704         int rc;
2705         u32 drv_msg_code;
2706
2707         /* validate only LIST_SET and LIST_GET are received from switch */
2708         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2709                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2710                           cmd_type);
2711
2712         func_params.f_obj = &bp->func_obj;
2713         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2714
2715         /* set parameters according to cmd_type */
2716         update_params->afex_vif_list_command = cmd_type;
2717         update_params->vif_list_index = vif_index;
2718         update_params->func_bit_map =
2719                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2720         update_params->func_to_clear = 0;
2721         drv_msg_code =
2722                 (cmd_type == VIF_LIST_RULE_GET) ?
2723                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2724                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2725
2726         /* if ramrod can not be sent, respond to MCP immediately for
2727          * SET and GET requests (other are not triggered from MCP)
2728          */
2729         rc = bnx2x_func_state_change(bp, &func_params);
2730         if (rc < 0)
2731                 bnx2x_fw_command(bp, drv_msg_code, 0);
2732
2733         return 0;
2734 }
2735
2736 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2737 {
2738         struct afex_stats afex_stats;
2739         u32 func = BP_ABS_FUNC(bp);
2740         u32 mf_config;
2741         u16 vlan_val;
2742         u32 vlan_prio;
2743         u16 vif_id;
2744         u8 allowed_prio;
2745         u8 vlan_mode;
2746         u32 addr_to_write, vifid, addrs, stats_type, i;
2747
2748         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2749                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2750                 DP(BNX2X_MSG_MCP,
2751                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2752                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2753         }
2754
2755         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2756                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2757                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2758                 DP(BNX2X_MSG_MCP,
2759                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2760                    vifid, addrs);
2761                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2762                                                addrs);
2763         }
2764
2765         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2766                 addr_to_write = SHMEM2_RD(bp,
2767                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2768                 stats_type = SHMEM2_RD(bp,
2769                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2770
2771                 DP(BNX2X_MSG_MCP,
2772                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2773                    addr_to_write);
2774
2775                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2776
2777                 /* write response to scratchpad, for MCP */
2778                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2779                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2780                                *(((u32 *)(&afex_stats))+i));
2781
2782                 /* send ack message to MCP */
2783                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2784         }
2785
2786         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2787                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2788                 bp->mf_config[BP_VN(bp)] = mf_config;
2789                 DP(BNX2X_MSG_MCP,
2790                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2791                    mf_config);
2792
2793                 /* if VIF_SET is "enabled" */
2794                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2795                         /* set rate limit directly to internal RAM */
2796                         struct cmng_init_input cmng_input;
2797                         struct rate_shaping_vars_per_vn m_rs_vn;
2798                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2799                         u32 addr = BAR_XSTRORM_INTMEM +
2800                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2801
2802                         bp->mf_config[BP_VN(bp)] = mf_config;
2803
2804                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2805                         m_rs_vn.vn_counter.rate =
2806                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2807                         m_rs_vn.vn_counter.quota =
2808                                 (m_rs_vn.vn_counter.rate *
2809                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2810
2811                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2812
2813                         /* read relevant values from mf_cfg struct in shmem */
2814                         vif_id =
2815                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2816                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2817                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2818                         vlan_val =
2819                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2820                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2821                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2822                         vlan_prio = (mf_config &
2823                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2824                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2825                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2826                         vlan_mode =
2827                                 (MF_CFG_RD(bp,
2828                                            func_mf_config[func].afex_config) &
2829                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2830                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2831                         allowed_prio =
2832                                 (MF_CFG_RD(bp,
2833                                            func_mf_config[func].afex_config) &
2834                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2835                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2836
2837                         /* send ramrod to FW, return in case of failure */
2838                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2839                                                    allowed_prio))
2840                                 return;
2841
2842                         bp->afex_def_vlan_tag = vlan_val;
2843                         bp->afex_vlan_mode = vlan_mode;
2844                 } else {
2845                         /* notify link down because BP->flags is disabled */
2846                         bnx2x_link_report(bp);
2847
2848                         /* send INVALID VIF ramrod to FW */
2849                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2850
2851                         /* Reset the default afex VLAN */
2852                         bp->afex_def_vlan_tag = -1;
2853                 }
2854         }
2855 }
2856
2857 static void bnx2x_pmf_update(struct bnx2x *bp)
2858 {
2859         int port = BP_PORT(bp);
2860         u32 val;
2861
2862         bp->port.pmf = 1;
2863         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2864
2865         /*
2866          * We need the mb() to ensure the ordering between the writing to
2867          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2868          */
2869         smp_mb();
2870
2871         /* queue a periodic task */
2872         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2873
2874         bnx2x_dcbx_pmf_update(bp);
2875
2876         /* enable nig attention */
2877         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2878         if (bp->common.int_block == INT_BLOCK_HC) {
2879                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2880                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2881         } else if (!CHIP_IS_E1x(bp)) {
2882                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2883                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2884         }
2885
2886         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2887 }
2888
2889 /* end of Link */
2890
2891 /* slow path */
2892
2893 /*
2894  * General service functions
2895  */
2896
2897 /* send the MCP a request, block until there is a reply */
2898 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2899 {
2900         int mb_idx = BP_FW_MB_IDX(bp);
2901         u32 seq;
2902         u32 rc = 0;
2903         u32 cnt = 1;
2904         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2905
2906         mutex_lock(&bp->fw_mb_mutex);
2907         seq = ++bp->fw_seq;
2908         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2909         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2910
2911         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2912                         (command | seq), param);
2913
2914         do {
2915                 /* let the FW do it's magic ... */
2916                 msleep(delay);
2917
2918                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2919
2920                 /* Give the FW up to 5 second (500*10ms) */
2921         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2922
2923         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2924            cnt*delay, rc, seq);
2925
2926         /* is this a reply to our command? */
2927         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2928                 rc &= FW_MSG_CODE_MASK;
2929         else {
2930                 /* FW BUG! */
2931                 BNX2X_ERR("FW failed to respond!\n");
2932                 bnx2x_fw_dump(bp);
2933                 rc = 0;
2934         }
2935         mutex_unlock(&bp->fw_mb_mutex);
2936
2937         return rc;
2938 }
2939
2940 static void storm_memset_func_cfg(struct bnx2x *bp,
2941                                  struct tstorm_eth_function_common_config *tcfg,
2942                                  u16 abs_fid)
2943 {
2944         size_t size = sizeof(struct tstorm_eth_function_common_config);
2945
2946         u32 addr = BAR_TSTRORM_INTMEM +
2947                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2948
2949         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2950 }
2951
2952 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2953 {
2954         if (CHIP_IS_E1x(bp)) {
2955                 struct tstorm_eth_function_common_config tcfg = {0};
2956
2957                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2958         }
2959
2960         /* Enable the function in the FW */
2961         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2962         storm_memset_func_en(bp, p->func_id, 1);
2963
2964         /* spq */
2965         if (p->func_flgs & FUNC_FLG_SPQ) {
2966                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2967                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2968                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2969         }
2970 }
2971
2972 /**
2973  * bnx2x_get_common_flags - Return common flags
2974  *
2975  * @bp          device handle
2976  * @fp          queue handle
2977  * @zero_stats  TRUE if statistics zeroing is needed
2978  *
2979  * Return the flags that are common for the Tx-only and not normal connections.
2980  */
2981 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2982                                             struct bnx2x_fastpath *fp,
2983                                             bool zero_stats)
2984 {
2985         unsigned long flags = 0;
2986
2987         /* PF driver will always initialize the Queue to an ACTIVE state */
2988         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2989
2990         /* tx only connections collect statistics (on the same index as the
2991          * parent connection). The statistics are zeroed when the parent
2992          * connection is initialized.
2993          */
2994
2995         __set_bit(BNX2X_Q_FLG_STATS, &flags);
2996         if (zero_stats)
2997                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2998
2999         __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3000         __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3001
3002 #ifdef BNX2X_STOP_ON_ERROR
3003         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3004 #endif
3005
3006         return flags;
3007 }
3008
3009 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3010                                        struct bnx2x_fastpath *fp,
3011                                        bool leading)
3012 {
3013         unsigned long flags = 0;
3014
3015         /* calculate other queue flags */
3016         if (IS_MF_SD(bp))
3017                 __set_bit(BNX2X_Q_FLG_OV, &flags);
3018
3019         if (IS_FCOE_FP(fp)) {
3020                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3021                 /* For FCoE - force usage of default priority (for afex) */
3022                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3023         }
3024
3025         if (!fp->disable_tpa) {
3026                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3027                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3028                 if (fp->mode == TPA_MODE_GRO)
3029                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3030         }
3031
3032         if (leading) {
3033                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3034                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3035         }
3036
3037         /* Always set HW VLAN stripping */
3038         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3039
3040         /* configure silent vlan removal */
3041         if (IS_MF_AFEX(bp))
3042                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3043
3044         return flags | bnx2x_get_common_flags(bp, fp, true);
3045 }
3046
3047 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3048         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3049         u8 cos)
3050 {
3051         gen_init->stat_id = bnx2x_stats_id(fp);
3052         gen_init->spcl_id = fp->cl_id;
3053
3054         /* Always use mini-jumbo MTU for FCoE L2 ring */
3055         if (IS_FCOE_FP(fp))
3056                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3057         else
3058                 gen_init->mtu = bp->dev->mtu;
3059
3060         gen_init->cos = cos;
3061 }
3062
3063 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3064         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3065         struct bnx2x_rxq_setup_params *rxq_init)
3066 {
3067         u8 max_sge = 0;
3068         u16 sge_sz = 0;
3069         u16 tpa_agg_size = 0;
3070
3071         if (!fp->disable_tpa) {
3072                 pause->sge_th_lo = SGE_TH_LO(bp);
3073                 pause->sge_th_hi = SGE_TH_HI(bp);
3074
3075                 /* validate SGE ring has enough to cross high threshold */
3076                 WARN_ON(bp->dropless_fc &&
3077                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3078                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3079
3080                 tpa_agg_size = TPA_AGG_SIZE;
3081                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3082                         SGE_PAGE_SHIFT;
3083                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3084                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3085                 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3086         }
3087
3088         /* pause - not for e1 */
3089         if (!CHIP_IS_E1(bp)) {
3090                 pause->bd_th_lo = BD_TH_LO(bp);
3091                 pause->bd_th_hi = BD_TH_HI(bp);
3092
3093                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3094                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3095                 /*
3096                  * validate that rings have enough entries to cross
3097                  * high thresholds
3098                  */
3099                 WARN_ON(bp->dropless_fc &&
3100                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3101                                 bp->rx_ring_size);
3102                 WARN_ON(bp->dropless_fc &&
3103                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3104                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3105
3106                 pause->pri_map = 1;
3107         }
3108
3109         /* rxq setup */
3110         rxq_init->dscr_map = fp->rx_desc_mapping;
3111         rxq_init->sge_map = fp->rx_sge_mapping;
3112         rxq_init->rcq_map = fp->rx_comp_mapping;
3113         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3114
3115         /* This should be a maximum number of data bytes that may be
3116          * placed on the BD (not including paddings).
3117          */
3118         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3119                            BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3120
3121         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3122         rxq_init->tpa_agg_sz = tpa_agg_size;
3123         rxq_init->sge_buf_sz = sge_sz;
3124         rxq_init->max_sges_pkt = max_sge;
3125         rxq_init->rss_engine_id = BP_FUNC(bp);
3126         rxq_init->mcast_engine_id = BP_FUNC(bp);
3127
3128         /* Maximum number or simultaneous TPA aggregation for this Queue.
3129          *
3130          * For PF Clients it should be the maximum available number.
3131          * VF driver(s) may want to define it to a smaller value.
3132          */
3133         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3134
3135         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3136         rxq_init->fw_sb_id = fp->fw_sb_id;
3137
3138         if (IS_FCOE_FP(fp))
3139                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3140         else
3141                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3142         /* configure silent vlan removal
3143          * if multi function mode is afex, then mask default vlan
3144          */
3145         if (IS_MF_AFEX(bp)) {
3146                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3147                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3148         }
3149 }
3150
3151 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3152         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3153         u8 cos)
3154 {
3155         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3156         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3157         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3158         txq_init->fw_sb_id = fp->fw_sb_id;
3159
3160         /*
3161          * set the tss leading client id for TX classification ==
3162          * leading RSS client id
3163          */
3164         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3165
3166         if (IS_FCOE_FP(fp)) {
3167                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3168                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3169         }
3170 }
3171
3172 static void bnx2x_pf_init(struct bnx2x *bp)
3173 {
3174         struct bnx2x_func_init_params func_init = {0};
3175         struct event_ring_data eq_data = { {0} };
3176         u16 flags;
3177
3178         if (!CHIP_IS_E1x(bp)) {
3179                 /* reset IGU PF statistics: MSIX + ATTN */
3180                 /* PF */
3181                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3182                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3183                            (CHIP_MODE_IS_4_PORT(bp) ?
3184                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3185                 /* ATTN */
3186                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3187                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3188                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3189                            (CHIP_MODE_IS_4_PORT(bp) ?
3190                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3191         }
3192
3193         /* function setup flags */
3194         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3195
3196         /* This flag is relevant for E1x only.
3197          * E2 doesn't have a TPA configuration in a function level.
3198          */
3199         flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
3200
3201         func_init.func_flgs = flags;
3202         func_init.pf_id = BP_FUNC(bp);
3203         func_init.func_id = BP_FUNC(bp);
3204         func_init.spq_map = bp->spq_mapping;
3205         func_init.spq_prod = bp->spq_prod_idx;
3206
3207         bnx2x_func_init(bp, &func_init);
3208
3209         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3210
3211         /*
3212          * Congestion management values depend on the link rate
3213          * There is no active link so initial link rate is set to 10 Gbps.
3214          * When the link comes up The congestion management values are
3215          * re-calculated according to the actual link rate.
3216          */
3217         bp->link_vars.line_speed = SPEED_10000;
3218         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3219
3220         /* Only the PMF sets the HW */
3221         if (bp->port.pmf)
3222                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3223
3224         /* init Event Queue - PCI bus guarantees correct endianity*/
3225         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3226         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3227         eq_data.producer = bp->eq_prod;
3228         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3229         eq_data.sb_id = DEF_SB_ID;
3230         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3231 }
3232
3233 static void bnx2x_e1h_disable(struct bnx2x *bp)
3234 {
3235         int port = BP_PORT(bp);
3236
3237         bnx2x_tx_disable(bp);
3238
3239         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3240 }
3241
3242 static void bnx2x_e1h_enable(struct bnx2x *bp)
3243 {
3244         int port = BP_PORT(bp);
3245
3246         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3247
3248         /* Tx queue should be only re-enabled */
3249         netif_tx_wake_all_queues(bp->dev);
3250
3251         /*
3252          * Should not call netif_carrier_on since it will be called if the link
3253          * is up when checking for link state
3254          */
3255 }
3256
3257 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3258
3259 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3260 {
3261         struct eth_stats_info *ether_stat =
3262                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3263         struct bnx2x_vlan_mac_obj *mac_obj =
3264                 &bp->sp_objs->mac_obj;
3265         int i;
3266
3267         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3268                 ETH_STAT_INFO_VERSION_LEN);
3269
3270         /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3271          * mac_local field in ether_stat struct. The base address is offset by 2
3272          * bytes to account for the field being 8 bytes but a mac address is
3273          * only 6 bytes. Likewise, the stride for the get_n_elements function is
3274          * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3275          * allocated by the ether_stat struct, so the macs will land in their
3276          * proper positions.
3277          */
3278         for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3279                 memset(ether_stat->mac_local + i, 0,
3280                        sizeof(ether_stat->mac_local[0]));
3281         mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3282                                 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3283                                 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3284                                 ETH_ALEN);
3285         ether_stat->mtu_size = bp->dev->mtu;
3286         if (bp->dev->features & NETIF_F_RXCSUM)
3287                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3288         if (bp->dev->features & NETIF_F_TSO)
3289                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3290         ether_stat->feature_flags |= bp->common.boot_mode;
3291
3292         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3293
3294         ether_stat->txq_size = bp->tx_ring_size;
3295         ether_stat->rxq_size = bp->rx_ring_size;
3296 }
3297
3298 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3299 {
3300         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3301         struct fcoe_stats_info *fcoe_stat =
3302                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3303
3304         if (!CNIC_LOADED(bp))
3305                 return;
3306
3307         memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3308
3309         fcoe_stat->qos_priority =
3310                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3311
3312         /* insert FCoE stats from ramrod response */
3313         if (!NO_FCOE(bp)) {
3314                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3315                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3316                         tstorm_queue_statistics;
3317
3318                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3319                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3320                         xstorm_queue_statistics;
3321
3322                 struct fcoe_statistics_params *fw_fcoe_stat =
3323                         &bp->fw_stats_data->fcoe;
3324
3325                 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3326                           fcoe_stat->rx_bytes_lo,
3327                           fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3328
3329                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3330                           fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3331                           fcoe_stat->rx_bytes_lo,
3332                           fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3333
3334                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3335                           fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3336                           fcoe_stat->rx_bytes_lo,
3337                           fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3338
3339                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3340                           fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3341                           fcoe_stat->rx_bytes_lo,
3342                           fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3343
3344                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3345                           fcoe_stat->rx_frames_lo,
3346                           fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3347
3348                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3349                           fcoe_stat->rx_frames_lo,
3350                           fcoe_q_tstorm_stats->rcv_ucast_pkts);
3351
3352                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3353                           fcoe_stat->rx_frames_lo,
3354                           fcoe_q_tstorm_stats->rcv_bcast_pkts);
3355
3356                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3357                           fcoe_stat->rx_frames_lo,
3358                           fcoe_q_tstorm_stats->rcv_mcast_pkts);
3359
3360                 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3361                           fcoe_stat->tx_bytes_lo,
3362                           fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3363
3364                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3365                           fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3366                           fcoe_stat->tx_bytes_lo,
3367                           fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3368
3369                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3370                           fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3371                           fcoe_stat->tx_bytes_lo,
3372                           fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3373
3374                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3375                           fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3376                           fcoe_stat->tx_bytes_lo,
3377                           fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3378
3379                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3380                           fcoe_stat->tx_frames_lo,
3381                           fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3382
3383                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3384                           fcoe_stat->tx_frames_lo,
3385                           fcoe_q_xstorm_stats->ucast_pkts_sent);
3386
3387                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3388                           fcoe_stat->tx_frames_lo,
3389                           fcoe_q_xstorm_stats->bcast_pkts_sent);
3390
3391                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3392                           fcoe_stat->tx_frames_lo,
3393                           fcoe_q_xstorm_stats->mcast_pkts_sent);
3394         }
3395
3396         /* ask L5 driver to add data to the struct */
3397         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3398 }
3399
3400 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3401 {
3402         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3403         struct iscsi_stats_info *iscsi_stat =
3404                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3405
3406         if (!CNIC_LOADED(bp))
3407                 return;
3408
3409         memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3410                ETH_ALEN);
3411
3412         iscsi_stat->qos_priority =
3413                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3414
3415         /* ask L5 driver to add data to the struct */
3416         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3417 }
3418
3419 /* called due to MCP event (on pmf):
3420  *      reread new bandwidth configuration
3421  *      configure FW
3422  *      notify others function about the change
3423  */
3424 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3425 {
3426         if (bp->link_vars.link_up) {
3427                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3428                 bnx2x_link_sync_notify(bp);
3429         }
3430         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3431 }
3432
3433 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3434 {
3435         bnx2x_config_mf_bw(bp);
3436         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3437 }
3438
3439 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3440 {
3441         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3442         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3443 }
3444
3445 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3446 {
3447         enum drv_info_opcode op_code;
3448         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3449
3450         /* if drv_info version supported by MFW doesn't match - send NACK */
3451         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3452                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3453                 return;
3454         }
3455
3456         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3457                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3458
3459         memset(&bp->slowpath->drv_info_to_mcp, 0,
3460                sizeof(union drv_info_to_mcp));
3461
3462         switch (op_code) {
3463         case ETH_STATS_OPCODE:
3464                 bnx2x_drv_info_ether_stat(bp);
3465                 break;
3466         case FCOE_STATS_OPCODE:
3467                 bnx2x_drv_info_fcoe_stat(bp);
3468                 break;
3469         case ISCSI_STATS_OPCODE:
3470                 bnx2x_drv_info_iscsi_stat(bp);
3471                 break;
3472         default:
3473                 /* if op code isn't supported - send NACK */
3474                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3475                 return;
3476         }
3477
3478         /* if we got drv_info attn from MFW then these fields are defined in
3479          * shmem2 for sure
3480          */
3481         SHMEM2_WR(bp, drv_info_host_addr_lo,
3482                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3483         SHMEM2_WR(bp, drv_info_host_addr_hi,
3484                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3485
3486         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3487 }
3488
3489 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3490 {
3491         DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3492
3493         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3494
3495                 /*
3496                  * This is the only place besides the function initialization
3497                  * where the bp->flags can change so it is done without any
3498                  * locks
3499                  */
3500                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3501                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3502                         bp->flags |= MF_FUNC_DIS;
3503
3504                         bnx2x_e1h_disable(bp);
3505                 } else {
3506                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3507                         bp->flags &= ~MF_FUNC_DIS;
3508
3509                         bnx2x_e1h_enable(bp);
3510                 }
3511                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3512         }
3513         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3514                 bnx2x_config_mf_bw(bp);
3515                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3516         }
3517
3518         /* Report results to MCP */
3519         if (dcc_event)
3520                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3521         else
3522                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3523 }
3524
3525 /* must be called under the spq lock */
3526 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3527 {
3528         struct eth_spe *next_spe = bp->spq_prod_bd;
3529
3530         if (bp->spq_prod_bd == bp->spq_last_bd) {
3531                 bp->spq_prod_bd = bp->spq;
3532                 bp->spq_prod_idx = 0;
3533                 DP(BNX2X_MSG_SP, "end of spq\n");
3534         } else {
3535                 bp->spq_prod_bd++;
3536                 bp->spq_prod_idx++;
3537         }
3538         return next_spe;
3539 }
3540
3541 /* must be called under the spq lock */
3542 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3543 {
3544         int func = BP_FUNC(bp);
3545
3546         /*
3547          * Make sure that BD data is updated before writing the producer:
3548          * BD data is written to the memory, the producer is read from the
3549          * memory, thus we need a full memory barrier to ensure the ordering.
3550          */
3551         mb();
3552
3553         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3554                  bp->spq_prod_idx);
3555         mmiowb();
3556 }
3557
3558 /**
3559  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3560  *
3561  * @cmd:        command to check
3562  * @cmd_type:   command type
3563  */
3564 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3565 {
3566         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3567             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3568             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3569             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3570             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3571             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3572             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3573                 return true;
3574         else
3575                 return false;
3576 }
3577
3578 /**
3579  * bnx2x_sp_post - place a single command on an SP ring
3580  *
3581  * @bp:         driver handle
3582  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3583  * @cid:        SW CID the command is related to
3584  * @data_hi:    command private data address (high 32 bits)
3585  * @data_lo:    command private data address (low 32 bits)
3586  * @cmd_type:   command type (e.g. NONE, ETH)
3587  *
3588  * SP data is handled as if it's always an address pair, thus data fields are
3589  * not swapped to little endian in upper functions. Instead this function swaps
3590  * data as if it's two u32 fields.
3591  */
3592 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3593                   u32 data_hi, u32 data_lo, int cmd_type)
3594 {
3595         struct eth_spe *spe;
3596         u16 type;
3597         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3598
3599 #ifdef BNX2X_STOP_ON_ERROR
3600         if (unlikely(bp->panic)) {
3601                 BNX2X_ERR("Can't post SP when there is panic\n");
3602                 return -EIO;
3603         }
3604 #endif
3605
3606         spin_lock_bh(&bp->spq_lock);
3607
3608         if (common) {
3609                 if (!atomic_read(&bp->eq_spq_left)) {
3610                         BNX2X_ERR("BUG! EQ ring full!\n");
3611                         spin_unlock_bh(&bp->spq_lock);
3612                         bnx2x_panic();
3613                         return -EBUSY;
3614                 }
3615         } else if (!atomic_read(&bp->cq_spq_left)) {
3616                         BNX2X_ERR("BUG! SPQ ring full!\n");
3617                         spin_unlock_bh(&bp->spq_lock);
3618                         bnx2x_panic();
3619                         return -EBUSY;
3620         }
3621
3622         spe = bnx2x_sp_get_next(bp);
3623
3624         /* CID needs port number to be encoded int it */
3625         spe->hdr.conn_and_cmd_data =
3626                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3627                                     HW_CID(bp, cid));
3628
3629         type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3630
3631         type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3632                  SPE_HDR_FUNCTION_ID);
3633
3634         spe->hdr.type = cpu_to_le16(type);
3635
3636         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3637         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3638
3639         /*
3640          * It's ok if the actual decrement is issued towards the memory
3641          * somewhere between the spin_lock and spin_unlock. Thus no
3642          * more explicit memory barrier is needed.
3643          */
3644         if (common)
3645                 atomic_dec(&bp->eq_spq_left);
3646         else
3647                 atomic_dec(&bp->cq_spq_left);
3648
3649         DP(BNX2X_MSG_SP,
3650            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3651            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3652            (u32)(U64_LO(bp->spq_mapping) +
3653            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3654            HW_CID(bp, cid), data_hi, data_lo, type,
3655            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3656
3657         bnx2x_sp_prod_update(bp);
3658         spin_unlock_bh(&bp->spq_lock);
3659         return 0;
3660 }
3661
3662 /* acquire split MCP access lock register */
3663 static int bnx2x_acquire_alr(struct bnx2x *bp)
3664 {
3665         u32 j, val;
3666         int rc = 0;
3667
3668         might_sleep();
3669         for (j = 0; j < 1000; j++) {
3670                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3671                 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3672                 if (val & MCPR_ACCESS_LOCK_LOCK)
3673                         break;
3674
3675                 usleep_range(5000, 10000);
3676         }
3677         if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3678                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3679                 rc = -EBUSY;
3680         }
3681
3682         return rc;
3683 }
3684
3685 /* release split MCP access lock register */
3686 static void bnx2x_release_alr(struct bnx2x *bp)
3687 {
3688         REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3689 }
3690
3691 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3692 #define BNX2X_DEF_SB_IDX        0x0002
3693
3694 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3695 {
3696         struct host_sp_status_block *def_sb = bp->def_status_blk;
3697         u16 rc = 0;
3698
3699         barrier(); /* status block is written to by the chip */
3700         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3701                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3702                 rc |= BNX2X_DEF_SB_ATT_IDX;
3703         }
3704
3705         if (bp->def_idx != def_sb->sp_sb.running_index) {
3706                 bp->def_idx = def_sb->sp_sb.running_index;
3707                 rc |= BNX2X_DEF_SB_IDX;
3708         }
3709
3710         /* Do not reorder: indices reading should complete before handling */
3711         barrier();
3712         return rc;
3713 }
3714
3715 /*
3716  * slow path service functions
3717  */
3718
3719 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3720 {
3721         int port = BP_PORT(bp);
3722         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3723                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3724         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3725                                        NIG_REG_MASK_INTERRUPT_PORT0;
3726         u32 aeu_mask;
3727         u32 nig_mask = 0;
3728         u32 reg_addr;
3729
3730         if (bp->attn_state & asserted)
3731                 BNX2X_ERR("IGU ERROR\n");
3732
3733         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3734         aeu_mask = REG_RD(bp, aeu_addr);
3735
3736         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
3737            aeu_mask, asserted);
3738         aeu_mask &= ~(asserted & 0x3ff);
3739         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3740
3741         REG_WR(bp, aeu_addr, aeu_mask);
3742         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3743
3744         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3745         bp->attn_state |= asserted;
3746         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3747
3748         if (asserted & ATTN_HARD_WIRED_MASK) {
3749                 if (asserted & ATTN_NIG_FOR_FUNC) {
3750
3751                         bnx2x_acquire_phy_lock(bp);
3752
3753                         /* save nig interrupt mask */
3754                         nig_mask = REG_RD(bp, nig_int_mask_addr);
3755
3756                         /* If nig_mask is not set, no need to call the update
3757                          * function.
3758                          */
3759                         if (nig_mask) {
3760                                 REG_WR(bp, nig_int_mask_addr, 0);
3761
3762                                 bnx2x_link_attn(bp);
3763                         }
3764
3765                         /* handle unicore attn? */
3766                 }
3767                 if (asserted & ATTN_SW_TIMER_4_FUNC)
3768                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3769
3770                 if (asserted & GPIO_2_FUNC)
3771                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3772
3773                 if (asserted & GPIO_3_FUNC)
3774                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3775
3776                 if (asserted & GPIO_4_FUNC)
3777                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3778
3779                 if (port == 0) {
3780                         if (asserted & ATTN_GENERAL_ATTN_1) {
3781                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3782                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3783                         }
3784                         if (asserted & ATTN_GENERAL_ATTN_2) {
3785                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3786                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3787                         }
3788                         if (asserted & ATTN_GENERAL_ATTN_3) {
3789                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3790                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3791                         }
3792                 } else {
3793                         if (asserted & ATTN_GENERAL_ATTN_4) {
3794                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3795                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3796                         }
3797                         if (asserted & ATTN_GENERAL_ATTN_5) {
3798                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3799                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3800                         }
3801                         if (asserted & ATTN_GENERAL_ATTN_6) {
3802                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3803                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3804                         }
3805                 }
3806
3807         } /* if hardwired */
3808
3809         if (bp->common.int_block == INT_BLOCK_HC)
3810                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3811                             COMMAND_REG_ATTN_BITS_SET);
3812         else
3813                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3814
3815         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3816            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3817         REG_WR(bp, reg_addr, asserted);
3818
3819         /* now set back the mask */
3820         if (asserted & ATTN_NIG_FOR_FUNC) {
3821                 /* Verify that IGU ack through BAR was written before restoring
3822                  * NIG mask. This loop should exit after 2-3 iterations max.
3823                  */
3824                 if (bp->common.int_block != INT_BLOCK_HC) {
3825                         u32 cnt = 0, igu_acked;
3826                         do {
3827                                 igu_acked = REG_RD(bp,
3828                                                    IGU_REG_ATTENTION_ACK_BITS);
3829                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
3830                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
3831                         if (!igu_acked)
3832                                 DP(NETIF_MSG_HW,
3833                                    "Failed to verify IGU ack on time\n");
3834                         barrier();
3835                 }
3836                 REG_WR(bp, nig_int_mask_addr, nig_mask);
3837                 bnx2x_release_phy_lock(bp);
3838         }
3839 }
3840
3841 static void bnx2x_fan_failure(struct bnx2x *bp)
3842 {
3843         int port = BP_PORT(bp);
3844         u32 ext_phy_config;
3845         /* mark the failure */
3846         ext_phy_config =
3847                 SHMEM_RD(bp,
3848                          dev_info.port_hw_config[port].external_phy_config);
3849
3850         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3851         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3852         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3853                  ext_phy_config);
3854
3855         /* log the failure */
3856         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3857                             "Please contact OEM Support for assistance\n");
3858
3859         /* Schedule device reset (unload)
3860          * This is due to some boards consuming sufficient power when driver is
3861          * up to overheat if fan fails.
3862          */
3863         smp_mb__before_clear_bit();
3864         set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3865         smp_mb__after_clear_bit();
3866         schedule_delayed_work(&bp->sp_rtnl_task, 0);
3867 }
3868
3869 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3870 {
3871         int port = BP_PORT(bp);
3872         int reg_offset;
3873         u32 val;
3874
3875         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3876                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3877
3878         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3879
3880                 val = REG_RD(bp, reg_offset);
3881                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3882                 REG_WR(bp, reg_offset, val);
3883
3884                 BNX2X_ERR("SPIO5 hw attention\n");
3885
3886                 /* Fan failure attention */
3887                 bnx2x_hw_reset_phy(&bp->link_params);
3888                 bnx2x_fan_failure(bp);
3889         }
3890
3891         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3892                 bnx2x_acquire_phy_lock(bp);
3893                 bnx2x_handle_module_detect_int(&bp->link_params);
3894                 bnx2x_release_phy_lock(bp);
3895         }
3896
3897         if (attn & HW_INTERRUT_ASSERT_SET_0) {
3898
3899                 val = REG_RD(bp, reg_offset);
3900                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3901                 REG_WR(bp, reg_offset, val);
3902
3903                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3904                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3905                 bnx2x_panic();
3906         }
3907 }
3908
3909 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3910 {
3911         u32 val;
3912
3913         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3914
3915                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3916                 BNX2X_ERR("DB hw attention 0x%x\n", val);
3917                 /* DORQ discard attention */
3918                 if (val & 0x2)
3919                         BNX2X_ERR("FATAL error from DORQ\n");
3920         }
3921
3922         if (attn & HW_INTERRUT_ASSERT_SET_1) {
3923
3924                 int port = BP_PORT(bp);
3925                 int reg_offset;
3926
3927                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3928                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3929
3930                 val = REG_RD(bp, reg_offset);
3931                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3932                 REG_WR(bp, reg_offset, val);
3933
3934                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3935                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3936                 bnx2x_panic();
3937         }
3938 }
3939
3940 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3941 {
3942         u32 val;
3943
3944         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3945
3946                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3947                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3948                 /* CFC error attention */
3949                 if (val & 0x2)
3950                         BNX2X_ERR("FATAL error from CFC\n");
3951         }
3952
3953         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3954                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3955                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3956                 /* RQ_USDMDP_FIFO_OVERFLOW */
3957                 if (val & 0x18000)
3958                         BNX2X_ERR("FATAL error from PXP\n");
3959
3960                 if (!CHIP_IS_E1x(bp)) {
3961                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3962                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3963                 }
3964         }
3965
3966         if (attn & HW_INTERRUT_ASSERT_SET_2) {
3967
3968                 int port = BP_PORT(bp);
3969                 int reg_offset;
3970
3971                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3972                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3973
3974                 val = REG_RD(bp, reg_offset);
3975                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3976                 REG_WR(bp, reg_offset, val);
3977
3978                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3979                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3980                 bnx2x_panic();
3981         }
3982 }
3983
3984 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3985 {
3986         u32 val;
3987
3988         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3989
3990                 if (attn & BNX2X_PMF_LINK_ASSERT) {
3991                         int func = BP_FUNC(bp);
3992
3993                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3994                         bnx2x_read_mf_cfg(bp);
3995                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3996                                         func_mf_config[BP_ABS_FUNC(bp)].config);
3997                         val = SHMEM_RD(bp,
3998                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
3999                         if (val & DRV_STATUS_DCC_EVENT_MASK)
4000                                 bnx2x_dcc_event(bp,
4001                                             (val & DRV_STATUS_DCC_EVENT_MASK));
4002
4003                         if (val & DRV_STATUS_SET_MF_BW)
4004                                 bnx2x_set_mf_bw(bp);
4005
4006                         if (val & DRV_STATUS_DRV_INFO_REQ)
4007                                 bnx2x_handle_drv_info_req(bp);
4008
4009                         if (val & DRV_STATUS_VF_DISABLED)
4010                                 bnx2x_vf_handle_flr_event(bp);
4011
4012                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4013                                 bnx2x_pmf_update(bp);
4014
4015                         if (bp->port.pmf &&
4016                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4017                                 bp->dcbx_enabled > 0)
4018                                 /* start dcbx state machine */
4019                                 bnx2x_dcbx_set_params(bp,
4020                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
4021                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
4022                                 bnx2x_handle_afex_cmd(bp,
4023                                         val & DRV_STATUS_AFEX_EVENT_MASK);
4024                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4025                                 bnx2x_handle_eee_event(bp);
4026                         if (bp->link_vars.periodic_flags &
4027                             PERIODIC_FLAGS_LINK_EVENT) {
4028                                 /*  sync with link */
4029                                 bnx2x_acquire_phy_lock(bp);
4030                                 bp->link_vars.periodic_flags &=
4031                                         ~PERIODIC_FLAGS_LINK_EVENT;
4032                                 bnx2x_release_phy_lock(bp);
4033                                 if (IS_MF(bp))
4034                                         bnx2x_link_sync_notify(bp);
4035                                 bnx2x_link_report(bp);
4036                         }
4037                         /* Always call it here: bnx2x_link_report() will
4038                          * prevent the link indication duplication.
4039                          */
4040                         bnx2x__link_status_update(bp);
4041                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4042
4043                         BNX2X_ERR("MC assert!\n");
4044                         bnx2x_mc_assert(bp);
4045                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4046                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4047                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4048                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4049                         bnx2x_panic();
4050
4051                 } else if (attn & BNX2X_MCP_ASSERT) {
4052
4053                         BNX2X_ERR("MCP assert!\n");
4054                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4055                         bnx2x_fw_dump(bp);
4056
4057                 } else
4058                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4059         }
4060
4061         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4062                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4063                 if (attn & BNX2X_GRC_TIMEOUT) {
4064                         val = CHIP_IS_E1(bp) ? 0 :
4065                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4066                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4067                 }
4068                 if (attn & BNX2X_GRC_RSV) {
4069                         val = CHIP_IS_E1(bp) ? 0 :
4070                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4071                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4072                 }
4073                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4074         }
4075 }
4076
4077 /*
4078  * Bits map:
4079  * 0-7   - Engine0 load counter.
4080  * 8-15  - Engine1 load counter.
4081  * 16    - Engine0 RESET_IN_PROGRESS bit.
4082  * 17    - Engine1 RESET_IN_PROGRESS bit.
4083  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4084  *         on the engine
4085  * 19    - Engine1 ONE_IS_LOADED.
4086  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4087  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4088  *         just the one belonging to its engine).
4089  *
4090  */
4091 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4092
4093 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4094 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4095 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4096 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4097 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4098 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4099 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4100
4101 /*
4102  * Set the GLOBAL_RESET bit.
4103  *
4104  * Should be run under rtnl lock
4105  */
4106 void bnx2x_set_reset_global(struct bnx2x *bp)
4107 {
4108         u32 val;
4109         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4110         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4111         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4112         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4113 }
4114
4115 /*
4116  * Clear the GLOBAL_RESET bit.
4117  *
4118  * Should be run under rtnl lock
4119  */
4120 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4121 {
4122         u32 val;
4123         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4124         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4125         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4126         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4127 }
4128
4129 /*
4130  * Checks the GLOBAL_RESET bit.
4131  *
4132  * should be run under rtnl lock
4133  */
4134 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4135 {
4136         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4137
4138         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4139         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4140 }
4141
4142 /*
4143  * Clear RESET_IN_PROGRESS bit for the current engine.
4144  *
4145  * Should be run under rtnl lock
4146  */
4147 static void bnx2x_set_reset_done(struct bnx2x *bp)
4148 {
4149         u32 val;
4150         u32 bit = BP_PATH(bp) ?
4151                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4152         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4153         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4154
4155         /* Clear the bit */
4156         val &= ~bit;
4157         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4158
4159         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4160 }
4161
4162 /*
4163  * Set RESET_IN_PROGRESS for the current engine.
4164  *
4165  * should be run under rtnl lock
4166  */
4167 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4168 {
4169         u32 val;
4170         u32 bit = BP_PATH(bp) ?
4171                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4172         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4173         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4174
4175         /* Set the bit */
4176         val |= bit;
4177         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4178         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4179 }
4180
4181 /*
4182  * Checks the RESET_IN_PROGRESS bit for the given engine.
4183  * should be run under rtnl lock
4184  */
4185 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4186 {
4187         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4188         u32 bit = engine ?
4189                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4190
4191         /* return false if bit is set */
4192         return (val & bit) ? false : true;
4193 }
4194
4195 /*
4196  * set pf load for the current pf.
4197  *
4198  * should be run under rtnl lock
4199  */
4200 void bnx2x_set_pf_load(struct bnx2x *bp)
4201 {
4202         u32 val1, val;
4203         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4204                              BNX2X_PATH0_LOAD_CNT_MASK;
4205         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4206                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4207
4208         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4209         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4210
4211         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4212
4213         /* get the current counter value */
4214         val1 = (val & mask) >> shift;
4215
4216         /* set bit of that PF */
4217         val1 |= (1 << bp->pf_num);
4218
4219         /* clear the old value */
4220         val &= ~mask;
4221
4222         /* set the new one */
4223         val |= ((val1 << shift) & mask);
4224
4225         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4226         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4227 }
4228
4229 /**
4230  * bnx2x_clear_pf_load - clear pf load mark
4231  *
4232  * @bp:         driver handle
4233  *
4234  * Should be run under rtnl lock.
4235  * Decrements the load counter for the current engine. Returns
4236  * whether other functions are still loaded
4237  */
4238 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4239 {
4240         u32 val1, val;
4241         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4242                              BNX2X_PATH0_LOAD_CNT_MASK;
4243         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4244                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4245
4246         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4247         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4248         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4249
4250         /* get the current counter value */
4251         val1 = (val & mask) >> shift;
4252
4253         /* clear bit of that PF */
4254         val1 &= ~(1 << bp->pf_num);
4255
4256         /* clear the old value */
4257         val &= ~mask;
4258
4259         /* set the new one */
4260         val |= ((val1 << shift) & mask);
4261
4262         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4263         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4264         return val1 != 0;
4265 }
4266
4267 /*
4268  * Read the load status for the current engine.
4269  *
4270  * should be run under rtnl lock
4271  */
4272 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4273 {
4274         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4275                              BNX2X_PATH0_LOAD_CNT_MASK);
4276         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4277                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4278         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4279
4280         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4281
4282         val = (val & mask) >> shift;
4283
4284         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4285            engine, val);
4286
4287         return val != 0;
4288 }
4289
4290 static void _print_parity(struct bnx2x *bp, u32 reg)
4291 {
4292         pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4293 }
4294
4295 static void _print_next_block(int idx, const char *blk)
4296 {
4297         pr_cont("%s%s", idx ? ", " : "", blk);
4298 }
4299
4300 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4301                                             int *par_num, bool print)
4302 {
4303         u32 cur_bit;
4304         bool res;
4305         int i;
4306
4307         res = false;
4308
4309         for (i = 0; sig; i++) {
4310                 cur_bit = (0x1UL << i);
4311                 if (sig & cur_bit) {
4312                         res |= true; /* Each bit is real error! */
4313
4314                         if (print) {
4315                                 switch (cur_bit) {
4316                                 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4317                                         _print_next_block((*par_num)++, "BRB");
4318                                         _print_parity(bp,
4319                                                       BRB1_REG_BRB1_PRTY_STS);
4320                                         break;
4321                                 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4322                                         _print_next_block((*par_num)++,
4323                                                           "PARSER");
4324                                         _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4325                                         break;
4326                                 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4327                                         _print_next_block((*par_num)++, "TSDM");
4328                                         _print_parity(bp,
4329                                                       TSDM_REG_TSDM_PRTY_STS);
4330                                         break;
4331                                 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4332                                         _print_next_block((*par_num)++,
4333                                                           "SEARCHER");
4334                                         _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4335                                         break;
4336                                 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4337                                         _print_next_block((*par_num)++, "TCM");
4338                                         _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4339                                         break;
4340                                 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4341                                         _print_next_block((*par_num)++,
4342                                                           "TSEMI");
4343                                         _print_parity(bp,
4344                                                       TSEM_REG_TSEM_PRTY_STS_0);
4345                                         _print_parity(bp,
4346                                                       TSEM_REG_TSEM_PRTY_STS_1);
4347                                         break;
4348                                 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4349                                         _print_next_block((*par_num)++, "XPB");
4350                                         _print_parity(bp, GRCBASE_XPB +
4351                                                           PB_REG_PB_PRTY_STS);
4352                                         break;
4353                                 }
4354                         }
4355
4356                         /* Clear the bit */
4357                         sig &= ~cur_bit;
4358                 }
4359         }
4360
4361         return res;
4362 }
4363
4364 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4365                                             int *par_num, bool *global,
4366                                             bool print)
4367 {
4368         u32 cur_bit;
4369         bool res;
4370         int i;
4371
4372         res = false;
4373
4374         for (i = 0; sig; i++) {
4375                 cur_bit = (0x1UL << i);
4376                 if (sig & cur_bit) {
4377                         res |= true; /* Each bit is real error! */
4378                         switch (cur_bit) {
4379                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4380                                 if (print) {
4381                                         _print_next_block((*par_num)++, "PBF");
4382                                         _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4383                                 }
4384                                 break;
4385                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4386                                 if (print) {
4387                                         _print_next_block((*par_num)++, "QM");
4388                                         _print_parity(bp, QM_REG_QM_PRTY_STS);
4389                                 }
4390                                 break;
4391                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4392                                 if (print) {
4393                                         _print_next_block((*par_num)++, "TM");
4394                                         _print_parity(bp, TM_REG_TM_PRTY_STS);
4395                                 }
4396                                 break;
4397                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4398                                 if (print) {
4399                                         _print_next_block((*par_num)++, "XSDM");
4400                                         _print_parity(bp,
4401                                                       XSDM_REG_XSDM_PRTY_STS);
4402                                 }
4403                                 break;
4404                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4405                                 if (print) {
4406                                         _print_next_block((*par_num)++, "XCM");
4407                                         _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4408                                 }
4409                                 break;
4410                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4411                                 if (print) {
4412                                         _print_next_block((*par_num)++,
4413                                                           "XSEMI");
4414                                         _print_parity(bp,
4415                                                       XSEM_REG_XSEM_PRTY_STS_0);
4416                                         _print_parity(bp,
4417                                                       XSEM_REG_XSEM_PRTY_STS_1);
4418                                 }
4419                                 break;
4420                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4421                                 if (print) {
4422                                         _print_next_block((*par_num)++,
4423                                                           "DOORBELLQ");
4424                                         _print_parity(bp,
4425                                                       DORQ_REG_DORQ_PRTY_STS);
4426                                 }
4427                                 break;
4428                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4429                                 if (print) {
4430                                         _print_next_block((*par_num)++, "NIG");
4431                                         if (CHIP_IS_E1x(bp)) {
4432                                                 _print_parity(bp,
4433                                                         NIG_REG_NIG_PRTY_STS);
4434                                         } else {
4435                                                 _print_parity(bp,
4436                                                         NIG_REG_NIG_PRTY_STS_0);
4437                                                 _print_parity(bp,
4438                                                         NIG_REG_NIG_PRTY_STS_1);
4439                                         }
4440                                 }
4441                                 break;
4442                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4443                                 if (print)
4444                                         _print_next_block((*par_num)++,
4445                                                           "VAUX PCI CORE");
4446                                 *global = true;
4447                                 break;
4448                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4449                                 if (print) {
4450                                         _print_next_block((*par_num)++,
4451                                                           "DEBUG");
4452                                         _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4453                                 }
4454                                 break;
4455                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4456                                 if (print) {
4457                                         _print_next_block((*par_num)++, "USDM");
4458                                         _print_parity(bp,
4459                                                       USDM_REG_USDM_PRTY_STS);
4460                                 }
4461                                 break;
4462                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4463                                 if (print) {
4464                                         _print_next_block((*par_num)++, "UCM");
4465                                         _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4466                                 }
4467                                 break;
4468                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4469                                 if (print) {
4470                                         _print_next_block((*par_num)++,
4471                                                           "USEMI");
4472                                         _print_parity(bp,
4473                                                       USEM_REG_USEM_PRTY_STS_0);
4474                                         _print_parity(bp,
4475                                                       USEM_REG_USEM_PRTY_STS_1);
4476                                 }
4477                                 break;
4478                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4479                                 if (print) {
4480                                         _print_next_block((*par_num)++, "UPB");
4481                                         _print_parity(bp, GRCBASE_UPB +
4482                                                           PB_REG_PB_PRTY_STS);
4483                                 }
4484                                 break;
4485                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4486                                 if (print) {
4487                                         _print_next_block((*par_num)++, "CSDM");
4488                                         _print_parity(bp,
4489                                                       CSDM_REG_CSDM_PRTY_STS);
4490                                 }
4491                                 break;
4492                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4493                                 if (print) {
4494                                         _print_next_block((*par_num)++, "CCM");
4495                                         _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4496                                 }
4497                                 break;
4498                         }
4499
4500                         /* Clear the bit */
4501                         sig &= ~cur_bit;
4502                 }
4503         }
4504
4505         return res;
4506 }
4507
4508 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4509                                             int *par_num, bool print)
4510 {
4511         u32 cur_bit;
4512         bool res;
4513         int i;
4514
4515         res = false;
4516
4517         for (i = 0; sig; i++) {
4518                 cur_bit = (0x1UL << i);
4519                 if (sig & cur_bit) {
4520                         res |= true; /* Each bit is real error! */
4521                         if (print) {
4522                                 switch (cur_bit) {
4523                                 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4524                                         _print_next_block((*par_num)++,
4525                                                           "CSEMI");
4526                                         _print_parity(bp,
4527                                                       CSEM_REG_CSEM_PRTY_STS_0);
4528                                         _print_parity(bp,
4529                                                       CSEM_REG_CSEM_PRTY_STS_1);
4530                                         break;
4531                                 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4532                                         _print_next_block((*par_num)++, "PXP");
4533                                         _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4534                                         _print_parity(bp,
4535                                                       PXP2_REG_PXP2_PRTY_STS_0);
4536                                         _print_parity(bp,
4537                                                       PXP2_REG_PXP2_PRTY_STS_1);
4538                                         break;
4539                                 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4540                                         _print_next_block((*par_num)++,
4541                                                           "PXPPCICLOCKCLIENT");
4542                                         break;
4543                                 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4544                                         _print_next_block((*par_num)++, "CFC");
4545                                         _print_parity(bp,
4546                                                       CFC_REG_CFC_PRTY_STS);
4547                                         break;
4548                                 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4549                                         _print_next_block((*par_num)++, "CDU");
4550                                         _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4551                                         break;
4552                                 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4553                                         _print_next_block((*par_num)++, "DMAE");
4554                                         _print_parity(bp,
4555                                                       DMAE_REG_DMAE_PRTY_STS);
4556                                         break;
4557                                 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4558                                         _print_next_block((*par_num)++, "IGU");
4559                                         if (CHIP_IS_E1x(bp))
4560                                                 _print_parity(bp,
4561                                                         HC_REG_HC_PRTY_STS);
4562                                         else
4563                                                 _print_parity(bp,
4564                                                         IGU_REG_IGU_PRTY_STS);
4565                                         break;
4566                                 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4567                                         _print_next_block((*par_num)++, "MISC");
4568                                         _print_parity(bp,
4569                                                       MISC_REG_MISC_PRTY_STS);
4570                                         break;
4571                                 }
4572                         }
4573
4574                         /* Clear the bit */
4575                         sig &= ~cur_bit;
4576                 }
4577         }
4578
4579         return res;
4580 }
4581
4582 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4583                                             int *par_num, bool *global,
4584                                             bool print)
4585 {
4586         bool res = false;
4587         u32 cur_bit;
4588         int i;
4589
4590         for (i = 0; sig; i++) {
4591                 cur_bit = (0x1UL << i);
4592                 if (sig & cur_bit) {
4593                         switch (cur_bit) {
4594                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4595                                 if (print)
4596                                         _print_next_block((*par_num)++,
4597                                                           "MCP ROM");
4598                                 *global = true;
4599                                 res |= true;
4600                                 break;
4601                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4602                                 if (print)
4603                                         _print_next_block((*par_num)++,
4604                                                           "MCP UMP RX");
4605                                 *global = true;
4606                                 res |= true;
4607                                 break;
4608                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4609                                 if (print)
4610                                         _print_next_block((*par_num)++,
4611                                                           "MCP UMP TX");
4612                                 *global = true;
4613                                 res |= true;
4614                                 break;
4615                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4616                                 if (print)
4617                                         _print_next_block((*par_num)++,
4618                                                           "MCP SCPAD");
4619                                 /* clear latched SCPAD PATIRY from MCP */
4620                                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4621                                        1UL << 10);
4622                                 break;
4623                         }
4624
4625                         /* Clear the bit */
4626                         sig &= ~cur_bit;
4627                 }
4628         }
4629
4630         return res;
4631 }
4632
4633 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4634                                             int *par_num, bool print)
4635 {
4636         u32 cur_bit;
4637         bool res;
4638         int i;
4639
4640         res = false;
4641
4642         for (i = 0; sig; i++) {
4643                 cur_bit = (0x1UL << i);
4644                 if (sig & cur_bit) {
4645                         res |= true; /* Each bit is real error! */
4646                         if (print) {
4647                                 switch (cur_bit) {
4648                                 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4649                                         _print_next_block((*par_num)++,
4650                                                           "PGLUE_B");
4651                                         _print_parity(bp,
4652                                                       PGLUE_B_REG_PGLUE_B_PRTY_STS);
4653                                         break;
4654                                 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4655                                         _print_next_block((*par_num)++, "ATC");
4656                                         _print_parity(bp,
4657                                                       ATC_REG_ATC_PRTY_STS);
4658                                         break;
4659                                 }
4660                         }
4661                         /* Clear the bit */
4662                         sig &= ~cur_bit;
4663                 }
4664         }
4665
4666         return res;
4667 }
4668
4669 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4670                               u32 *sig)
4671 {
4672         bool res = false;
4673
4674         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4675             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4676             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4677             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4678             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4679                 int par_num = 0;
4680                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4681                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4682                           sig[0] & HW_PRTY_ASSERT_SET_0,
4683                           sig[1] & HW_PRTY_ASSERT_SET_1,
4684                           sig[2] & HW_PRTY_ASSERT_SET_2,
4685                           sig[3] & HW_PRTY_ASSERT_SET_3,
4686                           sig[4] & HW_PRTY_ASSERT_SET_4);
4687                 if (print)
4688                         netdev_err(bp->dev,
4689                                    "Parity errors detected in blocks: ");
4690                 res |= bnx2x_check_blocks_with_parity0(bp,
4691                         sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4692                 res |= bnx2x_check_blocks_with_parity1(bp,
4693                         sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4694                 res |= bnx2x_check_blocks_with_parity2(bp,
4695                         sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4696                 res |= bnx2x_check_blocks_with_parity3(bp,
4697                         sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4698                 res |= bnx2x_check_blocks_with_parity4(bp,
4699                         sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4700
4701                 if (print)
4702                         pr_cont("\n");
4703         }
4704
4705         return res;
4706 }
4707
4708 /**
4709  * bnx2x_chk_parity_attn - checks for parity attentions.
4710  *
4711  * @bp:         driver handle
4712  * @global:     true if there was a global attention
4713  * @print:      show parity attention in syslog
4714  */
4715 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4716 {
4717         struct attn_route attn = { {0} };
4718         int port = BP_PORT(bp);
4719
4720         attn.sig[0] = REG_RD(bp,
4721                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4722                              port*4);
4723         attn.sig[1] = REG_RD(bp,
4724                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4725                              port*4);
4726         attn.sig[2] = REG_RD(bp,
4727                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4728                              port*4);
4729         attn.sig[3] = REG_RD(bp,
4730                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4731                              port*4);
4732         /* Since MCP attentions can't be disabled inside the block, we need to
4733          * read AEU registers to see whether they're currently disabled
4734          */
4735         attn.sig[3] &= ((REG_RD(bp,
4736                                 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
4737                                       : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
4738                          MISC_AEU_ENABLE_MCP_PRTY_BITS) |
4739                         ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
4740
4741         if (!CHIP_IS_E1x(bp))
4742                 attn.sig[4] = REG_RD(bp,
4743                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4744                                      port*4);
4745
4746         return bnx2x_parity_attn(bp, global, print, attn.sig);
4747 }
4748
4749 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4750 {
4751         u32 val;
4752         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4753
4754                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4755                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4756                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4757                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4758                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4759                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4760                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4761                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4762                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4763                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4764                 if (val &
4765                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4766                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4767                 if (val &
4768                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4769                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4770                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4771                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4772                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4773                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4774                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4775                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4776         }
4777         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4778                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4779                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4780                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4781                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4782                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4783                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4784                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4785                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4786                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4787                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4788                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4789                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4790                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4791                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4792         }
4793
4794         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4795                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4796                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4797                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4798                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4799         }
4800 }
4801
4802 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4803 {
4804         struct attn_route attn, *group_mask;
4805         int port = BP_PORT(bp);
4806         int index;
4807         u32 reg_addr;
4808         u32 val;
4809         u32 aeu_mask;
4810         bool global = false;
4811
4812         /* need to take HW lock because MCP or other port might also
4813            try to handle this event */
4814         bnx2x_acquire_alr(bp);
4815
4816         if (bnx2x_chk_parity_attn(bp, &global, true)) {
4817 #ifndef BNX2X_STOP_ON_ERROR
4818                 bp->recovery_state = BNX2X_RECOVERY_INIT;
4819                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4820                 /* Disable HW interrupts */
4821                 bnx2x_int_disable(bp);
4822                 /* In case of parity errors don't handle attentions so that
4823                  * other function would "see" parity errors.
4824                  */
4825 #else
4826                 bnx2x_panic();
4827 #endif
4828                 bnx2x_release_alr(bp);
4829                 return;
4830         }
4831
4832         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4833         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4834         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4835         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4836         if (!CHIP_IS_E1x(bp))
4837                 attn.sig[4] =
4838                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4839         else
4840                 attn.sig[4] = 0;
4841
4842         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4843            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4844
4845         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4846                 if (deasserted & (1 << index)) {
4847                         group_mask = &bp->attn_group[index];
4848
4849                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
4850                            index,
4851                            group_mask->sig[0], group_mask->sig[1],
4852                            group_mask->sig[2], group_mask->sig[3],
4853                            group_mask->sig[4]);
4854
4855                         bnx2x_attn_int_deasserted4(bp,
4856                                         attn.sig[4] & group_mask->sig[4]);
4857                         bnx2x_attn_int_deasserted3(bp,
4858                                         attn.sig[3] & group_mask->sig[3]);
4859                         bnx2x_attn_int_deasserted1(bp,
4860                                         attn.sig[1] & group_mask->sig[1]);
4861                         bnx2x_attn_int_deasserted2(bp,
4862                                         attn.sig[2] & group_mask->sig[2]);
4863                         bnx2x_attn_int_deasserted0(bp,
4864                                         attn.sig[0] & group_mask->sig[0]);
4865                 }
4866         }
4867
4868         bnx2x_release_alr(bp);
4869
4870         if (bp->common.int_block == INT_BLOCK_HC)
4871                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4872                             COMMAND_REG_ATTN_BITS_CLR);
4873         else
4874                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4875
4876         val = ~deasserted;
4877         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4878            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4879         REG_WR(bp, reg_addr, val);
4880
4881         if (~bp->attn_state & deasserted)
4882                 BNX2X_ERR("IGU ERROR\n");
4883
4884         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4885                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
4886
4887         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4888         aeu_mask = REG_RD(bp, reg_addr);
4889
4890         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
4891            aeu_mask, deasserted);
4892         aeu_mask |= (deasserted & 0x3ff);
4893         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4894
4895         REG_WR(bp, reg_addr, aeu_mask);
4896         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4897
4898         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4899         bp->attn_state &= ~deasserted;
4900         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4901 }
4902
4903 static void bnx2x_attn_int(struct bnx2x *bp)
4904 {
4905         /* read local copy of bits */
4906         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4907                                                                 attn_bits);
4908         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4909                                                                 attn_bits_ack);
4910         u32 attn_state = bp->attn_state;
4911
4912         /* look for changed bits */
4913         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
4914         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
4915
4916         DP(NETIF_MSG_HW,
4917            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
4918            attn_bits, attn_ack, asserted, deasserted);
4919
4920         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4921                 BNX2X_ERR("BAD attention state\n");
4922
4923         /* handle bits that were raised */
4924         if (asserted)
4925                 bnx2x_attn_int_asserted(bp, asserted);
4926
4927         if (deasserted)
4928                 bnx2x_attn_int_deasserted(bp, deasserted);
4929 }
4930
4931 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4932                       u16 index, u8 op, u8 update)
4933 {
4934         u32 igu_addr = bp->igu_base_addr;
4935         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4936         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4937                              igu_addr);
4938 }
4939
4940 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4941 {
4942         /* No memory barriers */
4943         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4944         mmiowb(); /* keep prod updates ordered */
4945 }
4946
4947 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4948                                       union event_ring_elem *elem)
4949 {
4950         u8 err = elem->message.error;
4951
4952         if (!bp->cnic_eth_dev.starting_cid  ||
4953             (cid < bp->cnic_eth_dev.starting_cid &&
4954             cid != bp->cnic_eth_dev.iscsi_l2_cid))
4955                 return 1;
4956
4957         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4958
4959         if (unlikely(err)) {
4960
4961                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4962                           cid);
4963                 bnx2x_panic_dump(bp, false);
4964         }
4965         bnx2x_cnic_cfc_comp(bp, cid, err);
4966         return 0;
4967 }
4968
4969 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4970 {
4971         struct bnx2x_mcast_ramrod_params rparam;
4972         int rc;
4973
4974         memset(&rparam, 0, sizeof(rparam));
4975
4976         rparam.mcast_obj = &bp->mcast_obj;
4977
4978         netif_addr_lock_bh(bp->dev);
4979
4980         /* Clear pending state for the last command */
4981         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4982
4983         /* If there are pending mcast commands - send them */
4984         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4985                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4986                 if (rc < 0)
4987                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4988                                   rc);
4989         }
4990
4991         netif_addr_unlock_bh(bp->dev);
4992 }
4993
4994 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4995                                             union event_ring_elem *elem)
4996 {
4997         unsigned long ramrod_flags = 0;
4998         int rc = 0;
4999         u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5000         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5001
5002         /* Always push next commands out, don't wait here */
5003         __set_bit(RAMROD_CONT, &ramrod_flags);
5004
5005         switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5006                             >> BNX2X_SWCID_SHIFT) {
5007         case BNX2X_FILTER_MAC_PENDING:
5008                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5009                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5010                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5011                 else
5012                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5013
5014                 break;
5015         case BNX2X_FILTER_MCAST_PENDING:
5016                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5017                 /* This is only relevant for 57710 where multicast MACs are
5018                  * configured as unicast MACs using the same ramrod.
5019                  */
5020                 bnx2x_handle_mcast_eqe(bp);
5021                 return;
5022         default:
5023                 BNX2X_ERR("Unsupported classification command: %d\n",
5024                           elem->message.data.eth_event.echo);
5025                 return;
5026         }
5027
5028         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5029
5030         if (rc < 0)
5031                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5032         else if (rc > 0)
5033                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5034 }
5035
5036 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5037
5038 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5039 {
5040         netif_addr_lock_bh(bp->dev);
5041
5042         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5043
5044         /* Send rx_mode command again if was requested */
5045         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5046                 bnx2x_set_storm_rx_mode(bp);
5047         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5048                                     &bp->sp_state))
5049                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5050         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5051                                     &bp->sp_state))
5052                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5053
5054         netif_addr_unlock_bh(bp->dev);
5055 }
5056
5057 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5058                                               union event_ring_elem *elem)
5059 {
5060         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5061                 DP(BNX2X_MSG_SP,
5062                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5063                    elem->message.data.vif_list_event.func_bit_map);
5064                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5065                         elem->message.data.vif_list_event.func_bit_map);
5066         } else if (elem->message.data.vif_list_event.echo ==
5067                    VIF_LIST_RULE_SET) {
5068                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5069                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5070         }
5071 }
5072
5073 /* called with rtnl_lock */
5074 static void bnx2x_after_function_update(struct bnx2x *bp)
5075 {
5076         int q, rc;
5077         struct bnx2x_fastpath *fp;
5078         struct bnx2x_queue_state_params queue_params = {NULL};
5079         struct bnx2x_queue_update_params *q_update_params =
5080                 &queue_params.params.update;
5081
5082         /* Send Q update command with afex vlan removal values for all Qs */
5083         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5084
5085         /* set silent vlan removal values according to vlan mode */
5086         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5087                   &q_update_params->update_flags);
5088         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5089                   &q_update_params->update_flags);
5090         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5091
5092         /* in access mode mark mask and value are 0 to strip all vlans */
5093         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5094                 q_update_params->silent_removal_value = 0;
5095                 q_update_params->silent_removal_mask = 0;
5096         } else {
5097                 q_update_params->silent_removal_value =
5098                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5099                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5100         }
5101
5102         for_each_eth_queue(bp, q) {
5103                 /* Set the appropriate Queue object */
5104                 fp = &bp->fp[q];
5105                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5106
5107                 /* send the ramrod */
5108                 rc = bnx2x_queue_state_change(bp, &queue_params);
5109                 if (rc < 0)
5110                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5111                                   q);
5112         }
5113
5114         if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5115                 fp = &bp->fp[FCOE_IDX(bp)];
5116                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5117
5118                 /* clear pending completion bit */
5119                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5120
5121                 /* mark latest Q bit */
5122                 smp_mb__before_clear_bit();
5123                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5124                 smp_mb__after_clear_bit();
5125
5126                 /* send Q update ramrod for FCoE Q */
5127                 rc = bnx2x_queue_state_change(bp, &queue_params);
5128                 if (rc < 0)
5129                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5130                                   q);
5131         } else {
5132                 /* If no FCoE ring - ACK MCP now */
5133                 bnx2x_link_report(bp);
5134                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5135         }
5136 }
5137
5138 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5139         struct bnx2x *bp, u32 cid)
5140 {
5141         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5142
5143         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5144                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5145         else
5146                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5147 }
5148
5149 static void bnx2x_eq_int(struct bnx2x *bp)
5150 {
5151         u16 hw_cons, sw_cons, sw_prod;
5152         union event_ring_elem *elem;
5153         u8 echo;
5154         u32 cid;
5155         u8 opcode;
5156         int rc, spqe_cnt = 0;
5157         struct bnx2x_queue_sp_obj *q_obj;
5158         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5159         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5160
5161         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5162
5163         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5164          * when we get the next-page we need to adjust so the loop
5165          * condition below will be met. The next element is the size of a
5166          * regular element and hence incrementing by 1
5167          */
5168         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5169                 hw_cons++;
5170
5171         /* This function may never run in parallel with itself for a
5172          * specific bp, thus there is no need in "paired" read memory
5173          * barrier here.
5174          */
5175         sw_cons = bp->eq_cons;
5176         sw_prod = bp->eq_prod;
5177
5178         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
5179                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5180
5181         for (; sw_cons != hw_cons;
5182               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5183
5184                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5185
5186                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5187                 if (!rc) {
5188                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5189                            rc);
5190                         goto next_spqe;
5191                 }
5192
5193                 /* elem CID originates from FW; actually LE */
5194                 cid = SW_CID((__force __le32)
5195                              elem->message.data.cfc_del_event.cid);
5196                 opcode = elem->message.opcode;
5197
5198                 /* handle eq element */
5199                 switch (opcode) {
5200                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5201                         DP(BNX2X_MSG_IOV, "vf pf channel element on eq\n");
5202                         bnx2x_vf_mbx(bp, &elem->message.data.vf_pf_event);
5203                         continue;
5204
5205                 case EVENT_RING_OPCODE_STAT_QUERY:
5206                         DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
5207                            "got statistics comp event %d\n",
5208                            bp->stats_comp++);
5209                         /* nothing to do with stats comp */
5210                         goto next_spqe;
5211
5212                 case EVENT_RING_OPCODE_CFC_DEL:
5213                         /* handle according to cid range */
5214                         /*
5215                          * we may want to verify here that the bp state is
5216                          * HALTING
5217                          */
5218                         DP(BNX2X_MSG_SP,
5219                            "got delete ramrod for MULTI[%d]\n", cid);
5220
5221                         if (CNIC_LOADED(bp) &&
5222                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5223                                 goto next_spqe;
5224
5225                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5226
5227                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5228                                 break;
5229
5230                         goto next_spqe;
5231
5232                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5233                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5234                         if (f_obj->complete_cmd(bp, f_obj,
5235                                                 BNX2X_F_CMD_TX_STOP))
5236                                 break;
5237                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5238                         goto next_spqe;
5239
5240                 case EVENT_RING_OPCODE_START_TRAFFIC:
5241                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5242                         if (f_obj->complete_cmd(bp, f_obj,
5243                                                 BNX2X_F_CMD_TX_START))
5244                                 break;
5245                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5246                         goto next_spqe;
5247
5248                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5249                         echo = elem->message.data.function_update_event.echo;
5250                         if (echo == SWITCH_UPDATE) {
5251                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5252                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5253                                 if (f_obj->complete_cmd(
5254                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5255                                         break;
5256
5257                         } else {
5258                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5259                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5260                                 f_obj->complete_cmd(bp, f_obj,
5261                                                     BNX2X_F_CMD_AFEX_UPDATE);
5262
5263                                 /* We will perform the Queues update from
5264                                  * sp_rtnl task as all Queue SP operations
5265                                  * should run under rtnl_lock.
5266                                  */
5267                                 smp_mb__before_clear_bit();
5268                                 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE,
5269                                         &bp->sp_rtnl_state);
5270                                 smp_mb__after_clear_bit();
5271
5272                                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5273                         }
5274
5275                         goto next_spqe;
5276
5277                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5278                         f_obj->complete_cmd(bp, f_obj,
5279                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5280                         bnx2x_after_afex_vif_lists(bp, elem);
5281                         goto next_spqe;
5282                 case EVENT_RING_OPCODE_FUNCTION_START:
5283                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5284                            "got FUNC_START ramrod\n");
5285                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5286                                 break;
5287
5288                         goto next_spqe;
5289
5290                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5291                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5292                            "got FUNC_STOP ramrod\n");
5293                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5294                                 break;
5295
5296                         goto next_spqe;
5297                 }
5298
5299                 switch (opcode | bp->state) {
5300                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5301                       BNX2X_STATE_OPEN):
5302                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5303                       BNX2X_STATE_OPENING_WAIT4_PORT):
5304                         cid = elem->message.data.eth_event.echo &
5305                                 BNX2X_SWCID_MASK;
5306                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5307                            cid);
5308                         rss_raw->clear_pending(rss_raw);
5309                         break;
5310
5311                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5312                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5313                 case (EVENT_RING_OPCODE_SET_MAC |
5314                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5315                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5316                       BNX2X_STATE_OPEN):
5317                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5318                       BNX2X_STATE_DIAG):
5319                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5320                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5321                         DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5322                         bnx2x_handle_classification_eqe(bp, elem);
5323                         break;
5324
5325                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5326                       BNX2X_STATE_OPEN):
5327                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5328                       BNX2X_STATE_DIAG):
5329                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5330                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5331                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5332                         bnx2x_handle_mcast_eqe(bp);
5333                         break;
5334
5335                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5336                       BNX2X_STATE_OPEN):
5337                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5338                       BNX2X_STATE_DIAG):
5339                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5340                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5341                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5342                         bnx2x_handle_rx_mode_eqe(bp);
5343                         break;
5344                 default:
5345                         /* unknown event log error and continue */
5346                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5347                                   elem->message.opcode, bp->state);
5348                 }
5349 next_spqe:
5350                 spqe_cnt++;
5351         } /* for */
5352
5353         smp_mb__before_atomic_inc();
5354         atomic_add(spqe_cnt, &bp->eq_spq_left);
5355
5356         bp->eq_cons = sw_cons;
5357         bp->eq_prod = sw_prod;
5358         /* Make sure that above mem writes were issued towards the memory */
5359         smp_wmb();
5360
5361         /* update producer */
5362         bnx2x_update_eq_prod(bp, bp->eq_prod);
5363 }
5364
5365 static void bnx2x_sp_task(struct work_struct *work)
5366 {
5367         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5368
5369         DP(BNX2X_MSG_SP, "sp task invoked\n");
5370
5371         /* make sure the atomic interrupt_occurred has been written */
5372         smp_rmb();
5373         if (atomic_read(&bp->interrupt_occurred)) {
5374
5375                 /* what work needs to be performed? */
5376                 u16 status = bnx2x_update_dsb_idx(bp);
5377
5378                 DP(BNX2X_MSG_SP, "status %x\n", status);
5379                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5380                 atomic_set(&bp->interrupt_occurred, 0);
5381
5382                 /* HW attentions */
5383                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5384                         bnx2x_attn_int(bp);
5385                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5386                 }
5387
5388                 /* SP events: STAT_QUERY and others */
5389                 if (status & BNX2X_DEF_SB_IDX) {
5390                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5391
5392                 if (FCOE_INIT(bp) &&
5393                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5394                                 /* Prevent local bottom-halves from running as
5395                                  * we are going to change the local NAPI list.
5396                                  */
5397                                 local_bh_disable();
5398                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5399                                 local_bh_enable();
5400                         }
5401
5402                         /* Handle EQ completions */
5403                         bnx2x_eq_int(bp);
5404                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5405                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5406
5407                         status &= ~BNX2X_DEF_SB_IDX;
5408                 }
5409
5410                 /* if status is non zero then perhaps something went wrong */
5411                 if (unlikely(status))
5412                         DP(BNX2X_MSG_SP,
5413                            "got an unknown interrupt! (status 0x%x)\n", status);
5414
5415                 /* ack status block only if something was actually handled */
5416                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5417                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5418         }
5419
5420         /* must be called after the EQ processing (since eq leads to sriov
5421          * ramrod completion flows).
5422          * This flow may have been scheduled by the arrival of a ramrod
5423          * completion, or by the sriov code rescheduling itself.
5424          */
5425         bnx2x_iov_sp_task(bp);
5426
5427         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5428         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5429                                &bp->sp_state)) {
5430                 bnx2x_link_report(bp);
5431                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5432         }
5433 }
5434
5435 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5436 {
5437         struct net_device *dev = dev_instance;
5438         struct bnx2x *bp = netdev_priv(dev);
5439
5440         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5441                      IGU_INT_DISABLE, 0);
5442
5443 #ifdef BNX2X_STOP_ON_ERROR
5444         if (unlikely(bp->panic))
5445                 return IRQ_HANDLED;
5446 #endif
5447
5448         if (CNIC_LOADED(bp)) {
5449                 struct cnic_ops *c_ops;
5450
5451                 rcu_read_lock();
5452                 c_ops = rcu_dereference(bp->cnic_ops);
5453                 if (c_ops)
5454                         c_ops->cnic_handler(bp->cnic_data, NULL);
5455                 rcu_read_unlock();
5456         }
5457
5458         /* schedule sp task to perform default status block work, ack
5459          * attentions and enable interrupts.
5460          */
5461         bnx2x_schedule_sp_task(bp);
5462
5463         return IRQ_HANDLED;
5464 }
5465
5466 /* end of slow path */
5467
5468 void bnx2x_drv_pulse(struct bnx2x *bp)
5469 {
5470         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5471                  bp->fw_drv_pulse_wr_seq);
5472 }
5473
5474 static void bnx2x_timer(unsigned long data)
5475 {
5476         struct bnx2x *bp = (struct bnx2x *) data;
5477
5478         if (!netif_running(bp->dev))
5479                 return;
5480
5481         if (IS_PF(bp) &&
5482             !BP_NOMCP(bp)) {
5483                 int mb_idx = BP_FW_MB_IDX(bp);
5484                 u16 drv_pulse;
5485                 u16 mcp_pulse;
5486
5487                 ++bp->fw_drv_pulse_wr_seq;
5488                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5489                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5490                 bnx2x_drv_pulse(bp);
5491
5492                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5493                              MCP_PULSE_SEQ_MASK);
5494                 /* The delta between driver pulse and mcp response
5495                  * should not get too big. If the MFW is more than 5 pulses
5496                  * behind, we should worry about it enough to generate an error
5497                  * log.
5498                  */
5499                 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5500                         BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5501                                   drv_pulse, mcp_pulse);
5502         }
5503
5504         if (bp->state == BNX2X_STATE_OPEN)
5505                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5506
5507         /* sample pf vf bulletin board for new posts from pf */
5508         if (IS_VF(bp))
5509                 bnx2x_timer_sriov(bp);
5510
5511         mod_timer(&bp->timer, jiffies + bp->current_interval);
5512 }
5513
5514 /* end of Statistics */
5515
5516 /* nic init */
5517
5518 /*
5519  * nic init service functions
5520  */
5521
5522 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5523 {
5524         u32 i;
5525         if (!(len%4) && !(addr%4))
5526                 for (i = 0; i < len; i += 4)
5527                         REG_WR(bp, addr + i, fill);
5528         else
5529                 for (i = 0; i < len; i++)
5530                         REG_WR8(bp, addr + i, fill);
5531 }
5532
5533 /* helper: writes FP SP data to FW - data_size in dwords */
5534 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5535                                 int fw_sb_id,
5536                                 u32 *sb_data_p,
5537                                 u32 data_size)
5538 {
5539         int index;
5540         for (index = 0; index < data_size; index++)
5541                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5542                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5543                         sizeof(u32)*index,
5544                         *(sb_data_p + index));
5545 }
5546
5547 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5548 {
5549         u32 *sb_data_p;
5550         u32 data_size = 0;
5551         struct hc_status_block_data_e2 sb_data_e2;
5552         struct hc_status_block_data_e1x sb_data_e1x;
5553
5554         /* disable the function first */
5555         if (!CHIP_IS_E1x(bp)) {
5556                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5557                 sb_data_e2.common.state = SB_DISABLED;
5558                 sb_data_e2.common.p_func.vf_valid = false;
5559                 sb_data_p = (u32 *)&sb_data_e2;
5560                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5561         } else {
5562                 memset(&sb_data_e1x, 0,
5563                        sizeof(struct hc_status_block_data_e1x));
5564                 sb_data_e1x.common.state = SB_DISABLED;
5565                 sb_data_e1x.common.p_func.vf_valid = false;
5566                 sb_data_p = (u32 *)&sb_data_e1x;
5567                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5568         }
5569         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5570
5571         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5572                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5573                         CSTORM_STATUS_BLOCK_SIZE);
5574         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5575                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5576                         CSTORM_SYNC_BLOCK_SIZE);
5577 }
5578
5579 /* helper:  writes SP SB data to FW */
5580 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5581                 struct hc_sp_status_block_data *sp_sb_data)
5582 {
5583         int func = BP_FUNC(bp);
5584         int i;
5585         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5586                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5587                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5588                         i*sizeof(u32),
5589                         *((u32 *)sp_sb_data + i));
5590 }
5591
5592 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5593 {
5594         int func = BP_FUNC(bp);
5595         struct hc_sp_status_block_data sp_sb_data;
5596         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5597
5598         sp_sb_data.state = SB_DISABLED;
5599         sp_sb_data.p_func.vf_valid = false;
5600
5601         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5602
5603         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5604                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5605                         CSTORM_SP_STATUS_BLOCK_SIZE);
5606         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5607                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5608                         CSTORM_SP_SYNC_BLOCK_SIZE);
5609 }
5610
5611 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5612                                            int igu_sb_id, int igu_seg_id)
5613 {
5614         hc_sm->igu_sb_id = igu_sb_id;
5615         hc_sm->igu_seg_id = igu_seg_id;
5616         hc_sm->timer_value = 0xFF;
5617         hc_sm->time_to_expire = 0xFFFFFFFF;
5618 }
5619
5620 /* allocates state machine ids. */
5621 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5622 {
5623         /* zero out state machine indices */
5624         /* rx indices */
5625         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5626
5627         /* tx indices */
5628         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5629         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5630         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5631         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5632
5633         /* map indices */
5634         /* rx indices */
5635         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5636                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5637
5638         /* tx indices */
5639         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5640                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5641         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5642                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5643         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5644                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5645         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5646                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5647 }
5648
5649 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5650                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5651 {
5652         int igu_seg_id;
5653
5654         struct hc_status_block_data_e2 sb_data_e2;
5655         struct hc_status_block_data_e1x sb_data_e1x;
5656         struct hc_status_block_sm  *hc_sm_p;
5657         int data_size;
5658         u32 *sb_data_p;
5659
5660         if (CHIP_INT_MODE_IS_BC(bp))
5661                 igu_seg_id = HC_SEG_ACCESS_NORM;
5662         else
5663                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5664
5665         bnx2x_zero_fp_sb(bp, fw_sb_id);
5666
5667         if (!CHIP_IS_E1x(bp)) {
5668                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5669                 sb_data_e2.common.state = SB_ENABLED;
5670                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5671                 sb_data_e2.common.p_func.vf_id = vfid;
5672                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5673                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5674                 sb_data_e2.common.same_igu_sb_1b = true;
5675                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5676                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5677                 hc_sm_p = sb_data_e2.common.state_machine;
5678                 sb_data_p = (u32 *)&sb_data_e2;
5679                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5680                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5681         } else {
5682                 memset(&sb_data_e1x, 0,
5683                        sizeof(struct hc_status_block_data_e1x));
5684                 sb_data_e1x.common.state = SB_ENABLED;
5685                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5686                 sb_data_e1x.common.p_func.vf_id = 0xff;
5687                 sb_data_e1x.common.p_func.vf_valid = false;
5688                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5689                 sb_data_e1x.common.same_igu_sb_1b = true;
5690                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5691                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5692                 hc_sm_p = sb_data_e1x.common.state_machine;
5693                 sb_data_p = (u32 *)&sb_data_e1x;
5694                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5695                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5696         }
5697
5698         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5699                                        igu_sb_id, igu_seg_id);
5700         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5701                                        igu_sb_id, igu_seg_id);
5702
5703         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5704
5705         /* write indices to HW - PCI guarantees endianity of regpairs */
5706         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5707 }
5708
5709 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5710                                      u16 tx_usec, u16 rx_usec)
5711 {
5712         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5713                                     false, rx_usec);
5714         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5715                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5716                                        tx_usec);
5717         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5718                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5719                                        tx_usec);
5720         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5721                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5722                                        tx_usec);
5723 }
5724
5725 static void bnx2x_init_def_sb(struct bnx2x *bp)
5726 {
5727         struct host_sp_status_block *def_sb = bp->def_status_blk;
5728         dma_addr_t mapping = bp->def_status_blk_mapping;
5729         int igu_sp_sb_index;
5730         int igu_seg_id;
5731         int port = BP_PORT(bp);
5732         int func = BP_FUNC(bp);
5733         int reg_offset, reg_offset_en5;
5734         u64 section;
5735         int index;
5736         struct hc_sp_status_block_data sp_sb_data;
5737         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5738
5739         if (CHIP_INT_MODE_IS_BC(bp)) {
5740                 igu_sp_sb_index = DEF_SB_IGU_ID;
5741                 igu_seg_id = HC_SEG_ACCESS_DEF;
5742         } else {
5743                 igu_sp_sb_index = bp->igu_dsb_id;
5744                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5745         }
5746
5747         /* ATTN */
5748         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5749                                             atten_status_block);
5750         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5751
5752         bp->attn_state = 0;
5753
5754         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5755                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5756         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5757                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5758         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5759                 int sindex;
5760                 /* take care of sig[0]..sig[4] */
5761                 for (sindex = 0; sindex < 4; sindex++)
5762                         bp->attn_group[index].sig[sindex] =
5763                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5764
5765                 if (!CHIP_IS_E1x(bp))
5766                         /*
5767                          * enable5 is separate from the rest of the registers,
5768                          * and therefore the address skip is 4
5769                          * and not 16 between the different groups
5770                          */
5771                         bp->attn_group[index].sig[4] = REG_RD(bp,
5772                                         reg_offset_en5 + 0x4*index);
5773                 else
5774                         bp->attn_group[index].sig[4] = 0;
5775         }
5776
5777         if (bp->common.int_block == INT_BLOCK_HC) {
5778                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5779                                      HC_REG_ATTN_MSG0_ADDR_L);
5780
5781                 REG_WR(bp, reg_offset, U64_LO(section));
5782                 REG_WR(bp, reg_offset + 4, U64_HI(section));
5783         } else if (!CHIP_IS_E1x(bp)) {
5784                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5785                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5786         }
5787
5788         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5789                                             sp_sb);
5790
5791         bnx2x_zero_sp_sb(bp);
5792
5793         /* PCI guarantees endianity of regpairs */
5794         sp_sb_data.state                = SB_ENABLED;
5795         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
5796         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
5797         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
5798         sp_sb_data.igu_seg_id           = igu_seg_id;
5799         sp_sb_data.p_func.pf_id         = func;
5800         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
5801         sp_sb_data.p_func.vf_id         = 0xff;
5802
5803         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5804
5805         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5806 }
5807
5808 void bnx2x_update_coalesce(struct bnx2x *bp)
5809 {
5810         int i;
5811
5812         for_each_eth_queue(bp, i)
5813                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5814                                          bp->tx_ticks, bp->rx_ticks);
5815 }
5816
5817 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5818 {
5819         spin_lock_init(&bp->spq_lock);
5820         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5821
5822         bp->spq_prod_idx = 0;
5823         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5824         bp->spq_prod_bd = bp->spq;
5825         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5826 }
5827
5828 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5829 {
5830         int i;
5831         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5832                 union event_ring_elem *elem =
5833                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5834
5835                 elem->next_page.addr.hi =
5836                         cpu_to_le32(U64_HI(bp->eq_mapping +
5837                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5838                 elem->next_page.addr.lo =
5839                         cpu_to_le32(U64_LO(bp->eq_mapping +
5840                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5841         }
5842         bp->eq_cons = 0;
5843         bp->eq_prod = NUM_EQ_DESC;
5844         bp->eq_cons_sb = BNX2X_EQ_INDEX;
5845         /* we want a warning message before it gets wrought... */
5846         atomic_set(&bp->eq_spq_left,
5847                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5848 }
5849
5850 /* called with netif_addr_lock_bh() */
5851 int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5852                         unsigned long rx_mode_flags,
5853                         unsigned long rx_accept_flags,
5854                         unsigned long tx_accept_flags,
5855                         unsigned long ramrod_flags)
5856 {
5857         struct bnx2x_rx_mode_ramrod_params ramrod_param;
5858         int rc;
5859
5860         memset(&ramrod_param, 0, sizeof(ramrod_param));
5861
5862         /* Prepare ramrod parameters */
5863         ramrod_param.cid = 0;
5864         ramrod_param.cl_id = cl_id;
5865         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5866         ramrod_param.func_id = BP_FUNC(bp);
5867
5868         ramrod_param.pstate = &bp->sp_state;
5869         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5870
5871         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5872         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5873
5874         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5875
5876         ramrod_param.ramrod_flags = ramrod_flags;
5877         ramrod_param.rx_mode_flags = rx_mode_flags;
5878
5879         ramrod_param.rx_accept_flags = rx_accept_flags;
5880         ramrod_param.tx_accept_flags = tx_accept_flags;
5881
5882         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5883         if (rc < 0) {
5884                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5885                 return rc;
5886         }
5887
5888         return 0;
5889 }
5890
5891 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
5892                                    unsigned long *rx_accept_flags,
5893                                    unsigned long *tx_accept_flags)
5894 {
5895         /* Clear the flags first */
5896         *rx_accept_flags = 0;
5897         *tx_accept_flags = 0;
5898
5899         switch (rx_mode) {
5900         case BNX2X_RX_MODE_NONE:
5901                 /*
5902                  * 'drop all' supersedes any accept flags that may have been
5903                  * passed to the function.
5904                  */
5905                 break;
5906         case BNX2X_RX_MODE_NORMAL:
5907                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5908                 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
5909                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5910
5911                 /* internal switching mode */
5912                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5913                 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
5914                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5915
5916                 break;
5917         case BNX2X_RX_MODE_ALLMULTI:
5918                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5919                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5920                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5921
5922                 /* internal switching mode */
5923                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5924                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5925                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5926
5927                 break;
5928         case BNX2X_RX_MODE_PROMISC:
5929                 /* According to definition of SI mode, iface in promisc mode
5930                  * should receive matched and unmatched (in resolution of port)
5931                  * unicast packets.
5932                  */
5933                 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
5934                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5935                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5936                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5937
5938                 /* internal switching mode */
5939                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5940                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5941
5942                 if (IS_MF_SI(bp))
5943                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
5944                 else
5945                         __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5946
5947                 break;
5948         default:
5949                 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
5950                 return -EINVAL;
5951         }
5952
5953         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
5954         if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5955                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
5956                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
5957         }
5958
5959         return 0;
5960 }
5961
5962 /* called with netif_addr_lock_bh() */
5963 int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5964 {
5965         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5966         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5967         int rc;
5968
5969         if (!NO_FCOE(bp))
5970                 /* Configure rx_mode of FCoE Queue */
5971                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5972
5973         rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
5974                                      &tx_accept_flags);
5975         if (rc)
5976                 return rc;
5977
5978         __set_bit(RAMROD_RX, &ramrod_flags);
5979         __set_bit(RAMROD_TX, &ramrod_flags);
5980
5981         return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
5982                                    rx_accept_flags, tx_accept_flags,
5983                                    ramrod_flags);
5984 }
5985
5986 static void bnx2x_init_internal_common(struct bnx2x *bp)
5987 {
5988         int i;
5989
5990         if (IS_MF_SI(bp))
5991                 /*
5992                  * In switch independent mode, the TSTORM needs to accept
5993                  * packets that failed classification, since approximate match
5994                  * mac addresses aren't written to NIG LLH
5995                  */
5996                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5997                             TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5998         else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5999                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
6000                             TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
6001
6002         /* Zero this manually as its initialization is
6003            currently missing in the initTool */
6004         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6005                 REG_WR(bp, BAR_USTRORM_INTMEM +
6006                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
6007         if (!CHIP_IS_E1x(bp)) {
6008                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6009                         CHIP_INT_MODE_IS_BC(bp) ?
6010                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6011         }
6012 }
6013
6014 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6015 {
6016         switch (load_code) {
6017         case FW_MSG_CODE_DRV_LOAD_COMMON:
6018         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6019                 bnx2x_init_internal_common(bp);
6020                 /* no break */
6021
6022         case FW_MSG_CODE_DRV_LOAD_PORT:
6023                 /* nothing to do */
6024                 /* no break */
6025
6026         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6027                 /* internal memory per function is
6028                    initialized inside bnx2x_pf_init */
6029                 break;
6030
6031         default:
6032                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6033                 break;
6034         }
6035 }
6036
6037 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6038 {
6039         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6040 }
6041
6042 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6043 {
6044         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6045 }
6046
6047 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6048 {
6049         if (CHIP_IS_E1x(fp->bp))
6050                 return BP_L_ID(fp->bp) + fp->index;
6051         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
6052                 return bnx2x_fp_igu_sb_id(fp);
6053 }
6054
6055 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6056 {
6057         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6058         u8 cos;
6059         unsigned long q_type = 0;
6060         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6061         fp->rx_queue = fp_idx;
6062         fp->cid = fp_idx;
6063         fp->cl_id = bnx2x_fp_cl_id(fp);
6064         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6065         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6066         /* qZone id equals to FW (per path) client id */
6067         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
6068
6069         /* init shortcut */
6070         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6071
6072         /* Setup SB indices */
6073         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6074
6075         /* Configure Queue State object */
6076         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6077         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6078
6079         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6080
6081         /* init tx data */
6082         for_each_cos_in_tx_queue(fp, cos) {
6083                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6084                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6085                                   FP_COS_TO_TXQ(fp, cos, bp),
6086                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
6087                 cids[cos] = fp->txdata_ptr[cos]->cid;
6088         }
6089
6090         /* nothing more for vf to do here */
6091         if (IS_VF(bp))
6092                 return;
6093
6094         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6095                       fp->fw_sb_id, fp->igu_sb_id);
6096         bnx2x_update_fpsb_idx(fp);
6097         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6098                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6099                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6100
6101         /**
6102          * Configure classification DBs: Always enable Tx switching
6103          */
6104         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6105
6106         DP(NETIF_MSG_IFUP,
6107            "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
6108            fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6109            fp->igu_sb_id);
6110 }
6111
6112 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6113 {
6114         int i;
6115
6116         for (i = 1; i <= NUM_TX_RINGS; i++) {
6117                 struct eth_tx_next_bd *tx_next_bd =
6118                         &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6119
6120                 tx_next_bd->addr_hi =
6121                         cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6122                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6123                 tx_next_bd->addr_lo =
6124                         cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6125                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6126         }
6127
6128         *txdata->tx_cons_sb = cpu_to_le16(0);
6129
6130         SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6131         txdata->tx_db.data.zero_fill1 = 0;
6132         txdata->tx_db.data.prod = 0;
6133
6134         txdata->tx_pkt_prod = 0;
6135         txdata->tx_pkt_cons = 0;
6136         txdata->tx_bd_prod = 0;
6137         txdata->tx_bd_cons = 0;
6138         txdata->tx_pkt = 0;
6139 }
6140
6141 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6142 {
6143         int i;
6144
6145         for_each_tx_queue_cnic(bp, i)
6146                 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6147 }
6148
6149 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6150 {
6151         int i;
6152         u8 cos;
6153
6154         for_each_eth_queue(bp, i)
6155                 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6156                         bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6157 }
6158
6159 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6160 {
6161         if (!NO_FCOE(bp))
6162                 bnx2x_init_fcoe_fp(bp);
6163
6164         bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6165                       BNX2X_VF_ID_INVALID, false,
6166                       bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6167
6168         /* ensure status block indices were read */
6169         rmb();
6170         bnx2x_init_rx_rings_cnic(bp);
6171         bnx2x_init_tx_rings_cnic(bp);
6172
6173         /* flush all */
6174         mb();
6175         mmiowb();
6176 }
6177
6178 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6179 {
6180         int i;
6181
6182         /* Setup NIC internals and enable interrupts */
6183         for_each_eth_queue(bp, i)
6184                 bnx2x_init_eth_fp(bp, i);
6185
6186         /* ensure status block indices were read */
6187         rmb();
6188         bnx2x_init_rx_rings(bp);
6189         bnx2x_init_tx_rings(bp);
6190
6191         if (IS_PF(bp)) {
6192                 /* Initialize MOD_ABS interrupts */
6193                 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6194                                        bp->common.shmem_base,
6195                                        bp->common.shmem2_base, BP_PORT(bp));
6196
6197                 /* initialize the default status block and sp ring */
6198                 bnx2x_init_def_sb(bp);
6199                 bnx2x_update_dsb_idx(bp);
6200                 bnx2x_init_sp_ring(bp);
6201         } else {
6202                 bnx2x_memset_stats(bp);
6203         }
6204 }
6205
6206 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6207 {
6208         bnx2x_init_eq_ring(bp);
6209         bnx2x_init_internal(bp, load_code);
6210         bnx2x_pf_init(bp);
6211         bnx2x_stats_init(bp);
6212
6213         /* flush all before enabling interrupts */
6214         mb();
6215         mmiowb();
6216
6217         bnx2x_int_enable(bp);
6218
6219         /* Check for SPIO5 */
6220         bnx2x_attn_int_deasserted0(bp,
6221                 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6222                                    AEU_INPUTS_ATTN_BITS_SPIO5);
6223 }
6224
6225 /* gzip service functions */
6226 static int bnx2x_gunzip_init(struct bnx2x *bp)
6227 {
6228         bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6229                                             &bp->gunzip_mapping, GFP_KERNEL);
6230         if (bp->gunzip_buf  == NULL)
6231                 goto gunzip_nomem1;
6232
6233         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6234         if (bp->strm  == NULL)
6235                 goto gunzip_nomem2;
6236
6237         bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6238         if (bp->strm->workspace == NULL)
6239                 goto gunzip_nomem3;
6240
6241         return 0;
6242
6243 gunzip_nomem3:
6244         kfree(bp->strm);
6245         bp->strm = NULL;
6246
6247 gunzip_nomem2:
6248         dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6249                           bp->gunzip_mapping);
6250         bp->gunzip_buf = NULL;
6251
6252 gunzip_nomem1:
6253         BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6254         return -ENOMEM;
6255 }
6256
6257 static void bnx2x_gunzip_end(struct bnx2x *bp)
6258 {
6259         if (bp->strm) {
6260                 vfree(bp->strm->workspace);
6261                 kfree(bp->strm);
6262                 bp->strm = NULL;
6263         }
6264
6265         if (bp->gunzip_buf) {
6266                 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6267                                   bp->gunzip_mapping);
6268                 bp->gunzip_buf = NULL;
6269         }
6270 }
6271
6272 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6273 {
6274         int n, rc;
6275
6276         /* check gzip header */
6277         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6278                 BNX2X_ERR("Bad gzip header\n");
6279                 return -EINVAL;
6280         }
6281
6282         n = 10;
6283
6284 #define FNAME                           0x8
6285
6286         if (zbuf[3] & FNAME)
6287                 while ((zbuf[n++] != 0) && (n < len));
6288
6289         bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6290         bp->strm->avail_in = len - n;
6291         bp->strm->next_out = bp->gunzip_buf;
6292         bp->strm->avail_out = FW_BUF_SIZE;
6293
6294         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6295         if (rc != Z_OK)
6296                 return rc;
6297
6298         rc = zlib_inflate(bp->strm, Z_FINISH);
6299         if ((rc != Z_OK) && (rc != Z_STREAM_END))
6300                 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6301                            bp->strm->msg);
6302
6303         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6304         if (bp->gunzip_outlen & 0x3)
6305                 netdev_err(bp->dev,
6306                            "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6307                                 bp->gunzip_outlen);
6308         bp->gunzip_outlen >>= 2;
6309
6310         zlib_inflateEnd(bp->strm);
6311
6312         if (rc == Z_STREAM_END)
6313                 return 0;
6314
6315         return rc;
6316 }
6317
6318 /* nic load/unload */
6319
6320 /*
6321  * General service functions
6322  */
6323
6324 /* send a NIG loopback debug packet */
6325 static void bnx2x_lb_pckt(struct bnx2x *bp)
6326 {
6327         u32 wb_write[3];
6328
6329         /* Ethernet source and destination addresses */
6330         wb_write[0] = 0x55555555;
6331         wb_write[1] = 0x55555555;
6332         wb_write[2] = 0x20;             /* SOP */
6333         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6334
6335         /* NON-IP protocol */
6336         wb_write[0] = 0x09000000;
6337         wb_write[1] = 0x55555555;
6338         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
6339         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6340 }
6341
6342 /* some of the internal memories
6343  * are not directly readable from the driver
6344  * to test them we send debug packets
6345  */
6346 static int bnx2x_int_mem_test(struct bnx2x *bp)
6347 {
6348         int factor;
6349         int count, i;
6350         u32 val = 0;
6351
6352         if (CHIP_REV_IS_FPGA(bp))
6353                 factor = 120;
6354         else if (CHIP_REV_IS_EMUL(bp))
6355                 factor = 200;
6356         else
6357                 factor = 1;
6358
6359         /* Disable inputs of parser neighbor blocks */
6360         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6361         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6362         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6363         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6364
6365         /*  Write 0 to parser credits for CFC search request */
6366         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6367
6368         /* send Ethernet packet */
6369         bnx2x_lb_pckt(bp);
6370
6371         /* TODO do i reset NIG statistic? */
6372         /* Wait until NIG register shows 1 packet of size 0x10 */
6373         count = 1000 * factor;
6374         while (count) {
6375
6376                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6377                 val = *bnx2x_sp(bp, wb_data[0]);
6378                 if (val == 0x10)
6379                         break;
6380
6381                 usleep_range(10000, 20000);
6382                 count--;
6383         }
6384         if (val != 0x10) {
6385                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6386                 return -1;
6387         }
6388
6389         /* Wait until PRS register shows 1 packet */
6390         count = 1000 * factor;
6391         while (count) {
6392                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6393                 if (val == 1)
6394                         break;
6395
6396                 usleep_range(10000, 20000);
6397                 count--;
6398         }
6399         if (val != 0x1) {
6400                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6401                 return -2;
6402         }
6403
6404         /* Reset and init BRB, PRS */
6405         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6406         msleep(50);
6407         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6408         msleep(50);
6409         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6410         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6411
6412         DP(NETIF_MSG_HW, "part2\n");
6413
6414         /* Disable inputs of parser neighbor blocks */
6415         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6416         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6417         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6418         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6419
6420         /* Write 0 to parser credits for CFC search request */
6421         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6422
6423         /* send 10 Ethernet packets */
6424         for (i = 0; i < 10; i++)
6425                 bnx2x_lb_pckt(bp);
6426
6427         /* Wait until NIG register shows 10 + 1
6428            packets of size 11*0x10 = 0xb0 */
6429         count = 1000 * factor;
6430         while (count) {
6431
6432                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6433                 val = *bnx2x_sp(bp, wb_data[0]);
6434                 if (val == 0xb0)
6435                         break;
6436
6437                 usleep_range(10000, 20000);
6438                 count--;
6439         }
6440         if (val != 0xb0) {
6441                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6442                 return -3;
6443         }
6444
6445         /* Wait until PRS register shows 2 packets */
6446         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6447         if (val != 2)
6448                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6449
6450         /* Write 1 to parser credits for CFC search request */
6451         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6452
6453         /* Wait until PRS register shows 3 packets */
6454         msleep(10 * factor);
6455         /* Wait until NIG register shows 1 packet of size 0x10 */
6456         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6457         if (val != 3)
6458                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6459
6460         /* clear NIG EOP FIFO */
6461         for (i = 0; i < 11; i++)
6462                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6463         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6464         if (val != 1) {
6465                 BNX2X_ERR("clear of NIG failed\n");
6466                 return -4;
6467         }
6468
6469         /* Reset and init BRB, PRS, NIG */
6470         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6471         msleep(50);
6472         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6473         msleep(50);
6474         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6475         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6476         if (!CNIC_SUPPORT(bp))
6477                 /* set NIC mode */
6478                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6479
6480         /* Enable inputs of parser neighbor blocks */
6481         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6482         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6483         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6484         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6485
6486         DP(NETIF_MSG_HW, "done\n");
6487
6488         return 0; /* OK */
6489 }
6490
6491 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6492 {
6493         u32 val;
6494
6495         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6496         if (!CHIP_IS_E1x(bp))
6497                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6498         else
6499                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6500         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6501         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6502         /*
6503          * mask read length error interrupts in brb for parser
6504          * (parsing unit and 'checksum and crc' unit)
6505          * these errors are legal (PU reads fixed length and CAC can cause
6506          * read length error on truncated packets)
6507          */
6508         REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6509         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6510         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6511         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6512         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6513         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6514 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6515 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6516         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6517         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6518         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6519 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6520 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6521         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6522         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6523         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6524         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6525 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6526 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6527
6528         val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT  |
6529                 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6530                 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6531         if (!CHIP_IS_E1x(bp))
6532                 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6533                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6534         REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6535
6536         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6537         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6538         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6539 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6540
6541         if (!CHIP_IS_E1x(bp))
6542                 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6543                 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6544
6545         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6546         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6547 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6548         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
6549 }
6550
6551 static void bnx2x_reset_common(struct bnx2x *bp)
6552 {
6553         u32 val = 0x1400;
6554
6555         /* reset_common */
6556         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6557                0xd3ffff7f);
6558
6559         if (CHIP_IS_E3(bp)) {
6560                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6561                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6562         }
6563
6564         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6565 }
6566
6567 static void bnx2x_setup_dmae(struct bnx2x *bp)
6568 {
6569         bp->dmae_ready = 0;
6570         spin_lock_init(&bp->dmae_lock);
6571 }
6572
6573 static void bnx2x_init_pxp(struct bnx2x *bp)
6574 {
6575         u16 devctl;
6576         int r_order, w_order;
6577
6578         pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6579         DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6580         w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6581         if (bp->mrrs == -1)
6582                 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6583         else {
6584                 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6585                 r_order = bp->mrrs;
6586         }
6587
6588         bnx2x_init_pxp_arb(bp, r_order, w_order);
6589 }
6590
6591 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6592 {
6593         int is_required;
6594         u32 val;
6595         int port;
6596
6597         if (BP_NOMCP(bp))
6598                 return;
6599
6600         is_required = 0;
6601         val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6602               SHARED_HW_CFG_FAN_FAILURE_MASK;
6603
6604         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6605                 is_required = 1;
6606
6607         /*
6608          * The fan failure mechanism is usually related to the PHY type since
6609          * the power consumption of the board is affected by the PHY. Currently,
6610          * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6611          */
6612         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6613                 for (port = PORT_0; port < PORT_MAX; port++) {
6614                         is_required |=
6615                                 bnx2x_fan_failure_det_req(
6616                                         bp,
6617                                         bp->common.shmem_base,
6618                                         bp->common.shmem2_base,
6619                                         port);
6620                 }
6621
6622         DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6623
6624         if (is_required == 0)
6625                 return;
6626
6627         /* Fan failure is indicated by SPIO 5 */
6628         bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6629
6630         /* set to active low mode */
6631         val = REG_RD(bp, MISC_REG_SPIO_INT);
6632         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6633         REG_WR(bp, MISC_REG_SPIO_INT, val);
6634
6635         /* enable interrupt to signal the IGU */
6636         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6637         val |= MISC_SPIO_SPIO5;
6638         REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6639 }
6640
6641 void bnx2x_pf_disable(struct bnx2x *bp)
6642 {
6643         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6644         val &= ~IGU_PF_CONF_FUNC_EN;
6645
6646         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6647         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6648         REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6649 }
6650
6651 static void bnx2x__common_init_phy(struct bnx2x *bp)
6652 {
6653         u32 shmem_base[2], shmem2_base[2];
6654         /* Avoid common init in case MFW supports LFA */
6655         if (SHMEM2_RD(bp, size) >
6656             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6657                 return;
6658         shmem_base[0] =  bp->common.shmem_base;
6659         shmem2_base[0] = bp->common.shmem2_base;
6660         if (!CHIP_IS_E1x(bp)) {
6661                 shmem_base[1] =
6662                         SHMEM2_RD(bp, other_shmem_base_addr);
6663                 shmem2_base[1] =
6664                         SHMEM2_RD(bp, other_shmem2_base_addr);
6665         }
6666         bnx2x_acquire_phy_lock(bp);
6667         bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6668                               bp->common.chip_id);
6669         bnx2x_release_phy_lock(bp);
6670 }
6671
6672 /**
6673  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6674  *
6675  * @bp:         driver handle
6676  */
6677 static int bnx2x_init_hw_common(struct bnx2x *bp)
6678 {
6679         u32 val;
6680
6681         DP(NETIF_MSG_HW, "starting common init  func %d\n", BP_ABS_FUNC(bp));
6682
6683         /*
6684          * take the RESET lock to protect undi_unload flow from accessing
6685          * registers while we're resetting the chip
6686          */
6687         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6688
6689         bnx2x_reset_common(bp);
6690         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6691
6692         val = 0xfffc;
6693         if (CHIP_IS_E3(bp)) {
6694                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6695                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6696         }
6697         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6698
6699         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6700
6701         bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6702
6703         if (!CHIP_IS_E1x(bp)) {
6704                 u8 abs_func_id;
6705
6706                 /**
6707                  * 4-port mode or 2-port mode we need to turn of master-enable
6708                  * for everyone, after that, turn it back on for self.
6709                  * so, we disregard multi-function or not, and always disable
6710                  * for all functions on the given path, this means 0,2,4,6 for
6711                  * path 0 and 1,3,5,7 for path 1
6712                  */
6713                 for (abs_func_id = BP_PATH(bp);
6714                      abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6715                         if (abs_func_id == BP_ABS_FUNC(bp)) {
6716                                 REG_WR(bp,
6717                                     PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6718                                     1);
6719                                 continue;
6720                         }
6721
6722                         bnx2x_pretend_func(bp, abs_func_id);
6723                         /* clear pf enable */
6724                         bnx2x_pf_disable(bp);
6725                         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6726                 }
6727         }
6728
6729         bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6730         if (CHIP_IS_E1(bp)) {
6731                 /* enable HW interrupt from PXP on USDM overflow
6732                    bit 16 on INT_MASK_0 */
6733                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6734         }
6735
6736         bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6737         bnx2x_init_pxp(bp);
6738
6739 #ifdef __BIG_ENDIAN
6740         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6741         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6742         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6743         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6744         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
6745         /* make sure this value is 0 */
6746         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6747
6748 /*      REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6749         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6750         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6751         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6752         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
6753 #endif
6754
6755         bnx2x_ilt_init_page_size(bp, INITOP_SET);
6756
6757         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6758                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6759
6760         /* let the HW do it's magic ... */
6761         msleep(100);
6762         /* finish PXP init */
6763         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6764         if (val != 1) {
6765                 BNX2X_ERR("PXP2 CFG failed\n");
6766                 return -EBUSY;
6767         }
6768         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6769         if (val != 1) {
6770                 BNX2X_ERR("PXP2 RD_INIT failed\n");
6771                 return -EBUSY;
6772         }
6773
6774         /* Timers bug workaround E2 only. We need to set the entire ILT to
6775          * have entries with value "0" and valid bit on.
6776          * This needs to be done by the first PF that is loaded in a path
6777          * (i.e. common phase)
6778          */
6779         if (!CHIP_IS_E1x(bp)) {
6780 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6781  * (i.e. vnic3) to start even if it is marked as "scan-off".
6782  * This occurs when a different function (func2,3) is being marked
6783  * as "scan-off". Real-life scenario for example: if a driver is being
6784  * load-unloaded while func6,7 are down. This will cause the timer to access
6785  * the ilt, translate to a logical address and send a request to read/write.
6786  * Since the ilt for the function that is down is not valid, this will cause
6787  * a translation error which is unrecoverable.
6788  * The Workaround is intended to make sure that when this happens nothing fatal
6789  * will occur. The workaround:
6790  *      1.  First PF driver which loads on a path will:
6791  *              a.  After taking the chip out of reset, by using pretend,
6792  *                  it will write "0" to the following registers of
6793  *                  the other vnics.
6794  *                  REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6795  *                  REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6796  *                  REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6797  *                  And for itself it will write '1' to
6798  *                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6799  *                  dmae-operations (writing to pram for example.)
6800  *                  note: can be done for only function 6,7 but cleaner this
6801  *                        way.
6802  *              b.  Write zero+valid to the entire ILT.
6803  *              c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
6804  *                  VNIC3 (of that port). The range allocated will be the
6805  *                  entire ILT. This is needed to prevent  ILT range error.
6806  *      2.  Any PF driver load flow:
6807  *              a.  ILT update with the physical addresses of the allocated
6808  *                  logical pages.
6809  *              b.  Wait 20msec. - note that this timeout is needed to make
6810  *                  sure there are no requests in one of the PXP internal
6811  *                  queues with "old" ILT addresses.
6812  *              c.  PF enable in the PGLC.
6813  *              d.  Clear the was_error of the PF in the PGLC. (could have
6814  *                  occurred while driver was down)
6815  *              e.  PF enable in the CFC (WEAK + STRONG)
6816  *              f.  Timers scan enable
6817  *      3.  PF driver unload flow:
6818  *              a.  Clear the Timers scan_en.
6819  *              b.  Polling for scan_on=0 for that PF.
6820  *              c.  Clear the PF enable bit in the PXP.
6821  *              d.  Clear the PF enable in the CFC (WEAK + STRONG)
6822  *              e.  Write zero+valid to all ILT entries (The valid bit must
6823  *                  stay set)
6824  *              f.  If this is VNIC 3 of a port then also init
6825  *                  first_timers_ilt_entry to zero and last_timers_ilt_entry
6826  *                  to the last entry in the ILT.
6827  *
6828  *      Notes:
6829  *      Currently the PF error in the PGLC is non recoverable.
6830  *      In the future the there will be a recovery routine for this error.
6831  *      Currently attention is masked.
6832  *      Having an MCP lock on the load/unload process does not guarantee that
6833  *      there is no Timer disable during Func6/7 enable. This is because the
6834  *      Timers scan is currently being cleared by the MCP on FLR.
6835  *      Step 2.d can be done only for PF6/7 and the driver can also check if
6836  *      there is error before clearing it. But the flow above is simpler and
6837  *      more general.
6838  *      All ILT entries are written by zero+valid and not just PF6/7
6839  *      ILT entries since in the future the ILT entries allocation for
6840  *      PF-s might be dynamic.
6841  */
6842                 struct ilt_client_info ilt_cli;
6843                 struct bnx2x_ilt ilt;
6844                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6845                 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6846
6847                 /* initialize dummy TM client */
6848                 ilt_cli.start = 0;
6849                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6850                 ilt_cli.client_num = ILT_CLIENT_TM;
6851
6852                 /* Step 1: set zeroes to all ilt page entries with valid bit on
6853                  * Step 2: set the timers first/last ilt entry to point
6854                  * to the entire range to prevent ILT range error for 3rd/4th
6855                  * vnic (this code assumes existence of the vnic)
6856                  *
6857                  * both steps performed by call to bnx2x_ilt_client_init_op()
6858                  * with dummy TM client
6859                  *
6860                  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6861                  * and his brother are split registers
6862                  */
6863                 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6864                 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6865                 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6866
6867                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6868                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6869                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6870         }
6871
6872         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6873         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6874
6875         if (!CHIP_IS_E1x(bp)) {
6876                 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6877                                 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6878                 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6879
6880                 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6881
6882                 /* let the HW do it's magic ... */
6883                 do {
6884                         msleep(200);
6885                         val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6886                 } while (factor-- && (val != 1));
6887
6888                 if (val != 1) {
6889                         BNX2X_ERR("ATC_INIT failed\n");
6890                         return -EBUSY;
6891                 }
6892         }
6893
6894         bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6895
6896         bnx2x_iov_init_dmae(bp);
6897
6898         /* clean the DMAE memory */
6899         bp->dmae_ready = 1;
6900         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6901
6902         bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6903
6904         bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6905
6906         bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6907
6908         bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6909
6910         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6911         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6912         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6913         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6914
6915         bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6916
6917         /* QM queues pointers table */
6918         bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6919
6920         /* soft reset pulse */
6921         REG_WR(bp, QM_REG_SOFT_RESET, 1);
6922         REG_WR(bp, QM_REG_SOFT_RESET, 0);
6923
6924         if (CNIC_SUPPORT(bp))
6925                 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6926
6927         bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6928
6929         if (!CHIP_REV_IS_SLOW(bp))
6930                 /* enable hw interrupt from doorbell Q */
6931                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6932
6933         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6934
6935         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6936         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6937
6938         if (!CHIP_IS_E1(bp))
6939                 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6940
6941         if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
6942                 if (IS_MF_AFEX(bp)) {
6943                         /* configure that VNTag and VLAN headers must be
6944                          * received in afex mode
6945                          */
6946                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
6947                         REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
6948                         REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
6949                         REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
6950                         REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
6951                 } else {
6952                         /* Bit-map indicating which L2 hdrs may appear
6953                          * after the basic Ethernet header
6954                          */
6955                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6956                                bp->path_has_ovlan ? 7 : 6);
6957                 }
6958         }
6959
6960         bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6961         bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6962         bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6963         bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6964
6965         if (!CHIP_IS_E1x(bp)) {
6966                 /* reset VFC memories */
6967                 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6968                            VFC_MEMORIES_RST_REG_CAM_RST |
6969                            VFC_MEMORIES_RST_REG_RAM_RST);
6970                 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6971                            VFC_MEMORIES_RST_REG_CAM_RST |
6972                            VFC_MEMORIES_RST_REG_RAM_RST);
6973
6974                 msleep(20);
6975         }
6976
6977         bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6978         bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6979         bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6980         bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6981
6982         /* sync semi rtc */
6983         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6984                0x80000000);
6985         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6986                0x80000000);
6987
6988         bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6989         bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6990         bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6991
6992         if (!CHIP_IS_E1x(bp)) {
6993                 if (IS_MF_AFEX(bp)) {
6994                         /* configure that VNTag and VLAN headers must be
6995                          * sent in afex mode
6996                          */
6997                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
6998                         REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
6999                         REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7000                         REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7001                         REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7002                 } else {
7003                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7004                                bp->path_has_ovlan ? 7 : 6);
7005                 }
7006         }
7007
7008         REG_WR(bp, SRC_REG_SOFT_RST, 1);
7009
7010         bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7011
7012         if (CNIC_SUPPORT(bp)) {
7013                 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7014                 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7015                 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7016                 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7017                 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7018                 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7019                 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7020                 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7021                 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7022                 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7023         }
7024         REG_WR(bp, SRC_REG_SOFT_RST, 0);
7025
7026         if (sizeof(union cdu_context) != 1024)
7027                 /* we currently assume that a context is 1024 bytes */
7028                 dev_alert(&bp->pdev->dev,
7029                           "please adjust the size of cdu_context(%ld)\n",
7030                           (long)sizeof(union cdu_context));
7031
7032         bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
7033         val = (4 << 24) + (0 << 12) + 1024;
7034         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
7035
7036         bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
7037         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
7038         /* enable context validation interrupt from CFC */
7039         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7040
7041         /* set the thresholds to prevent CFC/CDU race */
7042         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
7043
7044         bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
7045
7046         if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
7047                 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7048
7049         bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7050         bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7051
7052         /* Reset PCIE errors for debug */
7053         REG_WR(bp, 0x2814, 0xffffffff);
7054         REG_WR(bp, 0x3820, 0xffffffff);
7055
7056         if (!CHIP_IS_E1x(bp)) {
7057                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7058                            (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7059                                 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7060                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7061                            (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7062                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7063                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7064                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7065                            (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7066                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7067                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7068         }
7069
7070         bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7071         if (!CHIP_IS_E1(bp)) {
7072                 /* in E3 this done in per-port section */
7073                 if (!CHIP_IS_E3(bp))
7074                         REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7075         }
7076         if (CHIP_IS_E1H(bp))
7077                 /* not applicable for E2 (and above ...) */
7078                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7079
7080         if (CHIP_REV_IS_SLOW(bp))
7081                 msleep(200);
7082
7083         /* finish CFC init */
7084         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7085         if (val != 1) {
7086                 BNX2X_ERR("CFC LL_INIT failed\n");
7087                 return -EBUSY;
7088         }
7089         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7090         if (val != 1) {
7091                 BNX2X_ERR("CFC AC_INIT failed\n");
7092                 return -EBUSY;
7093         }
7094         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7095         if (val != 1) {
7096                 BNX2X_ERR("CFC CAM_INIT failed\n");
7097                 return -EBUSY;
7098         }
7099         REG_WR(bp, CFC_REG_DEBUG0, 0);
7100
7101         if (CHIP_IS_E1(bp)) {
7102                 /* read NIG statistic
7103                    to see if this is our first up since powerup */
7104                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7105                 val = *bnx2x_sp(bp, wb_data[0]);
7106
7107                 /* do internal memory self test */
7108                 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7109                         BNX2X_ERR("internal mem self test failed\n");
7110                         return -EBUSY;
7111                 }
7112         }
7113
7114         bnx2x_setup_fan_failure_detection(bp);
7115
7116         /* clear PXP2 attentions */
7117         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7118
7119         bnx2x_enable_blocks_attention(bp);
7120         bnx2x_enable_blocks_parity(bp);
7121
7122         if (!BP_NOMCP(bp)) {
7123                 if (CHIP_IS_E1x(bp))
7124                         bnx2x__common_init_phy(bp);
7125         } else
7126                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7127
7128         return 0;
7129 }
7130
7131 /**
7132  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7133  *
7134  * @bp:         driver handle
7135  */
7136 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7137 {
7138         int rc = bnx2x_init_hw_common(bp);
7139
7140         if (rc)
7141                 return rc;
7142
7143         /* In E2 2-PORT mode, same ext phy is used for the two paths */
7144         if (!BP_NOMCP(bp))
7145                 bnx2x__common_init_phy(bp);
7146
7147         return 0;
7148 }
7149
7150 static int bnx2x_init_hw_port(struct bnx2x *bp)
7151 {
7152         int port = BP_PORT(bp);
7153         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7154         u32 low, high;
7155         u32 val, reg;
7156
7157         DP(NETIF_MSG_HW, "starting port init  port %d\n", port);
7158
7159         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7160
7161         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7162         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7163         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7164
7165         /* Timers bug workaround: disables the pf_master bit in pglue at
7166          * common phase, we need to enable it here before any dmae access are
7167          * attempted. Therefore we manually added the enable-master to the
7168          * port phase (it also happens in the function phase)
7169          */
7170         if (!CHIP_IS_E1x(bp))
7171                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7172
7173         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7174         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7175         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7176         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7177
7178         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7179         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7180         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7181         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7182
7183         /* QM cid (connection) count */
7184         bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7185
7186         if (CNIC_SUPPORT(bp)) {
7187                 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7188                 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7189                 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7190         }
7191
7192         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7193
7194         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7195
7196         if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7197
7198                 if (IS_MF(bp))
7199                         low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7200                 else if (bp->dev->mtu > 4096) {
7201                         if (bp->flags & ONE_PORT_FLAG)
7202                                 low = 160;
7203                         else {
7204                                 val = bp->dev->mtu;
7205                                 /* (24*1024 + val*4)/256 */
7206                                 low = 96 + (val/64) +
7207                                                 ((val % 64) ? 1 : 0);
7208                         }
7209                 } else
7210                         low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7211                 high = low + 56;        /* 14*1024/256 */
7212                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7213                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7214         }
7215
7216         if (CHIP_MODE_IS_4_PORT(bp))
7217                 REG_WR(bp, (BP_PORT(bp) ?
7218                             BRB1_REG_MAC_GUARANTIED_1 :
7219                             BRB1_REG_MAC_GUARANTIED_0), 40);
7220
7221         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7222         if (CHIP_IS_E3B0(bp)) {
7223                 if (IS_MF_AFEX(bp)) {
7224                         /* configure headers for AFEX mode */
7225                         REG_WR(bp, BP_PORT(bp) ?
7226                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7227                                PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7228                         REG_WR(bp, BP_PORT(bp) ?
7229                                PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7230                                PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7231                         REG_WR(bp, BP_PORT(bp) ?
7232                                PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7233                                PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7234                 } else {
7235                         /* Ovlan exists only if we are in multi-function +
7236                          * switch-dependent mode, in switch-independent there
7237                          * is no ovlan headers
7238                          */
7239                         REG_WR(bp, BP_PORT(bp) ?
7240                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7241                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7242                                (bp->path_has_ovlan ? 7 : 6));
7243                 }
7244         }
7245
7246         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7247         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7248         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7249         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7250
7251         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7252         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7253         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7254         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7255
7256         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7257         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7258
7259         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7260
7261         if (CHIP_IS_E1x(bp)) {
7262                 /* configure PBF to work without PAUSE mtu 9000 */
7263                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7264
7265                 /* update threshold */
7266                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7267                 /* update init credit */
7268                 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7269
7270                 /* probe changes */
7271                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7272                 udelay(50);
7273                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7274         }
7275
7276         if (CNIC_SUPPORT(bp))
7277                 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7278
7279         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7280         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7281
7282         if (CHIP_IS_E1(bp)) {
7283                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7284                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7285         }
7286         bnx2x_init_block(bp, BLOCK_HC, init_phase);
7287
7288         bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7289
7290         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7291         /* init aeu_mask_attn_func_0/1:
7292          *  - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7293          *  - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7294          *             bits 4-7 are used for "per vn group attention" */
7295         val = IS_MF(bp) ? 0xF7 : 0x7;
7296         /* Enable DCBX attention for all but E1 */
7297         val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7298         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7299
7300         /* SCPAD_PARITY should NOT trigger close the gates */
7301         reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7302         REG_WR(bp, reg,
7303                REG_RD(bp, reg) &
7304                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7305
7306         reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7307         REG_WR(bp, reg,
7308                REG_RD(bp, reg) &
7309                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7310
7311         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7312
7313         if (!CHIP_IS_E1x(bp)) {
7314                 /* Bit-map indicating which L2 hdrs may appear after the
7315                  * basic Ethernet header
7316                  */
7317                 if (IS_MF_AFEX(bp))
7318                         REG_WR(bp, BP_PORT(bp) ?
7319                                NIG_REG_P1_HDRS_AFTER_BASIC :
7320                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7321                 else
7322                         REG_WR(bp, BP_PORT(bp) ?
7323                                NIG_REG_P1_HDRS_AFTER_BASIC :
7324                                NIG_REG_P0_HDRS_AFTER_BASIC,
7325                                IS_MF_SD(bp) ? 7 : 6);
7326
7327                 if (CHIP_IS_E3(bp))
7328                         REG_WR(bp, BP_PORT(bp) ?
7329                                    NIG_REG_LLH1_MF_MODE :
7330                                    NIG_REG_LLH_MF_MODE, IS_MF(bp));
7331         }
7332         if (!CHIP_IS_E3(bp))
7333                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7334
7335         if (!CHIP_IS_E1(bp)) {
7336                 /* 0x2 disable mf_ov, 0x1 enable */
7337                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7338                        (IS_MF_SD(bp) ? 0x1 : 0x2));
7339
7340                 if (!CHIP_IS_E1x(bp)) {
7341                         val = 0;
7342                         switch (bp->mf_mode) {
7343                         case MULTI_FUNCTION_SD:
7344                                 val = 1;
7345                                 break;
7346                         case MULTI_FUNCTION_SI:
7347                         case MULTI_FUNCTION_AFEX:
7348                                 val = 2;
7349                                 break;
7350                         }
7351
7352                         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7353                                                   NIG_REG_LLH0_CLS_TYPE), val);
7354                 }
7355                 {
7356                         REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7357                         REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7358                         REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7359                 }
7360         }
7361
7362         /* If SPIO5 is set to generate interrupts, enable it for this port */
7363         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7364         if (val & MISC_SPIO_SPIO5) {
7365                 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7366                                        MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7367                 val = REG_RD(bp, reg_addr);
7368                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7369                 REG_WR(bp, reg_addr, val);
7370         }
7371
7372         return 0;
7373 }
7374
7375 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7376 {
7377         int reg;
7378         u32 wb_write[2];
7379
7380         if (CHIP_IS_E1(bp))
7381                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7382         else
7383                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7384
7385         wb_write[0] = ONCHIP_ADDR1(addr);
7386         wb_write[1] = ONCHIP_ADDR2(addr);
7387         REG_WR_DMAE(bp, reg, wb_write, 2);
7388 }
7389
7390 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7391 {
7392         u32 data, ctl, cnt = 100;
7393         u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7394         u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7395         u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7396         u32 sb_bit =  1 << (idu_sb_id%32);
7397         u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7398         u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7399
7400         /* Not supported in BC mode */
7401         if (CHIP_INT_MODE_IS_BC(bp))
7402                 return;
7403
7404         data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7405                         << IGU_REGULAR_CLEANUP_TYPE_SHIFT)      |
7406                 IGU_REGULAR_CLEANUP_SET                         |
7407                 IGU_REGULAR_BCLEANUP;
7408
7409         ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT         |
7410               func_encode << IGU_CTRL_REG_FID_SHIFT             |
7411               IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7412
7413         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7414                          data, igu_addr_data);
7415         REG_WR(bp, igu_addr_data, data);
7416         mmiowb();
7417         barrier();
7418         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7419                           ctl, igu_addr_ctl);
7420         REG_WR(bp, igu_addr_ctl, ctl);
7421         mmiowb();
7422         barrier();
7423
7424         /* wait for clean up to finish */
7425         while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7426                 msleep(20);
7427
7428         if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7429                 DP(NETIF_MSG_HW,
7430                    "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7431                           idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7432         }
7433 }
7434
7435 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7436 {
7437         bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7438 }
7439
7440 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7441 {
7442         u32 i, base = FUNC_ILT_BASE(func);
7443         for (i = base; i < base + ILT_PER_FUNC; i++)
7444                 bnx2x_ilt_wr(bp, i, 0);
7445 }
7446
7447 static void bnx2x_init_searcher(struct bnx2x *bp)
7448 {
7449         int port = BP_PORT(bp);
7450         bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7451         /* T1 hash bits value determines the T1 number of entries */
7452         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7453 }
7454
7455 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7456 {
7457         int rc;
7458         struct bnx2x_func_state_params func_params = {NULL};
7459         struct bnx2x_func_switch_update_params *switch_update_params =
7460                 &func_params.params.switch_update;
7461
7462         /* Prepare parameters for function state transitions */
7463         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7464         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7465
7466         func_params.f_obj = &bp->func_obj;
7467         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7468
7469         /* Function parameters */
7470         switch_update_params->suspend = suspend;
7471
7472         rc = bnx2x_func_state_change(bp, &func_params);
7473
7474         return rc;
7475 }
7476
7477 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7478 {
7479         int rc, i, port = BP_PORT(bp);
7480         int vlan_en = 0, mac_en[NUM_MACS];
7481
7482         /* Close input from network */
7483         if (bp->mf_mode == SINGLE_FUNCTION) {
7484                 bnx2x_set_rx_filter(&bp->link_params, 0);
7485         } else {
7486                 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7487                                    NIG_REG_LLH0_FUNC_EN);
7488                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7489                           NIG_REG_LLH0_FUNC_EN, 0);
7490                 for (i = 0; i < NUM_MACS; i++) {
7491                         mac_en[i] = REG_RD(bp, port ?
7492                                              (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7493                                               4 * i) :
7494                                              (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7495                                               4 * i));
7496                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7497                                               4 * i) :
7498                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7499                 }
7500         }
7501
7502         /* Close BMC to host */
7503         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7504                NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7505
7506         /* Suspend Tx switching to the PF. Completion of this ramrod
7507          * further guarantees that all the packets of that PF / child
7508          * VFs in BRB were processed by the Parser, so it is safe to
7509          * change the NIC_MODE register.
7510          */
7511         rc = bnx2x_func_switch_update(bp, 1);
7512         if (rc) {
7513                 BNX2X_ERR("Can't suspend tx-switching!\n");
7514                 return rc;
7515         }
7516
7517         /* Change NIC_MODE register */
7518         REG_WR(bp, PRS_REG_NIC_MODE, 0);
7519
7520         /* Open input from network */
7521         if (bp->mf_mode == SINGLE_FUNCTION) {
7522                 bnx2x_set_rx_filter(&bp->link_params, 1);
7523         } else {
7524                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7525                           NIG_REG_LLH0_FUNC_EN, vlan_en);
7526                 for (i = 0; i < NUM_MACS; i++) {
7527                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7528                                               4 * i) :
7529                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7530                                   mac_en[i]);
7531                 }
7532         }
7533
7534         /* Enable BMC to host */
7535         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7536                NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7537
7538         /* Resume Tx switching to the PF */
7539         rc = bnx2x_func_switch_update(bp, 0);
7540         if (rc) {
7541                 BNX2X_ERR("Can't resume tx-switching!\n");
7542                 return rc;
7543         }
7544
7545         DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7546         return 0;
7547 }
7548
7549 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7550 {
7551         int rc;
7552
7553         bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7554
7555         if (CONFIGURE_NIC_MODE(bp)) {
7556                 /* Configure searcher as part of function hw init */
7557                 bnx2x_init_searcher(bp);
7558
7559                 /* Reset NIC mode */
7560                 rc = bnx2x_reset_nic_mode(bp);
7561                 if (rc)
7562                         BNX2X_ERR("Can't change NIC mode!\n");
7563                 return rc;
7564         }
7565
7566         return 0;
7567 }
7568
7569 static int bnx2x_init_hw_func(struct bnx2x *bp)
7570 {
7571         int port = BP_PORT(bp);
7572         int func = BP_FUNC(bp);
7573         int init_phase = PHASE_PF0 + func;
7574         struct bnx2x_ilt *ilt = BP_ILT(bp);
7575         u16 cdu_ilt_start;
7576         u32 addr, val;
7577         u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7578         int i, main_mem_width, rc;
7579
7580         DP(NETIF_MSG_HW, "starting func init  func %d\n", func);
7581
7582         /* FLR cleanup - hmmm */
7583         if (!CHIP_IS_E1x(bp)) {
7584                 rc = bnx2x_pf_flr_clnup(bp);
7585                 if (rc) {
7586                         bnx2x_fw_dump(bp);
7587                         return rc;
7588                 }
7589         }
7590
7591         /* set MSI reconfigure capability */
7592         if (bp->common.int_block == INT_BLOCK_HC) {
7593                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7594                 val = REG_RD(bp, addr);
7595                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7596                 REG_WR(bp, addr, val);
7597         }
7598
7599         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7600         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7601
7602         ilt = BP_ILT(bp);
7603         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7604
7605         if (IS_SRIOV(bp))
7606                 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7607         cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7608
7609         /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7610          * those of the VFs, so start line should be reset
7611          */
7612         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7613         for (i = 0; i < L2_ILT_LINES(bp); i++) {
7614                 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7615                 ilt->lines[cdu_ilt_start + i].page_mapping =
7616                         bp->context[i].cxt_mapping;
7617                 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7618         }
7619
7620         bnx2x_ilt_init_op(bp, INITOP_SET);
7621
7622         if (!CONFIGURE_NIC_MODE(bp)) {
7623                 bnx2x_init_searcher(bp);
7624                 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7625                 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7626         } else {
7627                 /* Set NIC mode */
7628                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7629                 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
7630         }
7631
7632         if (!CHIP_IS_E1x(bp)) {
7633                 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7634
7635                 /* Turn on a single ISR mode in IGU if driver is going to use
7636                  * INT#x or MSI
7637                  */
7638                 if (!(bp->flags & USING_MSIX_FLAG))
7639                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7640                 /*
7641                  * Timers workaround bug: function init part.
7642                  * Need to wait 20msec after initializing ILT,
7643                  * needed to make sure there are no requests in
7644                  * one of the PXP internal queues with "old" ILT addresses
7645                  */
7646                 msleep(20);
7647                 /*
7648                  * Master enable - Due to WB DMAE writes performed before this
7649                  * register is re-initialized as part of the regular function
7650                  * init
7651                  */
7652                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7653                 /* Enable the function in IGU */
7654                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7655         }
7656
7657         bp->dmae_ready = 1;
7658
7659         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7660
7661         if (!CHIP_IS_E1x(bp))
7662                 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7663
7664         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7665         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7666         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7667         bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7668         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7669         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7670         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7671         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7672         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7673         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7674         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7675         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7676         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7677
7678         if (!CHIP_IS_E1x(bp))
7679                 REG_WR(bp, QM_REG_PF_EN, 1);
7680
7681         if (!CHIP_IS_E1x(bp)) {
7682                 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7683                 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7684                 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7685                 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7686         }
7687         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7688
7689         bnx2x_init_block(bp, BLOCK_TM, init_phase);
7690         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7691         REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
7692
7693         bnx2x_iov_init_dq(bp);
7694
7695         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7696         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7697         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7698         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7699         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7700         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7701         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7702         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7703         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7704         if (!CHIP_IS_E1x(bp))
7705                 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7706
7707         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7708
7709         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7710
7711         if (!CHIP_IS_E1x(bp))
7712                 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7713
7714         if (IS_MF(bp)) {
7715                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7716                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
7717         }
7718
7719         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7720
7721         /* HC init per function */
7722         if (bp->common.int_block == INT_BLOCK_HC) {
7723                 if (CHIP_IS_E1H(bp)) {
7724                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7725
7726                         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7727                         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7728                 }
7729                 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7730
7731         } else {
7732                 int num_segs, sb_idx, prod_offset;
7733
7734                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7735
7736                 if (!CHIP_IS_E1x(bp)) {
7737                         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7738                         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7739                 }
7740
7741                 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7742
7743                 if (!CHIP_IS_E1x(bp)) {
7744                         int dsb_idx = 0;
7745                         /**
7746                          * Producer memory:
7747                          * E2 mode: address 0-135 match to the mapping memory;
7748                          * 136 - PF0 default prod; 137 - PF1 default prod;
7749                          * 138 - PF2 default prod; 139 - PF3 default prod;
7750                          * 140 - PF0 attn prod;    141 - PF1 attn prod;
7751                          * 142 - PF2 attn prod;    143 - PF3 attn prod;
7752                          * 144-147 reserved.
7753                          *
7754                          * E1.5 mode - In backward compatible mode;
7755                          * for non default SB; each even line in the memory
7756                          * holds the U producer and each odd line hold
7757                          * the C producer. The first 128 producers are for
7758                          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7759                          * producers are for the DSB for each PF.
7760                          * Each PF has five segments: (the order inside each
7761                          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7762                          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7763                          * 144-147 attn prods;
7764                          */
7765                         /* non-default-status-blocks */
7766                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7767                                 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7768                         for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7769                                 prod_offset = (bp->igu_base_sb + sb_idx) *
7770                                         num_segs;
7771
7772                                 for (i = 0; i < num_segs; i++) {
7773                                         addr = IGU_REG_PROD_CONS_MEMORY +
7774                                                         (prod_offset + i) * 4;
7775                                         REG_WR(bp, addr, 0);
7776                                 }
7777                                 /* send consumer update with value 0 */
7778                                 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7779                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7780                                 bnx2x_igu_clear_sb(bp,
7781                                                    bp->igu_base_sb + sb_idx);
7782                         }
7783
7784                         /* default-status-blocks */
7785                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7786                                 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7787
7788                         if (CHIP_MODE_IS_4_PORT(bp))
7789                                 dsb_idx = BP_FUNC(bp);
7790                         else
7791                                 dsb_idx = BP_VN(bp);
7792
7793                         prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7794                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
7795                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
7796
7797                         /*
7798                          * igu prods come in chunks of E1HVN_MAX (4) -
7799                          * does not matters what is the current chip mode
7800                          */
7801                         for (i = 0; i < (num_segs * E1HVN_MAX);
7802                              i += E1HVN_MAX) {
7803                                 addr = IGU_REG_PROD_CONS_MEMORY +
7804                                                         (prod_offset + i)*4;
7805                                 REG_WR(bp, addr, 0);
7806                         }
7807                         /* send consumer update with 0 */
7808                         if (CHIP_INT_MODE_IS_BC(bp)) {
7809                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7810                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7811                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7812                                              CSTORM_ID, 0, IGU_INT_NOP, 1);
7813                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7814                                              XSTORM_ID, 0, IGU_INT_NOP, 1);
7815                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7816                                              TSTORM_ID, 0, IGU_INT_NOP, 1);
7817                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7818                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
7819                         } else {
7820                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7821                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7822                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7823                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
7824                         }
7825                         bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7826
7827                         /* !!! These should become driver const once
7828                            rf-tool supports split-68 const */
7829                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
7830                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
7831                         REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7832                         REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7833                         REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
7834                         REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
7835                 }
7836         }
7837
7838         /* Reset PCIE errors for debug */
7839         REG_WR(bp, 0x2114, 0xffffffff);
7840         REG_WR(bp, 0x2120, 0xffffffff);
7841
7842         if (CHIP_IS_E1x(bp)) {
7843                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7844                 main_mem_base = HC_REG_MAIN_MEMORY +
7845                                 BP_PORT(bp) * (main_mem_size * 4);
7846                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7847                 main_mem_width = 8;
7848
7849                 val = REG_RD(bp, main_mem_prty_clr);
7850                 if (val)
7851                         DP(NETIF_MSG_HW,
7852                            "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7853                            val);
7854
7855                 /* Clear "false" parity errors in MSI-X table */
7856                 for (i = main_mem_base;
7857                      i < main_mem_base + main_mem_size * 4;
7858                      i += main_mem_width) {
7859                         bnx2x_read_dmae(bp, i, main_mem_width / 4);
7860                         bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7861                                          i, main_mem_width / 4);
7862                 }
7863                 /* Clear HC parity attention */
7864                 REG_RD(bp, main_mem_prty_clr);
7865         }
7866
7867 #ifdef BNX2X_STOP_ON_ERROR
7868         /* Enable STORMs SP logging */
7869         REG_WR8(bp, BAR_USTRORM_INTMEM +
7870                USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7871         REG_WR8(bp, BAR_TSTRORM_INTMEM +
7872                TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7873         REG_WR8(bp, BAR_CSTRORM_INTMEM +
7874                CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7875         REG_WR8(bp, BAR_XSTRORM_INTMEM +
7876                XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7877 #endif
7878
7879         bnx2x_phy_probe(&bp->link_params);
7880
7881         return 0;
7882 }
7883
7884 void bnx2x_free_mem_cnic(struct bnx2x *bp)
7885 {
7886         bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
7887
7888         if (!CHIP_IS_E1x(bp))
7889                 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7890                                sizeof(struct host_hc_status_block_e2));
7891         else
7892                 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7893                                sizeof(struct host_hc_status_block_e1x));
7894
7895         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7896 }
7897
7898 void bnx2x_free_mem(struct bnx2x *bp)
7899 {
7900         int i;
7901
7902         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7903                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7904
7905         if (IS_VF(bp))
7906                 return;
7907
7908         BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
7909                        sizeof(struct host_sp_status_block));
7910
7911         BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
7912                        sizeof(struct bnx2x_slowpath));
7913
7914         for (i = 0; i < L2_ILT_LINES(bp); i++)
7915                 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7916                                bp->context[i].size);
7917         bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7918
7919         BNX2X_FREE(bp->ilt->lines);
7920
7921         BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
7922
7923         BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7924                        BCM_PAGE_SIZE * NUM_EQ_PAGES);
7925
7926         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7927
7928         bnx2x_iov_free_mem(bp);
7929 }
7930
7931 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
7932 {
7933         if (!CHIP_IS_E1x(bp))
7934                 /* size = the status block + ramrod buffers */
7935                 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7936                                 sizeof(struct host_hc_status_block_e2));
7937         else
7938                 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb,
7939                                 &bp->cnic_sb_mapping,
7940                                 sizeof(struct
7941                                        host_hc_status_block_e1x));
7942
7943         if (CONFIGURE_NIC_MODE(bp) && !bp->t2)
7944                 /* allocate searcher T2 table, as it wasn't allocated before */
7945                 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7946
7947         /* write address to which L5 should insert its values */
7948         bp->cnic_eth_dev.addr_drv_info_to_mcp =
7949                 &bp->slowpath->drv_info_to_mcp;
7950
7951         if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
7952                 goto alloc_mem_err;
7953
7954         return 0;
7955
7956 alloc_mem_err:
7957         bnx2x_free_mem_cnic(bp);
7958         BNX2X_ERR("Can't allocate memory\n");
7959         return -ENOMEM;
7960 }
7961
7962 int bnx2x_alloc_mem(struct bnx2x *bp)
7963 {
7964         int i, allocated, context_size;
7965
7966         if (!CONFIGURE_NIC_MODE(bp) && !bp->t2)
7967                 /* allocate searcher T2 table */
7968                 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7969
7970         BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7971                         sizeof(struct host_sp_status_block));
7972
7973         BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7974                         sizeof(struct bnx2x_slowpath));
7975
7976         /* Allocate memory for CDU context:
7977          * This memory is allocated separately and not in the generic ILT
7978          * functions because CDU differs in few aspects:
7979          * 1. There are multiple entities allocating memory for context -
7980          * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7981          * its own ILT lines.
7982          * 2. Since CDU page-size is not a single 4KB page (which is the case
7983          * for the other ILT clients), to be efficient we want to support
7984          * allocation of sub-page-size in the last entry.
7985          * 3. Context pointers are used by the driver to pass to FW / update
7986          * the context (for the other ILT clients the pointers are used just to
7987          * free the memory during unload).
7988          */
7989         context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
7990
7991         for (i = 0, allocated = 0; allocated < context_size; i++) {
7992                 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
7993                                           (context_size - allocated));
7994                 BNX2X_PCI_ALLOC(bp->context[i].vcxt,
7995                                 &bp->context[i].cxt_mapping,
7996                                 bp->context[i].size);
7997                 allocated += bp->context[i].size;
7998         }
7999         BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
8000
8001         if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8002                 goto alloc_mem_err;
8003
8004         if (bnx2x_iov_alloc_mem(bp))
8005                 goto alloc_mem_err;
8006
8007         /* Slow path ring */
8008         BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
8009
8010         /* EQ */
8011         BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
8012                         BCM_PAGE_SIZE * NUM_EQ_PAGES);
8013
8014         return 0;
8015
8016 alloc_mem_err:
8017         bnx2x_free_mem(bp);
8018         BNX2X_ERR("Can't allocate memory\n");
8019         return -ENOMEM;
8020 }
8021
8022 /*
8023  * Init service functions
8024  */
8025
8026 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8027                       struct bnx2x_vlan_mac_obj *obj, bool set,
8028                       int mac_type, unsigned long *ramrod_flags)
8029 {
8030         int rc;
8031         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8032
8033         memset(&ramrod_param, 0, sizeof(ramrod_param));
8034
8035         /* Fill general parameters */
8036         ramrod_param.vlan_mac_obj = obj;
8037         ramrod_param.ramrod_flags = *ramrod_flags;
8038
8039         /* Fill a user request section if needed */
8040         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8041                 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
8042
8043                 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
8044
8045                 /* Set the command: ADD or DEL */
8046                 if (set)
8047                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8048                 else
8049                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8050         }
8051
8052         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8053
8054         if (rc == -EEXIST) {
8055                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8056                 /* do not treat adding same MAC as error */
8057                 rc = 0;
8058         } else if (rc < 0)
8059                 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8060
8061         return rc;
8062 }
8063
8064 int bnx2x_del_all_macs(struct bnx2x *bp,
8065                        struct bnx2x_vlan_mac_obj *mac_obj,
8066                        int mac_type, bool wait_for_comp)
8067 {
8068         int rc;
8069         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8070
8071         /* Wait for completion of requested */
8072         if (wait_for_comp)
8073                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8074
8075         /* Set the mac type of addresses we want to clear */
8076         __set_bit(mac_type, &vlan_mac_flags);
8077
8078         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8079         if (rc < 0)
8080                 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8081
8082         return rc;
8083 }
8084
8085 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8086 {
8087         if (is_zero_ether_addr(bp->dev->dev_addr) &&
8088             (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
8089                 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
8090                    "Ignoring Zero MAC for STORAGE SD mode\n");
8091                 return 0;
8092         }
8093
8094         if (IS_PF(bp)) {
8095                 unsigned long ramrod_flags = 0;
8096
8097                 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8098                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8099                 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8100                                          &bp->sp_objs->mac_obj, set,
8101                                          BNX2X_ETH_MAC, &ramrod_flags);
8102         } else { /* vf */
8103                 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8104                                              bp->fp->index, true);
8105         }
8106 }
8107
8108 int bnx2x_setup_leading(struct bnx2x *bp)
8109 {
8110         if (IS_PF(bp))
8111                 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8112         else /* VF */
8113                 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
8114 }
8115
8116 /**
8117  * bnx2x_set_int_mode - configure interrupt mode
8118  *
8119  * @bp:         driver handle
8120  *
8121  * In case of MSI-X it will also try to enable MSI-X.
8122  */
8123 int bnx2x_set_int_mode(struct bnx2x *bp)
8124 {
8125         int rc = 0;
8126
8127         if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8128                 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8129                 return -EINVAL;
8130         }
8131
8132         switch (int_mode) {
8133         case BNX2X_INT_MODE_MSIX:
8134                 /* attempt to enable msix */
8135                 rc = bnx2x_enable_msix(bp);
8136
8137                 /* msix attained */
8138                 if (!rc)
8139                         return 0;
8140
8141                 /* vfs use only msix */
8142                 if (rc && IS_VF(bp))
8143                         return rc;
8144
8145                 /* failed to enable multiple MSI-X */
8146                 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8147                                bp->num_queues,
8148                                1 + bp->num_cnic_queues);
8149
8150                 /* falling through... */
8151         case BNX2X_INT_MODE_MSI:
8152                 bnx2x_enable_msi(bp);
8153
8154                 /* falling through... */
8155         case BNX2X_INT_MODE_INTX:
8156                 bp->num_ethernet_queues = 1;
8157                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8158                 BNX2X_DEV_INFO("set number of queues to 1\n");
8159                 break;
8160         default:
8161                 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8162                 return -EINVAL;
8163         }
8164         return 0;
8165 }
8166
8167 /* must be called prior to any HW initializations */
8168 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8169 {
8170         if (IS_SRIOV(bp))
8171                 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8172         return L2_ILT_LINES(bp);
8173 }
8174
8175 void bnx2x_ilt_set_info(struct bnx2x *bp)
8176 {
8177         struct ilt_client_info *ilt_client;
8178         struct bnx2x_ilt *ilt = BP_ILT(bp);
8179         u16 line = 0;
8180
8181         ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8182         DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8183
8184         /* CDU */
8185         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8186         ilt_client->client_num = ILT_CLIENT_CDU;
8187         ilt_client->page_size = CDU_ILT_PAGE_SZ;
8188         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8189         ilt_client->start = line;
8190         line += bnx2x_cid_ilt_lines(bp);
8191
8192         if (CNIC_SUPPORT(bp))
8193                 line += CNIC_ILT_LINES;
8194         ilt_client->end = line - 1;
8195
8196         DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8197            ilt_client->start,
8198            ilt_client->end,
8199            ilt_client->page_size,
8200            ilt_client->flags,
8201            ilog2(ilt_client->page_size >> 12));
8202
8203         /* QM */
8204         if (QM_INIT(bp->qm_cid_count)) {
8205                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8206                 ilt_client->client_num = ILT_CLIENT_QM;
8207                 ilt_client->page_size = QM_ILT_PAGE_SZ;
8208                 ilt_client->flags = 0;
8209                 ilt_client->start = line;
8210
8211                 /* 4 bytes for each cid */
8212                 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8213                                                          QM_ILT_PAGE_SZ);
8214
8215                 ilt_client->end = line - 1;
8216
8217                 DP(NETIF_MSG_IFUP,
8218                    "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8219                    ilt_client->start,
8220                    ilt_client->end,
8221                    ilt_client->page_size,
8222                    ilt_client->flags,
8223                    ilog2(ilt_client->page_size >> 12));
8224         }
8225
8226         if (CNIC_SUPPORT(bp)) {
8227                 /* SRC */
8228                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8229                 ilt_client->client_num = ILT_CLIENT_SRC;
8230                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8231                 ilt_client->flags = 0;
8232                 ilt_client->start = line;
8233                 line += SRC_ILT_LINES;
8234                 ilt_client->end = line - 1;
8235
8236                 DP(NETIF_MSG_IFUP,
8237                    "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8238                    ilt_client->start,
8239                    ilt_client->end,
8240                    ilt_client->page_size,
8241                    ilt_client->flags,
8242                    ilog2(ilt_client->page_size >> 12));
8243
8244                 /* TM */
8245                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8246                 ilt_client->client_num = ILT_CLIENT_TM;
8247                 ilt_client->page_size = TM_ILT_PAGE_SZ;
8248                 ilt_client->flags = 0;
8249                 ilt_client->start = line;
8250                 line += TM_ILT_LINES;
8251                 ilt_client->end = line - 1;
8252
8253                 DP(NETIF_MSG_IFUP,
8254                    "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8255                    ilt_client->start,
8256                    ilt_client->end,
8257                    ilt_client->page_size,
8258                    ilt_client->flags,
8259                    ilog2(ilt_client->page_size >> 12));
8260         }
8261
8262         BUG_ON(line > ILT_MAX_LINES);
8263 }
8264
8265 /**
8266  * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8267  *
8268  * @bp:                 driver handle
8269  * @fp:                 pointer to fastpath
8270  * @init_params:        pointer to parameters structure
8271  *
8272  * parameters configured:
8273  *      - HC configuration
8274  *      - Queue's CDU context
8275  */
8276 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8277         struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8278 {
8279         u8 cos;
8280         int cxt_index, cxt_offset;
8281
8282         /* FCoE Queue uses Default SB, thus has no HC capabilities */
8283         if (!IS_FCOE_FP(fp)) {
8284                 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8285                 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8286
8287                 /* If HC is supported, enable host coalescing in the transition
8288                  * to INIT state.
8289                  */
8290                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8291                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8292
8293                 /* HC rate */
8294                 init_params->rx.hc_rate = bp->rx_ticks ?
8295                         (1000000 / bp->rx_ticks) : 0;
8296                 init_params->tx.hc_rate = bp->tx_ticks ?
8297                         (1000000 / bp->tx_ticks) : 0;
8298
8299                 /* FW SB ID */
8300                 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8301                         fp->fw_sb_id;
8302
8303                 /*
8304                  * CQ index among the SB indices: FCoE clients uses the default
8305                  * SB, therefore it's different.
8306                  */
8307                 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8308                 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8309         }
8310
8311         /* set maximum number of COSs supported by this queue */
8312         init_params->max_cos = fp->max_cos;
8313
8314         DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8315             fp->index, init_params->max_cos);
8316
8317         /* set the context pointers queue object */
8318         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8319                 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8320                 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8321                                 ILT_PAGE_CIDS);
8322                 init_params->cxts[cos] =
8323                         &bp->context[cxt_index].vcxt[cxt_offset].eth;
8324         }
8325 }
8326
8327 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8328                         struct bnx2x_queue_state_params *q_params,
8329                         struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8330                         int tx_index, bool leading)
8331 {
8332         memset(tx_only_params, 0, sizeof(*tx_only_params));
8333
8334         /* Set the command */
8335         q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8336
8337         /* Set tx-only QUEUE flags: don't zero statistics */
8338         tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8339
8340         /* choose the index of the cid to send the slow path on */
8341         tx_only_params->cid_index = tx_index;
8342
8343         /* Set general TX_ONLY_SETUP parameters */
8344         bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8345
8346         /* Set Tx TX_ONLY_SETUP parameters */
8347         bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8348
8349         DP(NETIF_MSG_IFUP,
8350            "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8351            tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8352            q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8353            tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8354
8355         /* send the ramrod */
8356         return bnx2x_queue_state_change(bp, q_params);
8357 }
8358
8359 /**
8360  * bnx2x_setup_queue - setup queue
8361  *
8362  * @bp:         driver handle
8363  * @fp:         pointer to fastpath
8364  * @leading:    is leading
8365  *
8366  * This function performs 2 steps in a Queue state machine
8367  *      actually: 1) RESET->INIT 2) INIT->SETUP
8368  */
8369
8370 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8371                        bool leading)
8372 {
8373         struct bnx2x_queue_state_params q_params = {NULL};
8374         struct bnx2x_queue_setup_params *setup_params =
8375                                                 &q_params.params.setup;
8376         struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8377                                                 &q_params.params.tx_only;
8378         int rc;
8379         u8 tx_index;
8380
8381         DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8382
8383         /* reset IGU state skip FCoE L2 queue */
8384         if (!IS_FCOE_FP(fp))
8385                 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8386                              IGU_INT_ENABLE, 0);
8387
8388         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8389         /* We want to wait for completion in this context */
8390         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8391
8392         /* Prepare the INIT parameters */
8393         bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8394
8395         /* Set the command */
8396         q_params.cmd = BNX2X_Q_CMD_INIT;
8397
8398         /* Change the state to INIT */
8399         rc = bnx2x_queue_state_change(bp, &q_params);
8400         if (rc) {
8401                 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8402                 return rc;
8403         }
8404
8405         DP(NETIF_MSG_IFUP, "init complete\n");
8406
8407         /* Now move the Queue to the SETUP state... */
8408         memset(setup_params, 0, sizeof(*setup_params));
8409
8410         /* Set QUEUE flags */
8411         setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8412
8413         /* Set general SETUP parameters */
8414         bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8415                                 FIRST_TX_COS_INDEX);
8416
8417         bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8418                             &setup_params->rxq_params);
8419
8420         bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8421                            FIRST_TX_COS_INDEX);
8422
8423         /* Set the command */
8424         q_params.cmd = BNX2X_Q_CMD_SETUP;
8425
8426         if (IS_FCOE_FP(fp))
8427                 bp->fcoe_init = true;
8428
8429         /* Change the state to SETUP */
8430         rc = bnx2x_queue_state_change(bp, &q_params);
8431         if (rc) {
8432                 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8433                 return rc;
8434         }
8435
8436         /* loop through the relevant tx-only indices */
8437         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8438               tx_index < fp->max_cos;
8439               tx_index++) {
8440
8441                 /* prepare and send tx-only ramrod*/
8442                 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8443                                           tx_only_params, tx_index, leading);
8444                 if (rc) {
8445                         BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8446                                   fp->index, tx_index);
8447                         return rc;
8448                 }
8449         }
8450
8451         return rc;
8452 }
8453
8454 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8455 {
8456         struct bnx2x_fastpath *fp = &bp->fp[index];
8457         struct bnx2x_fp_txdata *txdata;
8458         struct bnx2x_queue_state_params q_params = {NULL};
8459         int rc, tx_index;
8460
8461         DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8462
8463         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8464         /* We want to wait for completion in this context */
8465         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8466
8467         /* close tx-only connections */
8468         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8469              tx_index < fp->max_cos;
8470              tx_index++){
8471
8472                 /* ascertain this is a normal queue*/
8473                 txdata = fp->txdata_ptr[tx_index];
8474
8475                 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8476                                                         txdata->txq_index);
8477
8478                 /* send halt terminate on tx-only connection */
8479                 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8480                 memset(&q_params.params.terminate, 0,
8481                        sizeof(q_params.params.terminate));
8482                 q_params.params.terminate.cid_index = tx_index;
8483
8484                 rc = bnx2x_queue_state_change(bp, &q_params);
8485                 if (rc)
8486                         return rc;
8487
8488                 /* send halt terminate on tx-only connection */
8489                 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8490                 memset(&q_params.params.cfc_del, 0,
8491                        sizeof(q_params.params.cfc_del));
8492                 q_params.params.cfc_del.cid_index = tx_index;
8493                 rc = bnx2x_queue_state_change(bp, &q_params);
8494                 if (rc)
8495                         return rc;
8496         }
8497         /* Stop the primary connection: */
8498         /* ...halt the connection */
8499         q_params.cmd = BNX2X_Q_CMD_HALT;
8500         rc = bnx2x_queue_state_change(bp, &q_params);
8501         if (rc)
8502                 return rc;
8503
8504         /* ...terminate the connection */
8505         q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8506         memset(&q_params.params.terminate, 0,
8507                sizeof(q_params.params.terminate));
8508         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8509         rc = bnx2x_queue_state_change(bp, &q_params);
8510         if (rc)
8511                 return rc;
8512         /* ...delete cfc entry */
8513         q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8514         memset(&q_params.params.cfc_del, 0,
8515                sizeof(q_params.params.cfc_del));
8516         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8517         return bnx2x_queue_state_change(bp, &q_params);
8518 }
8519
8520 static void bnx2x_reset_func(struct bnx2x *bp)
8521 {
8522         int port = BP_PORT(bp);
8523         int func = BP_FUNC(bp);
8524         int i;
8525
8526         /* Disable the function in the FW */
8527         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8528         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8529         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8530         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8531
8532         /* FP SBs */
8533         for_each_eth_queue(bp, i) {
8534                 struct bnx2x_fastpath *fp = &bp->fp[i];
8535                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8536                            CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8537                            SB_DISABLED);
8538         }
8539
8540         if (CNIC_LOADED(bp))
8541                 /* CNIC SB */
8542                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8543                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8544                         (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8545
8546         /* SP SB */
8547         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8548                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8549                 SB_DISABLED);
8550
8551         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8552                 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8553                        0);
8554
8555         /* Configure IGU */
8556         if (bp->common.int_block == INT_BLOCK_HC) {
8557                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8558                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8559         } else {
8560                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8561                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8562         }
8563
8564         if (CNIC_LOADED(bp)) {
8565                 /* Disable Timer scan */
8566                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8567                 /*
8568                  * Wait for at least 10ms and up to 2 second for the timers
8569                  * scan to complete
8570                  */
8571                 for (i = 0; i < 200; i++) {
8572                         usleep_range(10000, 20000);
8573                         if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8574                                 break;
8575                 }
8576         }
8577         /* Clear ILT */
8578         bnx2x_clear_func_ilt(bp, func);
8579
8580         /* Timers workaround bug for E2: if this is vnic-3,
8581          * we need to set the entire ilt range for this timers.
8582          */
8583         if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8584                 struct ilt_client_info ilt_cli;
8585                 /* use dummy TM client */
8586                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8587                 ilt_cli.start = 0;
8588                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8589                 ilt_cli.client_num = ILT_CLIENT_TM;
8590
8591                 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8592         }
8593
8594         /* this assumes that reset_port() called before reset_func()*/
8595         if (!CHIP_IS_E1x(bp))
8596                 bnx2x_pf_disable(bp);
8597
8598         bp->dmae_ready = 0;
8599 }
8600
8601 static void bnx2x_reset_port(struct bnx2x *bp)
8602 {
8603         int port = BP_PORT(bp);
8604         u32 val;
8605
8606         /* Reset physical Link */
8607         bnx2x__link_reset(bp);
8608
8609         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8610
8611         /* Do not rcv packets to BRB */
8612         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8613         /* Do not direct rcv packets that are not for MCP to the BRB */
8614         REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8615                            NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8616
8617         /* Configure AEU */
8618         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8619
8620         msleep(100);
8621         /* Check for BRB port occupancy */
8622         val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8623         if (val)
8624                 DP(NETIF_MSG_IFDOWN,
8625                    "BRB1 is not empty  %d blocks are occupied\n", val);
8626
8627         /* TODO: Close Doorbell port? */
8628 }
8629
8630 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8631 {
8632         struct bnx2x_func_state_params func_params = {NULL};
8633
8634         /* Prepare parameters for function state transitions */
8635         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8636
8637         func_params.f_obj = &bp->func_obj;
8638         func_params.cmd = BNX2X_F_CMD_HW_RESET;
8639
8640         func_params.params.hw_init.load_phase = load_code;
8641
8642         return bnx2x_func_state_change(bp, &func_params);
8643 }
8644
8645 static int bnx2x_func_stop(struct bnx2x *bp)
8646 {
8647         struct bnx2x_func_state_params func_params = {NULL};
8648         int rc;
8649
8650         /* Prepare parameters for function state transitions */
8651         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8652         func_params.f_obj = &bp->func_obj;
8653         func_params.cmd = BNX2X_F_CMD_STOP;
8654
8655         /*
8656          * Try to stop the function the 'good way'. If fails (in case
8657          * of a parity error during bnx2x_chip_cleanup()) and we are
8658          * not in a debug mode, perform a state transaction in order to
8659          * enable further HW_RESET transaction.
8660          */
8661         rc = bnx2x_func_state_change(bp, &func_params);
8662         if (rc) {
8663 #ifdef BNX2X_STOP_ON_ERROR
8664                 return rc;
8665 #else
8666                 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8667                 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8668                 return bnx2x_func_state_change(bp, &func_params);
8669 #endif
8670         }
8671
8672         return 0;
8673 }
8674
8675 /**
8676  * bnx2x_send_unload_req - request unload mode from the MCP.
8677  *
8678  * @bp:                 driver handle
8679  * @unload_mode:        requested function's unload mode
8680  *
8681  * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8682  */
8683 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8684 {
8685         u32 reset_code = 0;
8686         int port = BP_PORT(bp);
8687
8688         /* Select the UNLOAD request mode */
8689         if (unload_mode == UNLOAD_NORMAL)
8690                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8691
8692         else if (bp->flags & NO_WOL_FLAG)
8693                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
8694
8695         else if (bp->wol) {
8696                 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8697                 u8 *mac_addr = bp->dev->dev_addr;
8698                 struct pci_dev *pdev = bp->pdev;
8699                 u32 val;
8700                 u16 pmc;
8701
8702                 /* The mac address is written to entries 1-4 to
8703                  * preserve entry 0 which is used by the PMF
8704                  */
8705                 u8 entry = (BP_VN(bp) + 1)*8;
8706
8707                 val = (mac_addr[0] << 8) | mac_addr[1];
8708                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8709
8710                 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8711                       (mac_addr[4] << 8) | mac_addr[5];
8712                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8713
8714                 /* Enable the PME and clear the status */
8715                 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
8716                 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
8717                 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
8718
8719                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8720
8721         } else
8722                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8723
8724         /* Send the request to the MCP */
8725         if (!BP_NOMCP(bp))
8726                 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8727         else {
8728                 int path = BP_PATH(bp);
8729
8730                 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d]      %d, %d, %d\n",
8731                    path, load_count[path][0], load_count[path][1],
8732                    load_count[path][2]);
8733                 load_count[path][0]--;
8734                 load_count[path][1 + port]--;
8735                 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d]  %d, %d, %d\n",
8736                    path, load_count[path][0], load_count[path][1],
8737                    load_count[path][2]);
8738                 if (load_count[path][0] == 0)
8739                         reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8740                 else if (load_count[path][1 + port] == 0)
8741                         reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8742                 else
8743                         reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8744         }
8745
8746         return reset_code;
8747 }
8748
8749 /**
8750  * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8751  *
8752  * @bp:         driver handle
8753  * @keep_link:          true iff link should be kept up
8754  */
8755 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
8756 {
8757         u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8758
8759         /* Report UNLOAD_DONE to MCP */
8760         if (!BP_NOMCP(bp))
8761                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
8762 }
8763
8764 static int bnx2x_func_wait_started(struct bnx2x *bp)
8765 {
8766         int tout = 50;
8767         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8768
8769         if (!bp->port.pmf)
8770                 return 0;
8771
8772         /*
8773          * (assumption: No Attention from MCP at this stage)
8774          * PMF probably in the middle of TX disable/enable transaction
8775          * 1. Sync IRS for default SB
8776          * 2. Sync SP queue - this guarantees us that attention handling started
8777          * 3. Wait, that TX disable/enable transaction completes
8778          *
8779          * 1+2 guarantee that if DCBx attention was scheduled it already changed
8780          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
8781          * received completion for the transaction the state is TX_STOPPED.
8782          * State will return to STARTED after completion of TX_STOPPED-->STARTED
8783          * transaction.
8784          */
8785
8786         /* make sure default SB ISR is done */
8787         if (msix)
8788                 synchronize_irq(bp->msix_table[0].vector);
8789         else
8790                 synchronize_irq(bp->pdev->irq);
8791
8792         flush_workqueue(bnx2x_wq);
8793
8794         while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8795                                 BNX2X_F_STATE_STARTED && tout--)
8796                 msleep(20);
8797
8798         if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8799                                                 BNX2X_F_STATE_STARTED) {
8800 #ifdef BNX2X_STOP_ON_ERROR
8801                 BNX2X_ERR("Wrong function state\n");
8802                 return -EBUSY;
8803 #else
8804                 /*
8805                  * Failed to complete the transaction in a "good way"
8806                  * Force both transactions with CLR bit
8807                  */
8808                 struct bnx2x_func_state_params func_params = {NULL};
8809
8810                 DP(NETIF_MSG_IFDOWN,
8811                    "Hmmm... Unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
8812
8813                 func_params.f_obj = &bp->func_obj;
8814                 __set_bit(RAMROD_DRV_CLR_ONLY,
8815                                         &func_params.ramrod_flags);
8816
8817                 /* STARTED-->TX_ST0PPED */
8818                 func_params.cmd = BNX2X_F_CMD_TX_STOP;
8819                 bnx2x_func_state_change(bp, &func_params);
8820
8821                 /* TX_ST0PPED-->STARTED */
8822                 func_params.cmd = BNX2X_F_CMD_TX_START;
8823                 return bnx2x_func_state_change(bp, &func_params);
8824 #endif
8825         }
8826
8827         return 0;
8828 }
8829
8830 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
8831 {
8832         int port = BP_PORT(bp);
8833         int i, rc = 0;
8834         u8 cos;
8835         struct bnx2x_mcast_ramrod_params rparam = {NULL};
8836         u32 reset_code;
8837
8838         /* Wait until tx fastpath tasks complete */
8839         for_each_tx_queue(bp, i) {
8840                 struct bnx2x_fastpath *fp = &bp->fp[i];
8841
8842                 for_each_cos_in_tx_queue(fp, cos)
8843                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
8844 #ifdef BNX2X_STOP_ON_ERROR
8845                 if (rc)
8846                         return;
8847 #endif
8848         }
8849
8850         /* Give HW time to discard old tx messages */
8851         usleep_range(1000, 2000);
8852
8853         /* Clean all ETH MACs */
8854         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8855                                 false);
8856         if (rc < 0)
8857                 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8858
8859         /* Clean up UC list  */
8860         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
8861                                 true);
8862         if (rc < 0)
8863                 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8864                           rc);
8865
8866         /* Disable LLH */
8867         if (!CHIP_IS_E1(bp))
8868                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8869
8870         /* Set "drop all" (stop Rx).
8871          * We need to take a netif_addr_lock() here in order to prevent
8872          * a race between the completion code and this code.
8873          */
8874         netif_addr_lock_bh(bp->dev);
8875         /* Schedule the rx_mode command */
8876         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
8877                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8878         else
8879                 bnx2x_set_storm_rx_mode(bp);
8880
8881         /* Cleanup multicast configuration */
8882         rparam.mcast_obj = &bp->mcast_obj;
8883         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8884         if (rc < 0)
8885                 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8886
8887         netif_addr_unlock_bh(bp->dev);
8888
8889         bnx2x_iov_chip_cleanup(bp);
8890
8891         /*
8892          * Send the UNLOAD_REQUEST to the MCP. This will return if
8893          * this function should perform FUNC, PORT or COMMON HW
8894          * reset.
8895          */
8896         reset_code = bnx2x_send_unload_req(bp, unload_mode);
8897
8898         /*
8899          * (assumption: No Attention from MCP at this stage)
8900          * PMF probably in the middle of TX disable/enable transaction
8901          */
8902         rc = bnx2x_func_wait_started(bp);
8903         if (rc) {
8904                 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8905 #ifdef BNX2X_STOP_ON_ERROR
8906                 return;
8907 #endif
8908         }
8909
8910         /* Close multi and leading connections
8911          * Completions for ramrods are collected in a synchronous way
8912          */
8913         for_each_eth_queue(bp, i)
8914                 if (bnx2x_stop_queue(bp, i))
8915 #ifdef BNX2X_STOP_ON_ERROR
8916                         return;
8917 #else
8918                         goto unload_error;
8919 #endif
8920
8921         if (CNIC_LOADED(bp)) {
8922                 for_each_cnic_queue(bp, i)
8923                         if (bnx2x_stop_queue(bp, i))
8924 #ifdef BNX2X_STOP_ON_ERROR
8925                                 return;
8926 #else
8927                                 goto unload_error;
8928 #endif
8929         }
8930
8931         /* If SP settings didn't get completed so far - something
8932          * very wrong has happen.
8933          */
8934         if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8935                 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8936
8937 #ifndef BNX2X_STOP_ON_ERROR
8938 unload_error:
8939 #endif
8940         rc = bnx2x_func_stop(bp);
8941         if (rc) {
8942                 BNX2X_ERR("Function stop failed!\n");
8943 #ifdef BNX2X_STOP_ON_ERROR
8944                 return;
8945 #endif
8946         }
8947
8948         /* Disable HW interrupts, NAPI */
8949         bnx2x_netif_stop(bp, 1);
8950         /* Delete all NAPI objects */
8951         bnx2x_del_all_napi(bp);
8952         if (CNIC_LOADED(bp))
8953                 bnx2x_del_all_napi_cnic(bp);
8954
8955         /* Release IRQs */
8956         bnx2x_free_irq(bp);
8957
8958         /* Reset the chip */
8959         rc = bnx2x_reset_hw(bp, reset_code);
8960         if (rc)
8961                 BNX2X_ERR("HW_RESET failed\n");
8962
8963         /* Report UNLOAD_DONE to MCP */
8964         bnx2x_send_unload_done(bp, keep_link);
8965 }
8966
8967 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
8968 {
8969         u32 val;
8970
8971         DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
8972
8973         if (CHIP_IS_E1(bp)) {
8974                 int port = BP_PORT(bp);
8975                 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8976                         MISC_REG_AEU_MASK_ATTN_FUNC_0;
8977
8978                 val = REG_RD(bp, addr);
8979                 val &= ~(0x300);
8980                 REG_WR(bp, addr, val);
8981         } else {
8982                 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8983                 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8984                          MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8985                 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8986         }
8987 }
8988
8989 /* Close gates #2, #3 and #4: */
8990 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8991 {
8992         u32 val;
8993
8994         /* Gates #2 and #4a are closed/opened for "not E1" only */
8995         if (!CHIP_IS_E1(bp)) {
8996                 /* #4 */
8997                 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
8998                 /* #2 */
8999                 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
9000         }
9001
9002         /* #3 */
9003         if (CHIP_IS_E1x(bp)) {
9004                 /* Prevent interrupts from HC on both ports */
9005                 val = REG_RD(bp, HC_REG_CONFIG_1);
9006                 REG_WR(bp, HC_REG_CONFIG_1,
9007                        (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9008                        (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9009
9010                 val = REG_RD(bp, HC_REG_CONFIG_0);
9011                 REG_WR(bp, HC_REG_CONFIG_0,
9012                        (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9013                        (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9014         } else {
9015                 /* Prevent incoming interrupts in IGU */
9016                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9017
9018                 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9019                        (!close) ?
9020                        (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9021                        (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9022         }
9023
9024         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
9025                 close ? "closing" : "opening");
9026         mmiowb();
9027 }
9028
9029 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
9030
9031 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9032 {
9033         /* Do some magic... */
9034         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9035         *magic_val = val & SHARED_MF_CLP_MAGIC;
9036         MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9037 }
9038
9039 /**
9040  * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9041  *
9042  * @bp:         driver handle
9043  * @magic_val:  old value of the `magic' bit.
9044  */
9045 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9046 {
9047         /* Restore the `magic' bit value... */
9048         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9049         MF_CFG_WR(bp, shared_mf_config.clp_mb,
9050                 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9051 }
9052
9053 /**
9054  * bnx2x_reset_mcp_prep - prepare for MCP reset.
9055  *
9056  * @bp:         driver handle
9057  * @magic_val:  old value of 'magic' bit.
9058  *
9059  * Takes care of CLP configurations.
9060  */
9061 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9062 {
9063         u32 shmem;
9064         u32 validity_offset;
9065
9066         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
9067
9068         /* Set `magic' bit in order to save MF config */
9069         if (!CHIP_IS_E1(bp))
9070                 bnx2x_clp_reset_prep(bp, magic_val);
9071
9072         /* Get shmem offset */
9073         shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9074         validity_offset =
9075                 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9076
9077         /* Clear validity map flags */
9078         if (shmem > 0)
9079                 REG_WR(bp, shmem + validity_offset, 0);
9080 }
9081
9082 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
9083 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
9084
9085 /**
9086  * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9087  *
9088  * @bp: driver handle
9089  */
9090 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9091 {
9092         /* special handling for emulation and FPGA,
9093            wait 10 times longer */
9094         if (CHIP_REV_IS_SLOW(bp))
9095                 msleep(MCP_ONE_TIMEOUT*10);
9096         else
9097                 msleep(MCP_ONE_TIMEOUT);
9098 }
9099
9100 /*
9101  * initializes bp->common.shmem_base and waits for validity signature to appear
9102  */
9103 static int bnx2x_init_shmem(struct bnx2x *bp)
9104 {
9105         int cnt = 0;
9106         u32 val = 0;
9107
9108         do {
9109                 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9110                 if (bp->common.shmem_base) {
9111                         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9112                         if (val & SHR_MEM_VALIDITY_MB)
9113                                 return 0;
9114                 }
9115
9116                 bnx2x_mcp_wait_one(bp);
9117
9118         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9119
9120         BNX2X_ERR("BAD MCP validity signature\n");
9121
9122         return -ENODEV;
9123 }
9124
9125 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9126 {
9127         int rc = bnx2x_init_shmem(bp);
9128
9129         /* Restore the `magic' bit value */
9130         if (!CHIP_IS_E1(bp))
9131                 bnx2x_clp_reset_done(bp, magic_val);
9132
9133         return rc;
9134 }
9135
9136 static void bnx2x_pxp_prep(struct bnx2x *bp)
9137 {
9138         if (!CHIP_IS_E1(bp)) {
9139                 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9140                 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9141                 mmiowb();
9142         }
9143 }
9144
9145 /*
9146  * Reset the whole chip except for:
9147  *      - PCIE core
9148  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9149  *              one reset bit)
9150  *      - IGU
9151  *      - MISC (including AEU)
9152  *      - GRC
9153  *      - RBCN, RBCP
9154  */
9155 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9156 {
9157         u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9158         u32 global_bits2, stay_reset2;
9159
9160         /*
9161          * Bits that have to be set in reset_mask2 if we want to reset 'global'
9162          * (per chip) blocks.
9163          */
9164         global_bits2 =
9165                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9166                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9167
9168         /* Don't reset the following blocks.
9169          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9170          *            reset, as in 4 port device they might still be owned
9171          *            by the MCP (there is only one leader per path).
9172          */
9173         not_reset_mask1 =
9174                 MISC_REGISTERS_RESET_REG_1_RST_HC |
9175                 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9176                 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9177
9178         not_reset_mask2 =
9179                 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9180                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9181                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9182                 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9183                 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9184                 MISC_REGISTERS_RESET_REG_2_RST_GRC  |
9185                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9186                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9187                 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9188                 MISC_REGISTERS_RESET_REG_2_PGLC |
9189                 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9190                 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9191                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9192                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9193                 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9194                 MISC_REGISTERS_RESET_REG_2_UMAC1;
9195
9196         /*
9197          * Keep the following blocks in reset:
9198          *  - all xxMACs are handled by the bnx2x_link code.
9199          */
9200         stay_reset2 =
9201                 MISC_REGISTERS_RESET_REG_2_XMAC |
9202                 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9203
9204         /* Full reset masks according to the chip */
9205         reset_mask1 = 0xffffffff;
9206
9207         if (CHIP_IS_E1(bp))
9208                 reset_mask2 = 0xffff;
9209         else if (CHIP_IS_E1H(bp))
9210                 reset_mask2 = 0x1ffff;
9211         else if (CHIP_IS_E2(bp))
9212                 reset_mask2 = 0xfffff;
9213         else /* CHIP_IS_E3 */
9214                 reset_mask2 = 0x3ffffff;
9215
9216         /* Don't reset global blocks unless we need to */
9217         if (!global)
9218                 reset_mask2 &= ~global_bits2;
9219
9220         /*
9221          * In case of attention in the QM, we need to reset PXP
9222          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9223          * because otherwise QM reset would release 'close the gates' shortly
9224          * before resetting the PXP, then the PSWRQ would send a write
9225          * request to PGLUE. Then when PXP is reset, PGLUE would try to
9226          * read the payload data from PSWWR, but PSWWR would not
9227          * respond. The write queue in PGLUE would stuck, dmae commands
9228          * would not return. Therefore it's important to reset the second
9229          * reset register (containing the
9230          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9231          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9232          * bit).
9233          */
9234         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9235                reset_mask2 & (~not_reset_mask2));
9236
9237         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9238                reset_mask1 & (~not_reset_mask1));
9239
9240         barrier();
9241         mmiowb();
9242
9243         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9244                reset_mask2 & (~stay_reset2));
9245
9246         barrier();
9247         mmiowb();
9248
9249         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9250         mmiowb();
9251 }
9252
9253 /**
9254  * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9255  * It should get cleared in no more than 1s.
9256  *
9257  * @bp: driver handle
9258  *
9259  * It should get cleared in no more than 1s. Returns 0 if
9260  * pending writes bit gets cleared.
9261  */
9262 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9263 {
9264         u32 cnt = 1000;
9265         u32 pend_bits = 0;
9266
9267         do {
9268                 pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9269
9270                 if (pend_bits == 0)
9271                         break;
9272
9273                 usleep_range(1000, 2000);
9274         } while (cnt-- > 0);
9275
9276         if (cnt <= 0) {
9277                 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9278                           pend_bits);
9279                 return -EBUSY;
9280         }
9281
9282         return 0;
9283 }
9284
9285 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9286 {
9287         int cnt = 1000;
9288         u32 val = 0;
9289         u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9290         u32 tags_63_32 = 0;
9291
9292         /* Empty the Tetris buffer, wait for 1s */
9293         do {
9294                 sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9295                 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9296                 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9297                 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9298                 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9299                 if (CHIP_IS_E3(bp))
9300                         tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9301
9302                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9303                     ((port_is_idle_0 & 0x1) == 0x1) &&
9304                     ((port_is_idle_1 & 0x1) == 0x1) &&
9305                     (pgl_exp_rom2 == 0xffffffff) &&
9306                     (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9307                         break;
9308                 usleep_range(1000, 2000);
9309         } while (cnt-- > 0);
9310
9311         if (cnt <= 0) {
9312                 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9313                 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9314                           sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9315                           pgl_exp_rom2);
9316                 return -EAGAIN;
9317         }
9318
9319         barrier();
9320
9321         /* Close gates #2, #3 and #4 */
9322         bnx2x_set_234_gates(bp, true);
9323
9324         /* Poll for IGU VQs for 57712 and newer chips */
9325         if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9326                 return -EAGAIN;
9327
9328         /* TBD: Indicate that "process kill" is in progress to MCP */
9329
9330         /* Clear "unprepared" bit */
9331         REG_WR(bp, MISC_REG_UNPREPARED, 0);
9332         barrier();
9333
9334         /* Make sure all is written to the chip before the reset */
9335         mmiowb();
9336
9337         /* Wait for 1ms to empty GLUE and PCI-E core queues,
9338          * PSWHST, GRC and PSWRD Tetris buffer.
9339          */
9340         usleep_range(1000, 2000);
9341
9342         /* Prepare to chip reset: */
9343         /* MCP */
9344         if (global)
9345                 bnx2x_reset_mcp_prep(bp, &val);
9346
9347         /* PXP */
9348         bnx2x_pxp_prep(bp);
9349         barrier();
9350
9351         /* reset the chip */
9352         bnx2x_process_kill_chip_reset(bp, global);
9353         barrier();
9354
9355         /* Recover after reset: */
9356         /* MCP */
9357         if (global && bnx2x_reset_mcp_comp(bp, val))
9358                 return -EAGAIN;
9359
9360         /* TBD: Add resetting the NO_MCP mode DB here */
9361
9362         /* Open the gates #2, #3 and #4 */
9363         bnx2x_set_234_gates(bp, false);
9364
9365         /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9366          * reset state, re-enable attentions. */
9367
9368         return 0;
9369 }
9370
9371 static int bnx2x_leader_reset(struct bnx2x *bp)
9372 {
9373         int rc = 0;
9374         bool global = bnx2x_reset_is_global(bp);
9375         u32 load_code;
9376
9377         /* if not going to reset MCP - load "fake" driver to reset HW while
9378          * driver is owner of the HW
9379          */
9380         if (!global && !BP_NOMCP(bp)) {
9381                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9382                                              DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9383                 if (!load_code) {
9384                         BNX2X_ERR("MCP response failure, aborting\n");
9385                         rc = -EAGAIN;
9386                         goto exit_leader_reset;
9387                 }
9388                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9389                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9390                         BNX2X_ERR("MCP unexpected resp, aborting\n");
9391                         rc = -EAGAIN;
9392                         goto exit_leader_reset2;
9393                 }
9394                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9395                 if (!load_code) {
9396                         BNX2X_ERR("MCP response failure, aborting\n");
9397                         rc = -EAGAIN;
9398                         goto exit_leader_reset2;
9399                 }
9400         }
9401
9402         /* Try to recover after the failure */
9403         if (bnx2x_process_kill(bp, global)) {
9404                 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9405                           BP_PATH(bp));
9406                 rc = -EAGAIN;
9407                 goto exit_leader_reset2;
9408         }
9409
9410         /*
9411          * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9412          * state.
9413          */
9414         bnx2x_set_reset_done(bp);
9415         if (global)
9416                 bnx2x_clear_reset_global(bp);
9417
9418 exit_leader_reset2:
9419         /* unload "fake driver" if it was loaded */
9420         if (!global && !BP_NOMCP(bp)) {
9421                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9422                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9423         }
9424 exit_leader_reset:
9425         bp->is_leader = 0;
9426         bnx2x_release_leader_lock(bp);
9427         smp_mb();
9428         return rc;
9429 }
9430
9431 static void bnx2x_recovery_failed(struct bnx2x *bp)
9432 {
9433         netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9434
9435         /* Disconnect this device */
9436         netif_device_detach(bp->dev);
9437
9438         /*
9439          * Block ifup for all function on this engine until "process kill"
9440          * or power cycle.
9441          */
9442         bnx2x_set_reset_in_progress(bp);
9443
9444         /* Shut down the power */
9445         bnx2x_set_power_state(bp, PCI_D3hot);
9446
9447         bp->recovery_state = BNX2X_RECOVERY_FAILED;
9448
9449         smp_mb();
9450 }
9451
9452 /*
9453  * Assumption: runs under rtnl lock. This together with the fact
9454  * that it's called only from bnx2x_sp_rtnl() ensure that it
9455  * will never be called when netif_running(bp->dev) is false.
9456  */
9457 static void bnx2x_parity_recover(struct bnx2x *bp)
9458 {
9459         bool global = false;
9460         u32 error_recovered, error_unrecovered;
9461         bool is_parity;
9462
9463         DP(NETIF_MSG_HW, "Handling parity\n");
9464         while (1) {
9465                 switch (bp->recovery_state) {
9466                 case BNX2X_RECOVERY_INIT:
9467                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9468                         is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9469                         WARN_ON(!is_parity);
9470
9471                         /* Try to get a LEADER_LOCK HW lock */
9472                         if (bnx2x_trylock_leader_lock(bp)) {
9473                                 bnx2x_set_reset_in_progress(bp);
9474                                 /*
9475                                  * Check if there is a global attention and if
9476                                  * there was a global attention, set the global
9477                                  * reset bit.
9478                                  */
9479
9480                                 if (global)
9481                                         bnx2x_set_reset_global(bp);
9482
9483                                 bp->is_leader = 1;
9484                         }
9485
9486                         /* Stop the driver */
9487                         /* If interface has been removed - break */
9488                         if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9489                                 return;
9490
9491                         bp->recovery_state = BNX2X_RECOVERY_WAIT;
9492
9493                         /* Ensure "is_leader", MCP command sequence and
9494                          * "recovery_state" update values are seen on other
9495                          * CPUs.
9496                          */
9497                         smp_mb();
9498                         break;
9499
9500                 case BNX2X_RECOVERY_WAIT:
9501                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9502                         if (bp->is_leader) {
9503                                 int other_engine = BP_PATH(bp) ? 0 : 1;
9504                                 bool other_load_status =
9505                                         bnx2x_get_load_status(bp, other_engine);
9506                                 bool load_status =
9507                                         bnx2x_get_load_status(bp, BP_PATH(bp));
9508                                 global = bnx2x_reset_is_global(bp);
9509
9510                                 /*
9511                                  * In case of a parity in a global block, let
9512                                  * the first leader that performs a
9513                                  * leader_reset() reset the global blocks in
9514                                  * order to clear global attentions. Otherwise
9515                                  * the gates will remain closed for that
9516                                  * engine.
9517                                  */
9518                                 if (load_status ||
9519                                     (global && other_load_status)) {
9520                                         /* Wait until all other functions get
9521                                          * down.
9522                                          */
9523                                         schedule_delayed_work(&bp->sp_rtnl_task,
9524                                                                 HZ/10);
9525                                         return;
9526                                 } else {
9527                                         /* If all other functions got down -
9528                                          * try to bring the chip back to
9529                                          * normal. In any case it's an exit
9530                                          * point for a leader.
9531                                          */
9532                                         if (bnx2x_leader_reset(bp)) {
9533                                                 bnx2x_recovery_failed(bp);
9534                                                 return;
9535                                         }
9536
9537                                         /* If we are here, means that the
9538                                          * leader has succeeded and doesn't
9539                                          * want to be a leader any more. Try
9540                                          * to continue as a none-leader.
9541                                          */
9542                                         break;
9543                                 }
9544                         } else { /* non-leader */
9545                                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9546                                         /* Try to get a LEADER_LOCK HW lock as
9547                                          * long as a former leader may have
9548                                          * been unloaded by the user or
9549                                          * released a leadership by another
9550                                          * reason.
9551                                          */
9552                                         if (bnx2x_trylock_leader_lock(bp)) {
9553                                                 /* I'm a leader now! Restart a
9554                                                  * switch case.
9555                                                  */
9556                                                 bp->is_leader = 1;
9557                                                 break;
9558                                         }
9559
9560                                         schedule_delayed_work(&bp->sp_rtnl_task,
9561                                                                 HZ/10);
9562                                         return;
9563
9564                                 } else {
9565                                         /*
9566                                          * If there was a global attention, wait
9567                                          * for it to be cleared.
9568                                          */
9569                                         if (bnx2x_reset_is_global(bp)) {
9570                                                 schedule_delayed_work(
9571                                                         &bp->sp_rtnl_task,
9572                                                         HZ/10);
9573                                                 return;
9574                                         }
9575
9576                                         error_recovered =
9577                                           bp->eth_stats.recoverable_error;
9578                                         error_unrecovered =
9579                                           bp->eth_stats.unrecoverable_error;
9580                                         bp->recovery_state =
9581                                                 BNX2X_RECOVERY_NIC_LOADING;
9582                                         if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9583                                                 error_unrecovered++;
9584                                                 netdev_err(bp->dev,
9585                                                            "Recovery failed. Power cycle needed\n");
9586                                                 /* Disconnect this device */
9587                                                 netif_device_detach(bp->dev);
9588                                                 /* Shut down the power */
9589                                                 bnx2x_set_power_state(
9590                                                         bp, PCI_D3hot);
9591                                                 smp_mb();
9592                                         } else {
9593                                                 bp->recovery_state =
9594                                                         BNX2X_RECOVERY_DONE;
9595                                                 error_recovered++;
9596                                                 smp_mb();
9597                                         }
9598                                         bp->eth_stats.recoverable_error =
9599                                                 error_recovered;
9600                                         bp->eth_stats.unrecoverable_error =
9601                                                 error_unrecovered;
9602
9603                                         return;
9604                                 }
9605                         }
9606                 default:
9607                         return;
9608                 }
9609         }
9610 }
9611
9612 static int bnx2x_close(struct net_device *dev);
9613
9614 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9615  * scheduled on a general queue in order to prevent a dead lock.
9616  */
9617 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9618 {
9619         struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9620
9621         rtnl_lock();
9622
9623         if (!netif_running(bp->dev)) {
9624                 rtnl_unlock();
9625                 return;
9626         }
9627
9628         if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9629 #ifdef BNX2X_STOP_ON_ERROR
9630                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9631                           "you will need to reboot when done\n");
9632                 goto sp_rtnl_not_reset;
9633 #endif
9634                 /*
9635                  * Clear all pending SP commands as we are going to reset the
9636                  * function anyway.
9637                  */
9638                 bp->sp_rtnl_state = 0;
9639                 smp_mb();
9640
9641                 bnx2x_parity_recover(bp);
9642
9643                 rtnl_unlock();
9644                 return;
9645         }
9646
9647         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
9648 #ifdef BNX2X_STOP_ON_ERROR
9649                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9650                           "you will need to reboot when done\n");
9651                 goto sp_rtnl_not_reset;
9652 #endif
9653
9654                 /*
9655                  * Clear all pending SP commands as we are going to reset the
9656                  * function anyway.
9657                  */
9658                 bp->sp_rtnl_state = 0;
9659                 smp_mb();
9660
9661                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
9662                 bnx2x_nic_load(bp, LOAD_NORMAL);
9663
9664                 rtnl_unlock();
9665                 return;
9666         }
9667 #ifdef BNX2X_STOP_ON_ERROR
9668 sp_rtnl_not_reset:
9669 #endif
9670         if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9671                 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
9672         if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9673                 bnx2x_after_function_update(bp);
9674         /*
9675          * in case of fan failure we need to reset id if the "stop on error"
9676          * debug flag is set, since we trying to prevent permanent overheating
9677          * damage
9678          */
9679         if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
9680                 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
9681                 netif_device_detach(bp->dev);
9682                 bnx2x_close(bp->dev);
9683                 rtnl_unlock();
9684                 return;
9685         }
9686
9687         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
9688                 DP(BNX2X_MSG_SP,
9689                    "sending set mcast vf pf channel message from rtnl sp-task\n");
9690                 bnx2x_vfpf_set_mcast(bp->dev);
9691         }
9692         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
9693                                &bp->sp_rtnl_state)){
9694                 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
9695                         bnx2x_tx_disable(bp);
9696                         BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
9697                 }
9698         }
9699
9700         if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
9701                 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
9702                 bnx2x_set_rx_mode_inner(bp);
9703         }
9704
9705         if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
9706                                &bp->sp_rtnl_state))
9707                 bnx2x_pf_set_vfs_vlan(bp);
9708
9709         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state))
9710                 bnx2x_dcbx_stop_hw_tx(bp);
9711
9712         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_RESUME, &bp->sp_rtnl_state))
9713                 bnx2x_dcbx_resume_hw_tx(bp);
9714
9715         /* work which needs rtnl lock not-taken (as it takes the lock itself and
9716          * can be called from other contexts as well)
9717          */
9718         rtnl_unlock();
9719
9720         /* enable SR-IOV if applicable */
9721         if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
9722                                                &bp->sp_rtnl_state)) {
9723                 bnx2x_disable_sriov(bp);
9724                 bnx2x_enable_sriov(bp);
9725         }
9726 }
9727
9728 static void bnx2x_period_task(struct work_struct *work)
9729 {
9730         struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9731
9732         if (!netif_running(bp->dev))
9733                 goto period_task_exit;
9734
9735         if (CHIP_REV_IS_SLOW(bp)) {
9736                 BNX2X_ERR("period task called on emulation, ignoring\n");
9737                 goto period_task_exit;
9738         }
9739
9740         bnx2x_acquire_phy_lock(bp);
9741         /*
9742          * The barrier is needed to ensure the ordering between the writing to
9743          * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9744          * the reading here.
9745          */
9746         smp_mb();
9747         if (bp->port.pmf) {
9748                 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9749
9750                 /* Re-queue task in 1 sec */
9751                 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9752         }
9753
9754         bnx2x_release_phy_lock(bp);
9755 period_task_exit:
9756         return;
9757 }
9758
9759 /*
9760  * Init service functions
9761  */
9762
9763 u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
9764 {
9765         u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9766         u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9767         return base + (BP_ABS_FUNC(bp)) * stride;
9768 }
9769
9770 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
9771                                         struct bnx2x_mac_vals *vals)
9772 {
9773         u32 val, base_addr, offset, mask, reset_reg;
9774         bool mac_stopped = false;
9775         u8 port = BP_PORT(bp);
9776
9777         /* reset addresses as they also mark which values were changed */
9778         vals->bmac_addr = 0;
9779         vals->umac_addr = 0;
9780         vals->xmac_addr = 0;
9781         vals->emac_addr = 0;
9782
9783         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
9784
9785         if (!CHIP_IS_E3(bp)) {
9786                 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9787                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9788                 if ((mask & reset_reg) && val) {
9789                         u32 wb_data[2];
9790                         BNX2X_DEV_INFO("Disable bmac Rx\n");
9791                         base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9792                                                 : NIG_REG_INGRESS_BMAC0_MEM;
9793                         offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9794                                                 : BIGMAC_REGISTER_BMAC_CONTROL;
9795
9796                         /*
9797                          * use rd/wr since we cannot use dmae. This is safe
9798                          * since MCP won't access the bus due to the request
9799                          * to unload, and no function on the path can be
9800                          * loaded at this time.
9801                          */
9802                         wb_data[0] = REG_RD(bp, base_addr + offset);
9803                         wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
9804                         vals->bmac_addr = base_addr + offset;
9805                         vals->bmac_val[0] = wb_data[0];
9806                         vals->bmac_val[1] = wb_data[1];
9807                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
9808                         REG_WR(bp, vals->bmac_addr, wb_data[0]);
9809                         REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
9810                 }
9811                 BNX2X_DEV_INFO("Disable emac Rx\n");
9812                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
9813                 vals->emac_val = REG_RD(bp, vals->emac_addr);
9814                 REG_WR(bp, vals->emac_addr, 0);
9815                 mac_stopped = true;
9816         } else {
9817                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9818                         BNX2X_DEV_INFO("Disable xmac Rx\n");
9819                         base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9820                         val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9821                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9822                                val & ~(1 << 1));
9823                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9824                                val | (1 << 1));
9825                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9826                         vals->xmac_val = REG_RD(bp, vals->xmac_addr);
9827                         REG_WR(bp, vals->xmac_addr, 0);
9828                         mac_stopped = true;
9829                 }
9830                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9831                 if (mask & reset_reg) {
9832                         BNX2X_DEV_INFO("Disable umac Rx\n");
9833                         base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9834                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9835                         vals->umac_val = REG_RD(bp, vals->umac_addr);
9836                         REG_WR(bp, vals->umac_addr, 0);
9837                         mac_stopped = true;
9838                 }
9839         }
9840
9841         if (mac_stopped)
9842                 msleep(20);
9843 }
9844
9845 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9846 #define BNX2X_PREV_UNDI_RCQ(val)        ((val) & 0xffff)
9847 #define BNX2X_PREV_UNDI_BD(val)         ((val) >> 16 & 0xffff)
9848 #define BNX2X_PREV_UNDI_PROD(rcq, bd)   ((bd) << 16 | (rcq))
9849
9850 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc)
9851 {
9852         u16 rcq, bd;
9853         u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
9854
9855         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9856         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9857
9858         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9859         REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9860
9861         BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9862                        port, bd, rcq);
9863 }
9864
9865 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
9866 {
9867         u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
9868                                   DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9869         if (!rc) {
9870                 BNX2X_ERR("MCP response failure, aborting\n");
9871                 return -EBUSY;
9872         }
9873
9874         return 0;
9875 }
9876
9877 static struct bnx2x_prev_path_list *
9878                 bnx2x_prev_path_get_entry(struct bnx2x *bp)
9879 {
9880         struct bnx2x_prev_path_list *tmp_list;
9881
9882         list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
9883                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9884                     bp->pdev->bus->number == tmp_list->bus &&
9885                     BP_PATH(bp) == tmp_list->path)
9886                         return tmp_list;
9887
9888         return NULL;
9889 }
9890
9891 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
9892 {
9893         struct bnx2x_prev_path_list *tmp_list;
9894         int rc;
9895
9896         rc = down_interruptible(&bnx2x_prev_sem);
9897         if (rc) {
9898                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9899                 return rc;
9900         }
9901
9902         tmp_list = bnx2x_prev_path_get_entry(bp);
9903         if (tmp_list) {
9904                 tmp_list->aer = 1;
9905                 rc = 0;
9906         } else {
9907                 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
9908                           BP_PATH(bp));
9909         }
9910
9911         up(&bnx2x_prev_sem);
9912
9913         return rc;
9914 }
9915
9916 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
9917 {
9918         struct bnx2x_prev_path_list *tmp_list;
9919         bool rc = false;
9920
9921         if (down_trylock(&bnx2x_prev_sem))
9922                 return false;
9923
9924         tmp_list = bnx2x_prev_path_get_entry(bp);
9925         if (tmp_list) {
9926                 if (tmp_list->aer) {
9927                         DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
9928                            BP_PATH(bp));
9929                 } else {
9930                         rc = true;
9931                         BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
9932                                        BP_PATH(bp));
9933                 }
9934         }
9935
9936         up(&bnx2x_prev_sem);
9937
9938         return rc;
9939 }
9940
9941 bool bnx2x_port_after_undi(struct bnx2x *bp)
9942 {
9943         struct bnx2x_prev_path_list *entry;
9944         bool val;
9945
9946         down(&bnx2x_prev_sem);
9947
9948         entry = bnx2x_prev_path_get_entry(bp);
9949         val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
9950
9951         up(&bnx2x_prev_sem);
9952
9953         return val;
9954 }
9955
9956 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
9957 {
9958         struct bnx2x_prev_path_list *tmp_list;
9959         int rc;
9960
9961         rc = down_interruptible(&bnx2x_prev_sem);
9962         if (rc) {
9963                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9964                 return rc;
9965         }
9966
9967         /* Check whether the entry for this path already exists */
9968         tmp_list = bnx2x_prev_path_get_entry(bp);
9969         if (tmp_list) {
9970                 if (!tmp_list->aer) {
9971                         BNX2X_ERR("Re-Marking the path.\n");
9972                 } else {
9973                         DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
9974                            BP_PATH(bp));
9975                         tmp_list->aer = 0;
9976                 }
9977                 up(&bnx2x_prev_sem);
9978                 return 0;
9979         }
9980         up(&bnx2x_prev_sem);
9981
9982         /* Create an entry for this path and add it */
9983         tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
9984         if (!tmp_list) {
9985                 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
9986                 return -ENOMEM;
9987         }
9988
9989         tmp_list->bus = bp->pdev->bus->number;
9990         tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
9991         tmp_list->path = BP_PATH(bp);
9992         tmp_list->aer = 0;
9993         tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
9994
9995         rc = down_interruptible(&bnx2x_prev_sem);
9996         if (rc) {
9997                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9998                 kfree(tmp_list);
9999         } else {
10000                 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10001                    BP_PATH(bp));
10002                 list_add(&tmp_list->list, &bnx2x_prev_list);
10003                 up(&bnx2x_prev_sem);
10004         }
10005
10006         return rc;
10007 }
10008
10009 static int bnx2x_do_flr(struct bnx2x *bp)
10010 {
10011         struct pci_dev *dev = bp->pdev;
10012
10013         if (CHIP_IS_E1x(bp)) {
10014                 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10015                 return -EINVAL;
10016         }
10017
10018         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10019         if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10020                 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10021                           bp->common.bc_ver);
10022                 return -EINVAL;
10023         }
10024
10025         if (!pci_wait_for_pending_transaction(dev))
10026                 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
10027
10028         BNX2X_DEV_INFO("Initiating FLR\n");
10029         bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10030
10031         return 0;
10032 }
10033
10034 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
10035 {
10036         int rc;
10037
10038         BNX2X_DEV_INFO("Uncommon unload Flow\n");
10039
10040         /* Test if previous unload process was already finished for this path */
10041         if (bnx2x_prev_is_path_marked(bp))
10042                 return bnx2x_prev_mcp_done(bp);
10043
10044         BNX2X_DEV_INFO("Path is unmarked\n");
10045
10046         /* If function has FLR capabilities, and existing FW version matches
10047          * the one required, then FLR will be sufficient to clean any residue
10048          * left by previous driver
10049          */
10050         rc = bnx2x_nic_load_analyze_req(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION);
10051
10052         if (!rc) {
10053                 /* fw version is good */
10054                 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10055                 rc = bnx2x_do_flr(bp);
10056         }
10057
10058         if (!rc) {
10059                 /* FLR was performed */
10060                 BNX2X_DEV_INFO("FLR successful\n");
10061                 return 0;
10062         }
10063
10064         BNX2X_DEV_INFO("Could not FLR\n");
10065
10066         /* Close the MCP request, return failure*/
10067         rc = bnx2x_prev_mcp_done(bp);
10068         if (!rc)
10069                 rc = BNX2X_PREV_WAIT_NEEDED;
10070
10071         return rc;
10072 }
10073
10074 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10075 {
10076         u32 reset_reg, tmp_reg = 0, rc;
10077         bool prev_undi = false;
10078         struct bnx2x_mac_vals mac_vals;
10079
10080         /* It is possible a previous function received 'common' answer,
10081          * but hasn't loaded yet, therefore creating a scenario of
10082          * multiple functions receiving 'common' on the same path.
10083          */
10084         BNX2X_DEV_INFO("Common unload Flow\n");
10085
10086         memset(&mac_vals, 0, sizeof(mac_vals));
10087
10088         if (bnx2x_prev_is_path_marked(bp))
10089                 return bnx2x_prev_mcp_done(bp);
10090
10091         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10092
10093         /* Reset should be performed after BRB is emptied */
10094         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10095                 u32 timer_count = 1000;
10096
10097                 /* Close the MAC Rx to prevent BRB from filling up */
10098                 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10099
10100                 /* close LLH filters towards the BRB */
10101                 bnx2x_set_rx_filter(&bp->link_params, 0);
10102
10103                 /* Check if the UNDI driver was previously loaded
10104                  * UNDI driver initializes CID offset for normal bell to 0x7
10105                  */
10106                 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
10107                         tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
10108                         if (tmp_reg == 0x7) {
10109                                 BNX2X_DEV_INFO("UNDI previously loaded\n");
10110                                 prev_undi = true;
10111                                 /* clear the UNDI indication */
10112                                 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10113                                 /* clear possible idle check errors */
10114                                 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10115                         }
10116                 }
10117                 if (!CHIP_IS_E1x(bp))
10118                         /* block FW from writing to host */
10119                         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10120
10121                 /* wait until BRB is empty */
10122                 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10123                 while (timer_count) {
10124                         u32 prev_brb = tmp_reg;
10125
10126                         tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10127                         if (!tmp_reg)
10128                                 break;
10129
10130                         BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10131
10132                         /* reset timer as long as BRB actually gets emptied */
10133                         if (prev_brb > tmp_reg)
10134                                 timer_count = 1000;
10135                         else
10136                                 timer_count--;
10137
10138                         /* If UNDI resides in memory, manually increment it */
10139                         if (prev_undi)
10140                                 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
10141
10142                         udelay(10);
10143                 }
10144
10145                 if (!timer_count)
10146                         BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10147         }
10148
10149         /* No packets are in the pipeline, path is ready for reset */
10150         bnx2x_reset_common(bp);
10151
10152         if (mac_vals.xmac_addr)
10153                 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10154         if (mac_vals.umac_addr)
10155                 REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val);
10156         if (mac_vals.emac_addr)
10157                 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10158         if (mac_vals.bmac_addr) {
10159                 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10160                 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10161         }
10162
10163         rc = bnx2x_prev_mark_path(bp, prev_undi);
10164         if (rc) {
10165                 bnx2x_prev_mcp_done(bp);
10166                 return rc;
10167         }
10168
10169         return bnx2x_prev_mcp_done(bp);
10170 }
10171
10172 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
10173  * and boot began, or when kdump kernel was loaded. Either case would invalidate
10174  * the addresses of the transaction, resulting in was-error bit set in the pci
10175  * causing all hw-to-host pcie transactions to timeout. If this happened we want
10176  * to clear the interrupt which detected this from the pglueb and the was done
10177  * bit
10178  */
10179 static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
10180 {
10181         if (!CHIP_IS_E1x(bp)) {
10182                 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
10183                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
10184                         DP(BNX2X_MSG_SP,
10185                            "'was error' bit was found to be set in pglueb upon startup. Clearing\n");
10186                         REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
10187                                1 << BP_FUNC(bp));
10188                 }
10189         }
10190 }
10191
10192 static int bnx2x_prev_unload(struct bnx2x *bp)
10193 {
10194         int time_counter = 10;
10195         u32 rc, fw, hw_lock_reg, hw_lock_val;
10196         BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10197
10198         /* clear hw from errors which may have resulted from an interrupted
10199          * dmae transaction.
10200          */
10201         bnx2x_prev_interrupted_dmae(bp);
10202
10203         /* Release previously held locks */
10204         hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10205                       (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10206                       (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10207
10208         hw_lock_val = REG_RD(bp, hw_lock_reg);
10209         if (hw_lock_val) {
10210                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10211                         BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10212                         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10213                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10214                 }
10215
10216                 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10217                 REG_WR(bp, hw_lock_reg, 0xffffffff);
10218         } else
10219                 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10220
10221         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10222                 BNX2X_DEV_INFO("Release previously held alr\n");
10223                 bnx2x_release_alr(bp);
10224         }
10225
10226         do {
10227                 int aer = 0;
10228                 /* Lock MCP using an unload request */
10229                 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10230                 if (!fw) {
10231                         BNX2X_ERR("MCP response failure, aborting\n");
10232                         rc = -EBUSY;
10233                         break;
10234                 }
10235
10236                 rc = down_interruptible(&bnx2x_prev_sem);
10237                 if (rc) {
10238                         BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10239                                   rc);
10240                 } else {
10241                         /* If Path is marked by EEH, ignore unload status */
10242                         aer = !!(bnx2x_prev_path_get_entry(bp) &&
10243                                  bnx2x_prev_path_get_entry(bp)->aer);
10244                         up(&bnx2x_prev_sem);
10245                 }
10246
10247                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10248                         rc = bnx2x_prev_unload_common(bp);
10249                         break;
10250                 }
10251
10252                 /* non-common reply from MCP might require looping */
10253                 rc = bnx2x_prev_unload_uncommon(bp);
10254                 if (rc != BNX2X_PREV_WAIT_NEEDED)
10255                         break;
10256
10257                 msleep(20);
10258         } while (--time_counter);
10259
10260         if (!time_counter || rc) {
10261                 BNX2X_ERR("Failed unloading previous driver, aborting\n");
10262                 rc = -EBUSY;
10263         }
10264
10265         /* Mark function if its port was used to boot from SAN */
10266         if (bnx2x_port_after_undi(bp))
10267                 bp->link_params.feature_config_flags |=
10268                         FEATURE_CONFIG_BOOT_FROM_SAN;
10269
10270         BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10271
10272         return rc;
10273 }
10274
10275 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10276 {
10277         u32 val, val2, val3, val4, id, boot_mode;
10278         u16 pmc;
10279
10280         /* Get the chip revision id and number. */
10281         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10282         val = REG_RD(bp, MISC_REG_CHIP_NUM);
10283         id = ((val & 0xffff) << 16);
10284         val = REG_RD(bp, MISC_REG_CHIP_REV);
10285         id |= ((val & 0xf) << 12);
10286
10287         /* Metal is read from PCI regs, but we can't access >=0x400 from
10288          * the configuration space (so we need to reg_rd)
10289          */
10290         val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10291         id |= (((val >> 24) & 0xf) << 4);
10292         val = REG_RD(bp, MISC_REG_BOND_ID);
10293         id |= (val & 0xf);
10294         bp->common.chip_id = id;
10295
10296         /* force 57811 according to MISC register */
10297         if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10298                 if (CHIP_IS_57810(bp))
10299                         bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10300                                 (bp->common.chip_id & 0x0000FFFF);
10301                 else if (CHIP_IS_57810_MF(bp))
10302                         bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10303                                 (bp->common.chip_id & 0x0000FFFF);
10304                 bp->common.chip_id |= 0x1;
10305         }
10306
10307         /* Set doorbell size */
10308         bp->db_size = (1 << BNX2X_DB_SHIFT);
10309
10310         if (!CHIP_IS_E1x(bp)) {
10311                 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10312                 if ((val & 1) == 0)
10313                         val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10314                 else
10315                         val = (val >> 1) & 1;
10316                 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10317                                                        "2_PORT_MODE");
10318                 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10319                                                  CHIP_2_PORT_MODE;
10320
10321                 if (CHIP_MODE_IS_4_PORT(bp))
10322                         bp->pfid = (bp->pf_num >> 1);   /* 0..3 */
10323                 else
10324                         bp->pfid = (bp->pf_num & 0x6);  /* 0, 2, 4, 6 */
10325         } else {
10326                 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10327                 bp->pfid = bp->pf_num;                  /* 0..7 */
10328         }
10329
10330         BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10331
10332         bp->link_params.chip_id = bp->common.chip_id;
10333         BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10334
10335         val = (REG_RD(bp, 0x2874) & 0x55);
10336         if ((bp->common.chip_id & 0x1) ||
10337             (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10338                 bp->flags |= ONE_PORT_FLAG;
10339                 BNX2X_DEV_INFO("single port device\n");
10340         }
10341
10342         val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10343         bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10344                                  (val & MCPR_NVM_CFG4_FLASH_SIZE));
10345         BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10346                        bp->common.flash_size, bp->common.flash_size);
10347
10348         bnx2x_init_shmem(bp);
10349
10350         bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10351                                         MISC_REG_GENERIC_CR_1 :
10352                                         MISC_REG_GENERIC_CR_0));
10353
10354         bp->link_params.shmem_base = bp->common.shmem_base;
10355         bp->link_params.shmem2_base = bp->common.shmem2_base;
10356         if (SHMEM2_RD(bp, size) >
10357             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10358                 bp->link_params.lfa_base =
10359                 REG_RD(bp, bp->common.shmem2_base +
10360                        (u32)offsetof(struct shmem2_region,
10361                                      lfa_host_addr[BP_PORT(bp)]));
10362         else
10363                 bp->link_params.lfa_base = 0;
10364         BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
10365                        bp->common.shmem_base, bp->common.shmem2_base);
10366
10367         if (!bp->common.shmem_base) {
10368                 BNX2X_DEV_INFO("MCP not active\n");
10369                 bp->flags |= NO_MCP_FLAG;
10370                 return;
10371         }
10372
10373         bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10374         BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10375
10376         bp->link_params.hw_led_mode = ((bp->common.hw_config &
10377                                         SHARED_HW_CFG_LED_MODE_MASK) >>
10378                                        SHARED_HW_CFG_LED_MODE_SHIFT);
10379
10380         bp->link_params.feature_config_flags = 0;
10381         val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10382         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10383                 bp->link_params.feature_config_flags |=
10384                                 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10385         else
10386                 bp->link_params.feature_config_flags &=
10387                                 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10388
10389         val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10390         bp->common.bc_ver = val;
10391         BNX2X_DEV_INFO("bc_ver %X\n", val);
10392         if (val < BNX2X_BC_VER) {
10393                 /* for now only warn
10394                  * later we might need to enforce this */
10395                 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10396                           BNX2X_BC_VER, val);
10397         }
10398         bp->link_params.feature_config_flags |=
10399                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10400                                 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10401
10402         bp->link_params.feature_config_flags |=
10403                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10404                 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10405         bp->link_params.feature_config_flags |=
10406                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10407                 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
10408         bp->link_params.feature_config_flags |=
10409                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10410                 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
10411
10412         bp->link_params.feature_config_flags |=
10413                 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10414                 FEATURE_CONFIG_MT_SUPPORT : 0;
10415
10416         bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10417                         BC_SUPPORTS_PFC_STATS : 0;
10418
10419         bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10420                         BC_SUPPORTS_FCOE_FEATURES : 0;
10421
10422         bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10423                         BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
10424
10425         bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
10426                         BC_SUPPORTS_RMMOD_CMD : 0;
10427
10428         boot_mode = SHMEM_RD(bp,
10429                         dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10430                         PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10431         switch (boot_mode) {
10432         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10433                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10434                 break;
10435         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10436                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10437                 break;
10438         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10439                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10440                 break;
10441         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10442                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10443                 break;
10444         }
10445
10446         pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
10447         bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10448
10449         BNX2X_DEV_INFO("%sWoL capable\n",
10450                        (bp->flags & NO_WOL_FLAG) ? "not " : "");
10451
10452         val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10453         val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10454         val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10455         val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10456
10457         dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10458                  val, val2, val3, val4);
10459 }
10460
10461 #define IGU_FID(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10462 #define IGU_VEC(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10463
10464 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10465 {
10466         int pfid = BP_FUNC(bp);
10467         int igu_sb_id;
10468         u32 val;
10469         u8 fid, igu_sb_cnt = 0;
10470
10471         bp->igu_base_sb = 0xff;
10472         if (CHIP_INT_MODE_IS_BC(bp)) {
10473                 int vn = BP_VN(bp);
10474                 igu_sb_cnt = bp->igu_sb_cnt;
10475                 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10476                         FP_SB_MAX_E1x;
10477
10478                 bp->igu_dsb_id =  E1HVN_MAX * FP_SB_MAX_E1x +
10479                         (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10480
10481                 return 0;
10482         }
10483
10484         /* IGU in normal mode - read CAM */
10485         for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10486              igu_sb_id++) {
10487                 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10488                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10489                         continue;
10490                 fid = IGU_FID(val);
10491                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10492                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10493                                 continue;
10494                         if (IGU_VEC(val) == 0)
10495                                 /* default status block */
10496                                 bp->igu_dsb_id = igu_sb_id;
10497                         else {
10498                                 if (bp->igu_base_sb == 0xff)
10499                                         bp->igu_base_sb = igu_sb_id;
10500                                 igu_sb_cnt++;
10501                         }
10502                 }
10503         }
10504
10505 #ifdef CONFIG_PCI_MSI
10506         /* Due to new PF resource allocation by MFW T7.4 and above, it's
10507          * optional that number of CAM entries will not be equal to the value
10508          * advertised in PCI.
10509          * Driver should use the minimal value of both as the actual status
10510          * block count
10511          */
10512         bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10513 #endif
10514
10515         if (igu_sb_cnt == 0) {
10516                 BNX2X_ERR("CAM configuration error\n");
10517                 return -EINVAL;
10518         }
10519
10520         return 0;
10521 }
10522
10523 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10524 {
10525         int cfg_size = 0, idx, port = BP_PORT(bp);
10526
10527         /* Aggregation of supported attributes of all external phys */
10528         bp->port.supported[0] = 0;
10529         bp->port.supported[1] = 0;
10530         switch (bp->link_params.num_phys) {
10531         case 1:
10532                 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10533                 cfg_size = 1;
10534                 break;
10535         case 2:
10536                 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10537                 cfg_size = 1;
10538                 break;
10539         case 3:
10540                 if (bp->link_params.multi_phy_config &
10541                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10542                         bp->port.supported[1] =
10543                                 bp->link_params.phy[EXT_PHY1].supported;
10544                         bp->port.supported[0] =
10545                                 bp->link_params.phy[EXT_PHY2].supported;
10546                 } else {
10547                         bp->port.supported[0] =
10548                                 bp->link_params.phy[EXT_PHY1].supported;
10549                         bp->port.supported[1] =
10550                                 bp->link_params.phy[EXT_PHY2].supported;
10551                 }
10552                 cfg_size = 2;
10553                 break;
10554         }
10555
10556         if (!(bp->port.supported[0] || bp->port.supported[1])) {
10557                 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10558                            SHMEM_RD(bp,
10559                            dev_info.port_hw_config[port].external_phy_config),
10560                            SHMEM_RD(bp,
10561                            dev_info.port_hw_config[port].external_phy_config2));
10562                         return;
10563         }
10564
10565         if (CHIP_IS_E3(bp))
10566                 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10567         else {
10568                 switch (switch_cfg) {
10569                 case SWITCH_CFG_1G:
10570                         bp->port.phy_addr = REG_RD(
10571                                 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10572                         break;
10573                 case SWITCH_CFG_10G:
10574                         bp->port.phy_addr = REG_RD(
10575                                 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10576                         break;
10577                 default:
10578                         BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10579                                   bp->port.link_config[0]);
10580                         return;
10581                 }
10582         }
10583         BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
10584         /* mask what we support according to speed_cap_mask per configuration */
10585         for (idx = 0; idx < cfg_size; idx++) {
10586                 if (!(bp->link_params.speed_cap_mask[idx] &
10587                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
10588                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
10589
10590                 if (!(bp->link_params.speed_cap_mask[idx] &
10591                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
10592                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
10593
10594                 if (!(bp->link_params.speed_cap_mask[idx] &
10595                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
10596                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
10597
10598                 if (!(bp->link_params.speed_cap_mask[idx] &
10599                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
10600                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
10601
10602                 if (!(bp->link_params.speed_cap_mask[idx] &
10603                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
10604                         bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
10605                                                      SUPPORTED_1000baseT_Full);
10606
10607                 if (!(bp->link_params.speed_cap_mask[idx] &
10608                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
10609                         bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
10610
10611                 if (!(bp->link_params.speed_cap_mask[idx] &
10612                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
10613                         bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
10614
10615                 if (!(bp->link_params.speed_cap_mask[idx] &
10616                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
10617                         bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
10618         }
10619
10620         BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10621                        bp->port.supported[1]);
10622 }
10623
10624 static void bnx2x_link_settings_requested(struct bnx2x *bp)
10625 {
10626         u32 link_config, idx, cfg_size = 0;
10627         bp->port.advertising[0] = 0;
10628         bp->port.advertising[1] = 0;
10629         switch (bp->link_params.num_phys) {
10630         case 1:
10631         case 2:
10632                 cfg_size = 1;
10633                 break;
10634         case 3:
10635                 cfg_size = 2;
10636                 break;
10637         }
10638         for (idx = 0; idx < cfg_size; idx++) {
10639                 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
10640                 link_config = bp->port.link_config[idx];
10641                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
10642                 case PORT_FEATURE_LINK_SPEED_AUTO:
10643                         if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
10644                                 bp->link_params.req_line_speed[idx] =
10645                                         SPEED_AUTO_NEG;
10646                                 bp->port.advertising[idx] |=
10647                                         bp->port.supported[idx];
10648                                 if (bp->link_params.phy[EXT_PHY1].type ==
10649                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10650                                         bp->port.advertising[idx] |=
10651                                         (SUPPORTED_100baseT_Half |
10652                                          SUPPORTED_100baseT_Full);
10653                         } else {
10654                                 /* force 10G, no AN */
10655                                 bp->link_params.req_line_speed[idx] =
10656                                         SPEED_10000;
10657                                 bp->port.advertising[idx] |=
10658                                         (ADVERTISED_10000baseT_Full |
10659                                          ADVERTISED_FIBRE);
10660                                 continue;
10661                         }
10662                         break;
10663
10664                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
10665                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
10666                                 bp->link_params.req_line_speed[idx] =
10667                                         SPEED_10;
10668                                 bp->port.advertising[idx] |=
10669                                         (ADVERTISED_10baseT_Full |
10670                                          ADVERTISED_TP);
10671                         } else {
10672                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10673                                             link_config,
10674                                     bp->link_params.speed_cap_mask[idx]);
10675                                 return;
10676                         }
10677                         break;
10678
10679                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
10680                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10681                                 bp->link_params.req_line_speed[idx] =
10682                                         SPEED_10;
10683                                 bp->link_params.req_duplex[idx] =
10684                                         DUPLEX_HALF;
10685                                 bp->port.advertising[idx] |=
10686                                         (ADVERTISED_10baseT_Half |
10687                                          ADVERTISED_TP);
10688                         } else {
10689                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10690                                             link_config,
10691                                           bp->link_params.speed_cap_mask[idx]);
10692                                 return;
10693                         }
10694                         break;
10695
10696                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10697                         if (bp->port.supported[idx] &
10698                             SUPPORTED_100baseT_Full) {
10699                                 bp->link_params.req_line_speed[idx] =
10700                                         SPEED_100;
10701                                 bp->port.advertising[idx] |=
10702                                         (ADVERTISED_100baseT_Full |
10703                                          ADVERTISED_TP);
10704                         } else {
10705                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10706                                             link_config,
10707                                           bp->link_params.speed_cap_mask[idx]);
10708                                 return;
10709                         }
10710                         break;
10711
10712                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10713                         if (bp->port.supported[idx] &
10714                             SUPPORTED_100baseT_Half) {
10715                                 bp->link_params.req_line_speed[idx] =
10716                                                                 SPEED_100;
10717                                 bp->link_params.req_duplex[idx] =
10718                                                                 DUPLEX_HALF;
10719                                 bp->port.advertising[idx] |=
10720                                         (ADVERTISED_100baseT_Half |
10721                                          ADVERTISED_TP);
10722                         } else {
10723                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10724                                     link_config,
10725                                     bp->link_params.speed_cap_mask[idx]);
10726                                 return;
10727                         }
10728                         break;
10729
10730                 case PORT_FEATURE_LINK_SPEED_1G:
10731                         if (bp->port.supported[idx] &
10732                             SUPPORTED_1000baseT_Full) {
10733                                 bp->link_params.req_line_speed[idx] =
10734                                         SPEED_1000;
10735                                 bp->port.advertising[idx] |=
10736                                         (ADVERTISED_1000baseT_Full |
10737                                          ADVERTISED_TP);
10738                         } else {
10739                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10740                                     link_config,
10741                                     bp->link_params.speed_cap_mask[idx]);
10742                                 return;
10743                         }
10744                         break;
10745
10746                 case PORT_FEATURE_LINK_SPEED_2_5G:
10747                         if (bp->port.supported[idx] &
10748                             SUPPORTED_2500baseX_Full) {
10749                                 bp->link_params.req_line_speed[idx] =
10750                                         SPEED_2500;
10751                                 bp->port.advertising[idx] |=
10752                                         (ADVERTISED_2500baseX_Full |
10753                                                 ADVERTISED_TP);
10754                         } else {
10755                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10756                                     link_config,
10757                                     bp->link_params.speed_cap_mask[idx]);
10758                                 return;
10759                         }
10760                         break;
10761
10762                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
10763                         if (bp->port.supported[idx] &
10764                             SUPPORTED_10000baseT_Full) {
10765                                 bp->link_params.req_line_speed[idx] =
10766                                         SPEED_10000;
10767                                 bp->port.advertising[idx] |=
10768                                         (ADVERTISED_10000baseT_Full |
10769                                                 ADVERTISED_FIBRE);
10770                         } else {
10771                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10772                                     link_config,
10773                                     bp->link_params.speed_cap_mask[idx]);
10774                                 return;
10775                         }
10776                         break;
10777                 case PORT_FEATURE_LINK_SPEED_20G:
10778                         bp->link_params.req_line_speed[idx] = SPEED_20000;
10779
10780                         break;
10781                 default:
10782                         BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
10783                                   link_config);
10784                                 bp->link_params.req_line_speed[idx] =
10785                                                         SPEED_AUTO_NEG;
10786                                 bp->port.advertising[idx] =
10787                                                 bp->port.supported[idx];
10788                         break;
10789                 }
10790
10791                 bp->link_params.req_flow_ctrl[idx] = (link_config &
10792                                          PORT_FEATURE_FLOW_CONTROL_MASK);
10793                 if (bp->link_params.req_flow_ctrl[idx] ==
10794                     BNX2X_FLOW_CTRL_AUTO) {
10795                         if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
10796                                 bp->link_params.req_flow_ctrl[idx] =
10797                                                         BNX2X_FLOW_CTRL_NONE;
10798                         else
10799                                 bnx2x_set_requested_fc(bp);
10800                 }
10801
10802                 BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
10803                                bp->link_params.req_line_speed[idx],
10804                                bp->link_params.req_duplex[idx],
10805                                bp->link_params.req_flow_ctrl[idx],
10806                                bp->port.advertising[idx]);
10807         }
10808 }
10809
10810 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
10811 {
10812         __be16 mac_hi_be = cpu_to_be16(mac_hi);
10813         __be32 mac_lo_be = cpu_to_be32(mac_lo);
10814         memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
10815         memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
10816 }
10817
10818 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
10819 {
10820         int port = BP_PORT(bp);
10821         u32 config;
10822         u32 ext_phy_type, ext_phy_config, eee_mode;
10823
10824         bp->link_params.bp = bp;
10825         bp->link_params.port = port;
10826
10827         bp->link_params.lane_config =
10828                 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
10829
10830         bp->link_params.speed_cap_mask[0] =
10831                 SHMEM_RD(bp,
10832                          dev_info.port_hw_config[port].speed_capability_mask) &
10833                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
10834         bp->link_params.speed_cap_mask[1] =
10835                 SHMEM_RD(bp,
10836                          dev_info.port_hw_config[port].speed_capability_mask2) &
10837                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
10838         bp->port.link_config[0] =
10839                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
10840
10841         bp->port.link_config[1] =
10842                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
10843
10844         bp->link_params.multi_phy_config =
10845                 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
10846         /* If the device is capable of WoL, set the default state according
10847          * to the HW
10848          */
10849         config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
10850         bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
10851                    (config & PORT_FEATURE_WOL_ENABLED));
10852
10853         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10854             PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
10855                 bp->flags |= NO_ISCSI_FLAG;
10856         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10857             PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
10858                 bp->flags |= NO_FCOE_FLAG;
10859
10860         BNX2X_DEV_INFO("lane_config 0x%08x  speed_cap_mask0 0x%08x  link_config0 0x%08x\n",
10861                        bp->link_params.lane_config,
10862                        bp->link_params.speed_cap_mask[0],
10863                        bp->port.link_config[0]);
10864
10865         bp->link_params.switch_cfg = (bp->port.link_config[0] &
10866                                       PORT_FEATURE_CONNECTED_SWITCH_MASK);
10867         bnx2x_phy_probe(&bp->link_params);
10868         bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
10869
10870         bnx2x_link_settings_requested(bp);
10871
10872         /*
10873          * If connected directly, work with the internal PHY, otherwise, work
10874          * with the external PHY
10875          */
10876         ext_phy_config =
10877                 SHMEM_RD(bp,
10878                          dev_info.port_hw_config[port].external_phy_config);
10879         ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
10880         if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
10881                 bp->mdio.prtad = bp->port.phy_addr;
10882
10883         else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
10884                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
10885                 bp->mdio.prtad =
10886                         XGXS_EXT_PHY_ADDR(ext_phy_config);
10887
10888         /* Configure link feature according to nvram value */
10889         eee_mode = (((SHMEM_RD(bp, dev_info.
10890                       port_feature_config[port].eee_power_mode)) &
10891                      PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
10892                     PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
10893         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
10894                 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
10895                                            EEE_MODE_ENABLE_LPI |
10896                                            EEE_MODE_OUTPUT_TIME;
10897         } else {
10898                 bp->link_params.eee_mode = 0;
10899         }
10900 }
10901
10902 void bnx2x_get_iscsi_info(struct bnx2x *bp)
10903 {
10904         u32 no_flags = NO_ISCSI_FLAG;
10905         int port = BP_PORT(bp);
10906         u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10907                                 drv_lic_key[port].max_iscsi_conn);
10908
10909         if (!CNIC_SUPPORT(bp)) {
10910                 bp->flags |= no_flags;
10911                 return;
10912         }
10913
10914         /* Get the number of maximum allowed iSCSI connections */
10915         bp->cnic_eth_dev.max_iscsi_conn =
10916                 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
10917                 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
10918
10919         BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10920                        bp->cnic_eth_dev.max_iscsi_conn);
10921
10922         /*
10923          * If maximum allowed number of connections is zero -
10924          * disable the feature.
10925          */
10926         if (!bp->cnic_eth_dev.max_iscsi_conn)
10927                 bp->flags |= no_flags;
10928 }
10929
10930 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
10931 {
10932         /* Port info */
10933         bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10934                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
10935         bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10936                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
10937
10938         /* Node info */
10939         bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10940                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
10941         bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10942                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
10943 }
10944
10945 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
10946 {
10947         u8 count = 0;
10948
10949         if (IS_MF(bp)) {
10950                 u8 fid;
10951
10952                 /* iterate over absolute function ids for this path: */
10953                 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
10954                         if (IS_MF_SD(bp)) {
10955                                 u32 cfg = MF_CFG_RD(bp,
10956                                                     func_mf_config[fid].config);
10957
10958                                 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
10959                                     ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
10960                                             FUNC_MF_CFG_PROTOCOL_FCOE))
10961                                         count++;
10962                         } else {
10963                                 u32 cfg = MF_CFG_RD(bp,
10964                                                     func_ext_config[fid].
10965                                                                       func_cfg);
10966
10967                                 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
10968                                     (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
10969                                         count++;
10970                         }
10971                 }
10972         } else { /* SF */
10973                 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
10974
10975                 for (port = 0; port < port_cnt; port++) {
10976                         u32 lic = SHMEM_RD(bp,
10977                                            drv_lic_key[port].max_fcoe_conn) ^
10978                                   FW_ENCODE_32BIT_PATTERN;
10979                         if (lic)
10980                                 count++;
10981                 }
10982         }
10983
10984         return count;
10985 }
10986
10987 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
10988 {
10989         int port = BP_PORT(bp);
10990         int func = BP_ABS_FUNC(bp);
10991         u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10992                                 drv_lic_key[port].max_fcoe_conn);
10993         u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
10994
10995         if (!CNIC_SUPPORT(bp)) {
10996                 bp->flags |= NO_FCOE_FLAG;
10997                 return;
10998         }
10999
11000         /* Get the number of maximum allowed FCoE connections */
11001         bp->cnic_eth_dev.max_fcoe_conn =
11002                 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11003                 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11004
11005         /* Calculate the number of maximum allowed FCoE tasks */
11006         bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
11007
11008         /* check if FCoE resources must be shared between different functions */
11009         if (num_fcoe_func)
11010                 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
11011
11012         /* Read the WWN: */
11013         if (!IS_MF(bp)) {
11014                 /* Port info */
11015                 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11016                         SHMEM_RD(bp,
11017                                  dev_info.port_hw_config[port].
11018                                  fcoe_wwn_port_name_upper);
11019                 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11020                         SHMEM_RD(bp,
11021                                  dev_info.port_hw_config[port].
11022                                  fcoe_wwn_port_name_lower);
11023
11024                 /* Node info */
11025                 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11026                         SHMEM_RD(bp,
11027                                  dev_info.port_hw_config[port].
11028                                  fcoe_wwn_node_name_upper);
11029                 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11030                         SHMEM_RD(bp,
11031                                  dev_info.port_hw_config[port].
11032                                  fcoe_wwn_node_name_lower);
11033         } else if (!IS_MF_SD(bp)) {
11034                 /*
11035                  * Read the WWN info only if the FCoE feature is enabled for
11036                  * this function.
11037                  */
11038                 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
11039                         bnx2x_get_ext_wwn_info(bp, func);
11040
11041         } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) {
11042                 bnx2x_get_ext_wwn_info(bp, func);
11043         }
11044
11045         BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
11046
11047         /*
11048          * If maximum allowed number of connections is zero -
11049          * disable the feature.
11050          */
11051         if (!bp->cnic_eth_dev.max_fcoe_conn)
11052                 bp->flags |= NO_FCOE_FLAG;
11053 }
11054
11055 static void bnx2x_get_cnic_info(struct bnx2x *bp)
11056 {
11057         /*
11058          * iSCSI may be dynamically disabled but reading
11059          * info here we will decrease memory usage by driver
11060          * if the feature is disabled for good
11061          */
11062         bnx2x_get_iscsi_info(bp);
11063         bnx2x_get_fcoe_info(bp);
11064 }
11065
11066 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11067 {
11068         u32 val, val2;
11069         int func = BP_ABS_FUNC(bp);
11070         int port = BP_PORT(bp);
11071         u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11072         u8 *fip_mac = bp->fip_mac;
11073
11074         if (IS_MF(bp)) {
11075                 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11076                  * FCoE MAC then the appropriate feature should be disabled.
11077                  * In non SD mode features configuration comes from struct
11078                  * func_ext_config.
11079                  */
11080                 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
11081                         u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11082                         if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11083                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11084                                                  iscsi_mac_addr_upper);
11085                                 val = MF_CFG_RD(bp, func_ext_config[func].
11086                                                 iscsi_mac_addr_lower);
11087                                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11088                                 BNX2X_DEV_INFO
11089                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11090                         } else {
11091                                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11092                         }
11093
11094                         if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11095                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11096                                                  fcoe_mac_addr_upper);
11097                                 val = MF_CFG_RD(bp, func_ext_config[func].
11098                                                 fcoe_mac_addr_lower);
11099                                 bnx2x_set_mac_buf(fip_mac, val, val2);
11100                                 BNX2X_DEV_INFO
11101                                         ("Read FCoE L2 MAC: %pM\n", fip_mac);
11102                         } else {
11103                                 bp->flags |= NO_FCOE_FLAG;
11104                         }
11105
11106                         bp->mf_ext_config = cfg;
11107
11108                 } else { /* SD MODE */
11109                         if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11110                                 /* use primary mac as iscsi mac */
11111                                 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11112
11113                                 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11114                                 BNX2X_DEV_INFO
11115                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11116                         } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11117                                 /* use primary mac as fip mac */
11118                                 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11119                                 BNX2X_DEV_INFO("SD FCoE MODE\n");
11120                                 BNX2X_DEV_INFO
11121                                         ("Read FIP MAC: %pM\n", fip_mac);
11122                         }
11123                 }
11124
11125                 /* If this is a storage-only interface, use SAN mac as
11126                  * primary MAC. Notice that for SD this is already the case,
11127                  * as the SAN mac was copied from the primary MAC.
11128                  */
11129                 if (IS_MF_FCOE_AFEX(bp))
11130                         memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11131         } else {
11132                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11133                                 iscsi_mac_upper);
11134                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11135                                iscsi_mac_lower);
11136                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11137
11138                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11139                                 fcoe_fip_mac_upper);
11140                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11141                                fcoe_fip_mac_lower);
11142                 bnx2x_set_mac_buf(fip_mac, val, val2);
11143         }
11144
11145         /* Disable iSCSI OOO if MAC configuration is invalid. */
11146         if (!is_valid_ether_addr(iscsi_mac)) {
11147                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11148                 memset(iscsi_mac, 0, ETH_ALEN);
11149         }
11150
11151         /* Disable FCoE if MAC configuration is invalid. */
11152         if (!is_valid_ether_addr(fip_mac)) {
11153                 bp->flags |= NO_FCOE_FLAG;
11154                 memset(bp->fip_mac, 0, ETH_ALEN);
11155         }
11156 }
11157
11158 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11159 {
11160         u32 val, val2;
11161         int func = BP_ABS_FUNC(bp);
11162         int port = BP_PORT(bp);
11163
11164         /* Zero primary MAC configuration */
11165         memset(bp->dev->dev_addr, 0, ETH_ALEN);
11166
11167         if (BP_NOMCP(bp)) {
11168                 BNX2X_ERROR("warning: random MAC workaround active\n");
11169                 eth_hw_addr_random(bp->dev);
11170         } else if (IS_MF(bp)) {
11171                 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11172                 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11173                 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11174                     (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11175                         bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11176
11177                 if (CNIC_SUPPORT(bp))
11178                         bnx2x_get_cnic_mac_hwinfo(bp);
11179         } else {
11180                 /* in SF read MACs from port configuration */
11181                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11182                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11183                 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11184
11185                 if (CNIC_SUPPORT(bp))
11186                         bnx2x_get_cnic_mac_hwinfo(bp);
11187         }
11188
11189         if (!BP_NOMCP(bp)) {
11190                 /* Read physical port identifier from shmem */
11191                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11192                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11193                 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11194                 bp->flags |= HAS_PHYS_PORT_ID;
11195         }
11196
11197         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11198
11199         if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
11200                 dev_err(&bp->pdev->dev,
11201                         "bad Ethernet MAC address configuration: %pM\n"
11202                         "change it manually before bringing up the appropriate network interface\n",
11203                         bp->dev->dev_addr);
11204 }
11205
11206 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11207 {
11208         int tmp;
11209         u32 cfg;
11210
11211         if (IS_VF(bp))
11212                 return 0;
11213
11214         if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11215                 /* Take function: tmp = func */
11216                 tmp = BP_ABS_FUNC(bp);
11217                 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11218                 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11219         } else {
11220                 /* Take port: tmp = port */
11221                 tmp = BP_PORT(bp);
11222                 cfg = SHMEM_RD(bp,
11223                                dev_info.port_hw_config[tmp].generic_features);
11224                 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11225         }
11226         return cfg;
11227 }
11228
11229 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11230 {
11231         int /*abs*/func = BP_ABS_FUNC(bp);
11232         int vn;
11233         u32 val = 0;
11234         int rc = 0;
11235
11236         bnx2x_get_common_hwinfo(bp);
11237
11238         /*
11239          * initialize IGU parameters
11240          */
11241         if (CHIP_IS_E1x(bp)) {
11242                 bp->common.int_block = INT_BLOCK_HC;
11243
11244                 bp->igu_dsb_id = DEF_SB_IGU_ID;
11245                 bp->igu_base_sb = 0;
11246         } else {
11247                 bp->common.int_block = INT_BLOCK_IGU;
11248
11249                 /* do not allow device reset during IGU info processing */
11250                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11251
11252                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11253
11254                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11255                         int tout = 5000;
11256
11257                         BNX2X_DEV_INFO("FORCING Normal Mode\n");
11258
11259                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11260                         REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11261                         REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11262
11263                         while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11264                                 tout--;
11265                                 usleep_range(1000, 2000);
11266                         }
11267
11268                         if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11269                                 dev_err(&bp->pdev->dev,
11270                                         "FORCING Normal Mode failed!!!\n");
11271                                 bnx2x_release_hw_lock(bp,
11272                                                       HW_LOCK_RESOURCE_RESET);
11273                                 return -EPERM;
11274                         }
11275                 }
11276
11277                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11278                         BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11279                         bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11280                 } else
11281                         BNX2X_DEV_INFO("IGU Normal Mode\n");
11282
11283                 rc = bnx2x_get_igu_cam_info(bp);
11284                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11285                 if (rc)
11286                         return rc;
11287         }
11288
11289         /*
11290          * set base FW non-default (fast path) status block id, this value is
11291          * used to initialize the fw_sb_id saved on the fp/queue structure to
11292          * determine the id used by the FW.
11293          */
11294         if (CHIP_IS_E1x(bp))
11295                 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11296         else /*
11297               * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11298               * the same queue are indicated on the same IGU SB). So we prefer
11299               * FW and IGU SBs to be the same value.
11300               */
11301                 bp->base_fw_ndsb = bp->igu_base_sb;
11302
11303         BNX2X_DEV_INFO("igu_dsb_id %d  igu_base_sb %d  igu_sb_cnt %d\n"
11304                        "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11305                        bp->igu_sb_cnt, bp->base_fw_ndsb);
11306
11307         /*
11308          * Initialize MF configuration
11309          */
11310
11311         bp->mf_ov = 0;
11312         bp->mf_mode = 0;
11313         vn = BP_VN(bp);
11314
11315         if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
11316                 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11317                                bp->common.shmem2_base, SHMEM2_RD(bp, size),
11318                               (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11319
11320                 if (SHMEM2_HAS(bp, mf_cfg_addr))
11321                         bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11322                 else
11323                         bp->common.mf_cfg_base = bp->common.shmem_base +
11324                                 offsetof(struct shmem_region, func_mb) +
11325                                 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11326                 /*
11327                  * get mf configuration:
11328                  * 1. Existence of MF configuration
11329                  * 2. MAC address must be legal (check only upper bytes)
11330                  *    for  Switch-Independent mode;
11331                  *    OVLAN must be legal for Switch-Dependent mode
11332                  * 3. SF_MODE configures specific MF mode
11333                  */
11334                 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11335                         /* get mf configuration */
11336                         val = SHMEM_RD(bp,
11337                                        dev_info.shared_feature_config.config);
11338                         val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11339
11340                         switch (val) {
11341                         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11342                                 val = MF_CFG_RD(bp, func_mf_config[func].
11343                                                 mac_upper);
11344                                 /* check for legal mac (upper bytes)*/
11345                                 if (val != 0xffff) {
11346                                         bp->mf_mode = MULTI_FUNCTION_SI;
11347                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11348                                                    func_mf_config[func].config);
11349                                 } else
11350                                         BNX2X_DEV_INFO("illegal MAC address for SI\n");
11351                                 break;
11352                         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11353                                 if ((!CHIP_IS_E1x(bp)) &&
11354                                     (MF_CFG_RD(bp, func_mf_config[func].
11355                                                mac_upper) != 0xffff) &&
11356                                     (SHMEM2_HAS(bp,
11357                                                 afex_driver_support))) {
11358                                         bp->mf_mode = MULTI_FUNCTION_AFEX;
11359                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11360                                                 func_mf_config[func].config);
11361                                 } else {
11362                                         BNX2X_DEV_INFO("can not configure afex mode\n");
11363                                 }
11364                                 break;
11365                         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11366                                 /* get OV configuration */
11367                                 val = MF_CFG_RD(bp,
11368                                         func_mf_config[FUNC_0].e1hov_tag);
11369                                 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11370
11371                                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11372                                         bp->mf_mode = MULTI_FUNCTION_SD;
11373                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11374                                                 func_mf_config[func].config);
11375                                 } else
11376                                         BNX2X_DEV_INFO("illegal OV for SD\n");
11377                                 break;
11378                         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11379                                 bp->mf_config[vn] = 0;
11380                                 break;
11381                         default:
11382                                 /* Unknown configuration: reset mf_config */
11383                                 bp->mf_config[vn] = 0;
11384                                 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
11385                         }
11386                 }
11387
11388                 BNX2X_DEV_INFO("%s function mode\n",
11389                                IS_MF(bp) ? "multi" : "single");
11390
11391                 switch (bp->mf_mode) {
11392                 case MULTI_FUNCTION_SD:
11393                         val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11394                               FUNC_MF_CFG_E1HOV_TAG_MASK;
11395                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11396                                 bp->mf_ov = val;
11397                                 bp->path_has_ovlan = true;
11398
11399                                 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11400                                                func, bp->mf_ov, bp->mf_ov);
11401                         } else {
11402                                 dev_err(&bp->pdev->dev,
11403                                         "No valid MF OV for func %d, aborting\n",
11404                                         func);
11405                                 return -EPERM;
11406                         }
11407                         break;
11408                 case MULTI_FUNCTION_AFEX:
11409                         BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11410                         break;
11411                 case MULTI_FUNCTION_SI:
11412                         BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11413                                        func);
11414                         break;
11415                 default:
11416                         if (vn) {
11417                                 dev_err(&bp->pdev->dev,
11418                                         "VN %d is in a single function mode, aborting\n",
11419                                         vn);
11420                                 return -EPERM;
11421                         }
11422                         break;
11423                 }
11424
11425                 /* check if other port on the path needs ovlan:
11426                  * Since MF configuration is shared between ports
11427                  * Possible mixed modes are only
11428                  * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11429                  */
11430                 if (CHIP_MODE_IS_4_PORT(bp) &&
11431                     !bp->path_has_ovlan &&
11432                     !IS_MF(bp) &&
11433                     bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11434                         u8 other_port = !BP_PORT(bp);
11435                         u8 other_func = BP_PATH(bp) + 2*other_port;
11436                         val = MF_CFG_RD(bp,
11437                                         func_mf_config[other_func].e1hov_tag);
11438                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11439                                 bp->path_has_ovlan = true;
11440                 }
11441         }
11442
11443         /* adjust igu_sb_cnt to MF for E1x */
11444         if (CHIP_IS_E1x(bp) && IS_MF(bp))
11445                 bp->igu_sb_cnt /= E1HVN_MAX;
11446
11447         /* port info */
11448         bnx2x_get_port_hwinfo(bp);
11449
11450         /* Get MAC addresses */
11451         bnx2x_get_mac_hwinfo(bp);
11452
11453         bnx2x_get_cnic_info(bp);
11454
11455         return rc;
11456 }
11457
11458 static void bnx2x_read_fwinfo(struct bnx2x *bp)
11459 {
11460         int cnt, i, block_end, rodi;
11461         char vpd_start[BNX2X_VPD_LEN+1];
11462         char str_id_reg[VENDOR_ID_LEN+1];
11463         char str_id_cap[VENDOR_ID_LEN+1];
11464         char *vpd_data;
11465         char *vpd_extended_data = NULL;
11466         u8 len;
11467
11468         cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
11469         memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11470
11471         if (cnt < BNX2X_VPD_LEN)
11472                 goto out_not_found;
11473
11474         /* VPD RO tag should be first tag after identifier string, hence
11475          * we should be able to find it in first BNX2X_VPD_LEN chars
11476          */
11477         i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
11478                              PCI_VPD_LRDT_RO_DATA);
11479         if (i < 0)
11480                 goto out_not_found;
11481
11482         block_end = i + PCI_VPD_LRDT_TAG_SIZE +
11483                     pci_vpd_lrdt_size(&vpd_start[i]);
11484
11485         i += PCI_VPD_LRDT_TAG_SIZE;
11486
11487         if (block_end > BNX2X_VPD_LEN) {
11488                 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11489                 if (vpd_extended_data  == NULL)
11490                         goto out_not_found;
11491
11492                 /* read rest of vpd image into vpd_extended_data */
11493                 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11494                 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11495                                    block_end - BNX2X_VPD_LEN,
11496                                    vpd_extended_data + BNX2X_VPD_LEN);
11497                 if (cnt < (block_end - BNX2X_VPD_LEN))
11498                         goto out_not_found;
11499                 vpd_data = vpd_extended_data;
11500         } else
11501                 vpd_data = vpd_start;
11502
11503         /* now vpd_data holds full vpd content in both cases */
11504
11505         rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11506                                    PCI_VPD_RO_KEYWORD_MFR_ID);
11507         if (rodi < 0)
11508                 goto out_not_found;
11509
11510         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11511
11512         if (len != VENDOR_ID_LEN)
11513                 goto out_not_found;
11514
11515         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11516
11517         /* vendor specific info */
11518         snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11519         snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11520         if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11521             !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11522
11523                 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11524                                                 PCI_VPD_RO_KEYWORD_VENDOR0);
11525                 if (rodi >= 0) {
11526                         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11527
11528                         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11529
11530                         if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11531                                 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11532                                 bp->fw_ver[len] = ' ';
11533                         }
11534                 }
11535                 kfree(vpd_extended_data);
11536                 return;
11537         }
11538 out_not_found:
11539         kfree(vpd_extended_data);
11540         return;
11541 }
11542
11543 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
11544 {
11545         u32 flags = 0;
11546
11547         if (CHIP_REV_IS_FPGA(bp))
11548                 SET_FLAGS(flags, MODE_FPGA);
11549         else if (CHIP_REV_IS_EMUL(bp))
11550                 SET_FLAGS(flags, MODE_EMUL);
11551         else
11552                 SET_FLAGS(flags, MODE_ASIC);
11553
11554         if (CHIP_MODE_IS_4_PORT(bp))
11555                 SET_FLAGS(flags, MODE_PORT4);
11556         else
11557                 SET_FLAGS(flags, MODE_PORT2);
11558
11559         if (CHIP_IS_E2(bp))
11560                 SET_FLAGS(flags, MODE_E2);
11561         else if (CHIP_IS_E3(bp)) {
11562                 SET_FLAGS(flags, MODE_E3);
11563                 if (CHIP_REV(bp) == CHIP_REV_Ax)
11564                         SET_FLAGS(flags, MODE_E3_A0);
11565                 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11566                         SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
11567         }
11568
11569         if (IS_MF(bp)) {
11570                 SET_FLAGS(flags, MODE_MF);
11571                 switch (bp->mf_mode) {
11572                 case MULTI_FUNCTION_SD:
11573                         SET_FLAGS(flags, MODE_MF_SD);
11574                         break;
11575                 case MULTI_FUNCTION_SI:
11576                         SET_FLAGS(flags, MODE_MF_SI);
11577                         break;
11578                 case MULTI_FUNCTION_AFEX:
11579                         SET_FLAGS(flags, MODE_MF_AFEX);
11580                         break;
11581                 }
11582         } else
11583                 SET_FLAGS(flags, MODE_SF);
11584
11585 #if defined(__LITTLE_ENDIAN)
11586         SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11587 #else /*(__BIG_ENDIAN)*/
11588         SET_FLAGS(flags, MODE_BIG_ENDIAN);
11589 #endif
11590         INIT_MODE_FLAGS(bp) = flags;
11591 }
11592
11593 static int bnx2x_init_bp(struct bnx2x *bp)
11594 {
11595         int func;
11596         int rc;
11597
11598         mutex_init(&bp->port.phy_mutex);
11599         mutex_init(&bp->fw_mb_mutex);
11600         spin_lock_init(&bp->stats_lock);
11601         sema_init(&bp->stats_sema, 1);
11602
11603         INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
11604         INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
11605         INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
11606         if (IS_PF(bp)) {
11607                 rc = bnx2x_get_hwinfo(bp);
11608                 if (rc)
11609                         return rc;
11610         } else {
11611                 eth_zero_addr(bp->dev->dev_addr);
11612         }
11613
11614         bnx2x_set_modes_bitmap(bp);
11615
11616         rc = bnx2x_alloc_mem_bp(bp);
11617         if (rc)
11618                 return rc;
11619
11620         bnx2x_read_fwinfo(bp);
11621
11622         func = BP_FUNC(bp);
11623
11624         /* need to reset chip if undi was active */
11625         if (IS_PF(bp) && !BP_NOMCP(bp)) {
11626                 /* init fw_seq */
11627                 bp->fw_seq =
11628                         SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11629                                                         DRV_MSG_SEQ_NUMBER_MASK;
11630                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11631
11632                 bnx2x_prev_unload(bp);
11633         }
11634
11635         if (CHIP_REV_IS_FPGA(bp))
11636                 dev_err(&bp->pdev->dev, "FPGA detected\n");
11637
11638         if (BP_NOMCP(bp) && (func == 0))
11639                 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
11640
11641         bp->disable_tpa = disable_tpa;
11642         bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
11643
11644         /* Set TPA flags */
11645         if (bp->disable_tpa) {
11646                 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11647                 bp->dev->features &= ~NETIF_F_LRO;
11648         } else {
11649                 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11650                 bp->dev->features |= NETIF_F_LRO;
11651         }
11652
11653         if (CHIP_IS_E1(bp))
11654                 bp->dropless_fc = 0;
11655         else
11656                 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
11657
11658         bp->mrrs = mrrs;
11659
11660         bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
11661         if (IS_VF(bp))
11662                 bp->rx_ring_size = MAX_RX_AVAIL;
11663
11664         /* make sure that the numbers are in the right granularity */
11665         bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
11666         bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
11667
11668         bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
11669
11670         init_timer(&bp->timer);
11671         bp->timer.expires = jiffies + bp->current_interval;
11672         bp->timer.data = (unsigned long) bp;
11673         bp->timer.function = bnx2x_timer;
11674
11675         if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
11676             SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
11677             SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
11678             SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
11679                 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
11680                 bnx2x_dcbx_init_params(bp);
11681         } else {
11682                 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
11683         }
11684
11685         if (CHIP_IS_E1x(bp))
11686                 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
11687         else
11688                 bp->cnic_base_cl_id = FP_SB_MAX_E2;
11689
11690         /* multiple tx priority */
11691         if (IS_VF(bp))
11692                 bp->max_cos = 1;
11693         else if (CHIP_IS_E1x(bp))
11694                 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
11695         else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
11696                 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
11697         else if (CHIP_IS_E3B0(bp))
11698                 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
11699         else
11700                 BNX2X_ERR("unknown chip %x revision %x\n",
11701                           CHIP_NUM(bp), CHIP_REV(bp));
11702         BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
11703
11704         /* We need at least one default status block for slow-path events,
11705          * second status block for the L2 queue, and a third status block for
11706          * CNIC if supported.
11707          */
11708         if (IS_VF(bp))
11709                 bp->min_msix_vec_cnt = 1;
11710         else if (CNIC_SUPPORT(bp))
11711                 bp->min_msix_vec_cnt = 3;
11712         else /* PF w/o cnic */
11713                 bp->min_msix_vec_cnt = 2;
11714         BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
11715
11716         bp->dump_preset_idx = 1;
11717
11718         return rc;
11719 }
11720
11721 /****************************************************************************
11722 * General service functions
11723 ****************************************************************************/
11724
11725 /*
11726  * net_device service functions
11727  */
11728
11729 /* called with rtnl_lock */
11730 static int bnx2x_open(struct net_device *dev)
11731 {
11732         struct bnx2x *bp = netdev_priv(dev);
11733         int rc;
11734
11735         bp->stats_init = true;
11736
11737         netif_carrier_off(dev);
11738
11739         bnx2x_set_power_state(bp, PCI_D0);
11740
11741         /* If parity had happen during the unload, then attentions
11742          * and/or RECOVERY_IN_PROGRES may still be set. In this case we
11743          * want the first function loaded on the current engine to
11744          * complete the recovery.
11745          * Parity recovery is only relevant for PF driver.
11746          */
11747         if (IS_PF(bp)) {
11748                 int other_engine = BP_PATH(bp) ? 0 : 1;
11749                 bool other_load_status, load_status;
11750                 bool global = false;
11751
11752                 other_load_status = bnx2x_get_load_status(bp, other_engine);
11753                 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
11754                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
11755                     bnx2x_chk_parity_attn(bp, &global, true)) {
11756                         do {
11757                                 /* If there are attentions and they are in a
11758                                  * global blocks, set the GLOBAL_RESET bit
11759                                  * regardless whether it will be this function
11760                                  * that will complete the recovery or not.
11761                                  */
11762                                 if (global)
11763                                         bnx2x_set_reset_global(bp);
11764
11765                                 /* Only the first function on the current
11766                                  * engine should try to recover in open. In case
11767                                  * of attentions in global blocks only the first
11768                                  * in the chip should try to recover.
11769                                  */
11770                                 if ((!load_status &&
11771                                      (!global || !other_load_status)) &&
11772                                       bnx2x_trylock_leader_lock(bp) &&
11773                                       !bnx2x_leader_reset(bp)) {
11774                                         netdev_info(bp->dev,
11775                                                     "Recovered in open\n");
11776                                         break;
11777                                 }
11778
11779                                 /* recovery has failed... */
11780                                 bnx2x_set_power_state(bp, PCI_D3hot);
11781                                 bp->recovery_state = BNX2X_RECOVERY_FAILED;
11782
11783                                 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
11784                                           "If you still see this message after a few retries then power cycle is required.\n");
11785
11786                                 return -EAGAIN;
11787                         } while (0);
11788                 }
11789         }
11790
11791         bp->recovery_state = BNX2X_RECOVERY_DONE;
11792         rc = bnx2x_nic_load(bp, LOAD_OPEN);
11793         if (rc)
11794                 return rc;
11795         return 0;
11796 }
11797
11798 /* called with rtnl_lock */
11799 static int bnx2x_close(struct net_device *dev)
11800 {
11801         struct bnx2x *bp = netdev_priv(dev);
11802
11803         /* Unload the driver, release IRQs */
11804         bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
11805
11806         return 0;
11807 }
11808
11809 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11810                                       struct bnx2x_mcast_ramrod_params *p)
11811 {
11812         int mc_count = netdev_mc_count(bp->dev);
11813         struct bnx2x_mcast_list_elem *mc_mac =
11814                 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
11815         struct netdev_hw_addr *ha;
11816
11817         if (!mc_mac)
11818                 return -ENOMEM;
11819
11820         INIT_LIST_HEAD(&p->mcast_list);
11821
11822         netdev_for_each_mc_addr(ha, bp->dev) {
11823                 mc_mac->mac = bnx2x_mc_addr(ha);
11824                 list_add_tail(&mc_mac->link, &p->mcast_list);
11825                 mc_mac++;
11826         }
11827
11828         p->mcast_list_len = mc_count;
11829
11830         return 0;
11831 }
11832
11833 static void bnx2x_free_mcast_macs_list(
11834         struct bnx2x_mcast_ramrod_params *p)
11835 {
11836         struct bnx2x_mcast_list_elem *mc_mac =
11837                 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
11838                                  link);
11839
11840         WARN_ON(!mc_mac);
11841         kfree(mc_mac);
11842 }
11843
11844 /**
11845  * bnx2x_set_uc_list - configure a new unicast MACs list.
11846  *
11847  * @bp: driver handle
11848  *
11849  * We will use zero (0) as a MAC type for these MACs.
11850  */
11851 static int bnx2x_set_uc_list(struct bnx2x *bp)
11852 {
11853         int rc;
11854         struct net_device *dev = bp->dev;
11855         struct netdev_hw_addr *ha;
11856         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
11857         unsigned long ramrod_flags = 0;
11858
11859         /* First schedule a cleanup up of old configuration */
11860         rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
11861         if (rc < 0) {
11862                 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
11863                 return rc;
11864         }
11865
11866         netdev_for_each_uc_addr(ha, dev) {
11867                 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
11868                                        BNX2X_UC_LIST_MAC, &ramrod_flags);
11869                 if (rc == -EEXIST) {
11870                         DP(BNX2X_MSG_SP,
11871                            "Failed to schedule ADD operations: %d\n", rc);
11872                         /* do not treat adding same MAC as error */
11873                         rc = 0;
11874
11875                 } else if (rc < 0) {
11876
11877                         BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11878                                   rc);
11879                         return rc;
11880                 }
11881         }
11882
11883         /* Execute the pending commands */
11884         __set_bit(RAMROD_CONT, &ramrod_flags);
11885         return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
11886                                  BNX2X_UC_LIST_MAC, &ramrod_flags);
11887 }
11888
11889 static int bnx2x_set_mc_list(struct bnx2x *bp)
11890 {
11891         struct net_device *dev = bp->dev;
11892         struct bnx2x_mcast_ramrod_params rparam = {NULL};
11893         int rc = 0;
11894
11895         rparam.mcast_obj = &bp->mcast_obj;
11896
11897         /* first, clear all configured multicast MACs */
11898         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
11899         if (rc < 0) {
11900                 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
11901                 return rc;
11902         }
11903
11904         /* then, configure a new MACs list */
11905         if (netdev_mc_count(dev)) {
11906                 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
11907                 if (rc) {
11908                         BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11909                                   rc);
11910                         return rc;
11911                 }
11912
11913                 /* Now add the new MACs */
11914                 rc = bnx2x_config_mcast(bp, &rparam,
11915                                         BNX2X_MCAST_CMD_ADD);
11916                 if (rc < 0)
11917                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11918                                   rc);
11919
11920                 bnx2x_free_mcast_macs_list(&rparam);
11921         }
11922
11923         return rc;
11924 }
11925
11926 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
11927 void bnx2x_set_rx_mode(struct net_device *dev)
11928 {
11929         struct bnx2x *bp = netdev_priv(dev);
11930
11931         if (bp->state != BNX2X_STATE_OPEN) {
11932                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
11933                 return;
11934         } else {
11935                 /* Schedule an SP task to handle rest of change */
11936                 DP(NETIF_MSG_IFUP, "Scheduling an Rx mode change\n");
11937                 smp_mb__before_clear_bit();
11938                 set_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state);
11939                 smp_mb__after_clear_bit();
11940                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
11941         }
11942 }
11943
11944 void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
11945 {
11946         u32 rx_mode = BNX2X_RX_MODE_NORMAL;
11947
11948         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
11949
11950         netif_addr_lock_bh(bp->dev);
11951
11952         if (bp->dev->flags & IFF_PROMISC) {
11953                 rx_mode = BNX2X_RX_MODE_PROMISC;
11954         } else if ((bp->dev->flags & IFF_ALLMULTI) ||
11955                    ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
11956                     CHIP_IS_E1(bp))) {
11957                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11958         } else {
11959                 if (IS_PF(bp)) {
11960                         /* some multicasts */
11961                         if (bnx2x_set_mc_list(bp) < 0)
11962                                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11963
11964                         /* release bh lock, as bnx2x_set_uc_list might sleep */
11965                         netif_addr_unlock_bh(bp->dev);
11966                         if (bnx2x_set_uc_list(bp) < 0)
11967                                 rx_mode = BNX2X_RX_MODE_PROMISC;
11968                         netif_addr_lock_bh(bp->dev);
11969                 } else {
11970                         /* configuring mcast to a vf involves sleeping (when we
11971                          * wait for the pf's response).
11972                          */
11973                         smp_mb__before_clear_bit();
11974                         set_bit(BNX2X_SP_RTNL_VFPF_MCAST,
11975                                 &bp->sp_rtnl_state);
11976                         smp_mb__after_clear_bit();
11977                         schedule_delayed_work(&bp->sp_rtnl_task, 0);
11978                 }
11979         }
11980
11981         bp->rx_mode = rx_mode;
11982         /* handle ISCSI SD mode */
11983         if (IS_MF_ISCSI_SD(bp))
11984                 bp->rx_mode = BNX2X_RX_MODE_NONE;
11985
11986         /* Schedule the rx_mode command */
11987         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
11988                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
11989                 netif_addr_unlock_bh(bp->dev);
11990                 return;
11991         }
11992
11993         if (IS_PF(bp)) {
11994                 bnx2x_set_storm_rx_mode(bp);
11995                 netif_addr_unlock_bh(bp->dev);
11996         } else {
11997                 /* VF will need to request the PF to make this change, and so
11998                  * the VF needs to release the bottom-half lock prior to the
11999                  * request (as it will likely require sleep on the VF side)
12000                  */
12001                 netif_addr_unlock_bh(bp->dev);
12002                 bnx2x_vfpf_storm_rx_mode(bp);
12003         }
12004 }
12005
12006 /* called with rtnl_lock */
12007 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12008                            int devad, u16 addr)
12009 {
12010         struct bnx2x *bp = netdev_priv(netdev);
12011         u16 value;
12012         int rc;
12013
12014         DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12015            prtad, devad, addr);
12016
12017         /* The HW expects different devad if CL22 is used */
12018         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12019
12020         bnx2x_acquire_phy_lock(bp);
12021         rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
12022         bnx2x_release_phy_lock(bp);
12023         DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
12024
12025         if (!rc)
12026                 rc = value;
12027         return rc;
12028 }
12029
12030 /* called with rtnl_lock */
12031 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12032                             u16 addr, u16 value)
12033 {
12034         struct bnx2x *bp = netdev_priv(netdev);
12035         int rc;
12036
12037         DP(NETIF_MSG_LINK,
12038            "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12039            prtad, devad, addr, value);
12040
12041         /* The HW expects different devad if CL22 is used */
12042         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12043
12044         bnx2x_acquire_phy_lock(bp);
12045         rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
12046         bnx2x_release_phy_lock(bp);
12047         return rc;
12048 }
12049
12050 /* called with rtnl_lock */
12051 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12052 {
12053         struct bnx2x *bp = netdev_priv(dev);
12054         struct mii_ioctl_data *mdio = if_mii(ifr);
12055
12056         DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12057            mdio->phy_id, mdio->reg_num, mdio->val_in);
12058
12059         if (!netif_running(dev))
12060                 return -EAGAIN;
12061
12062         return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12063 }
12064
12065 #ifdef CONFIG_NET_POLL_CONTROLLER
12066 static void poll_bnx2x(struct net_device *dev)
12067 {
12068         struct bnx2x *bp = netdev_priv(dev);
12069         int i;
12070
12071         for_each_eth_queue(bp, i) {
12072                 struct bnx2x_fastpath *fp = &bp->fp[i];
12073                 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12074         }
12075 }
12076 #endif
12077
12078 static int bnx2x_validate_addr(struct net_device *dev)
12079 {
12080         struct bnx2x *bp = netdev_priv(dev);
12081
12082         /* query the bulletin board for mac address configured by the PF */
12083         if (IS_VF(bp))
12084                 bnx2x_sample_bulletin(bp);
12085
12086         if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
12087                 BNX2X_ERR("Non-valid Ethernet address\n");
12088                 return -EADDRNOTAVAIL;
12089         }
12090         return 0;
12091 }
12092
12093 static int bnx2x_get_phys_port_id(struct net_device *netdev,
12094                                   struct netdev_phys_port_id *ppid)
12095 {
12096         struct bnx2x *bp = netdev_priv(netdev);
12097
12098         if (!(bp->flags & HAS_PHYS_PORT_ID))
12099                 return -EOPNOTSUPP;
12100
12101         ppid->id_len = sizeof(bp->phys_port_id);
12102         memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12103
12104         return 0;
12105 }
12106
12107 static const struct net_device_ops bnx2x_netdev_ops = {
12108         .ndo_open               = bnx2x_open,
12109         .ndo_stop               = bnx2x_close,
12110         .ndo_start_xmit         = bnx2x_start_xmit,
12111         .ndo_select_queue       = bnx2x_select_queue,
12112         .ndo_set_rx_mode        = bnx2x_set_rx_mode,
12113         .ndo_set_mac_address    = bnx2x_change_mac_addr,
12114         .ndo_validate_addr      = bnx2x_validate_addr,
12115         .ndo_do_ioctl           = bnx2x_ioctl,
12116         .ndo_change_mtu         = bnx2x_change_mtu,
12117         .ndo_fix_features       = bnx2x_fix_features,
12118         .ndo_set_features       = bnx2x_set_features,
12119         .ndo_tx_timeout         = bnx2x_tx_timeout,
12120 #ifdef CONFIG_NET_POLL_CONTROLLER
12121         .ndo_poll_controller    = poll_bnx2x,
12122 #endif
12123         .ndo_setup_tc           = bnx2x_setup_tc,
12124 #ifdef CONFIG_BNX2X_SRIOV
12125         .ndo_set_vf_mac         = bnx2x_set_vf_mac,
12126         .ndo_set_vf_vlan        = bnx2x_set_vf_vlan,
12127         .ndo_get_vf_config      = bnx2x_get_vf_config,
12128 #endif
12129 #ifdef NETDEV_FCOE_WWNN
12130         .ndo_fcoe_get_wwn       = bnx2x_fcoe_get_wwn,
12131 #endif
12132
12133 #ifdef CONFIG_NET_RX_BUSY_POLL
12134         .ndo_busy_poll          = bnx2x_low_latency_recv,
12135 #endif
12136         .ndo_get_phys_port_id   = bnx2x_get_phys_port_id,
12137 };
12138
12139 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
12140 {
12141         struct device *dev = &bp->pdev->dev;
12142
12143         if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
12144             dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
12145                 dev_err(dev, "System does not support DMA, aborting\n");
12146                 return -EIO;
12147         }
12148
12149         return 0;
12150 }
12151
12152 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
12153                           struct net_device *dev, unsigned long board_type)
12154 {
12155         int rc;
12156         u32 pci_cfg_dword;
12157         bool chip_is_e1x = (board_type == BCM57710 ||
12158                             board_type == BCM57711 ||
12159                             board_type == BCM57711E);
12160
12161         SET_NETDEV_DEV(dev, &pdev->dev);
12162
12163         bp->dev = dev;
12164         bp->pdev = pdev;
12165
12166         rc = pci_enable_device(pdev);
12167         if (rc) {
12168                 dev_err(&bp->pdev->dev,
12169                         "Cannot enable PCI device, aborting\n");
12170                 goto err_out;
12171         }
12172
12173         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12174                 dev_err(&bp->pdev->dev,
12175                         "Cannot find PCI device base address, aborting\n");
12176                 rc = -ENODEV;
12177                 goto err_out_disable;
12178         }
12179
12180         if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12181                 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
12182                 rc = -ENODEV;
12183                 goto err_out_disable;
12184         }
12185
12186         pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
12187         if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
12188             PCICFG_REVESION_ID_ERROR_VAL) {
12189                 pr_err("PCI device error, probably due to fan failure, aborting\n");
12190                 rc = -ENODEV;
12191                 goto err_out_disable;
12192         }
12193
12194         if (atomic_read(&pdev->enable_cnt) == 1) {
12195                 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12196                 if (rc) {
12197                         dev_err(&bp->pdev->dev,
12198                                 "Cannot obtain PCI resources, aborting\n");
12199                         goto err_out_disable;
12200                 }
12201
12202                 pci_set_master(pdev);
12203                 pci_save_state(pdev);
12204         }
12205
12206         if (IS_PF(bp)) {
12207                 if (!pdev->pm_cap) {
12208                         dev_err(&bp->pdev->dev,
12209                                 "Cannot find power management capability, aborting\n");
12210                         rc = -EIO;
12211                         goto err_out_release;
12212                 }
12213         }
12214
12215         if (!pci_is_pcie(pdev)) {
12216                 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
12217                 rc = -EIO;
12218                 goto err_out_release;
12219         }
12220
12221         rc = bnx2x_set_coherency_mask(bp);
12222         if (rc)
12223                 goto err_out_release;
12224
12225         dev->mem_start = pci_resource_start(pdev, 0);
12226         dev->base_addr = dev->mem_start;
12227         dev->mem_end = pci_resource_end(pdev, 0);
12228
12229         dev->irq = pdev->irq;
12230
12231         bp->regview = pci_ioremap_bar(pdev, 0);
12232         if (!bp->regview) {
12233                 dev_err(&bp->pdev->dev,
12234                         "Cannot map register space, aborting\n");
12235                 rc = -ENOMEM;
12236                 goto err_out_release;
12237         }
12238
12239         /* In E1/E1H use pci device function given by kernel.
12240          * In E2/E3 read physical function from ME register since these chips
12241          * support Physical Device Assignment where kernel BDF maybe arbitrary
12242          * (depending on hypervisor).
12243          */
12244         if (chip_is_e1x) {
12245                 bp->pf_num = PCI_FUNC(pdev->devfn);
12246         } else {
12247                 /* chip is E2/3*/
12248                 pci_read_config_dword(bp->pdev,
12249                                       PCICFG_ME_REGISTER, &pci_cfg_dword);
12250                 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
12251                                   ME_REG_ABS_PF_NUM_SHIFT);
12252         }
12253         BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
12254
12255         /* clean indirect addresses */
12256         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
12257                                PCICFG_VENDOR_ID_OFFSET);
12258         /*
12259          * Clean the following indirect addresses for all functions since it
12260          * is not used by the driver.
12261          */
12262         if (IS_PF(bp)) {
12263                 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
12264                 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
12265                 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12266                 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12267
12268                 if (chip_is_e1x) {
12269                         REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12270                         REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12271                         REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12272                         REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12273                 }
12274
12275                 /* Enable internal target-read (in case we are probed after PF
12276                  * FLR). Must be done prior to any BAR read access. Only for
12277                  * 57712 and up
12278                  */
12279                 if (!chip_is_e1x)
12280                         REG_WR(bp,
12281                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
12282         }
12283
12284         dev->watchdog_timeo = TX_TIMEOUT;
12285
12286         dev->netdev_ops = &bnx2x_netdev_ops;
12287         bnx2x_set_ethtool_ops(bp, dev);
12288
12289         dev->priv_flags |= IFF_UNICAST_FLT;
12290
12291         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12292                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12293                 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
12294                 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
12295         if (!CHIP_IS_E1x(bp)) {
12296                 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
12297                                     NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
12298                 dev->hw_enc_features =
12299                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12300                         NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12301                         NETIF_F_GSO_IPIP |
12302                         NETIF_F_GSO_SIT |
12303                         NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
12304         }
12305
12306         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12307                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12308
12309         dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
12310         dev->features |= NETIF_F_HIGHDMA;
12311
12312         /* Add Loopback capability to the device */
12313         dev->hw_features |= NETIF_F_LOOPBACK;
12314
12315 #ifdef BCM_DCBNL
12316         dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12317 #endif
12318
12319         /* get_port_hwinfo() will set prtad and mmds properly */
12320         bp->mdio.prtad = MDIO_PRTAD_NONE;
12321         bp->mdio.mmds = 0;
12322         bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12323         bp->mdio.dev = dev;
12324         bp->mdio.mdio_read = bnx2x_mdio_read;
12325         bp->mdio.mdio_write = bnx2x_mdio_write;
12326
12327         return 0;
12328
12329 err_out_release:
12330         if (atomic_read(&pdev->enable_cnt) == 1)
12331                 pci_release_regions(pdev);
12332
12333 err_out_disable:
12334         pci_disable_device(pdev);
12335
12336 err_out:
12337         return rc;
12338 }
12339
12340 static int bnx2x_check_firmware(struct bnx2x *bp)
12341 {
12342         const struct firmware *firmware = bp->firmware;
12343         struct bnx2x_fw_file_hdr *fw_hdr;
12344         struct bnx2x_fw_file_section *sections;
12345         u32 offset, len, num_ops;
12346         __be16 *ops_offsets;
12347         int i;
12348         const u8 *fw_ver;
12349
12350         if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12351                 BNX2X_ERR("Wrong FW size\n");
12352                 return -EINVAL;
12353         }
12354
12355         fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12356         sections = (struct bnx2x_fw_file_section *)fw_hdr;
12357
12358         /* Make sure none of the offsets and sizes make us read beyond
12359          * the end of the firmware data */
12360         for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12361                 offset = be32_to_cpu(sections[i].offset);
12362                 len = be32_to_cpu(sections[i].len);
12363                 if (offset + len > firmware->size) {
12364                         BNX2X_ERR("Section %d length is out of bounds\n", i);
12365                         return -EINVAL;
12366                 }
12367         }
12368
12369         /* Likewise for the init_ops offsets */
12370         offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
12371         ops_offsets = (__force __be16 *)(firmware->data + offset);
12372         num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12373
12374         for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12375                 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
12376                         BNX2X_ERR("Section offset %d is out of bounds\n", i);
12377                         return -EINVAL;
12378                 }
12379         }
12380
12381         /* Check FW version */
12382         offset = be32_to_cpu(fw_hdr->fw_version.offset);
12383         fw_ver = firmware->data + offset;
12384         if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12385             (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12386             (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12387             (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
12388                 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12389                        fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12390                        BCM_5710_FW_MAJOR_VERSION,
12391                        BCM_5710_FW_MINOR_VERSION,
12392                        BCM_5710_FW_REVISION_VERSION,
12393                        BCM_5710_FW_ENGINEERING_VERSION);
12394                 return -EINVAL;
12395         }
12396
12397         return 0;
12398 }
12399
12400 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12401 {
12402         const __be32 *source = (const __be32 *)_source;
12403         u32 *target = (u32 *)_target;
12404         u32 i;
12405
12406         for (i = 0; i < n/4; i++)
12407                 target[i] = be32_to_cpu(source[i]);
12408 }
12409
12410 /*
12411    Ops array is stored in the following format:
12412    {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12413  */
12414 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
12415 {
12416         const __be32 *source = (const __be32 *)_source;
12417         struct raw_op *target = (struct raw_op *)_target;
12418         u32 i, j, tmp;
12419
12420         for (i = 0, j = 0; i < n/8; i++, j += 2) {
12421                 tmp = be32_to_cpu(source[j]);
12422                 target[i].op = (tmp >> 24) & 0xff;
12423                 target[i].offset = tmp & 0xffffff;
12424                 target[i].raw_data = be32_to_cpu(source[j + 1]);
12425         }
12426 }
12427
12428 /* IRO array is stored in the following format:
12429  * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12430  */
12431 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
12432 {
12433         const __be32 *source = (const __be32 *)_source;
12434         struct iro *target = (struct iro *)_target;
12435         u32 i, j, tmp;
12436
12437         for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12438                 target[i].base = be32_to_cpu(source[j]);
12439                 j++;
12440                 tmp = be32_to_cpu(source[j]);
12441                 target[i].m1 = (tmp >> 16) & 0xffff;
12442                 target[i].m2 = tmp & 0xffff;
12443                 j++;
12444                 tmp = be32_to_cpu(source[j]);
12445                 target[i].m3 = (tmp >> 16) & 0xffff;
12446                 target[i].size = tmp & 0xffff;
12447                 j++;
12448         }
12449 }
12450
12451 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12452 {
12453         const __be16 *source = (const __be16 *)_source;
12454         u16 *target = (u16 *)_target;
12455         u32 i;
12456
12457         for (i = 0; i < n/2; i++)
12458                 target[i] = be16_to_cpu(source[i]);
12459 }
12460
12461 #define BNX2X_ALLOC_AND_SET(arr, lbl, func)                             \
12462 do {                                                                    \
12463         u32 len = be32_to_cpu(fw_hdr->arr.len);                         \
12464         bp->arr = kmalloc(len, GFP_KERNEL);                             \
12465         if (!bp->arr)                                                   \
12466                 goto lbl;                                               \
12467         func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset),      \
12468              (u8 *)bp->arr, len);                                       \
12469 } while (0)
12470
12471 static int bnx2x_init_firmware(struct bnx2x *bp)
12472 {
12473         const char *fw_file_name;
12474         struct bnx2x_fw_file_hdr *fw_hdr;
12475         int rc;
12476
12477         if (bp->firmware)
12478                 return 0;
12479
12480         if (CHIP_IS_E1(bp))
12481                 fw_file_name = FW_FILE_NAME_E1;
12482         else if (CHIP_IS_E1H(bp))
12483                 fw_file_name = FW_FILE_NAME_E1H;
12484         else if (!CHIP_IS_E1x(bp))
12485                 fw_file_name = FW_FILE_NAME_E2;
12486         else {
12487                 BNX2X_ERR("Unsupported chip revision\n");
12488                 return -EINVAL;
12489         }
12490         BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
12491
12492         rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12493         if (rc) {
12494                 BNX2X_ERR("Can't load firmware file %s\n",
12495                           fw_file_name);
12496                 goto request_firmware_exit;
12497         }
12498
12499         rc = bnx2x_check_firmware(bp);
12500         if (rc) {
12501                 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12502                 goto request_firmware_exit;
12503         }
12504
12505         fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12506
12507         /* Initialize the pointers to the init arrays */
12508         /* Blob */
12509         BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12510
12511         /* Opcodes */
12512         BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12513
12514         /* Offsets */
12515         BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12516                             be16_to_cpu_n);
12517
12518         /* STORMs firmware */
12519         INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12520                         be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12521         INIT_TSEM_PRAM_DATA(bp)      = bp->firmware->data +
12522                         be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12523         INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12524                         be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12525         INIT_USEM_PRAM_DATA(bp)      = bp->firmware->data +
12526                         be32_to_cpu(fw_hdr->usem_pram_data.offset);
12527         INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12528                         be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12529         INIT_XSEM_PRAM_DATA(bp)      = bp->firmware->data +
12530                         be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12531         INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12532                         be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12533         INIT_CSEM_PRAM_DATA(bp)      = bp->firmware->data +
12534                         be32_to_cpu(fw_hdr->csem_pram_data.offset);
12535         /* IRO */
12536         BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
12537
12538         return 0;
12539
12540 iro_alloc_err:
12541         kfree(bp->init_ops_offsets);
12542 init_offsets_alloc_err:
12543         kfree(bp->init_ops);
12544 init_ops_alloc_err:
12545         kfree(bp->init_data);
12546 request_firmware_exit:
12547         release_firmware(bp->firmware);
12548         bp->firmware = NULL;
12549
12550         return rc;
12551 }
12552
12553 static void bnx2x_release_firmware(struct bnx2x *bp)
12554 {
12555         kfree(bp->init_ops_offsets);
12556         kfree(bp->init_ops);
12557         kfree(bp->init_data);
12558         release_firmware(bp->firmware);
12559         bp->firmware = NULL;
12560 }
12561
12562 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12563         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12564         .init_hw_cmn      = bnx2x_init_hw_common,
12565         .init_hw_port     = bnx2x_init_hw_port,
12566         .init_hw_func     = bnx2x_init_hw_func,
12567
12568         .reset_hw_cmn     = bnx2x_reset_common,
12569         .reset_hw_port    = bnx2x_reset_port,
12570         .reset_hw_func    = bnx2x_reset_func,
12571
12572         .gunzip_init      = bnx2x_gunzip_init,
12573         .gunzip_end       = bnx2x_gunzip_end,
12574
12575         .init_fw          = bnx2x_init_firmware,
12576         .release_fw       = bnx2x_release_firmware,
12577 };
12578
12579 void bnx2x__init_func_obj(struct bnx2x *bp)
12580 {
12581         /* Prepare DMAE related driver resources */
12582         bnx2x_setup_dmae(bp);
12583
12584         bnx2x_init_func_obj(bp, &bp->func_obj,
12585                             bnx2x_sp(bp, func_rdata),
12586                             bnx2x_sp_mapping(bp, func_rdata),
12587                             bnx2x_sp(bp, func_afex_rdata),
12588                             bnx2x_sp_mapping(bp, func_afex_rdata),
12589                             &bnx2x_func_sp_drv);
12590 }
12591
12592 /* must be called after sriov-enable */
12593 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
12594 {
12595         int cid_count = BNX2X_L2_MAX_CID(bp);
12596
12597         if (IS_SRIOV(bp))
12598                 cid_count += BNX2X_VF_CIDS;
12599
12600         if (CNIC_SUPPORT(bp))
12601                 cid_count += CNIC_CID_MAX;
12602
12603         return roundup(cid_count, QM_CID_ROUND);
12604 }
12605
12606 /**
12607  * bnx2x_get_num_none_def_sbs - return the number of none default SBs
12608  *
12609  * @dev:        pci device
12610  *
12611  */
12612 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
12613 {
12614         int index;
12615         u16 control = 0;
12616
12617         /*
12618          * If MSI-X is not supported - return number of SBs needed to support
12619          * one fast path queue: one FP queue + SB for CNIC
12620          */
12621         if (!pdev->msix_cap) {
12622                 dev_info(&pdev->dev, "no msix capability found\n");
12623                 return 1 + cnic_cnt;
12624         }
12625         dev_info(&pdev->dev, "msix capability found\n");
12626
12627         /*
12628          * The value in the PCI configuration space is the index of the last
12629          * entry, namely one less than the actual size of the table, which is
12630          * exactly what we want to return from this function: number of all SBs
12631          * without the default SB.
12632          * For VFs there is no default SB, then we return (index+1).
12633          */
12634         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSI_FLAGS, &control);
12635
12636         index = control & PCI_MSIX_FLAGS_QSIZE;
12637
12638         return index;
12639 }
12640
12641 static int set_max_cos_est(int chip_id)
12642 {
12643         switch (chip_id) {
12644         case BCM57710:
12645         case BCM57711:
12646         case BCM57711E:
12647                 return BNX2X_MULTI_TX_COS_E1X;
12648         case BCM57712:
12649         case BCM57712_MF:
12650                 return BNX2X_MULTI_TX_COS_E2_E3A0;
12651         case BCM57800:
12652         case BCM57800_MF:
12653         case BCM57810:
12654         case BCM57810_MF:
12655         case BCM57840_4_10:
12656         case BCM57840_2_20:
12657         case BCM57840_O:
12658         case BCM57840_MFO:
12659         case BCM57840_MF:
12660         case BCM57811:
12661         case BCM57811_MF:
12662                 return BNX2X_MULTI_TX_COS_E3B0;
12663         case BCM57712_VF:
12664         case BCM57800_VF:
12665         case BCM57810_VF:
12666         case BCM57840_VF:
12667         case BCM57811_VF:
12668                 return 1;
12669         default:
12670                 pr_err("Unknown board_type (%d), aborting\n", chip_id);
12671                 return -ENODEV;
12672         }
12673 }
12674
12675 static int set_is_vf(int chip_id)
12676 {
12677         switch (chip_id) {
12678         case BCM57712_VF:
12679         case BCM57800_VF:
12680         case BCM57810_VF:
12681         case BCM57840_VF:
12682         case BCM57811_VF:
12683                 return true;
12684         default:
12685                 return false;
12686         }
12687 }
12688
12689 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
12690
12691 static int bnx2x_init_one(struct pci_dev *pdev,
12692                                     const struct pci_device_id *ent)
12693 {
12694         struct net_device *dev = NULL;
12695         struct bnx2x *bp;
12696         enum pcie_link_width pcie_width;
12697         enum pci_bus_speed pcie_speed;
12698         int rc, max_non_def_sbs;
12699         int rx_count, tx_count, rss_count, doorbell_size;
12700         int max_cos_est;
12701         bool is_vf;
12702         int cnic_cnt;
12703
12704         /* An estimated maximum supported CoS number according to the chip
12705          * version.
12706          * We will try to roughly estimate the maximum number of CoSes this chip
12707          * may support in order to minimize the memory allocated for Tx
12708          * netdev_queue's. This number will be accurately calculated during the
12709          * initialization of bp->max_cos based on the chip versions AND chip
12710          * revision in the bnx2x_init_bp().
12711          */
12712         max_cos_est = set_max_cos_est(ent->driver_data);
12713         if (max_cos_est < 0)
12714                 return max_cos_est;
12715         is_vf = set_is_vf(ent->driver_data);
12716         cnic_cnt = is_vf ? 0 : 1;
12717
12718         max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
12719
12720         /* add another SB for VF as it has no default SB */
12721         max_non_def_sbs += is_vf ? 1 : 0;
12722
12723         /* Maximum number of RSS queues: one IGU SB goes to CNIC */
12724         rss_count = max_non_def_sbs - cnic_cnt;
12725
12726         if (rss_count < 1)
12727                 return -EINVAL;
12728
12729         /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
12730         rx_count = rss_count + cnic_cnt;
12731
12732         /* Maximum number of netdev Tx queues:
12733          * Maximum TSS queues * Maximum supported number of CoS  + FCoE L2
12734          */
12735         tx_count = rss_count * max_cos_est + cnic_cnt;
12736
12737         /* dev zeroed in init_etherdev */
12738         dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
12739         if (!dev)
12740                 return -ENOMEM;
12741
12742         bp = netdev_priv(dev);
12743
12744         bp->flags = 0;
12745         if (is_vf)
12746                 bp->flags |= IS_VF_FLAG;
12747
12748         bp->igu_sb_cnt = max_non_def_sbs;
12749         bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
12750         bp->msg_enable = debug;
12751         bp->cnic_support = cnic_cnt;
12752         bp->cnic_probe = bnx2x_cnic_probe;
12753
12754         pci_set_drvdata(pdev, dev);
12755
12756         rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
12757         if (rc < 0) {
12758                 free_netdev(dev);
12759                 return rc;
12760         }
12761
12762         BNX2X_DEV_INFO("This is a %s function\n",
12763                        IS_PF(bp) ? "physical" : "virtual");
12764         BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
12765         BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
12766         BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
12767                        tx_count, rx_count);
12768
12769         rc = bnx2x_init_bp(bp);
12770         if (rc)
12771                 goto init_one_exit;
12772
12773         /* Map doorbells here as we need the real value of bp->max_cos which
12774          * is initialized in bnx2x_init_bp() to determine the number of
12775          * l2 connections.
12776          */
12777         if (IS_VF(bp)) {
12778                 bp->doorbells = bnx2x_vf_doorbells(bp);
12779                 rc = bnx2x_vf_pci_alloc(bp);
12780                 if (rc)
12781                         goto init_one_exit;
12782         } else {
12783                 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
12784                 if (doorbell_size > pci_resource_len(pdev, 2)) {
12785                         dev_err(&bp->pdev->dev,
12786                                 "Cannot map doorbells, bar size too small, aborting\n");
12787                         rc = -ENOMEM;
12788                         goto init_one_exit;
12789                 }
12790                 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
12791                                                 doorbell_size);
12792         }
12793         if (!bp->doorbells) {
12794                 dev_err(&bp->pdev->dev,
12795                         "Cannot map doorbell space, aborting\n");
12796                 rc = -ENOMEM;
12797                 goto init_one_exit;
12798         }
12799
12800         if (IS_VF(bp)) {
12801                 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
12802                 if (rc)
12803                         goto init_one_exit;
12804         }
12805
12806         /* Enable SRIOV if capability found in configuration space */
12807         rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
12808         if (rc)
12809                 goto init_one_exit;
12810
12811         /* calc qm_cid_count */
12812         bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
12813         BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
12814
12815         /* disable FCOE L2 queue for E1x*/
12816         if (CHIP_IS_E1x(bp))
12817                 bp->flags |= NO_FCOE_FLAG;
12818
12819         /* Set bp->num_queues for MSI-X mode*/
12820         bnx2x_set_num_queues(bp);
12821
12822         /* Configure interrupt mode: try to enable MSI-X/MSI if
12823          * needed.
12824          */
12825         rc = bnx2x_set_int_mode(bp);
12826         if (rc) {
12827                 dev_err(&pdev->dev, "Cannot set interrupts\n");
12828                 goto init_one_exit;
12829         }
12830         BNX2X_DEV_INFO("set interrupts successfully\n");
12831
12832         /* register the net device */
12833         rc = register_netdev(dev);
12834         if (rc) {
12835                 dev_err(&pdev->dev, "Cannot register net device\n");
12836                 goto init_one_exit;
12837         }
12838         BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
12839
12840         if (!NO_FCOE(bp)) {
12841                 /* Add storage MAC address */
12842                 rtnl_lock();
12843                 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12844                 rtnl_unlock();
12845         }
12846         if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
12847             pcie_speed == PCI_SPEED_UNKNOWN ||
12848             pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
12849                 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
12850         else
12851                 BNX2X_DEV_INFO(
12852                        "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
12853                        board_info[ent->driver_data].name,
12854                        (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
12855                        pcie_width,
12856                        pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
12857                        pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
12858                        pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
12859                        "Unknown",
12860                        dev->base_addr, bp->pdev->irq, dev->dev_addr);
12861
12862         return 0;
12863
12864 init_one_exit:
12865         if (bp->regview)
12866                 iounmap(bp->regview);
12867
12868         if (IS_PF(bp) && bp->doorbells)
12869                 iounmap(bp->doorbells);
12870
12871         free_netdev(dev);
12872
12873         if (atomic_read(&pdev->enable_cnt) == 1)
12874                 pci_release_regions(pdev);
12875
12876         pci_disable_device(pdev);
12877
12878         return rc;
12879 }
12880
12881 static void __bnx2x_remove(struct pci_dev *pdev,
12882                            struct net_device *dev,
12883                            struct bnx2x *bp,
12884                            bool remove_netdev)
12885 {
12886         /* Delete storage MAC address */
12887         if (!NO_FCOE(bp)) {
12888                 rtnl_lock();
12889                 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12890                 rtnl_unlock();
12891         }
12892
12893 #ifdef BCM_DCBNL
12894         /* Delete app tlvs from dcbnl */
12895         bnx2x_dcbnl_update_applist(bp, true);
12896 #endif
12897
12898         if (IS_PF(bp) &&
12899             !BP_NOMCP(bp) &&
12900             (bp->flags & BC_SUPPORTS_RMMOD_CMD))
12901                 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
12902
12903         /* Close the interface - either directly or implicitly */
12904         if (remove_netdev) {
12905                 unregister_netdev(dev);
12906         } else {
12907                 rtnl_lock();
12908                 dev_close(dev);
12909                 rtnl_unlock();
12910         }
12911
12912         bnx2x_iov_remove_one(bp);
12913
12914         /* Power on: we can't let PCI layer write to us while we are in D3 */
12915         if (IS_PF(bp))
12916                 bnx2x_set_power_state(bp, PCI_D0);
12917
12918         /* Disable MSI/MSI-X */
12919         bnx2x_disable_msi(bp);
12920
12921         /* Power off */
12922         if (IS_PF(bp))
12923                 bnx2x_set_power_state(bp, PCI_D3hot);
12924
12925         /* Make sure RESET task is not scheduled before continuing */
12926         cancel_delayed_work_sync(&bp->sp_rtnl_task);
12927
12928         /* send message via vfpf channel to release the resources of this vf */
12929         if (IS_VF(bp))
12930                 bnx2x_vfpf_release(bp);
12931
12932         /* Assumes no further PCIe PM changes will occur */
12933         if (system_state == SYSTEM_POWER_OFF) {
12934                 pci_wake_from_d3(pdev, bp->wol);
12935                 pci_set_power_state(pdev, PCI_D3hot);
12936         }
12937
12938         if (bp->regview)
12939                 iounmap(bp->regview);
12940
12941         /* for vf doorbells are part of the regview and were unmapped along with
12942          * it. FW is only loaded by PF.
12943          */
12944         if (IS_PF(bp)) {
12945                 if (bp->doorbells)
12946                         iounmap(bp->doorbells);
12947
12948                 bnx2x_release_firmware(bp);
12949         }
12950         bnx2x_free_mem_bp(bp);
12951
12952         if (remove_netdev)
12953                 free_netdev(dev);
12954
12955         if (atomic_read(&pdev->enable_cnt) == 1)
12956                 pci_release_regions(pdev);
12957
12958         pci_disable_device(pdev);
12959 }
12960
12961 static void bnx2x_remove_one(struct pci_dev *pdev)
12962 {
12963         struct net_device *dev = pci_get_drvdata(pdev);
12964         struct bnx2x *bp;
12965
12966         if (!dev) {
12967                 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
12968                 return;
12969         }
12970         bp = netdev_priv(dev);
12971
12972         __bnx2x_remove(pdev, dev, bp, true);
12973 }
12974
12975 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
12976 {
12977         bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
12978
12979         bp->rx_mode = BNX2X_RX_MODE_NONE;
12980
12981         if (CNIC_LOADED(bp))
12982                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
12983
12984         /* Stop Tx */
12985         bnx2x_tx_disable(bp);
12986         /* Delete all NAPI objects */
12987         bnx2x_del_all_napi(bp);
12988         if (CNIC_LOADED(bp))
12989                 bnx2x_del_all_napi_cnic(bp);
12990         netdev_reset_tc(bp->dev);
12991
12992         del_timer_sync(&bp->timer);
12993         cancel_delayed_work(&bp->sp_task);
12994         cancel_delayed_work(&bp->period_task);
12995
12996         spin_lock_bh(&bp->stats_lock);
12997         bp->stats_state = STATS_STATE_DISABLED;
12998         spin_unlock_bh(&bp->stats_lock);
12999
13000         bnx2x_save_statistics(bp);
13001
13002         netif_carrier_off(bp->dev);
13003
13004         return 0;
13005 }
13006
13007 /**
13008  * bnx2x_io_error_detected - called when PCI error is detected
13009  * @pdev: Pointer to PCI device
13010  * @state: The current pci connection state
13011  *
13012  * This function is called after a PCI bus error affecting
13013  * this device has been detected.
13014  */
13015 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
13016                                                 pci_channel_state_t state)
13017 {
13018         struct net_device *dev = pci_get_drvdata(pdev);
13019         struct bnx2x *bp = netdev_priv(dev);
13020
13021         rtnl_lock();
13022
13023         BNX2X_ERR("IO error detected\n");
13024
13025         netif_device_detach(dev);
13026
13027         if (state == pci_channel_io_perm_failure) {
13028                 rtnl_unlock();
13029                 return PCI_ERS_RESULT_DISCONNECT;
13030         }
13031
13032         if (netif_running(dev))
13033                 bnx2x_eeh_nic_unload(bp);
13034
13035         bnx2x_prev_path_mark_eeh(bp);
13036
13037         pci_disable_device(pdev);
13038
13039         rtnl_unlock();
13040
13041         /* Request a slot reset */
13042         return PCI_ERS_RESULT_NEED_RESET;
13043 }
13044
13045 /**
13046  * bnx2x_io_slot_reset - called after the PCI bus has been reset
13047  * @pdev: Pointer to PCI device
13048  *
13049  * Restart the card from scratch, as if from a cold-boot.
13050  */
13051 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
13052 {
13053         struct net_device *dev = pci_get_drvdata(pdev);
13054         struct bnx2x *bp = netdev_priv(dev);
13055         int i;
13056
13057         rtnl_lock();
13058         BNX2X_ERR("IO slot reset initializing...\n");
13059         if (pci_enable_device(pdev)) {
13060                 dev_err(&pdev->dev,
13061                         "Cannot re-enable PCI device after reset\n");
13062                 rtnl_unlock();
13063                 return PCI_ERS_RESULT_DISCONNECT;
13064         }
13065
13066         pci_set_master(pdev);
13067         pci_restore_state(pdev);
13068         pci_save_state(pdev);
13069
13070         if (netif_running(dev))
13071                 bnx2x_set_power_state(bp, PCI_D0);
13072
13073         if (netif_running(dev)) {
13074                 BNX2X_ERR("IO slot reset --> driver unload\n");
13075
13076                 /* MCP should have been reset; Need to wait for validity */
13077                 bnx2x_init_shmem(bp);
13078
13079                 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
13080                         u32 v;
13081
13082                         v = SHMEM2_RD(bp,
13083                                       drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
13084                         SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
13085                                   v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
13086                 }
13087                 bnx2x_drain_tx_queues(bp);
13088                 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
13089                 bnx2x_netif_stop(bp, 1);
13090                 bnx2x_free_irq(bp);
13091
13092                 /* Report UNLOAD_DONE to MCP */
13093                 bnx2x_send_unload_done(bp, true);
13094
13095                 bp->sp_state = 0;
13096                 bp->port.pmf = 0;
13097
13098                 bnx2x_prev_unload(bp);
13099
13100                 /* We should have reseted the engine, so It's fair to
13101                  * assume the FW will no longer write to the bnx2x driver.
13102                  */
13103                 bnx2x_squeeze_objects(bp);
13104                 bnx2x_free_skbs(bp);
13105                 for_each_rx_queue(bp, i)
13106                         bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
13107                 bnx2x_free_fp_mem(bp);
13108                 bnx2x_free_mem(bp);
13109
13110                 bp->state = BNX2X_STATE_CLOSED;
13111         }
13112
13113         rtnl_unlock();
13114
13115         return PCI_ERS_RESULT_RECOVERED;
13116 }
13117
13118 /**
13119  * bnx2x_io_resume - called when traffic can start flowing again
13120  * @pdev: Pointer to PCI device
13121  *
13122  * This callback is called when the error recovery driver tells us that
13123  * its OK to resume normal operation.
13124  */
13125 static void bnx2x_io_resume(struct pci_dev *pdev)
13126 {
13127         struct net_device *dev = pci_get_drvdata(pdev);
13128         struct bnx2x *bp = netdev_priv(dev);
13129
13130         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
13131                 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
13132                 return;
13133         }
13134
13135         rtnl_lock();
13136
13137         bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
13138                                                         DRV_MSG_SEQ_NUMBER_MASK;
13139
13140         if (netif_running(dev))
13141                 bnx2x_nic_load(bp, LOAD_NORMAL);
13142
13143         netif_device_attach(dev);
13144
13145         rtnl_unlock();
13146 }
13147
13148 static const struct pci_error_handlers bnx2x_err_handler = {
13149         .error_detected = bnx2x_io_error_detected,
13150         .slot_reset     = bnx2x_io_slot_reset,
13151         .resume         = bnx2x_io_resume,
13152 };
13153
13154 static void bnx2x_shutdown(struct pci_dev *pdev)
13155 {
13156         struct net_device *dev = pci_get_drvdata(pdev);
13157         struct bnx2x *bp;
13158
13159         if (!dev)
13160                 return;
13161
13162         bp = netdev_priv(dev);
13163         if (!bp)
13164                 return;
13165
13166         rtnl_lock();
13167         netif_device_detach(dev);
13168         rtnl_unlock();
13169
13170         /* Don't remove the netdevice, as there are scenarios which will cause
13171          * the kernel to hang, e.g., when trying to remove bnx2i while the
13172          * rootfs is mounted from SAN.
13173          */
13174         __bnx2x_remove(pdev, dev, bp, false);
13175 }
13176
13177 static struct pci_driver bnx2x_pci_driver = {
13178         .name        = DRV_MODULE_NAME,
13179         .id_table    = bnx2x_pci_tbl,
13180         .probe       = bnx2x_init_one,
13181         .remove      = bnx2x_remove_one,
13182         .suspend     = bnx2x_suspend,
13183         .resume      = bnx2x_resume,
13184         .err_handler = &bnx2x_err_handler,
13185 #ifdef CONFIG_BNX2X_SRIOV
13186         .sriov_configure = bnx2x_sriov_configure,
13187 #endif
13188         .shutdown    = bnx2x_shutdown,
13189 };
13190
13191 static int __init bnx2x_init(void)
13192 {
13193         int ret;
13194
13195         pr_info("%s", version);
13196
13197         bnx2x_wq = create_singlethread_workqueue("bnx2x");
13198         if (bnx2x_wq == NULL) {
13199                 pr_err("Cannot create workqueue\n");
13200                 return -ENOMEM;
13201         }
13202
13203         ret = pci_register_driver(&bnx2x_pci_driver);
13204         if (ret) {
13205                 pr_err("Cannot register driver\n");
13206                 destroy_workqueue(bnx2x_wq);
13207         }
13208         return ret;
13209 }
13210
13211 static void __exit bnx2x_cleanup(void)
13212 {
13213         struct list_head *pos, *q;
13214
13215         pci_unregister_driver(&bnx2x_pci_driver);
13216
13217         destroy_workqueue(bnx2x_wq);
13218
13219         /* Free globally allocated resources */
13220         list_for_each_safe(pos, q, &bnx2x_prev_list) {
13221                 struct bnx2x_prev_path_list *tmp =
13222                         list_entry(pos, struct bnx2x_prev_path_list, list);
13223                 list_del(pos);
13224                 kfree(tmp);
13225         }
13226 }
13227
13228 void bnx2x_notify_link_changed(struct bnx2x *bp)
13229 {
13230         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
13231 }
13232
13233 module_init(bnx2x_init);
13234 module_exit(bnx2x_cleanup);
13235
13236 /**
13237  * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
13238  *
13239  * @bp:         driver handle
13240  * @set:        set or clear the CAM entry
13241  *
13242  * This function will wait until the ramrod completion returns.
13243  * Return 0 if success, -ENODEV if ramrod doesn't return.
13244  */
13245 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
13246 {
13247         unsigned long ramrod_flags = 0;
13248
13249         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
13250         return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
13251                                  &bp->iscsi_l2_mac_obj, true,
13252                                  BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
13253 }
13254
13255 /* count denotes the number of new completions we have seen */
13256 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
13257 {
13258         struct eth_spe *spe;
13259         int cxt_index, cxt_offset;
13260
13261 #ifdef BNX2X_STOP_ON_ERROR
13262         if (unlikely(bp->panic))
13263                 return;
13264 #endif
13265
13266         spin_lock_bh(&bp->spq_lock);
13267         BUG_ON(bp->cnic_spq_pending < count);
13268         bp->cnic_spq_pending -= count;
13269
13270         for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
13271                 u16 type =  (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
13272                                 & SPE_HDR_CONN_TYPE) >>
13273                                 SPE_HDR_CONN_TYPE_SHIFT;
13274                 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
13275                                 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
13276
13277                 /* Set validation for iSCSI L2 client before sending SETUP
13278                  *  ramrod
13279                  */
13280                 if (type == ETH_CONNECTION_TYPE) {
13281                         if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
13282                                 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
13283                                         ILT_PAGE_CIDS;
13284                                 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
13285                                         (cxt_index * ILT_PAGE_CIDS);
13286                                 bnx2x_set_ctx_validation(bp,
13287                                         &bp->context[cxt_index].
13288                                                          vcxt[cxt_offset].eth,
13289                                         BNX2X_ISCSI_ETH_CID(bp));
13290                         }
13291                 }
13292
13293                 /*
13294                  * There may be not more than 8 L2, not more than 8 L5 SPEs
13295                  * and in the air. We also check that number of outstanding
13296                  * COMMON ramrods is not more than the EQ and SPQ can
13297                  * accommodate.
13298                  */
13299                 if (type == ETH_CONNECTION_TYPE) {
13300                         if (!atomic_read(&bp->cq_spq_left))
13301                                 break;
13302                         else
13303                                 atomic_dec(&bp->cq_spq_left);
13304                 } else if (type == NONE_CONNECTION_TYPE) {
13305                         if (!atomic_read(&bp->eq_spq_left))
13306                                 break;
13307                         else
13308                                 atomic_dec(&bp->eq_spq_left);
13309                 } else if ((type == ISCSI_CONNECTION_TYPE) ||
13310                            (type == FCOE_CONNECTION_TYPE)) {
13311                         if (bp->cnic_spq_pending >=
13312                             bp->cnic_eth_dev.max_kwqe_pending)
13313                                 break;
13314                         else
13315                                 bp->cnic_spq_pending++;
13316                 } else {
13317                         BNX2X_ERR("Unknown SPE type: %d\n", type);
13318                         bnx2x_panic();
13319                         break;
13320                 }
13321
13322                 spe = bnx2x_sp_get_next(bp);
13323                 *spe = *bp->cnic_kwq_cons;
13324
13325                 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
13326                    bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
13327
13328                 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
13329                         bp->cnic_kwq_cons = bp->cnic_kwq;
13330                 else
13331                         bp->cnic_kwq_cons++;
13332         }
13333         bnx2x_sp_prod_update(bp);
13334         spin_unlock_bh(&bp->spq_lock);
13335 }
13336
13337 static int bnx2x_cnic_sp_queue(struct net_device *dev,
13338                                struct kwqe_16 *kwqes[], u32 count)
13339 {
13340         struct bnx2x *bp = netdev_priv(dev);
13341         int i;
13342
13343 #ifdef BNX2X_STOP_ON_ERROR
13344         if (unlikely(bp->panic)) {
13345                 BNX2X_ERR("Can't post to SP queue while panic\n");
13346                 return -EIO;
13347         }
13348 #endif
13349
13350         if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
13351             (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
13352                 BNX2X_ERR("Handling parity error recovery. Try again later\n");
13353                 return -EAGAIN;
13354         }
13355
13356         spin_lock_bh(&bp->spq_lock);
13357
13358         for (i = 0; i < count; i++) {
13359                 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
13360
13361                 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
13362                         break;
13363
13364                 *bp->cnic_kwq_prod = *spe;
13365
13366                 bp->cnic_kwq_pending++;
13367
13368                 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
13369                    spe->hdr.conn_and_cmd_data, spe->hdr.type,
13370                    spe->data.update_data_addr.hi,
13371                    spe->data.update_data_addr.lo,
13372                    bp->cnic_kwq_pending);
13373
13374                 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
13375                         bp->cnic_kwq_prod = bp->cnic_kwq;
13376                 else
13377                         bp->cnic_kwq_prod++;
13378         }
13379
13380         spin_unlock_bh(&bp->spq_lock);
13381
13382         if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
13383                 bnx2x_cnic_sp_post(bp, 0);
13384
13385         return i;
13386 }
13387
13388 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13389 {
13390         struct cnic_ops *c_ops;
13391         int rc = 0;
13392
13393         mutex_lock(&bp->cnic_mutex);
13394         c_ops = rcu_dereference_protected(bp->cnic_ops,
13395                                           lockdep_is_held(&bp->cnic_mutex));
13396         if (c_ops)
13397                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13398         mutex_unlock(&bp->cnic_mutex);
13399
13400         return rc;
13401 }
13402
13403 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13404 {
13405         struct cnic_ops *c_ops;
13406         int rc = 0;
13407
13408         rcu_read_lock();
13409         c_ops = rcu_dereference(bp->cnic_ops);
13410         if (c_ops)
13411                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13412         rcu_read_unlock();
13413
13414         return rc;
13415 }
13416
13417 /*
13418  * for commands that have no data
13419  */
13420 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
13421 {
13422         struct cnic_ctl_info ctl = {0};
13423
13424         ctl.cmd = cmd;
13425
13426         return bnx2x_cnic_ctl_send(bp, &ctl);
13427 }
13428
13429 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
13430 {
13431         struct cnic_ctl_info ctl = {0};
13432
13433         /* first we tell CNIC and only then we count this as a completion */
13434         ctl.cmd = CNIC_CTL_COMPLETION_CMD;
13435         ctl.data.comp.cid = cid;
13436         ctl.data.comp.error = err;
13437
13438         bnx2x_cnic_ctl_send_bh(bp, &ctl);
13439         bnx2x_cnic_sp_post(bp, 0);
13440 }
13441
13442 /* Called with netif_addr_lock_bh() taken.
13443  * Sets an rx_mode config for an iSCSI ETH client.
13444  * Doesn't block.
13445  * Completion should be checked outside.
13446  */
13447 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
13448 {
13449         unsigned long accept_flags = 0, ramrod_flags = 0;
13450         u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13451         int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
13452
13453         if (start) {
13454                 /* Start accepting on iSCSI L2 ring. Accept all multicasts
13455                  * because it's the only way for UIO Queue to accept
13456                  * multicasts (in non-promiscuous mode only one Queue per
13457                  * function will receive multicast packets (leading in our
13458                  * case).
13459                  */
13460                 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
13461                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
13462                 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
13463                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
13464
13465                 /* Clear STOP_PENDING bit if START is requested */
13466                 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
13467
13468                 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
13469         } else
13470                 /* Clear START_PENDING bit if STOP is requested */
13471                 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
13472
13473         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
13474                 set_bit(sched_state, &bp->sp_state);
13475         else {
13476                 __set_bit(RAMROD_RX, &ramrod_flags);
13477                 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
13478                                     ramrod_flags);
13479         }
13480 }
13481
13482 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
13483 {
13484         struct bnx2x *bp = netdev_priv(dev);
13485         int rc = 0;
13486
13487         switch (ctl->cmd) {
13488         case DRV_CTL_CTXTBL_WR_CMD: {
13489                 u32 index = ctl->data.io.offset;
13490                 dma_addr_t addr = ctl->data.io.dma_addr;
13491
13492                 bnx2x_ilt_wr(bp, index, addr);
13493                 break;
13494         }
13495
13496         case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
13497                 int count = ctl->data.credit.credit_count;
13498
13499                 bnx2x_cnic_sp_post(bp, count);
13500                 break;
13501         }
13502
13503         /* rtnl_lock is held.  */
13504         case DRV_CTL_START_L2_CMD: {
13505                 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13506                 unsigned long sp_bits = 0;
13507
13508                 /* Configure the iSCSI classification object */
13509                 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
13510                                    cp->iscsi_l2_client_id,
13511                                    cp->iscsi_l2_cid, BP_FUNC(bp),
13512                                    bnx2x_sp(bp, mac_rdata),
13513                                    bnx2x_sp_mapping(bp, mac_rdata),
13514                                    BNX2X_FILTER_MAC_PENDING,
13515                                    &bp->sp_state, BNX2X_OBJ_TYPE_RX,
13516                                    &bp->macs_pool);
13517
13518                 /* Set iSCSI MAC address */
13519                 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
13520                 if (rc)
13521                         break;
13522
13523                 mmiowb();
13524                 barrier();
13525
13526                 /* Start accepting on iSCSI L2 ring */
13527
13528                 netif_addr_lock_bh(dev);
13529                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
13530                 netif_addr_unlock_bh(dev);
13531
13532                 /* bits to wait on */
13533                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13534                 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
13535
13536                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13537                         BNX2X_ERR("rx_mode completion timed out!\n");
13538
13539                 break;
13540         }
13541
13542         /* rtnl_lock is held.  */
13543         case DRV_CTL_STOP_L2_CMD: {
13544                 unsigned long sp_bits = 0;
13545
13546                 /* Stop accepting on iSCSI L2 ring */
13547                 netif_addr_lock_bh(dev);
13548                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
13549                 netif_addr_unlock_bh(dev);
13550
13551                 /* bits to wait on */
13552                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13553                 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
13554
13555                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13556                         BNX2X_ERR("rx_mode completion timed out!\n");
13557
13558                 mmiowb();
13559                 barrier();
13560
13561                 /* Unset iSCSI L2 MAC */
13562                 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
13563                                         BNX2X_ISCSI_ETH_MAC, true);
13564                 break;
13565         }
13566         case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
13567                 int count = ctl->data.credit.credit_count;
13568
13569                 smp_mb__before_atomic_inc();
13570                 atomic_add(count, &bp->cq_spq_left);
13571                 smp_mb__after_atomic_inc();
13572                 break;
13573         }
13574         case DRV_CTL_ULP_REGISTER_CMD: {
13575                 int ulp_type = ctl->data.register_data.ulp_type;
13576
13577                 if (CHIP_IS_E3(bp)) {
13578                         int idx = BP_FW_MB_IDX(bp);
13579                         u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13580                         int path = BP_PATH(bp);
13581                         int port = BP_PORT(bp);
13582                         int i;
13583                         u32 scratch_offset;
13584                         u32 *host_addr;
13585
13586                         /* first write capability to shmem2 */
13587                         if (ulp_type == CNIC_ULP_ISCSI)
13588                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13589                         else if (ulp_type == CNIC_ULP_FCOE)
13590                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13591                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13592
13593                         if ((ulp_type != CNIC_ULP_FCOE) ||
13594                             (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
13595                             (!(bp->flags &  BC_SUPPORTS_FCOE_FEATURES)))
13596                                 break;
13597
13598                         /* if reached here - should write fcoe capabilities */
13599                         scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
13600                         if (!scratch_offset)
13601                                 break;
13602                         scratch_offset += offsetof(struct glob_ncsi_oem_data,
13603                                                    fcoe_features[path][port]);
13604                         host_addr = (u32 *) &(ctl->data.register_data.
13605                                               fcoe_features);
13606                         for (i = 0; i < sizeof(struct fcoe_capabilities);
13607                              i += 4)
13608                                 REG_WR(bp, scratch_offset + i,
13609                                        *(host_addr + i/4));
13610                 }
13611                 break;
13612         }
13613
13614         case DRV_CTL_ULP_UNREGISTER_CMD: {
13615                 int ulp_type = ctl->data.ulp_type;
13616
13617                 if (CHIP_IS_E3(bp)) {
13618                         int idx = BP_FW_MB_IDX(bp);
13619                         u32 cap;
13620
13621                         cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13622                         if (ulp_type == CNIC_ULP_ISCSI)
13623                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13624                         else if (ulp_type == CNIC_ULP_FCOE)
13625                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13626                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13627                 }
13628                 break;
13629         }
13630
13631         default:
13632                 BNX2X_ERR("unknown command %x\n", ctl->cmd);
13633                 rc = -EINVAL;
13634         }
13635
13636         return rc;
13637 }
13638
13639 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
13640 {
13641         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13642
13643         if (bp->flags & USING_MSIX_FLAG) {
13644                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
13645                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
13646                 cp->irq_arr[0].vector = bp->msix_table[1].vector;
13647         } else {
13648                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
13649                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
13650         }
13651         if (!CHIP_IS_E1x(bp))
13652                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
13653         else
13654                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
13655
13656         cp->irq_arr[0].status_blk_num =  bnx2x_cnic_fw_sb_id(bp);
13657         cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
13658         cp->irq_arr[1].status_blk = bp->def_status_blk;
13659         cp->irq_arr[1].status_blk_num = DEF_SB_ID;
13660         cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
13661
13662         cp->num_irq = 2;
13663 }
13664
13665 void bnx2x_setup_cnic_info(struct bnx2x *bp)
13666 {
13667         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13668
13669         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13670                              bnx2x_cid_ilt_lines(bp);
13671         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13672         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13673         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13674
13675         DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
13676            BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
13677            cp->iscsi_l2_cid);
13678
13679         if (NO_ISCSI_OOO(bp))
13680                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13681 }
13682
13683 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
13684                                void *data)
13685 {
13686         struct bnx2x *bp = netdev_priv(dev);
13687         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13688         int rc;
13689
13690         DP(NETIF_MSG_IFUP, "Register_cnic called\n");
13691
13692         if (ops == NULL) {
13693                 BNX2X_ERR("NULL ops received\n");
13694                 return -EINVAL;
13695         }
13696
13697         if (!CNIC_SUPPORT(bp)) {
13698                 BNX2X_ERR("Can't register CNIC when not supported\n");
13699                 return -EOPNOTSUPP;
13700         }
13701
13702         if (!CNIC_LOADED(bp)) {
13703                 rc = bnx2x_load_cnic(bp);
13704                 if (rc) {
13705                         BNX2X_ERR("CNIC-related load failed\n");
13706                         return rc;
13707                 }
13708         }
13709
13710         bp->cnic_enabled = true;
13711
13712         bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
13713         if (!bp->cnic_kwq)
13714                 return -ENOMEM;
13715
13716         bp->cnic_kwq_cons = bp->cnic_kwq;
13717         bp->cnic_kwq_prod = bp->cnic_kwq;
13718         bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
13719
13720         bp->cnic_spq_pending = 0;
13721         bp->cnic_kwq_pending = 0;
13722
13723         bp->cnic_data = data;
13724
13725         cp->num_irq = 0;
13726         cp->drv_state |= CNIC_DRV_STATE_REGD;
13727         cp->iro_arr = bp->iro_arr;
13728
13729         bnx2x_setup_cnic_irq_info(bp);
13730
13731         rcu_assign_pointer(bp->cnic_ops, ops);
13732
13733         return 0;
13734 }
13735
13736 static int bnx2x_unregister_cnic(struct net_device *dev)
13737 {
13738         struct bnx2x *bp = netdev_priv(dev);
13739         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13740
13741         mutex_lock(&bp->cnic_mutex);
13742         cp->drv_state = 0;
13743         RCU_INIT_POINTER(bp->cnic_ops, NULL);
13744         mutex_unlock(&bp->cnic_mutex);
13745         synchronize_rcu();
13746         bp->cnic_enabled = false;
13747         kfree(bp->cnic_kwq);
13748         bp->cnic_kwq = NULL;
13749
13750         return 0;
13751 }
13752
13753 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
13754 {
13755         struct bnx2x *bp = netdev_priv(dev);
13756         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13757
13758         /* If both iSCSI and FCoE are disabled - return NULL in
13759          * order to indicate CNIC that it should not try to work
13760          * with this device.
13761          */
13762         if (NO_ISCSI(bp) && NO_FCOE(bp))
13763                 return NULL;
13764
13765         cp->drv_owner = THIS_MODULE;
13766         cp->chip_id = CHIP_ID(bp);
13767         cp->pdev = bp->pdev;
13768         cp->io_base = bp->regview;
13769         cp->io_base2 = bp->doorbells;
13770         cp->max_kwqe_pending = 8;
13771         cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
13772         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13773                              bnx2x_cid_ilt_lines(bp);
13774         cp->ctx_tbl_len = CNIC_ILT_LINES;
13775         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13776         cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
13777         cp->drv_ctl = bnx2x_drv_ctl;
13778         cp->drv_register_cnic = bnx2x_register_cnic;
13779         cp->drv_unregister_cnic = bnx2x_unregister_cnic;
13780         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13781         cp->iscsi_l2_client_id =
13782                 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13783         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13784
13785         if (NO_ISCSI_OOO(bp))
13786                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13787
13788         if (NO_ISCSI(bp))
13789                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
13790
13791         if (NO_FCOE(bp))
13792                 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
13793
13794         BNX2X_DEV_INFO(
13795                 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
13796            cp->ctx_blk_size,
13797            cp->ctx_tbl_offset,
13798            cp->ctx_tbl_len,
13799            cp->starting_cid);
13800         return cp;
13801 }
13802
13803 u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
13804 {
13805         struct bnx2x *bp = fp->bp;
13806         u32 offset = BAR_USTRORM_INTMEM;
13807
13808         if (IS_VF(bp))
13809                 return bnx2x_vf_ustorm_prods_offset(bp, fp);
13810         else if (!CHIP_IS_E1x(bp))
13811                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
13812         else
13813                 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
13814
13815         return offset;
13816 }
13817
13818 /* called only on E1H or E2.
13819  * When pretending to be PF, the pretend value is the function number 0...7
13820  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
13821  * combination
13822  */
13823 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
13824 {
13825         u32 pretend_reg;
13826
13827         if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
13828                 return -1;
13829
13830         /* get my own pretend register */
13831         pretend_reg = bnx2x_get_pretend_reg(bp);
13832         REG_WR(bp, pretend_reg, pretend_func_val);
13833         REG_RD(bp, pretend_reg);
13834         return 0;
13835 }