drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

   1 /* bnx2x_main.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/kernel.h>
  23 #include <linux/device.h>  /* for dev_info() */
  24 #include <linux/timer.h>
  25 #include <linux/errno.h>
  26 #include <linux/ioport.h>
  27 #include <linux/slab.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/pci.h>
  30 #include <linux/aer.h>
  31 #include <linux/init.h>
  32 #include <linux/netdevice.h>
  33 #include <linux/etherdevice.h>
  34 #include <linux/skbuff.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/bitops.h>
  37 #include <linux/irq.h>
  38 #include <linux/delay.h>
  39 #include <asm/byteorder.h>
  40 #include <linux/time.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/mii.h>
  43 #include <linux/if_vlan.h>
  44 #include <linux/crash_dump.h>
  45 #include <net/ip.h>
  46 #include <net/ipv6.h>
  47 #include <net/tcp.h>
  48 #include <net/checksum.h>
  49 #include <net/ip6_checksum.h>
  50 #include <linux/workqueue.h>
  51 #include <linux/crc32.h>
  52 #include <linux/crc32c.h>
  53 #include <linux/prefetch.h>
  54 #include <linux/zlib.h>
  55 #include <linux/io.h>
  56 #include <linux/semaphore.h>
  57 #include <linux/stringify.h>
  58 #include <linux/vmalloc.h>
  59
  60 #include "bnx2x.h"
  61 #include "bnx2x_init.h"
  62 #include "bnx2x_init_ops.h"
  63 #include "bnx2x_cmn.h"
  64 #include "bnx2x_vfpf.h"
  65 #include "bnx2x_dcb.h"
  66 #include "bnx2x_sp.h"
  67 #include <linux/firmware.h>
  68 #include "bnx2x_fw_file_hdr.h"
  69 /* FW files */
  70 #define FW_FILE_VERSION                                 \
  71         __stringify(BCM_5710_FW_MAJOR_VERSION) "."      \
  72         __stringify(BCM_5710_FW_MINOR_VERSION) "."      \
  73         __stringify(BCM_5710_FW_REVISION_VERSION) "."   \
  74         __stringify(BCM_5710_FW_ENGINEERING_VERSION)
  75 #define FW_FILE_NAME_E1         "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
  76 #define FW_FILE_NAME_E1H        "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
  77 #define FW_FILE_NAME_E2         "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
  78
  79 /* Time in jiffies before concluding the transmitter is hung */
  80 #define TX_TIMEOUT              (5*HZ)
  81
  82 static char version[] =
  83         "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
  84         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  85
  86 MODULE_AUTHOR("Eliezer Tamir");
  87 MODULE_DESCRIPTION("Broadcom NetXtreme II "
  88                    "BCM57710/57711/57711E/"
  89                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
  90                    "57840/57840_MF Driver");
  91 MODULE_LICENSE("GPL");
  92 MODULE_VERSION(DRV_MODULE_VERSION);
  93 MODULE_FIRMWARE(FW_FILE_NAME_E1);
  94 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
  95 MODULE_FIRMWARE(FW_FILE_NAME_E2);
  96
  97 int bnx2x_num_queues;
  98 module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
  99 MODULE_PARM_DESC(num_queues,
 100                  " Set number of queues (default is as a number of CPUs)");
 101
 102 static int disable_tpa;
 103 module_param(disable_tpa, int, S_IRUGO);
 104 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
 105
 106 static int int_mode;
 107 module_param(int_mode, int, S_IRUGO);
 108 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
 109                                 "(1 INT#x; 2 MSI)");
 110
 111 static int dropless_fc;
 112 module_param(dropless_fc, int, S_IRUGO);
 113 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
 114
 115 static int mrrs = -1;
 116 module_param(mrrs, int, S_IRUGO);
 117 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
 118
 119 static int debug;
 120 module_param(debug, int, S_IRUGO);
 121 MODULE_PARM_DESC(debug, " Default debug msglevel");
 122
 123 static struct workqueue_struct *bnx2x_wq;
 124 struct workqueue_struct *bnx2x_iov_wq;
 125
 126 struct bnx2x_mac_vals {
 127         u32 xmac_addr;
 128         u32 xmac_val;
 129         u32 emac_addr;
 130         u32 emac_val;
 131         u32 umac_addr;
 132         u32 umac_val;
 133         u32 bmac_addr;
 134         u32 bmac_val[2];
 135 };
 136
 137 enum bnx2x_board_type {
 138         BCM57710 = 0,
 139         BCM57711,
 140         BCM57711E,
 141         BCM57712,
 142         BCM57712_MF,
 143         BCM57712_VF,
 144         BCM57800,
 145         BCM57800_MF,
 146         BCM57800_VF,
 147         BCM57810,
 148         BCM57810_MF,
 149         BCM57810_VF,
 150         BCM57840_4_10,
 151         BCM57840_2_20,
 152         BCM57840_MF,
 153         BCM57840_VF,
 154         BCM57811,
 155         BCM57811_MF,
 156         BCM57840_O,
 157         BCM57840_MFO,
 158         BCM57811_VF
 159 };
 160
 161 /* indexed by board_type, above */
 162 static struct {
 163         char *name;
 164 } board_info[] = {
 165         [BCM57710]      = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
 166         [BCM57711]      = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
 167         [BCM57711E]     = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
 168         [BCM57712]      = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
 169         [BCM57712_MF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
 170         [BCM57712_VF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
 171         [BCM57800]      = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
 172         [BCM57800_MF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
 173         [BCM57800_VF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
 174         [BCM57810]      = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
 175         [BCM57810_MF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
 176         [BCM57810_VF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
 177         [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
 178         [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
 179         [BCM57840_MF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 180         [BCM57840_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
 181         [BCM57811]      = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
 182         [BCM57811_MF]   = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
 183         [BCM57840_O]    = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
 184         [BCM57840_MFO]  = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 185         [BCM57811_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
 186 };
 187
 188 #ifndef PCI_DEVICE_ID_NX2_57710
 189 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
 190 #endif
 191 #ifndef PCI_DEVICE_ID_NX2_57711
 192 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
 193 #endif
 194 #ifndef PCI_DEVICE_ID_NX2_57711E
 195 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
 196 #endif
 197 #ifndef PCI_DEVICE_ID_NX2_57712
 198 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
 199 #endif
 200 #ifndef PCI_DEVICE_ID_NX2_57712_MF
 201 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
 202 #endif
 203 #ifndef PCI_DEVICE_ID_NX2_57712_VF
 204 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
 205 #endif
 206 #ifndef PCI_DEVICE_ID_NX2_57800
 207 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
 208 #endif
 209 #ifndef PCI_DEVICE_ID_NX2_57800_MF
 210 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
 211 #endif
 212 #ifndef PCI_DEVICE_ID_NX2_57800_VF
 213 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
 214 #endif
 215 #ifndef PCI_DEVICE_ID_NX2_57810
 216 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
 217 #endif
 218 #ifndef PCI_DEVICE_ID_NX2_57810_MF
 219 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
 220 #endif
 221 #ifndef PCI_DEVICE_ID_NX2_57840_O
 222 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
 223 #endif
 224 #ifndef PCI_DEVICE_ID_NX2_57810_VF
 225 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
 226 #endif
 227 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
 228 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
 229 #endif
 230 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
 231 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
 232 #endif
 233 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
 234 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
 235 #endif
 236 #ifndef PCI_DEVICE_ID_NX2_57840_MF
 237 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
 238 #endif
 239 #ifndef PCI_DEVICE_ID_NX2_57840_VF
 240 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
 241 #endif
 242 #ifndef PCI_DEVICE_ID_NX2_57811
 243 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
 244 #endif
 245 #ifndef PCI_DEVICE_ID_NX2_57811_MF
 246 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
 247 #endif
 248 #ifndef PCI_DEVICE_ID_NX2_57811_VF
 249 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
 250 #endif
 251
 252 static const struct pci_device_id bnx2x_pci_tbl[] = {
 253         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
 254         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
 255         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
 256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
 257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
 258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
 259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
 260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
 261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
 262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
 263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
 264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
 265         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 266         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
 267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
 268         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
 269         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 270         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 271         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
 272         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
 273         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
 274         { 0 }
 275 };
 276
 277 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 278
 279 /* Global resources for unloading a previously loaded device */
 280 #define BNX2X_PREV_WAIT_NEEDED 1
 281 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
 282 static LIST_HEAD(bnx2x_prev_list);
 283
 284 /* Forward declaration */
 285 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
 286 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
 287 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
 288
 289 /****************************************************************************
 290 * General service functions
 291 ****************************************************************************/
 292
 293 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
 294
 295 static void __storm_memset_dma_mapping(struct bnx2x *bp,
 296                                        u32 addr, dma_addr_t mapping)
 297 {
 298         REG_WR(bp,  addr, U64_LO(mapping));
 299         REG_WR(bp,  addr + 4, U64_HI(mapping));
 300 }
 301
 302 static void storm_memset_spq_addr(struct bnx2x *bp,
 303                                   dma_addr_t mapping, u16 abs_fid)
 304 {
 305         u32 addr = XSEM_REG_FAST_MEMORY +
 306                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
 307
 308         __storm_memset_dma_mapping(bp, addr, mapping);
 309 }
 310
 311 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
 312                                   u16 pf_id)
 313 {
 314         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
 315                 pf_id);
 316         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
 317                 pf_id);
 318         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
 319                 pf_id);
 320         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
 321                 pf_id);
 322 }
 323
 324 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
 325                                  u8 enable)
 326 {
 327         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
 328                 enable);
 329         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
 330                 enable);
 331         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
 332                 enable);
 333         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
 334                 enable);
 335 }
 336
 337 static void storm_memset_eq_data(struct bnx2x *bp,
 338                                  struct event_ring_data *eq_data,
 339                                 u16 pfid)
 340 {
 341         size_t size = sizeof(struct event_ring_data);
 342
 343         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
 344
 345         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
 346 }
 347
 348 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
 349                                  u16 pfid)
 350 {
 351         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
 352         REG_WR16(bp, addr, eq_prod);
 353 }
 354
 355 /* used only at init
 356  * locking is done by mcp
 357  */
 358 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 359 {
 360         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 361         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
 362         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 363                                PCICFG_VENDOR_ID_OFFSET);
 364 }
 365
 366 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
 367 {
 368         u32 val;
 369
 370         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 371         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
 372         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 373                                PCICFG_VENDOR_ID_OFFSET);
 374
 375         return val;
 376 }
 377
 378 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
 379 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
 380 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
 381 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
 382 #define DMAE_DP_DST_NONE        "dst_addr [none]"
 383
 384 static void bnx2x_dp_dmae(struct bnx2x *bp,
 385                           struct dmae_command *dmae, int msglvl)
 386 {
 387         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
 388         int i;
 389
 390         switch (dmae->opcode & DMAE_COMMAND_DST) {
 391         case DMAE_CMD_DST_PCI:
 392                 if (src_type == DMAE_CMD_SRC_PCI)
 393                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 394                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
 395                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 396                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 397                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 398                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 399                            dmae->comp_val);
 400                 else
 401                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 402                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
 403                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 404                            dmae->opcode, dmae->src_addr_lo >> 2,
 405                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 406                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 407                            dmae->comp_val);
 408                 break;
 409         case DMAE_CMD_DST_GRC:
 410                 if (src_type == DMAE_CMD_SRC_PCI)
 411                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 412                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
 413                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 414                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 415                            dmae->len, dmae->dst_addr_lo >> 2,
 416                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 417                            dmae->comp_val);
 418                 else
 419                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 420                            "src [%08x], len [%d*4], dst [%08x]\n"
 421                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 422                            dmae->opcode, dmae->src_addr_lo >> 2,
 423                            dmae->len, dmae->dst_addr_lo >> 2,
 424                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 425                            dmae->comp_val);
 426                 break;
 427         default:
 428                 if (src_type == DMAE_CMD_SRC_PCI)
 429                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 430                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
 431                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 432                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 433                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 434                            dmae->comp_val);
 435                 else
 436                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 437                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
 438                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 439                            dmae->opcode, dmae->src_addr_lo >> 2,
 440                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 441                            dmae->comp_val);
 442                 break;
 443         }
 444
 445         for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
 446                 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
 447                    i, *(((u32 *)dmae) + i));
 448 }
 449
 450 /* copy command into DMAE command memory and set DMAE command go */
 451 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
 452 {
 453         u32 cmd_offset;
 454         int i;
 455
 456         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
 457         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
 458                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
 459         }
 460         REG_WR(bp, dmae_reg_go_c[idx], 1);
 461 }
 462
 463 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
 464 {
 465         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 466                            DMAE_CMD_C_ENABLE);
 467 }
 468
 469 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
 470 {
 471         return opcode & ~DMAE_CMD_SRC_RESET;
 472 }
 473
 474 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
 475                              bool with_comp, u8 comp_type)
 476 {
 477         u32 opcode = 0;
 478
 479         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 480                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 481
 482         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
 483
 484         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 485         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
 486                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
 487         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 488
 489 #ifdef __BIG_ENDIAN
 490         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 491 #else
 492         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 493 #endif
 494         if (with_comp)
 495                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 496         return opcode;
 497 }
 498
 499 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
 500                                       struct dmae_command *dmae,
 501                                       u8 src_type, u8 dst_type)
 502 {
 503         memset(dmae, 0, sizeof(struct dmae_command));
 504
 505         /* set the opcode */
 506         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
 507                                          true, DMAE_COMP_PCI);
 508
 509         /* fill in the completion parameters */
 510         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 511         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 512         dmae->comp_val = DMAE_COMP_VAL;
 513 }
 514
 515 /* issue a dmae command over the init-channel and wait for completion */
 516 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
 517                                u32 *comp)
 518 {
 519         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
 520         int rc = 0;
 521
 522         bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
 523
 524         /* Lock the dmae channel. Disable BHs to prevent a dead-lock
 525          * as long as this code is called both from syscall context and
 526          * from ndo_set_rx_mode() flow that may be called from BH.
 527          */
 528
 529         spin_lock_bh(&bp->dmae_lock);
 530
 531         /* reset completion */
 532         *comp = 0;
 533
 534         /* post the command on the channel used for initializations */
 535         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 536
 537         /* wait for completion */
 538         udelay(5);
 539         while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 540
 541                 if (!cnt ||
 542                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
 543                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 544                         BNX2X_ERR("DMAE timeout!\n");
 545                         rc = DMAE_TIMEOUT;
 546                         goto unlock;
 547                 }
 548                 cnt--;
 549                 udelay(50);
 550         }
 551         if (*comp & DMAE_PCI_ERR_FLAG) {
 552                 BNX2X_ERR("DMAE PCI error!\n");
 553                 rc = DMAE_PCI_ERROR;
 554         }
 555
 556 unlock:
 557
 558         spin_unlock_bh(&bp->dmae_lock);
 559
 560         return rc;
 561 }
 562
 563 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 564                       u32 len32)
 565 {
 566         int rc;
 567         struct dmae_command dmae;
 568
 569         if (!bp->dmae_ready) {
 570                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 571
 572                 if (CHIP_IS_E1(bp))
 573                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
 574                 else
 575                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
 576                 return;
 577         }
 578
 579         /* set opcode and fixed command fields */
 580         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 581
 582         /* fill in addresses and len */
 583         dmae.src_addr_lo = U64_LO(dma_addr);
 584         dmae.src_addr_hi = U64_HI(dma_addr);
 585         dmae.dst_addr_lo = dst_addr >> 2;
 586         dmae.dst_addr_hi = 0;
 587         dmae.len = len32;
 588
 589         /* issue the command and wait for completion */
 590         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 591         if (rc) {
 592                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 593 #ifdef BNX2X_STOP_ON_ERROR
 594                 bnx2x_panic();
 595 #endif
 596         }
 597 }
 598
 599 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 600 {
 601         int rc;
 602         struct dmae_command dmae;
 603
 604         if (!bp->dmae_ready) {
 605                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 606                 int i;
 607
 608                 if (CHIP_IS_E1(bp))
 609                         for (i = 0; i < len32; i++)
 610                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
 611                 else
 612                         for (i = 0; i < len32; i++)
 613                                 data[i] = REG_RD(bp, src_addr + i*4);
 614
 615                 return;
 616         }
 617
 618         /* set opcode and fixed command fields */
 619         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 620
 621         /* fill in addresses and len */
 622         dmae.src_addr_lo = src_addr >> 2;
 623         dmae.src_addr_hi = 0;
 624         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
 625         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
 626         dmae.len = len32;
 627
 628         /* issue the command and wait for completion */
 629         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 630         if (rc) {
 631                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 632 #ifdef BNX2X_STOP_ON_ERROR
 633                 bnx2x_panic();
 634 #endif
 635         }
 636 }
 637
 638 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
 639                                       u32 addr, u32 len)
 640 {
 641         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
 642         int offset = 0;
 643
 644         while (len > dmae_wr_max) {
 645                 bnx2x_write_dmae(bp, phys_addr + offset,
 646                                  addr + offset, dmae_wr_max);
 647                 offset += dmae_wr_max * 4;
 648                 len -= dmae_wr_max;
 649         }
 650
 651         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
 652 }
 653
 654 enum storms {
 655            XSTORM,
 656            TSTORM,
 657            CSTORM,
 658            USTORM,
 659            MAX_STORMS
 660 };
 661
 662 #define STORMS_NUM 4
 663 #define REGS_IN_ENTRY 4
 664
 665 static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
 666                                               enum storms storm,
 667                                               int entry)
 668 {
 669         switch (storm) {
 670         case XSTORM:
 671                 return XSTORM_ASSERT_LIST_OFFSET(entry);
 672         case TSTORM:
 673                 return TSTORM_ASSERT_LIST_OFFSET(entry);
 674         case CSTORM:
 675                 return CSTORM_ASSERT_LIST_OFFSET(entry);
 676         case USTORM:
 677                 return USTORM_ASSERT_LIST_OFFSET(entry);
 678         case MAX_STORMS:
 679         default:
 680                 BNX2X_ERR("unknown storm\n");
 681         }
 682         return -EINVAL;
 683 }
 684
 685 static int bnx2x_mc_assert(struct bnx2x *bp)
 686 {
 687         char last_idx;
 688         int i, j, rc = 0;
 689         enum storms storm;
 690         u32 regs[REGS_IN_ENTRY];
 691         u32 bar_storm_intmem[STORMS_NUM] = {
 692                 BAR_XSTRORM_INTMEM,
 693                 BAR_TSTRORM_INTMEM,
 694                 BAR_CSTRORM_INTMEM,
 695                 BAR_USTRORM_INTMEM
 696         };
 697         u32 storm_assert_list_index[STORMS_NUM] = {
 698                 XSTORM_ASSERT_LIST_INDEX_OFFSET,
 699                 TSTORM_ASSERT_LIST_INDEX_OFFSET,
 700                 CSTORM_ASSERT_LIST_INDEX_OFFSET,
 701                 USTORM_ASSERT_LIST_INDEX_OFFSET
 702         };
 703         char *storms_string[STORMS_NUM] = {
 704                 "XSTORM",
 705                 "TSTORM",
 706                 "CSTORM",
 707                 "USTORM"
 708         };
 709
 710         for (storm = XSTORM; storm < MAX_STORMS; storm++) {
 711                 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
 712                                    storm_assert_list_index[storm]);
 713                 if (last_idx)
 714                         BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
 715                                   storms_string[storm], last_idx);
 716
 717                 /* print the asserts */
 718                 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 719                         /* read a single assert entry */
 720                         for (j = 0; j < REGS_IN_ENTRY; j++)
 721                                 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
 722                                           bnx2x_get_assert_list_entry(bp,
 723                                                                       storm,
 724                                                                       i) +
 725                                           sizeof(u32) * j);
 726
 727                         /* log entry if it contains a valid assert */
 728                         if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 729                                 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 730                                           storms_string[storm], i, regs[3],
 731                                           regs[2], regs[1], regs[0]);
 732                                 rc++;
 733                         } else {
 734                                 break;
 735                         }
 736                 }
 737         }
 738
 739         BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
 740                   CHIP_IS_E1(bp) ? "everest1" :
 741                   CHIP_IS_E1H(bp) ? "everest1h" :
 742                   CHIP_IS_E2(bp) ? "everest2" : "everest3",
 743                   BCM_5710_FW_MAJOR_VERSION,
 744                   BCM_5710_FW_MINOR_VERSION,
 745                   BCM_5710_FW_REVISION_VERSION);
 746
 747         return rc;
 748 }
 749
 750 #define MCPR_TRACE_BUFFER_SIZE  (0x800)
 751 #define SCRATCH_BUFFER_SIZE(bp) \
 752         (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
 753
 754 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
 755 {
 756         u32 addr, val;
 757         u32 mark, offset;
 758         __be32 data[9];
 759         int word;
 760         u32 trace_shmem_base;
 761         if (BP_NOMCP(bp)) {
 762                 BNX2X_ERR("NO MCP - can not dump\n");
 763                 return;
 764         }
 765         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
 766                 (bp->common.bc_ver & 0xff0000) >> 16,
 767                 (bp->common.bc_ver & 0xff00) >> 8,
 768                 (bp->common.bc_ver & 0xff));
 769
 770         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
 771         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
 772                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
 773
 774         if (BP_PATH(bp) == 0)
 775                 trace_shmem_base = bp->common.shmem_base;
 776         else
 777                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
 778
 779         /* sanity */
 780         if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
 781             trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
 782                                 SCRATCH_BUFFER_SIZE(bp)) {
 783                 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
 784                           trace_shmem_base);
 785                 return;
 786         }
 787
 788         addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
 789
 790         /* validate TRCB signature */
 791         mark = REG_RD(bp, addr);
 792         if (mark != MFW_TRACE_SIGNATURE) {
 793                 BNX2X_ERR("Trace buffer signature is missing.");
 794                 return ;
 795         }
 796
 797         /* read cyclic buffer pointer */
 798         addr += 4;
 799         mark = REG_RD(bp, addr);
 800         mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
 801         if (mark >= trace_shmem_base || mark < addr + 4) {
 802                 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
 803                 return;
 804         }
 805         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
 806
 807         printk("%s", lvl);
 808
 809         /* dump buffer after the mark */
 810         for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
 811                 for (word = 0; word < 8; word++)
 812                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 813                 data[8] = 0x0;
 814                 pr_cont("%s", (char *)data);
 815         }
 816
 817         /* dump buffer before the mark */
 818         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
 819                 for (word = 0; word < 8; word++)
 820                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 821                 data[8] = 0x0;
 822                 pr_cont("%s", (char *)data);
 823         }
 824         printk("%s" "end of fw dump\n", lvl);
 825 }
 826
 827 static void bnx2x_fw_dump(struct bnx2x *bp)
 828 {
 829         bnx2x_fw_dump_lvl(bp, KERN_ERR);
 830 }
 831
 832 static void bnx2x_hc_int_disable(struct bnx2x *bp)
 833 {
 834         int port = BP_PORT(bp);
 835         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
 836         u32 val = REG_RD(bp, addr);
 837
 838         /* in E1 we must use only PCI configuration space to disable
 839          * MSI/MSIX capability
 840          * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
 841          */
 842         if (CHIP_IS_E1(bp)) {
 843                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
 844                  * Use mask register to prevent from HC sending interrupts
 845                  * after we exit the function
 846                  */
 847                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
 848
 849                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 850                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 851                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 852         } else
 853                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 854                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
 855                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 856                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 857
 858         DP(NETIF_MSG_IFDOWN,
 859            "write %x to HC %d (addr 0x%x)\n",
 860            val, port, addr);
 861
 862         /* flush all outstanding writes */
 863         mmiowb();
 864
 865         REG_WR(bp, addr, val);
 866         if (REG_RD(bp, addr) != val)
 867                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 868 }
 869
 870 static void bnx2x_igu_int_disable(struct bnx2x *bp)
 871 {
 872         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
 873
 874         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
 875                  IGU_PF_CONF_INT_LINE_EN |
 876                  IGU_PF_CONF_ATTN_BIT_EN);
 877
 878         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
 879
 880         /* flush all outstanding writes */
 881         mmiowb();
 882
 883         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
 884         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
 885                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 886 }
 887
 888 static void bnx2x_int_disable(struct bnx2x *bp)
 889 {
 890         if (bp->common.int_block == INT_BLOCK_HC)
 891                 bnx2x_hc_int_disable(bp);
 892         else
 893                 bnx2x_igu_int_disable(bp);
 894 }
 895
 896 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
 897 {
 898         int i;
 899         u16 j;
 900         struct hc_sp_status_block_data sp_sb_data;
 901         int func = BP_FUNC(bp);
 902 #ifdef BNX2X_STOP_ON_ERROR
 903         u16 start = 0, end = 0;
 904         u8 cos;
 905 #endif
 906         if (IS_PF(bp) && disable_int)
 907                 bnx2x_int_disable(bp);
 908
 909         bp->stats_state = STATS_STATE_DISABLED;
 910         bp->eth_stats.unrecoverable_error++;
 911         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
 912
 913         BNX2X_ERR("begin crash dump -----------------\n");
 914
 915         /* Indices */
 916         /* Common */
 917         if (IS_PF(bp)) {
 918                 struct host_sp_status_block *def_sb = bp->def_status_blk;
 919                 int data_size, cstorm_offset;
 920
 921                 BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
 922                           bp->def_idx, bp->def_att_idx, bp->attn_state,
 923                           bp->spq_prod_idx, bp->stats_counter);
 924                 BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
 925                           def_sb->atten_status_block.attn_bits,
 926                           def_sb->atten_status_block.attn_bits_ack,
 927                           def_sb->atten_status_block.status_block_id,
 928                           def_sb->atten_status_block.attn_bits_index);
 929                 BNX2X_ERR("     def (");
 930                 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
 931                         pr_cont("0x%x%s",
 932                                 def_sb->sp_sb.index_values[i],
 933                                 (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
 934
 935                 data_size = sizeof(struct hc_sp_status_block_data) /
 936                             sizeof(u32);
 937                 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
 938                 for (i = 0; i < data_size; i++)
 939                         *((u32 *)&sp_sb_data + i) =
 940                                 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
 941                                            i * sizeof(u32));
 942
 943                 pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
 944                         sp_sb_data.igu_sb_id,
 945                         sp_sb_data.igu_seg_id,
 946                         sp_sb_data.p_func.pf_id,
 947                         sp_sb_data.p_func.vnic_id,
 948                         sp_sb_data.p_func.vf_id,
 949                         sp_sb_data.p_func.vf_valid,
 950                         sp_sb_data.state);
 951         }
 952
 953         for_each_eth_queue(bp, i) {
 954                 struct bnx2x_fastpath *fp = &bp->fp[i];
 955                 int loop;
 956                 struct hc_status_block_data_e2 sb_data_e2;
 957                 struct hc_status_block_data_e1x sb_data_e1x;
 958                 struct hc_status_block_sm  *hc_sm_p =
 959                         CHIP_IS_E1x(bp) ?
 960                         sb_data_e1x.common.state_machine :
 961                         sb_data_e2.common.state_machine;
 962                 struct hc_index_data *hc_index_p =
 963                         CHIP_IS_E1x(bp) ?
 964                         sb_data_e1x.index_data :
 965                         sb_data_e2.index_data;
 966                 u8 data_size, cos;
 967                 u32 *sb_data_p;
 968                 struct bnx2x_fp_txdata txdata;
 969
 970                 if (!bp->fp)
 971                         break;
 972
 973                 if (!fp->rx_cons_sb)
 974                         continue;
 975
 976                 /* Rx */
 977                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
 978                           i, fp->rx_bd_prod, fp->rx_bd_cons,
 979                           fp->rx_comp_prod,
 980                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
 981                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
 982                           fp->rx_sge_prod, fp->last_max_sge,
 983                           le16_to_cpu(fp->fp_hc_idx));
 984
 985                 /* Tx */
 986                 for_each_cos_in_tx_queue(fp, cos)
 987                 {
 988                         if (!fp->txdata_ptr[cos])
 989                                 break;
 990
 991                         txdata = *fp->txdata_ptr[cos];
 992
 993                         if (!txdata.tx_cons_sb)
 994                                 continue;
 995
 996                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
 997                                   i, txdata.tx_pkt_prod,
 998                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
 999                                   txdata.tx_bd_cons,
1000                                   le16_to_cpu(*txdata.tx_cons_sb));
1001                 }
1002
1003                 loop = CHIP_IS_E1x(bp) ?
1004                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
1005
1006                 /* host sb data */
1007
1008                 if (IS_FCOE_FP(fp))
1009                         continue;
1010
1011                 BNX2X_ERR("     run indexes (");
1012                 for (j = 0; j < HC_SB_MAX_SM; j++)
1013                         pr_cont("0x%x%s",
1014                                fp->sb_running_index[j],
1015                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1016
1017                 BNX2X_ERR("     indexes (");
1018                 for (j = 0; j < loop; j++)
1019                         pr_cont("0x%x%s",
1020                                fp->sb_index_values[j],
1021                                (j == loop - 1) ? ")" : " ");
1022
1023                 /* VF cannot access FW refelection for status block */
1024                 if (IS_VF(bp))
1025                         continue;
1026
1027                 /* fw sb data */
1028                 data_size = CHIP_IS_E1x(bp) ?
1029                         sizeof(struct hc_status_block_data_e1x) :
1030                         sizeof(struct hc_status_block_data_e2);
1031                 data_size /= sizeof(u32);
1032                 sb_data_p = CHIP_IS_E1x(bp) ?
1033                         (u32 *)&sb_data_e1x :
1034                         (u32 *)&sb_data_e2;
1035                 /* copy sb data in here */
1036                 for (j = 0; j < data_size; j++)
1037                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1038                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1039                                 j * sizeof(u32));
1040
1041                 if (!CHIP_IS_E1x(bp)) {
1042                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1043                                 sb_data_e2.common.p_func.pf_id,
1044                                 sb_data_e2.common.p_func.vf_id,
1045                                 sb_data_e2.common.p_func.vf_valid,
1046                                 sb_data_e2.common.p_func.vnic_id,
1047                                 sb_data_e2.common.same_igu_sb_1b,
1048                                 sb_data_e2.common.state);
1049                 } else {
1050                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1051                                 sb_data_e1x.common.p_func.pf_id,
1052                                 sb_data_e1x.common.p_func.vf_id,
1053                                 sb_data_e1x.common.p_func.vf_valid,
1054                                 sb_data_e1x.common.p_func.vnic_id,
1055                                 sb_data_e1x.common.same_igu_sb_1b,
1056                                 sb_data_e1x.common.state);
1057                 }
1058
1059                 /* SB_SMs data */
1060                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1061                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1062                                 j, hc_sm_p[j].__flags,
1063                                 hc_sm_p[j].igu_sb_id,
1064                                 hc_sm_p[j].igu_seg_id,
1065                                 hc_sm_p[j].time_to_expire,
1066                                 hc_sm_p[j].timer_value);
1067                 }
1068
1069                 /* Indices data */
1070                 for (j = 0; j < loop; j++) {
1071                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1072                                hc_index_p[j].flags,
1073                                hc_index_p[j].timeout);
1074                 }
1075         }
1076
1077 #ifdef BNX2X_STOP_ON_ERROR
1078         if (IS_PF(bp)) {
1079                 /* event queue */
1080                 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1081                 for (i = 0; i < NUM_EQ_DESC; i++) {
1082                         u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1083
1084                         BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1085                                   i, bp->eq_ring[i].message.opcode,
1086                                   bp->eq_ring[i].message.error);
1087                         BNX2X_ERR("data: %x %x %x\n",
1088                                   data[0], data[1], data[2]);
1089                 }
1090         }
1091
1092         /* Rings */
1093         /* Rx */
1094         for_each_valid_rx_queue(bp, i) {
1095                 struct bnx2x_fastpath *fp = &bp->fp[i];
1096
1097                 if (!bp->fp)
1098                         break;
1099
1100                 if (!fp->rx_cons_sb)
1101                         continue;
1102
1103                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1104                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1105                 for (j = start; j != end; j = RX_BD(j + 1)) {
1106                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1107                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1108
1109                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1110                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1111                 }
1112
1113                 start = RX_SGE(fp->rx_sge_prod);
1114                 end = RX_SGE(fp->last_max_sge);
1115                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1116                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1117                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1118
1119                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1120                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1121                 }
1122
1123                 start = RCQ_BD(fp->rx_comp_cons - 10);
1124                 end = RCQ_BD(fp->rx_comp_cons + 503);
1125                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1126                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1127
1128                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1129                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1130                 }
1131         }
1132
1133         /* Tx */
1134         for_each_valid_tx_queue(bp, i) {
1135                 struct bnx2x_fastpath *fp = &bp->fp[i];
1136
1137                 if (!bp->fp)
1138                         break;
1139
1140                 for_each_cos_in_tx_queue(fp, cos) {
1141                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1142
1143                         if (!fp->txdata_ptr[cos])
1144                                 break;
1145
1146                         if (!txdata->tx_cons_sb)
1147                                 continue;
1148
1149                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1150                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1151                         for (j = start; j != end; j = TX_BD(j + 1)) {
1152                                 struct sw_tx_bd *sw_bd =
1153                                         &txdata->tx_buf_ring[j];
1154
1155                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1156                                           i, cos, j, sw_bd->skb,
1157                                           sw_bd->first_bd);
1158                         }
1159
1160                         start = TX_BD(txdata->tx_bd_cons - 10);
1161                         end = TX_BD(txdata->tx_bd_cons + 254);
1162                         for (j = start; j != end; j = TX_BD(j + 1)) {
1163                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1164
1165                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1166                                           i, cos, j, tx_bd[0], tx_bd[1],
1167                                           tx_bd[2], tx_bd[3]);
1168                         }
1169                 }
1170         }
1171 #endif
1172         if (IS_PF(bp)) {
1173                 bnx2x_fw_dump(bp);
1174                 bnx2x_mc_assert(bp);
1175         }
1176         BNX2X_ERR("end crash dump -----------------\n");
1177 }
1178
1179 /*
1180  * FLR Support for E2
1181  *
1182  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1183  * initialization.
1184  */
1185 #define FLR_WAIT_USEC           10000   /* 10 milliseconds */
1186 #define FLR_WAIT_INTERVAL       50      /* usec */
1187 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1188
1189 struct pbf_pN_buf_regs {
1190         int pN;
1191         u32 init_crd;
1192         u32 crd;
1193         u32 crd_freed;
1194 };
1195
1196 struct pbf_pN_cmd_regs {
1197         int pN;
1198         u32 lines_occup;
1199         u32 lines_freed;
1200 };
1201
1202 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1203                                      struct pbf_pN_buf_regs *regs,
1204                                      u32 poll_count)
1205 {
1206         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1207         u32 cur_cnt = poll_count;
1208
1209         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1210         crd = crd_start = REG_RD(bp, regs->crd);
1211         init_crd = REG_RD(bp, regs->init_crd);
1212
1213         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1214         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1215         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1216
1217         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1218                (init_crd - crd_start))) {
1219                 if (cur_cnt--) {
1220                         udelay(FLR_WAIT_INTERVAL);
1221                         crd = REG_RD(bp, regs->crd);
1222                         crd_freed = REG_RD(bp, regs->crd_freed);
1223                 } else {
1224                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1225                            regs->pN);
1226                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1227                            regs->pN, crd);
1228                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1229                            regs->pN, crd_freed);
1230                         break;
1231                 }
1232         }
1233         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1234            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1235 }
1236
1237 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1238                                      struct pbf_pN_cmd_regs *regs,
1239                                      u32 poll_count)
1240 {
1241         u32 occup, to_free, freed, freed_start;
1242         u32 cur_cnt = poll_count;
1243
1244         occup = to_free = REG_RD(bp, regs->lines_occup);
1245         freed = freed_start = REG_RD(bp, regs->lines_freed);
1246
1247         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1248         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1249
1250         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1251                 if (cur_cnt--) {
1252                         udelay(FLR_WAIT_INTERVAL);
1253                         occup = REG_RD(bp, regs->lines_occup);
1254                         freed = REG_RD(bp, regs->lines_freed);
1255                 } else {
1256                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1257                            regs->pN);
1258                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1259                            regs->pN, occup);
1260                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1261                            regs->pN, freed);
1262                         break;
1263                 }
1264         }
1265         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1266            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1267 }
1268
1269 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1270                                     u32 expected, u32 poll_count)
1271 {
1272         u32 cur_cnt = poll_count;
1273         u32 val;
1274
1275         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1276                 udelay(FLR_WAIT_INTERVAL);
1277
1278         return val;
1279 }
1280
1281 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1282                                     char *msg, u32 poll_cnt)
1283 {
1284         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1285         if (val != 0) {
1286                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1287                 return 1;
1288         }
1289         return 0;
1290 }
1291
1292 /* Common routines with VF FLR cleanup */
1293 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1294 {
1295         /* adjust polling timeout */
1296         if (CHIP_REV_IS_EMUL(bp))
1297                 return FLR_POLL_CNT * 2000;
1298
1299         if (CHIP_REV_IS_FPGA(bp))
1300                 return FLR_POLL_CNT * 120;
1301
1302         return FLR_POLL_CNT;
1303 }
1304
1305 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1306 {
1307         struct pbf_pN_cmd_regs cmd_regs[] = {
1308                 {0, (CHIP_IS_E3B0(bp)) ?
1309                         PBF_REG_TQ_OCCUPANCY_Q0 :
1310                         PBF_REG_P0_TQ_OCCUPANCY,
1311                     (CHIP_IS_E3B0(bp)) ?
1312                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1313                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1314                 {1, (CHIP_IS_E3B0(bp)) ?
1315                         PBF_REG_TQ_OCCUPANCY_Q1 :
1316                         PBF_REG_P1_TQ_OCCUPANCY,
1317                     (CHIP_IS_E3B0(bp)) ?
1318                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1319                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1320                 {4, (CHIP_IS_E3B0(bp)) ?
1321                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1322                         PBF_REG_P4_TQ_OCCUPANCY,
1323                     (CHIP_IS_E3B0(bp)) ?
1324                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1325                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1326         };
1327
1328         struct pbf_pN_buf_regs buf_regs[] = {
1329                 {0, (CHIP_IS_E3B0(bp)) ?
1330                         PBF_REG_INIT_CRD_Q0 :
1331                         PBF_REG_P0_INIT_CRD ,
1332                     (CHIP_IS_E3B0(bp)) ?
1333                         PBF_REG_CREDIT_Q0 :
1334                         PBF_REG_P0_CREDIT,
1335                     (CHIP_IS_E3B0(bp)) ?
1336                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1337                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1338                 {1, (CHIP_IS_E3B0(bp)) ?
1339                         PBF_REG_INIT_CRD_Q1 :
1340                         PBF_REG_P1_INIT_CRD,
1341                     (CHIP_IS_E3B0(bp)) ?
1342                         PBF_REG_CREDIT_Q1 :
1343                         PBF_REG_P1_CREDIT,
1344                     (CHIP_IS_E3B0(bp)) ?
1345                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1346                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1347                 {4, (CHIP_IS_E3B0(bp)) ?
1348                         PBF_REG_INIT_CRD_LB_Q :
1349                         PBF_REG_P4_INIT_CRD,
1350                     (CHIP_IS_E3B0(bp)) ?
1351                         PBF_REG_CREDIT_LB_Q :
1352                         PBF_REG_P4_CREDIT,
1353                     (CHIP_IS_E3B0(bp)) ?
1354                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1355                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1356         };
1357
1358         int i;
1359
1360         /* Verify the command queues are flushed P0, P1, P4 */
1361         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1362                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1363
1364         /* Verify the transmission buffers are flushed P0, P1, P4 */
1365         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1366                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1367 }
1368
1369 #define OP_GEN_PARAM(param) \
1370         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1371
1372 #define OP_GEN_TYPE(type) \
1373         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1374
1375 #define OP_GEN_AGG_VECT(index) \
1376         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1377
1378 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1379 {
1380         u32 op_gen_command = 0;
1381         u32 comp_addr = BAR_CSTRORM_INTMEM +
1382                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1383         int ret = 0;
1384
1385         if (REG_RD(bp, comp_addr)) {
1386                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1387                 return 1;
1388         }
1389
1390         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1391         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1392         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1393         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1394
1395         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1396         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1397
1398         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1399                 BNX2X_ERR("FW final cleanup did not succeed\n");
1400                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1401                    (REG_RD(bp, comp_addr)));
1402                 bnx2x_panic();
1403                 return 1;
1404         }
1405         /* Zero completion for next FLR */
1406         REG_WR(bp, comp_addr, 0);
1407
1408         return ret;
1409 }
1410
1411 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1412 {
1413         u16 status;
1414
1415         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1416         return status & PCI_EXP_DEVSTA_TRPND;
1417 }
1418
1419 /* PF FLR specific routines
1420 */
1421 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1422 {
1423         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1424         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1425                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1426                         "CFC PF usage counter timed out",
1427                         poll_cnt))
1428                 return 1;
1429
1430         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1431         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1432                         DORQ_REG_PF_USAGE_CNT,
1433                         "DQ PF usage counter timed out",
1434                         poll_cnt))
1435                 return 1;
1436
1437         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1438         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1439                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1440                         "QM PF usage counter timed out",
1441                         poll_cnt))
1442                 return 1;
1443
1444         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1445         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1446                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1447                         "Timers VNIC usage counter timed out",
1448                         poll_cnt))
1449                 return 1;
1450         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1451                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1452                         "Timers NUM_SCANS usage counter timed out",
1453                         poll_cnt))
1454                 return 1;
1455
1456         /* Wait DMAE PF usage counter to zero */
1457         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1458                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1459                         "DMAE command register timed out",
1460                         poll_cnt))
1461                 return 1;
1462
1463         return 0;
1464 }
1465
1466 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1467 {
1468         u32 val;
1469
1470         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1471         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1472
1473         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1474         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1475
1476         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1477         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1478
1479         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1480         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1481
1482         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1483         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1484
1485         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1486         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1487
1488         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1489         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1490
1491         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1492         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1493            val);
1494 }
1495
1496 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1497 {
1498         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1499
1500         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1501
1502         /* Re-enable PF target read access */
1503         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1504
1505         /* Poll HW usage counters */
1506         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1507         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1508                 return -EBUSY;
1509
1510         /* Zero the igu 'trailing edge' and 'leading edge' */
1511
1512         /* Send the FW cleanup command */
1513         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1514                 return -EBUSY;
1515
1516         /* ATC cleanup */
1517
1518         /* Verify TX hw is flushed */
1519         bnx2x_tx_hw_flushed(bp, poll_cnt);
1520
1521         /* Wait 100ms (not adjusted according to platform) */
1522         msleep(100);
1523
1524         /* Verify no pending pci transactions */
1525         if (bnx2x_is_pcie_pending(bp->pdev))
1526                 BNX2X_ERR("PCIE Transactions still pending\n");
1527
1528         /* Debug */
1529         bnx2x_hw_enable_status(bp);
1530
1531         /*
1532          * Master enable - Due to WB DMAE writes performed before this
1533          * register is re-initialized as part of the regular function init
1534          */
1535         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1536
1537         return 0;
1538 }
1539
1540 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1541 {
1542         int port = BP_PORT(bp);
1543         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1544         u32 val = REG_RD(bp, addr);
1545         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1546         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1547         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1548
1549         if (msix) {
1550                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1551                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1552                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1553                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1554                 if (single_msix)
1555                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1556         } else if (msi) {
1557                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1558                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1559                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1560                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1561         } else {
1562                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1563                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1564                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1565                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1566
1567                 if (!CHIP_IS_E1(bp)) {
1568                         DP(NETIF_MSG_IFUP,
1569                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1570
1571                         REG_WR(bp, addr, val);
1572
1573                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1574                 }
1575         }
1576
1577         if (CHIP_IS_E1(bp))
1578                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1579
1580         DP(NETIF_MSG_IFUP,
1581            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1582            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1583
1584         REG_WR(bp, addr, val);
1585         /*
1586          * Ensure that HC_CONFIG is written before leading/trailing edge config
1587          */
1588         mmiowb();
1589         barrier();
1590
1591         if (!CHIP_IS_E1(bp)) {
1592                 /* init leading/trailing edge */
1593                 if (IS_MF(bp)) {
1594                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1595                         if (bp->port.pmf)
1596                                 /* enable nig and gpio3 attention */
1597                                 val |= 0x1100;
1598                 } else
1599                         val = 0xffff;
1600
1601                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1602                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1603         }
1604
1605         /* Make sure that interrupts are indeed enabled from here on */
1606         mmiowb();
1607 }
1608
1609 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1610 {
1611         u32 val;
1612         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1613         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1614         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1615
1616         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1617
1618         if (msix) {
1619                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1620                          IGU_PF_CONF_SINGLE_ISR_EN);
1621                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1622                         IGU_PF_CONF_ATTN_BIT_EN);
1623
1624                 if (single_msix)
1625                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1626         } else if (msi) {
1627                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1628                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1629                         IGU_PF_CONF_ATTN_BIT_EN |
1630                         IGU_PF_CONF_SINGLE_ISR_EN);
1631         } else {
1632                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1633                 val |= (IGU_PF_CONF_INT_LINE_EN |
1634                         IGU_PF_CONF_ATTN_BIT_EN |
1635                         IGU_PF_CONF_SINGLE_ISR_EN);
1636         }
1637
1638         /* Clean previous status - need to configure igu prior to ack*/
1639         if ((!msix) || single_msix) {
1640                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1641                 bnx2x_ack_int(bp);
1642         }
1643
1644         val |= IGU_PF_CONF_FUNC_EN;
1645
1646         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1647            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1648
1649         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1650
1651         if (val & IGU_PF_CONF_INT_LINE_EN)
1652                 pci_intx(bp->pdev, true);
1653
1654         barrier();
1655
1656         /* init leading/trailing edge */
1657         if (IS_MF(bp)) {
1658                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1659                 if (bp->port.pmf)
1660                         /* enable nig and gpio3 attention */
1661                         val |= 0x1100;
1662         } else
1663                 val = 0xffff;
1664
1665         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1666         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1667
1668         /* Make sure that interrupts are indeed enabled from here on */
1669         mmiowb();
1670 }
1671
1672 void bnx2x_int_enable(struct bnx2x *bp)
1673 {
1674         if (bp->common.int_block == INT_BLOCK_HC)
1675                 bnx2x_hc_int_enable(bp);
1676         else
1677                 bnx2x_igu_int_enable(bp);
1678 }
1679
1680 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1681 {
1682         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1683         int i, offset;
1684
1685         if (disable_hw)
1686                 /* prevent the HW from sending interrupts */
1687                 bnx2x_int_disable(bp);
1688
1689         /* make sure all ISRs are done */
1690         if (msix) {
1691                 synchronize_irq(bp->msix_table[0].vector);
1692                 offset = 1;
1693                 if (CNIC_SUPPORT(bp))
1694                         offset++;
1695                 for_each_eth_queue(bp, i)
1696                         synchronize_irq(bp->msix_table[offset++].vector);
1697         } else
1698                 synchronize_irq(bp->pdev->irq);
1699
1700         /* make sure sp_task is not running */
1701         cancel_delayed_work(&bp->sp_task);
1702         cancel_delayed_work(&bp->period_task);
1703         flush_workqueue(bnx2x_wq);
1704 }
1705
1706 /* fast path */
1707
1708 /*
1709  * General service functions
1710  */
1711
1712 /* Return true if succeeded to acquire the lock */
1713 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1714 {
1715         u32 lock_status;
1716         u32 resource_bit = (1 << resource);
1717         int func = BP_FUNC(bp);
1718         u32 hw_lock_control_reg;
1719
1720         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1721            "Trying to take a lock on resource %d\n", resource);
1722
1723         /* Validating that the resource is within range */
1724         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1725                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1726                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1727                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1728                 return false;
1729         }
1730
1731         if (func <= 5)
1732                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1733         else
1734                 hw_lock_control_reg =
1735                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1736
1737         /* Try to acquire the lock */
1738         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1739         lock_status = REG_RD(bp, hw_lock_control_reg);
1740         if (lock_status & resource_bit)
1741                 return true;
1742
1743         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1744            "Failed to get a lock on resource %d\n", resource);
1745         return false;
1746 }
1747
1748 /**
1749  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1750  *
1751  * @bp: driver handle
1752  *
1753  * Returns the recovery leader resource id according to the engine this function
1754  * belongs to. Currently only only 2 engines is supported.
1755  */
1756 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1757 {
1758         if (BP_PATH(bp))
1759                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1760         else
1761                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1762 }
1763
1764 /**
1765  * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1766  *
1767  * @bp: driver handle
1768  *
1769  * Tries to acquire a leader lock for current engine.
1770  */
1771 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1772 {
1773         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1774 }
1775
1776 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1777
1778 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1779 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1780 {
1781         /* Set the interrupt occurred bit for the sp-task to recognize it
1782          * must ack the interrupt and transition according to the IGU
1783          * state machine.
1784          */
1785         atomic_set(&bp->interrupt_occurred, 1);
1786
1787         /* The sp_task must execute only after this bit
1788          * is set, otherwise we will get out of sync and miss all
1789          * further interrupts. Hence, the barrier.
1790          */
1791         smp_wmb();
1792
1793         /* schedule sp_task to workqueue */
1794         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1795 }
1796
1797 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1798 {
1799         struct bnx2x *bp = fp->bp;
1800         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1801         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1802         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1803         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1804
1805         DP(BNX2X_MSG_SP,
1806            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1807            fp->index, cid, command, bp->state,
1808            rr_cqe->ramrod_cqe.ramrod_type);
1809
1810         /* If cid is within VF range, replace the slowpath object with the
1811          * one corresponding to this VF
1812          */
1813         if (cid >= BNX2X_FIRST_VF_CID  &&
1814             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1815                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1816
1817         switch (command) {
1818         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1819                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1820                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1821                 break;
1822
1823         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1824                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1825                 drv_cmd = BNX2X_Q_CMD_SETUP;
1826                 break;
1827
1828         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1829                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1830                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1831                 break;
1832
1833         case (RAMROD_CMD_ID_ETH_HALT):
1834                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1835                 drv_cmd = BNX2X_Q_CMD_HALT;
1836                 break;
1837
1838         case (RAMROD_CMD_ID_ETH_TERMINATE):
1839                 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1840                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1841                 break;
1842
1843         case (RAMROD_CMD_ID_ETH_EMPTY):
1844                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1845                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1846                 break;
1847
1848         case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1849                 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1850                 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1851                 break;
1852
1853         default:
1854                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1855                           command, fp->index);
1856                 return;
1857         }
1858
1859         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1860             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1861                 /* q_obj->complete_cmd() failure means that this was
1862                  * an unexpected completion.
1863                  *
1864                  * In this case we don't want to increase the bp->spq_left
1865                  * because apparently we haven't sent this command the first
1866                  * place.
1867                  */
1868 #ifdef BNX2X_STOP_ON_ERROR
1869                 bnx2x_panic();
1870 #else
1871                 return;
1872 #endif
1873
1874         smp_mb__before_atomic();
1875         atomic_inc(&bp->cq_spq_left);
1876         /* push the change in bp->spq_left and towards the memory */
1877         smp_mb__after_atomic();
1878
1879         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1880
1881         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1882             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1883                 /* if Q update ramrod is completed for last Q in AFEX vif set
1884                  * flow, then ACK MCP at the end
1885                  *
1886                  * mark pending ACK to MCP bit.
1887                  * prevent case that both bits are cleared.
1888                  * At the end of load/unload driver checks that
1889                  * sp_state is cleared, and this order prevents
1890                  * races
1891                  */
1892                 smp_mb__before_atomic();
1893                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1894                 wmb();
1895                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1896                 smp_mb__after_atomic();
1897
1898                 /* schedule the sp task as mcp ack is required */
1899                 bnx2x_schedule_sp_task(bp);
1900         }
1901
1902         return;
1903 }
1904
1905 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1906 {
1907         struct bnx2x *bp = netdev_priv(dev_instance);
1908         u16 status = bnx2x_ack_int(bp);
1909         u16 mask;
1910         int i;
1911         u8 cos;
1912
1913         /* Return here if interrupt is shared and it's not for us */
1914         if (unlikely(status == 0)) {
1915                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1916                 return IRQ_NONE;
1917         }
1918         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1919
1920 #ifdef BNX2X_STOP_ON_ERROR
1921         if (unlikely(bp->panic))
1922                 return IRQ_HANDLED;
1923 #endif
1924
1925         for_each_eth_queue(bp, i) {
1926                 struct bnx2x_fastpath *fp = &bp->fp[i];
1927
1928                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1929                 if (status & mask) {
1930                         /* Handle Rx or Tx according to SB id */
1931                         for_each_cos_in_tx_queue(fp, cos)
1932                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1933                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1934                         napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
1935                         status &= ~mask;
1936                 }
1937         }
1938
1939         if (CNIC_SUPPORT(bp)) {
1940                 mask = 0x2;
1941                 if (status & (mask | 0x1)) {
1942                         struct cnic_ops *c_ops = NULL;
1943
1944                         rcu_read_lock();
1945                         c_ops = rcu_dereference(bp->cnic_ops);
1946                         if (c_ops && (bp->cnic_eth_dev.drv_state &
1947                                       CNIC_DRV_STATE_HANDLES_IRQ))
1948                                 c_ops->cnic_handler(bp->cnic_data, NULL);
1949                         rcu_read_unlock();
1950
1951                         status &= ~mask;
1952                 }
1953         }
1954
1955         if (unlikely(status & 0x1)) {
1956
1957                 /* schedule sp task to perform default status block work, ack
1958                  * attentions and enable interrupts.
1959                  */
1960                 bnx2x_schedule_sp_task(bp);
1961
1962                 status &= ~0x1;
1963                 if (!status)
1964                         return IRQ_HANDLED;
1965         }
1966
1967         if (unlikely(status))
1968                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1969                    status);
1970
1971         return IRQ_HANDLED;
1972 }
1973
1974 /* Link */
1975
1976 /*
1977  * General service functions
1978  */
1979
1980 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1981 {
1982         u32 lock_status;
1983         u32 resource_bit = (1 << resource);
1984         int func = BP_FUNC(bp);
1985         u32 hw_lock_control_reg;
1986         int cnt;
1987
1988         /* Validating that the resource is within range */
1989         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1990                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1991                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1992                 return -EINVAL;
1993         }
1994
1995         if (func <= 5) {
1996                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1997         } else {
1998                 hw_lock_control_reg =
1999                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2000         }
2001
2002         /* Validating that the resource is not already taken */
2003         lock_status = REG_RD(bp, hw_lock_control_reg);
2004         if (lock_status & resource_bit) {
2005                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
2006                    lock_status, resource_bit);
2007                 return -EEXIST;
2008         }
2009
2010         /* Try for 5 second every 5ms */
2011         for (cnt = 0; cnt < 1000; cnt++) {
2012                 /* Try to acquire the lock */
2013                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2014                 lock_status = REG_RD(bp, hw_lock_control_reg);
2015                 if (lock_status & resource_bit)
2016                         return 0;
2017
2018                 usleep_range(5000, 10000);
2019         }
2020         BNX2X_ERR("Timeout\n");
2021         return -EAGAIN;
2022 }
2023
2024 int bnx2x_release_leader_lock(struct bnx2x *bp)
2025 {
2026         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2027 }
2028
2029 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
2030 {
2031         u32 lock_status;
2032         u32 resource_bit = (1 << resource);
2033         int func = BP_FUNC(bp);
2034         u32 hw_lock_control_reg;
2035
2036         /* Validating that the resource is within range */
2037         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2038                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2039                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
2040                 return -EINVAL;
2041         }
2042
2043         if (func <= 5) {
2044                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2045         } else {
2046                 hw_lock_control_reg =
2047                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2048         }
2049
2050         /* Validating that the resource is currently taken */
2051         lock_status = REG_RD(bp, hw_lock_control_reg);
2052         if (!(lock_status & resource_bit)) {
2053                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2054                           lock_status, resource_bit);
2055                 return -EFAULT;
2056         }
2057
2058         REG_WR(bp, hw_lock_control_reg, resource_bit);
2059         return 0;
2060 }
2061
2062 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2063 {
2064         /* The GPIO should be swapped if swap register is set and active */
2065         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2066                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2067         int gpio_shift = gpio_num +
2068                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2069         u32 gpio_mask = (1 << gpio_shift);
2070         u32 gpio_reg;
2071         int value;
2072
2073         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2074                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2075                 return -EINVAL;
2076         }
2077
2078         /* read GPIO value */
2079         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2080
2081         /* get the requested pin value */
2082         if ((gpio_reg & gpio_mask) == gpio_mask)
2083                 value = 1;
2084         else
2085                 value = 0;
2086
2087         return value;
2088 }
2089
2090 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2091 {
2092         /* The GPIO should be swapped if swap register is set and active */
2093         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2094                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2095         int gpio_shift = gpio_num +
2096                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2097         u32 gpio_mask = (1 << gpio_shift);
2098         u32 gpio_reg;
2099
2100         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2101                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2102                 return -EINVAL;
2103         }
2104
2105         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2106         /* read GPIO and mask except the float bits */
2107         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2108
2109         switch (mode) {
2110         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2111                 DP(NETIF_MSG_LINK,
2112                    "Set GPIO %d (shift %d) -> output low\n",
2113                    gpio_num, gpio_shift);
2114                 /* clear FLOAT and set CLR */
2115                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2116                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2117                 break;
2118
2119         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2120                 DP(NETIF_MSG_LINK,
2121                    "Set GPIO %d (shift %d) -> output high\n",
2122                    gpio_num, gpio_shift);
2123                 /* clear FLOAT and set SET */
2124                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2125                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2126                 break;
2127
2128         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2129                 DP(NETIF_MSG_LINK,
2130                    "Set GPIO %d (shift %d) -> input\n",
2131                    gpio_num, gpio_shift);
2132                 /* set FLOAT */
2133                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2134                 break;
2135
2136         default:
2137                 break;
2138         }
2139
2140         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2141         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2142
2143         return 0;
2144 }
2145
2146 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2147 {
2148         u32 gpio_reg = 0;
2149         int rc = 0;
2150
2151         /* Any port swapping should be handled by caller. */
2152
2153         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2154         /* read GPIO and mask except the float bits */
2155         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2156         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2157         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2158         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2159
2160         switch (mode) {
2161         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2162                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2163                 /* set CLR */
2164                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2165                 break;
2166
2167         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2168                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2169                 /* set SET */
2170                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2171                 break;
2172
2173         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2174                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2175                 /* set FLOAT */
2176                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2177                 break;
2178
2179         default:
2180                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2181                 rc = -EINVAL;
2182                 break;
2183         }
2184
2185         if (rc == 0)
2186                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2187
2188         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2189
2190         return rc;
2191 }
2192
2193 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2194 {
2195         /* The GPIO should be swapped if swap register is set and active */
2196         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2197                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2198         int gpio_shift = gpio_num +
2199                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2200         u32 gpio_mask = (1 << gpio_shift);
2201         u32 gpio_reg;
2202
2203         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2204                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2205                 return -EINVAL;
2206         }
2207
2208         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2209         /* read GPIO int */
2210         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2211
2212         switch (mode) {
2213         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2214                 DP(NETIF_MSG_LINK,
2215                    "Clear GPIO INT %d (shift %d) -> output low\n",
2216                    gpio_num, gpio_shift);
2217                 /* clear SET and set CLR */
2218                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2219                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2220                 break;
2221
2222         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2223                 DP(NETIF_MSG_LINK,
2224                    "Set GPIO INT %d (shift %d) -> output high\n",
2225                    gpio_num, gpio_shift);
2226                 /* clear CLR and set SET */
2227                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2228                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2229                 break;
2230
2231         default:
2232                 break;
2233         }
2234
2235         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2236         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2237
2238         return 0;
2239 }
2240
2241 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2242 {
2243         u32 spio_reg;
2244
2245         /* Only 2 SPIOs are configurable */
2246         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2247                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2248                 return -EINVAL;
2249         }
2250
2251         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2252         /* read SPIO and mask except the float bits */
2253         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2254
2255         switch (mode) {
2256         case MISC_SPIO_OUTPUT_LOW:
2257                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2258                 /* clear FLOAT and set CLR */
2259                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2260                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2261                 break;
2262
2263         case MISC_SPIO_OUTPUT_HIGH:
2264                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2265                 /* clear FLOAT and set SET */
2266                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2267                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2268                 break;
2269
2270         case MISC_SPIO_INPUT_HI_Z:
2271                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2272                 /* set FLOAT */
2273                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2274                 break;
2275
2276         default:
2277                 break;
2278         }
2279
2280         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2281         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2282
2283         return 0;
2284 }
2285
2286 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2287 {
2288         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2289         switch (bp->link_vars.ieee_fc &
2290                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2291         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2292                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2293                                                    ADVERTISED_Pause);
2294                 break;
2295
2296         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2297                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2298                                                   ADVERTISED_Pause);
2299                 break;
2300
2301         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2302                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2303                 break;
2304
2305         default:
2306                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2307                                                    ADVERTISED_Pause);
2308                 break;
2309         }
2310 }
2311
2312 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2313 {
2314         /* Initialize link parameters structure variables
2315          * It is recommended to turn off RX FC for jumbo frames
2316          *  for better performance
2317          */
2318         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2319                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2320         else
2321                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2322 }
2323
2324 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2325 {
2326         u32 pause_enabled = 0;
2327
2328         if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2329                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2330                         pause_enabled = 1;
2331
2332                 REG_WR(bp, BAR_USTRORM_INTMEM +
2333                            USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2334                        pause_enabled);
2335         }
2336
2337         DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2338            pause_enabled ? "enabled" : "disabled");
2339 }
2340
2341 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2342 {
2343         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2344         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2345
2346         if (!BP_NOMCP(bp)) {
2347                 bnx2x_set_requested_fc(bp);
2348                 bnx2x_acquire_phy_lock(bp);
2349
2350                 if (load_mode == LOAD_DIAG) {
2351                         struct link_params *lp = &bp->link_params;
2352                         lp->loopback_mode = LOOPBACK_XGXS;
2353                         /* do PHY loopback at 10G speed, if possible */
2354                         if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2355                                 if (lp->speed_cap_mask[cfx_idx] &
2356                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2357                                         lp->req_line_speed[cfx_idx] =
2358                                         SPEED_10000;
2359                                 else
2360                                         lp->req_line_speed[cfx_idx] =
2361                                         SPEED_1000;
2362                         }
2363                 }
2364
2365                 if (load_mode == LOAD_LOOPBACK_EXT) {
2366                         struct link_params *lp = &bp->link_params;
2367                         lp->loopback_mode = LOOPBACK_EXT;
2368                 }
2369
2370                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2371
2372                 bnx2x_release_phy_lock(bp);
2373
2374                 bnx2x_init_dropless_fc(bp);
2375
2376                 bnx2x_calc_fc_adv(bp);
2377
2378                 if (bp->link_vars.link_up) {
2379                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2380                         bnx2x_link_report(bp);
2381                 }
2382                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2383                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2384                 return rc;
2385         }
2386         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2387         return -EINVAL;
2388 }
2389
2390 void bnx2x_link_set(struct bnx2x *bp)
2391 {
2392         if (!BP_NOMCP(bp)) {
2393                 bnx2x_acquire_phy_lock(bp);
2394                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2395                 bnx2x_release_phy_lock(bp);
2396
2397                 bnx2x_init_dropless_fc(bp);
2398
2399                 bnx2x_calc_fc_adv(bp);
2400         } else
2401                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2402 }
2403
2404 static void bnx2x__link_reset(struct bnx2x *bp)
2405 {
2406         if (!BP_NOMCP(bp)) {
2407                 bnx2x_acquire_phy_lock(bp);
2408                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2409                 bnx2x_release_phy_lock(bp);
2410         } else
2411                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2412 }
2413
2414 void bnx2x_force_link_reset(struct bnx2x *bp)
2415 {
2416         bnx2x_acquire_phy_lock(bp);
2417         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2418         bnx2x_release_phy_lock(bp);
2419 }
2420
2421 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2422 {
2423         u8 rc = 0;
2424
2425         if (!BP_NOMCP(bp)) {
2426                 bnx2x_acquire_phy_lock(bp);
2427                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2428                                      is_serdes);
2429                 bnx2x_release_phy_lock(bp);
2430         } else
2431                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2432
2433         return rc;
2434 }
2435
2436 /* Calculates the sum of vn_min_rates.
2437    It's needed for further normalizing of the min_rates.
2438    Returns:
2439      sum of vn_min_rates.
2440        or
2441      0 - if all the min_rates are 0.
2442      In the later case fairness algorithm should be deactivated.
2443      If not all min_rates are zero then those that are zeroes will be set to 1.
2444  */
2445 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2446                                       struct cmng_init_input *input)
2447 {
2448         int all_zero = 1;
2449         int vn;
2450
2451         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2452                 u32 vn_cfg = bp->mf_config[vn];
2453                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2454                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2455
2456                 /* Skip hidden vns */
2457                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2458                         vn_min_rate = 0;
2459                 /* If min rate is zero - set it to 1 */
2460                 else if (!vn_min_rate)
2461                         vn_min_rate = DEF_MIN_RATE;
2462                 else
2463                         all_zero = 0;
2464
2465                 input->vnic_min_rate[vn] = vn_min_rate;
2466         }
2467
2468         /* if ETS or all min rates are zeros - disable fairness */
2469         if (BNX2X_IS_ETS_ENABLED(bp)) {
2470                 input->flags.cmng_enables &=
2471                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2472                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2473         } else if (all_zero) {
2474                 input->flags.cmng_enables &=
2475                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2476                 DP(NETIF_MSG_IFUP,
2477                    "All MIN values are zeroes fairness will be disabled\n");
2478         } else
2479                 input->flags.cmng_enables |=
2480                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2481 }
2482
2483 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2484                                     struct cmng_init_input *input)
2485 {
2486         u16 vn_max_rate;
2487         u32 vn_cfg = bp->mf_config[vn];
2488
2489         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2490                 vn_max_rate = 0;
2491         else {
2492                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2493
2494                 if (IS_MF_SI(bp)) {
2495                         /* maxCfg in percents of linkspeed */
2496                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2497                 } else /* SD modes */
2498                         /* maxCfg is absolute in 100Mb units */
2499                         vn_max_rate = maxCfg * 100;
2500         }
2501
2502         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2503
2504         input->vnic_max_rate[vn] = vn_max_rate;
2505 }
2506
2507 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2508 {
2509         if (CHIP_REV_IS_SLOW(bp))
2510                 return CMNG_FNS_NONE;
2511         if (IS_MF(bp))
2512                 return CMNG_FNS_MINMAX;
2513
2514         return CMNG_FNS_NONE;
2515 }
2516
2517 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2518 {
2519         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2520
2521         if (BP_NOMCP(bp))
2522                 return; /* what should be the default value in this case */
2523
2524         /* For 2 port configuration the absolute function number formula
2525          * is:
2526          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2527          *
2528          *      and there are 4 functions per port
2529          *
2530          * For 4 port configuration it is
2531          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2532          *
2533          *      and there are 2 functions per port
2534          */
2535         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2536                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2537
2538                 if (func >= E1H_FUNC_MAX)
2539                         break;
2540
2541                 bp->mf_config[vn] =
2542                         MF_CFG_RD(bp, func_mf_config[func].config);
2543         }
2544         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2545                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2546                 bp->flags |= MF_FUNC_DIS;
2547         } else {
2548                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2549                 bp->flags &= ~MF_FUNC_DIS;
2550         }
2551 }
2552
2553 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2554 {
2555         struct cmng_init_input input;
2556         memset(&input, 0, sizeof(struct cmng_init_input));
2557
2558         input.port_rate = bp->link_vars.line_speed;
2559
2560         if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2561                 int vn;
2562
2563                 /* read mf conf from shmem */
2564                 if (read_cfg)
2565                         bnx2x_read_mf_cfg(bp);
2566
2567                 /* vn_weight_sum and enable fairness if not 0 */
2568                 bnx2x_calc_vn_min(bp, &input);
2569
2570                 /* calculate and set min-max rate for each vn */
2571                 if (bp->port.pmf)
2572                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2573                                 bnx2x_calc_vn_max(bp, vn, &input);
2574
2575                 /* always enable rate shaping and fairness */
2576                 input.flags.cmng_enables |=
2577                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2578
2579                 bnx2x_init_cmng(&input, &bp->cmng);
2580                 return;
2581         }
2582
2583         /* rate shaping and fairness are disabled */
2584         DP(NETIF_MSG_IFUP,
2585            "rate shaping and fairness are disabled\n");
2586 }
2587
2588 static void storm_memset_cmng(struct bnx2x *bp,
2589                               struct cmng_init *cmng,
2590                               u8 port)
2591 {
2592         int vn;
2593         size_t size = sizeof(struct cmng_struct_per_port);
2594
2595         u32 addr = BAR_XSTRORM_INTMEM +
2596                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2597
2598         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2599
2600         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2601                 int func = func_by_vn(bp, vn);
2602
2603                 addr = BAR_XSTRORM_INTMEM +
2604                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2605                 size = sizeof(struct rate_shaping_vars_per_vn);
2606                 __storm_memset_struct(bp, addr, size,
2607                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2608
2609                 addr = BAR_XSTRORM_INTMEM +
2610                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2611                 size = sizeof(struct fairness_vars_per_vn);
2612                 __storm_memset_struct(bp, addr, size,
2613                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2614         }
2615 }
2616
2617 /* init cmng mode in HW according to local configuration */
2618 void bnx2x_set_local_cmng(struct bnx2x *bp)
2619 {
2620         int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2621
2622         if (cmng_fns != CMNG_FNS_NONE) {
2623                 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2624                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2625         } else {
2626                 /* rate shaping and fairness are disabled */
2627                 DP(NETIF_MSG_IFUP,
2628                    "single function mode without fairness\n");
2629         }
2630 }
2631
2632 /* This function is called upon link interrupt */
2633 static void bnx2x_link_attn(struct bnx2x *bp)
2634 {
2635         /* Make sure that we are synced with the current statistics */
2636         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2637
2638         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2639
2640         bnx2x_init_dropless_fc(bp);
2641
2642         if (bp->link_vars.link_up) {
2643
2644                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2645                         struct host_port_stats *pstats;
2646
2647                         pstats = bnx2x_sp(bp, port_stats);
2648                         /* reset old mac stats */
2649                         memset(&(pstats->mac_stx[0]), 0,
2650                                sizeof(struct mac_stx));
2651                 }
2652                 if (bp->state == BNX2X_STATE_OPEN)
2653                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2654         }
2655
2656         if (bp->link_vars.link_up && bp->link_vars.line_speed)
2657                 bnx2x_set_local_cmng(bp);
2658
2659         __bnx2x_link_report(bp);
2660
2661         if (IS_MF(bp))
2662                 bnx2x_link_sync_notify(bp);
2663 }
2664
2665 void bnx2x__link_status_update(struct bnx2x *bp)
2666 {
2667         if (bp->state != BNX2X_STATE_OPEN)
2668                 return;
2669
2670         /* read updated dcb configuration */
2671         if (IS_PF(bp)) {
2672                 bnx2x_dcbx_pmf_update(bp);
2673                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2674                 if (bp->link_vars.link_up)
2675                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2676                 else
2677                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2678                         /* indicate link status */
2679                 bnx2x_link_report(bp);
2680
2681         } else { /* VF */
2682                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2683                                           SUPPORTED_10baseT_Full |
2684                                           SUPPORTED_100baseT_Half |
2685                                           SUPPORTED_100baseT_Full |
2686                                           SUPPORTED_1000baseT_Full |
2687                                           SUPPORTED_2500baseX_Full |
2688                                           SUPPORTED_10000baseT_Full |
2689                                           SUPPORTED_TP |
2690                                           SUPPORTED_FIBRE |
2691                                           SUPPORTED_Autoneg |
2692                                           SUPPORTED_Pause |
2693                                           SUPPORTED_Asym_Pause);
2694                 bp->port.advertising[0] = bp->port.supported[0];
2695
2696                 bp->link_params.bp = bp;
2697                 bp->link_params.port = BP_PORT(bp);
2698                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2699                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2700                 bp->link_params.req_line_speed[0] = SPEED_10000;
2701                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2702                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2703                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2704                 bp->link_vars.line_speed = SPEED_10000;
2705                 bp->link_vars.link_status =
2706                         (LINK_STATUS_LINK_UP |
2707                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2708                 bp->link_vars.link_up = 1;
2709                 bp->link_vars.duplex = DUPLEX_FULL;
2710                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2711                 __bnx2x_link_report(bp);
2712
2713                 bnx2x_sample_bulletin(bp);
2714
2715                 /* if bulletin board did not have an update for link status
2716                  * __bnx2x_link_report will report current status
2717                  * but it will NOT duplicate report in case of already reported
2718                  * during sampling bulletin board.
2719                  */
2720                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2721         }
2722 }
2723
2724 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2725                                   u16 vlan_val, u8 allowed_prio)
2726 {
2727         struct bnx2x_func_state_params func_params = {NULL};
2728         struct bnx2x_func_afex_update_params *f_update_params =
2729                 &func_params.params.afex_update;
2730
2731         func_params.f_obj = &bp->func_obj;
2732         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2733
2734         /* no need to wait for RAMROD completion, so don't
2735          * set RAMROD_COMP_WAIT flag
2736          */
2737
2738         f_update_params->vif_id = vifid;
2739         f_update_params->afex_default_vlan = vlan_val;
2740         f_update_params->allowed_priorities = allowed_prio;
2741
2742         /* if ramrod can not be sent, response to MCP immediately */
2743         if (bnx2x_func_state_change(bp, &func_params) < 0)
2744                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2745
2746         return 0;
2747 }
2748
2749 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2750                                           u16 vif_index, u8 func_bit_map)
2751 {
2752         struct bnx2x_func_state_params func_params = {NULL};
2753         struct bnx2x_func_afex_viflists_params *update_params =
2754                 &func_params.params.afex_viflists;
2755         int rc;
2756         u32 drv_msg_code;
2757
2758         /* validate only LIST_SET and LIST_GET are received from switch */
2759         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2760                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2761                           cmd_type);
2762
2763         func_params.f_obj = &bp->func_obj;
2764         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2765
2766         /* set parameters according to cmd_type */
2767         update_params->afex_vif_list_command = cmd_type;
2768         update_params->vif_list_index = vif_index;
2769         update_params->func_bit_map =
2770                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2771         update_params->func_to_clear = 0;
2772         drv_msg_code =
2773                 (cmd_type == VIF_LIST_RULE_GET) ?
2774                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2775                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2776
2777         /* if ramrod can not be sent, respond to MCP immediately for
2778          * SET and GET requests (other are not triggered from MCP)
2779          */
2780         rc = bnx2x_func_state_change(bp, &func_params);
2781         if (rc < 0)
2782                 bnx2x_fw_command(bp, drv_msg_code, 0);
2783
2784         return 0;
2785 }
2786
2787 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2788 {
2789         struct afex_stats afex_stats;
2790         u32 func = BP_ABS_FUNC(bp);
2791         u32 mf_config;
2792         u16 vlan_val;
2793         u32 vlan_prio;
2794         u16 vif_id;
2795         u8 allowed_prio;
2796         u8 vlan_mode;
2797         u32 addr_to_write, vifid, addrs, stats_type, i;
2798
2799         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2800                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2801                 DP(BNX2X_MSG_MCP,
2802                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2803                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2804         }
2805
2806         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2807                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2808                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2809                 DP(BNX2X_MSG_MCP,
2810                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2811                    vifid, addrs);
2812                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2813                                                addrs);
2814         }
2815
2816         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2817                 addr_to_write = SHMEM2_RD(bp,
2818                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2819                 stats_type = SHMEM2_RD(bp,
2820                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2821
2822                 DP(BNX2X_MSG_MCP,
2823                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2824                    addr_to_write);
2825
2826                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2827
2828                 /* write response to scratchpad, for MCP */
2829                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2830                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2831                                *(((u32 *)(&afex_stats))+i));
2832
2833                 /* send ack message to MCP */
2834                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2835         }
2836
2837         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2838                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2839                 bp->mf_config[BP_VN(bp)] = mf_config;
2840                 DP(BNX2X_MSG_MCP,
2841                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2842                    mf_config);
2843
2844                 /* if VIF_SET is "enabled" */
2845                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2846                         /* set rate limit directly to internal RAM */
2847                         struct cmng_init_input cmng_input;
2848                         struct rate_shaping_vars_per_vn m_rs_vn;
2849                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2850                         u32 addr = BAR_XSTRORM_INTMEM +
2851                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2852
2853                         bp->mf_config[BP_VN(bp)] = mf_config;
2854
2855                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2856                         m_rs_vn.vn_counter.rate =
2857                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2858                         m_rs_vn.vn_counter.quota =
2859                                 (m_rs_vn.vn_counter.rate *
2860                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2861
2862                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2863
2864                         /* read relevant values from mf_cfg struct in shmem */
2865                         vif_id =
2866                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2867                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2868                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2869                         vlan_val =
2870                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2871                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2872                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2873                         vlan_prio = (mf_config &
2874                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2875                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2876                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2877                         vlan_mode =
2878                                 (MF_CFG_RD(bp,
2879                                            func_mf_config[func].afex_config) &
2880                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2881                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2882                         allowed_prio =
2883                                 (MF_CFG_RD(bp,
2884                                            func_mf_config[func].afex_config) &
2885                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2886                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2887
2888                         /* send ramrod to FW, return in case of failure */
2889                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2890                                                    allowed_prio))
2891                                 return;
2892
2893                         bp->afex_def_vlan_tag = vlan_val;
2894                         bp->afex_vlan_mode = vlan_mode;
2895                 } else {
2896                         /* notify link down because BP->flags is disabled */
2897                         bnx2x_link_report(bp);
2898
2899                         /* send INVALID VIF ramrod to FW */
2900                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2901
2902                         /* Reset the default afex VLAN */
2903                         bp->afex_def_vlan_tag = -1;
2904                 }
2905         }
2906 }
2907
2908 static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
2909 {
2910         struct bnx2x_func_switch_update_params *switch_update_params;
2911         struct bnx2x_func_state_params func_params;
2912
2913         memset(&func_params, 0, sizeof(struct bnx2x_func_state_params));
2914         switch_update_params = &func_params.params.switch_update;
2915         func_params.f_obj = &bp->func_obj;
2916         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
2917
2918         if (IS_MF_UFP(bp)) {
2919                 int func = BP_ABS_FUNC(bp);
2920                 u32 val;
2921
2922                 /* Re-learn the S-tag from shmem */
2923                 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2924                                 FUNC_MF_CFG_E1HOV_TAG_MASK;
2925                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
2926                         bp->mf_ov = val;
2927                 } else {
2928                         BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2929                         goto fail;
2930                 }
2931
2932                 /* Configure new S-tag in LLH */
2933                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
2934                        bp->mf_ov);
2935
2936                 /* Send Ramrod to update FW of change */
2937                 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
2938                           &switch_update_params->changes);
2939                 switch_update_params->vlan = bp->mf_ov;
2940
2941                 if (bnx2x_func_state_change(bp, &func_params) < 0) {
2942                         BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2943                                   bp->mf_ov);
2944                         goto fail;
2945                 }
2946
2947                 DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n", bp->mf_ov);
2948
2949                 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
2950
2951                 return;
2952         }
2953
2954         /* not supported by SW yet */
2955 fail:
2956         bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);
2957 }
2958
2959 static void bnx2x_pmf_update(struct bnx2x *bp)
2960 {
2961         int port = BP_PORT(bp);
2962         u32 val;
2963
2964         bp->port.pmf = 1;
2965         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2966
2967         /*
2968          * We need the mb() to ensure the ordering between the writing to
2969          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2970          */
2971         smp_mb();
2972
2973         /* queue a periodic task */
2974         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2975
2976         bnx2x_dcbx_pmf_update(bp);
2977
2978         /* enable nig attention */
2979         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2980         if (bp->common.int_block == INT_BLOCK_HC) {
2981                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2982                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2983         } else if (!CHIP_IS_E1x(bp)) {
2984                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2985                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2986         }
2987
2988         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2989 }
2990
2991 /* end of Link */
2992
2993 /* slow path */
2994
2995 /*
2996  * General service functions
2997  */
2998
2999 /* send the MCP a request, block until there is a reply */
3000 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
3001 {
3002         int mb_idx = BP_FW_MB_IDX(bp);
3003         u32 seq;
3004         u32 rc = 0;
3005         u32 cnt = 1;
3006         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
3007
3008         mutex_lock(&bp->fw_mb_mutex);
3009         seq = ++bp->fw_seq;
3010         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
3011         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
3012
3013         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
3014                         (command | seq), param);
3015
3016         do {
3017                 /* let the FW do it's magic ... */
3018                 msleep(delay);
3019
3020                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
3021
3022                 /* Give the FW up to 5 second (500*10ms) */
3023         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
3024
3025         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3026            cnt*delay, rc, seq);
3027
3028         /* is this a reply to our command? */
3029         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
3030                 rc &= FW_MSG_CODE_MASK;
3031         else {
3032                 /* FW BUG! */
3033                 BNX2X_ERR("FW failed to respond!\n");
3034                 bnx2x_fw_dump(bp);
3035                 rc = 0;
3036         }
3037         mutex_unlock(&bp->fw_mb_mutex);
3038
3039         return rc;
3040 }
3041
3042 static void storm_memset_func_cfg(struct bnx2x *bp,
3043                                  struct tstorm_eth_function_common_config *tcfg,
3044                                  u16 abs_fid)
3045 {
3046         size_t size = sizeof(struct tstorm_eth_function_common_config);
3047
3048         u32 addr = BAR_TSTRORM_INTMEM +
3049                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
3050
3051         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3052 }
3053
3054 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3055 {
3056         if (CHIP_IS_E1x(bp)) {
3057                 struct tstorm_eth_function_common_config tcfg = {0};
3058
3059                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3060         }
3061
3062         /* Enable the function in the FW */
3063         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3064         storm_memset_func_en(bp, p->func_id, 1);
3065
3066         /* spq */
3067         if (p->func_flgs & FUNC_FLG_SPQ) {
3068                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3069                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3070                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3071         }
3072 }
3073
3074 /**
3075  * bnx2x_get_common_flags - Return common flags
3076  *
3077  * @bp          device handle
3078  * @fp          queue handle
3079  * @zero_stats  TRUE if statistics zeroing is needed
3080  *
3081  * Return the flags that are common for the Tx-only and not normal connections.
3082  */
3083 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3084                                             struct bnx2x_fastpath *fp,
3085                                             bool zero_stats)
3086 {
3087         unsigned long flags = 0;
3088
3089         /* PF driver will always initialize the Queue to an ACTIVE state */
3090         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
3091
3092         /* tx only connections collect statistics (on the same index as the
3093          * parent connection). The statistics are zeroed when the parent
3094          * connection is initialized.
3095          */
3096
3097         __set_bit(BNX2X_Q_FLG_STATS, &flags);
3098         if (zero_stats)
3099                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3100
3101         if (bp->flags & TX_SWITCHING)
3102                 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3103
3104         __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3105         __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3106
3107 #ifdef BNX2X_STOP_ON_ERROR
3108         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3109 #endif
3110
3111         return flags;
3112 }
3113
3114 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3115                                        struct bnx2x_fastpath *fp,
3116                                        bool leading)
3117 {
3118         unsigned long flags = 0;
3119
3120         /* calculate other queue flags */
3121         if (IS_MF_SD(bp))
3122                 __set_bit(BNX2X_Q_FLG_OV, &flags);
3123
3124         if (IS_FCOE_FP(fp)) {
3125                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3126                 /* For FCoE - force usage of default priority (for afex) */
3127                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3128         }
3129
3130         if (!fp->disable_tpa) {
3131                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3132                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3133                 if (fp->mode == TPA_MODE_GRO)
3134                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3135         }
3136
3137         if (leading) {
3138                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3139                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3140         }
3141
3142         /* Always set HW VLAN stripping */
3143         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3144
3145         /* configure silent vlan removal */
3146         if (IS_MF_AFEX(bp))
3147                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3148
3149         return flags | bnx2x_get_common_flags(bp, fp, true);
3150 }
3151
3152 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3153         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3154         u8 cos)
3155 {
3156         gen_init->stat_id = bnx2x_stats_id(fp);
3157         gen_init->spcl_id = fp->cl_id;
3158
3159         /* Always use mini-jumbo MTU for FCoE L2 ring */
3160         if (IS_FCOE_FP(fp))
3161                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3162         else
3163                 gen_init->mtu = bp->dev->mtu;
3164
3165         gen_init->cos = cos;
3166
3167         gen_init->fp_hsi = ETH_FP_HSI_VERSION;
3168 }
3169
3170 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3171         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3172         struct bnx2x_rxq_setup_params *rxq_init)
3173 {
3174         u8 max_sge = 0;
3175         u16 sge_sz = 0;
3176         u16 tpa_agg_size = 0;
3177
3178         if (!fp->disable_tpa) {
3179                 pause->sge_th_lo = SGE_TH_LO(bp);
3180                 pause->sge_th_hi = SGE_TH_HI(bp);
3181
3182                 /* validate SGE ring has enough to cross high threshold */
3183                 WARN_ON(bp->dropless_fc &&
3184                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3185                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3186
3187                 tpa_agg_size = TPA_AGG_SIZE;
3188                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3189                         SGE_PAGE_SHIFT;
3190                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3191                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3192                 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3193         }
3194
3195         /* pause - not for e1 */
3196         if (!CHIP_IS_E1(bp)) {
3197                 pause->bd_th_lo = BD_TH_LO(bp);
3198                 pause->bd_th_hi = BD_TH_HI(bp);
3199
3200                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3201                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3202                 /*
3203                  * validate that rings have enough entries to cross
3204                  * high thresholds
3205                  */
3206                 WARN_ON(bp->dropless_fc &&
3207                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3208                                 bp->rx_ring_size);
3209                 WARN_ON(bp->dropless_fc &&
3210                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3211                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3212
3213                 pause->pri_map = 1;
3214         }
3215
3216         /* rxq setup */
3217         rxq_init->dscr_map = fp->rx_desc_mapping;
3218         rxq_init->sge_map = fp->rx_sge_mapping;
3219         rxq_init->rcq_map = fp->rx_comp_mapping;
3220         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3221
3222         /* This should be a maximum number of data bytes that may be
3223          * placed on the BD (not including paddings).
3224          */
3225         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3226                            BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3227
3228         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3229         rxq_init->tpa_agg_sz = tpa_agg_size;
3230         rxq_init->sge_buf_sz = sge_sz;
3231         rxq_init->max_sges_pkt = max_sge;
3232         rxq_init->rss_engine_id = BP_FUNC(bp);
3233         rxq_init->mcast_engine_id = BP_FUNC(bp);
3234
3235         /* Maximum number or simultaneous TPA aggregation for this Queue.
3236          *
3237          * For PF Clients it should be the maximum available number.
3238          * VF driver(s) may want to define it to a smaller value.
3239          */
3240         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3241
3242         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3243         rxq_init->fw_sb_id = fp->fw_sb_id;
3244
3245         if (IS_FCOE_FP(fp))
3246                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3247         else
3248                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3249         /* configure silent vlan removal
3250          * if multi function mode is afex, then mask default vlan
3251          */
3252         if (IS_MF_AFEX(bp)) {
3253                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3254                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3255         }
3256 }
3257
3258 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3259         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3260         u8 cos)
3261 {
3262         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3263         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3264         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3265         txq_init->fw_sb_id = fp->fw_sb_id;
3266
3267         /*
3268          * set the tss leading client id for TX classification ==
3269          * leading RSS client id
3270          */
3271         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3272
3273         if (IS_FCOE_FP(fp)) {
3274                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3275                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3276         }
3277 }
3278
3279 static void bnx2x_pf_init(struct bnx2x *bp)
3280 {
3281         struct bnx2x_func_init_params func_init = {0};
3282         struct event_ring_data eq_data = { {0} };
3283         u16 flags;
3284
3285         if (!CHIP_IS_E1x(bp)) {
3286                 /* reset IGU PF statistics: MSIX + ATTN */
3287                 /* PF */
3288                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3289                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3290                            (CHIP_MODE_IS_4_PORT(bp) ?
3291                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3292                 /* ATTN */
3293                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3294                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3295                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3296                            (CHIP_MODE_IS_4_PORT(bp) ?
3297                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3298         }
3299
3300         /* function setup flags */
3301         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3302
3303         /* This flag is relevant for E1x only.
3304          * E2 doesn't have a TPA configuration in a function level.
3305          */
3306         flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
3307
3308         func_init.func_flgs = flags;
3309         func_init.pf_id = BP_FUNC(bp);
3310         func_init.func_id = BP_FUNC(bp);
3311         func_init.spq_map = bp->spq_mapping;
3312         func_init.spq_prod = bp->spq_prod_idx;
3313
3314         bnx2x_func_init(bp, &func_init);
3315
3316         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3317
3318         /*
3319          * Congestion management values depend on the link rate
3320          * There is no active link so initial link rate is set to 10 Gbps.
3321          * When the link comes up The congestion management values are
3322          * re-calculated according to the actual link rate.
3323          */
3324         bp->link_vars.line_speed = SPEED_10000;
3325         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3326
3327         /* Only the PMF sets the HW */
3328         if (bp->port.pmf)
3329                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3330
3331         /* init Event Queue - PCI bus guarantees correct endianity*/
3332         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3333         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3334         eq_data.producer = bp->eq_prod;
3335         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3336         eq_data.sb_id = DEF_SB_ID;
3337         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3338 }
3339
3340 static void bnx2x_e1h_disable(struct bnx2x *bp)
3341 {
3342         int port = BP_PORT(bp);
3343
3344         bnx2x_tx_disable(bp);
3345
3346         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3347 }
3348
3349 static void bnx2x_e1h_enable(struct bnx2x *bp)
3350 {
3351         int port = BP_PORT(bp);
3352
3353         if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
3354                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3355
3356         /* Tx queue should be only re-enabled */
3357         netif_tx_wake_all_queues(bp->dev);
3358
3359         /*
3360          * Should not call netif_carrier_on since it will be called if the link
3361          * is up when checking for link state
3362          */
3363 }
3364
3365 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3366
3367 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3368 {
3369         struct eth_stats_info *ether_stat =
3370                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3371         struct bnx2x_vlan_mac_obj *mac_obj =
3372                 &bp->sp_objs->mac_obj;
3373         int i;
3374
3375         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3376                 ETH_STAT_INFO_VERSION_LEN);
3377
3378         /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3379          * mac_local field in ether_stat struct. The base address is offset by 2
3380          * bytes to account for the field being 8 bytes but a mac address is
3381          * only 6 bytes. Likewise, the stride for the get_n_elements function is
3382          * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3383          * allocated by the ether_stat struct, so the macs will land in their
3384          * proper positions.
3385          */
3386         for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3387                 memset(ether_stat->mac_local + i, 0,
3388                        sizeof(ether_stat->mac_local[0]));
3389         mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3390                                 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3391                                 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3392                                 ETH_ALEN);
3393         ether_stat->mtu_size = bp->dev->mtu;
3394         if (bp->dev->features & NETIF_F_RXCSUM)
3395                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3396         if (bp->dev->features & NETIF_F_TSO)
3397                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3398         ether_stat->feature_flags |= bp->common.boot_mode;
3399
3400         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3401
3402         ether_stat->txq_size = bp->tx_ring_size;
3403         ether_stat->rxq_size = bp->rx_ring_size;
3404
3405 #ifdef CONFIG_BNX2X_SRIOV
3406         ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
3407 #endif
3408 }
3409
3410 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3411 {
3412         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3413         struct fcoe_stats_info *fcoe_stat =
3414                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3415
3416         if (!CNIC_LOADED(bp))
3417                 return;
3418
3419         memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3420
3421         fcoe_stat->qos_priority =
3422                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3423
3424         /* insert FCoE stats from ramrod response */
3425         if (!NO_FCOE(bp)) {
3426                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3427                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3428                         tstorm_queue_statistics;
3429
3430                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3431                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3432                         xstorm_queue_statistics;
3433
3434                 struct fcoe_statistics_params *fw_fcoe_stat =
3435                         &bp->fw_stats_data->fcoe;
3436
3437                 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3438                           fcoe_stat->rx_bytes_lo,
3439                           fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3440
3441                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3442                           fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3443                           fcoe_stat->rx_bytes_lo,
3444                           fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3445
3446                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3447                           fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3448                           fcoe_stat->rx_bytes_lo,
3449                           fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3450
3451                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3452                           fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3453                           fcoe_stat->rx_bytes_lo,
3454                           fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3455
3456                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3457                           fcoe_stat->rx_frames_lo,
3458                           fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3459
3460                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3461                           fcoe_stat->rx_frames_lo,
3462                           fcoe_q_tstorm_stats->rcv_ucast_pkts);
3463
3464                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3465                           fcoe_stat->rx_frames_lo,
3466                           fcoe_q_tstorm_stats->rcv_bcast_pkts);
3467
3468                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3469                           fcoe_stat->rx_frames_lo,
3470                           fcoe_q_tstorm_stats->rcv_mcast_pkts);
3471
3472                 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3473                           fcoe_stat->tx_bytes_lo,
3474                           fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3475
3476                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3477                           fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3478                           fcoe_stat->tx_bytes_lo,
3479                           fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3480
3481                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3482                           fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3483                           fcoe_stat->tx_bytes_lo,
3484                           fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3485
3486                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3487                           fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3488                           fcoe_stat->tx_bytes_lo,
3489                           fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3490
3491                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3492                           fcoe_stat->tx_frames_lo,
3493                           fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3494
3495                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3496                           fcoe_stat->tx_frames_lo,
3497                           fcoe_q_xstorm_stats->ucast_pkts_sent);
3498
3499                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3500                           fcoe_stat->tx_frames_lo,
3501                           fcoe_q_xstorm_stats->bcast_pkts_sent);
3502
3503                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3504                           fcoe_stat->tx_frames_lo,
3505                           fcoe_q_xstorm_stats->mcast_pkts_sent);
3506         }
3507
3508         /* ask L5 driver to add data to the struct */
3509         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3510 }
3511
3512 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3513 {
3514         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3515         struct iscsi_stats_info *iscsi_stat =
3516                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3517
3518         if (!CNIC_LOADED(bp))
3519                 return;
3520
3521         memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3522                ETH_ALEN);
3523
3524         iscsi_stat->qos_priority =
3525                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3526
3527         /* ask L5 driver to add data to the struct */
3528         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3529 }
3530
3531 /* called due to MCP event (on pmf):
3532  *      reread new bandwidth configuration
3533  *      configure FW
3534  *      notify others function about the change
3535  */
3536 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3537 {
3538         if (bp->link_vars.link_up) {
3539                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3540                 bnx2x_link_sync_notify(bp);
3541         }
3542         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3543 }
3544
3545 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3546 {
3547         bnx2x_config_mf_bw(bp);
3548         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3549 }
3550
3551 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3552 {
3553         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3554         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3555 }
3556
3557 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH        (20)
3558 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT         (25)
3559
3560 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3561 {
3562         enum drv_info_opcode op_code;
3563         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3564         bool release = false;
3565         int wait;
3566
3567         /* if drv_info version supported by MFW doesn't match - send NACK */
3568         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3569                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3570                 return;
3571         }
3572
3573         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3574                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3575
3576         /* Must prevent other flows from accessing drv_info_to_mcp */
3577         mutex_lock(&bp->drv_info_mutex);
3578
3579         memset(&bp->slowpath->drv_info_to_mcp, 0,
3580                sizeof(union drv_info_to_mcp));
3581
3582         switch (op_code) {
3583         case ETH_STATS_OPCODE:
3584                 bnx2x_drv_info_ether_stat(bp);
3585                 break;
3586         case FCOE_STATS_OPCODE:
3587                 bnx2x_drv_info_fcoe_stat(bp);
3588                 break;
3589         case ISCSI_STATS_OPCODE:
3590                 bnx2x_drv_info_iscsi_stat(bp);
3591                 break;
3592         default:
3593                 /* if op code isn't supported - send NACK */
3594                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3595                 goto out;
3596         }
3597
3598         /* if we got drv_info attn from MFW then these fields are defined in
3599          * shmem2 for sure
3600          */
3601         SHMEM2_WR(bp, drv_info_host_addr_lo,
3602                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3603         SHMEM2_WR(bp, drv_info_host_addr_hi,
3604                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3605
3606         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3607
3608         /* Since possible management wants both this and get_driver_version
3609          * need to wait until management notifies us it finished utilizing
3610          * the buffer.
3611          */
3612         if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3613                 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3614         } else if (!bp->drv_info_mng_owner) {
3615                 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3616
3617                 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3618                         u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3619
3620                         /* Management is done; need to clear indication */
3621                         if (indication & bit) {
3622                                 SHMEM2_WR(bp, mfw_drv_indication,
3623                                           indication & ~bit);
3624                                 release = true;
3625                                 break;
3626                         }
3627
3628                         msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3629                 }
3630         }
3631         if (!release) {
3632                 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3633                 bp->drv_info_mng_owner = true;
3634         }
3635
3636 out:
3637         mutex_unlock(&bp->drv_info_mutex);
3638 }
3639
3640 static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3641 {
3642         u8 vals[4];
3643         int i = 0;
3644
3645         if (bnx2x_format) {
3646                 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3647                            &vals[0], &vals[1], &vals[2], &vals[3]);
3648                 if (i > 0)
3649                         vals[0] -= '0';
3650         } else {
3651                 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3652                            &vals[0], &vals[1], &vals[2], &vals[3]);
3653         }
3654
3655         while (i < 4)
3656                 vals[i++] = 0;
3657
3658         return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3659 }
3660
3661 void bnx2x_update_mng_version(struct bnx2x *bp)
3662 {
3663         u32 iscsiver = DRV_VER_NOT_LOADED;
3664         u32 fcoever = DRV_VER_NOT_LOADED;
3665         u32 ethver = DRV_VER_NOT_LOADED;
3666         int idx = BP_FW_MB_IDX(bp);
3667         u8 *version;
3668
3669         if (!SHMEM2_HAS(bp, func_os_drv_ver))
3670                 return;
3671
3672         mutex_lock(&bp->drv_info_mutex);
3673         /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3674         if (bp->drv_info_mng_owner)
3675                 goto out;
3676
3677         if (bp->state != BNX2X_STATE_OPEN)
3678                 goto out;
3679
3680         /* Parse ethernet driver version */
3681         ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3682         if (!CNIC_LOADED(bp))
3683                 goto out;
3684
3685         /* Try getting storage driver version via cnic */
3686         memset(&bp->slowpath->drv_info_to_mcp, 0,
3687                sizeof(union drv_info_to_mcp));
3688         bnx2x_drv_info_iscsi_stat(bp);
3689         version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3690         iscsiver = bnx2x_update_mng_version_utility(version, false);
3691
3692         memset(&bp->slowpath->drv_info_to_mcp, 0,
3693                sizeof(union drv_info_to_mcp));
3694         bnx2x_drv_info_fcoe_stat(bp);
3695         version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3696         fcoever = bnx2x_update_mng_version_utility(version, false);
3697
3698 out:
3699         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3700         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3701         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3702
3703         mutex_unlock(&bp->drv_info_mutex);
3704
3705         DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3706            ethver, iscsiver, fcoever);
3707 }
3708
3709 static void bnx2x_oem_event(struct bnx2x *bp, u32 event)
3710 {
3711         u32 cmd_ok, cmd_fail;
3712
3713         /* sanity */
3714         if (event & DRV_STATUS_DCC_EVENT_MASK &&
3715             event & DRV_STATUS_OEM_EVENT_MASK) {
3716                 BNX2X_ERR("Received simultaneous events %08x\n", event);
3717                 return;
3718         }
3719
3720         if (event & DRV_STATUS_DCC_EVENT_MASK) {
3721                 cmd_fail = DRV_MSG_CODE_DCC_FAILURE;
3722                 cmd_ok = DRV_MSG_CODE_DCC_OK;
3723         } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3724                 cmd_fail = DRV_MSG_CODE_OEM_FAILURE;
3725                 cmd_ok = DRV_MSG_CODE_OEM_OK;
3726         }
3727
3728         DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event);
3729
3730         if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3731                      DRV_STATUS_OEM_DISABLE_ENABLE_PF)) {
3732                 /* This is the only place besides the function initialization
3733                  * where the bp->flags can change so it is done without any
3734                  * locks
3735                  */
3736                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3737                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3738                         bp->flags |= MF_FUNC_DIS;
3739
3740                         bnx2x_e1h_disable(bp);
3741                 } else {
3742                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3743                         bp->flags &= ~MF_FUNC_DIS;
3744
3745                         bnx2x_e1h_enable(bp);
3746                 }
3747                 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3748                            DRV_STATUS_OEM_DISABLE_ENABLE_PF);
3749         }
3750
3751         if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3752                      DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) {
3753                 bnx2x_config_mf_bw(bp);
3754                 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3755                            DRV_STATUS_OEM_BANDWIDTH_ALLOCATION);
3756         }
3757
3758         /* Report results to MCP */
3759         if (event)
3760                 bnx2x_fw_command(bp, cmd_fail, 0);
3761         else
3762                 bnx2x_fw_command(bp, cmd_ok, 0);
3763 }
3764
3765 /* must be called under the spq lock */
3766 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3767 {
3768         struct eth_spe *next_spe = bp->spq_prod_bd;
3769
3770         if (bp->spq_prod_bd == bp->spq_last_bd) {
3771                 bp->spq_prod_bd = bp->spq;
3772                 bp->spq_prod_idx = 0;
3773                 DP(BNX2X_MSG_SP, "end of spq\n");
3774         } else {
3775                 bp->spq_prod_bd++;
3776                 bp->spq_prod_idx++;
3777         }
3778         return next_spe;
3779 }
3780
3781 /* must be called under the spq lock */
3782 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3783 {
3784         int func = BP_FUNC(bp);
3785
3786         /*
3787          * Make sure that BD data is updated before writing the producer:
3788          * BD data is written to the memory, the producer is read from the
3789          * memory, thus we need a full memory barrier to ensure the ordering.
3790          */
3791         mb();
3792
3793         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3794                  bp->spq_prod_idx);
3795         mmiowb();
3796 }
3797
3798 /**
3799  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3800  *
3801  * @cmd:        command to check
3802  * @cmd_type:   command type
3803  */
3804 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3805 {
3806         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3807             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3808             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3809             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3810             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3811             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3812             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3813                 return true;
3814         else
3815                 return false;
3816 }
3817
3818 /**
3819  * bnx2x_sp_post - place a single command on an SP ring
3820  *
3821  * @bp:         driver handle
3822  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3823  * @cid:        SW CID the command is related to
3824  * @data_hi:    command private data address (high 32 bits)
3825  * @data_lo:    command private data address (low 32 bits)
3826  * @cmd_type:   command type (e.g. NONE, ETH)
3827  *
3828  * SP data is handled as if it's always an address pair, thus data fields are
3829  * not swapped to little endian in upper functions. Instead this function swaps
3830  * data as if it's two u32 fields.
3831  */
3832 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3833                   u32 data_hi, u32 data_lo, int cmd_type)
3834 {
3835         struct eth_spe *spe;
3836         u16 type;
3837         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3838
3839 #ifdef BNX2X_STOP_ON_ERROR
3840         if (unlikely(bp->panic)) {
3841                 BNX2X_ERR("Can't post SP when there is panic\n");
3842                 return -EIO;
3843         }
3844 #endif
3845
3846         spin_lock_bh(&bp->spq_lock);
3847
3848         if (common) {
3849                 if (!atomic_read(&bp->eq_spq_left)) {
3850                         BNX2X_ERR("BUG! EQ ring full!\n");
3851                         spin_unlock_bh(&bp->spq_lock);
3852                         bnx2x_panic();
3853                         return -EBUSY;
3854                 }
3855         } else if (!atomic_read(&bp->cq_spq_left)) {
3856                         BNX2X_ERR("BUG! SPQ ring full!\n");
3857                         spin_unlock_bh(&bp->spq_lock);
3858                         bnx2x_panic();
3859                         return -EBUSY;
3860         }
3861
3862         spe = bnx2x_sp_get_next(bp);
3863
3864         /* CID needs port number to be encoded int it */
3865         spe->hdr.conn_and_cmd_data =
3866                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3867                                     HW_CID(bp, cid));
3868
3869         /* In some cases, type may already contain the func-id
3870          * mainly in SRIOV related use cases, so we add it here only
3871          * if it's not already set.
3872          */
3873         if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3874                 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3875                         SPE_HDR_CONN_TYPE;
3876                 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3877                          SPE_HDR_FUNCTION_ID);
3878         } else {
3879                 type = cmd_type;
3880         }
3881
3882         spe->hdr.type = cpu_to_le16(type);
3883
3884         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3885         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3886
3887         /*
3888          * It's ok if the actual decrement is issued towards the memory
3889          * somewhere between the spin_lock and spin_unlock. Thus no
3890          * more explicit memory barrier is needed.
3891          */
3892         if (common)
3893                 atomic_dec(&bp->eq_spq_left);
3894         else
3895                 atomic_dec(&bp->cq_spq_left);
3896
3897         DP(BNX2X_MSG_SP,
3898            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3899            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3900            (u32)(U64_LO(bp->spq_mapping) +
3901            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3902            HW_CID(bp, cid), data_hi, data_lo, type,
3903            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3904
3905         bnx2x_sp_prod_update(bp);
3906         spin_unlock_bh(&bp->spq_lock);
3907         return 0;
3908 }
3909
3910 /* acquire split MCP access lock register */
3911 static int bnx2x_acquire_alr(struct bnx2x *bp)
3912 {
3913         u32 j, val;
3914         int rc = 0;
3915
3916         might_sleep();
3917         for (j = 0; j < 1000; j++) {
3918                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3919                 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3920                 if (val & MCPR_ACCESS_LOCK_LOCK)
3921                         break;
3922
3923                 usleep_range(5000, 10000);
3924         }
3925         if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3926                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3927                 rc = -EBUSY;
3928         }
3929
3930         return rc;
3931 }
3932
3933 /* release split MCP access lock register */
3934 static void bnx2x_release_alr(struct bnx2x *bp)
3935 {
3936         REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3937 }
3938
3939 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3940 #define BNX2X_DEF_SB_IDX        0x0002
3941
3942 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3943 {
3944         struct host_sp_status_block *def_sb = bp->def_status_blk;
3945         u16 rc = 0;
3946
3947         barrier(); /* status block is written to by the chip */
3948         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3949                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3950                 rc |= BNX2X_DEF_SB_ATT_IDX;
3951         }
3952
3953         if (bp->def_idx != def_sb->sp_sb.running_index) {
3954                 bp->def_idx = def_sb->sp_sb.running_index;
3955                 rc |= BNX2X_DEF_SB_IDX;
3956         }
3957
3958         /* Do not reorder: indices reading should complete before handling */
3959         barrier();
3960         return rc;
3961 }
3962
3963 /*
3964  * slow path service functions
3965  */
3966
3967 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3968 {
3969         int port = BP_PORT(bp);
3970         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3971                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3972         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3973                                        NIG_REG_MASK_INTERRUPT_PORT0;
3974         u32 aeu_mask;
3975         u32 nig_mask = 0;
3976         u32 reg_addr;
3977
3978         if (bp->attn_state & asserted)
3979                 BNX2X_ERR("IGU ERROR\n");
3980
3981         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3982         aeu_mask = REG_RD(bp, aeu_addr);
3983
3984         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
3985            aeu_mask, asserted);
3986         aeu_mask &= ~(asserted & 0x3ff);
3987         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3988
3989         REG_WR(bp, aeu_addr, aeu_mask);
3990         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3991
3992         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3993         bp->attn_state |= asserted;
3994         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3995
3996         if (asserted & ATTN_HARD_WIRED_MASK) {
3997                 if (asserted & ATTN_NIG_FOR_FUNC) {
3998
3999                         bnx2x_acquire_phy_lock(bp);
4000
4001                         /* save nig interrupt mask */
4002                         nig_mask = REG_RD(bp, nig_int_mask_addr);
4003
4004                         /* If nig_mask is not set, no need to call the update
4005                          * function.
4006                          */
4007                         if (nig_mask) {
4008                                 REG_WR(bp, nig_int_mask_addr, 0);
4009
4010                                 bnx2x_link_attn(bp);
4011                         }
4012
4013                         /* handle unicore attn? */
4014                 }
4015                 if (asserted & ATTN_SW_TIMER_4_FUNC)
4016                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
4017
4018                 if (asserted & GPIO_2_FUNC)
4019                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
4020
4021                 if (asserted & GPIO_3_FUNC)
4022                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
4023
4024                 if (asserted & GPIO_4_FUNC)
4025                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
4026
4027                 if (port == 0) {
4028                         if (asserted & ATTN_GENERAL_ATTN_1) {
4029                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
4030                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
4031                         }
4032                         if (asserted & ATTN_GENERAL_ATTN_2) {
4033                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
4034                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
4035                         }
4036                         if (asserted & ATTN_GENERAL_ATTN_3) {
4037                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
4038                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
4039                         }
4040                 } else {
4041                         if (asserted & ATTN_GENERAL_ATTN_4) {
4042                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
4043                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
4044                         }
4045                         if (asserted & ATTN_GENERAL_ATTN_5) {
4046                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
4047                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
4048                         }
4049                         if (asserted & ATTN_GENERAL_ATTN_6) {
4050                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
4051                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
4052                         }
4053                 }
4054
4055         } /* if hardwired */
4056
4057         if (bp->common.int_block == INT_BLOCK_HC)
4058                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4059                             COMMAND_REG_ATTN_BITS_SET);
4060         else
4061                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
4062
4063         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
4064            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4065         REG_WR(bp, reg_addr, asserted);
4066
4067         /* now set back the mask */
4068         if (asserted & ATTN_NIG_FOR_FUNC) {
4069                 /* Verify that IGU ack through BAR was written before restoring
4070                  * NIG mask. This loop should exit after 2-3 iterations max.
4071                  */
4072                 if (bp->common.int_block != INT_BLOCK_HC) {
4073                         u32 cnt = 0, igu_acked;
4074                         do {
4075                                 igu_acked = REG_RD(bp,
4076                                                    IGU_REG_ATTENTION_ACK_BITS);
4077                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4078                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
4079                         if (!igu_acked)
4080                                 DP(NETIF_MSG_HW,
4081                                    "Failed to verify IGU ack on time\n");
4082                         barrier();
4083                 }
4084                 REG_WR(bp, nig_int_mask_addr, nig_mask);
4085                 bnx2x_release_phy_lock(bp);
4086         }
4087 }
4088
4089 static void bnx2x_fan_failure(struct bnx2x *bp)
4090 {
4091         int port = BP_PORT(bp);
4092         u32 ext_phy_config;
4093         /* mark the failure */
4094         ext_phy_config =
4095                 SHMEM_RD(bp,
4096                          dev_info.port_hw_config[port].external_phy_config);
4097
4098         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4099         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4100         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
4101                  ext_phy_config);
4102
4103         /* log the failure */
4104         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4105                             "Please contact OEM Support for assistance\n");
4106
4107         /* Schedule device reset (unload)
4108          * This is due to some boards consuming sufficient power when driver is
4109          * up to overheat if fan fails.
4110          */
4111         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
4112 }
4113
4114 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4115 {
4116         int port = BP_PORT(bp);
4117         int reg_offset;
4118         u32 val;
4119
4120         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4121                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4122
4123         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4124
4125                 val = REG_RD(bp, reg_offset);
4126                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4127                 REG_WR(bp, reg_offset, val);
4128
4129                 BNX2X_ERR("SPIO5 hw attention\n");
4130
4131                 /* Fan failure attention */
4132                 bnx2x_hw_reset_phy(&bp->link_params);
4133                 bnx2x_fan_failure(bp);
4134         }
4135
4136         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
4137                 bnx2x_acquire_phy_lock(bp);
4138                 bnx2x_handle_module_detect_int(&bp->link_params);
4139                 bnx2x_release_phy_lock(bp);
4140         }
4141
4142         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4143
4144                 val = REG_RD(bp, reg_offset);
4145                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4146                 REG_WR(bp, reg_offset, val);
4147
4148                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4149                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
4150                 bnx2x_panic();
4151         }
4152 }
4153
4154 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
4155 {
4156         u32 val;
4157
4158         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4159
4160                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4161                 BNX2X_ERR("DB hw attention 0x%x\n", val);
4162                 /* DORQ discard attention */
4163                 if (val & 0x2)
4164                         BNX2X_ERR("FATAL error from DORQ\n");
4165         }
4166
4167         if (attn & HW_INTERRUT_ASSERT_SET_1) {
4168
4169                 int port = BP_PORT(bp);
4170                 int reg_offset;
4171
4172                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4173                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4174
4175                 val = REG_RD(bp, reg_offset);
4176                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4177                 REG_WR(bp, reg_offset, val);
4178
4179                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4180                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
4181                 bnx2x_panic();
4182         }
4183 }
4184
4185 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
4186 {
4187         u32 val;
4188
4189         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4190
4191                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4192                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4193                 /* CFC error attention */
4194                 if (val & 0x2)
4195                         BNX2X_ERR("FATAL error from CFC\n");
4196         }
4197
4198         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
4199                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
4200                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
4201                 /* RQ_USDMDP_FIFO_OVERFLOW */
4202                 if (val & 0x18000)
4203                         BNX2X_ERR("FATAL error from PXP\n");
4204
4205                 if (!CHIP_IS_E1x(bp)) {
4206                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4207                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4208                 }
4209         }
4210
4211         if (attn & HW_INTERRUT_ASSERT_SET_2) {
4212
4213                 int port = BP_PORT(bp);
4214                 int reg_offset;
4215
4216                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4217                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4218
4219                 val = REG_RD(bp, reg_offset);
4220                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4221                 REG_WR(bp, reg_offset, val);
4222
4223                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4224                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
4225                 bnx2x_panic();
4226         }
4227 }
4228
4229 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
4230 {
4231         u32 val;
4232
4233         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4234
4235                 if (attn & BNX2X_PMF_LINK_ASSERT) {
4236                         int func = BP_FUNC(bp);
4237
4238                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
4239                         bnx2x_read_mf_cfg(bp);
4240                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4241                                         func_mf_config[BP_ABS_FUNC(bp)].config);
4242                         val = SHMEM_RD(bp,
4243                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
4244
4245                         if (val & (DRV_STATUS_DCC_EVENT_MASK |
4246                                    DRV_STATUS_OEM_EVENT_MASK))
4247                                 bnx2x_oem_event(bp,
4248                                         (val & (DRV_STATUS_DCC_EVENT_MASK |
4249                                                 DRV_STATUS_OEM_EVENT_MASK)));
4250
4251                         if (val & DRV_STATUS_SET_MF_BW)
4252                                 bnx2x_set_mf_bw(bp);
4253
4254                         if (val & DRV_STATUS_DRV_INFO_REQ)
4255                                 bnx2x_handle_drv_info_req(bp);
4256
4257                         if (val & DRV_STATUS_VF_DISABLED)
4258                                 bnx2x_schedule_iov_task(bp,
4259                                                         BNX2X_IOV_HANDLE_FLR);
4260
4261                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4262                                 bnx2x_pmf_update(bp);
4263
4264                         if (bp->port.pmf &&
4265                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4266                                 bp->dcbx_enabled > 0)
4267                                 /* start dcbx state machine */
4268                                 bnx2x_dcbx_set_params(bp,
4269                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
4270                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
4271                                 bnx2x_handle_afex_cmd(bp,
4272                                         val & DRV_STATUS_AFEX_EVENT_MASK);
4273                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4274                                 bnx2x_handle_eee_event(bp);
4275
4276                         if (val & DRV_STATUS_OEM_UPDATE_SVID)
4277                                 bnx2x_handle_update_svid_cmd(bp);
4278
4279                         if (bp->link_vars.periodic_flags &
4280                             PERIODIC_FLAGS_LINK_EVENT) {
4281                                 /*  sync with link */
4282                                 bnx2x_acquire_phy_lock(bp);
4283                                 bp->link_vars.periodic_flags &=
4284                                         ~PERIODIC_FLAGS_LINK_EVENT;
4285                                 bnx2x_release_phy_lock(bp);
4286                                 if (IS_MF(bp))
4287                                         bnx2x_link_sync_notify(bp);
4288                                 bnx2x_link_report(bp);
4289                         }
4290                         /* Always call it here: bnx2x_link_report() will
4291                          * prevent the link indication duplication.
4292                          */
4293                         bnx2x__link_status_update(bp);
4294                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4295
4296                         BNX2X_ERR("MC assert!\n");
4297                         bnx2x_mc_assert(bp);
4298                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4299                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4300                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4301                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4302                         bnx2x_panic();
4303
4304                 } else if (attn & BNX2X_MCP_ASSERT) {
4305
4306                         BNX2X_ERR("MCP assert!\n");
4307                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4308                         bnx2x_fw_dump(bp);
4309
4310                 } else
4311                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4312         }
4313
4314         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4315                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4316                 if (attn & BNX2X_GRC_TIMEOUT) {
4317                         val = CHIP_IS_E1(bp) ? 0 :
4318                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4319                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4320                 }
4321                 if (attn & BNX2X_GRC_RSV) {
4322                         val = CHIP_IS_E1(bp) ? 0 :
4323                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4324                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4325                 }
4326                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4327         }
4328 }
4329
4330 /*
4331  * Bits map:
4332  * 0-7   - Engine0 load counter.
4333  * 8-15  - Engine1 load counter.
4334  * 16    - Engine0 RESET_IN_PROGRESS bit.
4335  * 17    - Engine1 RESET_IN_PROGRESS bit.
4336  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4337  *         on the engine
4338  * 19    - Engine1 ONE_IS_LOADED.
4339  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4340  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4341  *         just the one belonging to its engine).
4342  *
4343  */
4344 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4345
4346 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4347 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4348 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4349 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4350 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4351 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4352 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4353
4354 /*
4355  * Set the GLOBAL_RESET bit.
4356  *
4357  * Should be run under rtnl lock
4358  */
4359 void bnx2x_set_reset_global(struct bnx2x *bp)
4360 {
4361         u32 val;
4362         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4363         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4364         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4365         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4366 }
4367
4368 /*
4369  * Clear the GLOBAL_RESET bit.
4370  *
4371  * Should be run under rtnl lock
4372  */
4373 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4374 {
4375         u32 val;
4376         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4377         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4378         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4379         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4380 }
4381
4382 /*
4383  * Checks the GLOBAL_RESET bit.
4384  *
4385  * should be run under rtnl lock
4386  */
4387 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4388 {
4389         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4390
4391         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4392         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4393 }
4394
4395 /*
4396  * Clear RESET_IN_PROGRESS bit for the current engine.
4397  *
4398  * Should be run under rtnl lock
4399  */
4400 static void bnx2x_set_reset_done(struct bnx2x *bp)
4401 {
4402         u32 val;
4403         u32 bit = BP_PATH(bp) ?
4404                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4405         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4406         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4407
4408         /* Clear the bit */
4409         val &= ~bit;
4410         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4411
4412         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4413 }
4414
4415 /*
4416  * Set RESET_IN_PROGRESS for the current engine.
4417  *
4418  * should be run under rtnl lock
4419  */
4420 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4421 {
4422         u32 val;
4423         u32 bit = BP_PATH(bp) ?
4424                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4425         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4426         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4427
4428         /* Set the bit */
4429         val |= bit;
4430         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4431         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4432 }
4433
4434 /*
4435  * Checks the RESET_IN_PROGRESS bit for the given engine.
4436  * should be run under rtnl lock
4437  */
4438 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4439 {
4440         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4441         u32 bit = engine ?
4442                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4443
4444         /* return false if bit is set */
4445         return (val & bit) ? false : true;
4446 }
4447
4448 /*
4449  * set pf load for the current pf.
4450  *
4451  * should be run under rtnl lock
4452  */
4453 void bnx2x_set_pf_load(struct bnx2x *bp)
4454 {
4455         u32 val1, val;
4456         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4457                              BNX2X_PATH0_LOAD_CNT_MASK;
4458         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4459                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4460
4461         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4462         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4463
4464         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4465
4466         /* get the current counter value */
4467         val1 = (val & mask) >> shift;
4468
4469         /* set bit of that PF */
4470         val1 |= (1 << bp->pf_num);
4471
4472         /* clear the old value */
4473         val &= ~mask;
4474
4475         /* set the new one */
4476         val |= ((val1 << shift) & mask);
4477
4478         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4479         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4480 }
4481
4482 /**
4483  * bnx2x_clear_pf_load - clear pf load mark
4484  *
4485  * @bp:         driver handle
4486  *
4487  * Should be run under rtnl lock.
4488  * Decrements the load counter for the current engine. Returns
4489  * whether other functions are still loaded
4490  */
4491 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4492 {
4493         u32 val1, val;
4494         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4495                              BNX2X_PATH0_LOAD_CNT_MASK;
4496         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4497                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4498
4499         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4500         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4501         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4502
4503         /* get the current counter value */
4504         val1 = (val & mask) >> shift;
4505
4506         /* clear bit of that PF */
4507         val1 &= ~(1 << bp->pf_num);
4508
4509         /* clear the old value */
4510         val &= ~mask;
4511
4512         /* set the new one */
4513         val |= ((val1 << shift) & mask);
4514
4515         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4516         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4517         return val1 != 0;
4518 }
4519
4520 /*
4521  * Read the load status for the current engine.
4522  *
4523  * should be run under rtnl lock
4524  */
4525 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4526 {
4527         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4528                              BNX2X_PATH0_LOAD_CNT_MASK);
4529         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4530                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4531         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4532
4533         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4534
4535         val = (val & mask) >> shift;
4536
4537         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4538            engine, val);
4539
4540         return val != 0;
4541 }
4542
4543 static void _print_parity(struct bnx2x *bp, u32 reg)
4544 {
4545         pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4546 }
4547
4548 static void _print_next_block(int idx, const char *blk)
4549 {
4550         pr_cont("%s%s", idx ? ", " : "", blk);
4551 }
4552
4553 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4554                                             int *par_num, bool print)
4555 {
4556         u32 cur_bit;
4557         bool res;
4558         int i;
4559
4560         res = false;
4561
4562         for (i = 0; sig; i++) {
4563                 cur_bit = (0x1UL << i);
4564                 if (sig & cur_bit) {
4565                         res |= true; /* Each bit is real error! */
4566
4567                         if (print) {
4568                                 switch (cur_bit) {
4569                                 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4570                                         _print_next_block((*par_num)++, "BRB");
4571                                         _print_parity(bp,
4572                                                       BRB1_REG_BRB1_PRTY_STS);
4573                                         break;
4574                                 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4575                                         _print_next_block((*par_num)++,
4576                                                           "PARSER");
4577                                         _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4578                                         break;
4579                                 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4580                                         _print_next_block((*par_num)++, "TSDM");
4581                                         _print_parity(bp,
4582                                                       TSDM_REG_TSDM_PRTY_STS);
4583                                         break;
4584                                 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4585                                         _print_next_block((*par_num)++,
4586                                                           "SEARCHER");
4587                                         _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4588                                         break;
4589                                 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4590                                         _print_next_block((*par_num)++, "TCM");
4591                                         _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4592                                         break;
4593                                 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4594                                         _print_next_block((*par_num)++,
4595                                                           "TSEMI");
4596                                         _print_parity(bp,
4597                                                       TSEM_REG_TSEM_PRTY_STS_0);
4598                                         _print_parity(bp,
4599                                                       TSEM_REG_TSEM_PRTY_STS_1);
4600                                         break;
4601                                 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4602                                         _print_next_block((*par_num)++, "XPB");
4603                                         _print_parity(bp, GRCBASE_XPB +
4604                                                           PB_REG_PB_PRTY_STS);
4605                                         break;
4606                                 }
4607                         }
4608
4609                         /* Clear the bit */
4610                         sig &= ~cur_bit;
4611                 }
4612         }
4613
4614         return res;
4615 }
4616
4617 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4618                                             int *par_num, bool *global,
4619                                             bool print)
4620 {
4621         u32 cur_bit;
4622         bool res;
4623         int i;
4624
4625         res = false;
4626
4627         for (i = 0; sig; i++) {
4628                 cur_bit = (0x1UL << i);
4629                 if (sig & cur_bit) {
4630                         res |= true; /* Each bit is real error! */
4631                         switch (cur_bit) {
4632                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4633                                 if (print) {
4634                                         _print_next_block((*par_num)++, "PBF");
4635                                         _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4636                                 }
4637                                 break;
4638                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4639                                 if (print) {
4640                                         _print_next_block((*par_num)++, "QM");
4641                                         _print_parity(bp, QM_REG_QM_PRTY_STS);
4642                                 }
4643                                 break;
4644                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4645                                 if (print) {
4646                                         _print_next_block((*par_num)++, "TM");
4647                                         _print_parity(bp, TM_REG_TM_PRTY_STS);
4648                                 }
4649                                 break;
4650                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4651                                 if (print) {
4652                                         _print_next_block((*par_num)++, "XSDM");
4653                                         _print_parity(bp,
4654                                                       XSDM_REG_XSDM_PRTY_STS);
4655                                 }
4656                                 break;
4657                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4658                                 if (print) {
4659                                         _print_next_block((*par_num)++, "XCM");
4660                                         _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4661                                 }
4662                                 break;
4663                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4664                                 if (print) {
4665                                         _print_next_block((*par_num)++,
4666                                                           "XSEMI");
4667                                         _print_parity(bp,
4668                                                       XSEM_REG_XSEM_PRTY_STS_0);
4669                                         _print_parity(bp,
4670                                                       XSEM_REG_XSEM_PRTY_STS_1);
4671                                 }
4672                                 break;
4673                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4674                                 if (print) {
4675                                         _print_next_block((*par_num)++,
4676                                                           "DOORBELLQ");
4677                                         _print_parity(bp,
4678                                                       DORQ_REG_DORQ_PRTY_STS);
4679                                 }
4680                                 break;
4681                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4682                                 if (print) {
4683                                         _print_next_block((*par_num)++, "NIG");
4684                                         if (CHIP_IS_E1x(bp)) {
4685                                                 _print_parity(bp,
4686                                                         NIG_REG_NIG_PRTY_STS);
4687                                         } else {
4688                                                 _print_parity(bp,
4689                                                         NIG_REG_NIG_PRTY_STS_0);
4690                                                 _print_parity(bp,
4691                                                         NIG_REG_NIG_PRTY_STS_1);
4692                                         }
4693                                 }
4694                                 break;
4695                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4696                                 if (print)
4697                                         _print_next_block((*par_num)++,
4698                                                           "VAUX PCI CORE");
4699                                 *global = true;
4700                                 break;
4701                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4702                                 if (print) {
4703                                         _print_next_block((*par_num)++,
4704                                                           "DEBUG");
4705                                         _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4706                                 }
4707                                 break;
4708                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4709                                 if (print) {
4710                                         _print_next_block((*par_num)++, "USDM");
4711                                         _print_parity(bp,
4712                                                       USDM_REG_USDM_PRTY_STS);
4713                                 }
4714                                 break;
4715                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4716                                 if (print) {
4717                                         _print_next_block((*par_num)++, "UCM");
4718                                         _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4719                                 }
4720                                 break;
4721                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4722                                 if (print) {
4723                                         _print_next_block((*par_num)++,
4724                                                           "USEMI");
4725                                         _print_parity(bp,
4726                                                       USEM_REG_USEM_PRTY_STS_0);
4727                                         _print_parity(bp,
4728                                                       USEM_REG_USEM_PRTY_STS_1);
4729                                 }
4730                                 break;
4731                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4732                                 if (print) {
4733                                         _print_next_block((*par_num)++, "UPB");
4734                                         _print_parity(bp, GRCBASE_UPB +
4735                                                           PB_REG_PB_PRTY_STS);
4736                                 }
4737                                 break;
4738                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4739                                 if (print) {
4740                                         _print_next_block((*par_num)++, "CSDM");
4741                                         _print_parity(bp,
4742                                                       CSDM_REG_CSDM_PRTY_STS);
4743                                 }
4744                                 break;
4745                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4746                                 if (print) {
4747                                         _print_next_block((*par_num)++, "CCM");
4748                                         _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4749                                 }
4750                                 break;
4751                         }
4752
4753                         /* Clear the bit */
4754                         sig &= ~cur_bit;
4755                 }
4756         }
4757
4758         return res;
4759 }
4760
4761 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4762                                             int *par_num, bool print)
4763 {
4764         u32 cur_bit;
4765         bool res;
4766         int i;
4767
4768         res = false;
4769
4770         for (i = 0; sig; i++) {
4771                 cur_bit = (0x1UL << i);
4772                 if (sig & cur_bit) {
4773                         res = true; /* Each bit is real error! */
4774                         if (print) {
4775                                 switch (cur_bit) {
4776                                 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4777                                         _print_next_block((*par_num)++,
4778                                                           "CSEMI");
4779                                         _print_parity(bp,
4780                                                       CSEM_REG_CSEM_PRTY_STS_0);
4781                                         _print_parity(bp,
4782                                                       CSEM_REG_CSEM_PRTY_STS_1);
4783                                         break;
4784                                 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4785                                         _print_next_block((*par_num)++, "PXP");
4786                                         _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4787                                         _print_parity(bp,
4788                                                       PXP2_REG_PXP2_PRTY_STS_0);
4789                                         _print_parity(bp,
4790                                                       PXP2_REG_PXP2_PRTY_STS_1);
4791                                         break;
4792                                 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4793                                         _print_next_block((*par_num)++,
4794                                                           "PXPPCICLOCKCLIENT");
4795                                         break;
4796                                 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4797                                         _print_next_block((*par_num)++, "CFC");
4798                                         _print_parity(bp,
4799                                                       CFC_REG_CFC_PRTY_STS);
4800                                         break;
4801                                 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4802                                         _print_next_block((*par_num)++, "CDU");
4803                                         _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4804                                         break;
4805                                 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4806                                         _print_next_block((*par_num)++, "DMAE");
4807                                         _print_parity(bp,
4808                                                       DMAE_REG_DMAE_PRTY_STS);
4809                                         break;
4810                                 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4811                                         _print_next_block((*par_num)++, "IGU");
4812                                         if (CHIP_IS_E1x(bp))
4813                                                 _print_parity(bp,
4814                                                         HC_REG_HC_PRTY_STS);
4815                                         else
4816                                                 _print_parity(bp,
4817                                                         IGU_REG_IGU_PRTY_STS);
4818                                         break;
4819                                 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4820                                         _print_next_block((*par_num)++, "MISC");
4821                                         _print_parity(bp,
4822                                                       MISC_REG_MISC_PRTY_STS);
4823                                         break;
4824                                 }
4825                         }
4826
4827                         /* Clear the bit */
4828                         sig &= ~cur_bit;
4829                 }
4830         }
4831
4832         return res;
4833 }
4834
4835 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4836                                             int *par_num, bool *global,
4837                                             bool print)
4838 {
4839         bool res = false;
4840         u32 cur_bit;
4841         int i;
4842
4843         for (i = 0; sig; i++) {
4844                 cur_bit = (0x1UL << i);
4845                 if (sig & cur_bit) {
4846                         switch (cur_bit) {
4847                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4848                                 if (print)
4849                                         _print_next_block((*par_num)++,
4850                                                           "MCP ROM");
4851                                 *global = true;
4852                                 res = true;
4853                                 break;
4854                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4855                                 if (print)
4856                                         _print_next_block((*par_num)++,
4857                                                           "MCP UMP RX");
4858                                 *global = true;
4859                                 res = true;
4860                                 break;
4861                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4862                                 if (print)
4863                                         _print_next_block((*par_num)++,
4864                                                           "MCP UMP TX");
4865                                 *global = true;
4866                                 res = true;
4867                                 break;
4868                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4869                                 if (print)
4870                                         _print_next_block((*par_num)++,
4871                                                           "MCP SCPAD");
4872                                 /* clear latched SCPAD PATIRY from MCP */
4873                                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4874                                        1UL << 10);
4875                                 break;
4876                         }
4877
4878                         /* Clear the bit */
4879                         sig &= ~cur_bit;
4880                 }
4881         }
4882
4883         return res;
4884 }
4885
4886 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4887                                             int *par_num, bool print)
4888 {
4889         u32 cur_bit;
4890         bool res;
4891         int i;
4892
4893         res = false;
4894
4895         for (i = 0; sig; i++) {
4896                 cur_bit = (0x1UL << i);
4897                 if (sig & cur_bit) {
4898                         res = true; /* Each bit is real error! */
4899                         if (print) {
4900                                 switch (cur_bit) {
4901                                 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4902                                         _print_next_block((*par_num)++,
4903                                                           "PGLUE_B");
4904                                         _print_parity(bp,
4905                                                       PGLUE_B_REG_PGLUE_B_PRTY_STS);
4906                                         break;
4907                                 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4908                                         _print_next_block((*par_num)++, "ATC");
4909                                         _print_parity(bp,
4910                                                       ATC_REG_ATC_PRTY_STS);
4911                                         break;
4912                                 }
4913                         }
4914                         /* Clear the bit */
4915                         sig &= ~cur_bit;
4916                 }
4917         }
4918
4919         return res;
4920 }
4921
4922 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4923                               u32 *sig)
4924 {
4925         bool res = false;
4926
4927         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4928             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4929             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4930             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4931             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4932                 int par_num = 0;
4933                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4934                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4935                           sig[0] & HW_PRTY_ASSERT_SET_0,
4936                           sig[1] & HW_PRTY_ASSERT_SET_1,
4937                           sig[2] & HW_PRTY_ASSERT_SET_2,
4938                           sig[3] & HW_PRTY_ASSERT_SET_3,
4939                           sig[4] & HW_PRTY_ASSERT_SET_4);
4940                 if (print)
4941                         netdev_err(bp->dev,
4942                                    "Parity errors detected in blocks: ");
4943                 res |= bnx2x_check_blocks_with_parity0(bp,
4944                         sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4945                 res |= bnx2x_check_blocks_with_parity1(bp,
4946                         sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4947                 res |= bnx2x_check_blocks_with_parity2(bp,
4948                         sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4949                 res |= bnx2x_check_blocks_with_parity3(bp,
4950                         sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4951                 res |= bnx2x_check_blocks_with_parity4(bp,
4952                         sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4953
4954                 if (print)
4955                         pr_cont("\n");
4956         }
4957
4958         return res;
4959 }
4960
4961 /**
4962  * bnx2x_chk_parity_attn - checks for parity attentions.
4963  *
4964  * @bp:         driver handle
4965  * @global:     true if there was a global attention
4966  * @print:      show parity attention in syslog
4967  */
4968 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4969 {
4970         struct attn_route attn = { {0} };
4971         int port = BP_PORT(bp);
4972
4973         attn.sig[0] = REG_RD(bp,
4974                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4975                              port*4);
4976         attn.sig[1] = REG_RD(bp,
4977                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4978                              port*4);
4979         attn.sig[2] = REG_RD(bp,
4980                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4981                              port*4);
4982         attn.sig[3] = REG_RD(bp,
4983                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4984                              port*4);
4985         /* Since MCP attentions can't be disabled inside the block, we need to
4986          * read AEU registers to see whether they're currently disabled
4987          */
4988         attn.sig[3] &= ((REG_RD(bp,
4989                                 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
4990                                       : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
4991                          MISC_AEU_ENABLE_MCP_PRTY_BITS) |
4992                         ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
4993
4994         if (!CHIP_IS_E1x(bp))
4995                 attn.sig[4] = REG_RD(bp,
4996                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4997                                      port*4);
4998
4999         return bnx2x_parity_attn(bp, global, print, attn.sig);
5000 }
5001
5002 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
5003 {
5004         u32 val;
5005         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
5006
5007                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
5008                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
5009                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
5010                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
5011                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
5012                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
5013                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
5014                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
5015                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
5016                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
5017                 if (val &
5018                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
5019                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
5020                 if (val &
5021                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
5022                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
5023                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
5024                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
5025                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
5026                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
5027                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
5028                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
5029         }
5030         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
5031                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
5032                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
5033                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
5034                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5035                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
5036                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
5037                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
5038                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
5039                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
5040                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
5041                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
5042                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5043                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
5044                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
5045         }
5046
5047         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5048                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
5049                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5050                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5051                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
5052         }
5053 }
5054
5055 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
5056 {
5057         struct attn_route attn, *group_mask;
5058         int port = BP_PORT(bp);
5059         int index;
5060         u32 reg_addr;
5061         u32 val;
5062         u32 aeu_mask;
5063         bool global = false;
5064
5065         /* need to take HW lock because MCP or other port might also
5066            try to handle this event */
5067         bnx2x_acquire_alr(bp);
5068
5069         if (bnx2x_chk_parity_attn(bp, &global, true)) {
5070 #ifndef BNX2X_STOP_ON_ERROR
5071                 bp->recovery_state = BNX2X_RECOVERY_INIT;
5072                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5073                 /* Disable HW interrupts */
5074                 bnx2x_int_disable(bp);
5075                 /* In case of parity errors don't handle attentions so that
5076                  * other function would "see" parity errors.
5077                  */
5078 #else
5079                 bnx2x_panic();
5080 #endif
5081                 bnx2x_release_alr(bp);
5082                 return;
5083         }
5084
5085         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5086         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5087         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5088         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
5089         if (!CHIP_IS_E1x(bp))
5090                 attn.sig[4] =
5091                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5092         else
5093                 attn.sig[4] = 0;
5094
5095         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5096            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
5097
5098         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5099                 if (deasserted & (1 << index)) {
5100                         group_mask = &bp->attn_group[index];
5101
5102                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
5103                            index,
5104                            group_mask->sig[0], group_mask->sig[1],
5105                            group_mask->sig[2], group_mask->sig[3],
5106                            group_mask->sig[4]);
5107
5108                         bnx2x_attn_int_deasserted4(bp,
5109                                         attn.sig[4] & group_mask->sig[4]);
5110                         bnx2x_attn_int_deasserted3(bp,
5111                                         attn.sig[3] & group_mask->sig[3]);
5112                         bnx2x_attn_int_deasserted1(bp,
5113                                         attn.sig[1] & group_mask->sig[1]);
5114                         bnx2x_attn_int_deasserted2(bp,
5115                                         attn.sig[2] & group_mask->sig[2]);
5116                         bnx2x_attn_int_deasserted0(bp,
5117                                         attn.sig[0] & group_mask->sig[0]);
5118                 }
5119         }
5120
5121         bnx2x_release_alr(bp);
5122
5123         if (bp->common.int_block == INT_BLOCK_HC)
5124                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5125                             COMMAND_REG_ATTN_BITS_CLR);
5126         else
5127                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
5128
5129         val = ~deasserted;
5130         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5131            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5132         REG_WR(bp, reg_addr, val);
5133
5134         if (~bp->attn_state & deasserted)
5135                 BNX2X_ERR("IGU ERROR\n");
5136
5137         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5138                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
5139
5140         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5141         aeu_mask = REG_RD(bp, reg_addr);
5142
5143         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
5144            aeu_mask, deasserted);
5145         aeu_mask |= (deasserted & 0x3ff);
5146         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
5147
5148         REG_WR(bp, reg_addr, aeu_mask);
5149         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5150
5151         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5152         bp->attn_state &= ~deasserted;
5153         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5154 }
5155
5156 static void bnx2x_attn_int(struct bnx2x *bp)
5157 {
5158         /* read local copy of bits */
5159         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5160                                                                 attn_bits);
5161         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5162                                                                 attn_bits_ack);
5163         u32 attn_state = bp->attn_state;
5164
5165         /* look for changed bits */
5166         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
5167         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
5168
5169         DP(NETIF_MSG_HW,
5170            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
5171            attn_bits, attn_ack, asserted, deasserted);
5172
5173         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
5174                 BNX2X_ERR("BAD attention state\n");
5175
5176         /* handle bits that were raised */
5177         if (asserted)
5178                 bnx2x_attn_int_asserted(bp, asserted);
5179
5180         if (deasserted)
5181                 bnx2x_attn_int_deasserted(bp, deasserted);
5182 }
5183
5184 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5185                       u16 index, u8 op, u8 update)
5186 {
5187         u32 igu_addr = bp->igu_base_addr;
5188         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
5189         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5190                              igu_addr);
5191 }
5192
5193 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
5194 {
5195         /* No memory barriers */
5196         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5197         mmiowb(); /* keep prod updates ordered */
5198 }
5199
5200 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5201                                       union event_ring_elem *elem)
5202 {
5203         u8 err = elem->message.error;
5204
5205         if (!bp->cnic_eth_dev.starting_cid  ||
5206             (cid < bp->cnic_eth_dev.starting_cid &&
5207             cid != bp->cnic_eth_dev.iscsi_l2_cid))
5208                 return 1;
5209
5210         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5211
5212         if (unlikely(err)) {
5213
5214                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5215                           cid);
5216                 bnx2x_panic_dump(bp, false);
5217         }
5218         bnx2x_cnic_cfc_comp(bp, cid, err);
5219         return 0;
5220 }
5221
5222 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
5223 {
5224         struct bnx2x_mcast_ramrod_params rparam;
5225         int rc;
5226
5227         memset(&rparam, 0, sizeof(rparam));
5228
5229         rparam.mcast_obj = &bp->mcast_obj;
5230
5231         netif_addr_lock_bh(bp->dev);
5232
5233         /* Clear pending state for the last command */
5234         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5235
5236         /* If there are pending mcast commands - send them */
5237         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5238                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5239                 if (rc < 0)
5240                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5241                                   rc);
5242         }
5243
5244         netif_addr_unlock_bh(bp->dev);
5245 }
5246
5247 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5248                                             union event_ring_elem *elem)
5249 {
5250         unsigned long ramrod_flags = 0;
5251         int rc = 0;
5252         u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5253         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5254
5255         /* Always push next commands out, don't wait here */
5256         __set_bit(RAMROD_CONT, &ramrod_flags);
5257
5258         switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5259                             >> BNX2X_SWCID_SHIFT) {
5260         case BNX2X_FILTER_MAC_PENDING:
5261                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5262                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5263                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5264                 else
5265                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5266
5267                 break;
5268         case BNX2X_FILTER_MCAST_PENDING:
5269                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5270                 /* This is only relevant for 57710 where multicast MACs are
5271                  * configured as unicast MACs using the same ramrod.
5272                  */
5273                 bnx2x_handle_mcast_eqe(bp);
5274                 return;
5275         default:
5276                 BNX2X_ERR("Unsupported classification command: %d\n",
5277                           elem->message.data.eth_event.echo);
5278                 return;
5279         }
5280
5281         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5282
5283         if (rc < 0)
5284                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5285         else if (rc > 0)
5286                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5287 }
5288
5289 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5290
5291 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5292 {
5293         netif_addr_lock_bh(bp->dev);
5294
5295         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5296
5297         /* Send rx_mode command again if was requested */
5298         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5299                 bnx2x_set_storm_rx_mode(bp);
5300         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5301                                     &bp->sp_state))
5302                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5303         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5304                                     &bp->sp_state))
5305                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5306
5307         netif_addr_unlock_bh(bp->dev);
5308 }
5309
5310 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5311                                               union event_ring_elem *elem)
5312 {
5313         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5314                 DP(BNX2X_MSG_SP,
5315                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5316                    elem->message.data.vif_list_event.func_bit_map);
5317                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5318                         elem->message.data.vif_list_event.func_bit_map);
5319         } else if (elem->message.data.vif_list_event.echo ==
5320                    VIF_LIST_RULE_SET) {
5321                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5322                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5323         }
5324 }
5325
5326 /* called with rtnl_lock */
5327 static void bnx2x_after_function_update(struct bnx2x *bp)
5328 {
5329         int q, rc;
5330         struct bnx2x_fastpath *fp;
5331         struct bnx2x_queue_state_params queue_params = {NULL};
5332         struct bnx2x_queue_update_params *q_update_params =
5333                 &queue_params.params.update;
5334
5335         /* Send Q update command with afex vlan removal values for all Qs */
5336         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5337
5338         /* set silent vlan removal values according to vlan mode */
5339         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5340                   &q_update_params->update_flags);
5341         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5342                   &q_update_params->update_flags);
5343         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5344
5345         /* in access mode mark mask and value are 0 to strip all vlans */
5346         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5347                 q_update_params->silent_removal_value = 0;
5348                 q_update_params->silent_removal_mask = 0;
5349         } else {
5350                 q_update_params->silent_removal_value =
5351                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5352                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5353         }
5354
5355         for_each_eth_queue(bp, q) {
5356                 /* Set the appropriate Queue object */
5357                 fp = &bp->fp[q];
5358                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5359
5360                 /* send the ramrod */
5361                 rc = bnx2x_queue_state_change(bp, &queue_params);
5362                 if (rc < 0)
5363                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5364                                   q);
5365         }
5366
5367         if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5368                 fp = &bp->fp[FCOE_IDX(bp)];
5369                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5370
5371                 /* clear pending completion bit */
5372                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5373
5374                 /* mark latest Q bit */
5375                 smp_mb__before_atomic();
5376                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5377                 smp_mb__after_atomic();
5378
5379                 /* send Q update ramrod for FCoE Q */
5380                 rc = bnx2x_queue_state_change(bp, &queue_params);
5381                 if (rc < 0)
5382                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5383                                   q);
5384         } else {
5385                 /* If no FCoE ring - ACK MCP now */
5386                 bnx2x_link_report(bp);
5387                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5388         }
5389 }
5390
5391 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5392         struct bnx2x *bp, u32 cid)
5393 {
5394         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5395
5396         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5397                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5398         else
5399                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5400 }
5401
5402 static void bnx2x_eq_int(struct bnx2x *bp)
5403 {
5404         u16 hw_cons, sw_cons, sw_prod;
5405         union event_ring_elem *elem;
5406         u8 echo;
5407         u32 cid;
5408         u8 opcode;
5409         int rc, spqe_cnt = 0;
5410         struct bnx2x_queue_sp_obj *q_obj;
5411         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5412         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5413
5414         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5415
5416         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5417          * when we get the next-page we need to adjust so the loop
5418          * condition below will be met. The next element is the size of a
5419          * regular element and hence incrementing by 1
5420          */
5421         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5422                 hw_cons++;
5423
5424         /* This function may never run in parallel with itself for a
5425          * specific bp, thus there is no need in "paired" read memory
5426          * barrier here.
5427          */
5428         sw_cons = bp->eq_cons;
5429         sw_prod = bp->eq_prod;
5430
5431         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
5432                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5433
5434         for (; sw_cons != hw_cons;
5435               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5436
5437                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5438
5439                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5440                 if (!rc) {
5441                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5442                            rc);
5443                         goto next_spqe;
5444                 }
5445
5446                 /* elem CID originates from FW; actually LE */
5447                 cid = SW_CID((__force __le32)
5448                              elem->message.data.cfc_del_event.cid);
5449                 opcode = elem->message.opcode;
5450
5451                 /* handle eq element */
5452                 switch (opcode) {
5453                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5454                         bnx2x_vf_mbx_schedule(bp,
5455                                               &elem->message.data.vf_pf_event);
5456                         continue;
5457
5458                 case EVENT_RING_OPCODE_STAT_QUERY:
5459                         DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5460                                "got statistics comp event %d\n",
5461                                bp->stats_comp++);
5462                         /* nothing to do with stats comp */
5463                         goto next_spqe;
5464
5465                 case EVENT_RING_OPCODE_CFC_DEL:
5466                         /* handle according to cid range */
5467                         /*
5468                          * we may want to verify here that the bp state is
5469                          * HALTING
5470                          */
5471                         DP(BNX2X_MSG_SP,
5472                            "got delete ramrod for MULTI[%d]\n", cid);
5473
5474                         if (CNIC_LOADED(bp) &&
5475                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5476                                 goto next_spqe;
5477
5478                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5479
5480                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5481                                 break;
5482
5483                         goto next_spqe;
5484
5485                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5486                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5487                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5488                         if (f_obj->complete_cmd(bp, f_obj,
5489                                                 BNX2X_F_CMD_TX_STOP))
5490                                 break;
5491                         goto next_spqe;
5492
5493                 case EVENT_RING_OPCODE_START_TRAFFIC:
5494                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5495                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5496                         if (f_obj->complete_cmd(bp, f_obj,
5497                                                 BNX2X_F_CMD_TX_START))
5498                                 break;
5499                         goto next_spqe;
5500
5501                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5502                         echo = elem->message.data.function_update_event.echo;
5503                         if (echo == SWITCH_UPDATE) {
5504                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5505                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5506                                 if (f_obj->complete_cmd(
5507                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5508                                         break;
5509
5510                         } else {
5511                                 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5512
5513                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5514                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5515                                 f_obj->complete_cmd(bp, f_obj,
5516                                                     BNX2X_F_CMD_AFEX_UPDATE);
5517
5518                                 /* We will perform the Queues update from
5519                                  * sp_rtnl task as all Queue SP operations
5520                                  * should run under rtnl_lock.
5521                                  */
5522                                 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
5523                         }
5524
5525                         goto next_spqe;
5526
5527                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5528                         f_obj->complete_cmd(bp, f_obj,
5529                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5530                         bnx2x_after_afex_vif_lists(bp, elem);
5531                         goto next_spqe;
5532                 case EVENT_RING_OPCODE_FUNCTION_START:
5533                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5534                            "got FUNC_START ramrod\n");
5535                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5536                                 break;
5537
5538                         goto next_spqe;
5539
5540                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5541                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5542                            "got FUNC_STOP ramrod\n");
5543                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5544                                 break;
5545
5546                         goto next_spqe;
5547
5548                 case EVENT_RING_OPCODE_SET_TIMESYNC:
5549                         DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5550                            "got set_timesync ramrod completion\n");
5551                         if (f_obj->complete_cmd(bp, f_obj,
5552                                                 BNX2X_F_CMD_SET_TIMESYNC))
5553                                 break;
5554                         goto next_spqe;
5555                 }
5556
5557                 switch (opcode | bp->state) {
5558                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5559                       BNX2X_STATE_OPEN):
5560                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5561                       BNX2X_STATE_OPENING_WAIT4_PORT):
5562                         cid = elem->message.data.eth_event.echo &
5563                                 BNX2X_SWCID_MASK;
5564                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5565                            cid);
5566                         rss_raw->clear_pending(rss_raw);
5567                         break;
5568
5569                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5570                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5571                 case (EVENT_RING_OPCODE_SET_MAC |
5572                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5573                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5574                       BNX2X_STATE_OPEN):
5575                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5576                       BNX2X_STATE_DIAG):
5577                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5578                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5579                         DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5580                         bnx2x_handle_classification_eqe(bp, elem);
5581                         break;
5582
5583                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5584                       BNX2X_STATE_OPEN):
5585                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5586                       BNX2X_STATE_DIAG):
5587                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5588                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5589                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5590                         bnx2x_handle_mcast_eqe(bp);
5591                         break;
5592
5593                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5594                       BNX2X_STATE_OPEN):
5595                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5596                       BNX2X_STATE_DIAG):
5597                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5598                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5599                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5600                         bnx2x_handle_rx_mode_eqe(bp);
5601                         break;
5602                 default:
5603                         /* unknown event log error and continue */
5604                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5605                                   elem->message.opcode, bp->state);
5606                 }
5607 next_spqe:
5608                 spqe_cnt++;
5609         } /* for */
5610
5611         smp_mb__before_atomic();
5612         atomic_add(spqe_cnt, &bp->eq_spq_left);
5613
5614         bp->eq_cons = sw_cons;
5615         bp->eq_prod = sw_prod;
5616         /* Make sure that above mem writes were issued towards the memory */
5617         smp_wmb();
5618
5619         /* update producer */
5620         bnx2x_update_eq_prod(bp, bp->eq_prod);
5621 }
5622
5623 static void bnx2x_sp_task(struct work_struct *work)
5624 {
5625         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5626
5627         DP(BNX2X_MSG_SP, "sp task invoked\n");
5628
5629         /* make sure the atomic interrupt_occurred has been written */
5630         smp_rmb();
5631         if (atomic_read(&bp->interrupt_occurred)) {
5632
5633                 /* what work needs to be performed? */
5634                 u16 status = bnx2x_update_dsb_idx(bp);
5635
5636                 DP(BNX2X_MSG_SP, "status %x\n", status);
5637                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5638                 atomic_set(&bp->interrupt_occurred, 0);
5639
5640                 /* HW attentions */
5641                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5642                         bnx2x_attn_int(bp);
5643                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5644                 }
5645
5646                 /* SP events: STAT_QUERY and others */
5647                 if (status & BNX2X_DEF_SB_IDX) {
5648                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5649
5650                 if (FCOE_INIT(bp) &&
5651                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5652                                 /* Prevent local bottom-halves from running as
5653                                  * we are going to change the local NAPI list.
5654                                  */
5655                                 local_bh_disable();
5656                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5657                                 local_bh_enable();
5658                         }
5659
5660                         /* Handle EQ completions */
5661                         bnx2x_eq_int(bp);
5662                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5663                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5664
5665                         status &= ~BNX2X_DEF_SB_IDX;
5666                 }
5667
5668                 /* if status is non zero then perhaps something went wrong */
5669                 if (unlikely(status))
5670                         DP(BNX2X_MSG_SP,
5671                            "got an unknown interrupt! (status 0x%x)\n", status);
5672
5673                 /* ack status block only if something was actually handled */
5674                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5675                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5676         }
5677
5678         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5679         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5680                                &bp->sp_state)) {
5681                 bnx2x_link_report(bp);
5682                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5683         }
5684 }
5685
5686 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5687 {
5688         struct net_device *dev = dev_instance;
5689         struct bnx2x *bp = netdev_priv(dev);
5690
5691         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5692                      IGU_INT_DISABLE, 0);
5693
5694 #ifdef BNX2X_STOP_ON_ERROR
5695         if (unlikely(bp->panic))
5696                 return IRQ_HANDLED;
5697 #endif
5698
5699         if (CNIC_LOADED(bp)) {
5700                 struct cnic_ops *c_ops;
5701
5702                 rcu_read_lock();
5703                 c_ops = rcu_dereference(bp->cnic_ops);
5704                 if (c_ops)
5705                         c_ops->cnic_handler(bp->cnic_data, NULL);
5706                 rcu_read_unlock();
5707         }
5708
5709         /* schedule sp task to perform default status block work, ack
5710          * attentions and enable interrupts.
5711          */
5712         bnx2x_schedule_sp_task(bp);
5713
5714         return IRQ_HANDLED;
5715 }
5716
5717 /* end of slow path */
5718
5719 void bnx2x_drv_pulse(struct bnx2x *bp)
5720 {
5721         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5722                  bp->fw_drv_pulse_wr_seq);
5723 }
5724
5725 static void bnx2x_timer(unsigned long data)
5726 {
5727         struct bnx2x *bp = (struct bnx2x *) data;
5728
5729         if (!netif_running(bp->dev))
5730                 return;
5731
5732         if (IS_PF(bp) &&
5733             !BP_NOMCP(bp)) {
5734                 int mb_idx = BP_FW_MB_IDX(bp);
5735                 u16 drv_pulse;
5736                 u16 mcp_pulse;
5737
5738                 ++bp->fw_drv_pulse_wr_seq;
5739                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5740                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5741                 bnx2x_drv_pulse(bp);
5742
5743                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5744                              MCP_PULSE_SEQ_MASK);
5745                 /* The delta between driver pulse and mcp response
5746                  * should not get too big. If the MFW is more than 5 pulses
5747                  * behind, we should worry about it enough to generate an error
5748                  * log.
5749                  */
5750                 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5751                         BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5752                                   drv_pulse, mcp_pulse);
5753         }
5754
5755         if (bp->state == BNX2X_STATE_OPEN)
5756                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5757
5758         /* sample pf vf bulletin board for new posts from pf */
5759         if (IS_VF(bp))
5760                 bnx2x_timer_sriov(bp);
5761
5762         mod_timer(&bp->timer, jiffies + bp->current_interval);
5763 }
5764
5765 /* end of Statistics */
5766
5767 /* nic init */
5768
5769 /*
5770  * nic init service functions
5771  */
5772
5773 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5774 {
5775         u32 i;
5776         if (!(len%4) && !(addr%4))
5777                 for (i = 0; i < len; i += 4)
5778                         REG_WR(bp, addr + i, fill);
5779         else
5780                 for (i = 0; i < len; i++)
5781                         REG_WR8(bp, addr + i, fill);
5782 }
5783
5784 /* helper: writes FP SP data to FW - data_size in dwords */
5785 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5786                                 int fw_sb_id,
5787                                 u32 *sb_data_p,
5788                                 u32 data_size)
5789 {
5790         int index;
5791         for (index = 0; index < data_size; index++)
5792                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5793                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5794                         sizeof(u32)*index,
5795                         *(sb_data_p + index));
5796 }
5797
5798 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5799 {
5800         u32 *sb_data_p;
5801         u32 data_size = 0;
5802         struct hc_status_block_data_e2 sb_data_e2;
5803         struct hc_status_block_data_e1x sb_data_e1x;
5804
5805         /* disable the function first */
5806         if (!CHIP_IS_E1x(bp)) {
5807                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5808                 sb_data_e2.common.state = SB_DISABLED;
5809                 sb_data_e2.common.p_func.vf_valid = false;
5810                 sb_data_p = (u32 *)&sb_data_e2;
5811                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5812         } else {
5813                 memset(&sb_data_e1x, 0,
5814                        sizeof(struct hc_status_block_data_e1x));
5815                 sb_data_e1x.common.state = SB_DISABLED;
5816                 sb_data_e1x.common.p_func.vf_valid = false;
5817                 sb_data_p = (u32 *)&sb_data_e1x;
5818                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5819         }
5820         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5821
5822         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5823                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5824                         CSTORM_STATUS_BLOCK_SIZE);
5825         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5826                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5827                         CSTORM_SYNC_BLOCK_SIZE);
5828 }
5829
5830 /* helper:  writes SP SB data to FW */
5831 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5832                 struct hc_sp_status_block_data *sp_sb_data)
5833 {
5834         int func = BP_FUNC(bp);
5835         int i;
5836         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5837                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5838                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5839                         i*sizeof(u32),
5840                         *((u32 *)sp_sb_data + i));
5841 }
5842
5843 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5844 {
5845         int func = BP_FUNC(bp);
5846         struct hc_sp_status_block_data sp_sb_data;
5847         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5848
5849         sp_sb_data.state = SB_DISABLED;
5850         sp_sb_data.p_func.vf_valid = false;
5851
5852         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5853
5854         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5855                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5856                         CSTORM_SP_STATUS_BLOCK_SIZE);
5857         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5858                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5859                         CSTORM_SP_SYNC_BLOCK_SIZE);
5860 }
5861
5862 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5863                                            int igu_sb_id, int igu_seg_id)
5864 {
5865         hc_sm->igu_sb_id = igu_sb_id;
5866         hc_sm->igu_seg_id = igu_seg_id;
5867         hc_sm->timer_value = 0xFF;
5868         hc_sm->time_to_expire = 0xFFFFFFFF;
5869 }
5870
5871 /* allocates state machine ids. */
5872 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5873 {
5874         /* zero out state machine indices */
5875         /* rx indices */
5876         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5877
5878         /* tx indices */
5879         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5880         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5881         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5882         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5883
5884         /* map indices */
5885         /* rx indices */
5886         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5887                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5888
5889         /* tx indices */
5890         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5891                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5892         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5893                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5894         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5895                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5896         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5897                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5898 }
5899
5900 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5901                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5902 {
5903         int igu_seg_id;
5904
5905         struct hc_status_block_data_e2 sb_data_e2;
5906         struct hc_status_block_data_e1x sb_data_e1x;
5907         struct hc_status_block_sm  *hc_sm_p;
5908         int data_size;
5909         u32 *sb_data_p;
5910
5911         if (CHIP_INT_MODE_IS_BC(bp))
5912                 igu_seg_id = HC_SEG_ACCESS_NORM;
5913         else
5914                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5915
5916         bnx2x_zero_fp_sb(bp, fw_sb_id);
5917
5918         if (!CHIP_IS_E1x(bp)) {
5919                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5920                 sb_data_e2.common.state = SB_ENABLED;
5921                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5922                 sb_data_e2.common.p_func.vf_id = vfid;
5923                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5924                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5925                 sb_data_e2.common.same_igu_sb_1b = true;
5926                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5927                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5928                 hc_sm_p = sb_data_e2.common.state_machine;
5929                 sb_data_p = (u32 *)&sb_data_e2;
5930                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5931                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5932         } else {
5933                 memset(&sb_data_e1x, 0,
5934                        sizeof(struct hc_status_block_data_e1x));
5935                 sb_data_e1x.common.state = SB_ENABLED;
5936                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5937                 sb_data_e1x.common.p_func.vf_id = 0xff;
5938                 sb_data_e1x.common.p_func.vf_valid = false;
5939                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5940                 sb_data_e1x.common.same_igu_sb_1b = true;
5941                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5942                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5943                 hc_sm_p = sb_data_e1x.common.state_machine;
5944                 sb_data_p = (u32 *)&sb_data_e1x;
5945                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5946                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5947         }
5948
5949         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5950                                        igu_sb_id, igu_seg_id);
5951         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5952                                        igu_sb_id, igu_seg_id);
5953
5954         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5955
5956         /* write indices to HW - PCI guarantees endianity of regpairs */
5957         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5958 }
5959
5960 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5961                                      u16 tx_usec, u16 rx_usec)
5962 {
5963         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5964                                     false, rx_usec);
5965         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5966                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5967                                        tx_usec);
5968         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5969                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5970                                        tx_usec);
5971         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5972                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5973                                        tx_usec);
5974 }
5975
5976 static void bnx2x_init_def_sb(struct bnx2x *bp)
5977 {
5978         struct host_sp_status_block *def_sb = bp->def_status_blk;
5979         dma_addr_t mapping = bp->def_status_blk_mapping;
5980         int igu_sp_sb_index;
5981         int igu_seg_id;
5982         int port = BP_PORT(bp);
5983         int func = BP_FUNC(bp);
5984         int reg_offset, reg_offset_en5;
5985         u64 section;
5986         int index;
5987         struct hc_sp_status_block_data sp_sb_data;
5988         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5989
5990         if (CHIP_INT_MODE_IS_BC(bp)) {
5991                 igu_sp_sb_index = DEF_SB_IGU_ID;
5992                 igu_seg_id = HC_SEG_ACCESS_DEF;
5993         } else {
5994                 igu_sp_sb_index = bp->igu_dsb_id;
5995                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5996         }
5997
5998         /* ATTN */
5999         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6000                                             atten_status_block);
6001         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
6002
6003         bp->attn_state = 0;
6004
6005         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6006                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6007         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
6008                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
6009         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
6010                 int sindex;
6011                 /* take care of sig[0]..sig[4] */
6012                 for (sindex = 0; sindex < 4; sindex++)
6013                         bp->attn_group[index].sig[sindex] =
6014                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
6015
6016                 if (!CHIP_IS_E1x(bp))
6017                         /*
6018                          * enable5 is separate from the rest of the registers,
6019                          * and therefore the address skip is 4
6020                          * and not 16 between the different groups
6021                          */
6022                         bp->attn_group[index].sig[4] = REG_RD(bp,
6023                                         reg_offset_en5 + 0x4*index);
6024                 else
6025                         bp->attn_group[index].sig[4] = 0;
6026         }
6027
6028         if (bp->common.int_block == INT_BLOCK_HC) {
6029                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
6030                                      HC_REG_ATTN_MSG0_ADDR_L);
6031
6032                 REG_WR(bp, reg_offset, U64_LO(section));
6033                 REG_WR(bp, reg_offset + 4, U64_HI(section));
6034         } else if (!CHIP_IS_E1x(bp)) {
6035                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
6036                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
6037         }
6038
6039         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6040                                             sp_sb);
6041
6042         bnx2x_zero_sp_sb(bp);
6043
6044         /* PCI guarantees endianity of regpairs */
6045         sp_sb_data.state                = SB_ENABLED;
6046         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
6047         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
6048         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
6049         sp_sb_data.igu_seg_id           = igu_seg_id;
6050         sp_sb_data.p_func.pf_id         = func;
6051         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
6052         sp_sb_data.p_func.vf_id         = 0xff;
6053
6054         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
6055
6056         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6057 }
6058
6059 void bnx2x_update_coalesce(struct bnx2x *bp)
6060 {
6061         int i;
6062
6063         for_each_eth_queue(bp, i)
6064                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
6065                                          bp->tx_ticks, bp->rx_ticks);
6066 }
6067
6068 static void bnx2x_init_sp_ring(struct bnx2x *bp)
6069 {
6070         spin_lock_init(&bp->spq_lock);
6071         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
6072
6073         bp->spq_prod_idx = 0;
6074         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
6075         bp->spq_prod_bd = bp->spq;
6076         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
6077 }
6078
6079 static void bnx2x_init_eq_ring(struct bnx2x *bp)
6080 {
6081         int i;
6082         for (i = 1; i <= NUM_EQ_PAGES; i++) {
6083                 union event_ring_elem *elem =
6084                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
6085
6086                 elem->next_page.addr.hi =
6087                         cpu_to_le32(U64_HI(bp->eq_mapping +
6088                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6089                 elem->next_page.addr.lo =
6090                         cpu_to_le32(U64_LO(bp->eq_mapping +
6091                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
6092         }
6093         bp->eq_cons = 0;
6094         bp->eq_prod = NUM_EQ_DESC;
6095         bp->eq_cons_sb = BNX2X_EQ_INDEX;
6096         /* we want a warning message before it gets wrought... */
6097         atomic_set(&bp->eq_spq_left,
6098                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
6099 }
6100
6101 /* called with netif_addr_lock_bh() */
6102 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6103                                unsigned long rx_mode_flags,
6104                                unsigned long rx_accept_flags,
6105                                unsigned long tx_accept_flags,
6106                                unsigned long ramrod_flags)
6107 {
6108         struct bnx2x_rx_mode_ramrod_params ramrod_param;
6109         int rc;
6110
6111         memset(&ramrod_param, 0, sizeof(ramrod_param));
6112
6113         /* Prepare ramrod parameters */
6114         ramrod_param.cid = 0;
6115         ramrod_param.cl_id = cl_id;
6116         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6117         ramrod_param.func_id = BP_FUNC(bp);
6118
6119         ramrod_param.pstate = &bp->sp_state;
6120         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
6121
6122         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6123         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6124
6125         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6126
6127         ramrod_param.ramrod_flags = ramrod_flags;
6128         ramrod_param.rx_mode_flags = rx_mode_flags;
6129
6130         ramrod_param.rx_accept_flags = rx_accept_flags;
6131         ramrod_param.tx_accept_flags = tx_accept_flags;
6132
6133         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6134         if (rc < 0) {
6135                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
6136                 return rc;
6137         }
6138
6139         return 0;
6140 }
6141
6142 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6143                                    unsigned long *rx_accept_flags,
6144                                    unsigned long *tx_accept_flags)
6145 {
6146         /* Clear the flags first */
6147         *rx_accept_flags = 0;
6148         *tx_accept_flags = 0;
6149
6150         switch (rx_mode) {
6151         case BNX2X_RX_MODE_NONE:
6152                 /*
6153                  * 'drop all' supersedes any accept flags that may have been
6154                  * passed to the function.
6155                  */
6156                 break;
6157         case BNX2X_RX_MODE_NORMAL:
6158                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6159                 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6160                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6161
6162                 /* internal switching mode */
6163                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6164                 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6165                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6166
6167                 break;
6168         case BNX2X_RX_MODE_ALLMULTI:
6169                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6170                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6171                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6172
6173                 /* internal switching mode */
6174                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6175                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6176                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6177
6178                 break;
6179         case BNX2X_RX_MODE_PROMISC:
6180                 /* According to definition of SI mode, iface in promisc mode
6181                  * should receive matched and unmatched (in resolution of port)
6182                  * unicast packets.
6183                  */
6184                 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6185                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6186                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6187                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6188
6189                 /* internal switching mode */
6190                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6191                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6192
6193                 if (IS_MF_SI(bp))
6194                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
6195                 else
6196                         __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6197
6198                 break;
6199         default:
6200                 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6201                 return -EINVAL;
6202         }
6203
6204         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
6205         if (rx_mode != BNX2X_RX_MODE_NONE) {
6206                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6207                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6208         }
6209
6210         return 0;
6211 }
6212
6213 /* called with netif_addr_lock_bh() */
6214 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
6215 {
6216         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6217         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6218         int rc;
6219
6220         if (!NO_FCOE(bp))
6221                 /* Configure rx_mode of FCoE Queue */
6222                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6223
6224         rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6225                                      &tx_accept_flags);
6226         if (rc)
6227                 return rc;
6228
6229         __set_bit(RAMROD_RX, &ramrod_flags);
6230         __set_bit(RAMROD_TX, &ramrod_flags);
6231
6232         return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6233                                    rx_accept_flags, tx_accept_flags,
6234                                    ramrod_flags);
6235 }
6236
6237 static void bnx2x_init_internal_common(struct bnx2x *bp)
6238 {
6239         int i;
6240
6241         /* Zero this manually as its initialization is
6242            currently missing in the initTool */
6243         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6244                 REG_WR(bp, BAR_USTRORM_INTMEM +
6245                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
6246         if (!CHIP_IS_E1x(bp)) {
6247                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6248                         CHIP_INT_MODE_IS_BC(bp) ?
6249                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6250         }
6251 }
6252
6253 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6254 {
6255         switch (load_code) {
6256         case FW_MSG_CODE_DRV_LOAD_COMMON:
6257         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6258                 bnx2x_init_internal_common(bp);
6259                 /* no break */
6260
6261         case FW_MSG_CODE_DRV_LOAD_PORT:
6262                 /* nothing to do */
6263                 /* no break */
6264
6265         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6266                 /* internal memory per function is
6267                    initialized inside bnx2x_pf_init */
6268                 break;
6269
6270         default:
6271                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6272                 break;
6273         }
6274 }
6275
6276 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6277 {
6278         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6279 }
6280
6281 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6282 {
6283         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6284 }
6285
6286 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6287 {
6288         if (CHIP_IS_E1x(fp->bp))
6289                 return BP_L_ID(fp->bp) + fp->index;
6290         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
6291                 return bnx2x_fp_igu_sb_id(fp);
6292 }
6293
6294 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6295 {
6296         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6297         u8 cos;
6298         unsigned long q_type = 0;
6299         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6300         fp->rx_queue = fp_idx;
6301         fp->cid = fp_idx;
6302         fp->cl_id = bnx2x_fp_cl_id(fp);
6303         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6304         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6305         /* qZone id equals to FW (per path) client id */
6306         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
6307
6308         /* init shortcut */
6309         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6310
6311         /* Setup SB indices */
6312         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6313
6314         /* Configure Queue State object */
6315         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6316         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6317
6318         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6319
6320         /* init tx data */
6321         for_each_cos_in_tx_queue(fp, cos) {
6322                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6323                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6324                                   FP_COS_TO_TXQ(fp, cos, bp),
6325                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
6326                 cids[cos] = fp->txdata_ptr[cos]->cid;
6327         }
6328
6329         /* nothing more for vf to do here */
6330         if (IS_VF(bp))
6331                 return;
6332
6333         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6334                       fp->fw_sb_id, fp->igu_sb_id);
6335         bnx2x_update_fpsb_idx(fp);
6336         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6337                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6338                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6339
6340         /**
6341          * Configure classification DBs: Always enable Tx switching
6342          */
6343         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6344
6345         DP(NETIF_MSG_IFUP,
6346            "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
6347            fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6348            fp->igu_sb_id);
6349 }
6350
6351 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6352 {
6353         int i;
6354
6355         for (i = 1; i <= NUM_TX_RINGS; i++) {
6356                 struct eth_tx_next_bd *tx_next_bd =
6357                         &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6358
6359                 tx_next_bd->addr_hi =
6360                         cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6361                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6362                 tx_next_bd->addr_lo =
6363                         cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6364                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6365         }
6366
6367         *txdata->tx_cons_sb = cpu_to_le16(0);
6368
6369         SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6370         txdata->tx_db.data.zero_fill1 = 0;
6371         txdata->tx_db.data.prod = 0;
6372
6373         txdata->tx_pkt_prod = 0;
6374         txdata->tx_pkt_cons = 0;
6375         txdata->tx_bd_prod = 0;
6376         txdata->tx_bd_cons = 0;
6377         txdata->tx_pkt = 0;
6378 }
6379
6380 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6381 {
6382         int i;
6383
6384         for_each_tx_queue_cnic(bp, i)
6385                 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6386 }
6387
6388 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6389 {
6390         int i;
6391         u8 cos;
6392
6393         for_each_eth_queue(bp, i)
6394                 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6395                         bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6396 }
6397
6398 static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6399 {
6400         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6401         unsigned long q_type = 0;
6402
6403         bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6404         bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6405                                                      BNX2X_FCOE_ETH_CL_ID_IDX);
6406         bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6407         bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6408         bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6409         bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6410         bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6411                           fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6412                           fp);
6413
6414         DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6415
6416         /* qZone id equals to FW (per path) client id */
6417         bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6418         /* init shortcut */
6419         bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6420                 bnx2x_rx_ustorm_prods_offset(fp);
6421
6422         /* Configure Queue State object */
6423         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6424         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6425
6426         /* No multi-CoS for FCoE L2 client */
6427         BUG_ON(fp->max_cos != 1);
6428
6429         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6430                              &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6431                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6432
6433         DP(NETIF_MSG_IFUP,
6434            "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6435            fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6436            fp->igu_sb_id);
6437 }
6438
6439 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6440 {
6441         if (!NO_FCOE(bp))
6442                 bnx2x_init_fcoe_fp(bp);
6443
6444         bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6445                       BNX2X_VF_ID_INVALID, false,
6446                       bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6447
6448         /* ensure status block indices were read */
6449         rmb();
6450         bnx2x_init_rx_rings_cnic(bp);
6451         bnx2x_init_tx_rings_cnic(bp);
6452
6453         /* flush all */
6454         mb();
6455         mmiowb();
6456 }
6457
6458 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6459 {
6460         int i;
6461
6462         /* Setup NIC internals and enable interrupts */
6463         for_each_eth_queue(bp, i)
6464                 bnx2x_init_eth_fp(bp, i);
6465
6466         /* ensure status block indices were read */
6467         rmb();
6468         bnx2x_init_rx_rings(bp);
6469         bnx2x_init_tx_rings(bp);
6470
6471         if (IS_PF(bp)) {
6472                 /* Initialize MOD_ABS interrupts */
6473                 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6474                                        bp->common.shmem_base,
6475                                        bp->common.shmem2_base, BP_PORT(bp));
6476
6477                 /* initialize the default status block and sp ring */
6478                 bnx2x_init_def_sb(bp);
6479                 bnx2x_update_dsb_idx(bp);
6480                 bnx2x_init_sp_ring(bp);
6481         } else {
6482                 bnx2x_memset_stats(bp);
6483         }
6484 }
6485
6486 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6487 {
6488         bnx2x_init_eq_ring(bp);
6489         bnx2x_init_internal(bp, load_code);
6490         bnx2x_pf_init(bp);
6491         bnx2x_stats_init(bp);
6492
6493         /* flush all before enabling interrupts */
6494         mb();
6495         mmiowb();
6496
6497         bnx2x_int_enable(bp);
6498
6499         /* Check for SPIO5 */
6500         bnx2x_attn_int_deasserted0(bp,
6501                 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6502                                    AEU_INPUTS_ATTN_BITS_SPIO5);
6503 }
6504
6505 /* gzip service functions */
6506 static int bnx2x_gunzip_init(struct bnx2x *bp)
6507 {
6508         bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6509                                             &bp->gunzip_mapping, GFP_KERNEL);
6510         if (bp->gunzip_buf  == NULL)
6511                 goto gunzip_nomem1;
6512
6513         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6514         if (bp->strm  == NULL)
6515                 goto gunzip_nomem2;
6516
6517         bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6518         if (bp->strm->workspace == NULL)
6519                 goto gunzip_nomem3;
6520
6521         return 0;
6522
6523 gunzip_nomem3:
6524         kfree(bp->strm);
6525         bp->strm = NULL;
6526
6527 gunzip_nomem2:
6528         dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6529                           bp->gunzip_mapping);
6530         bp->gunzip_buf = NULL;
6531
6532 gunzip_nomem1:
6533         BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6534         return -ENOMEM;
6535 }
6536
6537 static void bnx2x_gunzip_end(struct bnx2x *bp)
6538 {
6539         if (bp->strm) {
6540                 vfree(bp->strm->workspace);
6541                 kfree(bp->strm);
6542                 bp->strm = NULL;
6543         }
6544
6545         if (bp->gunzip_buf) {
6546                 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6547                                   bp->gunzip_mapping);
6548                 bp->gunzip_buf = NULL;
6549         }
6550 }
6551
6552 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6553 {
6554         int n, rc;
6555
6556         /* check gzip header */
6557         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6558                 BNX2X_ERR("Bad gzip header\n");
6559                 return -EINVAL;
6560         }
6561
6562         n = 10;
6563
6564 #define FNAME                           0x8
6565
6566         if (zbuf[3] & FNAME)
6567                 while ((zbuf[n++] != 0) && (n < len));
6568
6569         bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6570         bp->strm->avail_in = len - n;
6571         bp->strm->next_out = bp->gunzip_buf;
6572         bp->strm->avail_out = FW_BUF_SIZE;
6573
6574         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6575         if (rc != Z_OK)
6576                 return rc;
6577
6578         rc = zlib_inflate(bp->strm, Z_FINISH);
6579         if ((rc != Z_OK) && (rc != Z_STREAM_END))
6580                 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6581                            bp->strm->msg);
6582
6583         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6584         if (bp->gunzip_outlen & 0x3)
6585                 netdev_err(bp->dev,
6586                            "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6587                                 bp->gunzip_outlen);
6588         bp->gunzip_outlen >>= 2;
6589
6590         zlib_inflateEnd(bp->strm);
6591
6592         if (rc == Z_STREAM_END)
6593                 return 0;
6594
6595         return rc;
6596 }
6597
6598 /* nic load/unload */
6599
6600 /*
6601  * General service functions
6602  */
6603
6604 /* send a NIG loopback debug packet */
6605 static void bnx2x_lb_pckt(struct bnx2x *bp)
6606 {
6607         u32 wb_write[3];
6608
6609         /* Ethernet source and destination addresses */
6610         wb_write[0] = 0x55555555;
6611         wb_write[1] = 0x55555555;
6612         wb_write[2] = 0x20;             /* SOP */
6613         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6614
6615         /* NON-IP protocol */
6616         wb_write[0] = 0x09000000;
6617         wb_write[1] = 0x55555555;
6618         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
6619         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6620 }
6621
6622 /* some of the internal memories
6623  * are not directly readable from the driver
6624  * to test them we send debug packets
6625  */
6626 static int bnx2x_int_mem_test(struct bnx2x *bp)
6627 {
6628         int factor;
6629         int count, i;
6630         u32 val = 0;
6631
6632         if (CHIP_REV_IS_FPGA(bp))
6633                 factor = 120;
6634         else if (CHIP_REV_IS_EMUL(bp))
6635                 factor = 200;
6636         else
6637                 factor = 1;
6638
6639         /* Disable inputs of parser neighbor blocks */
6640         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6641         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6642         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6643         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6644
6645         /*  Write 0 to parser credits for CFC search request */
6646         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6647
6648         /* send Ethernet packet */
6649         bnx2x_lb_pckt(bp);
6650
6651         /* TODO do i reset NIG statistic? */
6652         /* Wait until NIG register shows 1 packet of size 0x10 */
6653         count = 1000 * factor;
6654         while (count) {
6655
6656                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6657                 val = *bnx2x_sp(bp, wb_data[0]);
6658                 if (val == 0x10)
6659                         break;
6660
6661                 usleep_range(10000, 20000);
6662                 count--;
6663         }
6664         if (val != 0x10) {
6665                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6666                 return -1;
6667         }
6668
6669         /* Wait until PRS register shows 1 packet */
6670         count = 1000 * factor;
6671         while (count) {
6672                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6673                 if (val == 1)
6674                         break;
6675
6676                 usleep_range(10000, 20000);
6677                 count--;
6678         }
6679         if (val != 0x1) {
6680                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6681                 return -2;
6682         }
6683
6684         /* Reset and init BRB, PRS */
6685         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6686         msleep(50);
6687         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6688         msleep(50);
6689         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6690         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6691
6692         DP(NETIF_MSG_HW, "part2\n");
6693
6694         /* Disable inputs of parser neighbor blocks */
6695         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6696         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6697         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6698         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6699
6700         /* Write 0 to parser credits for CFC search request */
6701         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6702
6703         /* send 10 Ethernet packets */
6704         for (i = 0; i < 10; i++)
6705                 bnx2x_lb_pckt(bp);
6706
6707         /* Wait until NIG register shows 10 + 1
6708            packets of size 11*0x10 = 0xb0 */
6709         count = 1000 * factor;
6710         while (count) {
6711
6712                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6713                 val = *bnx2x_sp(bp, wb_data[0]);
6714                 if (val == 0xb0)
6715                         break;
6716
6717                 usleep_range(10000, 20000);
6718                 count--;
6719         }
6720         if (val != 0xb0) {
6721                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6722                 return -3;
6723         }
6724
6725         /* Wait until PRS register shows 2 packets */
6726         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6727         if (val != 2)
6728                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6729
6730         /* Write 1 to parser credits for CFC search request */
6731         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6732
6733         /* Wait until PRS register shows 3 packets */
6734         msleep(10 * factor);
6735         /* Wait until NIG register shows 1 packet of size 0x10 */
6736         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6737         if (val != 3)
6738                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6739
6740         /* clear NIG EOP FIFO */
6741         for (i = 0; i < 11; i++)
6742                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6743         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6744         if (val != 1) {
6745                 BNX2X_ERR("clear of NIG failed\n");
6746                 return -4;
6747         }
6748
6749         /* Reset and init BRB, PRS, NIG */
6750         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6751         msleep(50);
6752         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6753         msleep(50);
6754         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6755         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6756         if (!CNIC_SUPPORT(bp))
6757                 /* set NIC mode */
6758                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6759
6760         /* Enable inputs of parser neighbor blocks */
6761         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6762         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6763         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6764         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6765
6766         DP(NETIF_MSG_HW, "done\n");
6767
6768         return 0; /* OK */
6769 }
6770
6771 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6772 {
6773         u32 val;
6774
6775         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6776         if (!CHIP_IS_E1x(bp))
6777                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6778         else
6779                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6780         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6781         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6782         /*
6783          * mask read length error interrupts in brb for parser
6784          * (parsing unit and 'checksum and crc' unit)
6785          * these errors are legal (PU reads fixed length and CAC can cause
6786          * read length error on truncated packets)
6787          */
6788         REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6789         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6790         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6791         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6792         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6793         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6794 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6795 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6796         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6797         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6798         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6799 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6800 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6801         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6802         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6803         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6804         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6805 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6806 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6807
6808         val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT  |
6809                 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6810                 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6811         if (!CHIP_IS_E1x(bp))
6812                 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6813                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6814         REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6815
6816         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6817         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6818         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6819 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6820
6821         if (!CHIP_IS_E1x(bp))
6822                 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6823                 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6824
6825         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6826         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6827 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6828         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
6829 }
6830
6831 static void bnx2x_reset_common(struct bnx2x *bp)
6832 {
6833         u32 val = 0x1400;
6834
6835         /* reset_common */
6836         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6837                0xd3ffff7f);
6838
6839         if (CHIP_IS_E3(bp)) {
6840                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6841                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6842         }
6843
6844         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6845 }
6846
6847 static void bnx2x_setup_dmae(struct bnx2x *bp)
6848 {
6849         bp->dmae_ready = 0;
6850         spin_lock_init(&bp->dmae_lock);
6851 }
6852
6853 static void bnx2x_init_pxp(struct bnx2x *bp)
6854 {
6855         u16 devctl;
6856         int r_order, w_order;
6857
6858         pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6859         DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6860         w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6861         if (bp->mrrs == -1)
6862                 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6863         else {
6864                 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6865                 r_order = bp->mrrs;
6866         }
6867
6868         bnx2x_init_pxp_arb(bp, r_order, w_order);
6869 }
6870
6871 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6872 {
6873         int is_required;
6874         u32 val;
6875         int port;
6876
6877         if (BP_NOMCP(bp))
6878                 return;
6879
6880         is_required = 0;
6881         val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6882               SHARED_HW_CFG_FAN_FAILURE_MASK;
6883
6884         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6885                 is_required = 1;
6886
6887         /*
6888          * The fan failure mechanism is usually related to the PHY type since
6889          * the power consumption of the board is affected by the PHY. Currently,
6890          * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6891          */
6892         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6893                 for (port = PORT_0; port < PORT_MAX; port++) {
6894                         is_required |=
6895                                 bnx2x_fan_failure_det_req(
6896                                         bp,
6897                                         bp->common.shmem_base,
6898                                         bp->common.shmem2_base,
6899                                         port);
6900                 }
6901
6902         DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6903
6904         if (is_required == 0)
6905                 return;
6906
6907         /* Fan failure is indicated by SPIO 5 */
6908         bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6909
6910         /* set to active low mode */
6911         val = REG_RD(bp, MISC_REG_SPIO_INT);
6912         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6913         REG_WR(bp, MISC_REG_SPIO_INT, val);
6914
6915         /* enable interrupt to signal the IGU */
6916         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6917         val |= MISC_SPIO_SPIO5;
6918         REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6919 }
6920
6921 void bnx2x_pf_disable(struct bnx2x *bp)
6922 {
6923         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6924         val &= ~IGU_PF_CONF_FUNC_EN;
6925
6926         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6927         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6928         REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6929 }
6930
6931 static void bnx2x__common_init_phy(struct bnx2x *bp)
6932 {
6933         u32 shmem_base[2], shmem2_base[2];
6934         /* Avoid common init in case MFW supports LFA */
6935         if (SHMEM2_RD(bp, size) >
6936             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6937                 return;
6938         shmem_base[0] =  bp->common.shmem_base;
6939         shmem2_base[0] = bp->common.shmem2_base;
6940         if (!CHIP_IS_E1x(bp)) {
6941                 shmem_base[1] =
6942                         SHMEM2_RD(bp, other_shmem_base_addr);
6943                 shmem2_base[1] =
6944                         SHMEM2_RD(bp, other_shmem2_base_addr);
6945         }
6946         bnx2x_acquire_phy_lock(bp);
6947         bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6948                               bp->common.chip_id);
6949         bnx2x_release_phy_lock(bp);
6950 }
6951
6952 static void bnx2x_config_endianity(struct bnx2x *bp, u32 val)
6953 {
6954         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val);
6955         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val);
6956         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val);
6957         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val);
6958         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val);
6959
6960         /* make sure this value is 0 */
6961         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6962
6963         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val);
6964         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val);
6965         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val);
6966         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val);
6967 }
6968
6969 static void bnx2x_set_endianity(struct bnx2x *bp)
6970 {
6971 #ifdef __BIG_ENDIAN
6972         bnx2x_config_endianity(bp, 1);
6973 #else
6974         bnx2x_config_endianity(bp, 0);
6975 #endif
6976 }
6977
6978 static void bnx2x_reset_endianity(struct bnx2x *bp)
6979 {
6980         bnx2x_config_endianity(bp, 0);
6981 }
6982
6983 /**
6984  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6985  *
6986  * @bp:         driver handle
6987  */
6988 static int bnx2x_init_hw_common(struct bnx2x *bp)
6989 {
6990         u32 val;
6991
6992         DP(NETIF_MSG_HW, "starting common init  func %d\n", BP_ABS_FUNC(bp));
6993
6994         /*
6995          * take the RESET lock to protect undi_unload flow from accessing
6996          * registers while we're resetting the chip
6997          */
6998         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6999
7000         bnx2x_reset_common(bp);
7001         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
7002
7003         val = 0xfffc;
7004         if (CHIP_IS_E3(bp)) {
7005                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7006                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7007         }
7008         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
7009
7010         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7011
7012         bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
7013
7014         if (!CHIP_IS_E1x(bp)) {
7015                 u8 abs_func_id;
7016
7017                 /**
7018                  * 4-port mode or 2-port mode we need to turn of master-enable
7019                  * for everyone, after that, turn it back on for self.
7020                  * so, we disregard multi-function or not, and always disable
7021                  * for all functions on the given path, this means 0,2,4,6 for
7022                  * path 0 and 1,3,5,7 for path 1
7023                  */
7024                 for (abs_func_id = BP_PATH(bp);
7025                      abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
7026                         if (abs_func_id == BP_ABS_FUNC(bp)) {
7027                                 REG_WR(bp,
7028                                     PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
7029                                     1);
7030                                 continue;
7031                         }
7032
7033                         bnx2x_pretend_func(bp, abs_func_id);
7034                         /* clear pf enable */
7035                         bnx2x_pf_disable(bp);
7036                         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7037                 }
7038         }
7039
7040         bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
7041         if (CHIP_IS_E1(bp)) {
7042                 /* enable HW interrupt from PXP on USDM overflow
7043                    bit 16 on INT_MASK_0 */
7044                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
7045         }
7046
7047         bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
7048         bnx2x_init_pxp(bp);
7049         bnx2x_set_endianity(bp);
7050         bnx2x_ilt_init_page_size(bp, INITOP_SET);
7051
7052         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
7053                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
7054
7055         /* let the HW do it's magic ... */
7056         msleep(100);
7057         /* finish PXP init */
7058         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
7059         if (val != 1) {
7060                 BNX2X_ERR("PXP2 CFG failed\n");
7061                 return -EBUSY;
7062         }
7063         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
7064         if (val != 1) {
7065                 BNX2X_ERR("PXP2 RD_INIT failed\n");
7066                 return -EBUSY;
7067         }
7068
7069         /* Timers bug workaround E2 only. We need to set the entire ILT to
7070          * have entries with value "0" and valid bit on.
7071          * This needs to be done by the first PF that is loaded in a path
7072          * (i.e. common phase)
7073          */
7074         if (!CHIP_IS_E1x(bp)) {
7075 /* In E2 there is a bug in the timers block that can cause function 6 / 7
7076  * (i.e. vnic3) to start even if it is marked as "scan-off".
7077  * This occurs when a different function (func2,3) is being marked
7078  * as "scan-off". Real-life scenario for example: if a driver is being
7079  * load-unloaded while func6,7 are down. This will cause the timer to access
7080  * the ilt, translate to a logical address and send a request to read/write.
7081  * Since the ilt for the function that is down is not valid, this will cause
7082  * a translation error which is unrecoverable.
7083  * The Workaround is intended to make sure that when this happens nothing fatal
7084  * will occur. The workaround:
7085  *      1.  First PF driver which loads on a path will:
7086  *              a.  After taking the chip out of reset, by using pretend,
7087  *                  it will write "0" to the following registers of
7088  *                  the other vnics.
7089  *                  REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
7090  *                  REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
7091  *                  REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
7092  *                  And for itself it will write '1' to
7093  *                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
7094  *                  dmae-operations (writing to pram for example.)
7095  *                  note: can be done for only function 6,7 but cleaner this
7096  *                        way.
7097  *              b.  Write zero+valid to the entire ILT.
7098  *              c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
7099  *                  VNIC3 (of that port). The range allocated will be the
7100  *                  entire ILT. This is needed to prevent  ILT range error.
7101  *      2.  Any PF driver load flow:
7102  *              a.  ILT update with the physical addresses of the allocated
7103  *                  logical pages.
7104  *              b.  Wait 20msec. - note that this timeout is needed to make
7105  *                  sure there are no requests in one of the PXP internal
7106  *                  queues with "old" ILT addresses.
7107  *              c.  PF enable in the PGLC.
7108  *              d.  Clear the was_error of the PF in the PGLC. (could have
7109  *                  occurred while driver was down)
7110  *              e.  PF enable in the CFC (WEAK + STRONG)
7111  *              f.  Timers scan enable
7112  *      3.  PF driver unload flow:
7113  *              a.  Clear the Timers scan_en.
7114  *              b.  Polling for scan_on=0 for that PF.
7115  *              c.  Clear the PF enable bit in the PXP.
7116  *              d.  Clear the PF enable in the CFC (WEAK + STRONG)
7117  *              e.  Write zero+valid to all ILT entries (The valid bit must
7118  *                  stay set)
7119  *              f.  If this is VNIC 3 of a port then also init
7120  *                  first_timers_ilt_entry to zero and last_timers_ilt_entry
7121  *                  to the last entry in the ILT.
7122  *
7123  *      Notes:
7124  *      Currently the PF error in the PGLC is non recoverable.
7125  *      In the future the there will be a recovery routine for this error.
7126  *      Currently attention is masked.
7127  *      Having an MCP lock on the load/unload process does not guarantee that
7128  *      there is no Timer disable during Func6/7 enable. This is because the
7129  *      Timers scan is currently being cleared by the MCP on FLR.
7130  *      Step 2.d can be done only for PF6/7 and the driver can also check if
7131  *      there is error before clearing it. But the flow above is simpler and
7132  *      more general.
7133  *      All ILT entries are written by zero+valid and not just PF6/7
7134  *      ILT entries since in the future the ILT entries allocation for
7135  *      PF-s might be dynamic.
7136  */
7137                 struct ilt_client_info ilt_cli;
7138                 struct bnx2x_ilt ilt;
7139                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7140                 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7141
7142                 /* initialize dummy TM client */
7143                 ilt_cli.start = 0;
7144                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7145                 ilt_cli.client_num = ILT_CLIENT_TM;
7146
7147                 /* Step 1: set zeroes to all ilt page entries with valid bit on
7148                  * Step 2: set the timers first/last ilt entry to point
7149                  * to the entire range to prevent ILT range error for 3rd/4th
7150                  * vnic (this code assumes existence of the vnic)
7151                  *
7152                  * both steps performed by call to bnx2x_ilt_client_init_op()
7153                  * with dummy TM client
7154                  *
7155                  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7156                  * and his brother are split registers
7157                  */
7158                 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7159                 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7160                 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7161
7162                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7163                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7164                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7165         }
7166
7167         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7168         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
7169
7170         if (!CHIP_IS_E1x(bp)) {
7171                 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7172                                 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
7173                 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
7174
7175                 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
7176
7177                 /* let the HW do it's magic ... */
7178                 do {
7179                         msleep(200);
7180                         val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7181                 } while (factor-- && (val != 1));
7182
7183                 if (val != 1) {
7184                         BNX2X_ERR("ATC_INIT failed\n");
7185                         return -EBUSY;
7186                 }
7187         }
7188
7189         bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
7190
7191         bnx2x_iov_init_dmae(bp);
7192
7193         /* clean the DMAE memory */
7194         bp->dmae_ready = 1;
7195         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7196
7197         bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7198
7199         bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7200
7201         bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
7202
7203         bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
7204
7205         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7206         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7207         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7208         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7209
7210         bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
7211
7212         /* QM queues pointers table */
7213         bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7214
7215         /* soft reset pulse */
7216         REG_WR(bp, QM_REG_SOFT_RESET, 1);
7217         REG_WR(bp, QM_REG_SOFT_RESET, 0);
7218
7219         if (CNIC_SUPPORT(bp))
7220                 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
7221
7222         bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
7223
7224         if (!CHIP_REV_IS_SLOW(bp))
7225                 /* enable hw interrupt from doorbell Q */
7226                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
7227
7228         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
7229
7230         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
7231         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
7232
7233         if (!CHIP_IS_E1(bp))
7234                 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
7235
7236         if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7237                 if (IS_MF_AFEX(bp)) {
7238                         /* configure that VNTag and VLAN headers must be
7239                          * received in afex mode
7240                          */
7241                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7242                         REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7243                         REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7244                         REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7245                         REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7246                 } else {
7247                         /* Bit-map indicating which L2 hdrs may appear
7248                          * after the basic Ethernet header
7249                          */
7250                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7251                                bp->path_has_ovlan ? 7 : 6);
7252                 }
7253         }
7254
7255         bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7256         bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7257         bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7258         bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
7259
7260         if (!CHIP_IS_E1x(bp)) {
7261                 /* reset VFC memories */
7262                 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7263                            VFC_MEMORIES_RST_REG_CAM_RST |
7264                            VFC_MEMORIES_RST_REG_RAM_RST);
7265                 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7266                            VFC_MEMORIES_RST_REG_CAM_RST |
7267                            VFC_MEMORIES_RST_REG_RAM_RST);
7268
7269                 msleep(20);
7270         }
7271
7272         bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7273         bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7274         bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7275         bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
7276
7277         /* sync semi rtc */
7278         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7279                0x80000000);
7280         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7281                0x80000000);
7282
7283         bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7284         bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7285         bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
7286
7287         if (!CHIP_IS_E1x(bp)) {
7288                 if (IS_MF_AFEX(bp)) {
7289                         /* configure that VNTag and VLAN headers must be
7290                          * sent in afex mode
7291                          */
7292                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7293                         REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7294                         REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7295                         REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7296                         REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7297                 } else {
7298                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7299                                bp->path_has_ovlan ? 7 : 6);
7300                 }
7301         }
7302
7303         REG_WR(bp, SRC_REG_SOFT_RST, 1);
7304
7305         bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7306
7307         if (CNIC_SUPPORT(bp)) {
7308                 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7309                 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7310                 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7311                 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7312                 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7313                 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7314                 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7315                 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7316                 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7317                 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7318         }
7319         REG_WR(bp, SRC_REG_SOFT_RST, 0);
7320
7321         if (sizeof(union cdu_context) != 1024)
7322                 /* we currently assume that a context is 1024 bytes */
7323                 dev_alert(&bp->pdev->dev,
7324                           "please adjust the size of cdu_context(%ld)\n",
7325                           (long)sizeof(union cdu_context));
7326
7327         bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
7328         val = (4 << 24) + (0 << 12) + 1024;
7329         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
7330
7331         bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
7332         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
7333         /* enable context validation interrupt from CFC */
7334         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7335
7336         /* set the thresholds to prevent CFC/CDU race */
7337         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
7338
7339         bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
7340
7341         if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
7342                 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7343
7344         bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7345         bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7346
7347         /* Reset PCIE errors for debug */
7348         REG_WR(bp, 0x2814, 0xffffffff);
7349         REG_WR(bp, 0x3820, 0xffffffff);
7350
7351         if (!CHIP_IS_E1x(bp)) {
7352                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7353                            (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7354                                 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7355                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7356                            (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7357                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7358                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7359                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7360                            (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7361                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7362                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7363         }
7364
7365         bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7366         if (!CHIP_IS_E1(bp)) {
7367                 /* in E3 this done in per-port section */
7368                 if (!CHIP_IS_E3(bp))
7369                         REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7370         }
7371         if (CHIP_IS_E1H(bp))
7372                 /* not applicable for E2 (and above ...) */
7373                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7374
7375         if (CHIP_REV_IS_SLOW(bp))
7376                 msleep(200);
7377
7378         /* finish CFC init */
7379         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7380         if (val != 1) {
7381                 BNX2X_ERR("CFC LL_INIT failed\n");
7382                 return -EBUSY;
7383         }
7384         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7385         if (val != 1) {
7386                 BNX2X_ERR("CFC AC_INIT failed\n");
7387                 return -EBUSY;
7388         }
7389         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7390         if (val != 1) {
7391                 BNX2X_ERR("CFC CAM_INIT failed\n");
7392                 return -EBUSY;
7393         }
7394         REG_WR(bp, CFC_REG_DEBUG0, 0);
7395
7396         if (CHIP_IS_E1(bp)) {
7397                 /* read NIG statistic
7398                    to see if this is our first up since powerup */
7399                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7400                 val = *bnx2x_sp(bp, wb_data[0]);
7401
7402                 /* do internal memory self test */
7403                 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7404                         BNX2X_ERR("internal mem self test failed\n");
7405                         return -EBUSY;
7406                 }
7407         }
7408
7409         bnx2x_setup_fan_failure_detection(bp);
7410
7411         /* clear PXP2 attentions */
7412         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7413
7414         bnx2x_enable_blocks_attention(bp);
7415         bnx2x_enable_blocks_parity(bp);
7416
7417         if (!BP_NOMCP(bp)) {
7418                 if (CHIP_IS_E1x(bp))
7419                         bnx2x__common_init_phy(bp);
7420         } else
7421                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7422
7423         return 0;
7424 }
7425
7426 /**
7427  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7428  *
7429  * @bp:         driver handle
7430  */
7431 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7432 {
7433         int rc = bnx2x_init_hw_common(bp);
7434
7435         if (rc)
7436                 return rc;
7437
7438         /* In E2 2-PORT mode, same ext phy is used for the two paths */
7439         if (!BP_NOMCP(bp))
7440                 bnx2x__common_init_phy(bp);
7441
7442         return 0;
7443 }
7444
7445 static int bnx2x_init_hw_port(struct bnx2x *bp)
7446 {
7447         int port = BP_PORT(bp);
7448         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7449         u32 low, high;
7450         u32 val, reg;
7451
7452         DP(NETIF_MSG_HW, "starting port init  port %d\n", port);
7453
7454         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7455
7456         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7457         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7458         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7459
7460         /* Timers bug workaround: disables the pf_master bit in pglue at
7461          * common phase, we need to enable it here before any dmae access are
7462          * attempted. Therefore we manually added the enable-master to the
7463          * port phase (it also happens in the function phase)
7464          */
7465         if (!CHIP_IS_E1x(bp))
7466                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7467
7468         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7469         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7470         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7471         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7472
7473         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7474         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7475         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7476         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7477
7478         /* QM cid (connection) count */
7479         bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7480
7481         if (CNIC_SUPPORT(bp)) {
7482                 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7483                 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7484                 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7485         }
7486
7487         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7488
7489         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7490
7491         if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7492
7493                 if (IS_MF(bp))
7494                         low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7495                 else if (bp->dev->mtu > 4096) {
7496                         if (bp->flags & ONE_PORT_FLAG)
7497                                 low = 160;
7498                         else {
7499                                 val = bp->dev->mtu;
7500                                 /* (24*1024 + val*4)/256 */
7501                                 low = 96 + (val/64) +
7502                                                 ((val % 64) ? 1 : 0);
7503                         }
7504                 } else
7505                         low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7506                 high = low + 56;        /* 14*1024/256 */
7507                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7508                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7509         }
7510
7511         if (CHIP_MODE_IS_4_PORT(bp))
7512                 REG_WR(bp, (BP_PORT(bp) ?
7513                             BRB1_REG_MAC_GUARANTIED_1 :
7514                             BRB1_REG_MAC_GUARANTIED_0), 40);
7515
7516         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7517         if (CHIP_IS_E3B0(bp)) {
7518                 if (IS_MF_AFEX(bp)) {
7519                         /* configure headers for AFEX mode */
7520                         REG_WR(bp, BP_PORT(bp) ?
7521                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7522                                PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7523                         REG_WR(bp, BP_PORT(bp) ?
7524                                PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7525                                PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7526                         REG_WR(bp, BP_PORT(bp) ?
7527                                PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7528                                PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7529                 } else {
7530                         /* Ovlan exists only if we are in multi-function +
7531                          * switch-dependent mode, in switch-independent there
7532                          * is no ovlan headers
7533                          */
7534                         REG_WR(bp, BP_PORT(bp) ?
7535                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7536                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7537                                (bp->path_has_ovlan ? 7 : 6));
7538                 }
7539         }
7540
7541         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7542         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7543         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7544         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7545
7546         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7547         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7548         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7549         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7550
7551         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7552         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7553
7554         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7555
7556         if (CHIP_IS_E1x(bp)) {
7557                 /* configure PBF to work without PAUSE mtu 9000 */
7558                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7559
7560                 /* update threshold */
7561                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7562                 /* update init credit */
7563                 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7564
7565                 /* probe changes */
7566                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7567                 udelay(50);
7568                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7569         }
7570
7571         if (CNIC_SUPPORT(bp))
7572                 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7573
7574         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7575         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7576
7577         if (CHIP_IS_E1(bp)) {
7578                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7579                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7580         }
7581         bnx2x_init_block(bp, BLOCK_HC, init_phase);
7582
7583         bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7584
7585         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7586         /* init aeu_mask_attn_func_0/1:
7587          *  - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7588          *  - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7589          *             bits 4-7 are used for "per vn group attention" */
7590         val = IS_MF(bp) ? 0xF7 : 0x7;
7591         /* Enable DCBX attention for all but E1 */
7592         val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7593         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7594
7595         /* SCPAD_PARITY should NOT trigger close the gates */
7596         reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7597         REG_WR(bp, reg,
7598                REG_RD(bp, reg) &
7599                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7600
7601         reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7602         REG_WR(bp, reg,
7603                REG_RD(bp, reg) &
7604                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7605
7606         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7607
7608         if (!CHIP_IS_E1x(bp)) {
7609                 /* Bit-map indicating which L2 hdrs may appear after the
7610                  * basic Ethernet header
7611                  */
7612                 if (IS_MF_AFEX(bp))
7613                         REG_WR(bp, BP_PORT(bp) ?
7614                                NIG_REG_P1_HDRS_AFTER_BASIC :
7615                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7616                 else
7617                         REG_WR(bp, BP_PORT(bp) ?
7618                                NIG_REG_P1_HDRS_AFTER_BASIC :
7619                                NIG_REG_P0_HDRS_AFTER_BASIC,
7620                                IS_MF_SD(bp) ? 7 : 6);
7621
7622                 if (CHIP_IS_E3(bp))
7623                         REG_WR(bp, BP_PORT(bp) ?
7624                                    NIG_REG_LLH1_MF_MODE :
7625                                    NIG_REG_LLH_MF_MODE, IS_MF(bp));
7626         }
7627         if (!CHIP_IS_E3(bp))
7628                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7629
7630         if (!CHIP_IS_E1(bp)) {
7631                 /* 0x2 disable mf_ov, 0x1 enable */
7632                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7633                        (IS_MF_SD(bp) ? 0x1 : 0x2));
7634
7635                 if (!CHIP_IS_E1x(bp)) {
7636                         val = 0;
7637                         switch (bp->mf_mode) {
7638                         case MULTI_FUNCTION_SD:
7639                                 val = 1;
7640                                 break;
7641                         case MULTI_FUNCTION_SI:
7642                         case MULTI_FUNCTION_AFEX:
7643                                 val = 2;
7644                                 break;
7645                         }
7646
7647                         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7648                                                   NIG_REG_LLH0_CLS_TYPE), val);
7649                 }
7650                 {
7651                         REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7652                         REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7653                         REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7654                 }
7655         }
7656
7657         /* If SPIO5 is set to generate interrupts, enable it for this port */
7658         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7659         if (val & MISC_SPIO_SPIO5) {
7660                 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7661                                        MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7662                 val = REG_RD(bp, reg_addr);
7663                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7664                 REG_WR(bp, reg_addr, val);
7665         }
7666
7667         return 0;
7668 }
7669
7670 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7671 {
7672         int reg;
7673         u32 wb_write[2];
7674
7675         if (CHIP_IS_E1(bp))
7676                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7677         else
7678                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7679
7680         wb_write[0] = ONCHIP_ADDR1(addr);
7681         wb_write[1] = ONCHIP_ADDR2(addr);
7682         REG_WR_DMAE(bp, reg, wb_write, 2);
7683 }
7684
7685 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7686 {
7687         u32 data, ctl, cnt = 100;
7688         u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7689         u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7690         u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7691         u32 sb_bit =  1 << (idu_sb_id%32);
7692         u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7693         u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7694
7695         /* Not supported in BC mode */
7696         if (CHIP_INT_MODE_IS_BC(bp))
7697                 return;
7698
7699         data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7700                         << IGU_REGULAR_CLEANUP_TYPE_SHIFT)      |
7701                 IGU_REGULAR_CLEANUP_SET                         |
7702                 IGU_REGULAR_BCLEANUP;
7703
7704         ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT         |
7705               func_encode << IGU_CTRL_REG_FID_SHIFT             |
7706               IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7707
7708         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7709                          data, igu_addr_data);
7710         REG_WR(bp, igu_addr_data, data);
7711         mmiowb();
7712         barrier();
7713         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7714                           ctl, igu_addr_ctl);
7715         REG_WR(bp, igu_addr_ctl, ctl);
7716         mmiowb();
7717         barrier();
7718
7719         /* wait for clean up to finish */
7720         while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7721                 msleep(20);
7722
7723         if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7724                 DP(NETIF_MSG_HW,
7725                    "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7726                           idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7727         }
7728 }
7729
7730 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7731 {
7732         bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7733 }
7734
7735 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7736 {
7737         u32 i, base = FUNC_ILT_BASE(func);
7738         for (i = base; i < base + ILT_PER_FUNC; i++)
7739                 bnx2x_ilt_wr(bp, i, 0);
7740 }
7741
7742 static void bnx2x_init_searcher(struct bnx2x *bp)
7743 {
7744         int port = BP_PORT(bp);
7745         bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7746         /* T1 hash bits value determines the T1 number of entries */
7747         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7748 }
7749
7750 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7751 {
7752         int rc;
7753         struct bnx2x_func_state_params func_params = {NULL};
7754         struct bnx2x_func_switch_update_params *switch_update_params =
7755                 &func_params.params.switch_update;
7756
7757         /* Prepare parameters for function state transitions */
7758         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7759         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7760
7761         func_params.f_obj = &bp->func_obj;
7762         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7763
7764         /* Function parameters */
7765         __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
7766                   &switch_update_params->changes);
7767         if (suspend)
7768                 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
7769                           &switch_update_params->changes);
7770
7771         rc = bnx2x_func_state_change(bp, &func_params);
7772
7773         return rc;
7774 }
7775
7776 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7777 {
7778         int rc, i, port = BP_PORT(bp);
7779         int vlan_en = 0, mac_en[NUM_MACS];
7780
7781         /* Close input from network */
7782         if (bp->mf_mode == SINGLE_FUNCTION) {
7783                 bnx2x_set_rx_filter(&bp->link_params, 0);
7784         } else {
7785                 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7786                                    NIG_REG_LLH0_FUNC_EN);
7787                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7788                           NIG_REG_LLH0_FUNC_EN, 0);
7789                 for (i = 0; i < NUM_MACS; i++) {
7790                         mac_en[i] = REG_RD(bp, port ?
7791                                              (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7792                                               4 * i) :
7793                                              (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7794                                               4 * i));
7795                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7796                                               4 * i) :
7797                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7798                 }
7799         }
7800
7801         /* Close BMC to host */
7802         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7803                NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7804
7805         /* Suspend Tx switching to the PF. Completion of this ramrod
7806          * further guarantees that all the packets of that PF / child
7807          * VFs in BRB were processed by the Parser, so it is safe to
7808          * change the NIC_MODE register.
7809          */
7810         rc = bnx2x_func_switch_update(bp, 1);
7811         if (rc) {
7812                 BNX2X_ERR("Can't suspend tx-switching!\n");
7813                 return rc;
7814         }
7815
7816         /* Change NIC_MODE register */
7817         REG_WR(bp, PRS_REG_NIC_MODE, 0);
7818
7819         /* Open input from network */
7820         if (bp->mf_mode == SINGLE_FUNCTION) {
7821                 bnx2x_set_rx_filter(&bp->link_params, 1);
7822         } else {
7823                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7824                           NIG_REG_LLH0_FUNC_EN, vlan_en);
7825                 for (i = 0; i < NUM_MACS; i++) {
7826                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7827                                               4 * i) :
7828                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7829                                   mac_en[i]);
7830                 }
7831         }
7832
7833         /* Enable BMC to host */
7834         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7835                NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7836
7837         /* Resume Tx switching to the PF */
7838         rc = bnx2x_func_switch_update(bp, 0);
7839         if (rc) {
7840                 BNX2X_ERR("Can't resume tx-switching!\n");
7841                 return rc;
7842         }
7843
7844         DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7845         return 0;
7846 }
7847
7848 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7849 {
7850         int rc;
7851
7852         bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7853
7854         if (CONFIGURE_NIC_MODE(bp)) {
7855                 /* Configure searcher as part of function hw init */
7856                 bnx2x_init_searcher(bp);
7857
7858                 /* Reset NIC mode */
7859                 rc = bnx2x_reset_nic_mode(bp);
7860                 if (rc)
7861                         BNX2X_ERR("Can't change NIC mode!\n");
7862                 return rc;
7863         }
7864
7865         return 0;
7866 }
7867
7868 static int bnx2x_init_hw_func(struct bnx2x *bp)
7869 {
7870         int port = BP_PORT(bp);
7871         int func = BP_FUNC(bp);
7872         int init_phase = PHASE_PF0 + func;
7873         struct bnx2x_ilt *ilt = BP_ILT(bp);
7874         u16 cdu_ilt_start;
7875         u32 addr, val;
7876         u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7877         int i, main_mem_width, rc;
7878
7879         DP(NETIF_MSG_HW, "starting func init  func %d\n", func);
7880
7881         /* FLR cleanup - hmmm */
7882         if (!CHIP_IS_E1x(bp)) {
7883                 rc = bnx2x_pf_flr_clnup(bp);
7884                 if (rc) {
7885                         bnx2x_fw_dump(bp);
7886                         return rc;
7887                 }
7888         }
7889
7890         /* set MSI reconfigure capability */
7891         if (bp->common.int_block == INT_BLOCK_HC) {
7892                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7893                 val = REG_RD(bp, addr);
7894                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7895                 REG_WR(bp, addr, val);
7896         }
7897
7898         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7899         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7900
7901         ilt = BP_ILT(bp);
7902         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7903
7904         if (IS_SRIOV(bp))
7905                 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7906         cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7907
7908         /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7909          * those of the VFs, so start line should be reset
7910          */
7911         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7912         for (i = 0; i < L2_ILT_LINES(bp); i++) {
7913                 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7914                 ilt->lines[cdu_ilt_start + i].page_mapping =
7915                         bp->context[i].cxt_mapping;
7916                 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7917         }
7918
7919         bnx2x_ilt_init_op(bp, INITOP_SET);
7920
7921         if (!CONFIGURE_NIC_MODE(bp)) {
7922                 bnx2x_init_searcher(bp);
7923                 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7924                 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7925         } else {
7926                 /* Set NIC mode */
7927                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7928                 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
7929         }
7930
7931         if (!CHIP_IS_E1x(bp)) {
7932                 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7933
7934                 /* Turn on a single ISR mode in IGU if driver is going to use
7935                  * INT#x or MSI
7936                  */
7937                 if (!(bp->flags & USING_MSIX_FLAG))
7938                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7939                 /*
7940                  * Timers workaround bug: function init part.
7941                  * Need to wait 20msec after initializing ILT,
7942                  * needed to make sure there are no requests in
7943                  * one of the PXP internal queues with "old" ILT addresses
7944                  */
7945                 msleep(20);
7946                 /*
7947                  * Master enable - Due to WB DMAE writes performed before this
7948                  * register is re-initialized as part of the regular function
7949                  * init
7950                  */
7951                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7952                 /* Enable the function in IGU */
7953                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7954         }
7955
7956         bp->dmae_ready = 1;
7957
7958         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7959
7960         if (!CHIP_IS_E1x(bp))
7961                 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7962
7963         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7964         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7965         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7966         bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7967         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7968         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7969         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7970         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7971         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7972         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7973         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7974         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7975         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7976
7977         if (!CHIP_IS_E1x(bp))
7978                 REG_WR(bp, QM_REG_PF_EN, 1);
7979
7980         if (!CHIP_IS_E1x(bp)) {
7981                 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7982                 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7983                 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7984                 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7985         }
7986         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7987
7988         bnx2x_init_block(bp, BLOCK_TM, init_phase);
7989         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7990         REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
7991
7992         bnx2x_iov_init_dq(bp);
7993
7994         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7995         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7996         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7997         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7998         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7999         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
8000         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
8001         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
8002         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
8003         if (!CHIP_IS_E1x(bp))
8004                 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
8005
8006         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
8007
8008         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
8009
8010         if (!CHIP_IS_E1x(bp))
8011                 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
8012
8013         if (IS_MF(bp)) {
8014                 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) {
8015                         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
8016                         REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8,
8017                                bp->mf_ov);
8018                 }
8019         }
8020
8021         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
8022
8023         /* HC init per function */
8024         if (bp->common.int_block == INT_BLOCK_HC) {
8025                 if (CHIP_IS_E1H(bp)) {
8026                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8027
8028                         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8029                         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8030                 }
8031                 bnx2x_init_block(bp, BLOCK_HC, init_phase);
8032
8033         } else {
8034                 int num_segs, sb_idx, prod_offset;
8035
8036                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8037
8038                 if (!CHIP_IS_E1x(bp)) {
8039                         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8040                         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8041                 }
8042
8043                 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
8044
8045                 if (!CHIP_IS_E1x(bp)) {
8046                         int dsb_idx = 0;
8047                         /**
8048                          * Producer memory:
8049                          * E2 mode: address 0-135 match to the mapping memory;
8050                          * 136 - PF0 default prod; 137 - PF1 default prod;
8051                          * 138 - PF2 default prod; 139 - PF3 default prod;
8052                          * 140 - PF0 attn prod;    141 - PF1 attn prod;
8053                          * 142 - PF2 attn prod;    143 - PF3 attn prod;
8054                          * 144-147 reserved.
8055                          *
8056                          * E1.5 mode - In backward compatible mode;
8057                          * for non default SB; each even line in the memory
8058                          * holds the U producer and each odd line hold
8059                          * the C producer. The first 128 producers are for
8060                          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
8061                          * producers are for the DSB for each PF.
8062                          * Each PF has five segments: (the order inside each
8063                          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
8064                          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
8065                          * 144-147 attn prods;
8066                          */
8067                         /* non-default-status-blocks */
8068                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8069                                 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
8070                         for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
8071                                 prod_offset = (bp->igu_base_sb + sb_idx) *
8072                                         num_segs;
8073
8074                                 for (i = 0; i < num_segs; i++) {
8075                                         addr = IGU_REG_PROD_CONS_MEMORY +
8076                                                         (prod_offset + i) * 4;
8077                                         REG_WR(bp, addr, 0);
8078                                 }
8079                                 /* send consumer update with value 0 */
8080                                 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
8081                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8082                                 bnx2x_igu_clear_sb(bp,
8083                                                    bp->igu_base_sb + sb_idx);
8084                         }
8085
8086                         /* default-status-blocks */
8087                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8088                                 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
8089
8090                         if (CHIP_MODE_IS_4_PORT(bp))
8091                                 dsb_idx = BP_FUNC(bp);
8092                         else
8093                                 dsb_idx = BP_VN(bp);
8094
8095                         prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
8096                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
8097                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
8098
8099                         /*
8100                          * igu prods come in chunks of E1HVN_MAX (4) -
8101                          * does not matters what is the current chip mode
8102                          */
8103                         for (i = 0; i < (num_segs * E1HVN_MAX);
8104                              i += E1HVN_MAX) {
8105                                 addr = IGU_REG_PROD_CONS_MEMORY +
8106                                                         (prod_offset + i)*4;
8107                                 REG_WR(bp, addr, 0);
8108                         }
8109                         /* send consumer update with 0 */
8110                         if (CHIP_INT_MODE_IS_BC(bp)) {
8111                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8112                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8113                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8114                                              CSTORM_ID, 0, IGU_INT_NOP, 1);
8115                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8116                                              XSTORM_ID, 0, IGU_INT_NOP, 1);
8117                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8118                                              TSTORM_ID, 0, IGU_INT_NOP, 1);
8119                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8120                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8121                         } else {
8122                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8123                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8124                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8125                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8126                         }
8127                         bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
8128
8129                         /* !!! These should become driver const once
8130                            rf-tool supports split-68 const */
8131                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8132                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8133                         REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8134                         REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8135                         REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8136                         REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8137                 }
8138         }
8139
8140         /* Reset PCIE errors for debug */
8141         REG_WR(bp, 0x2114, 0xffffffff);
8142         REG_WR(bp, 0x2120, 0xffffffff);
8143
8144         if (CHIP_IS_E1x(bp)) {
8145                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8146                 main_mem_base = HC_REG_MAIN_MEMORY +
8147                                 BP_PORT(bp) * (main_mem_size * 4);
8148                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8149                 main_mem_width = 8;
8150
8151                 val = REG_RD(bp, main_mem_prty_clr);
8152                 if (val)
8153                         DP(NETIF_MSG_HW,
8154                            "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8155                            val);
8156
8157                 /* Clear "false" parity errors in MSI-X table */
8158                 for (i = main_mem_base;
8159                      i < main_mem_base + main_mem_size * 4;
8160                      i += main_mem_width) {
8161                         bnx2x_read_dmae(bp, i, main_mem_width / 4);
8162                         bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8163                                          i, main_mem_width / 4);
8164                 }
8165                 /* Clear HC parity attention */
8166                 REG_RD(bp, main_mem_prty_clr);
8167         }
8168
8169 #ifdef BNX2X_STOP_ON_ERROR
8170         /* Enable STORMs SP logging */
8171         REG_WR8(bp, BAR_USTRORM_INTMEM +
8172                USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8173         REG_WR8(bp, BAR_TSTRORM_INTMEM +
8174                TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8175         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8176                CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8177         REG_WR8(bp, BAR_XSTRORM_INTMEM +
8178                XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8179 #endif
8180
8181         bnx2x_phy_probe(&bp->link_params);
8182
8183         return 0;
8184 }
8185
8186 void bnx2x_free_mem_cnic(struct bnx2x *bp)
8187 {
8188         bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8189
8190         if (!CHIP_IS_E1x(bp))
8191                 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8192                                sizeof(struct host_hc_status_block_e2));
8193         else
8194                 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8195                                sizeof(struct host_hc_status_block_e1x));
8196
8197         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8198 }
8199
8200 void bnx2x_free_mem(struct bnx2x *bp)
8201 {
8202         int i;
8203
8204         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8205                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8206
8207         if (IS_VF(bp))
8208                 return;
8209
8210         BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8211                        sizeof(struct host_sp_status_block));
8212
8213         BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
8214                        sizeof(struct bnx2x_slowpath));
8215
8216         for (i = 0; i < L2_ILT_LINES(bp); i++)
8217                 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8218                                bp->context[i].size);
8219         bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8220
8221         BNX2X_FREE(bp->ilt->lines);
8222
8223         BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
8224
8225         BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8226                        BCM_PAGE_SIZE * NUM_EQ_PAGES);
8227
8228         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8229
8230         bnx2x_iov_free_mem(bp);
8231 }
8232
8233 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
8234 {
8235         if (!CHIP_IS_E1x(bp)) {
8236                 /* size = the status block + ramrod buffers */
8237                 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8238                                                     sizeof(struct host_hc_status_block_e2));
8239                 if (!bp->cnic_sb.e2_sb)
8240                         goto alloc_mem_err;
8241         } else {
8242                 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8243                                                      sizeof(struct host_hc_status_block_e1x));
8244                 if (!bp->cnic_sb.e1x_sb)
8245                         goto alloc_mem_err;
8246         }
8247
8248         if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8249                 /* allocate searcher T2 table, as it wasn't allocated before */
8250                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8251                 if (!bp->t2)
8252                         goto alloc_mem_err;
8253         }
8254
8255         /* write address to which L5 should insert its values */
8256         bp->cnic_eth_dev.addr_drv_info_to_mcp =
8257                 &bp->slowpath->drv_info_to_mcp;
8258
8259         if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8260                 goto alloc_mem_err;
8261
8262         return 0;
8263
8264 alloc_mem_err:
8265         bnx2x_free_mem_cnic(bp);
8266         BNX2X_ERR("Can't allocate memory\n");
8267         return -ENOMEM;
8268 }
8269
8270 int bnx2x_alloc_mem(struct bnx2x *bp)
8271 {
8272         int i, allocated, context_size;
8273
8274         if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8275                 /* allocate searcher T2 table */
8276                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8277                 if (!bp->t2)
8278                         goto alloc_mem_err;
8279         }
8280
8281         bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8282                                              sizeof(struct host_sp_status_block));
8283         if (!bp->def_status_blk)
8284                 goto alloc_mem_err;
8285
8286         bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8287                                        sizeof(struct bnx2x_slowpath));
8288         if (!bp->slowpath)
8289                 goto alloc_mem_err;
8290
8291         /* Allocate memory for CDU context:
8292          * This memory is allocated separately and not in the generic ILT
8293          * functions because CDU differs in few aspects:
8294          * 1. There are multiple entities allocating memory for context -
8295          * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8296          * its own ILT lines.
8297          * 2. Since CDU page-size is not a single 4KB page (which is the case
8298          * for the other ILT clients), to be efficient we want to support
8299          * allocation of sub-page-size in the last entry.
8300          * 3. Context pointers are used by the driver to pass to FW / update
8301          * the context (for the other ILT clients the pointers are used just to
8302          * free the memory during unload).
8303          */
8304         context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
8305
8306         for (i = 0, allocated = 0; allocated < context_size; i++) {
8307                 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8308                                           (context_size - allocated));
8309                 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8310                                                       bp->context[i].size);
8311                 if (!bp->context[i].vcxt)
8312                         goto alloc_mem_err;
8313                 allocated += bp->context[i].size;
8314         }
8315         bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8316                                  GFP_KERNEL);
8317         if (!bp->ilt->lines)
8318                 goto alloc_mem_err;
8319
8320         if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8321                 goto alloc_mem_err;
8322
8323         if (bnx2x_iov_alloc_mem(bp))
8324                 goto alloc_mem_err;
8325
8326         /* Slow path ring */
8327         bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8328         if (!bp->spq)
8329                 goto alloc_mem_err;
8330
8331         /* EQ */
8332         bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8333                                       BCM_PAGE_SIZE * NUM_EQ_PAGES);
8334         if (!bp->eq_ring)
8335                 goto alloc_mem_err;
8336
8337         return 0;
8338
8339 alloc_mem_err:
8340         bnx2x_free_mem(bp);
8341         BNX2X_ERR("Can't allocate memory\n");
8342         return -ENOMEM;
8343 }
8344
8345 /*
8346  * Init service functions
8347  */
8348
8349 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8350                       struct bnx2x_vlan_mac_obj *obj, bool set,
8351                       int mac_type, unsigned long *ramrod_flags)
8352 {
8353         int rc;
8354         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8355
8356         memset(&ramrod_param, 0, sizeof(ramrod_param));
8357
8358         /* Fill general parameters */
8359         ramrod_param.vlan_mac_obj = obj;
8360         ramrod_param.ramrod_flags = *ramrod_flags;
8361
8362         /* Fill a user request section if needed */
8363         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8364                 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
8365
8366                 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
8367
8368                 /* Set the command: ADD or DEL */
8369                 if (set)
8370                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8371                 else
8372                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8373         }
8374
8375         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8376
8377         if (rc == -EEXIST) {
8378                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8379                 /* do not treat adding same MAC as error */
8380                 rc = 0;
8381         } else if (rc < 0)
8382                 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8383
8384         return rc;
8385 }
8386
8387 int bnx2x_del_all_macs(struct bnx2x *bp,
8388                        struct bnx2x_vlan_mac_obj *mac_obj,
8389                        int mac_type, bool wait_for_comp)
8390 {
8391         int rc;
8392         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8393
8394         /* Wait for completion of requested */
8395         if (wait_for_comp)
8396                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8397
8398         /* Set the mac type of addresses we want to clear */
8399         __set_bit(mac_type, &vlan_mac_flags);
8400
8401         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8402         if (rc < 0)
8403                 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8404
8405         return rc;
8406 }
8407
8408 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8409 {
8410         if (IS_PF(bp)) {
8411                 unsigned long ramrod_flags = 0;
8412
8413                 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8414                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8415                 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8416                                          &bp->sp_objs->mac_obj, set,
8417                                          BNX2X_ETH_MAC, &ramrod_flags);
8418         } else { /* vf */
8419                 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8420                                              bp->fp->index, true);
8421         }
8422 }
8423
8424 int bnx2x_setup_leading(struct bnx2x *bp)
8425 {
8426         if (IS_PF(bp))
8427                 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8428         else /* VF */
8429                 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
8430 }
8431
8432 /**
8433  * bnx2x_set_int_mode - configure interrupt mode
8434  *
8435  * @bp:         driver handle
8436  *
8437  * In case of MSI-X it will also try to enable MSI-X.
8438  */
8439 int bnx2x_set_int_mode(struct bnx2x *bp)
8440 {
8441         int rc = 0;
8442
8443         if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8444                 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8445                 return -EINVAL;
8446         }
8447
8448         switch (int_mode) {
8449         case BNX2X_INT_MODE_MSIX:
8450                 /* attempt to enable msix */
8451                 rc = bnx2x_enable_msix(bp);
8452
8453                 /* msix attained */
8454                 if (!rc)
8455                         return 0;
8456
8457                 /* vfs use only msix */
8458                 if (rc && IS_VF(bp))
8459                         return rc;
8460
8461                 /* failed to enable multiple MSI-X */
8462                 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8463                                bp->num_queues,
8464                                1 + bp->num_cnic_queues);
8465
8466                 /* falling through... */
8467         case BNX2X_INT_MODE_MSI:
8468                 bnx2x_enable_msi(bp);
8469
8470                 /* falling through... */
8471         case BNX2X_INT_MODE_INTX:
8472                 bp->num_ethernet_queues = 1;
8473                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8474                 BNX2X_DEV_INFO("set number of queues to 1\n");
8475                 break;
8476         default:
8477                 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8478                 return -EINVAL;
8479         }
8480         return 0;
8481 }
8482
8483 /* must be called prior to any HW initializations */
8484 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8485 {
8486         if (IS_SRIOV(bp))
8487                 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8488         return L2_ILT_LINES(bp);
8489 }
8490
8491 void bnx2x_ilt_set_info(struct bnx2x *bp)
8492 {
8493         struct ilt_client_info *ilt_client;
8494         struct bnx2x_ilt *ilt = BP_ILT(bp);
8495         u16 line = 0;
8496
8497         ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8498         DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8499
8500         /* CDU */
8501         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8502         ilt_client->client_num = ILT_CLIENT_CDU;
8503         ilt_client->page_size = CDU_ILT_PAGE_SZ;
8504         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8505         ilt_client->start = line;
8506         line += bnx2x_cid_ilt_lines(bp);
8507
8508         if (CNIC_SUPPORT(bp))
8509                 line += CNIC_ILT_LINES;
8510         ilt_client->end = line - 1;
8511
8512         DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8513            ilt_client->start,
8514            ilt_client->end,
8515            ilt_client->page_size,
8516            ilt_client->flags,
8517            ilog2(ilt_client->page_size >> 12));
8518
8519         /* QM */
8520         if (QM_INIT(bp->qm_cid_count)) {
8521                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8522                 ilt_client->client_num = ILT_CLIENT_QM;
8523                 ilt_client->page_size = QM_ILT_PAGE_SZ;
8524                 ilt_client->flags = 0;
8525                 ilt_client->start = line;
8526
8527                 /* 4 bytes for each cid */
8528                 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8529                                                          QM_ILT_PAGE_SZ);
8530
8531                 ilt_client->end = line - 1;
8532
8533                 DP(NETIF_MSG_IFUP,
8534                    "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8535                    ilt_client->start,
8536                    ilt_client->end,
8537                    ilt_client->page_size,
8538                    ilt_client->flags,
8539                    ilog2(ilt_client->page_size >> 12));
8540         }
8541
8542         if (CNIC_SUPPORT(bp)) {
8543                 /* SRC */
8544                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8545                 ilt_client->client_num = ILT_CLIENT_SRC;
8546                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8547                 ilt_client->flags = 0;
8548                 ilt_client->start = line;
8549                 line += SRC_ILT_LINES;
8550                 ilt_client->end = line - 1;
8551
8552                 DP(NETIF_MSG_IFUP,
8553                    "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8554                    ilt_client->start,
8555                    ilt_client->end,
8556                    ilt_client->page_size,
8557                    ilt_client->flags,
8558                    ilog2(ilt_client->page_size >> 12));
8559
8560                 /* TM */
8561                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8562                 ilt_client->client_num = ILT_CLIENT_TM;
8563                 ilt_client->page_size = TM_ILT_PAGE_SZ;
8564                 ilt_client->flags = 0;
8565                 ilt_client->start = line;
8566                 line += TM_ILT_LINES;
8567                 ilt_client->end = line - 1;
8568
8569                 DP(NETIF_MSG_IFUP,
8570                    "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8571                    ilt_client->start,
8572                    ilt_client->end,
8573                    ilt_client->page_size,
8574                    ilt_client->flags,
8575                    ilog2(ilt_client->page_size >> 12));
8576         }
8577
8578         BUG_ON(line > ILT_MAX_LINES);
8579 }
8580
8581 /**
8582  * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8583  *
8584  * @bp:                 driver handle
8585  * @fp:                 pointer to fastpath
8586  * @init_params:        pointer to parameters structure
8587  *
8588  * parameters configured:
8589  *      - HC configuration
8590  *      - Queue's CDU context
8591  */
8592 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8593         struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8594 {
8595         u8 cos;
8596         int cxt_index, cxt_offset;
8597
8598         /* FCoE Queue uses Default SB, thus has no HC capabilities */
8599         if (!IS_FCOE_FP(fp)) {
8600                 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8601                 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8602
8603                 /* If HC is supported, enable host coalescing in the transition
8604                  * to INIT state.
8605                  */
8606                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8607                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8608
8609                 /* HC rate */
8610                 init_params->rx.hc_rate = bp->rx_ticks ?
8611                         (1000000 / bp->rx_ticks) : 0;
8612                 init_params->tx.hc_rate = bp->tx_ticks ?
8613                         (1000000 / bp->tx_ticks) : 0;
8614
8615                 /* FW SB ID */
8616                 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8617                         fp->fw_sb_id;
8618
8619                 /*
8620                  * CQ index among the SB indices: FCoE clients uses the default
8621                  * SB, therefore it's different.
8622                  */
8623                 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8624                 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8625         }
8626
8627         /* set maximum number of COSs supported by this queue */
8628         init_params->max_cos = fp->max_cos;
8629
8630         DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8631             fp->index, init_params->max_cos);
8632
8633         /* set the context pointers queue object */
8634         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8635                 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8636                 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8637                                 ILT_PAGE_CIDS);
8638                 init_params->cxts[cos] =
8639                         &bp->context[cxt_index].vcxt[cxt_offset].eth;
8640         }
8641 }
8642
8643 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8644                         struct bnx2x_queue_state_params *q_params,
8645                         struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8646                         int tx_index, bool leading)
8647 {
8648         memset(tx_only_params, 0, sizeof(*tx_only_params));
8649
8650         /* Set the command */
8651         q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8652
8653         /* Set tx-only QUEUE flags: don't zero statistics */
8654         tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8655
8656         /* choose the index of the cid to send the slow path on */
8657         tx_only_params->cid_index = tx_index;
8658
8659         /* Set general TX_ONLY_SETUP parameters */
8660         bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8661
8662         /* Set Tx TX_ONLY_SETUP parameters */
8663         bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8664
8665         DP(NETIF_MSG_IFUP,
8666            "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8667            tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8668            q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8669            tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8670
8671         /* send the ramrod */
8672         return bnx2x_queue_state_change(bp, q_params);
8673 }
8674
8675 /**
8676  * bnx2x_setup_queue - setup queue
8677  *
8678  * @bp:         driver handle
8679  * @fp:         pointer to fastpath
8680  * @leading:    is leading
8681  *
8682  * This function performs 2 steps in a Queue state machine
8683  *      actually: 1) RESET->INIT 2) INIT->SETUP
8684  */
8685
8686 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8687                        bool leading)
8688 {
8689         struct bnx2x_queue_state_params q_params = {NULL};
8690         struct bnx2x_queue_setup_params *setup_params =
8691                                                 &q_params.params.setup;
8692         struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8693                                                 &q_params.params.tx_only;
8694         int rc;
8695         u8 tx_index;
8696
8697         DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8698
8699         /* reset IGU state skip FCoE L2 queue */
8700         if (!IS_FCOE_FP(fp))
8701                 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8702                              IGU_INT_ENABLE, 0);
8703
8704         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8705         /* We want to wait for completion in this context */
8706         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8707
8708         /* Prepare the INIT parameters */
8709         bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8710
8711         /* Set the command */
8712         q_params.cmd = BNX2X_Q_CMD_INIT;
8713
8714         /* Change the state to INIT */
8715         rc = bnx2x_queue_state_change(bp, &q_params);
8716         if (rc) {
8717                 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8718                 return rc;
8719         }
8720
8721         DP(NETIF_MSG_IFUP, "init complete\n");
8722
8723         /* Now move the Queue to the SETUP state... */
8724         memset(setup_params, 0, sizeof(*setup_params));
8725
8726         /* Set QUEUE flags */
8727         setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8728
8729         /* Set general SETUP parameters */
8730         bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8731                                 FIRST_TX_COS_INDEX);
8732
8733         bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8734                             &setup_params->rxq_params);
8735
8736         bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8737                            FIRST_TX_COS_INDEX);
8738
8739         /* Set the command */
8740         q_params.cmd = BNX2X_Q_CMD_SETUP;
8741
8742         if (IS_FCOE_FP(fp))
8743                 bp->fcoe_init = true;
8744
8745         /* Change the state to SETUP */
8746         rc = bnx2x_queue_state_change(bp, &q_params);
8747         if (rc) {
8748                 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8749                 return rc;
8750         }
8751
8752         /* loop through the relevant tx-only indices */
8753         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8754               tx_index < fp->max_cos;
8755               tx_index++) {
8756
8757                 /* prepare and send tx-only ramrod*/
8758                 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8759                                           tx_only_params, tx_index, leading);
8760                 if (rc) {
8761                         BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8762                                   fp->index, tx_index);
8763                         return rc;
8764                 }
8765         }
8766
8767         return rc;
8768 }
8769
8770 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8771 {
8772         struct bnx2x_fastpath *fp = &bp->fp[index];
8773         struct bnx2x_fp_txdata *txdata;
8774         struct bnx2x_queue_state_params q_params = {NULL};
8775         int rc, tx_index;
8776
8777         DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8778
8779         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8780         /* We want to wait for completion in this context */
8781         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8782
8783         /* close tx-only connections */
8784         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8785              tx_index < fp->max_cos;
8786              tx_index++){
8787
8788                 /* ascertain this is a normal queue*/
8789                 txdata = fp->txdata_ptr[tx_index];
8790
8791                 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8792                                                         txdata->txq_index);
8793
8794                 /* send halt terminate on tx-only connection */
8795                 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8796                 memset(&q_params.params.terminate, 0,
8797                        sizeof(q_params.params.terminate));
8798                 q_params.params.terminate.cid_index = tx_index;
8799
8800                 rc = bnx2x_queue_state_change(bp, &q_params);
8801                 if (rc)
8802                         return rc;
8803
8804                 /* send halt terminate on tx-only connection */
8805                 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8806                 memset(&q_params.params.cfc_del, 0,
8807                        sizeof(q_params.params.cfc_del));
8808                 q_params.params.cfc_del.cid_index = tx_index;
8809                 rc = bnx2x_queue_state_change(bp, &q_params);
8810                 if (rc)
8811                         return rc;
8812         }
8813         /* Stop the primary connection: */
8814         /* ...halt the connection */
8815         q_params.cmd = BNX2X_Q_CMD_HALT;
8816         rc = bnx2x_queue_state_change(bp, &q_params);
8817         if (rc)
8818                 return rc;
8819
8820         /* ...terminate the connection */
8821         q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8822         memset(&q_params.params.terminate, 0,
8823                sizeof(q_params.params.terminate));
8824         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8825         rc = bnx2x_queue_state_change(bp, &q_params);
8826         if (rc)
8827                 return rc;
8828         /* ...delete cfc entry */
8829         q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8830         memset(&q_params.params.cfc_del, 0,
8831                sizeof(q_params.params.cfc_del));
8832         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8833         return bnx2x_queue_state_change(bp, &q_params);
8834 }
8835
8836 static void bnx2x_reset_func(struct bnx2x *bp)
8837 {
8838         int port = BP_PORT(bp);
8839         int func = BP_FUNC(bp);
8840         int i;
8841
8842         /* Disable the function in the FW */
8843         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8844         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8845         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8846         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8847
8848         /* FP SBs */
8849         for_each_eth_queue(bp, i) {
8850                 struct bnx2x_fastpath *fp = &bp->fp[i];
8851                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8852                            CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8853                            SB_DISABLED);
8854         }
8855
8856         if (CNIC_LOADED(bp))
8857                 /* CNIC SB */
8858                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8859                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8860                         (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8861
8862         /* SP SB */
8863         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8864                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8865                 SB_DISABLED);
8866
8867         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8868                 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8869                        0);
8870
8871         /* Configure IGU */
8872         if (bp->common.int_block == INT_BLOCK_HC) {
8873                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8874                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8875         } else {
8876                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8877                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8878         }
8879
8880         if (CNIC_LOADED(bp)) {
8881                 /* Disable Timer scan */
8882                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8883                 /*
8884                  * Wait for at least 10ms and up to 2 second for the timers
8885                  * scan to complete
8886                  */
8887                 for (i = 0; i < 200; i++) {
8888                         usleep_range(10000, 20000);
8889                         if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8890                                 break;
8891                 }
8892         }
8893         /* Clear ILT */
8894         bnx2x_clear_func_ilt(bp, func);
8895
8896         /* Timers workaround bug for E2: if this is vnic-3,
8897          * we need to set the entire ilt range for this timers.
8898          */
8899         if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8900                 struct ilt_client_info ilt_cli;
8901                 /* use dummy TM client */
8902                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8903                 ilt_cli.start = 0;
8904                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8905                 ilt_cli.client_num = ILT_CLIENT_TM;
8906
8907                 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8908         }
8909
8910         /* this assumes that reset_port() called before reset_func()*/
8911         if (!CHIP_IS_E1x(bp))
8912                 bnx2x_pf_disable(bp);
8913
8914         bp->dmae_ready = 0;
8915 }
8916
8917 static void bnx2x_reset_port(struct bnx2x *bp)
8918 {
8919         int port = BP_PORT(bp);
8920         u32 val;
8921
8922         /* Reset physical Link */
8923         bnx2x__link_reset(bp);
8924
8925         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8926
8927         /* Do not rcv packets to BRB */
8928         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8929         /* Do not direct rcv packets that are not for MCP to the BRB */
8930         REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8931                            NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8932
8933         /* Configure AEU */
8934         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8935
8936         msleep(100);
8937         /* Check for BRB port occupancy */
8938         val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8939         if (val)
8940                 DP(NETIF_MSG_IFDOWN,
8941                    "BRB1 is not empty  %d blocks are occupied\n", val);
8942
8943         /* TODO: Close Doorbell port? */
8944 }
8945
8946 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8947 {
8948         struct bnx2x_func_state_params func_params = {NULL};
8949
8950         /* Prepare parameters for function state transitions */
8951         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8952
8953         func_params.f_obj = &bp->func_obj;
8954         func_params.cmd = BNX2X_F_CMD_HW_RESET;
8955
8956         func_params.params.hw_init.load_phase = load_code;
8957
8958         return bnx2x_func_state_change(bp, &func_params);
8959 }
8960
8961 static int bnx2x_func_stop(struct bnx2x *bp)
8962 {
8963         struct bnx2x_func_state_params func_params = {NULL};
8964         int rc;
8965
8966         /* Prepare parameters for function state transitions */
8967         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8968         func_params.f_obj = &bp->func_obj;
8969         func_params.cmd = BNX2X_F_CMD_STOP;
8970
8971         /*
8972          * Try to stop the function the 'good way'. If fails (in case
8973          * of a parity error during bnx2x_chip_cleanup()) and we are
8974          * not in a debug mode, perform a state transaction in order to
8975          * enable further HW_RESET transaction.
8976          */
8977         rc = bnx2x_func_state_change(bp, &func_params);
8978         if (rc) {
8979 #ifdef BNX2X_STOP_ON_ERROR
8980                 return rc;
8981 #else
8982                 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8983                 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8984                 return bnx2x_func_state_change(bp, &func_params);
8985 #endif
8986         }
8987
8988         return 0;
8989 }
8990
8991 /**
8992  * bnx2x_send_unload_req - request unload mode from the MCP.
8993  *
8994  * @bp:                 driver handle
8995  * @unload_mode:        requested function's unload mode
8996  *
8997  * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8998  */
8999 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
9000 {
9001         u32 reset_code = 0;
9002         int port = BP_PORT(bp);
9003
9004         /* Select the UNLOAD request mode */
9005         if (unload_mode == UNLOAD_NORMAL)
9006                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9007
9008         else if (bp->flags & NO_WOL_FLAG)
9009                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
9010
9011         else if (bp->wol) {
9012                 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
9013                 u8 *mac_addr = bp->dev->dev_addr;
9014                 struct pci_dev *pdev = bp->pdev;
9015                 u32 val;
9016                 u16 pmc;
9017
9018                 /* The mac address is written to entries 1-4 to
9019                  * preserve entry 0 which is used by the PMF
9020                  */
9021                 u8 entry = (BP_VN(bp) + 1)*8;
9022
9023                 val = (mac_addr[0] << 8) | mac_addr[1];
9024                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
9025
9026                 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
9027                       (mac_addr[4] << 8) | mac_addr[5];
9028                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
9029
9030                 /* Enable the PME and clear the status */
9031                 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
9032                 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
9033                 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
9034
9035                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
9036
9037         } else
9038                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9039
9040         /* Send the request to the MCP */
9041         if (!BP_NOMCP(bp))
9042                 reset_code = bnx2x_fw_command(bp, reset_code, 0);
9043         else {
9044                 int path = BP_PATH(bp);
9045
9046                 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d]      %d, %d, %d\n",
9047                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9048                    bnx2x_load_count[path][2]);
9049                 bnx2x_load_count[path][0]--;
9050                 bnx2x_load_count[path][1 + port]--;
9051                 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d]  %d, %d, %d\n",
9052                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9053                    bnx2x_load_count[path][2]);
9054                 if (bnx2x_load_count[path][0] == 0)
9055                         reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
9056                 else if (bnx2x_load_count[path][1 + port] == 0)
9057                         reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
9058                 else
9059                         reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
9060         }
9061
9062         return reset_code;
9063 }
9064
9065 /**
9066  * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
9067  *
9068  * @bp:         driver handle
9069  * @keep_link:          true iff link should be kept up
9070  */
9071 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
9072 {
9073         u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
9074
9075         /* Report UNLOAD_DONE to MCP */
9076         if (!BP_NOMCP(bp))
9077                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
9078 }
9079
9080 static int bnx2x_func_wait_started(struct bnx2x *bp)
9081 {
9082         int tout = 50;
9083         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
9084
9085         if (!bp->port.pmf)
9086                 return 0;
9087
9088         /*
9089          * (assumption: No Attention from MCP at this stage)
9090          * PMF probably in the middle of TX disable/enable transaction
9091          * 1. Sync IRS for default SB
9092          * 2. Sync SP queue - this guarantees us that attention handling started
9093          * 3. Wait, that TX disable/enable transaction completes
9094          *
9095          * 1+2 guarantee that if DCBx attention was scheduled it already changed
9096          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9097          * received completion for the transaction the state is TX_STOPPED.
9098          * State will return to STARTED after completion of TX_STOPPED-->STARTED
9099          * transaction.
9100          */
9101
9102         /* make sure default SB ISR is done */
9103         if (msix)
9104                 synchronize_irq(bp->msix_table[0].vector);
9105         else
9106                 synchronize_irq(bp->pdev->irq);
9107
9108         flush_workqueue(bnx2x_wq);
9109         flush_workqueue(bnx2x_iov_wq);
9110
9111         while (bnx2x_func_get_state(bp, &bp->func_obj) !=
9112                                 BNX2X_F_STATE_STARTED && tout--)
9113                 msleep(20);
9114
9115         if (bnx2x_func_get_state(bp, &bp->func_obj) !=
9116                                                 BNX2X_F_STATE_STARTED) {
9117 #ifdef BNX2X_STOP_ON_ERROR
9118                 BNX2X_ERR("Wrong function state\n");
9119                 return -EBUSY;
9120 #else
9121                 /*
9122                  * Failed to complete the transaction in a "good way"
9123                  * Force both transactions with CLR bit
9124                  */
9125                 struct bnx2x_func_state_params func_params = {NULL};
9126
9127                 DP(NETIF_MSG_IFDOWN,
9128                    "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
9129
9130                 func_params.f_obj = &bp->func_obj;
9131                 __set_bit(RAMROD_DRV_CLR_ONLY,
9132                                         &func_params.ramrod_flags);
9133
9134                 /* STARTED-->TX_ST0PPED */
9135                 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9136                 bnx2x_func_state_change(bp, &func_params);
9137
9138                 /* TX_ST0PPED-->STARTED */
9139                 func_params.cmd = BNX2X_F_CMD_TX_START;
9140                 return bnx2x_func_state_change(bp, &func_params);
9141 #endif
9142         }
9143
9144         return 0;
9145 }
9146
9147 static void bnx2x_disable_ptp(struct bnx2x *bp)
9148 {
9149         int port = BP_PORT(bp);
9150
9151         /* Disable sending PTP packets to host */
9152         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
9153                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
9154
9155         /* Reset PTP event detection rules */
9156         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
9157                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
9158         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
9159                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
9160         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
9161                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
9162         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
9163                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
9164
9165         /* Disable the PTP feature */
9166         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
9167                NIG_REG_P0_PTP_EN, 0x0);
9168 }
9169
9170 /* Called during unload, to stop PTP-related stuff */
9171 void bnx2x_stop_ptp(struct bnx2x *bp)
9172 {
9173         /* Cancel PTP work queue. Should be done after the Tx queues are
9174          * drained to prevent additional scheduling.
9175          */
9176         cancel_work_sync(&bp->ptp_task);
9177
9178         if (bp->ptp_tx_skb) {
9179                 dev_kfree_skb_any(bp->ptp_tx_skb);
9180                 bp->ptp_tx_skb = NULL;
9181         }
9182
9183         /* Disable PTP in HW */
9184         bnx2x_disable_ptp(bp);
9185
9186         DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
9187 }
9188
9189 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
9190 {
9191         int port = BP_PORT(bp);
9192         int i, rc = 0;
9193         u8 cos;
9194         struct bnx2x_mcast_ramrod_params rparam = {NULL};
9195         u32 reset_code;
9196
9197         /* Wait until tx fastpath tasks complete */
9198         for_each_tx_queue(bp, i) {
9199                 struct bnx2x_fastpath *fp = &bp->fp[i];
9200
9201                 for_each_cos_in_tx_queue(fp, cos)
9202                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
9203 #ifdef BNX2X_STOP_ON_ERROR
9204                 if (rc)
9205                         return;
9206 #endif
9207         }
9208
9209         /* Give HW time to discard old tx messages */
9210         usleep_range(1000, 2000);
9211
9212         /* Clean all ETH MACs */
9213         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9214                                 false);
9215         if (rc < 0)
9216                 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9217
9218         /* Clean up UC list  */
9219         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
9220                                 true);
9221         if (rc < 0)
9222                 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9223                           rc);
9224
9225         /* Disable LLH */
9226         if (!CHIP_IS_E1(bp))
9227                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9228
9229         /* Set "drop all" (stop Rx).
9230          * We need to take a netif_addr_lock() here in order to prevent
9231          * a race between the completion code and this code.
9232          */
9233         netif_addr_lock_bh(bp->dev);
9234         /* Schedule the rx_mode command */
9235         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9236                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9237         else
9238                 bnx2x_set_storm_rx_mode(bp);
9239
9240         /* Cleanup multicast configuration */
9241         rparam.mcast_obj = &bp->mcast_obj;
9242         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9243         if (rc < 0)
9244                 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9245
9246         netif_addr_unlock_bh(bp->dev);
9247
9248         bnx2x_iov_chip_cleanup(bp);
9249
9250         /*
9251          * Send the UNLOAD_REQUEST to the MCP. This will return if
9252          * this function should perform FUNC, PORT or COMMON HW
9253          * reset.
9254          */
9255         reset_code = bnx2x_send_unload_req(bp, unload_mode);
9256
9257         /*
9258          * (assumption: No Attention from MCP at this stage)
9259          * PMF probably in the middle of TX disable/enable transaction
9260          */
9261         rc = bnx2x_func_wait_started(bp);
9262         if (rc) {
9263                 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9264 #ifdef BNX2X_STOP_ON_ERROR
9265                 return;
9266 #endif
9267         }
9268
9269         /* Close multi and leading connections
9270          * Completions for ramrods are collected in a synchronous way
9271          */
9272         for_each_eth_queue(bp, i)
9273                 if (bnx2x_stop_queue(bp, i))
9274 #ifdef BNX2X_STOP_ON_ERROR
9275                         return;
9276 #else
9277                         goto unload_error;
9278 #endif
9279
9280         if (CNIC_LOADED(bp)) {
9281                 for_each_cnic_queue(bp, i)
9282                         if (bnx2x_stop_queue(bp, i))
9283 #ifdef BNX2X_STOP_ON_ERROR
9284                                 return;
9285 #else
9286                                 goto unload_error;
9287 #endif
9288         }
9289
9290         /* If SP settings didn't get completed so far - something
9291          * very wrong has happen.
9292          */
9293         if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9294                 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
9295
9296 #ifndef BNX2X_STOP_ON_ERROR
9297 unload_error:
9298 #endif
9299         rc = bnx2x_func_stop(bp);
9300         if (rc) {
9301                 BNX2X_ERR("Function stop failed!\n");
9302 #ifdef BNX2X_STOP_ON_ERROR
9303                 return;
9304 #endif
9305         }
9306
9307         /* stop_ptp should be after the Tx queues are drained to prevent
9308          * scheduling to the cancelled PTP work queue. It should also be after
9309          * function stop ramrod is sent, since as part of this ramrod FW access
9310          * PTP registers.
9311          */
9312         bnx2x_stop_ptp(bp);
9313
9314         /* Disable HW interrupts, NAPI */
9315         bnx2x_netif_stop(bp, 1);
9316         /* Delete all NAPI objects */
9317         bnx2x_del_all_napi(bp);
9318         if (CNIC_LOADED(bp))
9319                 bnx2x_del_all_napi_cnic(bp);
9320
9321         /* Release IRQs */
9322         bnx2x_free_irq(bp);
9323
9324         /* Reset the chip */
9325         rc = bnx2x_reset_hw(bp, reset_code);
9326         if (rc)
9327                 BNX2X_ERR("HW_RESET failed\n");
9328
9329         /* Report UNLOAD_DONE to MCP */
9330         bnx2x_send_unload_done(bp, keep_link);
9331 }
9332
9333 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
9334 {
9335         u32 val;
9336
9337         DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
9338
9339         if (CHIP_IS_E1(bp)) {
9340                 int port = BP_PORT(bp);
9341                 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9342                         MISC_REG_AEU_MASK_ATTN_FUNC_0;
9343
9344                 val = REG_RD(bp, addr);
9345                 val &= ~(0x300);
9346                 REG_WR(bp, addr, val);
9347         } else {
9348                 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9349                 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9350                          MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9351                 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9352         }
9353 }
9354
9355 /* Close gates #2, #3 and #4: */
9356 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9357 {
9358         u32 val;
9359
9360         /* Gates #2 and #4a are closed/opened for "not E1" only */
9361         if (!CHIP_IS_E1(bp)) {
9362                 /* #4 */
9363                 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
9364                 /* #2 */
9365                 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
9366         }
9367
9368         /* #3 */
9369         if (CHIP_IS_E1x(bp)) {
9370                 /* Prevent interrupts from HC on both ports */
9371                 val = REG_RD(bp, HC_REG_CONFIG_1);
9372                 REG_WR(bp, HC_REG_CONFIG_1,
9373                        (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9374                        (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9375
9376                 val = REG_RD(bp, HC_REG_CONFIG_0);
9377                 REG_WR(bp, HC_REG_CONFIG_0,
9378                        (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9379                        (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9380         } else {
9381                 /* Prevent incoming interrupts in IGU */
9382                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9383
9384                 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9385                        (!close) ?
9386                        (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9387                        (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9388         }
9389
9390         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
9391                 close ? "closing" : "opening");
9392         mmiowb();
9393 }
9394
9395 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
9396
9397 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9398 {
9399         /* Do some magic... */
9400         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9401         *magic_val = val & SHARED_MF_CLP_MAGIC;
9402         MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9403 }
9404
9405 /**
9406  * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9407  *
9408  * @bp:         driver handle
9409  * @magic_val:  old value of the `magic' bit.
9410  */
9411 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9412 {
9413         /* Restore the `magic' bit value... */
9414         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9415         MF_CFG_WR(bp, shared_mf_config.clp_mb,
9416                 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9417 }
9418
9419 /**
9420  * bnx2x_reset_mcp_prep - prepare for MCP reset.
9421  *
9422  * @bp:         driver handle
9423  * @magic_val:  old value of 'magic' bit.
9424  *
9425  * Takes care of CLP configurations.
9426  */
9427 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9428 {
9429         u32 shmem;
9430         u32 validity_offset;
9431
9432         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
9433
9434         /* Set `magic' bit in order to save MF config */
9435         if (!CHIP_IS_E1(bp))
9436                 bnx2x_clp_reset_prep(bp, magic_val);
9437
9438         /* Get shmem offset */
9439         shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9440         validity_offset =
9441                 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9442
9443         /* Clear validity map flags */
9444         if (shmem > 0)
9445                 REG_WR(bp, shmem + validity_offset, 0);
9446 }
9447
9448 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
9449 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
9450
9451 /**
9452  * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9453  *
9454  * @bp: driver handle
9455  */
9456 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9457 {
9458         /* special handling for emulation and FPGA,
9459            wait 10 times longer */
9460         if (CHIP_REV_IS_SLOW(bp))
9461                 msleep(MCP_ONE_TIMEOUT*10);
9462         else
9463                 msleep(MCP_ONE_TIMEOUT);
9464 }
9465
9466 /*
9467  * initializes bp->common.shmem_base and waits for validity signature to appear
9468  */
9469 static int bnx2x_init_shmem(struct bnx2x *bp)
9470 {
9471         int cnt = 0;
9472         u32 val = 0;
9473
9474         do {
9475                 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9476                 if (bp->common.shmem_base) {
9477                         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9478                         if (val & SHR_MEM_VALIDITY_MB)
9479                                 return 0;
9480                 }
9481
9482                 bnx2x_mcp_wait_one(bp);
9483
9484         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9485
9486         BNX2X_ERR("BAD MCP validity signature\n");
9487
9488         return -ENODEV;
9489 }
9490
9491 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9492 {
9493         int rc = bnx2x_init_shmem(bp);
9494
9495         /* Restore the `magic' bit value */
9496         if (!CHIP_IS_E1(bp))
9497                 bnx2x_clp_reset_done(bp, magic_val);
9498
9499         return rc;
9500 }
9501
9502 static void bnx2x_pxp_prep(struct bnx2x *bp)
9503 {
9504         if (!CHIP_IS_E1(bp)) {
9505                 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9506                 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9507                 mmiowb();
9508         }
9509 }
9510
9511 /*
9512  * Reset the whole chip except for:
9513  *      - PCIE core
9514  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9515  *              one reset bit)
9516  *      - IGU
9517  *      - MISC (including AEU)
9518  *      - GRC
9519  *      - RBCN, RBCP
9520  */
9521 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9522 {
9523         u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9524         u32 global_bits2, stay_reset2;
9525
9526         /*
9527          * Bits that have to be set in reset_mask2 if we want to reset 'global'
9528          * (per chip) blocks.
9529          */
9530         global_bits2 =
9531                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9532                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9533
9534         /* Don't reset the following blocks.
9535          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9536          *            reset, as in 4 port device they might still be owned
9537          *            by the MCP (there is only one leader per path).
9538          */
9539         not_reset_mask1 =
9540                 MISC_REGISTERS_RESET_REG_1_RST_HC |
9541                 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9542                 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9543
9544         not_reset_mask2 =
9545                 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9546                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9547                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9548                 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9549                 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9550                 MISC_REGISTERS_RESET_REG_2_RST_GRC  |
9551                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9552                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9553                 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9554                 MISC_REGISTERS_RESET_REG_2_PGLC |
9555                 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9556                 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9557                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9558                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9559                 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9560                 MISC_REGISTERS_RESET_REG_2_UMAC1;
9561
9562         /*
9563          * Keep the following blocks in reset:
9564          *  - all xxMACs are handled by the bnx2x_link code.
9565          */
9566         stay_reset2 =
9567                 MISC_REGISTERS_RESET_REG_2_XMAC |
9568                 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9569
9570         /* Full reset masks according to the chip */
9571         reset_mask1 = 0xffffffff;
9572
9573         if (CHIP_IS_E1(bp))
9574                 reset_mask2 = 0xffff;
9575         else if (CHIP_IS_E1H(bp))
9576                 reset_mask2 = 0x1ffff;
9577         else if (CHIP_IS_E2(bp))
9578                 reset_mask2 = 0xfffff;
9579         else /* CHIP_IS_E3 */
9580                 reset_mask2 = 0x3ffffff;
9581
9582         /* Don't reset global blocks unless we need to */
9583         if (!global)
9584                 reset_mask2 &= ~global_bits2;
9585
9586         /*
9587          * In case of attention in the QM, we need to reset PXP
9588          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9589          * because otherwise QM reset would release 'close the gates' shortly
9590          * before resetting the PXP, then the PSWRQ would send a write
9591          * request to PGLUE. Then when PXP is reset, PGLUE would try to
9592          * read the payload data from PSWWR, but PSWWR would not
9593          * respond. The write queue in PGLUE would stuck, dmae commands
9594          * would not return. Therefore it's important to reset the second
9595          * reset register (containing the
9596          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9597          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9598          * bit).
9599          */
9600         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9601                reset_mask2 & (~not_reset_mask2));
9602
9603         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9604                reset_mask1 & (~not_reset_mask1));
9605
9606         barrier();
9607         mmiowb();
9608
9609         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9610                reset_mask2 & (~stay_reset2));
9611
9612         barrier();
9613         mmiowb();
9614
9615         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9616         mmiowb();
9617 }
9618
9619 /**
9620  * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9621  * It should get cleared in no more than 1s.
9622  *
9623  * @bp: driver handle
9624  *
9625  * It should get cleared in no more than 1s. Returns 0 if
9626  * pending writes bit gets cleared.
9627  */
9628 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9629 {
9630         u32 cnt = 1000;
9631         u32 pend_bits = 0;
9632
9633         do {
9634                 pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9635
9636                 if (pend_bits == 0)
9637                         break;
9638
9639                 usleep_range(1000, 2000);
9640         } while (cnt-- > 0);
9641
9642         if (cnt <= 0) {
9643                 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9644                           pend_bits);
9645                 return -EBUSY;
9646         }
9647
9648         return 0;
9649 }
9650
9651 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9652 {
9653         int cnt = 1000;
9654         u32 val = 0;
9655         u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9656         u32 tags_63_32 = 0;
9657
9658         /* Empty the Tetris buffer, wait for 1s */
9659         do {
9660                 sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9661                 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9662                 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9663                 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9664                 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9665                 if (CHIP_IS_E3(bp))
9666                         tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9667
9668                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9669                     ((port_is_idle_0 & 0x1) == 0x1) &&
9670                     ((port_is_idle_1 & 0x1) == 0x1) &&
9671                     (pgl_exp_rom2 == 0xffffffff) &&
9672                     (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9673                         break;
9674                 usleep_range(1000, 2000);
9675         } while (cnt-- > 0);
9676
9677         if (cnt <= 0) {
9678                 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9679                 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9680                           sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9681                           pgl_exp_rom2);
9682                 return -EAGAIN;
9683         }
9684
9685         barrier();
9686
9687         /* Close gates #2, #3 and #4 */
9688         bnx2x_set_234_gates(bp, true);
9689
9690         /* Poll for IGU VQs for 57712 and newer chips */
9691         if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9692                 return -EAGAIN;
9693
9694         /* TBD: Indicate that "process kill" is in progress to MCP */
9695
9696         /* Clear "unprepared" bit */
9697         REG_WR(bp, MISC_REG_UNPREPARED, 0);
9698         barrier();
9699
9700         /* Make sure all is written to the chip before the reset */
9701         mmiowb();
9702
9703         /* Wait for 1ms to empty GLUE and PCI-E core queues,
9704          * PSWHST, GRC and PSWRD Tetris buffer.
9705          */
9706         usleep_range(1000, 2000);
9707
9708         /* Prepare to chip reset: */
9709         /* MCP */
9710         if (global)
9711                 bnx2x_reset_mcp_prep(bp, &val);
9712
9713         /* PXP */
9714         bnx2x_pxp_prep(bp);
9715         barrier();
9716
9717         /* reset the chip */
9718         bnx2x_process_kill_chip_reset(bp, global);
9719         barrier();
9720
9721         /* clear errors in PGB */
9722         if (!CHIP_IS_E1x(bp))
9723                 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9724
9725         /* Recover after reset: */
9726         /* MCP */
9727         if (global && bnx2x_reset_mcp_comp(bp, val))
9728                 return -EAGAIN;
9729
9730         /* TBD: Add resetting the NO_MCP mode DB here */
9731
9732         /* Open the gates #2, #3 and #4 */
9733         bnx2x_set_234_gates(bp, false);
9734
9735         /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9736          * reset state, re-enable attentions. */
9737
9738         return 0;
9739 }
9740
9741 static int bnx2x_leader_reset(struct bnx2x *bp)
9742 {
9743         int rc = 0;
9744         bool global = bnx2x_reset_is_global(bp);
9745         u32 load_code;
9746
9747         /* if not going to reset MCP - load "fake" driver to reset HW while
9748          * driver is owner of the HW
9749          */
9750         if (!global && !BP_NOMCP(bp)) {
9751                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9752                                              DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9753                 if (!load_code) {
9754                         BNX2X_ERR("MCP response failure, aborting\n");
9755                         rc = -EAGAIN;
9756                         goto exit_leader_reset;
9757                 }
9758                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9759                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9760                         BNX2X_ERR("MCP unexpected resp, aborting\n");
9761                         rc = -EAGAIN;
9762                         goto exit_leader_reset2;
9763                 }
9764                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9765                 if (!load_code) {
9766                         BNX2X_ERR("MCP response failure, aborting\n");
9767                         rc = -EAGAIN;
9768                         goto exit_leader_reset2;
9769                 }
9770         }
9771
9772         /* Try to recover after the failure */
9773         if (bnx2x_process_kill(bp, global)) {
9774                 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9775                           BP_PATH(bp));
9776                 rc = -EAGAIN;
9777                 goto exit_leader_reset2;
9778         }
9779
9780         /*
9781          * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9782          * state.
9783          */
9784         bnx2x_set_reset_done(bp);
9785         if (global)
9786                 bnx2x_clear_reset_global(bp);
9787
9788 exit_leader_reset2:
9789         /* unload "fake driver" if it was loaded */
9790         if (!global && !BP_NOMCP(bp)) {
9791                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9792                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9793         }
9794 exit_leader_reset:
9795         bp->is_leader = 0;
9796         bnx2x_release_leader_lock(bp);
9797         smp_mb();
9798         return rc;
9799 }
9800
9801 static void bnx2x_recovery_failed(struct bnx2x *bp)
9802 {
9803         netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9804
9805         /* Disconnect this device */
9806         netif_device_detach(bp->dev);
9807
9808         /*
9809          * Block ifup for all function on this engine until "process kill"
9810          * or power cycle.
9811          */
9812         bnx2x_set_reset_in_progress(bp);
9813
9814         /* Shut down the power */
9815         bnx2x_set_power_state(bp, PCI_D3hot);
9816
9817         bp->recovery_state = BNX2X_RECOVERY_FAILED;
9818
9819         smp_mb();
9820 }
9821
9822 /*
9823  * Assumption: runs under rtnl lock. This together with the fact
9824  * that it's called only from bnx2x_sp_rtnl() ensure that it
9825  * will never be called when netif_running(bp->dev) is false.
9826  */
9827 static void bnx2x_parity_recover(struct bnx2x *bp)
9828 {
9829         bool global = false;
9830         u32 error_recovered, error_unrecovered;
9831         bool is_parity;
9832
9833         DP(NETIF_MSG_HW, "Handling parity\n");
9834         while (1) {
9835                 switch (bp->recovery_state) {
9836                 case BNX2X_RECOVERY_INIT:
9837                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9838                         is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9839                         WARN_ON(!is_parity);
9840
9841                         /* Try to get a LEADER_LOCK HW lock */
9842                         if (bnx2x_trylock_leader_lock(bp)) {
9843                                 bnx2x_set_reset_in_progress(bp);
9844                                 /*
9845                                  * Check if there is a global attention and if
9846                                  * there was a global attention, set the global
9847                                  * reset bit.
9848                                  */
9849
9850                                 if (global)
9851                                         bnx2x_set_reset_global(bp);
9852
9853                                 bp->is_leader = 1;
9854                         }
9855
9856                         /* Stop the driver */
9857                         /* If interface has been removed - break */
9858                         if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9859                                 return;
9860
9861                         bp->recovery_state = BNX2X_RECOVERY_WAIT;
9862
9863                         /* Ensure "is_leader", MCP command sequence and
9864                          * "recovery_state" update values are seen on other
9865                          * CPUs.
9866                          */
9867                         smp_mb();
9868                         break;
9869
9870                 case BNX2X_RECOVERY_WAIT:
9871                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9872                         if (bp->is_leader) {
9873                                 int other_engine = BP_PATH(bp) ? 0 : 1;
9874                                 bool other_load_status =
9875                                         bnx2x_get_load_status(bp, other_engine);
9876                                 bool load_status =
9877                                         bnx2x_get_load_status(bp, BP_PATH(bp));
9878                                 global = bnx2x_reset_is_global(bp);
9879
9880                                 /*
9881                                  * In case of a parity in a global block, let
9882                                  * the first leader that performs a
9883                                  * leader_reset() reset the global blocks in
9884                                  * order to clear global attentions. Otherwise
9885                                  * the gates will remain closed for that
9886                                  * engine.
9887                                  */
9888                                 if (load_status ||
9889                                     (global && other_load_status)) {
9890                                         /* Wait until all other functions get
9891                                          * down.
9892                                          */
9893                                         schedule_delayed_work(&bp->sp_rtnl_task,
9894                                                                 HZ/10);
9895                                         return;
9896                                 } else {
9897                                         /* If all other functions got down -
9898                                          * try to bring the chip back to
9899                                          * normal. In any case it's an exit
9900                                          * point for a leader.
9901                                          */
9902                                         if (bnx2x_leader_reset(bp)) {
9903                                                 bnx2x_recovery_failed(bp);
9904                                                 return;
9905                                         }
9906
9907                                         /* If we are here, means that the
9908                                          * leader has succeeded and doesn't
9909                                          * want to be a leader any more. Try
9910                                          * to continue as a none-leader.
9911                                          */
9912                                         break;
9913                                 }
9914                         } else { /* non-leader */
9915                                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9916                                         /* Try to get a LEADER_LOCK HW lock as
9917                                          * long as a former leader may have
9918                                          * been unloaded by the user or
9919                                          * released a leadership by another
9920                                          * reason.
9921                                          */
9922                                         if (bnx2x_trylock_leader_lock(bp)) {
9923                                                 /* I'm a leader now! Restart a
9924                                                  * switch case.
9925                                                  */
9926                                                 bp->is_leader = 1;
9927                                                 break;
9928                                         }
9929
9930                                         schedule_delayed_work(&bp->sp_rtnl_task,
9931                                                                 HZ/10);
9932                                         return;
9933
9934                                 } else {
9935                                         /*
9936                                          * If there was a global attention, wait
9937                                          * for it to be cleared.
9938                                          */
9939                                         if (bnx2x_reset_is_global(bp)) {
9940                                                 schedule_delayed_work(
9941                                                         &bp->sp_rtnl_task,
9942                                                         HZ/10);
9943                                                 return;
9944                                         }
9945
9946                                         error_recovered =
9947                                           bp->eth_stats.recoverable_error;
9948                                         error_unrecovered =
9949                                           bp->eth_stats.unrecoverable_error;
9950                                         bp->recovery_state =
9951                                                 BNX2X_RECOVERY_NIC_LOADING;
9952                                         if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9953                                                 error_unrecovered++;
9954                                                 netdev_err(bp->dev,
9955                                                            "Recovery failed. Power cycle needed\n");
9956                                                 /* Disconnect this device */
9957                                                 netif_device_detach(bp->dev);
9958                                                 /* Shut down the power */
9959                                                 bnx2x_set_power_state(
9960                                                         bp, PCI_D3hot);
9961                                                 smp_mb();
9962                                         } else {
9963                                                 bp->recovery_state =
9964                                                         BNX2X_RECOVERY_DONE;
9965                                                 error_recovered++;
9966                                                 smp_mb();
9967                                         }
9968                                         bp->eth_stats.recoverable_error =
9969                                                 error_recovered;
9970                                         bp->eth_stats.unrecoverable_error =
9971                                                 error_unrecovered;
9972
9973                                         return;
9974                                 }
9975                         }
9976                 default:
9977                         return;
9978                 }
9979         }
9980 }
9981
9982 static int bnx2x_close(struct net_device *dev);
9983
9984 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9985  * scheduled on a general queue in order to prevent a dead lock.
9986  */
9987 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9988 {
9989         struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9990
9991         rtnl_lock();
9992
9993         if (!netif_running(bp->dev)) {
9994                 rtnl_unlock();
9995                 return;
9996         }
9997
9998         if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9999 #ifdef BNX2X_STOP_ON_ERROR
10000                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10001                           "you will need to reboot when done\n");
10002                 goto sp_rtnl_not_reset;
10003 #endif
10004                 /*
10005                  * Clear all pending SP commands as we are going to reset the
10006                  * function anyway.
10007                  */
10008                 bp->sp_rtnl_state = 0;
10009                 smp_mb();
10010
10011                 bnx2x_parity_recover(bp);
10012
10013                 rtnl_unlock();
10014                 return;
10015         }
10016
10017         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
10018 #ifdef BNX2X_STOP_ON_ERROR
10019                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10020                           "you will need to reboot when done\n");
10021                 goto sp_rtnl_not_reset;
10022 #endif
10023
10024                 /*
10025                  * Clear all pending SP commands as we are going to reset the
10026                  * function anyway.
10027                  */
10028                 bp->sp_rtnl_state = 0;
10029                 smp_mb();
10030
10031                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
10032                 bnx2x_nic_load(bp, LOAD_NORMAL);
10033
10034                 rtnl_unlock();
10035                 return;
10036         }
10037 #ifdef BNX2X_STOP_ON_ERROR
10038 sp_rtnl_not_reset:
10039 #endif
10040         if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
10041                 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
10042         if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
10043                 bnx2x_after_function_update(bp);
10044         /*
10045          * in case of fan failure we need to reset id if the "stop on error"
10046          * debug flag is set, since we trying to prevent permanent overheating
10047          * damage
10048          */
10049         if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
10050                 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
10051                 netif_device_detach(bp->dev);
10052                 bnx2x_close(bp->dev);
10053                 rtnl_unlock();
10054                 return;
10055         }
10056
10057         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
10058                 DP(BNX2X_MSG_SP,
10059                    "sending set mcast vf pf channel message from rtnl sp-task\n");
10060                 bnx2x_vfpf_set_mcast(bp->dev);
10061         }
10062         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
10063                                &bp->sp_rtnl_state)){
10064                 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
10065                         bnx2x_tx_disable(bp);
10066                         BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
10067                 }
10068         }
10069
10070         if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
10071                 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
10072                 bnx2x_set_rx_mode_inner(bp);
10073         }
10074
10075         if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
10076                                &bp->sp_rtnl_state))
10077                 bnx2x_pf_set_vfs_vlan(bp);
10078
10079         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
10080                 bnx2x_dcbx_stop_hw_tx(bp);
10081                 bnx2x_dcbx_resume_hw_tx(bp);
10082         }
10083
10084         if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
10085                                &bp->sp_rtnl_state))
10086                 bnx2x_update_mng_version(bp);
10087
10088         /* work which needs rtnl lock not-taken (as it takes the lock itself and
10089          * can be called from other contexts as well)
10090          */
10091         rtnl_unlock();
10092
10093         /* enable SR-IOV if applicable */
10094         if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
10095                                                &bp->sp_rtnl_state)) {
10096                 bnx2x_disable_sriov(bp);
10097                 bnx2x_enable_sriov(bp);
10098         }
10099 }
10100
10101 static void bnx2x_period_task(struct work_struct *work)
10102 {
10103         struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
10104
10105         if (!netif_running(bp->dev))
10106                 goto period_task_exit;
10107
10108         if (CHIP_REV_IS_SLOW(bp)) {
10109                 BNX2X_ERR("period task called on emulation, ignoring\n");
10110                 goto period_task_exit;
10111         }
10112
10113         bnx2x_acquire_phy_lock(bp);
10114         /*
10115          * The barrier is needed to ensure the ordering between the writing to
10116          * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10117          * the reading here.
10118          */
10119         smp_mb();
10120         if (bp->port.pmf) {
10121                 bnx2x_period_func(&bp->link_params, &bp->link_vars);
10122
10123                 /* Re-queue task in 1 sec */
10124                 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
10125         }
10126
10127         bnx2x_release_phy_lock(bp);
10128 period_task_exit:
10129         return;
10130 }
10131
10132 /*
10133  * Init service functions
10134  */
10135
10136 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
10137 {
10138         u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10139         u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
10140         return base + (BP_ABS_FUNC(bp)) * stride;
10141 }
10142
10143 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
10144                                         struct bnx2x_mac_vals *vals)
10145 {
10146         u32 val, base_addr, offset, mask, reset_reg;
10147         bool mac_stopped = false;
10148         u8 port = BP_PORT(bp);
10149
10150         /* reset addresses as they also mark which values were changed */
10151         vals->bmac_addr = 0;
10152         vals->umac_addr = 0;
10153         vals->xmac_addr = 0;
10154         vals->emac_addr = 0;
10155
10156         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
10157
10158         if (!CHIP_IS_E3(bp)) {
10159                 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
10160                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
10161                 if ((mask & reset_reg) && val) {
10162                         u32 wb_data[2];
10163                         BNX2X_DEV_INFO("Disable bmac Rx\n");
10164                         base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
10165                                                 : NIG_REG_INGRESS_BMAC0_MEM;
10166                         offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
10167                                                 : BIGMAC_REGISTER_BMAC_CONTROL;
10168
10169                         /*
10170                          * use rd/wr since we cannot use dmae. This is safe
10171                          * since MCP won't access the bus due to the request
10172                          * to unload, and no function on the path can be
10173                          * loaded at this time.
10174                          */
10175                         wb_data[0] = REG_RD(bp, base_addr + offset);
10176                         wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
10177                         vals->bmac_addr = base_addr + offset;
10178                         vals->bmac_val[0] = wb_data[0];
10179                         vals->bmac_val[1] = wb_data[1];
10180                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
10181                         REG_WR(bp, vals->bmac_addr, wb_data[0]);
10182                         REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
10183                 }
10184                 BNX2X_DEV_INFO("Disable emac Rx\n");
10185                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10186                 vals->emac_val = REG_RD(bp, vals->emac_addr);
10187                 REG_WR(bp, vals->emac_addr, 0);
10188                 mac_stopped = true;
10189         } else {
10190                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10191                         BNX2X_DEV_INFO("Disable xmac Rx\n");
10192                         base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10193                         val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10194                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10195                                val & ~(1 << 1));
10196                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10197                                val | (1 << 1));
10198                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10199                         vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10200                         REG_WR(bp, vals->xmac_addr, 0);
10201                         mac_stopped = true;
10202                 }
10203                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10204                 if (mask & reset_reg) {
10205                         BNX2X_DEV_INFO("Disable umac Rx\n");
10206                         base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10207                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
10208                         vals->umac_val = REG_RD(bp, vals->umac_addr);
10209                         REG_WR(bp, vals->umac_addr, 0);
10210                         mac_stopped = true;
10211                 }
10212         }
10213
10214         if (mac_stopped)
10215                 msleep(20);
10216 }
10217
10218 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
10219 #define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \
10220                                         0x1848 + ((f) << 4))
10221 #define BNX2X_PREV_UNDI_RCQ(val)        ((val) & 0xffff)
10222 #define BNX2X_PREV_UNDI_BD(val)         ((val) >> 16 & 0xffff)
10223 #define BNX2X_PREV_UNDI_PROD(rcq, bd)   ((bd) << 16 | (rcq))
10224
10225 #define BCM_5710_UNDI_FW_MF_MAJOR       (0x07)
10226 #define BCM_5710_UNDI_FW_MF_MINOR       (0x08)
10227 #define BCM_5710_UNDI_FW_MF_VERS        (0x05)
10228
10229 static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
10230 {
10231         /* UNDI marks its presence in DORQ -
10232          * it initializes CID offset for normal bell to 0x7
10233          */
10234         if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10235             MISC_REGISTERS_RESET_REG_1_RST_DORQ))
10236                 return false;
10237
10238         if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
10239                 BNX2X_DEV_INFO("UNDI previously loaded\n");
10240                 return true;
10241         }
10242
10243         return false;
10244 }
10245
10246 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc)
10247 {
10248         u16 rcq, bd;
10249         u32 addr, tmp_reg;
10250
10251         if (BP_FUNC(bp) < 2)
10252                 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp));
10253         else
10254                 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2);
10255
10256         tmp_reg = REG_RD(bp, addr);
10257         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10258         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10259
10260         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
10261         REG_WR(bp, addr, tmp_reg);
10262
10263         BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10264                        BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq);
10265 }
10266
10267 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
10268 {
10269         u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10270                                   DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
10271         if (!rc) {
10272                 BNX2X_ERR("MCP response failure, aborting\n");
10273                 return -EBUSY;
10274         }
10275
10276         return 0;
10277 }
10278
10279 static struct bnx2x_prev_path_list *
10280                 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10281 {
10282         struct bnx2x_prev_path_list *tmp_list;
10283
10284         list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10285                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10286                     bp->pdev->bus->number == tmp_list->bus &&
10287                     BP_PATH(bp) == tmp_list->path)
10288                         return tmp_list;
10289
10290         return NULL;
10291 }
10292
10293 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10294 {
10295         struct bnx2x_prev_path_list *tmp_list;
10296         int rc;
10297
10298         rc = down_interruptible(&bnx2x_prev_sem);
10299         if (rc) {
10300                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10301                 return rc;
10302         }
10303
10304         tmp_list = bnx2x_prev_path_get_entry(bp);
10305         if (tmp_list) {
10306                 tmp_list->aer = 1;
10307                 rc = 0;
10308         } else {
10309                 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10310                           BP_PATH(bp));
10311         }
10312
10313         up(&bnx2x_prev_sem);
10314
10315         return rc;
10316 }
10317
10318 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
10319 {
10320         struct bnx2x_prev_path_list *tmp_list;
10321         bool rc = false;
10322
10323         if (down_trylock(&bnx2x_prev_sem))
10324                 return false;
10325
10326         tmp_list = bnx2x_prev_path_get_entry(bp);
10327         if (tmp_list) {
10328                 if (tmp_list->aer) {
10329                         DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10330                            BP_PATH(bp));
10331                 } else {
10332                         rc = true;
10333                         BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10334                                        BP_PATH(bp));
10335                 }
10336         }
10337
10338         up(&bnx2x_prev_sem);
10339
10340         return rc;
10341 }
10342
10343 bool bnx2x_port_after_undi(struct bnx2x *bp)
10344 {
10345         struct bnx2x_prev_path_list *entry;
10346         bool val;
10347
10348         down(&bnx2x_prev_sem);
10349
10350         entry = bnx2x_prev_path_get_entry(bp);
10351         val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10352
10353         up(&bnx2x_prev_sem);
10354
10355         return val;
10356 }
10357
10358 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
10359 {
10360         struct bnx2x_prev_path_list *tmp_list;
10361         int rc;
10362
10363         rc = down_interruptible(&bnx2x_prev_sem);
10364         if (rc) {
10365                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10366                 return rc;
10367         }
10368
10369         /* Check whether the entry for this path already exists */
10370         tmp_list = bnx2x_prev_path_get_entry(bp);
10371         if (tmp_list) {
10372                 if (!tmp_list->aer) {
10373                         BNX2X_ERR("Re-Marking the path.\n");
10374                 } else {
10375                         DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10376                            BP_PATH(bp));
10377                         tmp_list->aer = 0;
10378                 }
10379                 up(&bnx2x_prev_sem);
10380                 return 0;
10381         }
10382         up(&bnx2x_prev_sem);
10383
10384         /* Create an entry for this path and add it */
10385         tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
10386         if (!tmp_list) {
10387                 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10388                 return -ENOMEM;
10389         }
10390
10391         tmp_list->bus = bp->pdev->bus->number;
10392         tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10393         tmp_list->path = BP_PATH(bp);
10394         tmp_list->aer = 0;
10395         tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
10396
10397         rc = down_interruptible(&bnx2x_prev_sem);
10398         if (rc) {
10399                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10400                 kfree(tmp_list);
10401         } else {
10402                 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10403                    BP_PATH(bp));
10404                 list_add(&tmp_list->list, &bnx2x_prev_list);
10405                 up(&bnx2x_prev_sem);
10406         }
10407
10408         return rc;
10409 }
10410
10411 static int bnx2x_do_flr(struct bnx2x *bp)
10412 {
10413         struct pci_dev *dev = bp->pdev;
10414
10415         if (CHIP_IS_E1x(bp)) {
10416                 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10417                 return -EINVAL;
10418         }
10419
10420         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10421         if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10422                 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10423                           bp->common.bc_ver);
10424                 return -EINVAL;
10425         }
10426
10427         if (!pci_wait_for_pending_transaction(dev))
10428                 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
10429
10430         BNX2X_DEV_INFO("Initiating FLR\n");
10431         bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10432
10433         return 0;
10434 }
10435
10436 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
10437 {
10438         int rc;
10439
10440         BNX2X_DEV_INFO("Uncommon unload Flow\n");
10441
10442         /* Test if previous unload process was already finished for this path */
10443         if (bnx2x_prev_is_path_marked(bp))
10444                 return bnx2x_prev_mcp_done(bp);
10445
10446         BNX2X_DEV_INFO("Path is unmarked\n");
10447
10448         /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10449         if (bnx2x_prev_is_after_undi(bp))
10450                 goto out;
10451
10452         /* If function has FLR capabilities, and existing FW version matches
10453          * the one required, then FLR will be sufficient to clean any residue
10454          * left by previous driver
10455          */
10456         rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
10457
10458         if (!rc) {
10459                 /* fw version is good */
10460                 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10461                 rc = bnx2x_do_flr(bp);
10462         }
10463
10464         if (!rc) {
10465                 /* FLR was performed */
10466                 BNX2X_DEV_INFO("FLR successful\n");
10467                 return 0;
10468         }
10469
10470         BNX2X_DEV_INFO("Could not FLR\n");
10471
10472 out:
10473         /* Close the MCP request, return failure*/
10474         rc = bnx2x_prev_mcp_done(bp);
10475         if (!rc)
10476                 rc = BNX2X_PREV_WAIT_NEEDED;
10477
10478         return rc;
10479 }
10480
10481 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10482 {
10483         u32 reset_reg, tmp_reg = 0, rc;
10484         bool prev_undi = false;
10485         struct bnx2x_mac_vals mac_vals;
10486
10487         /* It is possible a previous function received 'common' answer,
10488          * but hasn't loaded yet, therefore creating a scenario of
10489          * multiple functions receiving 'common' on the same path.
10490          */
10491         BNX2X_DEV_INFO("Common unload Flow\n");
10492
10493         memset(&mac_vals, 0, sizeof(mac_vals));
10494
10495         if (bnx2x_prev_is_path_marked(bp))
10496                 return bnx2x_prev_mcp_done(bp);
10497
10498         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10499
10500         /* Reset should be performed after BRB is emptied */
10501         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10502                 u32 timer_count = 1000;
10503
10504                 /* Close the MAC Rx to prevent BRB from filling up */
10505                 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10506
10507                 /* close LLH filters towards the BRB */
10508                 bnx2x_set_rx_filter(&bp->link_params, 0);
10509
10510                 /* Check if the UNDI driver was previously loaded */
10511                 if (bnx2x_prev_is_after_undi(bp)) {
10512                         prev_undi = true;
10513                         /* clear the UNDI indication */
10514                         REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10515                         /* clear possible idle check errors */
10516                         REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10517                 }
10518                 if (!CHIP_IS_E1x(bp))
10519                         /* block FW from writing to host */
10520                         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10521
10522                 /* wait until BRB is empty */
10523                 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10524                 while (timer_count) {
10525                         u32 prev_brb = tmp_reg;
10526
10527                         tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10528                         if (!tmp_reg)
10529                                 break;
10530
10531                         BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10532
10533                         /* reset timer as long as BRB actually gets emptied */
10534                         if (prev_brb > tmp_reg)
10535                                 timer_count = 1000;
10536                         else
10537                                 timer_count--;
10538
10539                         /* If UNDI resides in memory, manually increment it */
10540                         if (prev_undi)
10541                                 bnx2x_prev_unload_undi_inc(bp, 1);
10542
10543                         udelay(10);
10544                 }
10545
10546                 if (!timer_count)
10547                         BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10548         }
10549
10550         /* No packets are in the pipeline, path is ready for reset */
10551         bnx2x_reset_common(bp);
10552
10553         if (mac_vals.xmac_addr)
10554                 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10555         if (mac_vals.umac_addr)
10556                 REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val);
10557         if (mac_vals.emac_addr)
10558                 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10559         if (mac_vals.bmac_addr) {
10560                 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10561                 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10562         }
10563
10564         rc = bnx2x_prev_mark_path(bp, prev_undi);
10565         if (rc) {
10566                 bnx2x_prev_mcp_done(bp);
10567                 return rc;
10568         }
10569
10570         return bnx2x_prev_mcp_done(bp);
10571 }
10572
10573 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
10574  * and boot began, or when kdump kernel was loaded. Either case would invalidate
10575  * the addresses of the transaction, resulting in was-error bit set in the pci
10576  * causing all hw-to-host pcie transactions to timeout. If this happened we want
10577  * to clear the interrupt which detected this from the pglueb and the was done
10578  * bit
10579  */
10580 static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
10581 {
10582         if (!CHIP_IS_E1x(bp)) {
10583                 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
10584                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
10585                         DP(BNX2X_MSG_SP,
10586                            "'was error' bit was found to be set in pglueb upon startup. Clearing\n");
10587                         REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
10588                                1 << BP_FUNC(bp));
10589                 }
10590         }
10591 }
10592
10593 static int bnx2x_prev_unload(struct bnx2x *bp)
10594 {
10595         int time_counter = 10;
10596         u32 rc, fw, hw_lock_reg, hw_lock_val;
10597         BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10598
10599         /* clear hw from errors which may have resulted from an interrupted
10600          * dmae transaction.
10601          */
10602         bnx2x_prev_interrupted_dmae(bp);
10603
10604         /* Release previously held locks */
10605         hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10606                       (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10607                       (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10608
10609         hw_lock_val = REG_RD(bp, hw_lock_reg);
10610         if (hw_lock_val) {
10611                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10612                         BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10613                         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10614                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10615                 }
10616
10617                 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10618                 REG_WR(bp, hw_lock_reg, 0xffffffff);
10619         } else
10620                 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10621
10622         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10623                 BNX2X_DEV_INFO("Release previously held alr\n");
10624                 bnx2x_release_alr(bp);
10625         }
10626
10627         do {
10628                 int aer = 0;
10629                 /* Lock MCP using an unload request */
10630                 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10631                 if (!fw) {
10632                         BNX2X_ERR("MCP response failure, aborting\n");
10633                         rc = -EBUSY;
10634                         break;
10635                 }
10636
10637                 rc = down_interruptible(&bnx2x_prev_sem);
10638                 if (rc) {
10639                         BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10640                                   rc);
10641                 } else {
10642                         /* If Path is marked by EEH, ignore unload status */
10643                         aer = !!(bnx2x_prev_path_get_entry(bp) &&
10644                                  bnx2x_prev_path_get_entry(bp)->aer);
10645                         up(&bnx2x_prev_sem);
10646                 }
10647
10648                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10649                         rc = bnx2x_prev_unload_common(bp);
10650                         break;
10651                 }
10652
10653                 /* non-common reply from MCP might require looping */
10654                 rc = bnx2x_prev_unload_uncommon(bp);
10655                 if (rc != BNX2X_PREV_WAIT_NEEDED)
10656                         break;
10657
10658                 msleep(20);
10659         } while (--time_counter);
10660
10661         if (!time_counter || rc) {
10662                 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10663                 rc = -EPROBE_DEFER;
10664         }
10665
10666         /* Mark function if its port was used to boot from SAN */
10667         if (bnx2x_port_after_undi(bp))
10668                 bp->link_params.feature_config_flags |=
10669                         FEATURE_CONFIG_BOOT_FROM_SAN;
10670
10671         BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10672
10673         return rc;
10674 }
10675
10676 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10677 {
10678         u32 val, val2, val3, val4, id, boot_mode;
10679         u16 pmc;
10680
10681         /* Get the chip revision id and number. */
10682         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10683         val = REG_RD(bp, MISC_REG_CHIP_NUM);
10684         id = ((val & 0xffff) << 16);
10685         val = REG_RD(bp, MISC_REG_CHIP_REV);
10686         id |= ((val & 0xf) << 12);
10687
10688         /* Metal is read from PCI regs, but we can't access >=0x400 from
10689          * the configuration space (so we need to reg_rd)
10690          */
10691         val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10692         id |= (((val >> 24) & 0xf) << 4);
10693         val = REG_RD(bp, MISC_REG_BOND_ID);
10694         id |= (val & 0xf);
10695         bp->common.chip_id = id;
10696
10697         /* force 57811 according to MISC register */
10698         if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10699                 if (CHIP_IS_57810(bp))
10700                         bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10701                                 (bp->common.chip_id & 0x0000FFFF);
10702                 else if (CHIP_IS_57810_MF(bp))
10703                         bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10704                                 (bp->common.chip_id & 0x0000FFFF);
10705                 bp->common.chip_id |= 0x1;
10706         }
10707
10708         /* Set doorbell size */
10709         bp->db_size = (1 << BNX2X_DB_SHIFT);
10710
10711         if (!CHIP_IS_E1x(bp)) {
10712                 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10713                 if ((val & 1) == 0)
10714                         val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10715                 else
10716                         val = (val >> 1) & 1;
10717                 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10718                                                        "2_PORT_MODE");
10719                 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10720                                                  CHIP_2_PORT_MODE;
10721
10722                 if (CHIP_MODE_IS_4_PORT(bp))
10723                         bp->pfid = (bp->pf_num >> 1);   /* 0..3 */
10724                 else
10725                         bp->pfid = (bp->pf_num & 0x6);  /* 0, 2, 4, 6 */
10726         } else {
10727                 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10728                 bp->pfid = bp->pf_num;                  /* 0..7 */
10729         }
10730
10731         BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10732
10733         bp->link_params.chip_id = bp->common.chip_id;
10734         BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10735
10736         val = (REG_RD(bp, 0x2874) & 0x55);
10737         if ((bp->common.chip_id & 0x1) ||
10738             (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10739                 bp->flags |= ONE_PORT_FLAG;
10740                 BNX2X_DEV_INFO("single port device\n");
10741         }
10742
10743         val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10744         bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10745                                  (val & MCPR_NVM_CFG4_FLASH_SIZE));
10746         BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10747                        bp->common.flash_size, bp->common.flash_size);
10748
10749         bnx2x_init_shmem(bp);
10750
10751         bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10752                                         MISC_REG_GENERIC_CR_1 :
10753                                         MISC_REG_GENERIC_CR_0));
10754
10755         bp->link_params.shmem_base = bp->common.shmem_base;
10756         bp->link_params.shmem2_base = bp->common.shmem2_base;
10757         if (SHMEM2_RD(bp, size) >
10758             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10759                 bp->link_params.lfa_base =
10760                 REG_RD(bp, bp->common.shmem2_base +
10761                        (u32)offsetof(struct shmem2_region,
10762                                      lfa_host_addr[BP_PORT(bp)]));
10763         else
10764                 bp->link_params.lfa_base = 0;
10765         BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
10766                        bp->common.shmem_base, bp->common.shmem2_base);
10767
10768         if (!bp->common.shmem_base) {
10769                 BNX2X_DEV_INFO("MCP not active\n");
10770                 bp->flags |= NO_MCP_FLAG;
10771                 return;
10772         }
10773
10774         bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10775         BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10776
10777         bp->link_params.hw_led_mode = ((bp->common.hw_config &
10778                                         SHARED_HW_CFG_LED_MODE_MASK) >>
10779                                        SHARED_HW_CFG_LED_MODE_SHIFT);
10780
10781         bp->link_params.feature_config_flags = 0;
10782         val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10783         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10784                 bp->link_params.feature_config_flags |=
10785                                 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10786         else
10787                 bp->link_params.feature_config_flags &=
10788                                 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10789
10790         val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10791         bp->common.bc_ver = val;
10792         BNX2X_DEV_INFO("bc_ver %X\n", val);
10793         if (val < BNX2X_BC_VER) {
10794                 /* for now only warn
10795                  * later we might need to enforce this */
10796                 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10797                           BNX2X_BC_VER, val);
10798         }
10799         bp->link_params.feature_config_flags |=
10800                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10801                                 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10802
10803         bp->link_params.feature_config_flags |=
10804                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10805                 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10806         bp->link_params.feature_config_flags |=
10807                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10808                 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
10809         bp->link_params.feature_config_flags |=
10810                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10811                 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
10812
10813         bp->link_params.feature_config_flags |=
10814                 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10815                 FEATURE_CONFIG_MT_SUPPORT : 0;
10816
10817         bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10818                         BC_SUPPORTS_PFC_STATS : 0;
10819
10820         bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10821                         BC_SUPPORTS_FCOE_FEATURES : 0;
10822
10823         bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10824                         BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
10825
10826         bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
10827                         BC_SUPPORTS_RMMOD_CMD : 0;
10828
10829         boot_mode = SHMEM_RD(bp,
10830                         dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10831                         PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10832         switch (boot_mode) {
10833         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10834                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10835                 break;
10836         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10837                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10838                 break;
10839         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10840                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10841                 break;
10842         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10843                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10844                 break;
10845         }
10846
10847         pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
10848         bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10849
10850         BNX2X_DEV_INFO("%sWoL capable\n",
10851                        (bp->flags & NO_WOL_FLAG) ? "not " : "");
10852
10853         val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10854         val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10855         val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10856         val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10857
10858         dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10859                  val, val2, val3, val4);
10860 }
10861
10862 #define IGU_FID(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10863 #define IGU_VEC(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10864
10865 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10866 {
10867         int pfid = BP_FUNC(bp);
10868         int igu_sb_id;
10869         u32 val;
10870         u8 fid, igu_sb_cnt = 0;
10871
10872         bp->igu_base_sb = 0xff;
10873         if (CHIP_INT_MODE_IS_BC(bp)) {
10874                 int vn = BP_VN(bp);
10875                 igu_sb_cnt = bp->igu_sb_cnt;
10876                 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10877                         FP_SB_MAX_E1x;
10878
10879                 bp->igu_dsb_id =  E1HVN_MAX * FP_SB_MAX_E1x +
10880                         (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10881
10882                 return 0;
10883         }
10884
10885         /* IGU in normal mode - read CAM */
10886         for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10887              igu_sb_id++) {
10888                 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10889                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10890                         continue;
10891                 fid = IGU_FID(val);
10892                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10893                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10894                                 continue;
10895                         if (IGU_VEC(val) == 0)
10896                                 /* default status block */
10897                                 bp->igu_dsb_id = igu_sb_id;
10898                         else {
10899                                 if (bp->igu_base_sb == 0xff)
10900                                         bp->igu_base_sb = igu_sb_id;
10901                                 igu_sb_cnt++;
10902                         }
10903                 }
10904         }
10905
10906 #ifdef CONFIG_PCI_MSI
10907         /* Due to new PF resource allocation by MFW T7.4 and above, it's
10908          * optional that number of CAM entries will not be equal to the value
10909          * advertised in PCI.
10910          * Driver should use the minimal value of both as the actual status
10911          * block count
10912          */
10913         bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10914 #endif
10915
10916         if (igu_sb_cnt == 0) {
10917                 BNX2X_ERR("CAM configuration error\n");
10918                 return -EINVAL;
10919         }
10920
10921         return 0;
10922 }
10923
10924 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10925 {
10926         int cfg_size = 0, idx, port = BP_PORT(bp);
10927
10928         /* Aggregation of supported attributes of all external phys */
10929         bp->port.supported[0] = 0;
10930         bp->port.supported[1] = 0;
10931         switch (bp->link_params.num_phys) {
10932         case 1:
10933                 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10934                 cfg_size = 1;
10935                 break;
10936         case 2:
10937                 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10938                 cfg_size = 1;
10939                 break;
10940         case 3:
10941                 if (bp->link_params.multi_phy_config &
10942                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10943                         bp->port.supported[1] =
10944                                 bp->link_params.phy[EXT_PHY1].supported;
10945                         bp->port.supported[0] =
10946                                 bp->link_params.phy[EXT_PHY2].supported;
10947                 } else {
10948                         bp->port.supported[0] =
10949                                 bp->link_params.phy[EXT_PHY1].supported;
10950                         bp->port.supported[1] =
10951                                 bp->link_params.phy[EXT_PHY2].supported;
10952                 }
10953                 cfg_size = 2;
10954                 break;
10955         }
10956
10957         if (!(bp->port.supported[0] || bp->port.supported[1])) {
10958                 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10959                            SHMEM_RD(bp,
10960                            dev_info.port_hw_config[port].external_phy_config),
10961                            SHMEM_RD(bp,
10962                            dev_info.port_hw_config[port].external_phy_config2));
10963                         return;
10964         }
10965
10966         if (CHIP_IS_E3(bp))
10967                 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10968         else {
10969                 switch (switch_cfg) {
10970                 case SWITCH_CFG_1G:
10971                         bp->port.phy_addr = REG_RD(
10972                                 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10973                         break;
10974                 case SWITCH_CFG_10G:
10975                         bp->port.phy_addr = REG_RD(
10976                                 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10977                         break;
10978                 default:
10979                         BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10980                                   bp->port.link_config[0]);
10981                         return;
10982                 }
10983         }
10984         BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
10985         /* mask what we support according to speed_cap_mask per configuration */
10986         for (idx = 0; idx < cfg_size; idx++) {
10987                 if (!(bp->link_params.speed_cap_mask[idx] &
10988                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
10989                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
10990
10991                 if (!(bp->link_params.speed_cap_mask[idx] &
10992                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
10993                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
10994
10995                 if (!(bp->link_params.speed_cap_mask[idx] &
10996                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
10997                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
10998
10999                 if (!(bp->link_params.speed_cap_mask[idx] &
11000                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
11001                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
11002
11003                 if (!(bp->link_params.speed_cap_mask[idx] &
11004                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
11005                         bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
11006                                                      SUPPORTED_1000baseT_Full);
11007
11008                 if (!(bp->link_params.speed_cap_mask[idx] &
11009                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
11010                         bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
11011
11012                 if (!(bp->link_params.speed_cap_mask[idx] &
11013                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
11014                         bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
11015
11016                 if (!(bp->link_params.speed_cap_mask[idx] &
11017                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
11018                         bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
11019         }
11020
11021         BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
11022                        bp->port.supported[1]);
11023 }
11024
11025 static void bnx2x_link_settings_requested(struct bnx2x *bp)
11026 {
11027         u32 link_config, idx, cfg_size = 0;
11028         bp->port.advertising[0] = 0;
11029         bp->port.advertising[1] = 0;
11030         switch (bp->link_params.num_phys) {
11031         case 1:
11032         case 2:
11033                 cfg_size = 1;
11034                 break;
11035         case 3:
11036                 cfg_size = 2;
11037                 break;
11038         }
11039         for (idx = 0; idx < cfg_size; idx++) {
11040                 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
11041                 link_config = bp->port.link_config[idx];
11042                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11043                 case PORT_FEATURE_LINK_SPEED_AUTO:
11044                         if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
11045                                 bp->link_params.req_line_speed[idx] =
11046                                         SPEED_AUTO_NEG;
11047                                 bp->port.advertising[idx] |=
11048                                         bp->port.supported[idx];
11049                                 if (bp->link_params.phy[EXT_PHY1].type ==
11050                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
11051                                         bp->port.advertising[idx] |=
11052                                         (SUPPORTED_100baseT_Half |
11053                                          SUPPORTED_100baseT_Full);
11054                         } else {
11055                                 /* force 10G, no AN */
11056                                 bp->link_params.req_line_speed[idx] =
11057                                         SPEED_10000;
11058                                 bp->port.advertising[idx] |=
11059                                         (ADVERTISED_10000baseT_Full |
11060                                          ADVERTISED_FIBRE);
11061                                 continue;
11062                         }
11063                         break;
11064
11065                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11066                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
11067                                 bp->link_params.req_line_speed[idx] =
11068                                         SPEED_10;
11069                                 bp->port.advertising[idx] |=
11070                                         (ADVERTISED_10baseT_Full |
11071                                          ADVERTISED_TP);
11072                         } else {
11073                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11074                                             link_config,
11075                                     bp->link_params.speed_cap_mask[idx]);
11076                                 return;
11077                         }
11078                         break;
11079
11080                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11081                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
11082                                 bp->link_params.req_line_speed[idx] =
11083                                         SPEED_10;
11084                                 bp->link_params.req_duplex[idx] =
11085                                         DUPLEX_HALF;
11086                                 bp->port.advertising[idx] |=
11087                                         (ADVERTISED_10baseT_Half |
11088                                          ADVERTISED_TP);
11089                         } else {
11090                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11091                                             link_config,
11092                                           bp->link_params.speed_cap_mask[idx]);
11093                                 return;
11094                         }
11095                         break;
11096
11097                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11098                         if (bp->port.supported[idx] &
11099                             SUPPORTED_100baseT_Full) {
11100                                 bp->link_params.req_line_speed[idx] =
11101                                         SPEED_100;
11102                                 bp->port.advertising[idx] |=
11103                                         (ADVERTISED_100baseT_Full |
11104                                          ADVERTISED_TP);
11105                         } else {
11106                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11107                                             link_config,
11108                                           bp->link_params.speed_cap_mask[idx]);
11109                                 return;
11110                         }
11111                         break;
11112
11113                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11114                         if (bp->port.supported[idx] &
11115                             SUPPORTED_100baseT_Half) {
11116                                 bp->link_params.req_line_speed[idx] =
11117                                                                 SPEED_100;
11118                                 bp->link_params.req_duplex[idx] =
11119                                                                 DUPLEX_HALF;
11120                                 bp->port.advertising[idx] |=
11121                                         (ADVERTISED_100baseT_Half |
11122                                          ADVERTISED_TP);
11123                         } else {
11124                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11125                                     link_config,
11126                                     bp->link_params.speed_cap_mask[idx]);
11127                                 return;
11128                         }
11129                         break;
11130
11131                 case PORT_FEATURE_LINK_SPEED_1G:
11132                         if (bp->port.supported[idx] &
11133                             SUPPORTED_1000baseT_Full) {
11134                                 bp->link_params.req_line_speed[idx] =
11135                                         SPEED_1000;
11136                                 bp->port.advertising[idx] |=
11137                                         (ADVERTISED_1000baseT_Full |
11138                                          ADVERTISED_TP);
11139                         } else {
11140                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11141                                     link_config,
11142                                     bp->link_params.speed_cap_mask[idx]);
11143                                 return;
11144                         }
11145                         break;
11146
11147                 case PORT_FEATURE_LINK_SPEED_2_5G:
11148                         if (bp->port.supported[idx] &
11149                             SUPPORTED_2500baseX_Full) {
11150                                 bp->link_params.req_line_speed[idx] =
11151                                         SPEED_2500;
11152                                 bp->port.advertising[idx] |=
11153                                         (ADVERTISED_2500baseX_Full |
11154                                                 ADVERTISED_TP);
11155                         } else {
11156                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11157                                     link_config,
11158                                     bp->link_params.speed_cap_mask[idx]);
11159                                 return;
11160                         }
11161                         break;
11162
11163                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11164                         if (bp->port.supported[idx] &
11165                             SUPPORTED_10000baseT_Full) {
11166                                 bp->link_params.req_line_speed[idx] =
11167                                         SPEED_10000;
11168                                 bp->port.advertising[idx] |=
11169                                         (ADVERTISED_10000baseT_Full |
11170                                                 ADVERTISED_FIBRE);
11171                         } else {
11172                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11173                                     link_config,
11174                                     bp->link_params.speed_cap_mask[idx]);
11175                                 return;
11176                         }
11177                         break;
11178                 case PORT_FEATURE_LINK_SPEED_20G:
11179                         bp->link_params.req_line_speed[idx] = SPEED_20000;
11180
11181                         break;
11182                 default:
11183                         BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
11184                                   link_config);
11185                                 bp->link_params.req_line_speed[idx] =
11186                                                         SPEED_AUTO_NEG;
11187                                 bp->port.advertising[idx] =
11188                                                 bp->port.supported[idx];
11189                         break;
11190                 }
11191
11192                 bp->link_params.req_flow_ctrl[idx] = (link_config &
11193                                          PORT_FEATURE_FLOW_CONTROL_MASK);
11194                 if (bp->link_params.req_flow_ctrl[idx] ==
11195                     BNX2X_FLOW_CTRL_AUTO) {
11196                         if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11197                                 bp->link_params.req_flow_ctrl[idx] =
11198                                                         BNX2X_FLOW_CTRL_NONE;
11199                         else
11200                                 bnx2x_set_requested_fc(bp);
11201                 }
11202
11203                 BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
11204                                bp->link_params.req_line_speed[idx],
11205                                bp->link_params.req_duplex[idx],
11206                                bp->link_params.req_flow_ctrl[idx],
11207                                bp->port.advertising[idx]);
11208         }
11209 }
11210
11211 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
11212 {
11213         __be16 mac_hi_be = cpu_to_be16(mac_hi);
11214         __be32 mac_lo_be = cpu_to_be32(mac_lo);
11215         memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11216         memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
11217 }
11218
11219 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
11220 {
11221         int port = BP_PORT(bp);
11222         u32 config;
11223         u32 ext_phy_type, ext_phy_config, eee_mode;
11224
11225         bp->link_params.bp = bp;
11226         bp->link_params.port = port;
11227
11228         bp->link_params.lane_config =
11229                 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
11230
11231         bp->link_params.speed_cap_mask[0] =
11232                 SHMEM_RD(bp,
11233                          dev_info.port_hw_config[port].speed_capability_mask) &
11234                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11235         bp->link_params.speed_cap_mask[1] =
11236                 SHMEM_RD(bp,
11237                          dev_info.port_hw_config[port].speed_capability_mask2) &
11238                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11239         bp->port.link_config[0] =
11240                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11241
11242         bp->port.link_config[1] =
11243                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
11244
11245         bp->link_params.multi_phy_config =
11246                 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
11247         /* If the device is capable of WoL, set the default state according
11248          * to the HW
11249          */
11250         config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
11251         bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11252                    (config & PORT_FEATURE_WOL_ENABLED));
11253
11254         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11255             PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11256                 bp->flags |= NO_ISCSI_FLAG;
11257         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11258             PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11259                 bp->flags |= NO_FCOE_FLAG;
11260
11261         BNX2X_DEV_INFO("lane_config 0x%08x  speed_cap_mask0 0x%08x  link_config0 0x%08x\n",
11262                        bp->link_params.lane_config,
11263                        bp->link_params.speed_cap_mask[0],
11264                        bp->port.link_config[0]);
11265
11266         bp->link_params.switch_cfg = (bp->port.link_config[0] &
11267                                       PORT_FEATURE_CONNECTED_SWITCH_MASK);
11268         bnx2x_phy_probe(&bp->link_params);
11269         bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
11270
11271         bnx2x_link_settings_requested(bp);
11272
11273         /*
11274          * If connected directly, work with the internal PHY, otherwise, work
11275          * with the external PHY
11276          */
11277         ext_phy_config =
11278                 SHMEM_RD(bp,
11279                          dev_info.port_hw_config[port].external_phy_config);
11280         ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11281         if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
11282                 bp->mdio.prtad = bp->port.phy_addr;
11283
11284         else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11285                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11286                 bp->mdio.prtad =
11287                         XGXS_EXT_PHY_ADDR(ext_phy_config);
11288
11289         /* Configure link feature according to nvram value */
11290         eee_mode = (((SHMEM_RD(bp, dev_info.
11291                       port_feature_config[port].eee_power_mode)) &
11292                      PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11293                     PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11294         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11295                 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11296                                            EEE_MODE_ENABLE_LPI |
11297                                            EEE_MODE_OUTPUT_TIME;
11298         } else {
11299                 bp->link_params.eee_mode = 0;
11300         }
11301 }
11302
11303 void bnx2x_get_iscsi_info(struct bnx2x *bp)
11304 {
11305         u32 no_flags = NO_ISCSI_FLAG;
11306         int port = BP_PORT(bp);
11307         u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11308                                 drv_lic_key[port].max_iscsi_conn);
11309
11310         if (!CNIC_SUPPORT(bp)) {
11311                 bp->flags |= no_flags;
11312                 return;
11313         }
11314
11315         /* Get the number of maximum allowed iSCSI connections */
11316         bp->cnic_eth_dev.max_iscsi_conn =
11317                 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11318                 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11319
11320         BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11321                        bp->cnic_eth_dev.max_iscsi_conn);
11322
11323         /*
11324          * If maximum allowed number of connections is zero -
11325          * disable the feature.
11326          */
11327         if (!bp->cnic_eth_dev.max_iscsi_conn)
11328                 bp->flags |= no_flags;
11329 }
11330
11331 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
11332 {
11333         /* Port info */
11334         bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11335                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11336         bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11337                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11338
11339         /* Node info */
11340         bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11341                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11342         bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11343                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11344 }
11345
11346 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11347 {
11348         u8 count = 0;
11349
11350         if (IS_MF(bp)) {
11351                 u8 fid;
11352
11353                 /* iterate over absolute function ids for this path: */
11354                 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11355                         if (IS_MF_SD(bp)) {
11356                                 u32 cfg = MF_CFG_RD(bp,
11357                                                     func_mf_config[fid].config);
11358
11359                                 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11360                                     ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11361                                             FUNC_MF_CFG_PROTOCOL_FCOE))
11362                                         count++;
11363                         } else {
11364                                 u32 cfg = MF_CFG_RD(bp,
11365                                                     func_ext_config[fid].
11366                                                                       func_cfg);
11367
11368                                 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11369                                     (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11370                                         count++;
11371                         }
11372                 }
11373         } else { /* SF */
11374                 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11375
11376                 for (port = 0; port < port_cnt; port++) {
11377                         u32 lic = SHMEM_RD(bp,
11378                                            drv_lic_key[port].max_fcoe_conn) ^
11379                                   FW_ENCODE_32BIT_PATTERN;
11380                         if (lic)
11381                                 count++;
11382                 }
11383         }
11384
11385         return count;
11386 }
11387
11388 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
11389 {
11390         int port = BP_PORT(bp);
11391         int func = BP_ABS_FUNC(bp);
11392         u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11393                                 drv_lic_key[port].max_fcoe_conn);
11394         u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
11395
11396         if (!CNIC_SUPPORT(bp)) {
11397                 bp->flags |= NO_FCOE_FLAG;
11398                 return;
11399         }
11400
11401         /* Get the number of maximum allowed FCoE connections */
11402         bp->cnic_eth_dev.max_fcoe_conn =
11403                 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11404                 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11405
11406         /* Calculate the number of maximum allowed FCoE tasks */
11407         bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
11408
11409         /* check if FCoE resources must be shared between different functions */
11410         if (num_fcoe_func)
11411                 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
11412
11413         /* Read the WWN: */
11414         if (!IS_MF(bp)) {
11415                 /* Port info */
11416                 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11417                         SHMEM_RD(bp,
11418                                  dev_info.port_hw_config[port].
11419                                  fcoe_wwn_port_name_upper);
11420                 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11421                         SHMEM_RD(bp,
11422                                  dev_info.port_hw_config[port].
11423                                  fcoe_wwn_port_name_lower);
11424
11425                 /* Node info */
11426                 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11427                         SHMEM_RD(bp,
11428                                  dev_info.port_hw_config[port].
11429                                  fcoe_wwn_node_name_upper);
11430                 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11431                         SHMEM_RD(bp,
11432                                  dev_info.port_hw_config[port].
11433                                  fcoe_wwn_node_name_lower);
11434         } else if (!IS_MF_SD(bp)) {
11435                 /* Read the WWN info only if the FCoE feature is enabled for
11436                  * this function.
11437                  */
11438                 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp))
11439                         bnx2x_get_ext_wwn_info(bp, func);
11440         } else {
11441                 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
11442                         bnx2x_get_ext_wwn_info(bp, func);
11443         }
11444
11445         BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
11446
11447         /*
11448          * If maximum allowed number of connections is zero -
11449          * disable the feature.
11450          */
11451         if (!bp->cnic_eth_dev.max_fcoe_conn)
11452                 bp->flags |= NO_FCOE_FLAG;
11453 }
11454
11455 static void bnx2x_get_cnic_info(struct bnx2x *bp)
11456 {
11457         /*
11458          * iSCSI may be dynamically disabled but reading
11459          * info here we will decrease memory usage by driver
11460          * if the feature is disabled for good
11461          */
11462         bnx2x_get_iscsi_info(bp);
11463         bnx2x_get_fcoe_info(bp);
11464 }
11465
11466 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11467 {
11468         u32 val, val2;
11469         int func = BP_ABS_FUNC(bp);
11470         int port = BP_PORT(bp);
11471         u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11472         u8 *fip_mac = bp->fip_mac;
11473
11474         if (IS_MF(bp)) {
11475                 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11476                  * FCoE MAC then the appropriate feature should be disabled.
11477                  * In non SD mode features configuration comes from struct
11478                  * func_ext_config.
11479                  */
11480                 if (!IS_MF_SD(bp)) {
11481                         u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11482                         if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11483                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11484                                                  iscsi_mac_addr_upper);
11485                                 val = MF_CFG_RD(bp, func_ext_config[func].
11486                                                 iscsi_mac_addr_lower);
11487                                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11488                                 BNX2X_DEV_INFO
11489                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11490                         } else {
11491                                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11492                         }
11493
11494                         if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11495                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11496                                                  fcoe_mac_addr_upper);
11497                                 val = MF_CFG_RD(bp, func_ext_config[func].
11498                                                 fcoe_mac_addr_lower);
11499                                 bnx2x_set_mac_buf(fip_mac, val, val2);
11500                                 BNX2X_DEV_INFO
11501                                         ("Read FCoE L2 MAC: %pM\n", fip_mac);
11502                         } else {
11503                                 bp->flags |= NO_FCOE_FLAG;
11504                         }
11505
11506                         bp->mf_ext_config = cfg;
11507
11508                 } else { /* SD MODE */
11509                         if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11510                                 /* use primary mac as iscsi mac */
11511                                 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11512
11513                                 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11514                                 BNX2X_DEV_INFO
11515                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11516                         } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11517                                 /* use primary mac as fip mac */
11518                                 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11519                                 BNX2X_DEV_INFO("SD FCoE MODE\n");
11520                                 BNX2X_DEV_INFO
11521                                         ("Read FIP MAC: %pM\n", fip_mac);
11522                         }
11523                 }
11524
11525                 /* If this is a storage-only interface, use SAN mac as
11526                  * primary MAC. Notice that for SD this is already the case,
11527                  * as the SAN mac was copied from the primary MAC.
11528                  */
11529                 if (IS_MF_FCOE_AFEX(bp))
11530                         memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11531         } else {
11532                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11533                                 iscsi_mac_upper);
11534                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11535                                iscsi_mac_lower);
11536                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11537
11538                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11539                                 fcoe_fip_mac_upper);
11540                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11541                                fcoe_fip_mac_lower);
11542                 bnx2x_set_mac_buf(fip_mac, val, val2);
11543         }
11544
11545         /* Disable iSCSI OOO if MAC configuration is invalid. */
11546         if (!is_valid_ether_addr(iscsi_mac)) {
11547                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11548                 memset(iscsi_mac, 0, ETH_ALEN);
11549         }
11550
11551         /* Disable FCoE if MAC configuration is invalid. */
11552         if (!is_valid_ether_addr(fip_mac)) {
11553                 bp->flags |= NO_FCOE_FLAG;
11554                 memset(bp->fip_mac, 0, ETH_ALEN);
11555         }
11556 }
11557
11558 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11559 {
11560         u32 val, val2;
11561         int func = BP_ABS_FUNC(bp);
11562         int port = BP_PORT(bp);
11563
11564         /* Zero primary MAC configuration */
11565         memset(bp->dev->dev_addr, 0, ETH_ALEN);
11566
11567         if (BP_NOMCP(bp)) {
11568                 BNX2X_ERROR("warning: random MAC workaround active\n");
11569                 eth_hw_addr_random(bp->dev);
11570         } else if (IS_MF(bp)) {
11571                 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11572                 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11573                 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11574                     (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11575                         bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11576
11577                 if (CNIC_SUPPORT(bp))
11578                         bnx2x_get_cnic_mac_hwinfo(bp);
11579         } else {
11580                 /* in SF read MACs from port configuration */
11581                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11582                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11583                 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11584
11585                 if (CNIC_SUPPORT(bp))
11586                         bnx2x_get_cnic_mac_hwinfo(bp);
11587         }
11588
11589         if (!BP_NOMCP(bp)) {
11590                 /* Read physical port identifier from shmem */
11591                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11592                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11593                 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11594                 bp->flags |= HAS_PHYS_PORT_ID;
11595         }
11596
11597         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11598
11599         if (!is_valid_ether_addr(bp->dev->dev_addr))
11600                 dev_err(&bp->pdev->dev,
11601                         "bad Ethernet MAC address configuration: %pM\n"
11602                         "change it manually before bringing up the appropriate network interface\n",
11603                         bp->dev->dev_addr);
11604 }
11605
11606 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11607 {
11608         int tmp;
11609         u32 cfg;
11610
11611         if (IS_VF(bp))
11612                 return 0;
11613
11614         if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11615                 /* Take function: tmp = func */
11616                 tmp = BP_ABS_FUNC(bp);
11617                 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11618                 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11619         } else {
11620                 /* Take port: tmp = port */
11621                 tmp = BP_PORT(bp);
11622                 cfg = SHMEM_RD(bp,
11623                                dev_info.port_hw_config[tmp].generic_features);
11624                 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11625         }
11626         return cfg;
11627 }
11628
11629 static void validate_set_si_mode(struct bnx2x *bp)
11630 {
11631         u8 func = BP_ABS_FUNC(bp);
11632         u32 val;
11633
11634         val = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11635
11636         /* check for legal mac (upper bytes) */
11637         if (val != 0xffff) {
11638                 bp->mf_mode = MULTI_FUNCTION_SI;
11639                 bp->mf_config[BP_VN(bp)] =
11640                         MF_CFG_RD(bp, func_mf_config[func].config);
11641         } else
11642                 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11643 }
11644
11645 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11646 {
11647         int /*abs*/func = BP_ABS_FUNC(bp);
11648         int vn;
11649         u32 val = 0, val2 = 0;
11650         int rc = 0;
11651
11652         bnx2x_get_common_hwinfo(bp);
11653
11654         /*
11655          * initialize IGU parameters
11656          */
11657         if (CHIP_IS_E1x(bp)) {
11658                 bp->common.int_block = INT_BLOCK_HC;
11659
11660                 bp->igu_dsb_id = DEF_SB_IGU_ID;
11661                 bp->igu_base_sb = 0;
11662         } else {
11663                 bp->common.int_block = INT_BLOCK_IGU;
11664
11665                 /* do not allow device reset during IGU info processing */
11666                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11667
11668                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11669
11670                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11671                         int tout = 5000;
11672
11673                         BNX2X_DEV_INFO("FORCING Normal Mode\n");
11674
11675                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11676                         REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11677                         REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11678
11679                         while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11680                                 tout--;
11681                                 usleep_range(1000, 2000);
11682                         }
11683
11684                         if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11685                                 dev_err(&bp->pdev->dev,
11686                                         "FORCING Normal Mode failed!!!\n");
11687                                 bnx2x_release_hw_lock(bp,
11688                                                       HW_LOCK_RESOURCE_RESET);
11689                                 return -EPERM;
11690                         }
11691                 }
11692
11693                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11694                         BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11695                         bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11696                 } else
11697                         BNX2X_DEV_INFO("IGU Normal Mode\n");
11698
11699                 rc = bnx2x_get_igu_cam_info(bp);
11700                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11701                 if (rc)
11702                         return rc;
11703         }
11704
11705         /*
11706          * set base FW non-default (fast path) status block id, this value is
11707          * used to initialize the fw_sb_id saved on the fp/queue structure to
11708          * determine the id used by the FW.
11709          */
11710         if (CHIP_IS_E1x(bp))
11711                 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11712         else /*
11713               * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11714               * the same queue are indicated on the same IGU SB). So we prefer
11715               * FW and IGU SBs to be the same value.
11716               */
11717                 bp->base_fw_ndsb = bp->igu_base_sb;
11718
11719         BNX2X_DEV_INFO("igu_dsb_id %d  igu_base_sb %d  igu_sb_cnt %d\n"
11720                        "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11721                        bp->igu_sb_cnt, bp->base_fw_ndsb);
11722
11723         /*
11724          * Initialize MF configuration
11725          */
11726
11727         bp->mf_ov = 0;
11728         bp->mf_mode = 0;
11729         bp->mf_sub_mode = 0;
11730         vn = BP_VN(bp);
11731
11732         if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
11733                 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11734                                bp->common.shmem2_base, SHMEM2_RD(bp, size),
11735                               (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11736
11737                 if (SHMEM2_HAS(bp, mf_cfg_addr))
11738                         bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11739                 else
11740                         bp->common.mf_cfg_base = bp->common.shmem_base +
11741                                 offsetof(struct shmem_region, func_mb) +
11742                                 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11743                 /*
11744                  * get mf configuration:
11745                  * 1. Existence of MF configuration
11746                  * 2. MAC address must be legal (check only upper bytes)
11747                  *    for  Switch-Independent mode;
11748                  *    OVLAN must be legal for Switch-Dependent mode
11749                  * 3. SF_MODE configures specific MF mode
11750                  */
11751                 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11752                         /* get mf configuration */
11753                         val = SHMEM_RD(bp,
11754                                        dev_info.shared_feature_config.config);
11755                         val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11756
11757                         switch (val) {
11758                         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11759                                 validate_set_si_mode(bp);
11760                                 break;
11761                         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11762                                 if ((!CHIP_IS_E1x(bp)) &&
11763                                     (MF_CFG_RD(bp, func_mf_config[func].
11764                                                mac_upper) != 0xffff) &&
11765                                     (SHMEM2_HAS(bp,
11766                                                 afex_driver_support))) {
11767                                         bp->mf_mode = MULTI_FUNCTION_AFEX;
11768                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11769                                                 func_mf_config[func].config);
11770                                 } else {
11771                                         BNX2X_DEV_INFO("can not configure afex mode\n");
11772                                 }
11773                                 break;
11774                         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11775                                 /* get OV configuration */
11776                                 val = MF_CFG_RD(bp,
11777                                         func_mf_config[FUNC_0].e1hov_tag);
11778                                 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11779
11780                                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11781                                         bp->mf_mode = MULTI_FUNCTION_SD;
11782                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11783                                                 func_mf_config[func].config);
11784                                 } else
11785                                         BNX2X_DEV_INFO("illegal OV for SD\n");
11786                                 break;
11787                         case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE:
11788                                 bp->mf_mode = MULTI_FUNCTION_SD;
11789                                 bp->mf_sub_mode = SUB_MF_MODE_UFP;
11790                                 bp->mf_config[vn] =
11791                                         MF_CFG_RD(bp,
11792                                                   func_mf_config[func].config);
11793                                 break;
11794                         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11795                                 bp->mf_config[vn] = 0;
11796                                 break;
11797                         case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE:
11798                                 val2 = SHMEM_RD(bp,
11799                                         dev_info.shared_hw_config.config_3);
11800                                 val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK;
11801                                 switch (val2) {
11802                                 case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5:
11803                                         validate_set_si_mode(bp);
11804                                         bp->mf_sub_mode =
11805                                                         SUB_MF_MODE_NPAR1_DOT_5;
11806                                         break;
11807                                 default:
11808                                         /* Unknown configuration */
11809                                         bp->mf_config[vn] = 0;
11810                                         BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n",
11811                                                        val);
11812                                 }
11813                                 break;
11814                         default:
11815                                 /* Unknown configuration: reset mf_config */
11816                                 bp->mf_config[vn] = 0;
11817                                 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
11818                         }
11819                 }
11820
11821                 BNX2X_DEV_INFO("%s function mode\n",
11822                                IS_MF(bp) ? "multi" : "single");
11823
11824                 switch (bp->mf_mode) {
11825                 case MULTI_FUNCTION_SD:
11826                         val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11827                               FUNC_MF_CFG_E1HOV_TAG_MASK;
11828                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11829                                 bp->mf_ov = val;
11830                                 bp->path_has_ovlan = true;
11831
11832                                 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11833                                                func, bp->mf_ov, bp->mf_ov);
11834                         } else if (bp->mf_sub_mode == SUB_MF_MODE_UFP) {
11835                                 dev_err(&bp->pdev->dev,
11836                                         "Unexpected - no valid MF OV for func %d in UFP mode\n",
11837                                         func);
11838                                 bp->path_has_ovlan = true;
11839                         } else {
11840                                 dev_err(&bp->pdev->dev,
11841                                         "No valid MF OV for func %d, aborting\n",
11842                                         func);
11843                                 return -EPERM;
11844                         }
11845                         break;
11846                 case MULTI_FUNCTION_AFEX:
11847                         BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11848                         break;
11849                 case MULTI_FUNCTION_SI:
11850                         BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11851                                        func);
11852                         break;
11853                 default:
11854                         if (vn) {
11855                                 dev_err(&bp->pdev->dev,
11856                                         "VN %d is in a single function mode, aborting\n",
11857                                         vn);
11858                                 return -EPERM;
11859                         }
11860                         break;
11861                 }
11862
11863                 /* check if other port on the path needs ovlan:
11864                  * Since MF configuration is shared between ports
11865                  * Possible mixed modes are only
11866                  * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11867                  */
11868                 if (CHIP_MODE_IS_4_PORT(bp) &&
11869                     !bp->path_has_ovlan &&
11870                     !IS_MF(bp) &&
11871                     bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11872                         u8 other_port = !BP_PORT(bp);
11873                         u8 other_func = BP_PATH(bp) + 2*other_port;
11874                         val = MF_CFG_RD(bp,
11875                                         func_mf_config[other_func].e1hov_tag);
11876                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11877                                 bp->path_has_ovlan = true;
11878                 }
11879         }
11880
11881         /* adjust igu_sb_cnt to MF for E1H */
11882         if (CHIP_IS_E1H(bp) && IS_MF(bp))
11883                 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
11884
11885         /* port info */
11886         bnx2x_get_port_hwinfo(bp);
11887
11888         /* Get MAC addresses */
11889         bnx2x_get_mac_hwinfo(bp);
11890
11891         bnx2x_get_cnic_info(bp);
11892
11893         return rc;
11894 }
11895
11896 static void bnx2x_read_fwinfo(struct bnx2x *bp)
11897 {
11898         int cnt, i, block_end, rodi;
11899         char vpd_start[BNX2X_VPD_LEN+1];
11900         char str_id_reg[VENDOR_ID_LEN+1];
11901         char str_id_cap[VENDOR_ID_LEN+1];
11902         char *vpd_data;
11903         char *vpd_extended_data = NULL;
11904         u8 len;
11905
11906         cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
11907         memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11908
11909         if (cnt < BNX2X_VPD_LEN)
11910                 goto out_not_found;
11911
11912         /* VPD RO tag should be first tag after identifier string, hence
11913          * we should be able to find it in first BNX2X_VPD_LEN chars
11914          */
11915         i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
11916                              PCI_VPD_LRDT_RO_DATA);
11917         if (i < 0)
11918                 goto out_not_found;
11919
11920         block_end = i + PCI_VPD_LRDT_TAG_SIZE +
11921                     pci_vpd_lrdt_size(&vpd_start[i]);
11922
11923         i += PCI_VPD_LRDT_TAG_SIZE;
11924
11925         if (block_end > BNX2X_VPD_LEN) {
11926                 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11927                 if (vpd_extended_data  == NULL)
11928                         goto out_not_found;
11929
11930                 /* read rest of vpd image into vpd_extended_data */
11931                 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11932                 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11933                                    block_end - BNX2X_VPD_LEN,
11934                                    vpd_extended_data + BNX2X_VPD_LEN);
11935                 if (cnt < (block_end - BNX2X_VPD_LEN))
11936                         goto out_not_found;
11937                 vpd_data = vpd_extended_data;
11938         } else
11939                 vpd_data = vpd_start;
11940
11941         /* now vpd_data holds full vpd content in both cases */
11942
11943         rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11944                                    PCI_VPD_RO_KEYWORD_MFR_ID);
11945         if (rodi < 0)
11946                 goto out_not_found;
11947
11948         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11949
11950         if (len != VENDOR_ID_LEN)
11951                 goto out_not_found;
11952
11953         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11954
11955         /* vendor specific info */
11956         snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11957         snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11958         if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11959             !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11960
11961                 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11962                                                 PCI_VPD_RO_KEYWORD_VENDOR0);
11963                 if (rodi >= 0) {
11964                         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11965
11966                         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11967
11968                         if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11969                                 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11970                                 bp->fw_ver[len] = ' ';
11971                         }
11972                 }
11973                 kfree(vpd_extended_data);
11974                 return;
11975         }
11976 out_not_found:
11977         kfree(vpd_extended_data);
11978         return;
11979 }
11980
11981 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
11982 {
11983         u32 flags = 0;
11984
11985         if (CHIP_REV_IS_FPGA(bp))
11986                 SET_FLAGS(flags, MODE_FPGA);
11987         else if (CHIP_REV_IS_EMUL(bp))
11988                 SET_FLAGS(flags, MODE_EMUL);
11989         else
11990                 SET_FLAGS(flags, MODE_ASIC);
11991
11992         if (CHIP_MODE_IS_4_PORT(bp))
11993                 SET_FLAGS(flags, MODE_PORT4);
11994         else
11995                 SET_FLAGS(flags, MODE_PORT2);
11996
11997         if (CHIP_IS_E2(bp))
11998                 SET_FLAGS(flags, MODE_E2);
11999         else if (CHIP_IS_E3(bp)) {
12000                 SET_FLAGS(flags, MODE_E3);
12001                 if (CHIP_REV(bp) == CHIP_REV_Ax)
12002                         SET_FLAGS(flags, MODE_E3_A0);
12003                 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
12004                         SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
12005         }
12006
12007         if (IS_MF(bp)) {
12008                 SET_FLAGS(flags, MODE_MF);
12009                 switch (bp->mf_mode) {
12010                 case MULTI_FUNCTION_SD:
12011                         SET_FLAGS(flags, MODE_MF_SD);
12012                         break;
12013                 case MULTI_FUNCTION_SI:
12014                         SET_FLAGS(flags, MODE_MF_SI);
12015                         break;
12016                 case MULTI_FUNCTION_AFEX:
12017                         SET_FLAGS(flags, MODE_MF_AFEX);
12018                         break;
12019                 }
12020         } else
12021                 SET_FLAGS(flags, MODE_SF);
12022
12023 #if defined(__LITTLE_ENDIAN)
12024         SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
12025 #else /*(__BIG_ENDIAN)*/
12026         SET_FLAGS(flags, MODE_BIG_ENDIAN);
12027 #endif
12028         INIT_MODE_FLAGS(bp) = flags;
12029 }
12030
12031 static int bnx2x_init_bp(struct bnx2x *bp)
12032 {
12033         int func;
12034         int rc;
12035
12036         mutex_init(&bp->port.phy_mutex);
12037         mutex_init(&bp->fw_mb_mutex);
12038         mutex_init(&bp->drv_info_mutex);
12039         bp->drv_info_mng_owner = false;
12040         spin_lock_init(&bp->stats_lock);
12041         sema_init(&bp->stats_sema, 1);
12042
12043         INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
12044         INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
12045         INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
12046         INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task);
12047         if (IS_PF(bp)) {
12048                 rc = bnx2x_get_hwinfo(bp);
12049                 if (rc)
12050                         return rc;
12051         } else {
12052                 eth_zero_addr(bp->dev->dev_addr);
12053         }
12054
12055         bnx2x_set_modes_bitmap(bp);
12056
12057         rc = bnx2x_alloc_mem_bp(bp);
12058         if (rc)
12059                 return rc;
12060
12061         bnx2x_read_fwinfo(bp);
12062
12063         func = BP_FUNC(bp);
12064
12065         /* need to reset chip if undi was active */
12066         if (IS_PF(bp) && !BP_NOMCP(bp)) {
12067                 /* init fw_seq */
12068                 bp->fw_seq =
12069                         SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
12070                                                         DRV_MSG_SEQ_NUMBER_MASK;
12071                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
12072
12073                 rc = bnx2x_prev_unload(bp);
12074                 if (rc) {
12075                         bnx2x_free_mem_bp(bp);
12076                         return rc;
12077                 }
12078         }
12079
12080         if (CHIP_REV_IS_FPGA(bp))
12081                 dev_err(&bp->pdev->dev, "FPGA detected\n");
12082
12083         if (BP_NOMCP(bp) && (func == 0))
12084                 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
12085
12086         bp->disable_tpa = disable_tpa;
12087         bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp);
12088         /* Reduce memory usage in kdump environment by disabling TPA */
12089         bp->disable_tpa |= is_kdump_kernel();
12090
12091         /* Set TPA flags */
12092         if (bp->disable_tpa) {
12093                 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
12094                 bp->dev->features &= ~NETIF_F_LRO;
12095         } else {
12096                 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
12097                 bp->dev->features |= NETIF_F_LRO;
12098         }
12099
12100         if (CHIP_IS_E1(bp))
12101                 bp->dropless_fc = 0;
12102         else
12103                 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
12104
12105         bp->mrrs = mrrs;
12106
12107         bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL;
12108         if (IS_VF(bp))
12109                 bp->rx_ring_size = MAX_RX_AVAIL;
12110
12111         /* make sure that the numbers are in the right granularity */
12112         bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
12113         bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
12114
12115         bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
12116
12117         init_timer(&bp->timer);
12118         bp->timer.expires = jiffies + bp->current_interval;
12119         bp->timer.data = (unsigned long) bp;
12120         bp->timer.function = bnx2x_timer;
12121
12122         if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
12123             SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
12124             SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
12125             SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
12126                 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
12127                 bnx2x_dcbx_init_params(bp);
12128         } else {
12129                 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
12130         }
12131
12132         if (CHIP_IS_E1x(bp))
12133                 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
12134         else
12135                 bp->cnic_base_cl_id = FP_SB_MAX_E2;
12136
12137         /* multiple tx priority */
12138         if (IS_VF(bp))
12139                 bp->max_cos = 1;
12140         else if (CHIP_IS_E1x(bp))
12141                 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
12142         else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
12143                 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
12144         else if (CHIP_IS_E3B0(bp))
12145                 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
12146         else
12147                 BNX2X_ERR("unknown chip %x revision %x\n",
12148                           CHIP_NUM(bp), CHIP_REV(bp));
12149         BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
12150
12151         /* We need at least one default status block for slow-path events,
12152          * second status block for the L2 queue, and a third status block for
12153          * CNIC if supported.
12154          */
12155         if (IS_VF(bp))
12156                 bp->min_msix_vec_cnt = 1;
12157         else if (CNIC_SUPPORT(bp))
12158                 bp->min_msix_vec_cnt = 3;
12159         else /* PF w/o cnic */
12160                 bp->min_msix_vec_cnt = 2;
12161         BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
12162
12163         bp->dump_preset_idx = 1;
12164
12165         if (CHIP_IS_E3B0(bp))
12166                 bp->flags |= PTP_SUPPORTED;
12167
12168         return rc;
12169 }
12170
12171 /****************************************************************************
12172 * General service functions
12173 ****************************************************************************/
12174
12175 /*
12176  * net_device service functions
12177  */
12178
12179 /* called with rtnl_lock */
12180 static int bnx2x_open(struct net_device *dev)
12181 {
12182         struct bnx2x *bp = netdev_priv(dev);
12183         int rc;
12184
12185         bp->stats_init = true;
12186
12187         netif_carrier_off(dev);
12188
12189         bnx2x_set_power_state(bp, PCI_D0);
12190
12191         /* If parity had happen during the unload, then attentions
12192          * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12193          * want the first function loaded on the current engine to
12194          * complete the recovery.
12195          * Parity recovery is only relevant for PF driver.
12196          */
12197         if (IS_PF(bp)) {
12198                 int other_engine = BP_PATH(bp) ? 0 : 1;
12199                 bool other_load_status, load_status;
12200                 bool global = false;
12201
12202                 other_load_status = bnx2x_get_load_status(bp, other_engine);
12203                 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12204                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12205                     bnx2x_chk_parity_attn(bp, &global, true)) {
12206                         do {
12207                                 /* If there are attentions and they are in a
12208                                  * global blocks, set the GLOBAL_RESET bit
12209                                  * regardless whether it will be this function
12210                                  * that will complete the recovery or not.
12211                                  */
12212                                 if (global)
12213                                         bnx2x_set_reset_global(bp);
12214
12215                                 /* Only the first function on the current
12216                                  * engine should try to recover in open. In case
12217                                  * of attentions in global blocks only the first
12218                                  * in the chip should try to recover.
12219                                  */
12220                                 if ((!load_status &&
12221                                      (!global || !other_load_status)) &&
12222                                       bnx2x_trylock_leader_lock(bp) &&
12223                                       !bnx2x_leader_reset(bp)) {
12224                                         netdev_info(bp->dev,
12225                                                     "Recovered in open\n");
12226                                         break;
12227                                 }
12228
12229                                 /* recovery has failed... */
12230                                 bnx2x_set_power_state(bp, PCI_D3hot);
12231                                 bp->recovery_state = BNX2X_RECOVERY_FAILED;
12232
12233                                 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12234                                           "If you still see this message after a few retries then power cycle is required.\n");
12235
12236                                 return -EAGAIN;
12237                         } while (0);
12238                 }
12239         }
12240
12241         bp->recovery_state = BNX2X_RECOVERY_DONE;
12242         rc = bnx2x_nic_load(bp, LOAD_OPEN);
12243         if (rc)
12244                 return rc;
12245         return 0;
12246 }
12247
12248 /* called with rtnl_lock */
12249 static int bnx2x_close(struct net_device *dev)
12250 {
12251         struct bnx2x *bp = netdev_priv(dev);
12252
12253         /* Unload the driver, release IRQs */
12254         bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
12255
12256         return 0;
12257 }
12258
12259 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12260                                       struct bnx2x_mcast_ramrod_params *p)
12261 {
12262         int mc_count = netdev_mc_count(bp->dev);
12263         struct bnx2x_mcast_list_elem *mc_mac =
12264                 kcalloc(mc_count, sizeof(*mc_mac), GFP_ATOMIC);
12265         struct netdev_hw_addr *ha;
12266
12267         if (!mc_mac)
12268                 return -ENOMEM;
12269
12270         INIT_LIST_HEAD(&p->mcast_list);
12271
12272         netdev_for_each_mc_addr(ha, bp->dev) {
12273                 mc_mac->mac = bnx2x_mc_addr(ha);
12274                 list_add_tail(&mc_mac->link, &p->mcast_list);
12275                 mc_mac++;
12276         }
12277
12278         p->mcast_list_len = mc_count;
12279
12280         return 0;
12281 }
12282
12283 static void bnx2x_free_mcast_macs_list(
12284         struct bnx2x_mcast_ramrod_params *p)
12285 {
12286         struct bnx2x_mcast_list_elem *mc_mac =
12287                 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
12288                                  link);
12289
12290         WARN_ON(!mc_mac);
12291         kfree(mc_mac);
12292 }
12293
12294 /**
12295  * bnx2x_set_uc_list - configure a new unicast MACs list.
12296  *
12297  * @bp: driver handle
12298  *
12299  * We will use zero (0) as a MAC type for these MACs.
12300  */
12301 static int bnx2x_set_uc_list(struct bnx2x *bp)
12302 {
12303         int rc;
12304         struct net_device *dev = bp->dev;
12305         struct netdev_hw_addr *ha;
12306         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
12307         unsigned long ramrod_flags = 0;
12308
12309         /* First schedule a cleanup up of old configuration */
12310         rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12311         if (rc < 0) {
12312                 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12313                 return rc;
12314         }
12315
12316         netdev_for_each_uc_addr(ha, dev) {
12317                 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12318                                        BNX2X_UC_LIST_MAC, &ramrod_flags);
12319                 if (rc == -EEXIST) {
12320                         DP(BNX2X_MSG_SP,
12321                            "Failed to schedule ADD operations: %d\n", rc);
12322                         /* do not treat adding same MAC as error */
12323                         rc = 0;
12324
12325                 } else if (rc < 0) {
12326
12327                         BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12328                                   rc);
12329                         return rc;
12330                 }
12331         }
12332
12333         /* Execute the pending commands */
12334         __set_bit(RAMROD_CONT, &ramrod_flags);
12335         return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12336                                  BNX2X_UC_LIST_MAC, &ramrod_flags);
12337 }
12338
12339 static int bnx2x_set_mc_list(struct bnx2x *bp)
12340 {
12341         struct net_device *dev = bp->dev;
12342         struct bnx2x_mcast_ramrod_params rparam = {NULL};
12343         int rc = 0;
12344
12345         rparam.mcast_obj = &bp->mcast_obj;
12346
12347         /* first, clear all configured multicast MACs */
12348         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12349         if (rc < 0) {
12350                 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
12351                 return rc;
12352         }
12353
12354         /* then, configure a new MACs list */
12355         if (netdev_mc_count(dev)) {
12356                 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
12357                 if (rc) {
12358                         BNX2X_ERR("Failed to create multicast MACs list: %d\n",
12359                                   rc);
12360                         return rc;
12361                 }
12362
12363                 /* Now add the new MACs */
12364                 rc = bnx2x_config_mcast(bp, &rparam,
12365                                         BNX2X_MCAST_CMD_ADD);
12366                 if (rc < 0)
12367                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12368                                   rc);
12369
12370                 bnx2x_free_mcast_macs_list(&rparam);
12371         }
12372
12373         return rc;
12374 }
12375
12376 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
12377 static void bnx2x_set_rx_mode(struct net_device *dev)
12378 {
12379         struct bnx2x *bp = netdev_priv(dev);
12380
12381         if (bp->state != BNX2X_STATE_OPEN) {
12382                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12383                 return;
12384         } else {
12385                 /* Schedule an SP task to handle rest of change */
12386                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12387                                        NETIF_MSG_IFUP);
12388         }
12389 }
12390
12391 void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12392 {
12393         u32 rx_mode = BNX2X_RX_MODE_NORMAL;
12394
12395         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
12396
12397         netif_addr_lock_bh(bp->dev);
12398
12399         if (bp->dev->flags & IFF_PROMISC) {
12400                 rx_mode = BNX2X_RX_MODE_PROMISC;
12401         } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12402                    ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12403                     CHIP_IS_E1(bp))) {
12404                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12405         } else {
12406                 if (IS_PF(bp)) {
12407                         /* some multicasts */
12408                         if (bnx2x_set_mc_list(bp) < 0)
12409                                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12410
12411                         /* release bh lock, as bnx2x_set_uc_list might sleep */
12412                         netif_addr_unlock_bh(bp->dev);
12413                         if (bnx2x_set_uc_list(bp) < 0)
12414                                 rx_mode = BNX2X_RX_MODE_PROMISC;
12415                         netif_addr_lock_bh(bp->dev);
12416                 } else {
12417                         /* configuring mcast to a vf involves sleeping (when we
12418                          * wait for the pf's response).
12419                          */
12420                         bnx2x_schedule_sp_rtnl(bp,
12421                                                BNX2X_SP_RTNL_VFPF_MCAST, 0);
12422                 }
12423         }
12424
12425         bp->rx_mode = rx_mode;
12426         /* handle ISCSI SD mode */
12427         if (IS_MF_ISCSI_ONLY(bp))
12428                 bp->rx_mode = BNX2X_RX_MODE_NONE;
12429
12430         /* Schedule the rx_mode command */
12431         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12432                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
12433                 netif_addr_unlock_bh(bp->dev);
12434                 return;
12435         }
12436
12437         if (IS_PF(bp)) {
12438                 bnx2x_set_storm_rx_mode(bp);
12439                 netif_addr_unlock_bh(bp->dev);
12440         } else {
12441                 /* VF will need to request the PF to make this change, and so
12442                  * the VF needs to release the bottom-half lock prior to the
12443                  * request (as it will likely require sleep on the VF side)
12444                  */
12445                 netif_addr_unlock_bh(bp->dev);
12446                 bnx2x_vfpf_storm_rx_mode(bp);
12447         }
12448 }
12449
12450 /* called with rtnl_lock */
12451 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12452                            int devad, u16 addr)
12453 {
12454         struct bnx2x *bp = netdev_priv(netdev);
12455         u16 value;
12456         int rc;
12457
12458         DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12459            prtad, devad, addr);
12460
12461         /* The HW expects different devad if CL22 is used */
12462         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12463
12464         bnx2x_acquire_phy_lock(bp);
12465         rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
12466         bnx2x_release_phy_lock(bp);
12467         DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
12468
12469         if (!rc)
12470                 rc = value;
12471         return rc;
12472 }
12473
12474 /* called with rtnl_lock */
12475 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12476                             u16 addr, u16 value)
12477 {
12478         struct bnx2x *bp = netdev_priv(netdev);
12479         int rc;
12480
12481         DP(NETIF_MSG_LINK,
12482            "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12483            prtad, devad, addr, value);
12484
12485         /* The HW expects different devad if CL22 is used */
12486         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12487
12488         bnx2x_acquire_phy_lock(bp);
12489         rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
12490         bnx2x_release_phy_lock(bp);
12491         return rc;
12492 }
12493
12494 /* called with rtnl_lock */
12495 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12496 {
12497         struct bnx2x *bp = netdev_priv(dev);
12498         struct mii_ioctl_data *mdio = if_mii(ifr);
12499
12500         if (!netif_running(dev))
12501                 return -EAGAIN;
12502
12503         switch (cmd) {
12504         case SIOCSHWTSTAMP:
12505                 return bnx2x_hwtstamp_ioctl(bp, ifr);
12506         default:
12507                 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12508                    mdio->phy_id, mdio->reg_num, mdio->val_in);
12509                 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12510         }
12511 }
12512
12513 #ifdef CONFIG_NET_POLL_CONTROLLER
12514 static void poll_bnx2x(struct net_device *dev)
12515 {
12516         struct bnx2x *bp = netdev_priv(dev);
12517         int i;
12518
12519         for_each_eth_queue(bp, i) {
12520                 struct bnx2x_fastpath *fp = &bp->fp[i];
12521                 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12522         }
12523 }
12524 #endif
12525
12526 static int bnx2x_validate_addr(struct net_device *dev)
12527 {
12528         struct bnx2x *bp = netdev_priv(dev);
12529
12530         /* query the bulletin board for mac address configured by the PF */
12531         if (IS_VF(bp))
12532                 bnx2x_sample_bulletin(bp);
12533
12534         if (!is_valid_ether_addr(dev->dev_addr)) {
12535                 BNX2X_ERR("Non-valid Ethernet address\n");
12536                 return -EADDRNOTAVAIL;
12537         }
12538         return 0;
12539 }
12540
12541 static int bnx2x_get_phys_port_id(struct net_device *netdev,
12542                                   struct netdev_phys_item_id *ppid)
12543 {
12544         struct bnx2x *bp = netdev_priv(netdev);
12545
12546         if (!(bp->flags & HAS_PHYS_PORT_ID))
12547                 return -EOPNOTSUPP;
12548
12549         ppid->id_len = sizeof(bp->phys_port_id);
12550         memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12551
12552         return 0;
12553 }
12554
12555 static const struct net_device_ops bnx2x_netdev_ops = {
12556         .ndo_open               = bnx2x_open,
12557         .ndo_stop               = bnx2x_close,
12558         .ndo_start_xmit         = bnx2x_start_xmit,
12559         .ndo_select_queue       = bnx2x_select_queue,
12560         .ndo_set_rx_mode        = bnx2x_set_rx_mode,
12561         .ndo_set_mac_address    = bnx2x_change_mac_addr,
12562         .ndo_validate_addr      = bnx2x_validate_addr,
12563         .ndo_do_ioctl           = bnx2x_ioctl,
12564         .ndo_change_mtu         = bnx2x_change_mtu,
12565         .ndo_fix_features       = bnx2x_fix_features,
12566         .ndo_set_features       = bnx2x_set_features,
12567         .ndo_tx_timeout         = bnx2x_tx_timeout,
12568 #ifdef CONFIG_NET_POLL_CONTROLLER
12569         .ndo_poll_controller    = poll_bnx2x,
12570 #endif
12571         .ndo_setup_tc           = bnx2x_setup_tc,
12572 #ifdef CONFIG_BNX2X_SRIOV
12573         .ndo_set_vf_mac         = bnx2x_set_vf_mac,
12574         .ndo_set_vf_vlan        = bnx2x_set_vf_vlan,
12575         .ndo_get_vf_config      = bnx2x_get_vf_config,
12576 #endif
12577 #ifdef NETDEV_FCOE_WWNN
12578         .ndo_fcoe_get_wwn       = bnx2x_fcoe_get_wwn,
12579 #endif
12580
12581 #ifdef CONFIG_NET_RX_BUSY_POLL
12582         .ndo_busy_poll          = bnx2x_low_latency_recv,
12583 #endif
12584         .ndo_get_phys_port_id   = bnx2x_get_phys_port_id,
12585         .ndo_set_vf_link_state  = bnx2x_set_vf_link_state,
12586 };
12587
12588 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
12589 {
12590         struct device *dev = &bp->pdev->dev;
12591
12592         if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
12593             dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
12594                 dev_err(dev, "System does not support DMA, aborting\n");
12595                 return -EIO;
12596         }
12597
12598         return 0;
12599 }
12600
12601 static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
12602 {
12603         if (bp->flags & AER_ENABLED) {
12604                 pci_disable_pcie_error_reporting(bp->pdev);
12605                 bp->flags &= ~AER_ENABLED;
12606         }
12607 }
12608
12609 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
12610                           struct net_device *dev, unsigned long board_type)
12611 {
12612         int rc;
12613         u32 pci_cfg_dword;
12614         bool chip_is_e1x = (board_type == BCM57710 ||
12615                             board_type == BCM57711 ||
12616                             board_type == BCM57711E);
12617
12618         SET_NETDEV_DEV(dev, &pdev->dev);
12619
12620         bp->dev = dev;
12621         bp->pdev = pdev;
12622
12623         rc = pci_enable_device(pdev);
12624         if (rc) {
12625                 dev_err(&bp->pdev->dev,
12626                         "Cannot enable PCI device, aborting\n");
12627                 goto err_out;
12628         }
12629
12630         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12631                 dev_err(&bp->pdev->dev,
12632                         "Cannot find PCI device base address, aborting\n");
12633                 rc = -ENODEV;
12634                 goto err_out_disable;
12635         }
12636
12637         if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12638                 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
12639                 rc = -ENODEV;
12640                 goto err_out_disable;
12641         }
12642
12643         pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
12644         if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
12645             PCICFG_REVESION_ID_ERROR_VAL) {
12646                 pr_err("PCI device error, probably due to fan failure, aborting\n");
12647                 rc = -ENODEV;
12648                 goto err_out_disable;
12649         }
12650
12651         if (atomic_read(&pdev->enable_cnt) == 1) {
12652                 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12653                 if (rc) {
12654                         dev_err(&bp->pdev->dev,
12655                                 "Cannot obtain PCI resources, aborting\n");
12656                         goto err_out_disable;
12657                 }
12658
12659                 pci_set_master(pdev);
12660                 pci_save_state(pdev);
12661         }
12662
12663         if (IS_PF(bp)) {
12664                 if (!pdev->pm_cap) {
12665                         dev_err(&bp->pdev->dev,
12666                                 "Cannot find power management capability, aborting\n");
12667                         rc = -EIO;
12668                         goto err_out_release;
12669                 }
12670         }
12671
12672         if (!pci_is_pcie(pdev)) {
12673                 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
12674                 rc = -EIO;
12675                 goto err_out_release;
12676         }
12677
12678         rc = bnx2x_set_coherency_mask(bp);
12679         if (rc)
12680                 goto err_out_release;
12681
12682         dev->mem_start = pci_resource_start(pdev, 0);
12683         dev->base_addr = dev->mem_start;
12684         dev->mem_end = pci_resource_end(pdev, 0);
12685
12686         dev->irq = pdev->irq;
12687
12688         bp->regview = pci_ioremap_bar(pdev, 0);
12689         if (!bp->regview) {
12690                 dev_err(&bp->pdev->dev,
12691                         "Cannot map register space, aborting\n");
12692                 rc = -ENOMEM;
12693                 goto err_out_release;
12694         }
12695
12696         /* In E1/E1H use pci device function given by kernel.
12697          * In E2/E3 read physical function from ME register since these chips
12698          * support Physical Device Assignment where kernel BDF maybe arbitrary
12699          * (depending on hypervisor).
12700          */
12701         if (chip_is_e1x) {
12702                 bp->pf_num = PCI_FUNC(pdev->devfn);
12703         } else {
12704                 /* chip is E2/3*/
12705                 pci_read_config_dword(bp->pdev,
12706                                       PCICFG_ME_REGISTER, &pci_cfg_dword);
12707                 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
12708                                   ME_REG_ABS_PF_NUM_SHIFT);
12709         }
12710         BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
12711
12712         /* clean indirect addresses */
12713         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
12714                                PCICFG_VENDOR_ID_OFFSET);
12715
12716         /* AER (Advanced Error reporting) configuration */
12717         rc = pci_enable_pcie_error_reporting(pdev);
12718         if (!rc)
12719                 bp->flags |= AER_ENABLED;
12720         else
12721                 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
12722
12723         /*
12724          * Clean the following indirect addresses for all functions since it
12725          * is not used by the driver.
12726          */
12727         if (IS_PF(bp)) {
12728                 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
12729                 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
12730                 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12731                 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12732
12733                 if (chip_is_e1x) {
12734                         REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12735                         REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12736                         REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12737                         REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12738                 }
12739
12740                 /* Enable internal target-read (in case we are probed after PF
12741                  * FLR). Must be done prior to any BAR read access. Only for
12742                  * 57712 and up
12743                  */
12744                 if (!chip_is_e1x)
12745                         REG_WR(bp,
12746                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
12747         }
12748
12749         dev->watchdog_timeo = TX_TIMEOUT;
12750
12751         dev->netdev_ops = &bnx2x_netdev_ops;
12752         bnx2x_set_ethtool_ops(bp, dev);
12753
12754         dev->priv_flags |= IFF_UNICAST_FLT;
12755
12756         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12757                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12758                 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
12759                 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
12760         if (!CHIP_IS_E1x(bp)) {
12761                 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
12762                                     NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
12763                 dev->hw_enc_features =
12764                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12765                         NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12766                         NETIF_F_GSO_IPIP |
12767                         NETIF_F_GSO_SIT |
12768                         NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
12769         }
12770
12771         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12772                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12773
12774         dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
12775         dev->features |= NETIF_F_HIGHDMA;
12776
12777         /* Add Loopback capability to the device */
12778         dev->hw_features |= NETIF_F_LOOPBACK;
12779
12780 #ifdef BCM_DCBNL
12781         dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12782 #endif
12783
12784         /* get_port_hwinfo() will set prtad and mmds properly */
12785         bp->mdio.prtad = MDIO_PRTAD_NONE;
12786         bp->mdio.mmds = 0;
12787         bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12788         bp->mdio.dev = dev;
12789         bp->mdio.mdio_read = bnx2x_mdio_read;
12790         bp->mdio.mdio_write = bnx2x_mdio_write;
12791
12792         return 0;
12793
12794 err_out_release:
12795         if (atomic_read(&pdev->enable_cnt) == 1)
12796                 pci_release_regions(pdev);
12797
12798 err_out_disable:
12799         pci_disable_device(pdev);
12800
12801 err_out:
12802         return rc;
12803 }
12804
12805 static int bnx2x_check_firmware(struct bnx2x *bp)
12806 {
12807         const struct firmware *firmware = bp->firmware;
12808         struct bnx2x_fw_file_hdr *fw_hdr;
12809         struct bnx2x_fw_file_section *sections;
12810         u32 offset, len, num_ops;
12811         __be16 *ops_offsets;
12812         int i;
12813         const u8 *fw_ver;
12814
12815         if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12816                 BNX2X_ERR("Wrong FW size\n");
12817                 return -EINVAL;
12818         }
12819
12820         fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12821         sections = (struct bnx2x_fw_file_section *)fw_hdr;
12822
12823         /* Make sure none of the offsets and sizes make us read beyond
12824          * the end of the firmware data */
12825         for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12826                 offset = be32_to_cpu(sections[i].offset);
12827                 len = be32_to_cpu(sections[i].len);
12828                 if (offset + len > firmware->size) {
12829                         BNX2X_ERR("Section %d length is out of bounds\n", i);
12830                         return -EINVAL;
12831                 }
12832         }
12833
12834         /* Likewise for the init_ops offsets */
12835         offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
12836         ops_offsets = (__force __be16 *)(firmware->data + offset);
12837         num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12838
12839         for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12840                 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
12841                         BNX2X_ERR("Section offset %d is out of bounds\n", i);
12842                         return -EINVAL;
12843                 }
12844         }
12845
12846         /* Check FW version */
12847         offset = be32_to_cpu(fw_hdr->fw_version.offset);
12848         fw_ver = firmware->data + offset;
12849         if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12850             (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12851             (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12852             (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
12853                 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12854                        fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12855                        BCM_5710_FW_MAJOR_VERSION,
12856                        BCM_5710_FW_MINOR_VERSION,
12857                        BCM_5710_FW_REVISION_VERSION,
12858                        BCM_5710_FW_ENGINEERING_VERSION);
12859                 return -EINVAL;
12860         }
12861
12862         return 0;
12863 }
12864
12865 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12866 {
12867         const __be32 *source = (const __be32 *)_source;
12868         u32 *target = (u32 *)_target;
12869         u32 i;
12870
12871         for (i = 0; i < n/4; i++)
12872                 target[i] = be32_to_cpu(source[i]);
12873 }
12874
12875 /*
12876    Ops array is stored in the following format:
12877    {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12878  */
12879 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
12880 {
12881         const __be32 *source = (const __be32 *)_source;
12882         struct raw_op *target = (struct raw_op *)_target;
12883         u32 i, j, tmp;
12884
12885         for (i = 0, j = 0; i < n/8; i++, j += 2) {
12886                 tmp = be32_to_cpu(source[j]);
12887                 target[i].op = (tmp >> 24) & 0xff;
12888                 target[i].offset = tmp & 0xffffff;
12889                 target[i].raw_data = be32_to_cpu(source[j + 1]);
12890         }
12891 }
12892
12893 /* IRO array is stored in the following format:
12894  * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12895  */
12896 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
12897 {
12898         const __be32 *source = (const __be32 *)_source;
12899         struct iro *target = (struct iro *)_target;
12900         u32 i, j, tmp;
12901
12902         for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12903                 target[i].base = be32_to_cpu(source[j]);
12904                 j++;
12905                 tmp = be32_to_cpu(source[j]);
12906                 target[i].m1 = (tmp >> 16) & 0xffff;
12907                 target[i].m2 = tmp & 0xffff;
12908                 j++;
12909                 tmp = be32_to_cpu(source[j]);
12910                 target[i].m3 = (tmp >> 16) & 0xffff;
12911                 target[i].size = tmp & 0xffff;
12912                 j++;
12913         }
12914 }
12915
12916 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12917 {
12918         const __be16 *source = (const __be16 *)_source;
12919         u16 *target = (u16 *)_target;
12920         u32 i;
12921
12922         for (i = 0; i < n/2; i++)
12923                 target[i] = be16_to_cpu(source[i]);
12924 }
12925
12926 #define BNX2X_ALLOC_AND_SET(arr, lbl, func)                             \
12927 do {                                                                    \
12928         u32 len = be32_to_cpu(fw_hdr->arr.len);                         \
12929         bp->arr = kmalloc(len, GFP_KERNEL);                             \
12930         if (!bp->arr)                                                   \
12931                 goto lbl;                                               \
12932         func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset),      \
12933              (u8 *)bp->arr, len);                                       \
12934 } while (0)
12935
12936 static int bnx2x_init_firmware(struct bnx2x *bp)
12937 {
12938         const char *fw_file_name;
12939         struct bnx2x_fw_file_hdr *fw_hdr;
12940         int rc;
12941
12942         if (bp->firmware)
12943                 return 0;
12944
12945         if (CHIP_IS_E1(bp))
12946                 fw_file_name = FW_FILE_NAME_E1;
12947         else if (CHIP_IS_E1H(bp))
12948                 fw_file_name = FW_FILE_NAME_E1H;
12949         else if (!CHIP_IS_E1x(bp))
12950                 fw_file_name = FW_FILE_NAME_E2;
12951         else {
12952                 BNX2X_ERR("Unsupported chip revision\n");
12953                 return -EINVAL;
12954         }
12955         BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
12956
12957         rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12958         if (rc) {
12959                 BNX2X_ERR("Can't load firmware file %s\n",
12960                           fw_file_name);
12961                 goto request_firmware_exit;
12962         }
12963
12964         rc = bnx2x_check_firmware(bp);
12965         if (rc) {
12966                 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12967                 goto request_firmware_exit;
12968         }
12969
12970         fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12971
12972         /* Initialize the pointers to the init arrays */
12973         /* Blob */
12974         BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12975
12976         /* Opcodes */
12977         BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12978
12979         /* Offsets */
12980         BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12981                             be16_to_cpu_n);
12982
12983         /* STORMs firmware */
12984         INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12985                         be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12986         INIT_TSEM_PRAM_DATA(bp)      = bp->firmware->data +
12987                         be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12988         INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12989                         be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12990         INIT_USEM_PRAM_DATA(bp)      = bp->firmware->data +
12991                         be32_to_cpu(fw_hdr->usem_pram_data.offset);
12992         INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12993                         be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12994         INIT_XSEM_PRAM_DATA(bp)      = bp->firmware->data +
12995                         be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12996         INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12997                         be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12998         INIT_CSEM_PRAM_DATA(bp)      = bp->firmware->data +
12999                         be32_to_cpu(fw_hdr->csem_pram_data.offset);
13000         /* IRO */
13001         BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
13002
13003         return 0;
13004
13005 iro_alloc_err:
13006         kfree(bp->init_ops_offsets);
13007 init_offsets_alloc_err:
13008         kfree(bp->init_ops);
13009 init_ops_alloc_err:
13010         kfree(bp->init_data);
13011 request_firmware_exit:
13012         release_firmware(bp->firmware);
13013         bp->firmware = NULL;
13014
13015         return rc;
13016 }
13017
13018 static void bnx2x_release_firmware(struct bnx2x *bp)
13019 {
13020         kfree(bp->init_ops_offsets);
13021         kfree(bp->init_ops);
13022         kfree(bp->init_data);
13023         release_firmware(bp->firmware);
13024         bp->firmware = NULL;
13025 }
13026
13027 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
13028         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
13029         .init_hw_cmn      = bnx2x_init_hw_common,
13030         .init_hw_port     = bnx2x_init_hw_port,
13031         .init_hw_func     = bnx2x_init_hw_func,
13032
13033         .reset_hw_cmn     = bnx2x_reset_common,
13034         .reset_hw_port    = bnx2x_reset_port,
13035         .reset_hw_func    = bnx2x_reset_func,
13036
13037         .gunzip_init      = bnx2x_gunzip_init,
13038         .gunzip_end       = bnx2x_gunzip_end,
13039
13040         .init_fw          = bnx2x_init_firmware,
13041         .release_fw       = bnx2x_release_firmware,
13042 };
13043
13044 void bnx2x__init_func_obj(struct bnx2x *bp)
13045 {
13046         /* Prepare DMAE related driver resources */
13047         bnx2x_setup_dmae(bp);
13048
13049         bnx2x_init_func_obj(bp, &bp->func_obj,
13050                             bnx2x_sp(bp, func_rdata),
13051                             bnx2x_sp_mapping(bp, func_rdata),
13052                             bnx2x_sp(bp, func_afex_rdata),
13053                             bnx2x_sp_mapping(bp, func_afex_rdata),
13054                             &bnx2x_func_sp_drv);
13055 }
13056
13057 /* must be called after sriov-enable */
13058 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
13059 {
13060         int cid_count = BNX2X_L2_MAX_CID(bp);
13061
13062         if (IS_SRIOV(bp))
13063                 cid_count += BNX2X_VF_CIDS;
13064
13065         if (CNIC_SUPPORT(bp))
13066                 cid_count += CNIC_CID_MAX;
13067
13068         return roundup(cid_count, QM_CID_ROUND);
13069 }
13070
13071 /**
13072  * bnx2x_get_num_none_def_sbs - return the number of none default SBs
13073  *
13074  * @dev:        pci device
13075  *
13076  */
13077 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
13078 {
13079         int index;
13080         u16 control = 0;
13081
13082         /*
13083          * If MSI-X is not supported - return number of SBs needed to support
13084          * one fast path queue: one FP queue + SB for CNIC
13085          */
13086         if (!pdev->msix_cap) {
13087                 dev_info(&pdev->dev, "no msix capability found\n");
13088                 return 1 + cnic_cnt;
13089         }
13090         dev_info(&pdev->dev, "msix capability found\n");
13091
13092         /*
13093          * The value in the PCI configuration space is the index of the last
13094          * entry, namely one less than the actual size of the table, which is
13095          * exactly what we want to return from this function: number of all SBs
13096          * without the default SB.
13097          * For VFs there is no default SB, then we return (index+1).
13098          */
13099         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
13100
13101         index = control & PCI_MSIX_FLAGS_QSIZE;
13102
13103         return index;
13104 }
13105
13106 static int set_max_cos_est(int chip_id)
13107 {
13108         switch (chip_id) {
13109         case BCM57710:
13110         case BCM57711:
13111         case BCM57711E:
13112                 return BNX2X_MULTI_TX_COS_E1X;
13113         case BCM57712:
13114         case BCM57712_MF:
13115                 return BNX2X_MULTI_TX_COS_E2_E3A0;
13116         case BCM57800:
13117         case BCM57800_MF:
13118         case BCM57810:
13119         case BCM57810_MF:
13120         case BCM57840_4_10:
13121         case BCM57840_2_20:
13122         case BCM57840_O:
13123         case BCM57840_MFO:
13124         case BCM57840_MF:
13125         case BCM57811:
13126         case BCM57811_MF:
13127                 return BNX2X_MULTI_TX_COS_E3B0;
13128         case BCM57712_VF:
13129         case BCM57800_VF:
13130         case BCM57810_VF:
13131         case BCM57840_VF:
13132         case BCM57811_VF:
13133                 return 1;
13134         default:
13135                 pr_err("Unknown board_type (%d), aborting\n", chip_id);
13136                 return -ENODEV;
13137         }
13138 }
13139
13140 static int set_is_vf(int chip_id)
13141 {
13142         switch (chip_id) {
13143         case BCM57712_VF:
13144         case BCM57800_VF:
13145         case BCM57810_VF:
13146         case BCM57840_VF:
13147         case BCM57811_VF:
13148                 return true;
13149         default:
13150                 return false;
13151         }
13152 }
13153
13154 /* nig_tsgen registers relative address */
13155 #define tsgen_ctrl 0x0
13156 #define tsgen_freecount 0x10
13157 #define tsgen_synctime_t0 0x20
13158 #define tsgen_offset_t0 0x28
13159 #define tsgen_drift_t0 0x30
13160 #define tsgen_synctime_t1 0x58
13161 #define tsgen_offset_t1 0x60
13162 #define tsgen_drift_t1 0x68
13163
13164 /* FW workaround for setting drift */
13165 static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
13166                                           int best_val, int best_period)
13167 {
13168         struct bnx2x_func_state_params func_params = {NULL};
13169         struct bnx2x_func_set_timesync_params *set_timesync_params =
13170                 &func_params.params.set_timesync;
13171
13172         /* Prepare parameters for function state transitions */
13173         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
13174         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
13175
13176         func_params.f_obj = &bp->func_obj;
13177         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
13178
13179         /* Function parameters */
13180         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
13181         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
13182         set_timesync_params->add_sub_drift_adjust_value =
13183                 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
13184         set_timesync_params->drift_adjust_value = best_val;
13185         set_timesync_params->drift_adjust_period = best_period;
13186
13187         return bnx2x_func_state_change(bp, &func_params);
13188 }
13189
13190 static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
13191 {
13192         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13193         int rc;
13194         int drift_dir = 1;
13195         int val, period, period1, period2, dif, dif1, dif2;
13196         int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
13197
13198         DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
13199
13200         if (!netif_running(bp->dev)) {
13201                 DP(BNX2X_MSG_PTP,
13202                    "PTP adjfreq called while the interface is down\n");
13203                 return -EFAULT;
13204         }
13205
13206         if (ppb < 0) {
13207                 ppb = -ppb;
13208                 drift_dir = 0;
13209         }
13210
13211         if (ppb == 0) {
13212                 best_val = 1;
13213                 best_period = 0x1FFFFFF;
13214         } else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
13215                 best_val = 31;
13216                 best_period = 1;
13217         } else {
13218                 /* Changed not to allow val = 8, 16, 24 as these values
13219                  * are not supported in workaround.
13220                  */
13221                 for (val = 0; val <= 31; val++) {
13222                         if ((val & 0x7) == 0)
13223                                 continue;
13224                         period1 = val * 1000000 / ppb;
13225                         period2 = period1 + 1;
13226                         if (period1 != 0)
13227                                 dif1 = ppb - (val * 1000000 / period1);
13228                         else
13229                                 dif1 = BNX2X_MAX_PHC_DRIFT;
13230                         if (dif1 < 0)
13231                                 dif1 = -dif1;
13232                         dif2 = ppb - (val * 1000000 / period2);
13233                         if (dif2 < 0)
13234                                 dif2 = -dif2;
13235                         dif = (dif1 < dif2) ? dif1 : dif2;
13236                         period = (dif1 < dif2) ? period1 : period2;
13237                         if (dif < best_dif) {
13238                                 best_dif = dif;
13239                                 best_val = val;
13240                                 best_period = period;
13241                         }
13242                 }
13243         }
13244
13245         rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
13246                                             best_period);
13247         if (rc) {
13248                 BNX2X_ERR("Failed to set drift\n");
13249                 return -EFAULT;
13250         }
13251
13252         DP(BNX2X_MSG_PTP, "Configrued val = %d, period = %d\n", best_val,
13253            best_period);
13254
13255         return 0;
13256 }
13257
13258 static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
13259 {
13260         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13261         u64 now;
13262
13263         DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
13264
13265         now = timecounter_read(&bp->timecounter);
13266         now += delta;
13267         /* Re-init the timecounter */
13268         timecounter_init(&bp->timecounter, &bp->cyclecounter, now);
13269
13270         return 0;
13271 }
13272
13273 static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
13274 {
13275         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13276         u64 ns;
13277         u32 remainder;
13278
13279         ns = timecounter_read(&bp->timecounter);
13280
13281         DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
13282
13283         ts->tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder);
13284         ts->tv_nsec = remainder;
13285
13286         return 0;
13287 }
13288
13289 static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
13290                              const struct timespec *ts)
13291 {
13292         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13293         u64 ns;
13294
13295         ns = ts->tv_sec * 1000000000ULL;
13296         ns += ts->tv_nsec;
13297
13298         DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
13299
13300         /* Re-init the timecounter */
13301         timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
13302
13303         return 0;
13304 }
13305
13306 /* Enable (or disable) ancillary features of the phc subsystem */
13307 static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
13308                             struct ptp_clock_request *rq, int on)
13309 {
13310         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13311
13312         BNX2X_ERR("PHC ancillary features are not supported\n");
13313         return -ENOTSUPP;
13314 }
13315
13316 void bnx2x_register_phc(struct bnx2x *bp)
13317 {
13318         /* Fill the ptp_clock_info struct and register PTP clock*/
13319         bp->ptp_clock_info.owner = THIS_MODULE;
13320         snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
13321         bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
13322         bp->ptp_clock_info.n_alarm = 0;
13323         bp->ptp_clock_info.n_ext_ts = 0;
13324         bp->ptp_clock_info.n_per_out = 0;
13325         bp->ptp_clock_info.pps = 0;
13326         bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
13327         bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
13328         bp->ptp_clock_info.gettime = bnx2x_ptp_gettime;
13329         bp->ptp_clock_info.settime = bnx2x_ptp_settime;
13330         bp->ptp_clock_info.enable = bnx2x_ptp_enable;
13331
13332         bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
13333         if (IS_ERR(bp->ptp_clock)) {
13334                 bp->ptp_clock = NULL;
13335                 BNX2X_ERR("PTP clock registeration failed\n");
13336         }
13337 }
13338
13339 static int bnx2x_init_one(struct pci_dev *pdev,
13340                                     const struct pci_device_id *ent)
13341 {
13342         struct net_device *dev = NULL;
13343         struct bnx2x *bp;
13344         enum pcie_link_width pcie_width;
13345         enum pci_bus_speed pcie_speed;
13346         int rc, max_non_def_sbs;
13347         int rx_count, tx_count, rss_count, doorbell_size;
13348         int max_cos_est;
13349         bool is_vf;
13350         int cnic_cnt;
13351
13352         /* An estimated maximum supported CoS number according to the chip
13353          * version.
13354          * We will try to roughly estimate the maximum number of CoSes this chip
13355          * may support in order to minimize the memory allocated for Tx
13356          * netdev_queue's. This number will be accurately calculated during the
13357          * initialization of bp->max_cos based on the chip versions AND chip
13358          * revision in the bnx2x_init_bp().
13359          */
13360         max_cos_est = set_max_cos_est(ent->driver_data);
13361         if (max_cos_est < 0)
13362                 return max_cos_est;
13363         is_vf = set_is_vf(ent->driver_data);
13364         cnic_cnt = is_vf ? 0 : 1;
13365
13366         max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13367
13368         /* add another SB for VF as it has no default SB */
13369         max_non_def_sbs += is_vf ? 1 : 0;
13370
13371         /* Maximum number of RSS queues: one IGU SB goes to CNIC */
13372         rss_count = max_non_def_sbs - cnic_cnt;
13373
13374         if (rss_count < 1)
13375                 return -EINVAL;
13376
13377         /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
13378         rx_count = rss_count + cnic_cnt;
13379
13380         /* Maximum number of netdev Tx queues:
13381          * Maximum TSS queues * Maximum supported number of CoS  + FCoE L2
13382          */
13383         tx_count = rss_count * max_cos_est + cnic_cnt;
13384
13385         /* dev zeroed in init_etherdev */
13386         dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
13387         if (!dev)
13388                 return -ENOMEM;
13389
13390         bp = netdev_priv(dev);
13391
13392         bp->flags = 0;
13393         if (is_vf)
13394                 bp->flags |= IS_VF_FLAG;
13395
13396         bp->igu_sb_cnt = max_non_def_sbs;
13397         bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
13398         bp->msg_enable = debug;
13399         bp->cnic_support = cnic_cnt;
13400         bp->cnic_probe = bnx2x_cnic_probe;
13401
13402         pci_set_drvdata(pdev, dev);
13403
13404         rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
13405         if (rc < 0) {
13406                 free_netdev(dev);
13407                 return rc;
13408         }
13409
13410         BNX2X_DEV_INFO("This is a %s function\n",
13411                        IS_PF(bp) ? "physical" : "virtual");
13412         BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
13413         BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
13414         BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
13415                        tx_count, rx_count);
13416
13417         rc = bnx2x_init_bp(bp);
13418         if (rc)
13419                 goto init_one_exit;
13420
13421         /* Map doorbells here as we need the real value of bp->max_cos which
13422          * is initialized in bnx2x_init_bp() to determine the number of
13423          * l2 connections.
13424          */
13425         if (IS_VF(bp)) {
13426                 bp->doorbells = bnx2x_vf_doorbells(bp);
13427                 rc = bnx2x_vf_pci_alloc(bp);
13428                 if (rc)
13429                         goto init_one_exit;
13430         } else {
13431                 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
13432                 if (doorbell_size > pci_resource_len(pdev, 2)) {
13433                         dev_err(&bp->pdev->dev,
13434                                 "Cannot map doorbells, bar size too small, aborting\n");
13435                         rc = -ENOMEM;
13436                         goto init_one_exit;
13437                 }
13438                 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
13439                                                 doorbell_size);
13440         }
13441         if (!bp->doorbells) {
13442                 dev_err(&bp->pdev->dev,
13443                         "Cannot map doorbell space, aborting\n");
13444                 rc = -ENOMEM;
13445                 goto init_one_exit;
13446         }
13447
13448         if (IS_VF(bp)) {
13449                 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
13450                 if (rc)
13451                         goto init_one_exit;
13452         }
13453
13454         /* Enable SRIOV if capability found in configuration space */
13455         rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
13456         if (rc)
13457                 goto init_one_exit;
13458
13459         /* calc qm_cid_count */
13460         bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
13461         BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
13462
13463         /* disable FCOE L2 queue for E1x*/
13464         if (CHIP_IS_E1x(bp))
13465                 bp->flags |= NO_FCOE_FLAG;
13466
13467         /* Set bp->num_queues for MSI-X mode*/
13468         bnx2x_set_num_queues(bp);
13469
13470         /* Configure interrupt mode: try to enable MSI-X/MSI if
13471          * needed.
13472          */
13473         rc = bnx2x_set_int_mode(bp);
13474         if (rc) {
13475                 dev_err(&pdev->dev, "Cannot set interrupts\n");
13476                 goto init_one_exit;
13477         }
13478         BNX2X_DEV_INFO("set interrupts successfully\n");
13479
13480         /* register the net device */
13481         rc = register_netdev(dev);
13482         if (rc) {
13483                 dev_err(&pdev->dev, "Cannot register net device\n");
13484                 goto init_one_exit;
13485         }
13486         BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
13487
13488         if (!NO_FCOE(bp)) {
13489                 /* Add storage MAC address */
13490                 rtnl_lock();
13491                 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13492                 rtnl_unlock();
13493         }
13494         if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
13495             pcie_speed == PCI_SPEED_UNKNOWN ||
13496             pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
13497                 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
13498         else
13499                 BNX2X_DEV_INFO(
13500                        "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
13501                        board_info[ent->driver_data].name,
13502                        (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
13503                        pcie_width,
13504                        pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
13505                        pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
13506                        pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
13507                        "Unknown",
13508                        dev->base_addr, bp->pdev->irq, dev->dev_addr);
13509
13510         bnx2x_register_phc(bp);
13511
13512         return 0;
13513
13514 init_one_exit:
13515         bnx2x_disable_pcie_error_reporting(bp);
13516
13517         if (bp->regview)
13518                 iounmap(bp->regview);
13519
13520         if (IS_PF(bp) && bp->doorbells)
13521                 iounmap(bp->doorbells);
13522
13523         free_netdev(dev);
13524
13525         if (atomic_read(&pdev->enable_cnt) == 1)
13526                 pci_release_regions(pdev);
13527
13528         pci_disable_device(pdev);
13529
13530         return rc;
13531 }
13532
13533 static void __bnx2x_remove(struct pci_dev *pdev,
13534                            struct net_device *dev,
13535                            struct bnx2x *bp,
13536                            bool remove_netdev)
13537 {
13538         if (bp->ptp_clock) {
13539                 ptp_clock_unregister(bp->ptp_clock);
13540                 bp->ptp_clock = NULL;
13541         }
13542
13543         /* Delete storage MAC address */
13544         if (!NO_FCOE(bp)) {
13545                 rtnl_lock();
13546                 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13547                 rtnl_unlock();
13548         }
13549
13550 #ifdef BCM_DCBNL
13551         /* Delete app tlvs from dcbnl */
13552         bnx2x_dcbnl_update_applist(bp, true);
13553 #endif
13554
13555         if (IS_PF(bp) &&
13556             !BP_NOMCP(bp) &&
13557             (bp->flags & BC_SUPPORTS_RMMOD_CMD))
13558                 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
13559
13560         /* Close the interface - either directly or implicitly */
13561         if (remove_netdev) {
13562                 unregister_netdev(dev);
13563         } else {
13564                 rtnl_lock();
13565                 dev_close(dev);
13566                 rtnl_unlock();
13567         }
13568
13569         bnx2x_iov_remove_one(bp);
13570
13571         /* Power on: we can't let PCI layer write to us while we are in D3 */
13572         if (IS_PF(bp)) {
13573                 bnx2x_set_power_state(bp, PCI_D0);
13574
13575                 /* Set endianity registers to reset values in case next driver
13576                  * boots in different endianty environment.
13577                  */
13578                 bnx2x_reset_endianity(bp);
13579         }
13580
13581         /* Disable MSI/MSI-X */
13582         bnx2x_disable_msi(bp);
13583
13584         /* Power off */
13585         if (IS_PF(bp))
13586                 bnx2x_set_power_state(bp, PCI_D3hot);
13587
13588         /* Make sure RESET task is not scheduled before continuing */
13589         cancel_delayed_work_sync(&bp->sp_rtnl_task);
13590
13591         /* send message via vfpf channel to release the resources of this vf */
13592         if (IS_VF(bp))
13593                 bnx2x_vfpf_release(bp);
13594
13595         /* Assumes no further PCIe PM changes will occur */
13596         if (system_state == SYSTEM_POWER_OFF) {
13597                 pci_wake_from_d3(pdev, bp->wol);
13598                 pci_set_power_state(pdev, PCI_D3hot);
13599         }
13600
13601         bnx2x_disable_pcie_error_reporting(bp);
13602         if (remove_netdev) {
13603                 if (bp->regview)
13604                         iounmap(bp->regview);
13605
13606                 /* For vfs, doorbells are part of the regview and were unmapped
13607                  * along with it. FW is only loaded by PF.
13608                  */
13609                 if (IS_PF(bp)) {
13610                         if (bp->doorbells)
13611                                 iounmap(bp->doorbells);
13612
13613                         bnx2x_release_firmware(bp);
13614                 } else {
13615                         bnx2x_vf_pci_dealloc(bp);
13616                 }
13617                 bnx2x_free_mem_bp(bp);
13618
13619                 free_netdev(dev);
13620
13621                 if (atomic_read(&pdev->enable_cnt) == 1)
13622                         pci_release_regions(pdev);
13623
13624                 pci_disable_device(pdev);
13625         }
13626 }
13627
13628 static void bnx2x_remove_one(struct pci_dev *pdev)
13629 {
13630         struct net_device *dev = pci_get_drvdata(pdev);
13631         struct bnx2x *bp;
13632
13633         if (!dev) {
13634                 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
13635                 return;
13636         }
13637         bp = netdev_priv(dev);
13638
13639         __bnx2x_remove(pdev, dev, bp, true);
13640 }
13641
13642 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
13643 {
13644         bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
13645
13646         bp->rx_mode = BNX2X_RX_MODE_NONE;
13647
13648         if (CNIC_LOADED(bp))
13649                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
13650
13651         /* Stop Tx */
13652         bnx2x_tx_disable(bp);
13653         /* Delete all NAPI objects */
13654         bnx2x_del_all_napi(bp);
13655         if (CNIC_LOADED(bp))
13656                 bnx2x_del_all_napi_cnic(bp);
13657         netdev_reset_tc(bp->dev);
13658
13659         del_timer_sync(&bp->timer);
13660         cancel_delayed_work_sync(&bp->sp_task);
13661         cancel_delayed_work_sync(&bp->period_task);
13662
13663         spin_lock_bh(&bp->stats_lock);
13664         bp->stats_state = STATS_STATE_DISABLED;
13665         spin_unlock_bh(&bp->stats_lock);
13666
13667         bnx2x_save_statistics(bp);
13668
13669         netif_carrier_off(bp->dev);
13670
13671         return 0;
13672 }
13673
13674 /**
13675  * bnx2x_io_error_detected - called when PCI error is detected
13676  * @pdev: Pointer to PCI device
13677  * @state: The current pci connection state
13678  *
13679  * This function is called after a PCI bus error affecting
13680  * this device has been detected.
13681  */
13682 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
13683                                                 pci_channel_state_t state)
13684 {
13685         struct net_device *dev = pci_get_drvdata(pdev);
13686         struct bnx2x *bp = netdev_priv(dev);
13687
13688         rtnl_lock();
13689
13690         BNX2X_ERR("IO error detected\n");
13691
13692         netif_device_detach(dev);
13693
13694         if (state == pci_channel_io_perm_failure) {
13695                 rtnl_unlock();
13696                 return PCI_ERS_RESULT_DISCONNECT;
13697         }
13698
13699         if (netif_running(dev))
13700                 bnx2x_eeh_nic_unload(bp);
13701
13702         bnx2x_prev_path_mark_eeh(bp);
13703
13704         pci_disable_device(pdev);
13705
13706         rtnl_unlock();
13707
13708         /* Request a slot reset */
13709         return PCI_ERS_RESULT_NEED_RESET;
13710 }
13711
13712 /**
13713  * bnx2x_io_slot_reset - called after the PCI bus has been reset
13714  * @pdev: Pointer to PCI device
13715  *
13716  * Restart the card from scratch, as if from a cold-boot.
13717  */
13718 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
13719 {
13720         struct net_device *dev = pci_get_drvdata(pdev);
13721         struct bnx2x *bp = netdev_priv(dev);
13722         int i;
13723
13724         rtnl_lock();
13725         BNX2X_ERR("IO slot reset initializing...\n");
13726         if (pci_enable_device(pdev)) {
13727                 dev_err(&pdev->dev,
13728                         "Cannot re-enable PCI device after reset\n");
13729                 rtnl_unlock();
13730                 return PCI_ERS_RESULT_DISCONNECT;
13731         }
13732
13733         pci_set_master(pdev);
13734         pci_restore_state(pdev);
13735         pci_save_state(pdev);
13736
13737         if (netif_running(dev))
13738                 bnx2x_set_power_state(bp, PCI_D0);
13739
13740         if (netif_running(dev)) {
13741                 BNX2X_ERR("IO slot reset --> driver unload\n");
13742
13743                 /* MCP should have been reset; Need to wait for validity */
13744                 bnx2x_init_shmem(bp);
13745
13746                 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
13747                         u32 v;
13748
13749                         v = SHMEM2_RD(bp,
13750                                       drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
13751                         SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
13752                                   v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
13753                 }
13754                 bnx2x_drain_tx_queues(bp);
13755                 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
13756                 bnx2x_netif_stop(bp, 1);
13757                 bnx2x_free_irq(bp);
13758
13759                 /* Report UNLOAD_DONE to MCP */
13760                 bnx2x_send_unload_done(bp, true);
13761
13762                 bp->sp_state = 0;
13763                 bp->port.pmf = 0;
13764
13765                 bnx2x_prev_unload(bp);
13766
13767                 /* We should have reseted the engine, so It's fair to
13768                  * assume the FW will no longer write to the bnx2x driver.
13769                  */
13770                 bnx2x_squeeze_objects(bp);
13771                 bnx2x_free_skbs(bp);
13772                 for_each_rx_queue(bp, i)
13773                         bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
13774                 bnx2x_free_fp_mem(bp);
13775                 bnx2x_free_mem(bp);
13776
13777                 bp->state = BNX2X_STATE_CLOSED;
13778         }
13779
13780         rtnl_unlock();
13781
13782         /* If AER, perform cleanup of the PCIe registers */
13783         if (bp->flags & AER_ENABLED) {
13784                 if (pci_cleanup_aer_uncorrect_error_status(pdev))
13785                         BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
13786                 else
13787                         DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
13788         }
13789
13790         return PCI_ERS_RESULT_RECOVERED;
13791 }
13792
13793 /**
13794  * bnx2x_io_resume - called when traffic can start flowing again
13795  * @pdev: Pointer to PCI device
13796  *
13797  * This callback is called when the error recovery driver tells us that
13798  * its OK to resume normal operation.
13799  */
13800 static void bnx2x_io_resume(struct pci_dev *pdev)
13801 {
13802         struct net_device *dev = pci_get_drvdata(pdev);
13803         struct bnx2x *bp = netdev_priv(dev);
13804
13805         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
13806                 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
13807                 return;
13808         }
13809
13810         rtnl_lock();
13811
13812         bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
13813                                                         DRV_MSG_SEQ_NUMBER_MASK;
13814
13815         if (netif_running(dev))
13816                 bnx2x_nic_load(bp, LOAD_NORMAL);
13817
13818         netif_device_attach(dev);
13819
13820         rtnl_unlock();
13821 }
13822
13823 static const struct pci_error_handlers bnx2x_err_handler = {
13824         .error_detected = bnx2x_io_error_detected,
13825         .slot_reset     = bnx2x_io_slot_reset,
13826         .resume         = bnx2x_io_resume,
13827 };
13828
13829 static void bnx2x_shutdown(struct pci_dev *pdev)
13830 {
13831         struct net_device *dev = pci_get_drvdata(pdev);
13832         struct bnx2x *bp;
13833
13834         if (!dev)
13835                 return;
13836
13837         bp = netdev_priv(dev);
13838         if (!bp)
13839                 return;
13840
13841         rtnl_lock();
13842         netif_device_detach(dev);
13843         rtnl_unlock();
13844
13845         /* Don't remove the netdevice, as there are scenarios which will cause
13846          * the kernel to hang, e.g., when trying to remove bnx2i while the
13847          * rootfs is mounted from SAN.
13848          */
13849         __bnx2x_remove(pdev, dev, bp, false);
13850 }
13851
13852 static struct pci_driver bnx2x_pci_driver = {
13853         .name        = DRV_MODULE_NAME,
13854         .id_table    = bnx2x_pci_tbl,
13855         .probe       = bnx2x_init_one,
13856         .remove      = bnx2x_remove_one,
13857         .suspend     = bnx2x_suspend,
13858         .resume      = bnx2x_resume,
13859         .err_handler = &bnx2x_err_handler,
13860 #ifdef CONFIG_BNX2X_SRIOV
13861         .sriov_configure = bnx2x_sriov_configure,
13862 #endif
13863         .shutdown    = bnx2x_shutdown,
13864 };
13865
13866 static int __init bnx2x_init(void)
13867 {
13868         int ret;
13869
13870         pr_info("%s", version);
13871
13872         bnx2x_wq = create_singlethread_workqueue("bnx2x");
13873         if (bnx2x_wq == NULL) {
13874                 pr_err("Cannot create workqueue\n");
13875                 return -ENOMEM;
13876         }
13877         bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov");
13878         if (!bnx2x_iov_wq) {
13879                 pr_err("Cannot create iov workqueue\n");
13880                 destroy_workqueue(bnx2x_wq);
13881                 return -ENOMEM;
13882         }
13883
13884         ret = pci_register_driver(&bnx2x_pci_driver);
13885         if (ret) {
13886                 pr_err("Cannot register driver\n");
13887                 destroy_workqueue(bnx2x_wq);
13888                 destroy_workqueue(bnx2x_iov_wq);
13889         }
13890         return ret;
13891 }
13892
13893 static void __exit bnx2x_cleanup(void)
13894 {
13895         struct list_head *pos, *q;
13896
13897         pci_unregister_driver(&bnx2x_pci_driver);
13898
13899         destroy_workqueue(bnx2x_wq);
13900         destroy_workqueue(bnx2x_iov_wq);
13901
13902         /* Free globally allocated resources */
13903         list_for_each_safe(pos, q, &bnx2x_prev_list) {
13904                 struct bnx2x_prev_path_list *tmp =
13905                         list_entry(pos, struct bnx2x_prev_path_list, list);
13906                 list_del(pos);
13907                 kfree(tmp);
13908         }
13909 }
13910
13911 void bnx2x_notify_link_changed(struct bnx2x *bp)
13912 {
13913         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
13914 }
13915
13916 module_init(bnx2x_init);
13917 module_exit(bnx2x_cleanup);
13918
13919 /**
13920  * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
13921  *
13922  * @bp:         driver handle
13923  * @set:        set or clear the CAM entry
13924  *
13925  * This function will wait until the ramrod completion returns.
13926  * Return 0 if success, -ENODEV if ramrod doesn't return.
13927  */
13928 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
13929 {
13930         unsigned long ramrod_flags = 0;
13931
13932         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
13933         return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
13934                                  &bp->iscsi_l2_mac_obj, true,
13935                                  BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
13936 }
13937
13938 /* count denotes the number of new completions we have seen */
13939 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
13940 {
13941         struct eth_spe *spe;
13942         int cxt_index, cxt_offset;
13943
13944 #ifdef BNX2X_STOP_ON_ERROR
13945         if (unlikely(bp->panic))
13946                 return;
13947 #endif
13948
13949         spin_lock_bh(&bp->spq_lock);
13950         BUG_ON(bp->cnic_spq_pending < count);
13951         bp->cnic_spq_pending -= count;
13952
13953         for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
13954                 u16 type =  (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
13955                                 & SPE_HDR_CONN_TYPE) >>
13956                                 SPE_HDR_CONN_TYPE_SHIFT;
13957                 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
13958                                 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
13959
13960                 /* Set validation for iSCSI L2 client before sending SETUP
13961                  *  ramrod
13962                  */
13963                 if (type == ETH_CONNECTION_TYPE) {
13964                         if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
13965                                 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
13966                                         ILT_PAGE_CIDS;
13967                                 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
13968                                         (cxt_index * ILT_PAGE_CIDS);
13969                                 bnx2x_set_ctx_validation(bp,
13970                                         &bp->context[cxt_index].
13971                                                          vcxt[cxt_offset].eth,
13972                                         BNX2X_ISCSI_ETH_CID(bp));
13973                         }
13974                 }
13975
13976                 /*
13977                  * There may be not more than 8 L2, not more than 8 L5 SPEs
13978                  * and in the air. We also check that number of outstanding
13979                  * COMMON ramrods is not more than the EQ and SPQ can
13980                  * accommodate.
13981                  */
13982                 if (type == ETH_CONNECTION_TYPE) {
13983                         if (!atomic_read(&bp->cq_spq_left))
13984                                 break;
13985                         else
13986                                 atomic_dec(&bp->cq_spq_left);
13987                 } else if (type == NONE_CONNECTION_TYPE) {
13988                         if (!atomic_read(&bp->eq_spq_left))
13989                                 break;
13990                         else
13991                                 atomic_dec(&bp->eq_spq_left);
13992                 } else if ((type == ISCSI_CONNECTION_TYPE) ||
13993                            (type == FCOE_CONNECTION_TYPE)) {
13994                         if (bp->cnic_spq_pending >=
13995                             bp->cnic_eth_dev.max_kwqe_pending)
13996                                 break;
13997                         else
13998                                 bp->cnic_spq_pending++;
13999                 } else {
14000                         BNX2X_ERR("Unknown SPE type: %d\n", type);
14001                         bnx2x_panic();
14002                         break;
14003                 }
14004
14005                 spe = bnx2x_sp_get_next(bp);
14006                 *spe = *bp->cnic_kwq_cons;
14007
14008                 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
14009                    bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
14010
14011                 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
14012                         bp->cnic_kwq_cons = bp->cnic_kwq;
14013                 else
14014                         bp->cnic_kwq_cons++;
14015         }
14016         bnx2x_sp_prod_update(bp);
14017         spin_unlock_bh(&bp->spq_lock);
14018 }
14019
14020 static int bnx2x_cnic_sp_queue(struct net_device *dev,
14021                                struct kwqe_16 *kwqes[], u32 count)
14022 {
14023         struct bnx2x *bp = netdev_priv(dev);
14024         int i;
14025
14026 #ifdef BNX2X_STOP_ON_ERROR
14027         if (unlikely(bp->panic)) {
14028                 BNX2X_ERR("Can't post to SP queue while panic\n");
14029                 return -EIO;
14030         }
14031 #endif
14032
14033         if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
14034             (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
14035                 BNX2X_ERR("Handling parity error recovery. Try again later\n");
14036                 return -EAGAIN;
14037         }
14038
14039         spin_lock_bh(&bp->spq_lock);
14040
14041         for (i = 0; i < count; i++) {
14042                 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
14043
14044                 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
14045                         break;
14046
14047                 *bp->cnic_kwq_prod = *spe;
14048
14049                 bp->cnic_kwq_pending++;
14050
14051                 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
14052                    spe->hdr.conn_and_cmd_data, spe->hdr.type,
14053                    spe->data.update_data_addr.hi,
14054                    spe->data.update_data_addr.lo,
14055                    bp->cnic_kwq_pending);
14056
14057                 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
14058                         bp->cnic_kwq_prod = bp->cnic_kwq;
14059                 else
14060                         bp->cnic_kwq_prod++;
14061         }
14062
14063         spin_unlock_bh(&bp->spq_lock);
14064
14065         if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
14066                 bnx2x_cnic_sp_post(bp, 0);
14067
14068         return i;
14069 }
14070
14071 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14072 {
14073         struct cnic_ops *c_ops;
14074         int rc = 0;
14075
14076         mutex_lock(&bp->cnic_mutex);
14077         c_ops = rcu_dereference_protected(bp->cnic_ops,
14078                                           lockdep_is_held(&bp->cnic_mutex));
14079         if (c_ops)
14080                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14081         mutex_unlock(&bp->cnic_mutex);
14082
14083         return rc;
14084 }
14085
14086 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14087 {
14088         struct cnic_ops *c_ops;
14089         int rc = 0;
14090
14091         rcu_read_lock();
14092         c_ops = rcu_dereference(bp->cnic_ops);
14093         if (c_ops)
14094                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14095         rcu_read_unlock();
14096
14097         return rc;
14098 }
14099
14100 /*
14101  * for commands that have no data
14102  */
14103 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
14104 {
14105         struct cnic_ctl_info ctl = {0};
14106
14107         ctl.cmd = cmd;
14108
14109         return bnx2x_cnic_ctl_send(bp, &ctl);
14110 }
14111
14112 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
14113 {
14114         struct cnic_ctl_info ctl = {0};
14115
14116         /* first we tell CNIC and only then we count this as a completion */
14117         ctl.cmd = CNIC_CTL_COMPLETION_CMD;
14118         ctl.data.comp.cid = cid;
14119         ctl.data.comp.error = err;
14120
14121         bnx2x_cnic_ctl_send_bh(bp, &ctl);
14122         bnx2x_cnic_sp_post(bp, 0);
14123 }
14124
14125 /* Called with netif_addr_lock_bh() taken.
14126  * Sets an rx_mode config for an iSCSI ETH client.
14127  * Doesn't block.
14128  * Completion should be checked outside.
14129  */
14130 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
14131 {
14132         unsigned long accept_flags = 0, ramrod_flags = 0;
14133         u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14134         int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
14135
14136         if (start) {
14137                 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14138                  * because it's the only way for UIO Queue to accept
14139                  * multicasts (in non-promiscuous mode only one Queue per
14140                  * function will receive multicast packets (leading in our
14141                  * case).
14142                  */
14143                 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
14144                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
14145                 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
14146                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
14147
14148                 /* Clear STOP_PENDING bit if START is requested */
14149                 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
14150
14151                 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
14152         } else
14153                 /* Clear START_PENDING bit if STOP is requested */
14154                 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
14155
14156         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
14157                 set_bit(sched_state, &bp->sp_state);
14158         else {
14159                 __set_bit(RAMROD_RX, &ramrod_flags);
14160                 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
14161                                     ramrod_flags);
14162         }
14163 }
14164
14165 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
14166 {
14167         struct bnx2x *bp = netdev_priv(dev);
14168         int rc = 0;
14169
14170         switch (ctl->cmd) {
14171         case DRV_CTL_CTXTBL_WR_CMD: {
14172                 u32 index = ctl->data.io.offset;
14173                 dma_addr_t addr = ctl->data.io.dma_addr;
14174
14175                 bnx2x_ilt_wr(bp, index, addr);
14176                 break;
14177         }
14178
14179         case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
14180                 int count = ctl->data.credit.credit_count;
14181
14182                 bnx2x_cnic_sp_post(bp, count);
14183                 break;
14184         }
14185
14186         /* rtnl_lock is held.  */
14187         case DRV_CTL_START_L2_CMD: {
14188                 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14189                 unsigned long sp_bits = 0;
14190
14191                 /* Configure the iSCSI classification object */
14192                 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
14193                                    cp->iscsi_l2_client_id,
14194                                    cp->iscsi_l2_cid, BP_FUNC(bp),
14195                                    bnx2x_sp(bp, mac_rdata),
14196                                    bnx2x_sp_mapping(bp, mac_rdata),
14197                                    BNX2X_FILTER_MAC_PENDING,
14198                                    &bp->sp_state, BNX2X_OBJ_TYPE_RX,
14199                                    &bp->macs_pool);
14200
14201                 /* Set iSCSI MAC address */
14202                 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
14203                 if (rc)
14204                         break;
14205
14206                 mmiowb();
14207                 barrier();
14208
14209                 /* Start accepting on iSCSI L2 ring */
14210
14211                 netif_addr_lock_bh(dev);
14212                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
14213                 netif_addr_unlock_bh(dev);
14214
14215                 /* bits to wait on */
14216                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14217                 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
14218
14219                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14220                         BNX2X_ERR("rx_mode completion timed out!\n");
14221
14222                 break;
14223         }
14224
14225         /* rtnl_lock is held.  */
14226         case DRV_CTL_STOP_L2_CMD: {
14227                 unsigned long sp_bits = 0;
14228
14229                 /* Stop accepting on iSCSI L2 ring */
14230                 netif_addr_lock_bh(dev);
14231                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
14232                 netif_addr_unlock_bh(dev);
14233
14234                 /* bits to wait on */
14235                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14236                 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
14237
14238                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14239                         BNX2X_ERR("rx_mode completion timed out!\n");
14240
14241                 mmiowb();
14242                 barrier();
14243
14244                 /* Unset iSCSI L2 MAC */
14245                 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
14246                                         BNX2X_ISCSI_ETH_MAC, true);
14247                 break;
14248         }
14249         case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
14250                 int count = ctl->data.credit.credit_count;
14251
14252                 smp_mb__before_atomic();
14253                 atomic_add(count, &bp->cq_spq_left);
14254                 smp_mb__after_atomic();
14255                 break;
14256         }
14257         case DRV_CTL_ULP_REGISTER_CMD: {
14258                 int ulp_type = ctl->data.register_data.ulp_type;
14259
14260                 if (CHIP_IS_E3(bp)) {
14261                         int idx = BP_FW_MB_IDX(bp);
14262                         u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14263                         int path = BP_PATH(bp);
14264                         int port = BP_PORT(bp);
14265                         int i;
14266                         u32 scratch_offset;
14267                         u32 *host_addr;
14268
14269                         /* first write capability to shmem2 */
14270                         if (ulp_type == CNIC_ULP_ISCSI)
14271                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14272                         else if (ulp_type == CNIC_ULP_FCOE)
14273                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14274                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14275
14276                         if ((ulp_type != CNIC_ULP_FCOE) ||
14277                             (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
14278                             (!(bp->flags &  BC_SUPPORTS_FCOE_FEATURES)))
14279                                 break;
14280
14281                         /* if reached here - should write fcoe capabilities */
14282                         scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
14283                         if (!scratch_offset)
14284                                 break;
14285                         scratch_offset += offsetof(struct glob_ncsi_oem_data,
14286                                                    fcoe_features[path][port]);
14287                         host_addr = (u32 *) &(ctl->data.register_data.
14288                                               fcoe_features);
14289                         for (i = 0; i < sizeof(struct fcoe_capabilities);
14290                              i += 4)
14291                                 REG_WR(bp, scratch_offset + i,
14292                                        *(host_addr + i/4));
14293                 }
14294                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14295                 break;
14296         }
14297
14298         case DRV_CTL_ULP_UNREGISTER_CMD: {
14299                 int ulp_type = ctl->data.ulp_type;
14300
14301                 if (CHIP_IS_E3(bp)) {
14302                         int idx = BP_FW_MB_IDX(bp);
14303                         u32 cap;
14304
14305                         cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14306                         if (ulp_type == CNIC_ULP_ISCSI)
14307                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14308                         else if (ulp_type == CNIC_ULP_FCOE)
14309                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14310                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14311                 }
14312                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14313                 break;
14314         }
14315
14316         default:
14317                 BNX2X_ERR("unknown command %x\n", ctl->cmd);
14318                 rc = -EINVAL;
14319         }
14320
14321         return rc;
14322 }
14323
14324 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
14325 {
14326         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14327
14328         if (bp->flags & USING_MSIX_FLAG) {
14329                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
14330                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
14331                 cp->irq_arr[0].vector = bp->msix_table[1].vector;
14332         } else {
14333                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
14334                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
14335         }
14336         if (!CHIP_IS_E1x(bp))
14337                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
14338         else
14339                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
14340
14341         cp->irq_arr[0].status_blk_num =  bnx2x_cnic_fw_sb_id(bp);
14342         cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
14343         cp->irq_arr[1].status_blk = bp->def_status_blk;
14344         cp->irq_arr[1].status_blk_num = DEF_SB_ID;
14345         cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
14346
14347         cp->num_irq = 2;
14348 }
14349
14350 void bnx2x_setup_cnic_info(struct bnx2x *bp)
14351 {
14352         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14353
14354         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14355                              bnx2x_cid_ilt_lines(bp);
14356         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14357         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14358         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14359
14360         DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
14361            BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
14362            cp->iscsi_l2_cid);
14363
14364         if (NO_ISCSI_OOO(bp))
14365                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14366 }
14367
14368 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
14369                                void *data)
14370 {
14371         struct bnx2x *bp = netdev_priv(dev);
14372         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14373         int rc;
14374
14375         DP(NETIF_MSG_IFUP, "Register_cnic called\n");
14376
14377         if (ops == NULL) {
14378                 BNX2X_ERR("NULL ops received\n");
14379                 return -EINVAL;
14380         }
14381
14382         if (!CNIC_SUPPORT(bp)) {
14383                 BNX2X_ERR("Can't register CNIC when not supported\n");
14384                 return -EOPNOTSUPP;
14385         }
14386
14387         if (!CNIC_LOADED(bp)) {
14388                 rc = bnx2x_load_cnic(bp);
14389                 if (rc) {
14390                         BNX2X_ERR("CNIC-related load failed\n");
14391                         return rc;
14392                 }
14393         }
14394
14395         bp->cnic_enabled = true;
14396
14397         bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
14398         if (!bp->cnic_kwq)
14399                 return -ENOMEM;
14400
14401         bp->cnic_kwq_cons = bp->cnic_kwq;
14402         bp->cnic_kwq_prod = bp->cnic_kwq;
14403         bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
14404
14405         bp->cnic_spq_pending = 0;
14406         bp->cnic_kwq_pending = 0;
14407
14408         bp->cnic_data = data;
14409
14410         cp->num_irq = 0;
14411         cp->drv_state |= CNIC_DRV_STATE_REGD;
14412         cp->iro_arr = bp->iro_arr;
14413
14414         bnx2x_setup_cnic_irq_info(bp);
14415
14416         rcu_assign_pointer(bp->cnic_ops, ops);
14417
14418         /* Schedule driver to read CNIC driver versions */
14419         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14420
14421         return 0;
14422 }
14423
14424 static int bnx2x_unregister_cnic(struct net_device *dev)
14425 {
14426         struct bnx2x *bp = netdev_priv(dev);
14427         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14428
14429         mutex_lock(&bp->cnic_mutex);
14430         cp->drv_state = 0;
14431         RCU_INIT_POINTER(bp->cnic_ops, NULL);
14432         mutex_unlock(&bp->cnic_mutex);
14433         synchronize_rcu();
14434         bp->cnic_enabled = false;
14435         kfree(bp->cnic_kwq);
14436         bp->cnic_kwq = NULL;
14437
14438         return 0;
14439 }
14440
14441 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
14442 {
14443         struct bnx2x *bp = netdev_priv(dev);
14444         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14445
14446         /* If both iSCSI and FCoE are disabled - return NULL in
14447          * order to indicate CNIC that it should not try to work
14448          * with this device.
14449          */
14450         if (NO_ISCSI(bp) && NO_FCOE(bp))
14451                 return NULL;
14452
14453         cp->drv_owner = THIS_MODULE;
14454         cp->chip_id = CHIP_ID(bp);
14455         cp->pdev = bp->pdev;
14456         cp->io_base = bp->regview;
14457         cp->io_base2 = bp->doorbells;
14458         cp->max_kwqe_pending = 8;
14459         cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
14460         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14461                              bnx2x_cid_ilt_lines(bp);
14462         cp->ctx_tbl_len = CNIC_ILT_LINES;
14463         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14464         cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
14465         cp->drv_ctl = bnx2x_drv_ctl;
14466         cp->drv_register_cnic = bnx2x_register_cnic;
14467         cp->drv_unregister_cnic = bnx2x_unregister_cnic;
14468         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14469         cp->iscsi_l2_client_id =
14470                 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14471         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14472
14473         if (NO_ISCSI_OOO(bp))
14474                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14475
14476         if (NO_ISCSI(bp))
14477                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
14478
14479         if (NO_FCOE(bp))
14480                 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
14481
14482         BNX2X_DEV_INFO(
14483                 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
14484            cp->ctx_blk_size,
14485            cp->ctx_tbl_offset,
14486            cp->ctx_tbl_len,
14487            cp->starting_cid);
14488         return cp;
14489 }
14490
14491 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
14492 {
14493         struct bnx2x *bp = fp->bp;
14494         u32 offset = BAR_USTRORM_INTMEM;
14495
14496         if (IS_VF(bp))
14497                 return bnx2x_vf_ustorm_prods_offset(bp, fp);
14498         else if (!CHIP_IS_E1x(bp))
14499                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
14500         else
14501                 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
14502
14503         return offset;
14504 }
14505
14506 /* called only on E1H or E2.
14507  * When pretending to be PF, the pretend value is the function number 0...7
14508  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
14509  * combination
14510  */
14511 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
14512 {
14513         u32 pretend_reg;
14514
14515         if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
14516                 return -1;
14517
14518         /* get my own pretend register */
14519         pretend_reg = bnx2x_get_pretend_reg(bp);
14520         REG_WR(bp, pretend_reg, pretend_func_val);
14521         REG_RD(bp, pretend_reg);
14522         return 0;
14523 }
14524
14525 static void bnx2x_ptp_task(struct work_struct *work)
14526 {
14527         struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
14528         int port = BP_PORT(bp);
14529         u32 val_seq;
14530         u64 timestamp, ns;
14531         struct skb_shared_hwtstamps shhwtstamps;
14532
14533         /* Read Tx timestamp registers */
14534         val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14535                          NIG_REG_P0_TLLH_PTP_BUF_SEQID);
14536         if (val_seq & 0x10000) {
14537                 /* There is a valid timestamp value */
14538                 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
14539                                    NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
14540                 timestamp <<= 32;
14541                 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
14542                                     NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
14543                 /* Reset timestamp register to allow new timestamp */
14544                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14545                        NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
14546                 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
14547
14548                 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
14549                 shhwtstamps.hwtstamp = ns_to_ktime(ns);
14550                 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
14551                 dev_kfree_skb_any(bp->ptp_tx_skb);
14552                 bp->ptp_tx_skb = NULL;
14553
14554                 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
14555                    timestamp, ns);
14556         } else {
14557                 DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n");
14558                 /* Reschedule to keep checking for a valid timestamp value */
14559                 schedule_work(&bp->ptp_task);
14560         }
14561 }
14562
14563 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
14564 {
14565         int port = BP_PORT(bp);
14566         u64 timestamp, ns;
14567
14568         timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
14569                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
14570         timestamp <<= 32;
14571         timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
14572                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
14573
14574         /* Reset timestamp register to allow new timestamp */
14575         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
14576                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
14577
14578         ns = timecounter_cyc2time(&bp->timecounter, timestamp);
14579
14580         skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
14581
14582         DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
14583            timestamp, ns);
14584 }
14585
14586 /* Read the PHC */
14587 static cycle_t bnx2x_cyclecounter_read(const struct cyclecounter *cc)
14588 {
14589         struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
14590         int port = BP_PORT(bp);
14591         u32 wb_data[2];
14592         u64 phc_cycles;
14593
14594         REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
14595                     NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
14596         phc_cycles = wb_data[1];
14597         phc_cycles = (phc_cycles << 32) + wb_data[0];
14598
14599         DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
14600
14601         return phc_cycles;
14602 }
14603
14604 static void bnx2x_init_cyclecounter(struct bnx2x *bp)
14605 {
14606         memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
14607         bp->cyclecounter.read = bnx2x_cyclecounter_read;
14608         bp->cyclecounter.mask = CLOCKSOURCE_MASK(64);
14609         bp->cyclecounter.shift = 1;
14610         bp->cyclecounter.mult = 1;
14611 }
14612
14613 static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
14614 {
14615         struct bnx2x_func_state_params func_params = {NULL};
14616         struct bnx2x_func_set_timesync_params *set_timesync_params =
14617                 &func_params.params.set_timesync;
14618
14619         /* Prepare parameters for function state transitions */
14620         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
14621         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
14622
14623         func_params.f_obj = &bp->func_obj;
14624         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
14625
14626         /* Function parameters */
14627         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
14628         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
14629
14630         return bnx2x_func_state_change(bp, &func_params);
14631 }
14632
14633 int bnx2x_enable_ptp_packets(struct bnx2x *bp)
14634 {
14635         struct bnx2x_queue_state_params q_params;
14636         int rc, i;
14637
14638         /* send queue update ramrod to enable PTP packets */
14639         memset(&q_params, 0, sizeof(q_params));
14640         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
14641         q_params.cmd = BNX2X_Q_CMD_UPDATE;
14642         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
14643                   &q_params.params.update.update_flags);
14644         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
14645                   &q_params.params.update.update_flags);
14646
14647         /* send the ramrod on all the queues of the PF */
14648         for_each_eth_queue(bp, i) {
14649                 struct bnx2x_fastpath *fp = &bp->fp[i];
14650
14651                 /* Set the appropriate Queue object */
14652                 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
14653
14654                 /* Update the Queue state */
14655                 rc = bnx2x_queue_state_change(bp, &q_params);
14656                 if (rc) {
14657                         BNX2X_ERR("Failed to enable PTP packets\n");
14658                         return rc;
14659                 }
14660         }
14661
14662         return 0;
14663 }
14664
14665 int bnx2x_configure_ptp_filters(struct bnx2x *bp)
14666 {
14667         int port = BP_PORT(bp);
14668         int rc;
14669
14670         if (!bp->hwtstamp_ioctl_called)
14671                 return 0;
14672
14673         switch (bp->tx_type) {
14674         case HWTSTAMP_TX_ON:
14675                 bp->flags |= TX_TIMESTAMPING_EN;
14676                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
14677                        NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
14678                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
14679                        NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
14680                 break;
14681         case HWTSTAMP_TX_ONESTEP_SYNC:
14682                 BNX2X_ERR("One-step timestamping is not supported\n");
14683                 return -ERANGE;
14684         }
14685
14686         switch (bp->rx_filter) {
14687         case HWTSTAMP_FILTER_NONE:
14688                 break;
14689         case HWTSTAMP_FILTER_ALL:
14690         case HWTSTAMP_FILTER_SOME:
14691                 bp->rx_filter = HWTSTAMP_FILTER_NONE;
14692                 break;
14693         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
14694         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
14695         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
14696                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
14697                 /* Initialize PTP detection for UDP/IPv4 events */
14698                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14699                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
14700                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14701                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
14702                 break;
14703         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
14704         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
14705         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
14706                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
14707                 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
14708                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14709                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
14710                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14711                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
14712                 break;
14713         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
14714         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
14715         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
14716                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
14717                 /* Initialize PTP detection L2 events */
14718                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14719                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
14720                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14721                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
14722
14723                 break;
14724         case HWTSTAMP_FILTER_PTP_V2_EVENT:
14725         case HWTSTAMP_FILTER_PTP_V2_SYNC:
14726         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
14727                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
14728                 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
14729                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14730                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
14731                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14732                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
14733                 break;
14734         }
14735
14736         /* Indicate to FW that this PF expects recorded PTP packets */
14737         rc = bnx2x_enable_ptp_packets(bp);
14738         if (rc)
14739                 return rc;
14740
14741         /* Enable sending PTP packets to host */
14742         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
14743                NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
14744
14745         return 0;
14746 }
14747
14748 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
14749 {
14750         struct hwtstamp_config config;
14751         int rc;
14752
14753         DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
14754
14755         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
14756                 return -EFAULT;
14757
14758         DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
14759            config.tx_type, config.rx_filter);
14760
14761         if (config.flags) {
14762                 BNX2X_ERR("config.flags is reserved for future use\n");
14763                 return -EINVAL;
14764         }
14765
14766         bp->hwtstamp_ioctl_called = 1;
14767         bp->tx_type = config.tx_type;
14768         bp->rx_filter = config.rx_filter;
14769
14770         rc = bnx2x_configure_ptp_filters(bp);
14771         if (rc)
14772                 return rc;
14773
14774         config.rx_filter = bp->rx_filter;
14775
14776         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
14777                 -EFAULT : 0;
14778 }
14779
14780 /* Configrues HW for PTP */
14781 static int bnx2x_configure_ptp(struct bnx2x *bp)
14782 {
14783         int rc, port = BP_PORT(bp);
14784         u32 wb_data[2];
14785
14786         /* Reset PTP event detection rules - will be configured in the IOCTL */
14787         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14788                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
14789         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14790                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
14791         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
14792                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
14793         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
14794                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
14795
14796         /* Disable PTP packets to host - will be configured in the IOCTL*/
14797         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
14798                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
14799
14800         /* Enable the PTP feature */
14801         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
14802                NIG_REG_P0_PTP_EN, 0x3F);
14803
14804         /* Enable the free-running counter */
14805         wb_data[0] = 0;
14806         wb_data[1] = 0;
14807         REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
14808
14809         /* Reset drift register (offset register is not reset) */
14810         rc = bnx2x_send_reset_timesync_ramrod(bp);
14811         if (rc) {
14812                 BNX2X_ERR("Failed to reset PHC drift register\n");
14813                 return -EFAULT;
14814         }
14815
14816         /* Reset possibly old timestamps */
14817         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
14818                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
14819         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14820                NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
14821
14822         return 0;
14823 }
14824
14825 /* Called during load, to initialize PTP-related stuff */
14826 void bnx2x_init_ptp(struct bnx2x *bp)
14827 {
14828         int rc;
14829
14830         /* Configure PTP in HW */
14831         rc = bnx2x_configure_ptp(bp);
14832         if (rc) {
14833                 BNX2X_ERR("Stopping PTP initialization\n");
14834                 return;
14835         }
14836
14837         /* Init work queue for Tx timestamping */
14838         INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
14839
14840         /* Init cyclecounter and timecounter. This is done only in the first
14841          * load. If done in every load, PTP application will fail when doing
14842          * unload / load (e.g. MTU change) while it is running.
14843          */
14844         if (!bp->timecounter_init_done) {
14845                 bnx2x_init_cyclecounter(bp);
14846                 timecounter_init(&bp->timecounter, &bp->cyclecounter,
14847                                  ktime_to_ns(ktime_get_real()));
14848                 bp->timecounter_init_done = 1;
14849         }
14850
14851         DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");
14852 }