drivers/net/ethernet/broadcom/bnxt/bnxt.h

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2015 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  */
   9
  10 #ifndef BNXT_H
  11 #define BNXT_H
  12
  13 #define DRV_MODULE_NAME         "bnxt_en"
  14 #define DRV_MODULE_VERSION      "1.0.0"
  15
  16 #define DRV_VER_MAJ     1
  17 #define DRV_VER_MIN     0
  18 #define DRV_VER_UPD     0
  19
  20 struct tx_bd {
  21         __le32 tx_bd_len_flags_type;
  22         #define TX_BD_TYPE                                      (0x3f << 0)
  23          #define TX_BD_TYPE_SHORT_TX_BD                          (0x00 << 0)
  24          #define TX_BD_TYPE_LONG_TX_BD                           (0x10 << 0)
  25         #define TX_BD_FLAGS_PACKET_END                          (1 << 6)
  26         #define TX_BD_FLAGS_NO_CMPL                             (1 << 7)
  27         #define TX_BD_FLAGS_BD_CNT                              (0x1f << 8)
  28          #define TX_BD_FLAGS_BD_CNT_SHIFT                        8
  29         #define TX_BD_FLAGS_LHINT                               (3 << 13)
  30          #define TX_BD_FLAGS_LHINT_SHIFT                         13
  31          #define TX_BD_FLAGS_LHINT_512_AND_SMALLER               (0 << 13)
  32          #define TX_BD_FLAGS_LHINT_512_TO_1023                   (1 << 13)
  33          #define TX_BD_FLAGS_LHINT_1024_TO_2047                  (2 << 13)
  34          #define TX_BD_FLAGS_LHINT_2048_AND_LARGER               (3 << 13)
  35         #define TX_BD_FLAGS_COAL_NOW                            (1 << 15)
  36         #define TX_BD_LEN                                       (0xffff << 16)
  37          #define TX_BD_LEN_SHIFT                                 16
  38
  39         u32 tx_bd_opaque;
  40         __le64 tx_bd_haddr;
  41 } __packed;
  42
  43 struct tx_bd_ext {
  44         __le32 tx_bd_hsize_lflags;
  45         #define TX_BD_FLAGS_TCP_UDP_CHKSUM                      (1 << 0)
  46         #define TX_BD_FLAGS_IP_CKSUM                            (1 << 1)
  47         #define TX_BD_FLAGS_NO_CRC                              (1 << 2)
  48         #define TX_BD_FLAGS_STAMP                               (1 << 3)
  49         #define TX_BD_FLAGS_T_IP_CHKSUM                         (1 << 4)
  50         #define TX_BD_FLAGS_LSO                                 (1 << 5)
  51         #define TX_BD_FLAGS_IPID_FMT                            (1 << 6)
  52         #define TX_BD_FLAGS_T_IPID                              (1 << 7)
  53         #define TX_BD_HSIZE                                     (0xff << 16)
  54          #define TX_BD_HSIZE_SHIFT                               16
  55
  56         __le32 tx_bd_mss;
  57         __le32 tx_bd_cfa_action;
  58         #define TX_BD_CFA_ACTION                                (0xffff << 16)
  59          #define TX_BD_CFA_ACTION_SHIFT                          16
  60
  61         __le32 tx_bd_cfa_meta;
  62         #define TX_BD_CFA_META_MASK                             0xfffffff
  63         #define TX_BD_CFA_META_VID_MASK                         0xfff
  64         #define TX_BD_CFA_META_PRI_MASK                         (0xf << 12)
  65          #define TX_BD_CFA_META_PRI_SHIFT                        12
  66         #define TX_BD_CFA_META_TPID_MASK                        (3 << 16)
  67          #define TX_BD_CFA_META_TPID_SHIFT                       16
  68         #define TX_BD_CFA_META_KEY                              (0xf << 28)
  69          #define TX_BD_CFA_META_KEY_SHIFT                        28
  70         #define TX_BD_CFA_META_KEY_VLAN                         (1 << 28)
  71 };
  72
  73 struct rx_bd {
  74         __le32 rx_bd_len_flags_type;
  75         #define RX_BD_TYPE                                      (0x3f << 0)
  76          #define RX_BD_TYPE_RX_PACKET_BD                         0x4
  77          #define RX_BD_TYPE_RX_BUFFER_BD                         0x5
  78          #define RX_BD_TYPE_RX_AGG_BD                            0x6
  79          #define RX_BD_TYPE_16B_BD_SIZE                          (0 << 4)
  80          #define RX_BD_TYPE_32B_BD_SIZE                          (1 << 4)
  81          #define RX_BD_TYPE_48B_BD_SIZE                          (2 << 4)
  82          #define RX_BD_TYPE_64B_BD_SIZE                          (3 << 4)
  83         #define RX_BD_FLAGS_SOP                                 (1 << 6)
  84         #define RX_BD_FLAGS_EOP                                 (1 << 7)
  85         #define RX_BD_FLAGS_BUFFERS                             (3 << 8)
  86          #define RX_BD_FLAGS_1_BUFFER_PACKET                     (0 << 8)
  87          #define RX_BD_FLAGS_2_BUFFER_PACKET                     (1 << 8)
  88          #define RX_BD_FLAGS_3_BUFFER_PACKET                     (2 << 8)
  89          #define RX_BD_FLAGS_4_BUFFER_PACKET                     (3 << 8)
  90         #define RX_BD_LEN                                       (0xffff << 16)
  91          #define RX_BD_LEN_SHIFT                                 16
  92
  93         u32 rx_bd_opaque;
  94         __le64 rx_bd_haddr;
  95 };
  96
  97 struct tx_cmp {
  98         __le32 tx_cmp_flags_type;
  99         #define CMP_TYPE                                        (0x3f << 0)
 100          #define CMP_TYPE_TX_L2_CMP                              0
 101          #define CMP_TYPE_RX_L2_CMP                              17
 102          #define CMP_TYPE_RX_AGG_CMP                             18
 103          #define CMP_TYPE_RX_L2_TPA_START_CMP                    19
 104          #define CMP_TYPE_RX_L2_TPA_END_CMP                      21
 105          #define CMP_TYPE_STATUS_CMP                             32
 106          #define CMP_TYPE_REMOTE_DRIVER_REQ                      34
 107          #define CMP_TYPE_REMOTE_DRIVER_RESP                     36
 108          #define CMP_TYPE_ERROR_STATUS                           48
 109          #define CMPL_BASE_TYPE_STAT_EJECT                       (0x1aUL << 0)
 110          #define CMPL_BASE_TYPE_HWRM_DONE                        (0x20UL << 0)
 111          #define CMPL_BASE_TYPE_HWRM_FWD_REQ                     (0x22UL << 0)
 112          #define CMPL_BASE_TYPE_HWRM_FWD_RESP                    (0x24UL << 0)
 113          #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT                 (0x2eUL << 0)
 114
 115         #define TX_CMP_FLAGS_ERROR                              (1 << 6)
 116         #define TX_CMP_FLAGS_PUSH                               (1 << 7)
 117
 118         u32 tx_cmp_opaque;
 119         __le32 tx_cmp_errors_v;
 120         #define TX_CMP_V                                        (1 << 0)
 121         #define TX_CMP_ERRORS_BUFFER_ERROR                      (7 << 1)
 122          #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR             0
 123          #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT           2
 124          #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG         4
 125          #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS          5
 126          #define TX_CMP_ERRORS_ZERO_LENGTH_PKT                   (1 << 4)
 127          #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN                  (1 << 5)
 128          #define TX_CMP_ERRORS_DMA_ERROR                         (1 << 6)
 129          #define TX_CMP_ERRORS_HINT_TOO_SHORT                    (1 << 7)
 130
 131         __le32 tx_cmp_unsed_3;
 132 };
 133
 134 struct rx_cmp {
 135         __le32 rx_cmp_len_flags_type;
 136         #define RX_CMP_CMP_TYPE                                 (0x3f << 0)
 137         #define RX_CMP_FLAGS_ERROR                              (1 << 6)
 138         #define RX_CMP_FLAGS_PLACEMENT                          (7 << 7)
 139         #define RX_CMP_FLAGS_RSS_VALID                          (1 << 10)
 140         #define RX_CMP_FLAGS_UNUSED                             (1 << 11)
 141          #define RX_CMP_FLAGS_ITYPES_SHIFT                       12
 142          #define RX_CMP_FLAGS_ITYPE_UNKNOWN                      (0 << 12)
 143          #define RX_CMP_FLAGS_ITYPE_IP                           (1 << 12)
 144          #define RX_CMP_FLAGS_ITYPE_TCP                          (2 << 12)
 145          #define RX_CMP_FLAGS_ITYPE_UDP                          (3 << 12)
 146          #define RX_CMP_FLAGS_ITYPE_FCOE                         (4 << 12)
 147          #define RX_CMP_FLAGS_ITYPE_ROCE                         (5 << 12)
 148          #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS                    (8 << 12)
 149          #define RX_CMP_FLAGS_ITYPE_PTP_W_TS                     (9 << 12)
 150         #define RX_CMP_LEN                                      (0xffff << 16)
 151          #define RX_CMP_LEN_SHIFT                                16
 152
 153         u32 rx_cmp_opaque;
 154         __le32 rx_cmp_misc_v1;
 155         #define RX_CMP_V1                                       (1 << 0)
 156         #define RX_CMP_AGG_BUFS                                 (0x1f << 1)
 157          #define RX_CMP_AGG_BUFS_SHIFT                           1
 158         #define RX_CMP_RSS_HASH_TYPE                            (0x7f << 9)
 159          #define RX_CMP_RSS_HASH_TYPE_SHIFT                      9
 160         #define RX_CMP_PAYLOAD_OFFSET                           (0xff << 16)
 161          #define RX_CMP_PAYLOAD_OFFSET_SHIFT                     16
 162
 163         __le32 rx_cmp_rss_hash;
 164 };
 165
 166 #define RX_CMP_HASH_VALID(rxcmp)                                \
 167         ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
 168
 169 #define RSS_PROFILE_ID_MASK     0x1f
 170
 171 #define RX_CMP_HASH_TYPE(rxcmp)                                 \
 172         (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
 173           RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
 174
 175 struct rx_cmp_ext {
 176         __le32 rx_cmp_flags2;
 177         #define RX_CMP_FLAGS2_IP_CS_CALC                        0x1
 178         #define RX_CMP_FLAGS2_L4_CS_CALC                        (0x1 << 1)
 179         #define RX_CMP_FLAGS2_T_IP_CS_CALC                      (0x1 << 2)
 180         #define RX_CMP_FLAGS2_T_L4_CS_CALC                      (0x1 << 3)
 181         #define RX_CMP_FLAGS2_META_FORMAT_VLAN                  (0x1 << 4)
 182         __le32 rx_cmp_meta_data;
 183         #define RX_CMP_FLAGS2_METADATA_VID_MASK                 0xfff
 184         #define RX_CMP_FLAGS2_METADATA_TPID_MASK                0xffff0000
 185          #define RX_CMP_FLAGS2_METADATA_TPID_SFT                 16
 186         __le32 rx_cmp_cfa_code_errors_v2;
 187         #define RX_CMP_V                                        (1 << 0)
 188         #define RX_CMPL_ERRORS_MASK                             (0x7fff << 1)
 189          #define RX_CMPL_ERRORS_SFT                              1
 190         #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK                (0x7 << 1)
 191          #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER           (0x0 << 1)
 192          #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT         (0x1 << 1)
 193          #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP         (0x2 << 1)
 194          #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT          (0x3 << 1)
 195         #define RX_CMPL_ERRORS_IP_CS_ERROR                      (0x1 << 4)
 196         #define RX_CMPL_ERRORS_L4_CS_ERROR                      (0x1 << 5)
 197         #define RX_CMPL_ERRORS_T_IP_CS_ERROR                    (0x1 << 6)
 198         #define RX_CMPL_ERRORS_T_L4_CS_ERROR                    (0x1 << 7)
 199         #define RX_CMPL_ERRORS_CRC_ERROR                        (0x1 << 8)
 200         #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK                 (0x7 << 9)
 201          #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR             (0x0 << 9)
 202          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION     (0x1 << 9)
 203          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN     (0x2 << 9)
 204          #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR   (0x3 << 9)
 205          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR     (0x4 << 9)
 206          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR    (0x5 << 9)
 207          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL         (0x6 << 9)
 208         #define RX_CMPL_ERRORS_PKT_ERROR_MASK                   (0xf << 12)
 209          #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR               (0x0 << 12)
 210          #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION         (0x1 << 12)
 211          #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN         (0x2 << 12)
 212          #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL             (0x3 << 12)
 213          #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR         (0x4 << 12)
 214          #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR        (0x5 << 12)
 215          #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN         (0x6 << 12)
 216          #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
 217          #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN         (0x8 << 12)
 218
 219         #define RX_CMPL_CFA_CODE_MASK                           (0xffff << 16)
 220          #define RX_CMPL_CFA_CODE_SFT                            16
 221
 222         __le32 rx_cmp_unused3;
 223 };
 224
 225 #define RX_CMP_L2_ERRORS                                                \
 226         cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
 227
 228 #define RX_CMP_L4_CS_BITS                                               \
 229         (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
 230
 231 #define RX_CMP_L4_CS_ERR_BITS                                           \
 232         (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
 233
 234 #define RX_CMP_L4_CS_OK(rxcmp1)                                         \
 235             (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) &&           \
 236              !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
 237
 238 #define RX_CMP_ENCAP(rxcmp1)                                            \
 239             ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) &                    \
 240              RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
 241
 242 struct rx_agg_cmp {
 243         __le32 rx_agg_cmp_len_flags_type;
 244         #define RX_AGG_CMP_TYPE                                 (0x3f << 0)
 245         #define RX_AGG_CMP_LEN                                  (0xffff << 16)
 246          #define RX_AGG_CMP_LEN_SHIFT                            16
 247         u32 rx_agg_cmp_opaque;
 248         __le32 rx_agg_cmp_v;
 249         #define RX_AGG_CMP_V                                    (1 << 0)
 250         __le32 rx_agg_cmp_unused;
 251 };
 252
 253 struct rx_tpa_start_cmp {
 254         __le32 rx_tpa_start_cmp_len_flags_type;
 255         #define RX_TPA_START_CMP_TYPE                           (0x3f << 0)
 256         #define RX_TPA_START_CMP_FLAGS                          (0x3ff << 6)
 257          #define RX_TPA_START_CMP_FLAGS_SHIFT                    6
 258         #define RX_TPA_START_CMP_FLAGS_PLACEMENT                (0x7 << 7)
 259          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT          7
 260          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO          (0x1 << 7)
 261          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS            (0x2 << 7)
 262          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO      (0x5 << 7)
 263          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS        (0x6 << 7)
 264         #define RX_TPA_START_CMP_FLAGS_RSS_VALID                (0x1 << 10)
 265         #define RX_TPA_START_CMP_FLAGS_ITYPES                   (0xf << 12)
 266          #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT             12
 267          #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP                (0x2 << 12)
 268         #define RX_TPA_START_CMP_LEN                            (0xffff << 16)
 269          #define RX_TPA_START_CMP_LEN_SHIFT                      16
 270
 271         u32 rx_tpa_start_cmp_opaque;
 272         __le32 rx_tpa_start_cmp_misc_v1;
 273         #define RX_TPA_START_CMP_V1                             (0x1 << 0)
 274         #define RX_TPA_START_CMP_RSS_HASH_TYPE                  (0x7f << 9)
 275          #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT            9
 276         #define RX_TPA_START_CMP_AGG_ID                         (0x7f << 25)
 277          #define RX_TPA_START_CMP_AGG_ID_SHIFT                   25
 278
 279         __le32 rx_tpa_start_cmp_rss_hash;
 280 };
 281
 282 #define TPA_START_HASH_VALID(rx_tpa_start)                              \
 283         ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type &              \
 284          cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
 285
 286 #define TPA_START_HASH_TYPE(rx_tpa_start)                               \
 287         (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &      \
 288            RX_TPA_START_CMP_RSS_HASH_TYPE) >>                           \
 289           RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
 290
 291 #define TPA_START_AGG_ID(rx_tpa_start)                                  \
 292         ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &       \
 293          RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
 294
 295 struct rx_tpa_start_cmp_ext {
 296         __le32 rx_tpa_start_cmp_flags2;
 297         #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC              (0x1 << 0)
 298         #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC              (0x1 << 1)
 299         #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC            (0x1 << 2)
 300         #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC            (0x1 << 3)
 301
 302         __le32 rx_tpa_start_cmp_metadata;
 303         __le32 rx_tpa_start_cmp_cfa_code_v2;
 304         #define RX_TPA_START_CMP_V2                             (0x1 << 0)
 305         #define RX_TPA_START_CMP_CFA_CODE                       (0xffff << 16)
 306          #define RX_TPA_START_CMPL_CFA_CODE_SHIFT                16
 307         __le32 rx_tpa_start_cmp_unused5;
 308 };
 309
 310 struct rx_tpa_end_cmp {
 311         __le32 rx_tpa_end_cmp_len_flags_type;
 312         #define RX_TPA_END_CMP_TYPE                             (0x3f << 0)
 313         #define RX_TPA_END_CMP_FLAGS                            (0x3ff << 6)
 314          #define RX_TPA_END_CMP_FLAGS_SHIFT                      6
 315         #define RX_TPA_END_CMP_FLAGS_PLACEMENT                  (0x7 << 7)
 316          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT            7
 317          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO            (0x1 << 7)
 318          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS              (0x2 << 7)
 319          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO        (0x5 << 7)
 320          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS          (0x6 << 7)
 321         #define RX_TPA_END_CMP_FLAGS_RSS_VALID                  (0x1 << 10)
 322         #define RX_TPA_END_CMP_FLAGS_ITYPES                     (0xf << 12)
 323          #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT               12
 324          #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP                  (0x2 << 12)
 325         #define RX_TPA_END_CMP_LEN                              (0xffff << 16)
 326          #define RX_TPA_END_CMP_LEN_SHIFT                        16
 327
 328         u32 rx_tpa_end_cmp_opaque;
 329         __le32 rx_tpa_end_cmp_misc_v1;
 330         #define RX_TPA_END_CMP_V1                               (0x1 << 0)
 331         #define RX_TPA_END_CMP_AGG_BUFS                         (0x3f << 1)
 332          #define RX_TPA_END_CMP_AGG_BUFS_SHIFT                   1
 333         #define RX_TPA_END_CMP_TPA_SEGS                         (0xff << 8)
 334          #define RX_TPA_END_CMP_TPA_SEGS_SHIFT                   8
 335         #define RX_TPA_END_CMP_PAYLOAD_OFFSET                   (0xff << 16)
 336          #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT             16
 337         #define RX_TPA_END_CMP_AGG_ID                           (0x7f << 25)
 338          #define RX_TPA_END_CMP_AGG_ID_SHIFT                     25
 339
 340         __le32 rx_tpa_end_cmp_tsdelta;
 341         #define RX_TPA_END_GRO_TS                               (0x1 << 31)
 342 };
 343
 344 #define TPA_END_AGG_ID(rx_tpa_end)                                      \
 345         ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &           \
 346          RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
 347
 348 #define TPA_END_TPA_SEGS(rx_tpa_end)                                    \
 349         ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &           \
 350          RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
 351
 352 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO                          \
 353         cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO &          \
 354                     RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
 355
 356 #define TPA_END_GRO(rx_tpa_end)                                         \
 357         ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type &                  \
 358          RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
 359
 360 #define TPA_END_GRO_TS(rx_tpa_end)                                      \
 361         ((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & cpu_to_le32(RX_TPA_END_GRO_TS))
 362
 363 struct rx_tpa_end_cmp_ext {
 364         __le32 rx_tpa_end_cmp_dup_acks;
 365         #define RX_TPA_END_CMP_TPA_DUP_ACKS                     (0xf << 0)
 366
 367         __le32 rx_tpa_end_cmp_seg_len;
 368         #define RX_TPA_END_CMP_TPA_SEG_LEN                      (0xffff << 0)
 369
 370         __le32 rx_tpa_end_cmp_errors_v2;
 371         #define RX_TPA_END_CMP_V2                               (0x1 << 0)
 372         #define RX_TPA_END_CMP_ERRORS                           (0x7fff << 1)
 373         #define RX_TPA_END_CMPL_ERRORS_SHIFT                     1
 374
 375         u32 rx_tpa_end_cmp_start_opaque;
 376 };
 377
 378 #define DB_IDX_MASK                                             0xffffff
 379 #define DB_IDX_VALID                                            (0x1 << 26)
 380 #define DB_IRQ_DIS                                              (0x1 << 27)
 381 #define DB_KEY_TX                                               (0x0 << 28)
 382 #define DB_KEY_RX                                               (0x1 << 28)
 383 #define DB_KEY_CP                                               (0x2 << 28)
 384 #define DB_KEY_ST                                               (0x3 << 28)
 385 #define DB_KEY_TX_PUSH                                          (0x4 << 28)
 386 #define DB_LONG_TX_PUSH                                         (0x2 << 24)
 387
 388 #define INVALID_HW_RING_ID      ((u16)-1)
 389
 390 #define BNXT_RSS_HASH_TYPE_FLAG_IPV4            0x01
 391 #define BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4        0x02
 392 #define BNXT_RSS_HASH_TYPE_FLAG_IPV6            0x04
 393 #define BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6        0x08
 394
 395 /* The hardware supports certain page sizes.  Use the supported page sizes
 396  * to allocate the rings.
 397  */
 398 #if (PAGE_SHIFT < 12)
 399 #define BNXT_PAGE_SHIFT 12
 400 #elif (PAGE_SHIFT <= 13)
 401 #define BNXT_PAGE_SHIFT PAGE_SHIFT
 402 #elif (PAGE_SHIFT < 16)
 403 #define BNXT_PAGE_SHIFT 13
 404 #else
 405 #define BNXT_PAGE_SHIFT 16
 406 #endif
 407
 408 #define BNXT_PAGE_SIZE  (1 << BNXT_PAGE_SHIFT)
 409
 410 #define BNXT_MIN_PKT_SIZE       45
 411
 412 #define BNXT_NUM_TESTS(bp)      0
 413
 414 #define BNXT_DEFAULT_RX_RING_SIZE       511
 415 #define BNXT_DEFAULT_TX_RING_SIZE       511
 416
 417 #define MAX_TPA         64
 418
 419 #define MAX_RX_PAGES    8
 420 #define MAX_RX_AGG_PAGES        32
 421 #define MAX_TX_PAGES    8
 422 #define MAX_CP_PAGES    64
 423
 424 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
 425 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
 426 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
 427
 428 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
 429 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
 430
 431 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
 432
 433 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
 434 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
 435
 436 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
 437
 438 #define BNXT_MAX_RX_DESC_CNT            (RX_DESC_CNT * MAX_RX_PAGES - 1)
 439 #define BNXT_MAX_RX_JUM_DESC_CNT        (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
 440 #define BNXT_MAX_TX_DESC_CNT            (TX_DESC_CNT * MAX_TX_PAGES - 1)
 441
 442 #define RX_RING(x)      (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
 443 #define RX_IDX(x)       ((x) & (RX_DESC_CNT - 1))
 444
 445 #define TX_RING(x)      (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
 446 #define TX_IDX(x)       ((x) & (TX_DESC_CNT - 1))
 447
 448 #define CP_RING(x)      (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
 449 #define CP_IDX(x)       ((x) & (CP_DESC_CNT - 1))
 450
 451 #define TX_CMP_VALID(txcmp, raw_cons)                                   \
 452         (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) ==        \
 453          !((raw_cons) & bp->cp_bit))
 454
 455 #define RX_CMP_VALID(rxcmp1, raw_cons)                                  \
 456         (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
 457          !((raw_cons) & bp->cp_bit))
 458
 459 #define RX_AGG_CMP_VALID(agg, raw_cons)                         \
 460         (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
 461          !((raw_cons) & bp->cp_bit))
 462
 463 #define TX_CMP_TYPE(txcmp)                                      \
 464         (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
 465
 466 #define RX_CMP_TYPE(rxcmp)                                      \
 467         (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
 468
 469 #define NEXT_RX(idx)            (((idx) + 1) & bp->rx_ring_mask)
 470
 471 #define NEXT_RX_AGG(idx)        (((idx) + 1) & bp->rx_agg_ring_mask)
 472
 473 #define NEXT_TX(idx)            (((idx) + 1) & bp->tx_ring_mask)
 474
 475 #define ADV_RAW_CMP(idx, n)     ((idx) + (n))
 476 #define NEXT_RAW_CMP(idx)       ADV_RAW_CMP(idx, 1)
 477 #define RING_CMP(idx)           ((idx) & bp->cp_ring_mask)
 478 #define NEXT_CMP(idx)           RING_CMP(ADV_RAW_CMP(idx, 1))
 479
 480 #define HWRM_CMD_TIMEOUT                500
 481 #define HWRM_RESET_TIMEOUT              ((HWRM_CMD_TIMEOUT) * 4)
 482 #define HWRM_RESP_ERR_CODE_MASK         0xffff
 483 #define HWRM_RESP_LEN_MASK              0xffff0000
 484 #define HWRM_RESP_LEN_SFT               16
 485 #define HWRM_RESP_VALID_MASK            0xff000000
 486 #define BNXT_HWRM_REQ_MAX_SIZE          128
 487 #define BNXT_HWRM_REQS_PER_PAGE         (BNXT_PAGE_SIZE /       \
 488                                          BNXT_HWRM_REQ_MAX_SIZE)
 489
 490 struct bnxt_sw_tx_bd {
 491         struct sk_buff          *skb;
 492         DEFINE_DMA_UNMAP_ADDR(mapping);
 493         u8                      is_gso;
 494         u8                      is_push;
 495         unsigned short          nr_frags;
 496 };
 497
 498 struct bnxt_sw_rx_bd {
 499         u8                      *data;
 500         DEFINE_DMA_UNMAP_ADDR(mapping);
 501 };
 502
 503 struct bnxt_sw_rx_agg_bd {
 504         struct page             *page;
 505         dma_addr_t              mapping;
 506 };
 507
 508 struct bnxt_ring_struct {
 509         int                     nr_pages;
 510         int                     page_size;
 511         void                    **pg_arr;
 512         dma_addr_t              *dma_arr;
 513
 514         __le64                  *pg_tbl;
 515         dma_addr_t              pg_tbl_map;
 516
 517         int                     vmem_size;
 518         void                    **vmem;
 519
 520         u16                     fw_ring_id; /* Ring id filled by Chimp FW */
 521         u8                      queue_id;
 522 };
 523
 524 struct tx_push_bd {
 525         __le32                  doorbell;
 526         __le32                  tx_bd_len_flags_type;
 527         u32                     tx_bd_opaque;
 528         struct tx_bd_ext        txbd2;
 529 };
 530
 531 struct tx_push_buffer {
 532         struct tx_push_bd       push_bd;
 533         u32                     data[25];
 534 };
 535
 536 struct bnxt_tx_ring_info {
 537         struct bnxt_napi        *bnapi;
 538         u16                     tx_prod;
 539         u16                     tx_cons;
 540         void __iomem            *tx_doorbell;
 541
 542         struct tx_bd            *tx_desc_ring[MAX_TX_PAGES];
 543         struct bnxt_sw_tx_bd    *tx_buf_ring;
 544
 545         dma_addr_t              tx_desc_mapping[MAX_TX_PAGES];
 546
 547         struct tx_push_buffer   *tx_push;
 548         dma_addr_t              tx_push_mapping;
 549         __le64                  data_mapping;
 550
 551 #define BNXT_DEV_STATE_CLOSING  0x1
 552         u32                     dev_state;
 553
 554         struct bnxt_ring_struct tx_ring_struct;
 555 };
 556
 557 struct bnxt_tpa_info {
 558         u8                      *data;
 559         dma_addr_t              mapping;
 560         u16                     len;
 561         unsigned short          gso_type;
 562         u32                     flags2;
 563         u32                     metadata;
 564         enum pkt_hash_types     hash_type;
 565         u32                     rss_hash;
 566 };
 567
 568 struct bnxt_rx_ring_info {
 569         struct bnxt_napi        *bnapi;
 570         u16                     rx_prod;
 571         u16                     rx_agg_prod;
 572         u16                     rx_sw_agg_prod;
 573         void __iomem            *rx_doorbell;
 574         void __iomem            *rx_agg_doorbell;
 575
 576         struct rx_bd            *rx_desc_ring[MAX_RX_PAGES];
 577         struct bnxt_sw_rx_bd    *rx_buf_ring;
 578
 579         struct rx_bd            *rx_agg_desc_ring[MAX_RX_AGG_PAGES];
 580         struct bnxt_sw_rx_agg_bd        *rx_agg_ring;
 581
 582         unsigned long           *rx_agg_bmap;
 583         u16                     rx_agg_bmap_size;
 584
 585         dma_addr_t              rx_desc_mapping[MAX_RX_PAGES];
 586         dma_addr_t              rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
 587
 588         struct bnxt_tpa_info    *rx_tpa;
 589
 590         struct bnxt_ring_struct rx_ring_struct;
 591         struct bnxt_ring_struct rx_agg_ring_struct;
 592 };
 593
 594 struct bnxt_cp_ring_info {
 595         u32                     cp_raw_cons;
 596         void __iomem            *cp_doorbell;
 597
 598         struct tx_cmp           *cp_desc_ring[MAX_CP_PAGES];
 599
 600         dma_addr_t              cp_desc_mapping[MAX_CP_PAGES];
 601
 602         struct ctx_hw_stats     *hw_stats;
 603         dma_addr_t              hw_stats_map;
 604         u32                     hw_stats_ctx_id;
 605         u64                     rx_l4_csum_errors;
 606
 607         struct bnxt_ring_struct cp_ring_struct;
 608 };
 609
 610 struct bnxt_napi {
 611         struct napi_struct      napi;
 612         struct bnxt             *bp;
 613
 614         int                     index;
 615         struct bnxt_cp_ring_info        cp_ring;
 616         struct bnxt_rx_ring_info        *rx_ring;
 617         struct bnxt_tx_ring_info        *tx_ring;
 618
 619 #ifdef CONFIG_NET_RX_BUSY_POLL
 620         atomic_t                poll_state;
 621 #endif
 622 };
 623
 624 #ifdef CONFIG_NET_RX_BUSY_POLL
 625 enum bnxt_poll_state_t {
 626         BNXT_STATE_IDLE = 0,
 627         BNXT_STATE_NAPI,
 628         BNXT_STATE_POLL,
 629         BNXT_STATE_DISABLE,
 630 };
 631 #endif
 632
 633 struct bnxt_irq {
 634         irq_handler_t   handler;
 635         unsigned int    vector;
 636         u8              requested;
 637         char            name[IFNAMSIZ + 2];
 638 };
 639
 640 #define HWRM_RING_ALLOC_TX      0x1
 641 #define HWRM_RING_ALLOC_RX      0x2
 642 #define HWRM_RING_ALLOC_AGG     0x4
 643 #define HWRM_RING_ALLOC_CMPL    0x8
 644
 645 #define INVALID_STATS_CTX_ID    -1
 646
 647 struct hwrm_cmd_req_hdr {
 648 #define HWRM_CMPL_RING_MASK     0xffff0000
 649 #define HWRM_CMPL_RING_SFT      16
 650         __le32  cmpl_ring_req_type;
 651 #define HWRM_SEQ_ID_MASK        0xffff
 652 #define HWRM_SEQ_ID_INVALID -1
 653 #define HWRM_RESP_LEN_OFFSET    4
 654 #define HWRM_TARGET_FID_MASK    0xffff0000
 655 #define HWRM_TARGET_FID_SFT     16
 656         __le32  target_id_seq_id;
 657         __le64  resp_addr;
 658 };
 659
 660 struct bnxt_ring_grp_info {
 661         u16     fw_stats_ctx;
 662         u16     fw_grp_id;
 663         u16     rx_fw_ring_id;
 664         u16     agg_fw_ring_id;
 665         u16     cp_fw_ring_id;
 666 };
 667
 668 struct bnxt_vnic_info {
 669         u16             fw_vnic_id; /* returned by Chimp during alloc */
 670         u16             fw_rss_cos_lb_ctx;
 671         u16             fw_l2_ctx_id;
 672 #define BNXT_MAX_UC_ADDRS       4
 673         __le64          fw_l2_filter_id[BNXT_MAX_UC_ADDRS];
 674                                 /* index 0 always dev_addr */
 675         u16             uc_filter_count;
 676         u8              *uc_list;
 677
 678         u16             *fw_grp_ids;
 679         u16             hash_type;
 680         dma_addr_t      rss_table_dma_addr;
 681         __le16          *rss_table;
 682         dma_addr_t      rss_hash_key_dma_addr;
 683         u64             *rss_hash_key;
 684         u32             rx_mask;
 685
 686         u8              *mc_list;
 687         int             mc_list_size;
 688         int             mc_list_count;
 689         dma_addr_t      mc_list_mapping;
 690 #define BNXT_MAX_MC_ADDRS       16
 691
 692         u32             flags;
 693 #define BNXT_VNIC_RSS_FLAG      1
 694 #define BNXT_VNIC_RFS_FLAG      2
 695 #define BNXT_VNIC_MCAST_FLAG    4
 696 #define BNXT_VNIC_UCAST_FLAG    8
 697 };
 698
 699 #if defined(CONFIG_BNXT_SRIOV)
 700 struct bnxt_vf_info {
 701         u16     fw_fid;
 702         u8      mac_addr[ETH_ALEN];
 703         u16     max_rsscos_ctxs;
 704         u16     max_cp_rings;
 705         u16     max_tx_rings;
 706         u16     max_rx_rings;
 707         u16     max_hw_ring_grps;
 708         u16     max_l2_ctxs;
 709         u16     max_irqs;
 710         u16     max_vnics;
 711         u16     max_stat_ctxs;
 712         u16     vlan;
 713         u32     flags;
 714 #define BNXT_VF_QOS             0x1
 715 #define BNXT_VF_SPOOFCHK        0x2
 716 #define BNXT_VF_LINK_FORCED     0x4
 717 #define BNXT_VF_LINK_UP         0x8
 718         u32     func_flags; /* func cfg flags */
 719         u32     min_tx_rate;
 720         u32     max_tx_rate;
 721         void    *hwrm_cmd_req_addr;
 722         dma_addr_t      hwrm_cmd_req_dma_addr;
 723 };
 724 #endif
 725
 726 struct bnxt_pf_info {
 727 #define BNXT_FIRST_PF_FID       1
 728 #define BNXT_FIRST_VF_FID       128
 729         u32     fw_fid;
 730         u8      port_id;
 731         u8      mac_addr[ETH_ALEN];
 732         u16     max_rsscos_ctxs;
 733         u16     max_cp_rings;
 734         u16     max_tx_rings; /* HW assigned max tx rings for this PF */
 735         u16     max_rx_rings; /* HW assigned max rx rings for this PF */
 736         u16     max_hw_ring_grps;
 737         u16     max_irqs;
 738         u16     max_l2_ctxs;
 739         u16     max_vnics;
 740         u16     max_stat_ctxs;
 741         u32     first_vf_id;
 742         u16     active_vfs;
 743         u16     max_vfs;
 744         u32     max_encap_records;
 745         u32     max_decap_records;
 746         u32     max_tx_em_flows;
 747         u32     max_tx_wm_flows;
 748         u32     max_rx_em_flows;
 749         u32     max_rx_wm_flows;
 750         unsigned long   *vf_event_bmap;
 751         u16     hwrm_cmd_req_pages;
 752         void                    *hwrm_cmd_req_addr[4];
 753         dma_addr_t              hwrm_cmd_req_dma_addr[4];
 754         struct bnxt_vf_info     *vf;
 755 };
 756
 757 struct bnxt_ntuple_filter {
 758         struct hlist_node       hash;
 759         u8                      src_mac_addr[ETH_ALEN];
 760         struct flow_keys        fkeys;
 761         __le64                  filter_id;
 762         u16                     sw_id;
 763         u16                     rxq;
 764         u32                     flow_id;
 765         unsigned long           state;
 766 #define BNXT_FLTR_VALID         0
 767 #define BNXT_FLTR_UPDATE        1
 768 };
 769
 770 #define BNXT_ALL_COPPER_ETHTOOL_SPEED                           \
 771         (ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full | \
 772          ADVERTISED_10000baseT_Full)
 773
 774 struct bnxt_link_info {
 775         u8                      media_type;
 776         u8                      transceiver;
 777         u8                      phy_addr;
 778         u8                      phy_link_status;
 779 #define BNXT_LINK_NO_LINK       PORT_PHY_QCFG_RESP_LINK_NO_LINK
 780 #define BNXT_LINK_SIGNAL        PORT_PHY_QCFG_RESP_LINK_SIGNAL
 781 #define BNXT_LINK_LINK          PORT_PHY_QCFG_RESP_LINK_LINK
 782         u8                      wire_speed;
 783         u8                      loop_back;
 784         u8                      link_up;
 785         u8                      duplex;
 786 #define BNXT_LINK_DUPLEX_HALF   PORT_PHY_QCFG_RESP_DUPLEX_HALF
 787 #define BNXT_LINK_DUPLEX_FULL   PORT_PHY_QCFG_RESP_DUPLEX_FULL
 788         u8                      pause;
 789 #define BNXT_LINK_PAUSE_TX      PORT_PHY_QCFG_RESP_PAUSE_TX
 790 #define BNXT_LINK_PAUSE_RX      PORT_PHY_QCFG_RESP_PAUSE_RX
 791 #define BNXT_LINK_PAUSE_BOTH    (PORT_PHY_QCFG_RESP_PAUSE_RX | \
 792                                  PORT_PHY_QCFG_RESP_PAUSE_TX)
 793         u8                      auto_pause_setting;
 794         u8                      force_pause_setting;
 795         u8                      duplex_setting;
 796         u8                      auto_mode;
 797 #define BNXT_AUTO_MODE(mode)    ((mode) > BNXT_LINK_AUTO_NONE && \
 798                                  (mode) <= BNXT_LINK_AUTO_MSK)
 799 #define BNXT_LINK_AUTO_NONE     PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
 800 #define BNXT_LINK_AUTO_ALLSPDS  PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
 801 #define BNXT_LINK_AUTO_ONESPD   PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
 802 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
 803 #define BNXT_LINK_AUTO_MSK      PORT_PHY_QCFG_RESP_AUTO_MODE_MASK
 804 #define PHY_VER_LEN             3
 805         u8                      phy_ver[PHY_VER_LEN];
 806         u16                     link_speed;
 807 #define BNXT_LINK_SPEED_100MB   PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
 808 #define BNXT_LINK_SPEED_1GB     PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
 809 #define BNXT_LINK_SPEED_2GB     PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
 810 #define BNXT_LINK_SPEED_2_5GB   PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
 811 #define BNXT_LINK_SPEED_10GB    PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
 812 #define BNXT_LINK_SPEED_20GB    PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
 813 #define BNXT_LINK_SPEED_25GB    PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
 814 #define BNXT_LINK_SPEED_40GB    PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
 815 #define BNXT_LINK_SPEED_50GB    PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
 816         u16                     support_speeds;
 817         u16                     auto_link_speeds;
 818 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
 819 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
 820 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
 821 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
 822 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
 823 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
 824 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
 825 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
 826 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
 827         u16                     auto_link_speed;
 828         u16                     force_link_speed;
 829         u32                     preemphasis;
 830
 831         /* copy of requested setting from ethtool cmd */
 832         u8                      autoneg;
 833 #define BNXT_AUTONEG_SPEED              1
 834 #define BNXT_AUTONEG_FLOW_CTRL          2
 835         u8                      req_duplex;
 836         u8                      req_flow_ctrl;
 837         u16                     req_link_speed;
 838         u32                     advertising;
 839         bool                    force_link_chng;
 840         /* a copy of phy_qcfg output used to report link
 841          * info to VF
 842          */
 843         struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
 844 };
 845
 846 #define BNXT_MAX_QUEUE  8
 847
 848 struct bnxt_queue_info {
 849         u8      queue_id;
 850         u8      queue_profile;
 851 };
 852
 853 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT  0x400
 854 #define BNXT_CAG_REG_LEGACY_INT_STATUS  0x4014
 855 #define BNXT_CAG_REG_BASE               0x300000
 856
 857 struct bnxt {
 858         void __iomem            *bar0;
 859         void __iomem            *bar1;
 860         void __iomem            *bar2;
 861
 862         u32                     reg_base;
 863
 864         struct net_device       *dev;
 865         struct pci_dev          *pdev;
 866
 867         atomic_t                intr_sem;
 868
 869         u32                     flags;
 870         #define BNXT_FLAG_DCB_ENABLED   0x1
 871         #define BNXT_FLAG_VF            0x2
 872         #define BNXT_FLAG_LRO           0x4
 873 #ifdef CONFIG_INET
 874         #define BNXT_FLAG_GRO           0x8
 875 #else
 876         /* Cannot support hardware GRO if CONFIG_INET is not set */
 877         #define BNXT_FLAG_GRO           0x0
 878 #endif
 879         #define BNXT_FLAG_TPA           (BNXT_FLAG_LRO | BNXT_FLAG_GRO)
 880         #define BNXT_FLAG_JUMBO         0x10
 881         #define BNXT_FLAG_STRIP_VLAN    0x20
 882         #define BNXT_FLAG_AGG_RINGS     (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
 883                                          BNXT_FLAG_LRO)
 884         #define BNXT_FLAG_USING_MSIX    0x40
 885         #define BNXT_FLAG_MSIX_CAP      0x80
 886         #define BNXT_FLAG_RFS           0x100
 887         #define BNXT_FLAG_SHARED_RINGS  0x200
 888
 889         #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA |             \
 890                                             BNXT_FLAG_RFS |             \
 891                                             BNXT_FLAG_STRIP_VLAN)
 892
 893 #define BNXT_PF(bp)             (!((bp)->flags & BNXT_FLAG_VF))
 894 #define BNXT_VF(bp)             ((bp)->flags & BNXT_FLAG_VF)
 895
 896         struct bnxt_napi        **bnapi;
 897
 898         struct bnxt_rx_ring_info        *rx_ring;
 899         struct bnxt_tx_ring_info        *tx_ring;
 900
 901         u32                     rx_buf_size;
 902         u32                     rx_buf_use_size;        /* useable size */
 903         u32                     rx_ring_size;
 904         u32                     rx_agg_ring_size;
 905         u32                     rx_copy_thresh;
 906         u32                     rx_ring_mask;
 907         u32                     rx_agg_ring_mask;
 908         int                     rx_nr_pages;
 909         int                     rx_agg_nr_pages;
 910         int                     rx_nr_rings;
 911         int                     rsscos_nr_ctxs;
 912
 913         u32                     tx_ring_size;
 914         u32                     tx_ring_mask;
 915         int                     tx_nr_pages;
 916         int                     tx_nr_rings;
 917         int                     tx_nr_rings_per_tc;
 918
 919         int                     tx_wake_thresh;
 920         int                     tx_push_thresh;
 921         int                     tx_push_size;
 922
 923         u32                     cp_ring_size;
 924         u32                     cp_ring_mask;
 925         u32                     cp_bit;
 926         int                     cp_nr_pages;
 927         int                     cp_nr_rings;
 928
 929         int                     num_stat_ctxs;
 930
 931         /* grp_info indexed by completion ring index */
 932         struct bnxt_ring_grp_info       *grp_info;
 933         struct bnxt_vnic_info   *vnic_info;
 934         int                     nr_vnics;
 935
 936         u8                      max_tc;
 937         struct bnxt_queue_info  q_info[BNXT_MAX_QUEUE];
 938
 939         unsigned int            current_interval;
 940 #define BNXT_TIMER_INTERVAL     (HZ / 2)
 941
 942         struct timer_list       timer;
 943
 944         unsigned long           state;
 945 #define BNXT_STATE_OPEN         0
 946 #define BNXT_STATE_IN_SP_TASK   1
 947
 948         struct bnxt_irq *irq_tbl;
 949         u8                      mac_addr[ETH_ALEN];
 950
 951         u32                     msg_enable;
 952
 953         u16                     hwrm_cmd_seq;
 954         u32                     hwrm_intr_seq_id;
 955         void                    *hwrm_cmd_resp_addr;
 956         dma_addr_t              hwrm_cmd_resp_dma_addr;
 957         void                    *hwrm_dbg_resp_addr;
 958         dma_addr_t              hwrm_dbg_resp_dma_addr;
 959 #define HWRM_DBG_REG_BUF_SIZE   128
 960         struct mutex            hwrm_cmd_lock;  /* serialize hwrm messages */
 961         struct hwrm_ver_get_output      ver_resp;
 962 #define FW_VER_STR_LEN          32
 963 #define BC_HWRM_STR_LEN         21
 964 #define PHY_VER_STR_LEN         (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
 965         char                    fw_ver_str[FW_VER_STR_LEN];
 966         __be16                  vxlan_port;
 967         u8                      vxlan_port_cnt;
 968         __le16                  vxlan_fw_dst_port_id;
 969         u8                      nge_port_cnt;
 970         __le16                  nge_fw_dst_port_id;
 971         u16                     coal_ticks;
 972         u16                     coal_ticks_irq;
 973         u16                     coal_bufs;
 974         u16                     coal_bufs_irq;
 975
 976 #define BNXT_USEC_TO_COAL_TIMER(x)      ((x) * 25 / 2)
 977 #define BNXT_COAL_TIMER_TO_USEC(x) ((x) * 2 / 25)
 978
 979         struct work_struct      sp_task;
 980         unsigned long           sp_event;
 981 #define BNXT_RX_MASK_SP_EVENT           0
 982 #define BNXT_RX_NTP_FLTR_SP_EVENT       1
 983 #define BNXT_LINK_CHNG_SP_EVENT         2
 984 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
 985 #define BNXT_VXLAN_ADD_PORT_SP_EVENT    4
 986 #define BNXT_VXLAN_DEL_PORT_SP_EVENT    5
 987 #define BNXT_RESET_TASK_SP_EVENT        6
 988 #define BNXT_RST_RING_SP_EVENT          7
 989
 990         struct bnxt_pf_info     pf;
 991 #ifdef CONFIG_BNXT_SRIOV
 992         int                     nr_vfs;
 993         struct bnxt_vf_info     vf;
 994         wait_queue_head_t       sriov_cfg_wait;
 995         bool                    sriov_cfg;
 996 #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000)
 997 #endif
 998
 999 #define BNXT_NTP_FLTR_MAX_FLTR  4096
1000 #define BNXT_NTP_FLTR_HASH_SIZE 512
1001 #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1)
1002         struct hlist_head       ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
1003         spinlock_t              ntp_fltr_lock;  /* for hash table add, del */
1004
1005         unsigned long           *ntp_fltr_bmap;
1006         int                     ntp_fltr_count;
1007
1008         struct bnxt_link_info   link_info;
1009 };
1010
1011 #ifdef CONFIG_NET_RX_BUSY_POLL
1012 static inline void bnxt_enable_poll(struct bnxt_napi *bnapi)
1013 {
1014         atomic_set(&bnapi->poll_state, BNXT_STATE_IDLE);
1015 }
1016
1017 /* called from the NAPI poll routine to get ownership of a bnapi */
1018 static inline bool bnxt_lock_napi(struct bnxt_napi *bnapi)
1019 {
1020         int rc = atomic_cmpxchg(&bnapi->poll_state, BNXT_STATE_IDLE,
1021                                 BNXT_STATE_NAPI);
1022
1023         return rc == BNXT_STATE_IDLE;
1024 }
1025
1026 static inline void bnxt_unlock_napi(struct bnxt_napi *bnapi)
1027 {
1028         atomic_set(&bnapi->poll_state, BNXT_STATE_IDLE);
1029 }
1030
1031 /* called from the busy poll routine to get ownership of a bnapi */
1032 static inline bool bnxt_lock_poll(struct bnxt_napi *bnapi)
1033 {
1034         int rc = atomic_cmpxchg(&bnapi->poll_state, BNXT_STATE_IDLE,
1035                                 BNXT_STATE_POLL);
1036
1037         return rc == BNXT_STATE_IDLE;
1038 }
1039
1040 static inline void bnxt_unlock_poll(struct bnxt_napi *bnapi)
1041 {
1042         atomic_set(&bnapi->poll_state, BNXT_STATE_IDLE);
1043 }
1044
1045 static inline bool bnxt_busy_polling(struct bnxt_napi *bnapi)
1046 {
1047         return atomic_read(&bnapi->poll_state) == BNXT_STATE_POLL;
1048 }
1049
1050 static inline void bnxt_disable_poll(struct bnxt_napi *bnapi)
1051 {
1052         int old;
1053
1054         while (1) {
1055                 old = atomic_cmpxchg(&bnapi->poll_state, BNXT_STATE_IDLE,
1056                                      BNXT_STATE_DISABLE);
1057                 if (old == BNXT_STATE_IDLE)
1058                         break;
1059                 usleep_range(500, 5000);
1060         }
1061 }
1062
1063 #else
1064
1065 static inline void bnxt_enable_poll(struct bnxt_napi *bnapi)
1066 {
1067 }
1068
1069 static inline bool bnxt_lock_napi(struct bnxt_napi *bnapi)
1070 {
1071         return true;
1072 }
1073
1074 static inline void bnxt_unlock_napi(struct bnxt_napi *bnapi)
1075 {
1076 }
1077
1078 static inline bool bnxt_lock_poll(struct bnxt_napi *bnapi)
1079 {
1080         return false;
1081 }
1082
1083 static inline void bnxt_unlock_poll(struct bnxt_napi *bnapi)
1084 {
1085 }
1086
1087 static inline bool bnxt_busy_polling(struct bnxt_napi *bnapi)
1088 {
1089         return false;
1090 }
1091
1092 static inline void bnxt_disable_poll(struct bnxt_napi *bnapi)
1093 {
1094 }
1095
1096 #endif
1097
1098 void bnxt_set_ring_params(struct bnxt *);
1099 void bnxt_hwrm_cmd_hdr_init(struct bnxt *, void *, u16, u16, u16);
1100 int _hwrm_send_message(struct bnxt *, void *, u32, int);
1101 int hwrm_send_message(struct bnxt *, void *, u32, int);
1102 int bnxt_hwrm_set_coal(struct bnxt *);
1103 int bnxt_hwrm_func_qcaps(struct bnxt *);
1104 int bnxt_hwrm_set_pause(struct bnxt *);
1105 int bnxt_hwrm_set_link_setting(struct bnxt *, bool);
1106 int bnxt_open_nic(struct bnxt *, bool, bool);
1107 int bnxt_close_nic(struct bnxt *, bool, bool);
1108 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
1109 #endif