2 * Cadence MACB/GEM Ethernet Controller driver
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/circ_buf.h>
18 #include <linux/slab.h>
19 #include <linux/init.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_data/macb.h>
27 #include <linux/platform_device.h>
28 #include <linux/phy.h>
30 #include <linux/of_device.h>
31 #include <linux/of_mdio.h>
32 #include <linux/of_net.h>
33 #include <linux/pinctrl/consumer.h>
37 #define MACB_RX_BUFFER_SIZE 128
38 #define RX_BUFFER_MULTIPLE 64 /* bytes */
39 #define RX_RING_SIZE 512 /* must be power of 2 */
40 #define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
42 #define TX_RING_SIZE 128 /* must be power of 2 */
43 #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
45 /* level of occupied TX descriptors under which we wake up TX process */
46 #define MACB_TX_WAKEUP_THRESH (3 * TX_RING_SIZE / 4)
48 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
50 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
53 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
55 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1))
56 #define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1))
59 * Graceful stop timeouts in us. We should allow up to
60 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
62 #define MACB_HALT_TIMEOUT 1230
64 /* Ring buffer accessors */
65 static unsigned int macb_tx_ring_wrap(unsigned int index)
67 return index & (TX_RING_SIZE - 1);
70 static struct macb_dma_desc *macb_tx_desc(struct macb *bp, unsigned int index)
72 return &bp->tx_ring[macb_tx_ring_wrap(index)];
75 static struct macb_tx_skb *macb_tx_skb(struct macb *bp, unsigned int index)
77 return &bp->tx_skb[macb_tx_ring_wrap(index)];
80 static dma_addr_t macb_tx_dma(struct macb *bp, unsigned int index)
84 offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc);
86 return bp->tx_ring_dma + offset;
89 static unsigned int macb_rx_ring_wrap(unsigned int index)
91 return index & (RX_RING_SIZE - 1);
94 static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
96 return &bp->rx_ring[macb_rx_ring_wrap(index)];
99 static void *macb_rx_buffer(struct macb *bp, unsigned int index)
101 return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index);
104 void macb_set_hwaddr(struct macb *bp)
109 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
110 macb_or_gem_writel(bp, SA1B, bottom);
111 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
112 macb_or_gem_writel(bp, SA1T, top);
114 /* Clear unused address register sets */
115 macb_or_gem_writel(bp, SA2B, 0);
116 macb_or_gem_writel(bp, SA2T, 0);
117 macb_or_gem_writel(bp, SA3B, 0);
118 macb_or_gem_writel(bp, SA3T, 0);
119 macb_or_gem_writel(bp, SA4B, 0);
120 macb_or_gem_writel(bp, SA4T, 0);
122 EXPORT_SYMBOL_GPL(macb_set_hwaddr);
124 void macb_get_hwaddr(struct macb *bp)
126 struct macb_platform_data *pdata;
132 pdata = dev_get_platdata(&bp->pdev->dev);
134 /* Check all 4 address register for vaild address */
135 for (i = 0; i < 4; i++) {
136 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
137 top = macb_or_gem_readl(bp, SA1T + i * 8);
139 if (pdata && pdata->rev_eth_addr) {
140 addr[5] = bottom & 0xff;
141 addr[4] = (bottom >> 8) & 0xff;
142 addr[3] = (bottom >> 16) & 0xff;
143 addr[2] = (bottom >> 24) & 0xff;
144 addr[1] = top & 0xff;
145 addr[0] = (top & 0xff00) >> 8;
147 addr[0] = bottom & 0xff;
148 addr[1] = (bottom >> 8) & 0xff;
149 addr[2] = (bottom >> 16) & 0xff;
150 addr[3] = (bottom >> 24) & 0xff;
151 addr[4] = top & 0xff;
152 addr[5] = (top >> 8) & 0xff;
155 if (is_valid_ether_addr(addr)) {
156 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
161 netdev_info(bp->dev, "invalid hw address, using random\n");
162 eth_hw_addr_random(bp->dev);
164 EXPORT_SYMBOL_GPL(macb_get_hwaddr);
166 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
168 struct macb *bp = bus->priv;
171 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
172 | MACB_BF(RW, MACB_MAN_READ)
173 | MACB_BF(PHYA, mii_id)
174 | MACB_BF(REGA, regnum)
175 | MACB_BF(CODE, MACB_MAN_CODE)));
177 /* wait for end of transfer */
178 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
181 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
186 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
189 struct macb *bp = bus->priv;
191 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
192 | MACB_BF(RW, MACB_MAN_WRITE)
193 | MACB_BF(PHYA, mii_id)
194 | MACB_BF(REGA, regnum)
195 | MACB_BF(CODE, MACB_MAN_CODE)
196 | MACB_BF(DATA, value)));
198 /* wait for end of transfer */
199 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
206 * macb_set_tx_clk() - Set a clock to a new frequency
207 * @clk Pointer to the clock to change
208 * @rate New frequency in Hz
209 * @dev Pointer to the struct net_device
211 static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
213 long ferr, rate, rate_rounded;
229 rate_rounded = clk_round_rate(clk, rate);
230 if (rate_rounded < 0)
233 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
236 ferr = abs(rate_rounded - rate);
237 ferr = DIV_ROUND_UP(ferr, rate / 100000);
239 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
242 if (clk_set_rate(clk, rate_rounded))
243 netdev_err(dev, "adjusting tx_clk failed.\n");
246 static void macb_handle_link_change(struct net_device *dev)
248 struct macb *bp = netdev_priv(dev);
249 struct phy_device *phydev = bp->phy_dev;
252 int status_change = 0;
254 spin_lock_irqsave(&bp->lock, flags);
257 if ((bp->speed != phydev->speed) ||
258 (bp->duplex != phydev->duplex)) {
261 reg = macb_readl(bp, NCFGR);
262 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
264 reg &= ~GEM_BIT(GBE);
268 if (phydev->speed == SPEED_100)
269 reg |= MACB_BIT(SPD);
270 if (phydev->speed == SPEED_1000 &&
271 bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
274 macb_or_gem_writel(bp, NCFGR, reg);
276 bp->speed = phydev->speed;
277 bp->duplex = phydev->duplex;
282 if (phydev->link != bp->link) {
287 bp->link = phydev->link;
292 spin_unlock_irqrestore(&bp->lock, flags);
294 if (!IS_ERR(bp->tx_clk))
295 macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
299 netif_carrier_on(dev);
300 netdev_info(dev, "link up (%d/%s)\n",
302 phydev->duplex == DUPLEX_FULL ?
305 netif_carrier_off(dev);
306 netdev_info(dev, "link down\n");
311 /* based on au1000_eth. c*/
312 static int macb_mii_probe(struct net_device *dev)
314 struct macb *bp = netdev_priv(dev);
315 struct macb_platform_data *pdata;
316 struct phy_device *phydev;
320 phydev = phy_find_first(bp->mii_bus);
322 netdev_err(dev, "no PHY found\n");
326 pdata = dev_get_platdata(&bp->pdev->dev);
327 if (pdata && gpio_is_valid(pdata->phy_irq_pin)) {
328 ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin, "phy int");
330 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
331 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
335 /* attach the mac to the phy */
336 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
339 netdev_err(dev, "Could not attach to PHY\n");
343 /* mask with MAC supported features */
344 if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
345 phydev->supported &= PHY_GBIT_FEATURES;
347 phydev->supported &= PHY_BASIC_FEATURES;
349 phydev->advertising = phydev->supported;
354 bp->phy_dev = phydev;
359 int macb_mii_init(struct macb *bp)
361 struct macb_platform_data *pdata;
362 struct device_node *np;
365 /* Enable management port */
366 macb_writel(bp, NCR, MACB_BIT(MPE));
368 bp->mii_bus = mdiobus_alloc();
369 if (bp->mii_bus == NULL) {
374 bp->mii_bus->name = "MACB_mii_bus";
375 bp->mii_bus->read = &macb_mdio_read;
376 bp->mii_bus->write = &macb_mdio_write;
377 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
378 bp->pdev->name, bp->pdev->id);
379 bp->mii_bus->priv = bp;
380 bp->mii_bus->parent = &bp->dev->dev;
381 pdata = dev_get_platdata(&bp->pdev->dev);
383 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
384 if (!bp->mii_bus->irq) {
386 goto err_out_free_mdiobus;
389 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
391 np = bp->pdev->dev.of_node;
393 /* try dt phy registration */
394 err = of_mdiobus_register(bp->mii_bus, np);
396 /* fallback to standard phy registration if no phy were
397 found during dt phy registration */
398 if (!err && !phy_find_first(bp->mii_bus)) {
399 for (i = 0; i < PHY_MAX_ADDR; i++) {
400 struct phy_device *phydev;
402 phydev = mdiobus_scan(bp->mii_bus, i);
403 if (IS_ERR(phydev)) {
404 err = PTR_ERR(phydev);
410 goto err_out_unregister_bus;
413 for (i = 0; i < PHY_MAX_ADDR; i++)
414 bp->mii_bus->irq[i] = PHY_POLL;
417 bp->mii_bus->phy_mask = pdata->phy_mask;
419 err = mdiobus_register(bp->mii_bus);
423 goto err_out_free_mdio_irq;
425 err = macb_mii_probe(bp->dev);
427 goto err_out_unregister_bus;
431 err_out_unregister_bus:
432 mdiobus_unregister(bp->mii_bus);
433 err_out_free_mdio_irq:
434 kfree(bp->mii_bus->irq);
435 err_out_free_mdiobus:
436 mdiobus_free(bp->mii_bus);
440 EXPORT_SYMBOL_GPL(macb_mii_init);
442 static void macb_update_stats(struct macb *bp)
444 u32 __iomem *reg = bp->regs + MACB_PFR;
445 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
446 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
448 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
450 for(; p < end; p++, reg++)
451 *p += __raw_readl(reg);
454 static int macb_halt_tx(struct macb *bp)
456 unsigned long halt_time, timeout;
459 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
461 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
464 status = macb_readl(bp, TSR);
465 if (!(status & MACB_BIT(TGO)))
468 usleep_range(10, 250);
469 } while (time_before(halt_time, timeout));
474 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
476 if (tx_skb->mapping) {
477 if (tx_skb->mapped_as_page)
478 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
479 tx_skb->size, DMA_TO_DEVICE);
481 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
482 tx_skb->size, DMA_TO_DEVICE);
487 dev_kfree_skb_any(tx_skb->skb);
492 static void macb_tx_error_task(struct work_struct *work)
494 struct macb *bp = container_of(work, struct macb, tx_error_task);
495 struct macb_tx_skb *tx_skb;
499 netdev_vdbg(bp->dev, "macb_tx_error_task: t = %u, h = %u\n",
500 bp->tx_tail, bp->tx_head);
502 /* Make sure nobody is trying to queue up new packets */
503 netif_stop_queue(bp->dev);
506 * Stop transmission now
507 * (in case we have just queued new packets)
509 if (macb_halt_tx(bp))
510 /* Just complain for now, reinitializing TX path can be good */
511 netdev_err(bp->dev, "BUG: halt tx timed out\n");
513 /* No need for the lock here as nobody will interrupt us anymore */
516 * Treat frames in TX queue including the ones that caused the error.
517 * Free transmit buffers in upper layer.
519 for (tail = bp->tx_tail; tail != bp->tx_head; tail++) {
520 struct macb_dma_desc *desc;
523 desc = macb_tx_desc(bp, tail);
525 tx_skb = macb_tx_skb(bp, tail);
528 if (ctrl & MACB_BIT(TX_USED)) {
529 /* skb is set for the last buffer of the frame */
531 macb_tx_unmap(bp, tx_skb);
533 tx_skb = macb_tx_skb(bp, tail);
537 /* ctrl still refers to the first buffer descriptor
538 * since it's the only one written back by the hardware
540 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
541 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
542 macb_tx_ring_wrap(tail), skb->data);
543 bp->stats.tx_packets++;
544 bp->stats.tx_bytes += skb->len;
548 * "Buffers exhausted mid-frame" errors may only happen
549 * if the driver is buggy, so complain loudly about those.
550 * Statistics are updated by hardware.
552 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
554 "BUG: TX buffers exhausted mid-frame\n");
556 desc->ctrl = ctrl | MACB_BIT(TX_USED);
559 macb_tx_unmap(bp, tx_skb);
562 /* Make descriptor updates visible to hardware */
565 /* Reinitialize the TX desc queue */
566 macb_writel(bp, TBQP, bp->tx_ring_dma);
567 /* Make TX ring reflect state of hardware */
568 bp->tx_head = bp->tx_tail = 0;
570 /* Now we are ready to start transmission again */
571 netif_wake_queue(bp->dev);
573 /* Housework before enabling TX IRQ */
574 macb_writel(bp, TSR, macb_readl(bp, TSR));
575 macb_writel(bp, IER, MACB_TX_INT_FLAGS);
578 static void macb_tx_interrupt(struct macb *bp)
584 status = macb_readl(bp, TSR);
585 macb_writel(bp, TSR, status);
587 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
588 macb_writel(bp, ISR, MACB_BIT(TCOMP));
590 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
591 (unsigned long)status);
594 for (tail = bp->tx_tail; tail != head; tail++) {
595 struct macb_tx_skb *tx_skb;
597 struct macb_dma_desc *desc;
600 desc = macb_tx_desc(bp, tail);
602 /* Make hw descriptor updates visible to CPU */
607 /* TX_USED bit is only set by hardware on the very first buffer
608 * descriptor of the transmitted frame.
610 if (!(ctrl & MACB_BIT(TX_USED)))
613 /* Process all buffers of the current transmitted frame */
615 tx_skb = macb_tx_skb(bp, tail);
618 /* First, update TX stats if needed */
620 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
621 macb_tx_ring_wrap(tail), skb->data);
622 bp->stats.tx_packets++;
623 bp->stats.tx_bytes += skb->len;
626 /* Now we can safely release resources */
627 macb_tx_unmap(bp, tx_skb);
629 /* skb is set only for the last buffer of the frame.
630 * WARNING: at this point skb has been freed by
639 if (netif_queue_stopped(bp->dev)
640 && CIRC_CNT(bp->tx_head, bp->tx_tail,
641 TX_RING_SIZE) <= MACB_TX_WAKEUP_THRESH)
642 netif_wake_queue(bp->dev);
645 static void gem_rx_refill(struct macb *bp)
651 while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail, RX_RING_SIZE) > 0) {
652 entry = macb_rx_ring_wrap(bp->rx_prepared_head);
654 /* Make hw descriptor updates visible to CPU */
657 bp->rx_prepared_head++;
659 if (bp->rx_skbuff[entry] == NULL) {
660 /* allocate sk_buff for this free entry in ring */
661 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
662 if (unlikely(skb == NULL)) {
664 "Unable to allocate sk_buff\n");
668 /* now fill corresponding descriptor entry */
669 paddr = dma_map_single(&bp->pdev->dev, skb->data,
670 bp->rx_buffer_size, DMA_FROM_DEVICE);
671 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
676 bp->rx_skbuff[entry] = skb;
678 if (entry == RX_RING_SIZE - 1)
679 paddr |= MACB_BIT(RX_WRAP);
680 bp->rx_ring[entry].addr = paddr;
681 bp->rx_ring[entry].ctrl = 0;
683 /* properly align Ethernet header */
684 skb_reserve(skb, NET_IP_ALIGN);
688 /* Make descriptor updates visible to hardware */
691 netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n",
692 bp->rx_prepared_head, bp->rx_tail);
695 /* Mark DMA descriptors from begin up to and not including end as unused */
696 static void discard_partial_frame(struct macb *bp, unsigned int begin,
701 for (frag = begin; frag != end; frag++) {
702 struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
703 desc->addr &= ~MACB_BIT(RX_USED);
706 /* Make descriptor updates visible to hardware */
710 * When this happens, the hardware stats registers for
711 * whatever caused this is updated, so we don't have to record
716 static int gem_rx(struct macb *bp, int budget)
721 struct macb_dma_desc *desc;
724 while (count < budget) {
727 entry = macb_rx_ring_wrap(bp->rx_tail);
728 desc = &bp->rx_ring[entry];
730 /* Make hw descriptor updates visible to CPU */
736 if (!(addr & MACB_BIT(RX_USED)))
742 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
744 "not whole frame pointed by descriptor\n");
745 bp->stats.rx_dropped++;
748 skb = bp->rx_skbuff[entry];
749 if (unlikely(!skb)) {
751 "inconsistent Rx descriptor chain\n");
752 bp->stats.rx_dropped++;
755 /* now everything is ready for receiving packet */
756 bp->rx_skbuff[entry] = NULL;
757 len = MACB_BFEXT(RX_FRMLEN, ctrl);
759 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
762 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, addr));
763 dma_unmap_single(&bp->pdev->dev, addr,
764 bp->rx_buffer_size, DMA_FROM_DEVICE);
766 skb->protocol = eth_type_trans(skb, bp->dev);
767 skb_checksum_none_assert(skb);
768 if (bp->dev->features & NETIF_F_RXCSUM &&
769 !(bp->dev->flags & IFF_PROMISC) &&
770 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
771 skb->ip_summed = CHECKSUM_UNNECESSARY;
773 bp->stats.rx_packets++;
774 bp->stats.rx_bytes += skb->len;
776 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
777 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
778 skb->len, skb->csum);
779 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
780 skb->mac_header, 16, true);
781 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
782 skb->data, 32, true);
785 netif_receive_skb(skb);
793 static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
794 unsigned int last_frag)
800 struct macb_dma_desc *desc;
802 desc = macb_rx_desc(bp, last_frag);
803 len = MACB_BFEXT(RX_FRMLEN, desc->ctrl);
805 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
806 macb_rx_ring_wrap(first_frag),
807 macb_rx_ring_wrap(last_frag), len);
810 * The ethernet header starts NET_IP_ALIGN bytes into the
811 * first buffer. Since the header is 14 bytes, this makes the
812 * payload word-aligned.
814 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
815 * the two padding bytes into the skb so that we avoid hitting
816 * the slowpath in memcpy(), and pull them off afterwards.
818 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
820 bp->stats.rx_dropped++;
821 for (frag = first_frag; ; frag++) {
822 desc = macb_rx_desc(bp, frag);
823 desc->addr &= ~MACB_BIT(RX_USED);
824 if (frag == last_frag)
828 /* Make descriptor updates visible to hardware */
836 skb_checksum_none_assert(skb);
839 for (frag = first_frag; ; frag++) {
840 unsigned int frag_len = bp->rx_buffer_size;
842 if (offset + frag_len > len) {
843 BUG_ON(frag != last_frag);
844 frag_len = len - offset;
846 skb_copy_to_linear_data_offset(skb, offset,
847 macb_rx_buffer(bp, frag), frag_len);
848 offset += bp->rx_buffer_size;
849 desc = macb_rx_desc(bp, frag);
850 desc->addr &= ~MACB_BIT(RX_USED);
852 if (frag == last_frag)
856 /* Make descriptor updates visible to hardware */
859 __skb_pull(skb, NET_IP_ALIGN);
860 skb->protocol = eth_type_trans(skb, bp->dev);
862 bp->stats.rx_packets++;
863 bp->stats.rx_bytes += skb->len;
864 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
865 skb->len, skb->csum);
866 netif_receive_skb(skb);
871 static int macb_rx(struct macb *bp, int budget)
877 for (tail = bp->rx_tail; budget > 0; tail++) {
878 struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
881 /* Make hw descriptor updates visible to CPU */
887 if (!(addr & MACB_BIT(RX_USED)))
890 if (ctrl & MACB_BIT(RX_SOF)) {
891 if (first_frag != -1)
892 discard_partial_frame(bp, first_frag, tail);
896 if (ctrl & MACB_BIT(RX_EOF)) {
898 BUG_ON(first_frag == -1);
900 dropped = macb_rx_frame(bp, first_frag, tail);
909 if (first_frag != -1)
910 bp->rx_tail = first_frag;
917 static int macb_poll(struct napi_struct *napi, int budget)
919 struct macb *bp = container_of(napi, struct macb, napi);
923 status = macb_readl(bp, RSR);
924 macb_writel(bp, RSR, status);
928 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
929 (unsigned long)status, budget);
931 work_done = bp->macbgem_ops.mog_rx(bp, budget);
932 if (work_done < budget) {
935 /* Packets received while interrupts were disabled */
936 status = macb_readl(bp, RSR);
938 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
939 macb_writel(bp, ISR, MACB_BIT(RCOMP));
940 napi_reschedule(napi);
942 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
946 /* TODO: Handle errors */
951 static irqreturn_t macb_interrupt(int irq, void *dev_id)
953 struct net_device *dev = dev_id;
954 struct macb *bp = netdev_priv(dev);
957 status = macb_readl(bp, ISR);
959 if (unlikely(!status))
962 spin_lock(&bp->lock);
965 /* close possible race with dev_close */
966 if (unlikely(!netif_running(dev))) {
967 macb_writel(bp, IDR, -1);
971 netdev_vdbg(bp->dev, "isr = 0x%08lx\n", (unsigned long)status);
973 if (status & MACB_RX_INT_FLAGS) {
975 * There's no point taking any more interrupts
976 * until we have processed the buffers. The
977 * scheduling call may fail if the poll routine
978 * is already scheduled, so disable interrupts
981 macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
982 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
983 macb_writel(bp, ISR, MACB_BIT(RCOMP));
985 if (napi_schedule_prep(&bp->napi)) {
986 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
987 __napi_schedule(&bp->napi);
991 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
992 macb_writel(bp, IDR, MACB_TX_INT_FLAGS);
993 schedule_work(&bp->tx_error_task);
995 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
996 macb_writel(bp, ISR, MACB_TX_ERR_FLAGS);
1001 if (status & MACB_BIT(TCOMP))
1002 macb_tx_interrupt(bp);
1005 * Link change detection isn't possible with RMII, so we'll
1006 * add that if/when we get our hands on a full-blown MII PHY.
1009 if (status & MACB_BIT(ISR_ROVR)) {
1010 /* We missed at least one packet */
1011 if (macb_is_gem(bp))
1012 bp->hw_stats.gem.rx_overruns++;
1014 bp->hw_stats.macb.rx_overruns++;
1016 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1017 macb_writel(bp, ISR, MACB_BIT(ISR_ROVR));
1020 if (status & MACB_BIT(HRESP)) {
1022 * TODO: Reset the hardware, and maybe move the
1023 * netdev_err to a lower-priority context as well
1026 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1028 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1029 macb_writel(bp, ISR, MACB_BIT(HRESP));
1032 status = macb_readl(bp, ISR);
1035 spin_unlock(&bp->lock);
1040 #ifdef CONFIG_NET_POLL_CONTROLLER
1042 * Polling receive - used by netconsole and other diagnostic tools
1043 * to allow network i/o with interrupts disabled.
1045 static void macb_poll_controller(struct net_device *dev)
1047 unsigned long flags;
1049 local_irq_save(flags);
1050 macb_interrupt(dev->irq, dev);
1051 local_irq_restore(flags);
1055 static inline unsigned int macb_count_tx_descriptors(struct macb *bp,
1058 return (len + bp->max_tx_length - 1) / bp->max_tx_length;
1061 static unsigned int macb_tx_map(struct macb *bp,
1062 struct sk_buff *skb)
1065 unsigned int len, entry, i, tx_head = bp->tx_head;
1066 struct macb_tx_skb *tx_skb = NULL;
1067 struct macb_dma_desc *desc;
1068 unsigned int offset, size, count = 0;
1069 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1070 unsigned int eof = 1;
1073 /* First, map non-paged data */
1074 len = skb_headlen(skb);
1077 size = min(len, bp->max_tx_length);
1078 entry = macb_tx_ring_wrap(tx_head);
1079 tx_skb = &bp->tx_skb[entry];
1081 mapping = dma_map_single(&bp->pdev->dev,
1083 size, DMA_TO_DEVICE);
1084 if (dma_mapping_error(&bp->pdev->dev, mapping))
1087 /* Save info to properly release resources */
1089 tx_skb->mapping = mapping;
1090 tx_skb->size = size;
1091 tx_skb->mapped_as_page = false;
1099 /* Then, map paged data from fragments */
1100 for (f = 0; f < nr_frags; f++) {
1101 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1103 len = skb_frag_size(frag);
1106 size = min(len, bp->max_tx_length);
1107 entry = macb_tx_ring_wrap(tx_head);
1108 tx_skb = &bp->tx_skb[entry];
1110 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1111 offset, size, DMA_TO_DEVICE);
1112 if (dma_mapping_error(&bp->pdev->dev, mapping))
1115 /* Save info to properly release resources */
1117 tx_skb->mapping = mapping;
1118 tx_skb->size = size;
1119 tx_skb->mapped_as_page = true;
1128 /* Should never happen */
1129 if (unlikely(tx_skb == NULL)) {
1130 netdev_err(bp->dev, "BUG! empty skb!\n");
1134 /* This is the last buffer of the frame: save socket buffer */
1137 /* Update TX ring: update buffer descriptors in reverse order
1138 * to avoid race condition
1141 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1142 * to set the end of TX queue
1145 entry = macb_tx_ring_wrap(i);
1146 ctrl = MACB_BIT(TX_USED);
1147 desc = &bp->tx_ring[entry];
1152 entry = macb_tx_ring_wrap(i);
1153 tx_skb = &bp->tx_skb[entry];
1154 desc = &bp->tx_ring[entry];
1156 ctrl = (u32)tx_skb->size;
1158 ctrl |= MACB_BIT(TX_LAST);
1161 if (unlikely(entry == (TX_RING_SIZE - 1)))
1162 ctrl |= MACB_BIT(TX_WRAP);
1164 /* Set TX buffer descriptor */
1165 desc->addr = tx_skb->mapping;
1166 /* desc->addr must be visible to hardware before clearing
1167 * 'TX_USED' bit in desc->ctrl.
1171 } while (i != bp->tx_head);
1173 bp->tx_head = tx_head;
1178 netdev_err(bp->dev, "TX DMA map failed\n");
1180 for (i = bp->tx_head; i != tx_head; i++) {
1181 tx_skb = macb_tx_skb(bp, i);
1183 macb_tx_unmap(bp, tx_skb);
1189 static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1191 struct macb *bp = netdev_priv(dev);
1192 unsigned long flags;
1193 unsigned int count, nr_frags, frag_size, f;
1195 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1196 netdev_vdbg(bp->dev,
1197 "start_xmit: len %u head %p data %p tail %p end %p\n",
1198 skb->len, skb->head, skb->data,
1199 skb_tail_pointer(skb), skb_end_pointer(skb));
1200 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1201 skb->data, 16, true);
1204 /* Count how many TX buffer descriptors are needed to send this
1205 * socket buffer: skb fragments of jumbo frames may need to be
1206 * splitted into many buffer descriptors.
1208 count = macb_count_tx_descriptors(bp, skb_headlen(skb));
1209 nr_frags = skb_shinfo(skb)->nr_frags;
1210 for (f = 0; f < nr_frags; f++) {
1211 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
1212 count += macb_count_tx_descriptors(bp, frag_size);
1215 spin_lock_irqsave(&bp->lock, flags);
1217 /* This is a hard error, log it. */
1218 if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < count) {
1219 netif_stop_queue(dev);
1220 spin_unlock_irqrestore(&bp->lock, flags);
1221 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
1222 bp->tx_head, bp->tx_tail);
1223 return NETDEV_TX_BUSY;
1226 /* Map socket buffer for DMA transfer */
1227 if (!macb_tx_map(bp, skb)) {
1228 dev_kfree_skb_any(skb);
1232 /* Make newly initialized descriptor visible to hardware */
1235 skb_tx_timestamp(skb);
1237 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1239 if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < 1)
1240 netif_stop_queue(dev);
1243 spin_unlock_irqrestore(&bp->lock, flags);
1245 return NETDEV_TX_OK;
1248 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1250 if (!macb_is_gem(bp)) {
1251 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1253 bp->rx_buffer_size = size;
1255 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
1257 "RX buffer must be multiple of %d bytes, expanding\n",
1258 RX_BUFFER_MULTIPLE);
1259 bp->rx_buffer_size =
1260 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1264 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%Zu]\n",
1265 bp->dev->mtu, bp->rx_buffer_size);
1268 static void gem_free_rx_buffers(struct macb *bp)
1270 struct sk_buff *skb;
1271 struct macb_dma_desc *desc;
1278 for (i = 0; i < RX_RING_SIZE; i++) {
1279 skb = bp->rx_skbuff[i];
1284 desc = &bp->rx_ring[i];
1285 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
1286 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
1288 dev_kfree_skb_any(skb);
1292 kfree(bp->rx_skbuff);
1293 bp->rx_skbuff = NULL;
1296 static void macb_free_rx_buffers(struct macb *bp)
1298 if (bp->rx_buffers) {
1299 dma_free_coherent(&bp->pdev->dev,
1300 RX_RING_SIZE * bp->rx_buffer_size,
1301 bp->rx_buffers, bp->rx_buffers_dma);
1302 bp->rx_buffers = NULL;
1306 static void macb_free_consistent(struct macb *bp)
1312 bp->macbgem_ops.mog_free_rx_buffers(bp);
1314 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
1315 bp->rx_ring, bp->rx_ring_dma);
1319 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
1320 bp->tx_ring, bp->tx_ring_dma);
1325 static int gem_alloc_rx_buffers(struct macb *bp)
1329 size = RX_RING_SIZE * sizeof(struct sk_buff *);
1330 bp->rx_skbuff = kzalloc(size, GFP_KERNEL);
1335 "Allocated %d RX struct sk_buff entries at %p\n",
1336 RX_RING_SIZE, bp->rx_skbuff);
1340 static int macb_alloc_rx_buffers(struct macb *bp)
1344 size = RX_RING_SIZE * bp->rx_buffer_size;
1345 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
1346 &bp->rx_buffers_dma, GFP_KERNEL);
1347 if (!bp->rx_buffers)
1351 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1352 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
1356 static int macb_alloc_consistent(struct macb *bp)
1360 size = TX_RING_SIZE * sizeof(struct macb_tx_skb);
1361 bp->tx_skb = kmalloc(size, GFP_KERNEL);
1365 size = RX_RING_BYTES;
1366 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1367 &bp->rx_ring_dma, GFP_KERNEL);
1371 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1372 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
1374 size = TX_RING_BYTES;
1375 bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1376 &bp->tx_ring_dma, GFP_KERNEL);
1380 "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
1381 size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
1383 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
1389 macb_free_consistent(bp);
1393 static void gem_init_rings(struct macb *bp)
1397 for (i = 0; i < TX_RING_SIZE; i++) {
1398 bp->tx_ring[i].addr = 0;
1399 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1401 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1403 bp->rx_tail = bp->rx_prepared_head = bp->tx_head = bp->tx_tail = 0;
1408 static void macb_init_rings(struct macb *bp)
1413 addr = bp->rx_buffers_dma;
1414 for (i = 0; i < RX_RING_SIZE; i++) {
1415 bp->rx_ring[i].addr = addr;
1416 bp->rx_ring[i].ctrl = 0;
1417 addr += bp->rx_buffer_size;
1419 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
1421 for (i = 0; i < TX_RING_SIZE; i++) {
1422 bp->tx_ring[i].addr = 0;
1423 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1425 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1427 bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
1430 static void macb_reset_hw(struct macb *bp)
1433 * Disable RX and TX (XXX: Should we halt the transmission
1436 macb_writel(bp, NCR, 0);
1438 /* Clear the stats registers (XXX: Update stats first?) */
1439 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
1441 /* Clear all status flags */
1442 macb_writel(bp, TSR, -1);
1443 macb_writel(bp, RSR, -1);
1445 /* Disable all interrupts */
1446 macb_writel(bp, IDR, -1);
1447 macb_readl(bp, ISR);
1450 static u32 gem_mdc_clk_div(struct macb *bp)
1453 unsigned long pclk_hz = clk_get_rate(bp->pclk);
1455 if (pclk_hz <= 20000000)
1456 config = GEM_BF(CLK, GEM_CLK_DIV8);
1457 else if (pclk_hz <= 40000000)
1458 config = GEM_BF(CLK, GEM_CLK_DIV16);
1459 else if (pclk_hz <= 80000000)
1460 config = GEM_BF(CLK, GEM_CLK_DIV32);
1461 else if (pclk_hz <= 120000000)
1462 config = GEM_BF(CLK, GEM_CLK_DIV48);
1463 else if (pclk_hz <= 160000000)
1464 config = GEM_BF(CLK, GEM_CLK_DIV64);
1466 config = GEM_BF(CLK, GEM_CLK_DIV96);
1471 static u32 macb_mdc_clk_div(struct macb *bp)
1474 unsigned long pclk_hz;
1476 if (macb_is_gem(bp))
1477 return gem_mdc_clk_div(bp);
1479 pclk_hz = clk_get_rate(bp->pclk);
1480 if (pclk_hz <= 20000000)
1481 config = MACB_BF(CLK, MACB_CLK_DIV8);
1482 else if (pclk_hz <= 40000000)
1483 config = MACB_BF(CLK, MACB_CLK_DIV16);
1484 else if (pclk_hz <= 80000000)
1485 config = MACB_BF(CLK, MACB_CLK_DIV32);
1487 config = MACB_BF(CLK, MACB_CLK_DIV64);
1493 * Get the DMA bus width field of the network configuration register that we
1494 * should program. We find the width from decoding the design configuration
1495 * register to find the maximum supported data bus width.
1497 static u32 macb_dbw(struct macb *bp)
1499 if (!macb_is_gem(bp))
1502 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
1504 return GEM_BF(DBW, GEM_DBW128);
1506 return GEM_BF(DBW, GEM_DBW64);
1509 return GEM_BF(DBW, GEM_DBW32);
1514 * Configure the receive DMA engine
1515 * - use the correct receive buffer size
1516 * - set best burst length for DMA operations
1517 * (if not supported by FIFO, it will fallback to default)
1518 * - set both rx/tx packet buffers to full memory size
1519 * These are configurable parameters for GEM.
1521 static void macb_configure_dma(struct macb *bp)
1525 if (macb_is_gem(bp)) {
1526 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
1527 dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
1528 if (bp->dma_burst_length)
1529 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
1530 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
1531 dmacfg &= ~GEM_BIT(ENDIA);
1532 if (bp->dev->features & NETIF_F_HW_CSUM)
1533 dmacfg |= GEM_BIT(TXCOEN);
1535 dmacfg &= ~GEM_BIT(TXCOEN);
1536 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
1538 gem_writel(bp, DMACFG, dmacfg);
1542 static void macb_init_hw(struct macb *bp)
1547 macb_set_hwaddr(bp);
1549 config = macb_mdc_clk_div(bp);
1550 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
1551 config |= MACB_BIT(PAE); /* PAuse Enable */
1552 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
1553 config |= MACB_BIT(BIG); /* Receive oversized frames */
1554 if (bp->dev->flags & IFF_PROMISC)
1555 config |= MACB_BIT(CAF); /* Copy All Frames */
1556 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
1557 config |= GEM_BIT(RXCOEN);
1558 if (!(bp->dev->flags & IFF_BROADCAST))
1559 config |= MACB_BIT(NBC); /* No BroadCast */
1560 config |= macb_dbw(bp);
1561 macb_writel(bp, NCFGR, config);
1562 bp->speed = SPEED_10;
1563 bp->duplex = DUPLEX_HALF;
1565 macb_configure_dma(bp);
1567 /* Initialize TX and RX buffers */
1568 macb_writel(bp, RBQP, bp->rx_ring_dma);
1569 macb_writel(bp, TBQP, bp->tx_ring_dma);
1571 /* Enable TX and RX */
1572 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
1574 /* Enable interrupts */
1575 macb_writel(bp, IER, (MACB_RX_INT_FLAGS
1577 | MACB_BIT(HRESP)));
1582 * The hash address register is 64 bits long and takes up two
1583 * locations in the memory map. The least significant bits are stored
1584 * in EMAC_HSL and the most significant bits in EMAC_HSH.
1586 * The unicast hash enable and the multicast hash enable bits in the
1587 * network configuration register enable the reception of hash matched
1588 * frames. The destination address is reduced to a 6 bit index into
1589 * the 64 bit hash register using the following hash function. The
1590 * hash function is an exclusive or of every sixth bit of the
1591 * destination address.
1593 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
1594 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
1595 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
1596 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
1597 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
1598 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
1600 * da[0] represents the least significant bit of the first byte
1601 * received, that is, the multicast/unicast indicator, and da[47]
1602 * represents the most significant bit of the last byte received. If
1603 * the hash index, hi[n], points to a bit that is set in the hash
1604 * register then the frame will be matched according to whether the
1605 * frame is multicast or unicast. A multicast match will be signalled
1606 * if the multicast hash enable bit is set, da[0] is 1 and the hash
1607 * index points to a bit set in the hash register. A unicast match
1608 * will be signalled if the unicast hash enable bit is set, da[0] is 0
1609 * and the hash index points to a bit set in the hash register. To
1610 * receive all multicast frames, the hash register should be set with
1611 * all ones and the multicast hash enable bit should be set in the
1612 * network configuration register.
1615 static inline int hash_bit_value(int bitnr, __u8 *addr)
1617 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
1623 * Return the hash index value for the specified address.
1625 static int hash_get_index(__u8 *addr)
1630 for (j = 0; j < 6; j++) {
1631 for (i = 0, bitval = 0; i < 8; i++)
1632 bitval ^= hash_bit_value(i*6 + j, addr);
1634 hash_index |= (bitval << j);
1641 * Add multicast addresses to the internal multicast-hash table.
1643 static void macb_sethashtable(struct net_device *dev)
1645 struct netdev_hw_addr *ha;
1646 unsigned long mc_filter[2];
1648 struct macb *bp = netdev_priv(dev);
1650 mc_filter[0] = mc_filter[1] = 0;
1652 netdev_for_each_mc_addr(ha, dev) {
1653 bitnr = hash_get_index(ha->addr);
1654 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
1657 macb_or_gem_writel(bp, HRB, mc_filter[0]);
1658 macb_or_gem_writel(bp, HRT, mc_filter[1]);
1662 * Enable/Disable promiscuous and multicast modes.
1664 void macb_set_rx_mode(struct net_device *dev)
1667 struct macb *bp = netdev_priv(dev);
1669 cfg = macb_readl(bp, NCFGR);
1671 if (dev->flags & IFF_PROMISC) {
1672 /* Enable promiscuous mode */
1673 cfg |= MACB_BIT(CAF);
1675 /* Disable RX checksum offload */
1676 if (macb_is_gem(bp))
1677 cfg &= ~GEM_BIT(RXCOEN);
1679 /* Disable promiscuous mode */
1680 cfg &= ~MACB_BIT(CAF);
1682 /* Enable RX checksum offload only if requested */
1683 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
1684 cfg |= GEM_BIT(RXCOEN);
1687 if (dev->flags & IFF_ALLMULTI) {
1688 /* Enable all multicast mode */
1689 macb_or_gem_writel(bp, HRB, -1);
1690 macb_or_gem_writel(bp, HRT, -1);
1691 cfg |= MACB_BIT(NCFGR_MTI);
1692 } else if (!netdev_mc_empty(dev)) {
1693 /* Enable specific multicasts */
1694 macb_sethashtable(dev);
1695 cfg |= MACB_BIT(NCFGR_MTI);
1696 } else if (dev->flags & (~IFF_ALLMULTI)) {
1697 /* Disable all multicast mode */
1698 macb_or_gem_writel(bp, HRB, 0);
1699 macb_or_gem_writel(bp, HRT, 0);
1700 cfg &= ~MACB_BIT(NCFGR_MTI);
1703 macb_writel(bp, NCFGR, cfg);
1705 EXPORT_SYMBOL_GPL(macb_set_rx_mode);
1707 static int macb_open(struct net_device *dev)
1709 struct macb *bp = netdev_priv(dev);
1710 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
1713 netdev_dbg(bp->dev, "open\n");
1715 /* carrier starts down */
1716 netif_carrier_off(dev);
1718 /* if the phy is not yet register, retry later*/
1722 /* RX buffers initialization */
1723 macb_init_rx_buffer_size(bp, bufsz);
1725 err = macb_alloc_consistent(bp);
1727 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
1732 napi_enable(&bp->napi);
1734 bp->macbgem_ops.mog_init_rings(bp);
1737 /* schedule a link state check */
1738 phy_start(bp->phy_dev);
1740 netif_start_queue(dev);
1745 static int macb_close(struct net_device *dev)
1747 struct macb *bp = netdev_priv(dev);
1748 unsigned long flags;
1750 netif_stop_queue(dev);
1751 napi_disable(&bp->napi);
1754 phy_stop(bp->phy_dev);
1756 spin_lock_irqsave(&bp->lock, flags);
1758 netif_carrier_off(dev);
1759 spin_unlock_irqrestore(&bp->lock, flags);
1761 macb_free_consistent(bp);
1766 static void gem_update_stats(struct macb *bp)
1768 u32 __iomem *reg = bp->regs + GEM_OTX;
1769 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
1770 u32 *end = &bp->hw_stats.gem.rx_udp_checksum_errors + 1;
1772 for (; p < end; p++, reg++)
1773 *p += __raw_readl(reg);
1776 static struct net_device_stats *gem_get_stats(struct macb *bp)
1778 struct gem_stats *hwstat = &bp->hw_stats.gem;
1779 struct net_device_stats *nstat = &bp->stats;
1781 gem_update_stats(bp);
1783 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
1784 hwstat->rx_alignment_errors +
1785 hwstat->rx_resource_errors +
1786 hwstat->rx_overruns +
1787 hwstat->rx_oversize_frames +
1788 hwstat->rx_jabbers +
1789 hwstat->rx_undersized_frames +
1790 hwstat->rx_length_field_frame_errors);
1791 nstat->tx_errors = (hwstat->tx_late_collisions +
1792 hwstat->tx_excessive_collisions +
1793 hwstat->tx_underrun +
1794 hwstat->tx_carrier_sense_errors);
1795 nstat->multicast = hwstat->rx_multicast_frames;
1796 nstat->collisions = (hwstat->tx_single_collision_frames +
1797 hwstat->tx_multiple_collision_frames +
1798 hwstat->tx_excessive_collisions);
1799 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
1800 hwstat->rx_jabbers +
1801 hwstat->rx_undersized_frames +
1802 hwstat->rx_length_field_frame_errors);
1803 nstat->rx_over_errors = hwstat->rx_resource_errors;
1804 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
1805 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
1806 nstat->rx_fifo_errors = hwstat->rx_overruns;
1807 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
1808 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
1809 nstat->tx_fifo_errors = hwstat->tx_underrun;
1814 struct net_device_stats *macb_get_stats(struct net_device *dev)
1816 struct macb *bp = netdev_priv(dev);
1817 struct net_device_stats *nstat = &bp->stats;
1818 struct macb_stats *hwstat = &bp->hw_stats.macb;
1820 if (macb_is_gem(bp))
1821 return gem_get_stats(bp);
1823 /* read stats from hardware */
1824 macb_update_stats(bp);
1826 /* Convert HW stats into netdevice stats */
1827 nstat->rx_errors = (hwstat->rx_fcs_errors +
1828 hwstat->rx_align_errors +
1829 hwstat->rx_resource_errors +
1830 hwstat->rx_overruns +
1831 hwstat->rx_oversize_pkts +
1832 hwstat->rx_jabbers +
1833 hwstat->rx_undersize_pkts +
1834 hwstat->sqe_test_errors +
1835 hwstat->rx_length_mismatch);
1836 nstat->tx_errors = (hwstat->tx_late_cols +
1837 hwstat->tx_excessive_cols +
1838 hwstat->tx_underruns +
1839 hwstat->tx_carrier_errors);
1840 nstat->collisions = (hwstat->tx_single_cols +
1841 hwstat->tx_multiple_cols +
1842 hwstat->tx_excessive_cols);
1843 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1844 hwstat->rx_jabbers +
1845 hwstat->rx_undersize_pkts +
1846 hwstat->rx_length_mismatch);
1847 nstat->rx_over_errors = hwstat->rx_resource_errors +
1848 hwstat->rx_overruns;
1849 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
1850 nstat->rx_frame_errors = hwstat->rx_align_errors;
1851 nstat->rx_fifo_errors = hwstat->rx_overruns;
1852 /* XXX: What does "missed" mean? */
1853 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
1854 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
1855 nstat->tx_fifo_errors = hwstat->tx_underruns;
1856 /* Don't know about heartbeat or window errors... */
1860 EXPORT_SYMBOL_GPL(macb_get_stats);
1862 static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1864 struct macb *bp = netdev_priv(dev);
1865 struct phy_device *phydev = bp->phy_dev;
1870 return phy_ethtool_gset(phydev, cmd);
1873 static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1875 struct macb *bp = netdev_priv(dev);
1876 struct phy_device *phydev = bp->phy_dev;
1881 return phy_ethtool_sset(phydev, cmd);
1884 static int macb_get_regs_len(struct net_device *netdev)
1886 return MACB_GREGS_NBR * sizeof(u32);
1889 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1892 struct macb *bp = netdev_priv(dev);
1893 unsigned int tail, head;
1896 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
1897 | MACB_GREGS_VERSION;
1899 tail = macb_tx_ring_wrap(bp->tx_tail);
1900 head = macb_tx_ring_wrap(bp->tx_head);
1902 regs_buff[0] = macb_readl(bp, NCR);
1903 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
1904 regs_buff[2] = macb_readl(bp, NSR);
1905 regs_buff[3] = macb_readl(bp, TSR);
1906 regs_buff[4] = macb_readl(bp, RBQP);
1907 regs_buff[5] = macb_readl(bp, TBQP);
1908 regs_buff[6] = macb_readl(bp, RSR);
1909 regs_buff[7] = macb_readl(bp, IMR);
1911 regs_buff[8] = tail;
1912 regs_buff[9] = head;
1913 regs_buff[10] = macb_tx_dma(bp, tail);
1914 regs_buff[11] = macb_tx_dma(bp, head);
1916 if (macb_is_gem(bp)) {
1917 regs_buff[12] = gem_readl(bp, USRIO);
1918 regs_buff[13] = gem_readl(bp, DMACFG);
1922 const struct ethtool_ops macb_ethtool_ops = {
1923 .get_settings = macb_get_settings,
1924 .set_settings = macb_set_settings,
1925 .get_regs_len = macb_get_regs_len,
1926 .get_regs = macb_get_regs,
1927 .get_link = ethtool_op_get_link,
1928 .get_ts_info = ethtool_op_get_ts_info,
1930 EXPORT_SYMBOL_GPL(macb_ethtool_ops);
1932 int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1934 struct macb *bp = netdev_priv(dev);
1935 struct phy_device *phydev = bp->phy_dev;
1937 if (!netif_running(dev))
1943 return phy_mii_ioctl(phydev, rq, cmd);
1945 EXPORT_SYMBOL_GPL(macb_ioctl);
1947 static int macb_set_features(struct net_device *netdev,
1948 netdev_features_t features)
1950 struct macb *bp = netdev_priv(netdev);
1951 netdev_features_t changed = features ^ netdev->features;
1953 /* TX checksum offload */
1954 if ((changed & NETIF_F_HW_CSUM) && macb_is_gem(bp)) {
1957 dmacfg = gem_readl(bp, DMACFG);
1958 if (features & NETIF_F_HW_CSUM)
1959 dmacfg |= GEM_BIT(TXCOEN);
1961 dmacfg &= ~GEM_BIT(TXCOEN);
1962 gem_writel(bp, DMACFG, dmacfg);
1965 /* RX checksum offload */
1966 if ((changed & NETIF_F_RXCSUM) && macb_is_gem(bp)) {
1969 netcfg = gem_readl(bp, NCFGR);
1970 if (features & NETIF_F_RXCSUM &&
1971 !(netdev->flags & IFF_PROMISC))
1972 netcfg |= GEM_BIT(RXCOEN);
1974 netcfg &= ~GEM_BIT(RXCOEN);
1975 gem_writel(bp, NCFGR, netcfg);
1981 static const struct net_device_ops macb_netdev_ops = {
1982 .ndo_open = macb_open,
1983 .ndo_stop = macb_close,
1984 .ndo_start_xmit = macb_start_xmit,
1985 .ndo_set_rx_mode = macb_set_rx_mode,
1986 .ndo_get_stats = macb_get_stats,
1987 .ndo_do_ioctl = macb_ioctl,
1988 .ndo_validate_addr = eth_validate_addr,
1989 .ndo_change_mtu = eth_change_mtu,
1990 .ndo_set_mac_address = eth_mac_addr,
1991 #ifdef CONFIG_NET_POLL_CONTROLLER
1992 .ndo_poll_controller = macb_poll_controller,
1994 .ndo_set_features = macb_set_features,
1997 #if defined(CONFIG_OF)
1998 static struct macb_config pc302gem_config = {
1999 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
2000 .dma_burst_length = 16,
2003 static struct macb_config sama5d3_config = {
2004 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
2005 .dma_burst_length = 16,
2008 static struct macb_config sama5d4_config = {
2010 .dma_burst_length = 4,
2013 static const struct of_device_id macb_dt_ids[] = {
2014 { .compatible = "cdns,at32ap7000-macb" },
2015 { .compatible = "cdns,at91sam9260-macb" },
2016 { .compatible = "cdns,macb" },
2017 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
2018 { .compatible = "cdns,gem", .data = &pc302gem_config },
2019 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
2020 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
2023 MODULE_DEVICE_TABLE(of, macb_dt_ids);
2027 * Configure peripheral capacities according to device tree
2028 * and integration options used
2030 static void macb_configure_caps(struct macb *bp)
2033 const struct of_device_id *match;
2034 const struct macb_config *config;
2036 if (bp->pdev->dev.of_node) {
2037 match = of_match_node(macb_dt_ids, bp->pdev->dev.of_node);
2038 if (match && match->data) {
2039 config = (const struct macb_config *)match->data;
2041 bp->caps = config->caps;
2043 * As we have access to the matching node, configure
2044 * DMA burst length as well
2046 bp->dma_burst_length = config->dma_burst_length;
2050 if (MACB_BFEXT(IDNUM, macb_readl(bp, MID)) == 0x2)
2051 bp->caps |= MACB_CAPS_MACB_IS_GEM;
2053 if (macb_is_gem(bp)) {
2054 dcfg = gem_readl(bp, DCFG1);
2055 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
2056 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
2057 dcfg = gem_readl(bp, DCFG2);
2058 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
2059 bp->caps |= MACB_CAPS_FIFO_MODE;
2062 netdev_dbg(bp->dev, "Cadence caps 0x%08x\n", bp->caps);
2065 static int __init macb_probe(struct platform_device *pdev)
2067 struct macb_platform_data *pdata;
2068 struct resource *regs;
2069 struct net_device *dev;
2071 struct phy_device *phydev;
2074 struct pinctrl *pinctrl;
2077 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2079 dev_err(&pdev->dev, "no mmio resource defined\n");
2083 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
2084 if (IS_ERR(pinctrl)) {
2085 err = PTR_ERR(pinctrl);
2086 if (err == -EPROBE_DEFER)
2089 dev_warn(&pdev->dev, "No pinctrl provided\n");
2093 dev = alloc_etherdev(sizeof(*bp));
2097 SET_NETDEV_DEV(dev, &pdev->dev);
2099 bp = netdev_priv(dev);
2103 spin_lock_init(&bp->lock);
2104 INIT_WORK(&bp->tx_error_task, macb_tx_error_task);
2106 bp->pclk = devm_clk_get(&pdev->dev, "pclk");
2107 if (IS_ERR(bp->pclk)) {
2108 err = PTR_ERR(bp->pclk);
2109 dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err);
2110 goto err_out_free_dev;
2113 bp->hclk = devm_clk_get(&pdev->dev, "hclk");
2114 if (IS_ERR(bp->hclk)) {
2115 err = PTR_ERR(bp->hclk);
2116 dev_err(&pdev->dev, "failed to get hclk (%u)\n", err);
2117 goto err_out_free_dev;
2120 bp->tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
2122 err = clk_prepare_enable(bp->pclk);
2124 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
2125 goto err_out_free_dev;
2128 err = clk_prepare_enable(bp->hclk);
2130 dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err);
2131 goto err_out_disable_pclk;
2134 if (!IS_ERR(bp->tx_clk)) {
2135 err = clk_prepare_enable(bp->tx_clk);
2137 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n",
2139 goto err_out_disable_hclk;
2143 bp->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
2145 dev_err(&pdev->dev, "failed to map registers, aborting.\n");
2147 goto err_out_disable_clocks;
2150 dev->irq = platform_get_irq(pdev, 0);
2151 err = devm_request_irq(&pdev->dev, dev->irq, macb_interrupt, 0,
2154 dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n",
2156 goto err_out_disable_clocks;
2159 dev->netdev_ops = &macb_netdev_ops;
2160 netif_napi_add(dev, &bp->napi, macb_poll, 64);
2161 dev->ethtool_ops = &macb_ethtool_ops;
2163 dev->base_addr = regs->start;
2165 /* setup capacities */
2166 macb_configure_caps(bp);
2168 /* setup appropriated routines according to adapter type */
2169 if (macb_is_gem(bp)) {
2170 bp->max_tx_length = GEM_MAX_TX_LEN;
2171 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
2172 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
2173 bp->macbgem_ops.mog_init_rings = gem_init_rings;
2174 bp->macbgem_ops.mog_rx = gem_rx;
2176 bp->max_tx_length = MACB_MAX_TX_LEN;
2177 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
2178 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
2179 bp->macbgem_ops.mog_init_rings = macb_init_rings;
2180 bp->macbgem_ops.mog_rx = macb_rx;
2184 dev->hw_features = NETIF_F_SG;
2185 /* Checksum offload is only available on gem with packet buffer */
2186 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
2187 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
2188 if (bp->caps & MACB_CAPS_SG_DISABLED)
2189 dev->hw_features &= ~NETIF_F_SG;
2190 dev->features = dev->hw_features;
2192 /* Set MII management clock divider */
2193 config = macb_mdc_clk_div(bp);
2194 config |= macb_dbw(bp);
2195 macb_writel(bp, NCFGR, config);
2197 mac = of_get_mac_address(pdev->dev.of_node);
2199 memcpy(bp->dev->dev_addr, mac, ETH_ALEN);
2201 macb_get_hwaddr(bp);
2203 err = of_get_phy_mode(pdev->dev.of_node);
2205 pdata = dev_get_platdata(&pdev->dev);
2206 if (pdata && pdata->is_rmii)
2207 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
2209 bp->phy_interface = PHY_INTERFACE_MODE_MII;
2211 bp->phy_interface = err;
2214 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
2215 macb_or_gem_writel(bp, USRIO, GEM_BIT(RGMII));
2216 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
2217 #if defined(CONFIG_ARCH_AT91)
2218 macb_or_gem_writel(bp, USRIO, (MACB_BIT(RMII) |
2221 macb_or_gem_writel(bp, USRIO, 0);
2224 #if defined(CONFIG_ARCH_AT91)
2225 macb_or_gem_writel(bp, USRIO, MACB_BIT(CLKEN));
2227 macb_or_gem_writel(bp, USRIO, MACB_BIT(MII));
2230 err = register_netdev(dev);
2232 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
2233 goto err_out_disable_clocks;
2236 err = macb_mii_init(bp);
2238 goto err_out_unregister_netdev;
2240 platform_set_drvdata(pdev, dev);
2242 netif_carrier_off(dev);
2244 netdev_info(dev, "Cadence %s at 0x%08lx irq %d (%pM)\n",
2245 macb_is_gem(bp) ? "GEM" : "MACB", dev->base_addr,
2246 dev->irq, dev->dev_addr);
2248 phydev = bp->phy_dev;
2249 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
2250 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
2254 err_out_unregister_netdev:
2255 unregister_netdev(dev);
2256 err_out_disable_clocks:
2257 if (!IS_ERR(bp->tx_clk))
2258 clk_disable_unprepare(bp->tx_clk);
2259 err_out_disable_hclk:
2260 clk_disable_unprepare(bp->hclk);
2261 err_out_disable_pclk:
2262 clk_disable_unprepare(bp->pclk);
2269 static int __exit macb_remove(struct platform_device *pdev)
2271 struct net_device *dev;
2274 dev = platform_get_drvdata(pdev);
2277 bp = netdev_priv(dev);
2279 phy_disconnect(bp->phy_dev);
2280 mdiobus_unregister(bp->mii_bus);
2281 kfree(bp->mii_bus->irq);
2282 mdiobus_free(bp->mii_bus);
2283 unregister_netdev(dev);
2284 if (!IS_ERR(bp->tx_clk))
2285 clk_disable_unprepare(bp->tx_clk);
2286 clk_disable_unprepare(bp->hclk);
2287 clk_disable_unprepare(bp->pclk);
2295 static int macb_suspend(struct device *dev)
2297 struct platform_device *pdev = to_platform_device(dev);
2298 struct net_device *netdev = platform_get_drvdata(pdev);
2299 struct macb *bp = netdev_priv(netdev);
2301 netif_carrier_off(netdev);
2302 netif_device_detach(netdev);
2304 if (!IS_ERR(bp->tx_clk))
2305 clk_disable_unprepare(bp->tx_clk);
2306 clk_disable_unprepare(bp->hclk);
2307 clk_disable_unprepare(bp->pclk);
2312 static int macb_resume(struct device *dev)
2314 struct platform_device *pdev = to_platform_device(dev);
2315 struct net_device *netdev = platform_get_drvdata(pdev);
2316 struct macb *bp = netdev_priv(netdev);
2318 clk_prepare_enable(bp->pclk);
2319 clk_prepare_enable(bp->hclk);
2320 if (!IS_ERR(bp->tx_clk))
2321 clk_prepare_enable(bp->tx_clk);
2323 netif_device_attach(netdev);
2329 static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
2331 static struct platform_driver macb_driver = {
2332 .remove = __exit_p(macb_remove),
2335 .owner = THIS_MODULE,
2336 .of_match_table = of_match_ptr(macb_dt_ids),
2341 module_platform_driver_probe(macb_driver, macb_probe);
2343 MODULE_LICENSE("GPL");
2344 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
2345 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2346 MODULE_ALIAS("platform:macb");