drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.c

   1 /*
   2  * cxgb4_uld.c:Chelsio Upper Layer Driver Interface for T4/T5/T6 SGE management
   3  *
   4  * Copyright (c) 2016 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  *
  34  *  Written by: Atul Gupta (atul.gupta@chelsio.com)
  35  *  Written by: Hariprasad Shenai (hariprasad@chelsio.com)
  36  */
  37
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/errno.h>
  41 #include <linux/types.h>
  42 #include <linux/debugfs.h>
  43 #include <linux/export.h>
  44 #include <linux/list.h>
  45 #include <linux/skbuff.h>
  46 #include <linux/pci.h>
  47
  48 #include "cxgb4.h"
  49 #include "cxgb4_uld.h"
  50 #include "t4_regs.h"
  51 #include "t4fw_api.h"
  52 #include "t4_msg.h"
  53
  54 #define for_each_uldrxq(m, i) for (i = 0; i < ((m)->nrxq + (m)->nciq); i++)
  55
  56 static int get_msix_idx_from_bmap(struct adapter *adap)
  57 {
  58         struct uld_msix_bmap *bmap = &adap->msix_bmap_ulds;
  59         unsigned long flags;
  60         unsigned int msix_idx;
  61
  62         spin_lock_irqsave(&bmap->lock, flags);
  63         msix_idx = find_first_zero_bit(bmap->msix_bmap, bmap->mapsize);
  64         if (msix_idx < bmap->mapsize) {
  65                 __set_bit(msix_idx, bmap->msix_bmap);
  66         } else {
  67                 spin_unlock_irqrestore(&bmap->lock, flags);
  68                 return -ENOSPC;
  69         }
  70
  71         spin_unlock_irqrestore(&bmap->lock, flags);
  72         return msix_idx;
  73 }
  74
  75 static void free_msix_idx_in_bmap(struct adapter *adap, unsigned int msix_idx)
  76 {
  77         struct uld_msix_bmap *bmap = &adap->msix_bmap_ulds;
  78         unsigned long flags;
  79
  80         spin_lock_irqsave(&bmap->lock, flags);
  81          __clear_bit(msix_idx, bmap->msix_bmap);
  82         spin_unlock_irqrestore(&bmap->lock, flags);
  83 }
  84
  85 /* Flush the aggregated lro sessions */
  86 static void uldrx_flush_handler(struct sge_rspq *q)
  87 {
  88         struct adapter *adap = q->adap;
  89
  90         if (adap->uld[q->uld].lro_flush)
  91                 adap->uld[q->uld].lro_flush(&q->lro_mgr);
  92 }
  93
  94 /**
  95  *      uldrx_handler - response queue handler for ULD queues
  96  *      @q: the response queue that received the packet
  97  *      @rsp: the response queue descriptor holding the offload message
  98  *      @gl: the gather list of packet fragments
  99  *
 100  *      Deliver an ingress offload packet to a ULD.  All processing is done by
 101  *      the ULD, we just maintain statistics.
 102  */
 103 static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp,
 104                          const struct pkt_gl *gl)
 105 {
 106         struct adapter *adap = q->adap;
 107         struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq);
 108         int ret;
 109
 110         /* FW can send CPLs encapsulated in a CPL_FW4_MSG */
 111         if (((const struct rss_header *)rsp)->opcode == CPL_FW4_MSG &&
 112             ((const struct cpl_fw4_msg *)(rsp + 1))->type == FW_TYPE_RSSCPL)
 113                 rsp += 2;
 114
 115         if (q->flush_handler)
 116                 ret = adap->uld[q->uld].lro_rx_handler(adap->uld[q->uld].handle,
 117                                 rsp, gl, &q->lro_mgr,
 118                                 &q->napi);
 119         else
 120                 ret = adap->uld[q->uld].rx_handler(adap->uld[q->uld].handle,
 121                                 rsp, gl);
 122
 123         if (ret) {
 124                 rxq->stats.nomem++;
 125                 return -1;
 126         }
 127
 128         if (!gl)
 129                 rxq->stats.imm++;
 130         else if (gl == CXGB4_MSG_AN)
 131                 rxq->stats.an++;
 132         else
 133                 rxq->stats.pkts++;
 134         return 0;
 135 }
 136
 137 static int alloc_uld_rxqs(struct adapter *adap,
 138                           struct sge_uld_rxq_info *rxq_info, bool lro)
 139 {
 140         struct sge *s = &adap->sge;
 141         unsigned int nq = rxq_info->nrxq + rxq_info->nciq;
 142         struct sge_ofld_rxq *q = rxq_info->uldrxq;
 143         unsigned short *ids = rxq_info->rspq_id;
 144         unsigned int bmap_idx = 0;
 145         unsigned int per_chan;
 146         int i, err, msi_idx, que_idx = 0;
 147
 148         per_chan = rxq_info->nrxq / adap->params.nports;
 149
 150         if (adap->flags & USING_MSIX)
 151                 msi_idx = 1;
 152         else
 153                 msi_idx = -((int)s->intrq.abs_id + 1);
 154
 155         for (i = 0; i < nq; i++, q++) {
 156                 if (i == rxq_info->nrxq) {
 157                         /* start allocation of concentrator queues */
 158                         per_chan = rxq_info->nciq / adap->params.nports;
 159                         que_idx = 0;
 160                 }
 161
 162                 if (msi_idx >= 0) {
 163                         bmap_idx = get_msix_idx_from_bmap(adap);
 164                         msi_idx = adap->msix_info_ulds[bmap_idx].idx;
 165                 }
 166                 err = t4_sge_alloc_rxq(adap, &q->rspq, false,
 167                                        adap->port[que_idx++ / per_chan],
 168                                        msi_idx,
 169                                        q->fl.size ? &q->fl : NULL,
 170                                        uldrx_handler,
 171                                        lro ? uldrx_flush_handler : NULL,
 172                                        0);
 173                 if (err)
 174                         goto freeout;
 175                 if (msi_idx >= 0)
 176                         rxq_info->msix_tbl[i] = bmap_idx;
 177                 memset(&q->stats, 0, sizeof(q->stats));
 178                 if (ids)
 179                         ids[i] = q->rspq.abs_id;
 180         }
 181         return 0;
 182 freeout:
 183         q = rxq_info->uldrxq;
 184         for ( ; i; i--, q++) {
 185                 if (q->rspq.desc)
 186                         free_rspq_fl(adap, &q->rspq,
 187                                      q->fl.size ? &q->fl : NULL);
 188         }
 189         return err;
 190 }
 191
 192 static int
 193 setup_sge_queues_uld(struct adapter *adap, unsigned int uld_type, bool lro)
 194 {
 195         struct sge_uld_rxq_info *rxq_info = adap->sge.uld_rxq_info[uld_type];
 196         int i, ret = 0;
 197
 198         if (adap->flags & USING_MSIX) {
 199                 rxq_info->msix_tbl = kcalloc((rxq_info->nrxq + rxq_info->nciq),
 200                                              sizeof(unsigned short),
 201                                              GFP_KERNEL);
 202                 if (!rxq_info->msix_tbl)
 203                         return -ENOMEM;
 204         }
 205
 206         ret = !(!alloc_uld_rxqs(adap, rxq_info, lro));
 207
 208         /* Tell uP to route control queue completions to rdma rspq */
 209         if (adap->flags & FULL_INIT_DONE &&
 210             !ret && uld_type == CXGB4_ULD_RDMA) {
 211                 struct sge *s = &adap->sge;
 212                 unsigned int cmplqid;
 213                 u32 param, cmdop;
 214
 215                 cmdop = FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL;
 216                 for_each_port(adap, i) {
 217                         cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id;
 218                         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
 219                                  FW_PARAMS_PARAM_X_V(cmdop) |
 220                                  FW_PARAMS_PARAM_YZ_V(s->ctrlq[i].q.cntxt_id));
 221                         ret = t4_set_params(adap, adap->mbox, adap->pf,
 222                                             0, 1, &param, &cmplqid);
 223                 }
 224         }
 225         return ret;
 226 }
 227
 228 static void t4_free_uld_rxqs(struct adapter *adap, int n,
 229                              struct sge_ofld_rxq *q)
 230 {
 231         for ( ; n; n--, q++) {
 232                 if (q->rspq.desc)
 233                         free_rspq_fl(adap, &q->rspq,
 234                                      q->fl.size ? &q->fl : NULL);
 235         }
 236 }
 237
 238 static void free_sge_queues_uld(struct adapter *adap, unsigned int uld_type)
 239 {
 240         struct sge_uld_rxq_info *rxq_info = adap->sge.uld_rxq_info[uld_type];
 241
 242         if (adap->flags & FULL_INIT_DONE && uld_type == CXGB4_ULD_RDMA) {
 243                 struct sge *s = &adap->sge;
 244                 u32 param, cmdop, cmplqid = 0;
 245                 int i;
 246
 247                 cmdop = FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL;
 248                 for_each_port(adap, i) {
 249                         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
 250                                  FW_PARAMS_PARAM_X_V(cmdop) |
 251                                  FW_PARAMS_PARAM_YZ_V(s->ctrlq[i].q.cntxt_id));
 252                         t4_set_params(adap, adap->mbox, adap->pf,
 253                                       0, 1, &param, &cmplqid);
 254                 }
 255         }
 256
 257         if (rxq_info->nciq)
 258                 t4_free_uld_rxqs(adap, rxq_info->nciq,
 259                                  rxq_info->uldrxq + rxq_info->nrxq);
 260         t4_free_uld_rxqs(adap, rxq_info->nrxq, rxq_info->uldrxq);
 261         if (adap->flags & USING_MSIX)
 262                 kfree(rxq_info->msix_tbl);
 263 }
 264
 265 static int cfg_queues_uld(struct adapter *adap, unsigned int uld_type,
 266                           const struct cxgb4_uld_info *uld_info)
 267 {
 268         struct sge *s = &adap->sge;
 269         struct sge_uld_rxq_info *rxq_info;
 270         int i, nrxq, ciq_size;
 271
 272         rxq_info = kzalloc(sizeof(*rxq_info), GFP_KERNEL);
 273         if (!rxq_info)
 274                 return -ENOMEM;
 275
 276         if (adap->flags & USING_MSIX && uld_info->nrxq > s->nqs_per_uld) {
 277                 i = s->nqs_per_uld;
 278                 rxq_info->nrxq = roundup(i, adap->params.nports);
 279         } else {
 280                 i = min_t(int, uld_info->nrxq,
 281                           num_online_cpus());
 282                 rxq_info->nrxq = roundup(i, adap->params.nports);
 283         }
 284         if (!uld_info->ciq) {
 285                 rxq_info->nciq = 0;
 286         } else  {
 287                 if (adap->flags & USING_MSIX)
 288                         rxq_info->nciq = min_t(int, s->nqs_per_uld,
 289                                                num_online_cpus());
 290                 else
 291                         rxq_info->nciq = min_t(int, MAX_OFLD_QSETS,
 292                                                num_online_cpus());
 293                 rxq_info->nciq = ((rxq_info->nciq / adap->params.nports) *
 294                                   adap->params.nports);
 295                 rxq_info->nciq = max_t(int, rxq_info->nciq,
 296                                        adap->params.nports);
 297         }
 298
 299         nrxq = rxq_info->nrxq + rxq_info->nciq; /* total rxq's */
 300         rxq_info->uldrxq = kcalloc(nrxq, sizeof(struct sge_ofld_rxq),
 301                                    GFP_KERNEL);
 302         if (!rxq_info->uldrxq) {
 303                 kfree(rxq_info);
 304                 return -ENOMEM;
 305         }
 306
 307         rxq_info->rspq_id = kcalloc(nrxq, sizeof(unsigned short), GFP_KERNEL);
 308         if (!rxq_info->rspq_id) {
 309                 kfree(rxq_info->uldrxq);
 310                 kfree(rxq_info);
 311                 return -ENOMEM;
 312         }
 313
 314         for (i = 0; i < rxq_info->nrxq; i++) {
 315                 struct sge_ofld_rxq *r = &rxq_info->uldrxq[i];
 316
 317                 init_rspq(adap, &r->rspq, 5, 1, uld_info->rxq_size, 64);
 318                 r->rspq.uld = uld_type;
 319                 r->fl.size = 72;
 320         }
 321
 322         ciq_size = 64 + adap->vres.cq.size + adap->tids.nftids;
 323         if (ciq_size > SGE_MAX_IQ_SIZE) {
 324                 dev_warn(adap->pdev_dev, "CIQ size too small for available IQs\n");
 325                 ciq_size = SGE_MAX_IQ_SIZE;
 326         }
 327
 328         for (i = rxq_info->nrxq; i < nrxq; i++) {
 329                 struct sge_ofld_rxq *r = &rxq_info->uldrxq[i];
 330
 331                 init_rspq(adap, &r->rspq, 5, 1, ciq_size, 64);
 332                 r->rspq.uld = uld_type;
 333         }
 334
 335         memcpy(rxq_info->name, uld_info->name, IFNAMSIZ);
 336         adap->sge.uld_rxq_info[uld_type] = rxq_info;
 337
 338         return 0;
 339 }
 340
 341 static void free_queues_uld(struct adapter *adap, unsigned int uld_type)
 342 {
 343         struct sge_uld_rxq_info *rxq_info = adap->sge.uld_rxq_info[uld_type];
 344
 345         kfree(rxq_info->rspq_id);
 346         kfree(rxq_info->uldrxq);
 347         kfree(rxq_info);
 348 }
 349
 350 static int
 351 request_msix_queue_irqs_uld(struct adapter *adap, unsigned int uld_type)
 352 {
 353         struct sge_uld_rxq_info *rxq_info = adap->sge.uld_rxq_info[uld_type];
 354         int err = 0;
 355         unsigned int idx, bmap_idx;
 356
 357         for_each_uldrxq(rxq_info, idx) {
 358                 bmap_idx = rxq_info->msix_tbl[idx];
 359                 err = request_irq(adap->msix_info_ulds[bmap_idx].vec,
 360                                   t4_sge_intr_msix, 0,
 361                                   adap->msix_info_ulds[bmap_idx].desc,
 362                                   &rxq_info->uldrxq[idx].rspq);
 363                 if (err)
 364                         goto unwind;
 365         }
 366         return 0;
 367 unwind:
 368         while (idx-- > 0) {
 369                 bmap_idx = rxq_info->msix_tbl[idx];
 370                 free_msix_idx_in_bmap(adap, bmap_idx);
 371                 free_irq(adap->msix_info_ulds[bmap_idx].vec,
 372                          &rxq_info->uldrxq[idx].rspq);
 373         }
 374         return err;
 375 }
 376
 377 static void
 378 free_msix_queue_irqs_uld(struct adapter *adap, unsigned int uld_type)
 379 {
 380         struct sge_uld_rxq_info *rxq_info = adap->sge.uld_rxq_info[uld_type];
 381         unsigned int idx, bmap_idx;
 382
 383         for_each_uldrxq(rxq_info, idx) {
 384                 bmap_idx = rxq_info->msix_tbl[idx];
 385
 386                 free_msix_idx_in_bmap(adap, bmap_idx);
 387                 free_irq(adap->msix_info_ulds[bmap_idx].vec,
 388                          &rxq_info->uldrxq[idx].rspq);
 389         }
 390 }
 391
 392 static void name_msix_vecs_uld(struct adapter *adap, unsigned int uld_type)
 393 {
 394         struct sge_uld_rxq_info *rxq_info = adap->sge.uld_rxq_info[uld_type];
 395         int n = sizeof(adap->msix_info_ulds[0].desc);
 396         unsigned int idx, bmap_idx;
 397
 398         for_each_uldrxq(rxq_info, idx) {
 399                 bmap_idx = rxq_info->msix_tbl[idx];
 400
 401                 snprintf(adap->msix_info_ulds[bmap_idx].desc, n, "%s-%s%d",
 402                          adap->port[0]->name, rxq_info->name, idx);
 403         }
 404 }
 405
 406 static void enable_rx(struct adapter *adap, struct sge_rspq *q)
 407 {
 408         if (!q)
 409                 return;
 410
 411         if (q->handler) {
 412                 cxgb_busy_poll_init_lock(q);
 413                 napi_enable(&q->napi);
 414         }
 415         /* 0-increment GTS to start the timer and enable interrupts */
 416         t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
 417                      SEINTARM_V(q->intr_params) |
 418                      INGRESSQID_V(q->cntxt_id));
 419 }
 420
 421 static void quiesce_rx(struct adapter *adap, struct sge_rspq *q)
 422 {
 423         if (q && q->handler) {
 424                 napi_disable(&q->napi);
 425                 local_bh_disable();
 426                 while (!cxgb_poll_lock_napi(q))
 427                         mdelay(1);
 428                 local_bh_enable();
 429         }
 430 }
 431
 432 static void enable_rx_uld(struct adapter *adap, unsigned int uld_type)
 433 {
 434         struct sge_uld_rxq_info *rxq_info = adap->sge.uld_rxq_info[uld_type];
 435         int idx;
 436
 437         for_each_uldrxq(rxq_info, idx)
 438                 enable_rx(adap, &rxq_info->uldrxq[idx].rspq);
 439 }
 440
 441 static void quiesce_rx_uld(struct adapter *adap, unsigned int uld_type)
 442 {
 443         struct sge_uld_rxq_info *rxq_info = adap->sge.uld_rxq_info[uld_type];
 444         int idx;
 445
 446         for_each_uldrxq(rxq_info, idx)
 447                 quiesce_rx(adap, &rxq_info->uldrxq[idx].rspq);
 448 }
 449
 450 static void uld_queue_init(struct adapter *adap, unsigned int uld_type,
 451                            struct cxgb4_lld_info *lli)
 452 {
 453         struct sge_uld_rxq_info *rxq_info = adap->sge.uld_rxq_info[uld_type];
 454
 455         lli->rxq_ids = rxq_info->rspq_id;
 456         lli->nrxq = rxq_info->nrxq;
 457         lli->ciq_ids = rxq_info->rspq_id + rxq_info->nrxq;
 458         lli->nciq = rxq_info->nciq;
 459 }
 460
 461 int t4_uld_mem_alloc(struct adapter *adap)
 462 {
 463         struct sge *s = &adap->sge;
 464
 465         adap->uld = kcalloc(CXGB4_ULD_MAX, sizeof(*adap->uld), GFP_KERNEL);
 466         if (!adap->uld)
 467                 return -ENOMEM;
 468
 469         s->uld_rxq_info = kzalloc(CXGB4_ULD_MAX *
 470                                   sizeof(struct sge_uld_rxq_info *),
 471                                   GFP_KERNEL);
 472         if (!s->uld_rxq_info)
 473                 goto err_uld;
 474
 475         return 0;
 476 err_uld:
 477         kfree(adap->uld);
 478         return -ENOMEM;
 479 }
 480
 481 void t4_uld_mem_free(struct adapter *adap)
 482 {
 483         struct sge *s = &adap->sge;
 484
 485         kfree(s->uld_rxq_info);
 486         kfree(adap->uld);
 487 }
 488
 489 void t4_uld_clean_up(struct adapter *adap)
 490 {
 491         struct sge_uld_rxq_info *rxq_info;
 492         unsigned int i;
 493
 494         if (!adap->uld)
 495                 return;
 496         for (i = 0; i < CXGB4_ULD_MAX; i++) {
 497                 if (!adap->uld[i].handle)
 498                         continue;
 499                 rxq_info = adap->sge.uld_rxq_info[i];
 500                 if (adap->flags & FULL_INIT_DONE)
 501                         quiesce_rx_uld(adap, i);
 502                 if (adap->flags & USING_MSIX)
 503                         free_msix_queue_irqs_uld(adap, i);
 504                 free_sge_queues_uld(adap, i);
 505                 free_queues_uld(adap, i);
 506         }
 507 }
 508
 509 static void uld_init(struct adapter *adap, struct cxgb4_lld_info *lld)
 510 {
 511         int i;
 512
 513         lld->pdev = adap->pdev;
 514         lld->pf = adap->pf;
 515         lld->l2t = adap->l2t;
 516         lld->tids = &adap->tids;
 517         lld->ports = adap->port;
 518         lld->vr = &adap->vres;
 519         lld->mtus = adap->params.mtus;
 520         lld->ntxq = adap->sge.ofldqsets;
 521         lld->nchan = adap->params.nports;
 522         lld->nports = adap->params.nports;
 523         lld->wr_cred = adap->params.ofldq_wr_cred;
 524         lld->iscsi_iolen = MAXRXDATA_G(t4_read_reg(adap, TP_PARA_REG2_A));
 525         lld->iscsi_tagmask = t4_read_reg(adap, ULP_RX_ISCSI_TAGMASK_A);
 526         lld->iscsi_pgsz_order = t4_read_reg(adap, ULP_RX_ISCSI_PSZ_A);
 527         lld->iscsi_llimit = t4_read_reg(adap, ULP_RX_ISCSI_LLIMIT_A);
 528         lld->iscsi_ppm = &adap->iscsi_ppm;
 529         lld->adapter_type = adap->params.chip;
 530         lld->cclk_ps = 1000000000 / adap->params.vpd.cclk;
 531         lld->udb_density = 1 << adap->params.sge.eq_qpp;
 532         lld->ucq_density = 1 << adap->params.sge.iq_qpp;
 533         lld->filt_mode = adap->params.tp.vlan_pri_map;
 534         /* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */
 535         for (i = 0; i < NCHAN; i++)
 536                 lld->tx_modq[i] = i;
 537         lld->gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS_A);
 538         lld->db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL_A);
 539         lld->fw_vers = adap->params.fw_vers;
 540         lld->dbfifo_int_thresh = dbfifo_int_thresh;
 541         lld->sge_ingpadboundary = adap->sge.fl_align;
 542         lld->sge_egrstatuspagesize = adap->sge.stat_len;
 543         lld->sge_pktshift = adap->sge.pktshift;
 544         lld->enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN;
 545         lld->max_ordird_qp = adap->params.max_ordird_qp;
 546         lld->max_ird_adapter = adap->params.max_ird_adapter;
 547         lld->ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl;
 548         lld->nodeid = dev_to_node(adap->pdev_dev);
 549         lld->fr_nsmr_tpte_wr_support = adap->params.fr_nsmr_tpte_wr_support;
 550 }
 551
 552 static void uld_attach(struct adapter *adap, unsigned int uld)
 553 {
 554         void *handle;
 555         struct cxgb4_lld_info lli;
 556
 557         uld_init(adap, &lli);
 558         uld_queue_init(adap, uld, &lli);
 559
 560         handle = adap->uld[uld].add(&lli);
 561         if (IS_ERR(handle)) {
 562                 dev_warn(adap->pdev_dev,
 563                          "could not attach to the %s driver, error %ld\n",
 564                          adap->uld[uld].name, PTR_ERR(handle));
 565                 return;
 566         }
 567
 568         adap->uld[uld].handle = handle;
 569         t4_register_netevent_notifier();
 570
 571         if (adap->flags & FULL_INIT_DONE)
 572                 adap->uld[uld].state_change(handle, CXGB4_STATE_UP);
 573 }
 574
 575 /**
 576  *      cxgb4_register_uld - register an upper-layer driver
 577  *      @type: the ULD type
 578  *      @p: the ULD methods
 579  *
 580  *      Registers an upper-layer driver with this driver and notifies the ULD
 581  *      about any presently available devices that support its type.  Returns
 582  *      %-EBUSY if a ULD of the same type is already registered.
 583  */
 584 int cxgb4_register_uld(enum cxgb4_uld type,
 585                        const struct cxgb4_uld_info *p)
 586 {
 587         int ret = 0;
 588         unsigned int adap_idx = 0;
 589         struct adapter *adap;
 590
 591         if (type >= CXGB4_ULD_MAX)
 592                 return -EINVAL;
 593
 594         mutex_lock(&uld_mutex);
 595         list_for_each_entry(adap, &adapter_list, list_node) {
 596                 if ((type == CXGB4_ULD_CRYPTO && !is_pci_uld(adap)) ||
 597                     (type != CXGB4_ULD_CRYPTO && !is_offload(adap)))
 598                         continue;
 599                 if (type == CXGB4_ULD_ISCSIT && is_t4(adap->params.chip))
 600                         continue;
 601                 ret = cfg_queues_uld(adap, type, p);
 602                 if (ret)
 603                         goto out;
 604                 ret = setup_sge_queues_uld(adap, type, p->lro);
 605                 if (ret)
 606                         goto free_queues;
 607                 if (adap->flags & USING_MSIX) {
 608                         name_msix_vecs_uld(adap, type);
 609                         ret = request_msix_queue_irqs_uld(adap, type);
 610                         if (ret)
 611                                 goto free_rxq;
 612                 }
 613                 if (adap->flags & FULL_INIT_DONE)
 614                         enable_rx_uld(adap, type);
 615                 if (adap->uld[type].add) {
 616                         ret = -EBUSY;
 617                         goto free_irq;
 618                 }
 619                 adap->uld[type] = *p;
 620                 uld_attach(adap, type);
 621                 adap_idx++;
 622         }
 623         mutex_unlock(&uld_mutex);
 624         return 0;
 625
 626 free_irq:
 627         if (adap->flags & FULL_INIT_DONE)
 628                 quiesce_rx_uld(adap, type);
 629         if (adap->flags & USING_MSIX)
 630                 free_msix_queue_irqs_uld(adap, type);
 631 free_rxq:
 632         free_sge_queues_uld(adap, type);
 633 free_queues:
 634         free_queues_uld(adap, type);
 635 out:
 636
 637         list_for_each_entry(adap, &adapter_list, list_node) {
 638                 if ((type == CXGB4_ULD_CRYPTO && !is_pci_uld(adap)) ||
 639                     (type != CXGB4_ULD_CRYPTO && !is_offload(adap)))
 640                         continue;
 641                 if (type == CXGB4_ULD_ISCSIT && is_t4(adap->params.chip))
 642                         continue;
 643                 if (!adap_idx)
 644                         break;
 645                 adap->uld[type].handle = NULL;
 646                 adap->uld[type].add = NULL;
 647                 if (adap->flags & FULL_INIT_DONE)
 648                         quiesce_rx_uld(adap, type);
 649                 if (adap->flags & USING_MSIX)
 650                         free_msix_queue_irqs_uld(adap, type);
 651                 free_sge_queues_uld(adap, type);
 652                 free_queues_uld(adap, type);
 653                 adap_idx--;
 654         }
 655         mutex_unlock(&uld_mutex);
 656         return ret;
 657 }
 658 EXPORT_SYMBOL(cxgb4_register_uld);
 659
 660 /**
 661  *      cxgb4_unregister_uld - unregister an upper-layer driver
 662  *      @type: the ULD type
 663  *
 664  *      Unregisters an existing upper-layer driver.
 665  */
 666 int cxgb4_unregister_uld(enum cxgb4_uld type)
 667 {
 668         struct adapter *adap;
 669
 670         if (type >= CXGB4_ULD_MAX)
 671                 return -EINVAL;
 672
 673         mutex_lock(&uld_mutex);
 674         list_for_each_entry(adap, &adapter_list, list_node) {
 675                 if ((type == CXGB4_ULD_CRYPTO && !is_pci_uld(adap)) ||
 676                     (type != CXGB4_ULD_CRYPTO && !is_offload(adap)))
 677                         continue;
 678                 if (type == CXGB4_ULD_ISCSIT && is_t4(adap->params.chip))
 679                         continue;
 680                 adap->uld[type].handle = NULL;
 681                 adap->uld[type].add = NULL;
 682                 if (adap->flags & FULL_INIT_DONE)
 683                         quiesce_rx_uld(adap, type);
 684                 if (adap->flags & USING_MSIX)
 685                         free_msix_queue_irqs_uld(adap, type);
 686                 free_sge_queues_uld(adap, type);
 687                 free_queues_uld(adap, type);
 688         }
 689         mutex_unlock(&uld_mutex);
 690
 691         return 0;
 692 }
 693 EXPORT_SYMBOL(cxgb4_unregister_uld);