drivers/net/ethernet/chelsio/cxgb4/t4_hw.c

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #include <linux/delay.h>
  36 #include "cxgb4.h"
  37 #include "t4_regs.h"
  38 #include "t4_values.h"
  39 #include "t4fw_api.h"
  40 #include "t4fw_version.h"
  41
  42 /**
  43  *      t4_wait_op_done_val - wait until an operation is completed
  44  *      @adapter: the adapter performing the operation
  45  *      @reg: the register to check for completion
  46  *      @mask: a single-bit field within @reg that indicates completion
  47  *      @polarity: the value of the field when the operation is completed
  48  *      @attempts: number of check iterations
  49  *      @delay: delay in usecs between iterations
  50  *      @valp: where to store the value of the register at completion time
  51  *
  52  *      Wait until an operation is completed by checking a bit in a register
  53  *      up to @attempts times.  If @valp is not NULL the value of the register
  54  *      at the time it indicated completion is stored there.  Returns 0 if the
  55  *      operation completes and -EAGAIN otherwise.
  56  */
  57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
  58                                int polarity, int attempts, int delay, u32 *valp)
  59 {
  60         while (1) {
  61                 u32 val = t4_read_reg(adapter, reg);
  62
  63                 if (!!(val & mask) == polarity) {
  64                         if (valp)
  65                                 *valp = val;
  66                         return 0;
  67                 }
  68                 if (--attempts == 0)
  69                         return -EAGAIN;
  70                 if (delay)
  71                         udelay(delay);
  72         }
  73 }
  74
  75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
  76                                   int polarity, int attempts, int delay)
  77 {
  78         return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
  79                                    delay, NULL);
  80 }
  81
  82 /**
  83  *      t4_set_reg_field - set a register field to a value
  84  *      @adapter: the adapter to program
  85  *      @addr: the register address
  86  *      @mask: specifies the portion of the register to modify
  87  *      @val: the new value for the register field
  88  *
  89  *      Sets a register field specified by the supplied mask to the
  90  *      given value.
  91  */
  92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
  93                       u32 val)
  94 {
  95         u32 v = t4_read_reg(adapter, addr) & ~mask;
  96
  97         t4_write_reg(adapter, addr, v | val);
  98         (void) t4_read_reg(adapter, addr);      /* flush */
  99 }
 100
 101 /**
 102  *      t4_read_indirect - read indirectly addressed registers
 103  *      @adap: the adapter
 104  *      @addr_reg: register holding the indirect address
 105  *      @data_reg: register holding the value of the indirect register
 106  *      @vals: where the read register values are stored
 107  *      @nregs: how many indirect registers to read
 108  *      @start_idx: index of first indirect register to read
 109  *
 110  *      Reads registers that are accessed indirectly through an address/data
 111  *      register pair.
 112  */
 113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
 114                              unsigned int data_reg, u32 *vals,
 115                              unsigned int nregs, unsigned int start_idx)
 116 {
 117         while (nregs--) {
 118                 t4_write_reg(adap, addr_reg, start_idx);
 119                 *vals++ = t4_read_reg(adap, data_reg);
 120                 start_idx++;
 121         }
 122 }
 123
 124 /**
 125  *      t4_write_indirect - write indirectly addressed registers
 126  *      @adap: the adapter
 127  *      @addr_reg: register holding the indirect addresses
 128  *      @data_reg: register holding the value for the indirect registers
 129  *      @vals: values to write
 130  *      @nregs: how many indirect registers to write
 131  *      @start_idx: address of first indirect register to write
 132  *
 133  *      Writes a sequential block of registers that are accessed indirectly
 134  *      through an address/data register pair.
 135  */
 136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
 137                        unsigned int data_reg, const u32 *vals,
 138                        unsigned int nregs, unsigned int start_idx)
 139 {
 140         while (nregs--) {
 141                 t4_write_reg(adap, addr_reg, start_idx++);
 142                 t4_write_reg(adap, data_reg, *vals++);
 143         }
 144 }
 145
 146 /*
 147  * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
 148  * mechanism.  This guarantees that we get the real value even if we're
 149  * operating within a Virtual Machine and the Hypervisor is trapping our
 150  * Configuration Space accesses.
 151  */
 152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
 153 {
 154         u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
 155
 156         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
 157                 req |= ENABLE_F;
 158         else
 159                 req |= T6_ENABLE_F;
 160
 161         if (is_t4(adap->params.chip))
 162                 req |= LOCALCFG_F;
 163
 164         t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
 165         *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
 166
 167         /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
 168          * Configuration Space read.  (None of the other fields matter when
 169          * ENABLE is 0 so a simple register write is easier than a
 170          * read-modify-write via t4_set_reg_field().)
 171          */
 172         t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
 173 }
 174
 175 /*
 176  * t4_report_fw_error - report firmware error
 177  * @adap: the adapter
 178  *
 179  * The adapter firmware can indicate error conditions to the host.
 180  * If the firmware has indicated an error, print out the reason for
 181  * the firmware error.
 182  */
 183 static void t4_report_fw_error(struct adapter *adap)
 184 {
 185         static const char *const reason[] = {
 186                 "Crash",                        /* PCIE_FW_EVAL_CRASH */
 187                 "During Device Preparation",    /* PCIE_FW_EVAL_PREP */
 188                 "During Device Configuration",  /* PCIE_FW_EVAL_CONF */
 189                 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
 190                 "Unexpected Event",             /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
 191                 "Insufficient Airflow",         /* PCIE_FW_EVAL_OVERHEAT */
 192                 "Device Shutdown",              /* PCIE_FW_EVAL_DEVICESHUTDOWN */
 193                 "Reserved",                     /* reserved */
 194         };
 195         u32 pcie_fw;
 196
 197         pcie_fw = t4_read_reg(adap, PCIE_FW_A);
 198         if (pcie_fw & PCIE_FW_ERR_F)
 199                 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
 200                         reason[PCIE_FW_EVAL_G(pcie_fw)]);
 201 }
 202
 203 /*
 204  * Get the reply to a mailbox command and store it in @rpl in big-endian order.
 205  */
 206 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
 207                          u32 mbox_addr)
 208 {
 209         for ( ; nflit; nflit--, mbox_addr += 8)
 210                 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
 211 }
 212
 213 /*
 214  * Handle a FW assertion reported in a mailbox.
 215  */
 216 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
 217 {
 218         struct fw_debug_cmd asrt;
 219
 220         get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
 221         dev_alert(adap->pdev_dev,
 222                   "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
 223                   asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
 224                   be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
 225 }
 226
 227 /**
 228  *      t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
 229  *      @adapter: the adapter
 230  *      @cmd: the Firmware Mailbox Command or Reply
 231  *      @size: command length in bytes
 232  *      @access: the time (ms) needed to access the Firmware Mailbox
 233  *      @execute: the time (ms) the command spent being executed
 234  */
 235 static void t4_record_mbox(struct adapter *adapter,
 236                            const __be64 *cmd, unsigned int size,
 237                            int access, int execute)
 238 {
 239         struct mbox_cmd_log *log = adapter->mbox_log;
 240         struct mbox_cmd *entry;
 241         int i;
 242
 243         entry = mbox_cmd_log_entry(log, log->cursor++);
 244         if (log->cursor == log->size)
 245                 log->cursor = 0;
 246
 247         for (i = 0; i < size / 8; i++)
 248                 entry->cmd[i] = be64_to_cpu(cmd[i]);
 249         while (i < MBOX_LEN / 8)
 250                 entry->cmd[i++] = 0;
 251         entry->timestamp = jiffies;
 252         entry->seqno = log->seqno++;
 253         entry->access = access;
 254         entry->execute = execute;
 255 }
 256
 257 /**
 258  *      t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
 259  *      @adap: the adapter
 260  *      @mbox: index of the mailbox to use
 261  *      @cmd: the command to write
 262  *      @size: command length in bytes
 263  *      @rpl: where to optionally store the reply
 264  *      @sleep_ok: if true we may sleep while awaiting command completion
 265  *      @timeout: time to wait for command to finish before timing out
 266  *
 267  *      Sends the given command to FW through the selected mailbox and waits
 268  *      for the FW to execute the command.  If @rpl is not %NULL it is used to
 269  *      store the FW's reply to the command.  The command and its optional
 270  *      reply are of the same length.  FW can take up to %FW_CMD_MAX_TIMEOUT ms
 271  *      to respond.  @sleep_ok determines whether we may sleep while awaiting
 272  *      the response.  If sleeping is allowed we use progressive backoff
 273  *      otherwise we spin.
 274  *
 275  *      The return value is 0 on success or a negative errno on failure.  A
 276  *      failure can happen either because we are not able to execute the
 277  *      command or FW executes it but signals an error.  In the latter case
 278  *      the return value is the error code indicated by FW (negated).
 279  */
 280 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
 281                             int size, void *rpl, bool sleep_ok, int timeout)
 282 {
 283         static const int delay[] = {
 284                 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
 285         };
 286
 287         u16 access = 0;
 288         u16 execute = 0;
 289         u32 v;
 290         u64 res;
 291         int i, ms, delay_idx, ret;
 292         const __be64 *p = cmd;
 293         u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
 294         u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
 295         __be64 cmd_rpl[MBOX_LEN / 8];
 296         u32 pcie_fw;
 297
 298         if ((size & 15) || size > MBOX_LEN)
 299                 return -EINVAL;
 300
 301         /*
 302          * If the device is off-line, as in EEH, commands will time out.
 303          * Fail them early so we don't waste time waiting.
 304          */
 305         if (adap->pdev->error_state != pci_channel_io_normal)
 306                 return -EIO;
 307
 308         /* If we have a negative timeout, that implies that we can't sleep. */
 309         if (timeout < 0) {
 310                 sleep_ok = false;
 311                 timeout = -timeout;
 312         }
 313
 314         v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
 315         for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
 316                 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
 317
 318         if (v != MBOX_OWNER_DRV) {
 319                 ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
 320                 t4_record_mbox(adap, cmd, MBOX_LEN, access, ret);
 321                 return ret;
 322         }
 323
 324         /* Copy in the new mailbox command and send it on its way ... */
 325         t4_record_mbox(adap, cmd, MBOX_LEN, access, 0);
 326         for (i = 0; i < size; i += 8)
 327                 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
 328
 329         t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
 330         t4_read_reg(adap, ctl_reg);          /* flush write */
 331
 332         delay_idx = 0;
 333         ms = delay[0];
 334
 335         for (i = 0;
 336              !((pcie_fw = t4_read_reg(adap, PCIE_FW_A)) & PCIE_FW_ERR_F) &&
 337              i < timeout;
 338              i += ms) {
 339                 if (sleep_ok) {
 340                         ms = delay[delay_idx];  /* last element may repeat */
 341                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 342                                 delay_idx++;
 343                         msleep(ms);
 344                 } else
 345                         mdelay(ms);
 346
 347                 v = t4_read_reg(adap, ctl_reg);
 348                 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
 349                         if (!(v & MBMSGVALID_F)) {
 350                                 t4_write_reg(adap, ctl_reg, 0);
 351                                 continue;
 352                         }
 353
 354                         get_mbox_rpl(adap, cmd_rpl, MBOX_LEN / 8, data_reg);
 355                         res = be64_to_cpu(cmd_rpl[0]);
 356
 357                         if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
 358                                 fw_asrt(adap, data_reg);
 359                                 res = FW_CMD_RETVAL_V(EIO);
 360                         } else if (rpl) {
 361                                 memcpy(rpl, cmd_rpl, size);
 362                         }
 363
 364                         t4_write_reg(adap, ctl_reg, 0);
 365
 366                         execute = i + ms;
 367                         t4_record_mbox(adap, cmd_rpl,
 368                                        MBOX_LEN, access, execute);
 369                         return -FW_CMD_RETVAL_G((int)res);
 370                 }
 371         }
 372
 373         ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -ETIMEDOUT;
 374         t4_record_mbox(adap, cmd, MBOX_LEN, access, ret);
 375         dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
 376                 *(const u8 *)cmd, mbox);
 377         t4_report_fw_error(adap);
 378         return ret;
 379 }
 380
 381 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
 382                     void *rpl, bool sleep_ok)
 383 {
 384         return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
 385                                        FW_CMD_MAX_TIMEOUT);
 386 }
 387
 388 static int t4_edc_err_read(struct adapter *adap, int idx)
 389 {
 390         u32 edc_ecc_err_addr_reg;
 391         u32 rdata_reg;
 392
 393         if (is_t4(adap->params.chip)) {
 394                 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
 395                 return 0;
 396         }
 397         if (idx != 0 && idx != 1) {
 398                 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
 399                 return 0;
 400         }
 401
 402         edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
 403         rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
 404
 405         CH_WARN(adap,
 406                 "edc%d err addr 0x%x: 0x%x.\n",
 407                 idx, edc_ecc_err_addr_reg,
 408                 t4_read_reg(adap, edc_ecc_err_addr_reg));
 409         CH_WARN(adap,
 410                 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
 411                 rdata_reg,
 412                 (unsigned long long)t4_read_reg64(adap, rdata_reg),
 413                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
 414                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
 415                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
 416                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
 417                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
 418                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
 419                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
 420                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
 421
 422         return 0;
 423 }
 424
 425 /**
 426  *      t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
 427  *      @adap: the adapter
 428  *      @win: PCI-E Memory Window to use
 429  *      @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
 430  *      @addr: address within indicated memory type
 431  *      @len: amount of memory to transfer
 432  *      @hbuf: host memory buffer
 433  *      @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
 434  *
 435  *      Reads/writes an [almost] arbitrary memory region in the firmware: the
 436  *      firmware memory address and host buffer must be aligned on 32-bit
 437  *      boudaries; the length may be arbitrary.  The memory is transferred as
 438  *      a raw byte sequence from/to the firmware's memory.  If this memory
 439  *      contains data structures which contain multi-byte integers, it's the
 440  *      caller's responsibility to perform appropriate byte order conversions.
 441  */
 442 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
 443                  u32 len, void *hbuf, int dir)
 444 {
 445         u32 pos, offset, resid, memoffset;
 446         u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
 447         u32 *buf;
 448
 449         /* Argument sanity checks ...
 450          */
 451         if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
 452                 return -EINVAL;
 453         buf = (u32 *)hbuf;
 454
 455         /* It's convenient to be able to handle lengths which aren't a
 456          * multiple of 32-bits because we often end up transferring files to
 457          * the firmware.  So we'll handle that by normalizing the length here
 458          * and then handling any residual transfer at the end.
 459          */
 460         resid = len & 0x3;
 461         len -= resid;
 462
 463         /* Offset into the region of memory which is being accessed
 464          * MEM_EDC0 = 0
 465          * MEM_EDC1 = 1
 466          * MEM_MC   = 2 -- MEM_MC for chips with only 1 memory controller
 467          * MEM_MC1  = 3 -- for chips with 2 memory controllers (e.g. T5)
 468          */
 469         edc_size  = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
 470         if (mtype != MEM_MC1)
 471                 memoffset = (mtype * (edc_size * 1024 * 1024));
 472         else {
 473                 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
 474                                                       MA_EXT_MEMORY0_BAR_A));
 475                 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
 476         }
 477
 478         /* Determine the PCIE_MEM_ACCESS_OFFSET */
 479         addr = addr + memoffset;
 480
 481         /* Each PCI-E Memory Window is programmed with a window size -- or
 482          * "aperture" -- which controls the granularity of its mapping onto
 483          * adapter memory.  We need to grab that aperture in order to know
 484          * how to use the specified window.  The window is also programmed
 485          * with the base address of the Memory Window in BAR0's address
 486          * space.  For T4 this is an absolute PCI-E Bus Address.  For T5
 487          * the address is relative to BAR0.
 488          */
 489         mem_reg = t4_read_reg(adap,
 490                               PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
 491                                                   win));
 492         mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
 493         mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
 494         if (is_t4(adap->params.chip))
 495                 mem_base -= adap->t4_bar0;
 496         win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
 497
 498         /* Calculate our initial PCI-E Memory Window Position and Offset into
 499          * that Window.
 500          */
 501         pos = addr & ~(mem_aperture-1);
 502         offset = addr - pos;
 503
 504         /* Set up initial PCI-E Memory Window to cover the start of our
 505          * transfer.  (Read it back to ensure that changes propagate before we
 506          * attempt to use the new value.)
 507          */
 508         t4_write_reg(adap,
 509                      PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
 510                      pos | win_pf);
 511         t4_read_reg(adap,
 512                     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
 513
 514         /* Transfer data to/from the adapter as long as there's an integral
 515          * number of 32-bit transfers to complete.
 516          *
 517          * A note on Endianness issues:
 518          *
 519          * The "register" reads and writes below from/to the PCI-E Memory
 520          * Window invoke the standard adapter Big-Endian to PCI-E Link
 521          * Little-Endian "swizzel."  As a result, if we have the following
 522          * data in adapter memory:
 523          *
 524          *     Memory:  ... | b0 | b1 | b2 | b3 | ...
 525          *     Address:      i+0  i+1  i+2  i+3
 526          *
 527          * Then a read of the adapter memory via the PCI-E Memory Window
 528          * will yield:
 529          *
 530          *     x = readl(i)
 531          *         31                  0
 532          *         [ b3 | b2 | b1 | b0 ]
 533          *
 534          * If this value is stored into local memory on a Little-Endian system
 535          * it will show up correctly in local memory as:
 536          *
 537          *     ( ..., b0, b1, b2, b3, ... )
 538          *
 539          * But on a Big-Endian system, the store will show up in memory
 540          * incorrectly swizzled as:
 541          *
 542          *     ( ..., b3, b2, b1, b0, ... )
 543          *
 544          * So we need to account for this in the reads and writes to the
 545          * PCI-E Memory Window below by undoing the register read/write
 546          * swizzels.
 547          */
 548         while (len > 0) {
 549                 if (dir == T4_MEMORY_READ)
 550                         *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
 551                                                 mem_base + offset));
 552                 else
 553                         t4_write_reg(adap, mem_base + offset,
 554                                      (__force u32)cpu_to_le32(*buf++));
 555                 offset += sizeof(__be32);
 556                 len -= sizeof(__be32);
 557
 558                 /* If we've reached the end of our current window aperture,
 559                  * move the PCI-E Memory Window on to the next.  Note that
 560                  * doing this here after "len" may be 0 allows us to set up
 561                  * the PCI-E Memory Window for a possible final residual
 562                  * transfer below ...
 563                  */
 564                 if (offset == mem_aperture) {
 565                         pos += mem_aperture;
 566                         offset = 0;
 567                         t4_write_reg(adap,
 568                                 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
 569                                                     win), pos | win_pf);
 570                         t4_read_reg(adap,
 571                                 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
 572                                                     win));
 573                 }
 574         }
 575
 576         /* If the original transfer had a length which wasn't a multiple of
 577          * 32-bits, now's where we need to finish off the transfer of the
 578          * residual amount.  The PCI-E Memory Window has already been moved
 579          * above (if necessary) to cover this final transfer.
 580          */
 581         if (resid) {
 582                 union {
 583                         u32 word;
 584                         char byte[4];
 585                 } last;
 586                 unsigned char *bp;
 587                 int i;
 588
 589                 if (dir == T4_MEMORY_READ) {
 590                         last.word = le32_to_cpu(
 591                                         (__force __le32)t4_read_reg(adap,
 592                                                 mem_base + offset));
 593                         for (bp = (unsigned char *)buf, i = resid; i < 4; i++)
 594                                 bp[i] = last.byte[i];
 595                 } else {
 596                         last.word = *buf;
 597                         for (i = resid; i < 4; i++)
 598                                 last.byte[i] = 0;
 599                         t4_write_reg(adap, mem_base + offset,
 600                                      (__force u32)cpu_to_le32(last.word));
 601                 }
 602         }
 603
 604         return 0;
 605 }
 606
 607 /* Return the specified PCI-E Configuration Space register from our Physical
 608  * Function.  We try first via a Firmware LDST Command since we prefer to let
 609  * the firmware own all of these registers, but if that fails we go for it
 610  * directly ourselves.
 611  */
 612 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
 613 {
 614         u32 val, ldst_addrspace;
 615
 616         /* If fw_attach != 0, construct and send the Firmware LDST Command to
 617          * retrieve the specified PCI-E Configuration Space register.
 618          */
 619         struct fw_ldst_cmd ldst_cmd;
 620         int ret;
 621
 622         memset(&ldst_cmd, 0, sizeof(ldst_cmd));
 623         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
 624         ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
 625                                                FW_CMD_REQUEST_F |
 626                                                FW_CMD_READ_F |
 627                                                ldst_addrspace);
 628         ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
 629         ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
 630         ldst_cmd.u.pcie.ctrl_to_fn =
 631                 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
 632         ldst_cmd.u.pcie.r = reg;
 633
 634         /* If the LDST Command succeeds, return the result, otherwise
 635          * fall through to reading it directly ourselves ...
 636          */
 637         ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
 638                          &ldst_cmd);
 639         if (ret == 0)
 640                 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
 641         else
 642                 /* Read the desired Configuration Space register via the PCI-E
 643                  * Backdoor mechanism.
 644                  */
 645                 t4_hw_pci_read_cfg4(adap, reg, &val);
 646         return val;
 647 }
 648
 649 /* Get the window based on base passed to it.
 650  * Window aperture is currently unhandled, but there is no use case for it
 651  * right now
 652  */
 653 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
 654                          u32 memwin_base)
 655 {
 656         u32 ret;
 657
 658         if (is_t4(adap->params.chip)) {
 659                 u32 bar0;
 660
 661                 /* Truncation intentional: we only read the bottom 32-bits of
 662                  * the 64-bit BAR0/BAR1 ...  We use the hardware backdoor
 663                  * mechanism to read BAR0 instead of using
 664                  * pci_resource_start() because we could be operating from
 665                  * within a Virtual Machine which is trapping our accesses to
 666                  * our Configuration Space and we need to set up the PCI-E
 667                  * Memory Window decoders with the actual addresses which will
 668                  * be coming across the PCI-E link.
 669                  */
 670                 bar0 = t4_read_pcie_cfg4(adap, pci_base);
 671                 bar0 &= pci_mask;
 672                 adap->t4_bar0 = bar0;
 673
 674                 ret = bar0 + memwin_base;
 675         } else {
 676                 /* For T5, only relative offset inside the PCIe BAR is passed */
 677                 ret = memwin_base;
 678         }
 679         return ret;
 680 }
 681
 682 /* Get the default utility window (win0) used by everyone */
 683 u32 t4_get_util_window(struct adapter *adap)
 684 {
 685         return t4_get_window(adap, PCI_BASE_ADDRESS_0,
 686                              PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
 687 }
 688
 689 /* Set up memory window for accessing adapter memory ranges.  (Read
 690  * back MA register to ensure that changes propagate before we attempt
 691  * to use the new values.)
 692  */
 693 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
 694 {
 695         t4_write_reg(adap,
 696                      PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
 697                      memwin_base | BIR_V(0) |
 698                      WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
 699         t4_read_reg(adap,
 700                     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
 701 }
 702
 703 /**
 704  *      t4_get_regs_len - return the size of the chips register set
 705  *      @adapter: the adapter
 706  *
 707  *      Returns the size of the chip's BAR0 register space.
 708  */
 709 unsigned int t4_get_regs_len(struct adapter *adapter)
 710 {
 711         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
 712
 713         switch (chip_version) {
 714         case CHELSIO_T4:
 715                 return T4_REGMAP_SIZE;
 716
 717         case CHELSIO_T5:
 718         case CHELSIO_T6:
 719                 return T5_REGMAP_SIZE;
 720         }
 721
 722         dev_err(adapter->pdev_dev,
 723                 "Unsupported chip version %d\n", chip_version);
 724         return 0;
 725 }
 726
 727 /**
 728  *      t4_get_regs - read chip registers into provided buffer
 729  *      @adap: the adapter
 730  *      @buf: register buffer
 731  *      @buf_size: size (in bytes) of register buffer
 732  *
 733  *      If the provided register buffer isn't large enough for the chip's
 734  *      full register range, the register dump will be truncated to the
 735  *      register buffer's size.
 736  */
 737 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
 738 {
 739         static const unsigned int t4_reg_ranges[] = {
 740                 0x1008, 0x1108,
 741                 0x1180, 0x1184,
 742                 0x1190, 0x1194,
 743                 0x11a0, 0x11a4,
 744                 0x11b0, 0x11b4,
 745                 0x11fc, 0x123c,
 746                 0x1300, 0x173c,
 747                 0x1800, 0x18fc,
 748                 0x3000, 0x30d8,
 749                 0x30e0, 0x30e4,
 750                 0x30ec, 0x5910,
 751                 0x5920, 0x5924,
 752                 0x5960, 0x5960,
 753                 0x5968, 0x5968,
 754                 0x5970, 0x5970,
 755                 0x5978, 0x5978,
 756                 0x5980, 0x5980,
 757                 0x5988, 0x5988,
 758                 0x5990, 0x5990,
 759                 0x5998, 0x5998,
 760                 0x59a0, 0x59d4,
 761                 0x5a00, 0x5ae0,
 762                 0x5ae8, 0x5ae8,
 763                 0x5af0, 0x5af0,
 764                 0x5af8, 0x5af8,
 765                 0x6000, 0x6098,
 766                 0x6100, 0x6150,
 767                 0x6200, 0x6208,
 768                 0x6240, 0x6248,
 769                 0x6280, 0x62b0,
 770                 0x62c0, 0x6338,
 771                 0x6370, 0x638c,
 772                 0x6400, 0x643c,
 773                 0x6500, 0x6524,
 774                 0x6a00, 0x6a04,
 775                 0x6a14, 0x6a38,
 776                 0x6a60, 0x6a70,
 777                 0x6a78, 0x6a78,
 778                 0x6b00, 0x6b0c,
 779                 0x6b1c, 0x6b84,
 780                 0x6bf0, 0x6bf8,
 781                 0x6c00, 0x6c0c,
 782                 0x6c1c, 0x6c84,
 783                 0x6cf0, 0x6cf8,
 784                 0x6d00, 0x6d0c,
 785                 0x6d1c, 0x6d84,
 786                 0x6df0, 0x6df8,
 787                 0x6e00, 0x6e0c,
 788                 0x6e1c, 0x6e84,
 789                 0x6ef0, 0x6ef8,
 790                 0x6f00, 0x6f0c,
 791                 0x6f1c, 0x6f84,
 792                 0x6ff0, 0x6ff8,
 793                 0x7000, 0x700c,
 794                 0x701c, 0x7084,
 795                 0x70f0, 0x70f8,
 796                 0x7100, 0x710c,
 797                 0x711c, 0x7184,
 798                 0x71f0, 0x71f8,
 799                 0x7200, 0x720c,
 800                 0x721c, 0x7284,
 801                 0x72f0, 0x72f8,
 802                 0x7300, 0x730c,
 803                 0x731c, 0x7384,
 804                 0x73f0, 0x73f8,
 805                 0x7400, 0x7450,
 806                 0x7500, 0x7530,
 807                 0x7600, 0x760c,
 808                 0x7614, 0x761c,
 809                 0x7680, 0x76cc,
 810                 0x7700, 0x7798,
 811                 0x77c0, 0x77fc,
 812                 0x7900, 0x79fc,
 813                 0x7b00, 0x7b58,
 814                 0x7b60, 0x7b84,
 815                 0x7b8c, 0x7c38,
 816                 0x7d00, 0x7d38,
 817                 0x7d40, 0x7d80,
 818                 0x7d8c, 0x7ddc,
 819                 0x7de4, 0x7e04,
 820                 0x7e10, 0x7e1c,
 821                 0x7e24, 0x7e38,
 822                 0x7e40, 0x7e44,
 823                 0x7e4c, 0x7e78,
 824                 0x7e80, 0x7ea4,
 825                 0x7eac, 0x7edc,
 826                 0x7ee8, 0x7efc,
 827                 0x8dc0, 0x8e04,
 828                 0x8e10, 0x8e1c,
 829                 0x8e30, 0x8e78,
 830                 0x8ea0, 0x8eb8,
 831                 0x8ec0, 0x8f6c,
 832                 0x8fc0, 0x9008,
 833                 0x9010, 0x9058,
 834                 0x9060, 0x9060,
 835                 0x9068, 0x9074,
 836                 0x90fc, 0x90fc,
 837                 0x9400, 0x9408,
 838                 0x9410, 0x9458,
 839                 0x9600, 0x9600,
 840                 0x9608, 0x9638,
 841                 0x9640, 0x96bc,
 842                 0x9800, 0x9808,
 843                 0x9820, 0x983c,
 844                 0x9850, 0x9864,
 845                 0x9c00, 0x9c6c,
 846                 0x9c80, 0x9cec,
 847                 0x9d00, 0x9d6c,
 848                 0x9d80, 0x9dec,
 849                 0x9e00, 0x9e6c,
 850                 0x9e80, 0x9eec,
 851                 0x9f00, 0x9f6c,
 852                 0x9f80, 0x9fec,
 853                 0xd004, 0xd004,
 854                 0xd010, 0xd03c,
 855                 0xdfc0, 0xdfe0,
 856                 0xe000, 0xea7c,
 857                 0xf000, 0x11190,
 858                 0x19040, 0x1906c,
 859                 0x19078, 0x19080,
 860                 0x1908c, 0x190e4,
 861                 0x190f0, 0x190f8,
 862                 0x19100, 0x19110,
 863                 0x19120, 0x19124,
 864                 0x19150, 0x19194,
 865                 0x1919c, 0x191b0,
 866                 0x191d0, 0x191e8,
 867                 0x19238, 0x1924c,
 868                 0x193f8, 0x1943c,
 869                 0x1944c, 0x19474,
 870                 0x19490, 0x194e0,
 871                 0x194f0, 0x194f8,
 872                 0x19800, 0x19c08,
 873                 0x19c10, 0x19c90,
 874                 0x19ca0, 0x19ce4,
 875                 0x19cf0, 0x19d40,
 876                 0x19d50, 0x19d94,
 877                 0x19da0, 0x19de8,
 878                 0x19df0, 0x19e40,
 879                 0x19e50, 0x19e90,
 880                 0x19ea0, 0x19f4c,
 881                 0x1a000, 0x1a004,
 882                 0x1a010, 0x1a06c,
 883                 0x1a0b0, 0x1a0e4,
 884                 0x1a0ec, 0x1a0f4,
 885                 0x1a100, 0x1a108,
 886                 0x1a114, 0x1a120,
 887                 0x1a128, 0x1a130,
 888                 0x1a138, 0x1a138,
 889                 0x1a190, 0x1a1c4,
 890                 0x1a1fc, 0x1a1fc,
 891                 0x1e040, 0x1e04c,
 892                 0x1e284, 0x1e28c,
 893                 0x1e2c0, 0x1e2c0,
 894                 0x1e2e0, 0x1e2e0,
 895                 0x1e300, 0x1e384,
 896                 0x1e3c0, 0x1e3c8,
 897                 0x1e440, 0x1e44c,
 898                 0x1e684, 0x1e68c,
 899                 0x1e6c0, 0x1e6c0,
 900                 0x1e6e0, 0x1e6e0,
 901                 0x1e700, 0x1e784,
 902                 0x1e7c0, 0x1e7c8,
 903                 0x1e840, 0x1e84c,
 904                 0x1ea84, 0x1ea8c,
 905                 0x1eac0, 0x1eac0,
 906                 0x1eae0, 0x1eae0,
 907                 0x1eb00, 0x1eb84,
 908                 0x1ebc0, 0x1ebc8,
 909                 0x1ec40, 0x1ec4c,
 910                 0x1ee84, 0x1ee8c,
 911                 0x1eec0, 0x1eec0,
 912                 0x1eee0, 0x1eee0,
 913                 0x1ef00, 0x1ef84,
 914                 0x1efc0, 0x1efc8,
 915                 0x1f040, 0x1f04c,
 916                 0x1f284, 0x1f28c,
 917                 0x1f2c0, 0x1f2c0,
 918                 0x1f2e0, 0x1f2e0,
 919                 0x1f300, 0x1f384,
 920                 0x1f3c0, 0x1f3c8,
 921                 0x1f440, 0x1f44c,
 922                 0x1f684, 0x1f68c,
 923                 0x1f6c0, 0x1f6c0,
 924                 0x1f6e0, 0x1f6e0,
 925                 0x1f700, 0x1f784,
 926                 0x1f7c0, 0x1f7c8,
 927                 0x1f840, 0x1f84c,
 928                 0x1fa84, 0x1fa8c,
 929                 0x1fac0, 0x1fac0,
 930                 0x1fae0, 0x1fae0,
 931                 0x1fb00, 0x1fb84,
 932                 0x1fbc0, 0x1fbc8,
 933                 0x1fc40, 0x1fc4c,
 934                 0x1fe84, 0x1fe8c,
 935                 0x1fec0, 0x1fec0,
 936                 0x1fee0, 0x1fee0,
 937                 0x1ff00, 0x1ff84,
 938                 0x1ffc0, 0x1ffc8,
 939                 0x20000, 0x2002c,
 940                 0x20100, 0x2013c,
 941                 0x20190, 0x201a0,
 942                 0x201a8, 0x201b8,
 943                 0x201c4, 0x201c8,
 944                 0x20200, 0x20318,
 945                 0x20400, 0x204b4,
 946                 0x204c0, 0x20528,
 947                 0x20540, 0x20614,
 948                 0x21000, 0x21040,
 949                 0x2104c, 0x21060,
 950                 0x210c0, 0x210ec,
 951                 0x21200, 0x21268,
 952                 0x21270, 0x21284,
 953                 0x212fc, 0x21388,
 954                 0x21400, 0x21404,
 955                 0x21500, 0x21500,
 956                 0x21510, 0x21518,
 957                 0x2152c, 0x21530,
 958                 0x2153c, 0x2153c,
 959                 0x21550, 0x21554,
 960                 0x21600, 0x21600,
 961                 0x21608, 0x2161c,
 962                 0x21624, 0x21628,
 963                 0x21630, 0x21634,
 964                 0x2163c, 0x2163c,
 965                 0x21700, 0x2171c,
 966                 0x21780, 0x2178c,
 967                 0x21800, 0x21818,
 968                 0x21820, 0x21828,
 969                 0x21830, 0x21848,
 970                 0x21850, 0x21854,
 971                 0x21860, 0x21868,
 972                 0x21870, 0x21870,
 973                 0x21878, 0x21898,
 974                 0x218a0, 0x218a8,
 975                 0x218b0, 0x218c8,
 976                 0x218d0, 0x218d4,
 977                 0x218e0, 0x218e8,
 978                 0x218f0, 0x218f0,
 979                 0x218f8, 0x21a18,
 980                 0x21a20, 0x21a28,
 981                 0x21a30, 0x21a48,
 982                 0x21a50, 0x21a54,
 983                 0x21a60, 0x21a68,
 984                 0x21a70, 0x21a70,
 985                 0x21a78, 0x21a98,
 986                 0x21aa0, 0x21aa8,
 987                 0x21ab0, 0x21ac8,
 988                 0x21ad0, 0x21ad4,
 989                 0x21ae0, 0x21ae8,
 990                 0x21af0, 0x21af0,
 991                 0x21af8, 0x21c18,
 992                 0x21c20, 0x21c20,
 993                 0x21c28, 0x21c30,
 994                 0x21c38, 0x21c38,
 995                 0x21c80, 0x21c98,
 996                 0x21ca0, 0x21ca8,
 997                 0x21cb0, 0x21cc8,
 998                 0x21cd0, 0x21cd4,
 999                 0x21ce0, 0x21ce8,
1000                 0x21cf0, 0x21cf0,
1001                 0x21cf8, 0x21d7c,
1002                 0x21e00, 0x21e04,
1003                 0x22000, 0x2202c,
1004                 0x22100, 0x2213c,
1005                 0x22190, 0x221a0,
1006                 0x221a8, 0x221b8,
1007                 0x221c4, 0x221c8,
1008                 0x22200, 0x22318,
1009                 0x22400, 0x224b4,
1010                 0x224c0, 0x22528,
1011                 0x22540, 0x22614,
1012                 0x23000, 0x23040,
1013                 0x2304c, 0x23060,
1014                 0x230c0, 0x230ec,
1015                 0x23200, 0x23268,
1016                 0x23270, 0x23284,
1017                 0x232fc, 0x23388,
1018                 0x23400, 0x23404,
1019                 0x23500, 0x23500,
1020                 0x23510, 0x23518,
1021                 0x2352c, 0x23530,
1022                 0x2353c, 0x2353c,
1023                 0x23550, 0x23554,
1024                 0x23600, 0x23600,
1025                 0x23608, 0x2361c,
1026                 0x23624, 0x23628,
1027                 0x23630, 0x23634,
1028                 0x2363c, 0x2363c,
1029                 0x23700, 0x2371c,
1030                 0x23780, 0x2378c,
1031                 0x23800, 0x23818,
1032                 0x23820, 0x23828,
1033                 0x23830, 0x23848,
1034                 0x23850, 0x23854,
1035                 0x23860, 0x23868,
1036                 0x23870, 0x23870,
1037                 0x23878, 0x23898,
1038                 0x238a0, 0x238a8,
1039                 0x238b0, 0x238c8,
1040                 0x238d0, 0x238d4,
1041                 0x238e0, 0x238e8,
1042                 0x238f0, 0x238f0,
1043                 0x238f8, 0x23a18,
1044                 0x23a20, 0x23a28,
1045                 0x23a30, 0x23a48,
1046                 0x23a50, 0x23a54,
1047                 0x23a60, 0x23a68,
1048                 0x23a70, 0x23a70,
1049                 0x23a78, 0x23a98,
1050                 0x23aa0, 0x23aa8,
1051                 0x23ab0, 0x23ac8,
1052                 0x23ad0, 0x23ad4,
1053                 0x23ae0, 0x23ae8,
1054                 0x23af0, 0x23af0,
1055                 0x23af8, 0x23c18,
1056                 0x23c20, 0x23c20,
1057                 0x23c28, 0x23c30,
1058                 0x23c38, 0x23c38,
1059                 0x23c80, 0x23c98,
1060                 0x23ca0, 0x23ca8,
1061                 0x23cb0, 0x23cc8,
1062                 0x23cd0, 0x23cd4,
1063                 0x23ce0, 0x23ce8,
1064                 0x23cf0, 0x23cf0,
1065                 0x23cf8, 0x23d7c,
1066                 0x23e00, 0x23e04,
1067                 0x24000, 0x2402c,
1068                 0x24100, 0x2413c,
1069                 0x24190, 0x241a0,
1070                 0x241a8, 0x241b8,
1071                 0x241c4, 0x241c8,
1072                 0x24200, 0x24318,
1073                 0x24400, 0x244b4,
1074                 0x244c0, 0x24528,
1075                 0x24540, 0x24614,
1076                 0x25000, 0x25040,
1077                 0x2504c, 0x25060,
1078                 0x250c0, 0x250ec,
1079                 0x25200, 0x25268,
1080                 0x25270, 0x25284,
1081                 0x252fc, 0x25388,
1082                 0x25400, 0x25404,
1083                 0x25500, 0x25500,
1084                 0x25510, 0x25518,
1085                 0x2552c, 0x25530,
1086                 0x2553c, 0x2553c,
1087                 0x25550, 0x25554,
1088                 0x25600, 0x25600,
1089                 0x25608, 0x2561c,
1090                 0x25624, 0x25628,
1091                 0x25630, 0x25634,
1092                 0x2563c, 0x2563c,
1093                 0x25700, 0x2571c,
1094                 0x25780, 0x2578c,
1095                 0x25800, 0x25818,
1096                 0x25820, 0x25828,
1097                 0x25830, 0x25848,
1098                 0x25850, 0x25854,
1099                 0x25860, 0x25868,
1100                 0x25870, 0x25870,
1101                 0x25878, 0x25898,
1102                 0x258a0, 0x258a8,
1103                 0x258b0, 0x258c8,
1104                 0x258d0, 0x258d4,
1105                 0x258e0, 0x258e8,
1106                 0x258f0, 0x258f0,
1107                 0x258f8, 0x25a18,
1108                 0x25a20, 0x25a28,
1109                 0x25a30, 0x25a48,
1110                 0x25a50, 0x25a54,
1111                 0x25a60, 0x25a68,
1112                 0x25a70, 0x25a70,
1113                 0x25a78, 0x25a98,
1114                 0x25aa0, 0x25aa8,
1115                 0x25ab0, 0x25ac8,
1116                 0x25ad0, 0x25ad4,
1117                 0x25ae0, 0x25ae8,
1118                 0x25af0, 0x25af0,
1119                 0x25af8, 0x25c18,
1120                 0x25c20, 0x25c20,
1121                 0x25c28, 0x25c30,
1122                 0x25c38, 0x25c38,
1123                 0x25c80, 0x25c98,
1124                 0x25ca0, 0x25ca8,
1125                 0x25cb0, 0x25cc8,
1126                 0x25cd0, 0x25cd4,
1127                 0x25ce0, 0x25ce8,
1128                 0x25cf0, 0x25cf0,
1129                 0x25cf8, 0x25d7c,
1130                 0x25e00, 0x25e04,
1131                 0x26000, 0x2602c,
1132                 0x26100, 0x2613c,
1133                 0x26190, 0x261a0,
1134                 0x261a8, 0x261b8,
1135                 0x261c4, 0x261c8,
1136                 0x26200, 0x26318,
1137                 0x26400, 0x264b4,
1138                 0x264c0, 0x26528,
1139                 0x26540, 0x26614,
1140                 0x27000, 0x27040,
1141                 0x2704c, 0x27060,
1142                 0x270c0, 0x270ec,
1143                 0x27200, 0x27268,
1144                 0x27270, 0x27284,
1145                 0x272fc, 0x27388,
1146                 0x27400, 0x27404,
1147                 0x27500, 0x27500,
1148                 0x27510, 0x27518,
1149                 0x2752c, 0x27530,
1150                 0x2753c, 0x2753c,
1151                 0x27550, 0x27554,
1152                 0x27600, 0x27600,
1153                 0x27608, 0x2761c,
1154                 0x27624, 0x27628,
1155                 0x27630, 0x27634,
1156                 0x2763c, 0x2763c,
1157                 0x27700, 0x2771c,
1158                 0x27780, 0x2778c,
1159                 0x27800, 0x27818,
1160                 0x27820, 0x27828,
1161                 0x27830, 0x27848,
1162                 0x27850, 0x27854,
1163                 0x27860, 0x27868,
1164                 0x27870, 0x27870,
1165                 0x27878, 0x27898,
1166                 0x278a0, 0x278a8,
1167                 0x278b0, 0x278c8,
1168                 0x278d0, 0x278d4,
1169                 0x278e0, 0x278e8,
1170                 0x278f0, 0x278f0,
1171                 0x278f8, 0x27a18,
1172                 0x27a20, 0x27a28,
1173                 0x27a30, 0x27a48,
1174                 0x27a50, 0x27a54,
1175                 0x27a60, 0x27a68,
1176                 0x27a70, 0x27a70,
1177                 0x27a78, 0x27a98,
1178                 0x27aa0, 0x27aa8,
1179                 0x27ab0, 0x27ac8,
1180                 0x27ad0, 0x27ad4,
1181                 0x27ae0, 0x27ae8,
1182                 0x27af0, 0x27af0,
1183                 0x27af8, 0x27c18,
1184                 0x27c20, 0x27c20,
1185                 0x27c28, 0x27c30,
1186                 0x27c38, 0x27c38,
1187                 0x27c80, 0x27c98,
1188                 0x27ca0, 0x27ca8,
1189                 0x27cb0, 0x27cc8,
1190                 0x27cd0, 0x27cd4,
1191                 0x27ce0, 0x27ce8,
1192                 0x27cf0, 0x27cf0,
1193                 0x27cf8, 0x27d7c,
1194                 0x27e00, 0x27e04,
1195         };
1196
1197         static const unsigned int t5_reg_ranges[] = {
1198                 0x1008, 0x10c0,
1199                 0x10cc, 0x10f8,
1200                 0x1100, 0x1100,
1201                 0x110c, 0x1148,
1202                 0x1180, 0x1184,
1203                 0x1190, 0x1194,
1204                 0x11a0, 0x11a4,
1205                 0x11b0, 0x11b4,
1206                 0x11fc, 0x123c,
1207                 0x1280, 0x173c,
1208                 0x1800, 0x18fc,
1209                 0x3000, 0x3028,
1210                 0x3060, 0x30b0,
1211                 0x30b8, 0x30d8,
1212                 0x30e0, 0x30fc,
1213                 0x3140, 0x357c,
1214                 0x35a8, 0x35cc,
1215                 0x35ec, 0x35ec,
1216                 0x3600, 0x5624,
1217                 0x56cc, 0x56ec,
1218                 0x56f4, 0x5720,
1219                 0x5728, 0x575c,
1220                 0x580c, 0x5814,
1221                 0x5890, 0x589c,
1222                 0x58a4, 0x58ac,
1223                 0x58b8, 0x58bc,
1224                 0x5940, 0x59c8,
1225                 0x59d0, 0x59dc,
1226                 0x59fc, 0x5a18,
1227                 0x5a60, 0x5a70,
1228                 0x5a80, 0x5a9c,
1229                 0x5b94, 0x5bfc,
1230                 0x6000, 0x6020,
1231                 0x6028, 0x6040,
1232                 0x6058, 0x609c,
1233                 0x60a8, 0x614c,
1234                 0x7700, 0x7798,
1235                 0x77c0, 0x78fc,
1236                 0x7b00, 0x7b58,
1237                 0x7b60, 0x7b84,
1238                 0x7b8c, 0x7c54,
1239                 0x7d00, 0x7d38,
1240                 0x7d40, 0x7d80,
1241                 0x7d8c, 0x7ddc,
1242                 0x7de4, 0x7e04,
1243                 0x7e10, 0x7e1c,
1244                 0x7e24, 0x7e38,
1245                 0x7e40, 0x7e44,
1246                 0x7e4c, 0x7e78,
1247                 0x7e80, 0x7edc,
1248                 0x7ee8, 0x7efc,
1249                 0x8dc0, 0x8de0,
1250                 0x8df8, 0x8e04,
1251                 0x8e10, 0x8e84,
1252                 0x8ea0, 0x8f84,
1253                 0x8fc0, 0x9058,
1254                 0x9060, 0x9060,
1255                 0x9068, 0x90f8,
1256                 0x9400, 0x9408,
1257                 0x9410, 0x9470,
1258                 0x9600, 0x9600,
1259                 0x9608, 0x9638,
1260                 0x9640, 0x96f4,
1261                 0x9800, 0x9808,
1262                 0x9820, 0x983c,
1263                 0x9850, 0x9864,
1264                 0x9c00, 0x9c6c,
1265                 0x9c80, 0x9cec,
1266                 0x9d00, 0x9d6c,
1267                 0x9d80, 0x9dec,
1268                 0x9e00, 0x9e6c,
1269                 0x9e80, 0x9eec,
1270                 0x9f00, 0x9f6c,
1271                 0x9f80, 0xa020,
1272                 0xd004, 0xd004,
1273                 0xd010, 0xd03c,
1274                 0xdfc0, 0xdfe0,
1275                 0xe000, 0x1106c,
1276                 0x11074, 0x11088,
1277                 0x1109c, 0x1117c,
1278                 0x11190, 0x11204,
1279                 0x19040, 0x1906c,
1280                 0x19078, 0x19080,
1281                 0x1908c, 0x190e8,
1282                 0x190f0, 0x190f8,
1283                 0x19100, 0x19110,
1284                 0x19120, 0x19124,
1285                 0x19150, 0x19194,
1286                 0x1919c, 0x191b0,
1287                 0x191d0, 0x191e8,
1288                 0x19238, 0x19290,
1289                 0x193f8, 0x19428,
1290                 0x19430, 0x19444,
1291                 0x1944c, 0x1946c,
1292                 0x19474, 0x19474,
1293                 0x19490, 0x194cc,
1294                 0x194f0, 0x194f8,
1295                 0x19c00, 0x19c08,
1296                 0x19c10, 0x19c60,
1297                 0x19c94, 0x19ce4,
1298                 0x19cf0, 0x19d40,
1299                 0x19d50, 0x19d94,
1300                 0x19da0, 0x19de8,
1301                 0x19df0, 0x19e10,
1302                 0x19e50, 0x19e90,
1303                 0x19ea0, 0x19f24,
1304                 0x19f34, 0x19f34,
1305                 0x19f40, 0x19f50,
1306                 0x19f90, 0x19fb4,
1307                 0x19fc4, 0x19fe4,
1308                 0x1a000, 0x1a004,
1309                 0x1a010, 0x1a06c,
1310                 0x1a0b0, 0x1a0e4,
1311                 0x1a0ec, 0x1a0f8,
1312                 0x1a100, 0x1a108,
1313                 0x1a114, 0x1a120,
1314                 0x1a128, 0x1a130,
1315                 0x1a138, 0x1a138,
1316                 0x1a190, 0x1a1c4,
1317                 0x1a1fc, 0x1a1fc,
1318                 0x1e008, 0x1e00c,
1319                 0x1e040, 0x1e044,
1320                 0x1e04c, 0x1e04c,
1321                 0x1e284, 0x1e290,
1322                 0x1e2c0, 0x1e2c0,
1323                 0x1e2e0, 0x1e2e0,
1324                 0x1e300, 0x1e384,
1325                 0x1e3c0, 0x1e3c8,
1326                 0x1e408, 0x1e40c,
1327                 0x1e440, 0x1e444,
1328                 0x1e44c, 0x1e44c,
1329                 0x1e684, 0x1e690,
1330                 0x1e6c0, 0x1e6c0,
1331                 0x1e6e0, 0x1e6e0,
1332                 0x1e700, 0x1e784,
1333                 0x1e7c0, 0x1e7c8,
1334                 0x1e808, 0x1e80c,
1335                 0x1e840, 0x1e844,
1336                 0x1e84c, 0x1e84c,
1337                 0x1ea84, 0x1ea90,
1338                 0x1eac0, 0x1eac0,
1339                 0x1eae0, 0x1eae0,
1340                 0x1eb00, 0x1eb84,
1341                 0x1ebc0, 0x1ebc8,
1342                 0x1ec08, 0x1ec0c,
1343                 0x1ec40, 0x1ec44,
1344                 0x1ec4c, 0x1ec4c,
1345                 0x1ee84, 0x1ee90,
1346                 0x1eec0, 0x1eec0,
1347                 0x1eee0, 0x1eee0,
1348                 0x1ef00, 0x1ef84,
1349                 0x1efc0, 0x1efc8,
1350                 0x1f008, 0x1f00c,
1351                 0x1f040, 0x1f044,
1352                 0x1f04c, 0x1f04c,
1353                 0x1f284, 0x1f290,
1354                 0x1f2c0, 0x1f2c0,
1355                 0x1f2e0, 0x1f2e0,
1356                 0x1f300, 0x1f384,
1357                 0x1f3c0, 0x1f3c8,
1358                 0x1f408, 0x1f40c,
1359                 0x1f440, 0x1f444,
1360                 0x1f44c, 0x1f44c,
1361                 0x1f684, 0x1f690,
1362                 0x1f6c0, 0x1f6c0,
1363                 0x1f6e0, 0x1f6e0,
1364                 0x1f700, 0x1f784,
1365                 0x1f7c0, 0x1f7c8,
1366                 0x1f808, 0x1f80c,
1367                 0x1f840, 0x1f844,
1368                 0x1f84c, 0x1f84c,
1369                 0x1fa84, 0x1fa90,
1370                 0x1fac0, 0x1fac0,
1371                 0x1fae0, 0x1fae0,
1372                 0x1fb00, 0x1fb84,
1373                 0x1fbc0, 0x1fbc8,
1374                 0x1fc08, 0x1fc0c,
1375                 0x1fc40, 0x1fc44,
1376                 0x1fc4c, 0x1fc4c,
1377                 0x1fe84, 0x1fe90,
1378                 0x1fec0, 0x1fec0,
1379                 0x1fee0, 0x1fee0,
1380                 0x1ff00, 0x1ff84,
1381                 0x1ffc0, 0x1ffc8,
1382                 0x30000, 0x30030,
1383                 0x30038, 0x30038,
1384                 0x30040, 0x30040,
1385                 0x30100, 0x30144,
1386                 0x30190, 0x301a0,
1387                 0x301a8, 0x301b8,
1388                 0x301c4, 0x301c8,
1389                 0x301d0, 0x301d0,
1390                 0x30200, 0x30318,
1391                 0x30400, 0x304b4,
1392                 0x304c0, 0x3052c,
1393                 0x30540, 0x3061c,
1394                 0x30800, 0x30828,
1395                 0x30834, 0x30834,
1396                 0x308c0, 0x30908,
1397                 0x30910, 0x309ac,
1398                 0x30a00, 0x30a14,
1399                 0x30a1c, 0x30a2c,
1400                 0x30a44, 0x30a50,
1401                 0x30a74, 0x30a74,
1402                 0x30a7c, 0x30afc,
1403                 0x30b08, 0x30c24,
1404                 0x30d00, 0x30d00,
1405                 0x30d08, 0x30d14,
1406                 0x30d1c, 0x30d20,
1407                 0x30d3c, 0x30d3c,
1408                 0x30d48, 0x30d50,
1409                 0x31200, 0x3120c,
1410                 0x31220, 0x31220,
1411                 0x31240, 0x31240,
1412                 0x31600, 0x3160c,
1413                 0x31a00, 0x31a1c,
1414                 0x31e00, 0x31e20,
1415                 0x31e38, 0x31e3c,
1416                 0x31e80, 0x31e80,
1417                 0x31e88, 0x31ea8,
1418                 0x31eb0, 0x31eb4,
1419                 0x31ec8, 0x31ed4,
1420                 0x31fb8, 0x32004,
1421                 0x32200, 0x32200,
1422                 0x32208, 0x32240,
1423                 0x32248, 0x32280,
1424                 0x32288, 0x322c0,
1425                 0x322c8, 0x322fc,
1426                 0x32600, 0x32630,
1427                 0x32a00, 0x32abc,
1428                 0x32b00, 0x32b10,
1429                 0x32b20, 0x32b30,
1430                 0x32b40, 0x32b50,
1431                 0x32b60, 0x32b70,
1432                 0x33000, 0x33028,
1433                 0x33030, 0x33048,
1434                 0x33060, 0x33068,
1435                 0x33070, 0x3309c,
1436                 0x330f0, 0x33128,
1437                 0x33130, 0x33148,
1438                 0x33160, 0x33168,
1439                 0x33170, 0x3319c,
1440                 0x331f0, 0x33238,
1441                 0x33240, 0x33240,
1442                 0x33248, 0x33250,
1443                 0x3325c, 0x33264,
1444                 0x33270, 0x332b8,
1445                 0x332c0, 0x332e4,
1446                 0x332f8, 0x33338,
1447                 0x33340, 0x33340,
1448                 0x33348, 0x33350,
1449                 0x3335c, 0x33364,
1450                 0x33370, 0x333b8,
1451                 0x333c0, 0x333e4,
1452                 0x333f8, 0x33428,
1453                 0x33430, 0x33448,
1454                 0x33460, 0x33468,
1455                 0x33470, 0x3349c,
1456                 0x334f0, 0x33528,
1457                 0x33530, 0x33548,
1458                 0x33560, 0x33568,
1459                 0x33570, 0x3359c,
1460                 0x335f0, 0x33638,
1461                 0x33640, 0x33640,
1462                 0x33648, 0x33650,
1463                 0x3365c, 0x33664,
1464                 0x33670, 0x336b8,
1465                 0x336c0, 0x336e4,
1466                 0x336f8, 0x33738,
1467                 0x33740, 0x33740,
1468                 0x33748, 0x33750,
1469                 0x3375c, 0x33764,
1470                 0x33770, 0x337b8,
1471                 0x337c0, 0x337e4,
1472                 0x337f8, 0x337fc,
1473                 0x33814, 0x33814,
1474                 0x3382c, 0x3382c,
1475                 0x33880, 0x3388c,
1476                 0x338e8, 0x338ec,
1477                 0x33900, 0x33928,
1478                 0x33930, 0x33948,
1479                 0x33960, 0x33968,
1480                 0x33970, 0x3399c,
1481                 0x339f0, 0x33a38,
1482                 0x33a40, 0x33a40,
1483                 0x33a48, 0x33a50,
1484                 0x33a5c, 0x33a64,
1485                 0x33a70, 0x33ab8,
1486                 0x33ac0, 0x33ae4,
1487                 0x33af8, 0x33b10,
1488                 0x33b28, 0x33b28,
1489                 0x33b3c, 0x33b50,
1490                 0x33bf0, 0x33c10,
1491                 0x33c28, 0x33c28,
1492                 0x33c3c, 0x33c50,
1493                 0x33cf0, 0x33cfc,
1494                 0x34000, 0x34030,
1495                 0x34038, 0x34038,
1496                 0x34040, 0x34040,
1497                 0x34100, 0x34144,
1498                 0x34190, 0x341a0,
1499                 0x341a8, 0x341b8,
1500                 0x341c4, 0x341c8,
1501                 0x341d0, 0x341d0,
1502                 0x34200, 0x34318,
1503                 0x34400, 0x344b4,
1504                 0x344c0, 0x3452c,
1505                 0x34540, 0x3461c,
1506                 0x34800, 0x34828,
1507                 0x34834, 0x34834,
1508                 0x348c0, 0x34908,
1509                 0x34910, 0x349ac,
1510                 0x34a00, 0x34a14,
1511                 0x34a1c, 0x34a2c,
1512                 0x34a44, 0x34a50,
1513                 0x34a74, 0x34a74,
1514                 0x34a7c, 0x34afc,
1515                 0x34b08, 0x34c24,
1516                 0x34d00, 0x34d00,
1517                 0x34d08, 0x34d14,
1518                 0x34d1c, 0x34d20,
1519                 0x34d3c, 0x34d3c,
1520                 0x34d48, 0x34d50,
1521                 0x35200, 0x3520c,
1522                 0x35220, 0x35220,
1523                 0x35240, 0x35240,
1524                 0x35600, 0x3560c,
1525                 0x35a00, 0x35a1c,
1526                 0x35e00, 0x35e20,
1527                 0x35e38, 0x35e3c,
1528                 0x35e80, 0x35e80,
1529                 0x35e88, 0x35ea8,
1530                 0x35eb0, 0x35eb4,
1531                 0x35ec8, 0x35ed4,
1532                 0x35fb8, 0x36004,
1533                 0x36200, 0x36200,
1534                 0x36208, 0x36240,
1535                 0x36248, 0x36280,
1536                 0x36288, 0x362c0,
1537                 0x362c8, 0x362fc,
1538                 0x36600, 0x36630,
1539                 0x36a00, 0x36abc,
1540                 0x36b00, 0x36b10,
1541                 0x36b20, 0x36b30,
1542                 0x36b40, 0x36b50,
1543                 0x36b60, 0x36b70,
1544                 0x37000, 0x37028,
1545                 0x37030, 0x37048,
1546                 0x37060, 0x37068,
1547                 0x37070, 0x3709c,
1548                 0x370f0, 0x37128,
1549                 0x37130, 0x37148,
1550                 0x37160, 0x37168,
1551                 0x37170, 0x3719c,
1552                 0x371f0, 0x37238,
1553                 0x37240, 0x37240,
1554                 0x37248, 0x37250,
1555                 0x3725c, 0x37264,
1556                 0x37270, 0x372b8,
1557                 0x372c0, 0x372e4,
1558                 0x372f8, 0x37338,
1559                 0x37340, 0x37340,
1560                 0x37348, 0x37350,
1561                 0x3735c, 0x37364,
1562                 0x37370, 0x373b8,
1563                 0x373c0, 0x373e4,
1564                 0x373f8, 0x37428,
1565                 0x37430, 0x37448,
1566                 0x37460, 0x37468,
1567                 0x37470, 0x3749c,
1568                 0x374f0, 0x37528,
1569                 0x37530, 0x37548,
1570                 0x37560, 0x37568,
1571                 0x37570, 0x3759c,
1572                 0x375f0, 0x37638,
1573                 0x37640, 0x37640,
1574                 0x37648, 0x37650,
1575                 0x3765c, 0x37664,
1576                 0x37670, 0x376b8,
1577                 0x376c0, 0x376e4,
1578                 0x376f8, 0x37738,
1579                 0x37740, 0x37740,
1580                 0x37748, 0x37750,
1581                 0x3775c, 0x37764,
1582                 0x37770, 0x377b8,
1583                 0x377c0, 0x377e4,
1584                 0x377f8, 0x377fc,
1585                 0x37814, 0x37814,
1586                 0x3782c, 0x3782c,
1587                 0x37880, 0x3788c,
1588                 0x378e8, 0x378ec,
1589                 0x37900, 0x37928,
1590                 0x37930, 0x37948,
1591                 0x37960, 0x37968,
1592                 0x37970, 0x3799c,
1593                 0x379f0, 0x37a38,
1594                 0x37a40, 0x37a40,
1595                 0x37a48, 0x37a50,
1596                 0x37a5c, 0x37a64,
1597                 0x37a70, 0x37ab8,
1598                 0x37ac0, 0x37ae4,
1599                 0x37af8, 0x37b10,
1600                 0x37b28, 0x37b28,
1601                 0x37b3c, 0x37b50,
1602                 0x37bf0, 0x37c10,
1603                 0x37c28, 0x37c28,
1604                 0x37c3c, 0x37c50,
1605                 0x37cf0, 0x37cfc,
1606                 0x38000, 0x38030,
1607                 0x38038, 0x38038,
1608                 0x38040, 0x38040,
1609                 0x38100, 0x38144,
1610                 0x38190, 0x381a0,
1611                 0x381a8, 0x381b8,
1612                 0x381c4, 0x381c8,
1613                 0x381d0, 0x381d0,
1614                 0x38200, 0x38318,
1615                 0x38400, 0x384b4,
1616                 0x384c0, 0x3852c,
1617                 0x38540, 0x3861c,
1618                 0x38800, 0x38828,
1619                 0x38834, 0x38834,
1620                 0x388c0, 0x38908,
1621                 0x38910, 0x389ac,
1622                 0x38a00, 0x38a14,
1623                 0x38a1c, 0x38a2c,
1624                 0x38a44, 0x38a50,
1625                 0x38a74, 0x38a74,
1626                 0x38a7c, 0x38afc,
1627                 0x38b08, 0x38c24,
1628                 0x38d00, 0x38d00,
1629                 0x38d08, 0x38d14,
1630                 0x38d1c, 0x38d20,
1631                 0x38d3c, 0x38d3c,
1632                 0x38d48, 0x38d50,
1633                 0x39200, 0x3920c,
1634                 0x39220, 0x39220,
1635                 0x39240, 0x39240,
1636                 0x39600, 0x3960c,
1637                 0x39a00, 0x39a1c,
1638                 0x39e00, 0x39e20,
1639                 0x39e38, 0x39e3c,
1640                 0x39e80, 0x39e80,
1641                 0x39e88, 0x39ea8,
1642                 0x39eb0, 0x39eb4,
1643                 0x39ec8, 0x39ed4,
1644                 0x39fb8, 0x3a004,
1645                 0x3a200, 0x3a200,
1646                 0x3a208, 0x3a240,
1647                 0x3a248, 0x3a280,
1648                 0x3a288, 0x3a2c0,
1649                 0x3a2c8, 0x3a2fc,
1650                 0x3a600, 0x3a630,
1651                 0x3aa00, 0x3aabc,
1652                 0x3ab00, 0x3ab10,
1653                 0x3ab20, 0x3ab30,
1654                 0x3ab40, 0x3ab50,
1655                 0x3ab60, 0x3ab70,
1656                 0x3b000, 0x3b028,
1657                 0x3b030, 0x3b048,
1658                 0x3b060, 0x3b068,
1659                 0x3b070, 0x3b09c,
1660                 0x3b0f0, 0x3b128,
1661                 0x3b130, 0x3b148,
1662                 0x3b160, 0x3b168,
1663                 0x3b170, 0x3b19c,
1664                 0x3b1f0, 0x3b238,
1665                 0x3b240, 0x3b240,
1666                 0x3b248, 0x3b250,
1667                 0x3b25c, 0x3b264,
1668                 0x3b270, 0x3b2b8,
1669                 0x3b2c0, 0x3b2e4,
1670                 0x3b2f8, 0x3b338,
1671                 0x3b340, 0x3b340,
1672                 0x3b348, 0x3b350,
1673                 0x3b35c, 0x3b364,
1674                 0x3b370, 0x3b3b8,
1675                 0x3b3c0, 0x3b3e4,
1676                 0x3b3f8, 0x3b428,
1677                 0x3b430, 0x3b448,
1678                 0x3b460, 0x3b468,
1679                 0x3b470, 0x3b49c,
1680                 0x3b4f0, 0x3b528,
1681                 0x3b530, 0x3b548,
1682                 0x3b560, 0x3b568,
1683                 0x3b570, 0x3b59c,
1684                 0x3b5f0, 0x3b638,
1685                 0x3b640, 0x3b640,
1686                 0x3b648, 0x3b650,
1687                 0x3b65c, 0x3b664,
1688                 0x3b670, 0x3b6b8,
1689                 0x3b6c0, 0x3b6e4,
1690                 0x3b6f8, 0x3b738,
1691                 0x3b740, 0x3b740,
1692                 0x3b748, 0x3b750,
1693                 0x3b75c, 0x3b764,
1694                 0x3b770, 0x3b7b8,
1695                 0x3b7c0, 0x3b7e4,
1696                 0x3b7f8, 0x3b7fc,
1697                 0x3b814, 0x3b814,
1698                 0x3b82c, 0x3b82c,
1699                 0x3b880, 0x3b88c,
1700                 0x3b8e8, 0x3b8ec,
1701                 0x3b900, 0x3b928,
1702                 0x3b930, 0x3b948,
1703                 0x3b960, 0x3b968,
1704                 0x3b970, 0x3b99c,
1705                 0x3b9f0, 0x3ba38,
1706                 0x3ba40, 0x3ba40,
1707                 0x3ba48, 0x3ba50,
1708                 0x3ba5c, 0x3ba64,
1709                 0x3ba70, 0x3bab8,
1710                 0x3bac0, 0x3bae4,
1711                 0x3baf8, 0x3bb10,
1712                 0x3bb28, 0x3bb28,
1713                 0x3bb3c, 0x3bb50,
1714                 0x3bbf0, 0x3bc10,
1715                 0x3bc28, 0x3bc28,
1716                 0x3bc3c, 0x3bc50,
1717                 0x3bcf0, 0x3bcfc,
1718                 0x3c000, 0x3c030,
1719                 0x3c038, 0x3c038,
1720                 0x3c040, 0x3c040,
1721                 0x3c100, 0x3c144,
1722                 0x3c190, 0x3c1a0,
1723                 0x3c1a8, 0x3c1b8,
1724                 0x3c1c4, 0x3c1c8,
1725                 0x3c1d0, 0x3c1d0,
1726                 0x3c200, 0x3c318,
1727                 0x3c400, 0x3c4b4,
1728                 0x3c4c0, 0x3c52c,
1729                 0x3c540, 0x3c61c,
1730                 0x3c800, 0x3c828,
1731                 0x3c834, 0x3c834,
1732                 0x3c8c0, 0x3c908,
1733                 0x3c910, 0x3c9ac,
1734                 0x3ca00, 0x3ca14,
1735                 0x3ca1c, 0x3ca2c,
1736                 0x3ca44, 0x3ca50,
1737                 0x3ca74, 0x3ca74,
1738                 0x3ca7c, 0x3cafc,
1739                 0x3cb08, 0x3cc24,
1740                 0x3cd00, 0x3cd00,
1741                 0x3cd08, 0x3cd14,
1742                 0x3cd1c, 0x3cd20,
1743                 0x3cd3c, 0x3cd3c,
1744                 0x3cd48, 0x3cd50,
1745                 0x3d200, 0x3d20c,
1746                 0x3d220, 0x3d220,
1747                 0x3d240, 0x3d240,
1748                 0x3d600, 0x3d60c,
1749                 0x3da00, 0x3da1c,
1750                 0x3de00, 0x3de20,
1751                 0x3de38, 0x3de3c,
1752                 0x3de80, 0x3de80,
1753                 0x3de88, 0x3dea8,
1754                 0x3deb0, 0x3deb4,
1755                 0x3dec8, 0x3ded4,
1756                 0x3dfb8, 0x3e004,
1757                 0x3e200, 0x3e200,
1758                 0x3e208, 0x3e240,
1759                 0x3e248, 0x3e280,
1760                 0x3e288, 0x3e2c0,
1761                 0x3e2c8, 0x3e2fc,
1762                 0x3e600, 0x3e630,
1763                 0x3ea00, 0x3eabc,
1764                 0x3eb00, 0x3eb10,
1765                 0x3eb20, 0x3eb30,
1766                 0x3eb40, 0x3eb50,
1767                 0x3eb60, 0x3eb70,
1768                 0x3f000, 0x3f028,
1769                 0x3f030, 0x3f048,
1770                 0x3f060, 0x3f068,
1771                 0x3f070, 0x3f09c,
1772                 0x3f0f0, 0x3f128,
1773                 0x3f130, 0x3f148,
1774                 0x3f160, 0x3f168,
1775                 0x3f170, 0x3f19c,
1776                 0x3f1f0, 0x3f238,
1777                 0x3f240, 0x3f240,
1778                 0x3f248, 0x3f250,
1779                 0x3f25c, 0x3f264,
1780                 0x3f270, 0x3f2b8,
1781                 0x3f2c0, 0x3f2e4,
1782                 0x3f2f8, 0x3f338,
1783                 0x3f340, 0x3f340,
1784                 0x3f348, 0x3f350,
1785                 0x3f35c, 0x3f364,
1786                 0x3f370, 0x3f3b8,
1787                 0x3f3c0, 0x3f3e4,
1788                 0x3f3f8, 0x3f428,
1789                 0x3f430, 0x3f448,
1790                 0x3f460, 0x3f468,
1791                 0x3f470, 0x3f49c,
1792                 0x3f4f0, 0x3f528,
1793                 0x3f530, 0x3f548,
1794                 0x3f560, 0x3f568,
1795                 0x3f570, 0x3f59c,
1796                 0x3f5f0, 0x3f638,
1797                 0x3f640, 0x3f640,
1798                 0x3f648, 0x3f650,
1799                 0x3f65c, 0x3f664,
1800                 0x3f670, 0x3f6b8,
1801                 0x3f6c0, 0x3f6e4,
1802                 0x3f6f8, 0x3f738,
1803                 0x3f740, 0x3f740,
1804                 0x3f748, 0x3f750,
1805                 0x3f75c, 0x3f764,
1806                 0x3f770, 0x3f7b8,
1807                 0x3f7c0, 0x3f7e4,
1808                 0x3f7f8, 0x3f7fc,
1809                 0x3f814, 0x3f814,
1810                 0x3f82c, 0x3f82c,
1811                 0x3f880, 0x3f88c,
1812                 0x3f8e8, 0x3f8ec,
1813                 0x3f900, 0x3f928,
1814                 0x3f930, 0x3f948,
1815                 0x3f960, 0x3f968,
1816                 0x3f970, 0x3f99c,
1817                 0x3f9f0, 0x3fa38,
1818                 0x3fa40, 0x3fa40,
1819                 0x3fa48, 0x3fa50,
1820                 0x3fa5c, 0x3fa64,
1821                 0x3fa70, 0x3fab8,
1822                 0x3fac0, 0x3fae4,
1823                 0x3faf8, 0x3fb10,
1824                 0x3fb28, 0x3fb28,
1825                 0x3fb3c, 0x3fb50,
1826                 0x3fbf0, 0x3fc10,
1827                 0x3fc28, 0x3fc28,
1828                 0x3fc3c, 0x3fc50,
1829                 0x3fcf0, 0x3fcfc,
1830                 0x40000, 0x4000c,
1831                 0x40040, 0x40050,
1832                 0x40060, 0x40068,
1833                 0x4007c, 0x4008c,
1834                 0x40094, 0x400b0,
1835                 0x400c0, 0x40144,
1836                 0x40180, 0x4018c,
1837                 0x40200, 0x40254,
1838                 0x40260, 0x40264,
1839                 0x40270, 0x40288,
1840                 0x40290, 0x40298,
1841                 0x402ac, 0x402c8,
1842                 0x402d0, 0x402e0,
1843                 0x402f0, 0x402f0,
1844                 0x40300, 0x4033c,
1845                 0x403f8, 0x403fc,
1846                 0x41304, 0x413c4,
1847                 0x41400, 0x4140c,
1848                 0x41414, 0x4141c,
1849                 0x41480, 0x414d0,
1850                 0x44000, 0x44054,
1851                 0x4405c, 0x44078,
1852                 0x440c0, 0x44174,
1853                 0x44180, 0x441ac,
1854                 0x441b4, 0x441b8,
1855                 0x441c0, 0x44254,
1856                 0x4425c, 0x44278,
1857                 0x442c0, 0x44374,
1858                 0x44380, 0x443ac,
1859                 0x443b4, 0x443b8,
1860                 0x443c0, 0x44454,
1861                 0x4445c, 0x44478,
1862                 0x444c0, 0x44574,
1863                 0x44580, 0x445ac,
1864                 0x445b4, 0x445b8,
1865                 0x445c0, 0x44654,
1866                 0x4465c, 0x44678,
1867                 0x446c0, 0x44774,
1868                 0x44780, 0x447ac,
1869                 0x447b4, 0x447b8,
1870                 0x447c0, 0x44854,
1871                 0x4485c, 0x44878,
1872                 0x448c0, 0x44974,
1873                 0x44980, 0x449ac,
1874                 0x449b4, 0x449b8,
1875                 0x449c0, 0x449fc,
1876                 0x45000, 0x45004,
1877                 0x45010, 0x45030,
1878                 0x45040, 0x45060,
1879                 0x45068, 0x45068,
1880                 0x45080, 0x45084,
1881                 0x450a0, 0x450b0,
1882                 0x45200, 0x45204,
1883                 0x45210, 0x45230,
1884                 0x45240, 0x45260,
1885                 0x45268, 0x45268,
1886                 0x45280, 0x45284,
1887                 0x452a0, 0x452b0,
1888                 0x460c0, 0x460e4,
1889                 0x47000, 0x4703c,
1890                 0x47044, 0x4708c,
1891                 0x47200, 0x47250,
1892                 0x47400, 0x47408,
1893                 0x47414, 0x47420,
1894                 0x47600, 0x47618,
1895                 0x47800, 0x47814,
1896                 0x48000, 0x4800c,
1897                 0x48040, 0x48050,
1898                 0x48060, 0x48068,
1899                 0x4807c, 0x4808c,
1900                 0x48094, 0x480b0,
1901                 0x480c0, 0x48144,
1902                 0x48180, 0x4818c,
1903                 0x48200, 0x48254,
1904                 0x48260, 0x48264,
1905                 0x48270, 0x48288,
1906                 0x48290, 0x48298,
1907                 0x482ac, 0x482c8,
1908                 0x482d0, 0x482e0,
1909                 0x482f0, 0x482f0,
1910                 0x48300, 0x4833c,
1911                 0x483f8, 0x483fc,
1912                 0x49304, 0x493c4,
1913                 0x49400, 0x4940c,
1914                 0x49414, 0x4941c,
1915                 0x49480, 0x494d0,
1916                 0x4c000, 0x4c054,
1917                 0x4c05c, 0x4c078,
1918                 0x4c0c0, 0x4c174,
1919                 0x4c180, 0x4c1ac,
1920                 0x4c1b4, 0x4c1b8,
1921                 0x4c1c0, 0x4c254,
1922                 0x4c25c, 0x4c278,
1923                 0x4c2c0, 0x4c374,
1924                 0x4c380, 0x4c3ac,
1925                 0x4c3b4, 0x4c3b8,
1926                 0x4c3c0, 0x4c454,
1927                 0x4c45c, 0x4c478,
1928                 0x4c4c0, 0x4c574,
1929                 0x4c580, 0x4c5ac,
1930                 0x4c5b4, 0x4c5b8,
1931                 0x4c5c0, 0x4c654,
1932                 0x4c65c, 0x4c678,
1933                 0x4c6c0, 0x4c774,
1934                 0x4c780, 0x4c7ac,
1935                 0x4c7b4, 0x4c7b8,
1936                 0x4c7c0, 0x4c854,
1937                 0x4c85c, 0x4c878,
1938                 0x4c8c0, 0x4c974,
1939                 0x4c980, 0x4c9ac,
1940                 0x4c9b4, 0x4c9b8,
1941                 0x4c9c0, 0x4c9fc,
1942                 0x4d000, 0x4d004,
1943                 0x4d010, 0x4d030,
1944                 0x4d040, 0x4d060,
1945                 0x4d068, 0x4d068,
1946                 0x4d080, 0x4d084,
1947                 0x4d0a0, 0x4d0b0,
1948                 0x4d200, 0x4d204,
1949                 0x4d210, 0x4d230,
1950                 0x4d240, 0x4d260,
1951                 0x4d268, 0x4d268,
1952                 0x4d280, 0x4d284,
1953                 0x4d2a0, 0x4d2b0,
1954                 0x4e0c0, 0x4e0e4,
1955                 0x4f000, 0x4f03c,
1956                 0x4f044, 0x4f08c,
1957                 0x4f200, 0x4f250,
1958                 0x4f400, 0x4f408,
1959                 0x4f414, 0x4f420,
1960                 0x4f600, 0x4f618,
1961                 0x4f800, 0x4f814,
1962                 0x50000, 0x50084,
1963                 0x50090, 0x500cc,
1964                 0x50400, 0x50400,
1965                 0x50800, 0x50884,
1966                 0x50890, 0x508cc,
1967                 0x50c00, 0x50c00,
1968                 0x51000, 0x5101c,
1969                 0x51300, 0x51308,
1970         };
1971
1972         static const unsigned int t6_reg_ranges[] = {
1973                 0x1008, 0x101c,
1974                 0x1024, 0x10a8,
1975                 0x10b4, 0x10f8,
1976                 0x1100, 0x1114,
1977                 0x111c, 0x112c,
1978                 0x1138, 0x113c,
1979                 0x1144, 0x114c,
1980                 0x1180, 0x1184,
1981                 0x1190, 0x1194,
1982                 0x11a0, 0x11a4,
1983                 0x11b0, 0x11b4,
1984                 0x11fc, 0x1258,
1985                 0x1280, 0x12d4,
1986                 0x12d9, 0x12d9,
1987                 0x12de, 0x12de,
1988                 0x12e3, 0x12e3,
1989                 0x12e8, 0x133c,
1990                 0x1800, 0x18fc,
1991                 0x3000, 0x302c,
1992                 0x3060, 0x30b0,
1993                 0x30b8, 0x30d8,
1994                 0x30e0, 0x30fc,
1995                 0x3140, 0x357c,
1996                 0x35a8, 0x35cc,
1997                 0x35ec, 0x35ec,
1998                 0x3600, 0x5624,
1999                 0x56cc, 0x56ec,
2000                 0x56f4, 0x5720,
2001                 0x5728, 0x575c,
2002                 0x580c, 0x5814,
2003                 0x5890, 0x589c,
2004                 0x58a4, 0x58ac,
2005                 0x58b8, 0x58bc,
2006                 0x5940, 0x595c,
2007                 0x5980, 0x598c,
2008                 0x59b0, 0x59c8,
2009                 0x59d0, 0x59dc,
2010                 0x59fc, 0x5a18,
2011                 0x5a60, 0x5a6c,
2012                 0x5a80, 0x5a8c,
2013                 0x5a94, 0x5a9c,
2014                 0x5b94, 0x5bfc,
2015                 0x5c10, 0x5e48,
2016                 0x5e50, 0x5e94,
2017                 0x5ea0, 0x5eb0,
2018                 0x5ec0, 0x5ec0,
2019                 0x5ec8, 0x5ed0,
2020                 0x6000, 0x6020,
2021                 0x6028, 0x6040,
2022                 0x6058, 0x609c,
2023                 0x60a8, 0x619c,
2024                 0x7700, 0x7798,
2025                 0x77c0, 0x7880,
2026                 0x78cc, 0x78fc,
2027                 0x7b00, 0x7b58,
2028                 0x7b60, 0x7b84,
2029                 0x7b8c, 0x7c54,
2030                 0x7d00, 0x7d38,
2031                 0x7d40, 0x7d84,
2032                 0x7d8c, 0x7ddc,
2033                 0x7de4, 0x7e04,
2034                 0x7e10, 0x7e1c,
2035                 0x7e24, 0x7e38,
2036                 0x7e40, 0x7e44,
2037                 0x7e4c, 0x7e78,
2038                 0x7e80, 0x7edc,
2039                 0x7ee8, 0x7efc,
2040                 0x8dc0, 0x8de4,
2041                 0x8df8, 0x8e04,
2042                 0x8e10, 0x8e84,
2043                 0x8ea0, 0x8f88,
2044                 0x8fb8, 0x9058,
2045                 0x9060, 0x9060,
2046                 0x9068, 0x90f8,
2047                 0x9100, 0x9124,
2048                 0x9400, 0x9470,
2049                 0x9600, 0x9600,
2050                 0x9608, 0x9638,
2051                 0x9640, 0x9704,
2052                 0x9710, 0x971c,
2053                 0x9800, 0x9808,
2054                 0x9820, 0x983c,
2055                 0x9850, 0x9864,
2056                 0x9c00, 0x9c6c,
2057                 0x9c80, 0x9cec,
2058                 0x9d00, 0x9d6c,
2059                 0x9d80, 0x9dec,
2060                 0x9e00, 0x9e6c,
2061                 0x9e80, 0x9eec,
2062                 0x9f00, 0x9f6c,
2063                 0x9f80, 0xa020,
2064                 0xd004, 0xd03c,
2065                 0xd100, 0xd118,
2066                 0xd200, 0xd214,
2067                 0xd220, 0xd234,
2068                 0xd240, 0xd254,
2069                 0xd260, 0xd274,
2070                 0xd280, 0xd294,
2071                 0xd2a0, 0xd2b4,
2072                 0xd2c0, 0xd2d4,
2073                 0xd2e0, 0xd2f4,
2074                 0xd300, 0xd31c,
2075                 0xdfc0, 0xdfe0,
2076                 0xe000, 0xf008,
2077                 0x11000, 0x11014,
2078                 0x11048, 0x1106c,
2079                 0x11074, 0x11088,
2080                 0x11098, 0x11120,
2081                 0x1112c, 0x1117c,
2082                 0x11190, 0x112e0,
2083                 0x11300, 0x1130c,
2084                 0x12000, 0x1206c,
2085                 0x19040, 0x1906c,
2086                 0x19078, 0x19080,
2087                 0x1908c, 0x190e8,
2088                 0x190f0, 0x190f8,
2089                 0x19100, 0x19110,
2090                 0x19120, 0x19124,
2091                 0x19150, 0x19194,
2092                 0x1919c, 0x191b0,
2093                 0x191d0, 0x191e8,
2094                 0x19238, 0x19290,
2095                 0x192a4, 0x192b0,
2096                 0x192bc, 0x192bc,
2097                 0x19348, 0x1934c,
2098                 0x193f8, 0x19418,
2099                 0x19420, 0x19428,
2100                 0x19430, 0x19444,
2101                 0x1944c, 0x1946c,
2102                 0x19474, 0x19474,
2103                 0x19490, 0x194cc,
2104                 0x194f0, 0x194f8,
2105                 0x19c00, 0x19c48,
2106                 0x19c50, 0x19c80,
2107                 0x19c94, 0x19c98,
2108                 0x19ca0, 0x19cbc,
2109                 0x19ce4, 0x19ce4,
2110                 0x19cf0, 0x19cf8,
2111                 0x19d00, 0x19d28,
2112                 0x19d50, 0x19d78,
2113                 0x19d94, 0x19d98,
2114                 0x19da0, 0x19dc8,
2115                 0x19df0, 0x19e10,
2116                 0x19e50, 0x19e6c,
2117                 0x19ea0, 0x19ebc,
2118                 0x19ec4, 0x19ef4,
2119                 0x19f04, 0x19f2c,
2120                 0x19f34, 0x19f34,
2121                 0x19f40, 0x19f50,
2122                 0x19f90, 0x19fac,
2123                 0x19fc4, 0x19fc8,
2124                 0x19fd0, 0x19fe4,
2125                 0x1a000, 0x1a004,
2126                 0x1a010, 0x1a06c,
2127                 0x1a0b0, 0x1a0e4,
2128                 0x1a0ec, 0x1a0f8,
2129                 0x1a100, 0x1a108,
2130                 0x1a114, 0x1a120,
2131                 0x1a128, 0x1a130,
2132                 0x1a138, 0x1a138,
2133                 0x1a190, 0x1a1c4,
2134                 0x1a1fc, 0x1a1fc,
2135                 0x1e008, 0x1e00c,
2136                 0x1e040, 0x1e044,
2137                 0x1e04c, 0x1e04c,
2138                 0x1e284, 0x1e290,
2139                 0x1e2c0, 0x1e2c0,
2140                 0x1e2e0, 0x1e2e0,
2141                 0x1e300, 0x1e384,
2142                 0x1e3c0, 0x1e3c8,
2143                 0x1e408, 0x1e40c,
2144                 0x1e440, 0x1e444,
2145                 0x1e44c, 0x1e44c,
2146                 0x1e684, 0x1e690,
2147                 0x1e6c0, 0x1e6c0,
2148                 0x1e6e0, 0x1e6e0,
2149                 0x1e700, 0x1e784,
2150                 0x1e7c0, 0x1e7c8,
2151                 0x1e808, 0x1e80c,
2152                 0x1e840, 0x1e844,
2153                 0x1e84c, 0x1e84c,
2154                 0x1ea84, 0x1ea90,
2155                 0x1eac0, 0x1eac0,
2156                 0x1eae0, 0x1eae0,
2157                 0x1eb00, 0x1eb84,
2158                 0x1ebc0, 0x1ebc8,
2159                 0x1ec08, 0x1ec0c,
2160                 0x1ec40, 0x1ec44,
2161                 0x1ec4c, 0x1ec4c,
2162                 0x1ee84, 0x1ee90,
2163                 0x1eec0, 0x1eec0,
2164                 0x1eee0, 0x1eee0,
2165                 0x1ef00, 0x1ef84,
2166                 0x1efc0, 0x1efc8,
2167                 0x1f008, 0x1f00c,
2168                 0x1f040, 0x1f044,
2169                 0x1f04c, 0x1f04c,
2170                 0x1f284, 0x1f290,
2171                 0x1f2c0, 0x1f2c0,
2172                 0x1f2e0, 0x1f2e0,
2173                 0x1f300, 0x1f384,
2174                 0x1f3c0, 0x1f3c8,
2175                 0x1f408, 0x1f40c,
2176                 0x1f440, 0x1f444,
2177                 0x1f44c, 0x1f44c,
2178                 0x1f684, 0x1f690,
2179                 0x1f6c0, 0x1f6c0,
2180                 0x1f6e0, 0x1f6e0,
2181                 0x1f700, 0x1f784,
2182                 0x1f7c0, 0x1f7c8,
2183                 0x1f808, 0x1f80c,
2184                 0x1f840, 0x1f844,
2185                 0x1f84c, 0x1f84c,
2186                 0x1fa84, 0x1fa90,
2187                 0x1fac0, 0x1fac0,
2188                 0x1fae0, 0x1fae0,
2189                 0x1fb00, 0x1fb84,
2190                 0x1fbc0, 0x1fbc8,
2191                 0x1fc08, 0x1fc0c,
2192                 0x1fc40, 0x1fc44,
2193                 0x1fc4c, 0x1fc4c,
2194                 0x1fe84, 0x1fe90,
2195                 0x1fec0, 0x1fec0,
2196                 0x1fee0, 0x1fee0,
2197                 0x1ff00, 0x1ff84,
2198                 0x1ffc0, 0x1ffc8,
2199                 0x30000, 0x30030,
2200                 0x30038, 0x30038,
2201                 0x30040, 0x30040,
2202                 0x30048, 0x30048,
2203                 0x30050, 0x30050,
2204                 0x3005c, 0x30060,
2205                 0x30068, 0x30068,
2206                 0x30070, 0x30070,
2207                 0x30100, 0x30168,
2208                 0x30190, 0x301a0,
2209                 0x301a8, 0x301b8,
2210                 0x301c4, 0x301c8,
2211                 0x301d0, 0x301d0,
2212                 0x30200, 0x30320,
2213                 0x30400, 0x304b4,
2214                 0x304c0, 0x3052c,
2215                 0x30540, 0x3061c,
2216                 0x30800, 0x308a0,
2217                 0x308c0, 0x30908,
2218                 0x30910, 0x309b8,
2219                 0x30a00, 0x30a04,
2220                 0x30a0c, 0x30a14,
2221                 0x30a1c, 0x30a2c,
2222                 0x30a44, 0x30a50,
2223                 0x30a74, 0x30a74,
2224                 0x30a7c, 0x30afc,
2225                 0x30b08, 0x30c24,
2226                 0x30d00, 0x30d14,
2227                 0x30d1c, 0x30d3c,
2228                 0x30d44, 0x30d4c,
2229                 0x30d54, 0x30d74,
2230                 0x30d7c, 0x30d7c,
2231                 0x30de0, 0x30de0,
2232                 0x30e00, 0x30ed4,
2233                 0x30f00, 0x30fa4,
2234                 0x30fc0, 0x30fc4,
2235                 0x31000, 0x31004,
2236                 0x31080, 0x310fc,
2237                 0x31208, 0x31220,
2238                 0x3123c, 0x31254,
2239                 0x31300, 0x31300,
2240                 0x31308, 0x3131c,
2241                 0x31338, 0x3133c,
2242                 0x31380, 0x31380,
2243                 0x31388, 0x313a8,
2244                 0x313b4, 0x313b4,
2245                 0x31400, 0x31420,
2246                 0x31438, 0x3143c,
2247                 0x31480, 0x31480,
2248                 0x314a8, 0x314a8,
2249                 0x314b0, 0x314b4,
2250                 0x314c8, 0x314d4,
2251                 0x31a40, 0x31a4c,
2252                 0x31af0, 0x31b20,
2253                 0x31b38, 0x31b3c,
2254                 0x31b80, 0x31b80,
2255                 0x31ba8, 0x31ba8,
2256                 0x31bb0, 0x31bb4,
2257                 0x31bc8, 0x31bd4,
2258                 0x32140, 0x3218c,
2259                 0x321f0, 0x321f4,
2260                 0x32200, 0x32200,
2261                 0x32218, 0x32218,
2262                 0x32400, 0x32400,
2263                 0x32408, 0x3241c,
2264                 0x32618, 0x32620,
2265                 0x32664, 0x32664,
2266                 0x326a8, 0x326a8,
2267                 0x326ec, 0x326ec,
2268                 0x32a00, 0x32abc,
2269                 0x32b00, 0x32b38,
2270                 0x32b40, 0x32b58,
2271                 0x32b60, 0x32b78,
2272                 0x32c00, 0x32c00,
2273                 0x32c08, 0x32c3c,
2274                 0x32e00, 0x32e2c,
2275                 0x32f00, 0x32f2c,
2276                 0x33000, 0x3302c,
2277                 0x33034, 0x33050,
2278                 0x33058, 0x33058,
2279                 0x33060, 0x3308c,
2280                 0x3309c, 0x330ac,
2281                 0x330c0, 0x330c0,
2282                 0x330c8, 0x330d0,
2283                 0x330d8, 0x330e0,
2284                 0x330ec, 0x3312c,
2285                 0x33134, 0x33150,
2286                 0x33158, 0x33158,
2287                 0x33160, 0x3318c,
2288                 0x3319c, 0x331ac,
2289                 0x331c0, 0x331c0,
2290                 0x331c8, 0x331d0,
2291                 0x331d8, 0x331e0,
2292                 0x331ec, 0x33290,
2293                 0x33298, 0x332c4,
2294                 0x332e4, 0x33390,
2295                 0x33398, 0x333c4,
2296                 0x333e4, 0x3342c,
2297                 0x33434, 0x33450,
2298                 0x33458, 0x33458,
2299                 0x33460, 0x3348c,
2300                 0x3349c, 0x334ac,
2301                 0x334c0, 0x334c0,
2302                 0x334c8, 0x334d0,
2303                 0x334d8, 0x334e0,
2304                 0x334ec, 0x3352c,
2305                 0x33534, 0x33550,
2306                 0x33558, 0x33558,
2307                 0x33560, 0x3358c,
2308                 0x3359c, 0x335ac,
2309                 0x335c0, 0x335c0,
2310                 0x335c8, 0x335d0,
2311                 0x335d8, 0x335e0,
2312                 0x335ec, 0x33690,
2313                 0x33698, 0x336c4,
2314                 0x336e4, 0x33790,
2315                 0x33798, 0x337c4,
2316                 0x337e4, 0x337fc,
2317                 0x33814, 0x33814,
2318                 0x33854, 0x33868,
2319                 0x33880, 0x3388c,
2320                 0x338c0, 0x338d0,
2321                 0x338e8, 0x338ec,
2322                 0x33900, 0x3392c,
2323                 0x33934, 0x33950,
2324                 0x33958, 0x33958,
2325                 0x33960, 0x3398c,
2326                 0x3399c, 0x339ac,
2327                 0x339c0, 0x339c0,
2328                 0x339c8, 0x339d0,
2329                 0x339d8, 0x339e0,
2330                 0x339ec, 0x33a90,
2331                 0x33a98, 0x33ac4,
2332                 0x33ae4, 0x33b10,
2333                 0x33b24, 0x33b28,
2334                 0x33b38, 0x33b50,
2335                 0x33bf0, 0x33c10,
2336                 0x33c24, 0x33c28,
2337                 0x33c38, 0x33c50,
2338                 0x33cf0, 0x33cfc,
2339                 0x34000, 0x34030,
2340                 0x34038, 0x34038,
2341                 0x34040, 0x34040,
2342                 0x34048, 0x34048,
2343                 0x34050, 0x34050,
2344                 0x3405c, 0x34060,
2345                 0x34068, 0x34068,
2346                 0x34070, 0x34070,
2347                 0x34100, 0x34168,
2348                 0x34190, 0x341a0,
2349                 0x341a8, 0x341b8,
2350                 0x341c4, 0x341c8,
2351                 0x341d0, 0x341d0,
2352                 0x34200, 0x34320,
2353                 0x34400, 0x344b4,
2354                 0x344c0, 0x3452c,
2355                 0x34540, 0x3461c,
2356                 0x34800, 0x348a0,
2357                 0x348c0, 0x34908,
2358                 0x34910, 0x349b8,
2359                 0x34a00, 0x34a04,
2360                 0x34a0c, 0x34a14,
2361                 0x34a1c, 0x34a2c,
2362                 0x34a44, 0x34a50,
2363                 0x34a74, 0x34a74,
2364                 0x34a7c, 0x34afc,
2365                 0x34b08, 0x34c24,
2366                 0x34d00, 0x34d14,
2367                 0x34d1c, 0x34d3c,
2368                 0x34d44, 0x34d4c,
2369                 0x34d54, 0x34d74,
2370                 0x34d7c, 0x34d7c,
2371                 0x34de0, 0x34de0,
2372                 0x34e00, 0x34ed4,
2373                 0x34f00, 0x34fa4,
2374                 0x34fc0, 0x34fc4,
2375                 0x35000, 0x35004,
2376                 0x35080, 0x350fc,
2377                 0x35208, 0x35220,
2378                 0x3523c, 0x35254,
2379                 0x35300, 0x35300,
2380                 0x35308, 0x3531c,
2381                 0x35338, 0x3533c,
2382                 0x35380, 0x35380,
2383                 0x35388, 0x353a8,
2384                 0x353b4, 0x353b4,
2385                 0x35400, 0x35420,
2386                 0x35438, 0x3543c,
2387                 0x35480, 0x35480,
2388                 0x354a8, 0x354a8,
2389                 0x354b0, 0x354b4,
2390                 0x354c8, 0x354d4,
2391                 0x35a40, 0x35a4c,
2392                 0x35af0, 0x35b20,
2393                 0x35b38, 0x35b3c,
2394                 0x35b80, 0x35b80,
2395                 0x35ba8, 0x35ba8,
2396                 0x35bb0, 0x35bb4,
2397                 0x35bc8, 0x35bd4,
2398                 0x36140, 0x3618c,
2399                 0x361f0, 0x361f4,
2400                 0x36200, 0x36200,
2401                 0x36218, 0x36218,
2402                 0x36400, 0x36400,
2403                 0x36408, 0x3641c,
2404                 0x36618, 0x36620,
2405                 0x36664, 0x36664,
2406                 0x366a8, 0x366a8,
2407                 0x366ec, 0x366ec,
2408                 0x36a00, 0x36abc,
2409                 0x36b00, 0x36b38,
2410                 0x36b40, 0x36b58,
2411                 0x36b60, 0x36b78,
2412                 0x36c00, 0x36c00,
2413                 0x36c08, 0x36c3c,
2414                 0x36e00, 0x36e2c,
2415                 0x36f00, 0x36f2c,
2416                 0x37000, 0x3702c,
2417                 0x37034, 0x37050,
2418                 0x37058, 0x37058,
2419                 0x37060, 0x3708c,
2420                 0x3709c, 0x370ac,
2421                 0x370c0, 0x370c0,
2422                 0x370c8, 0x370d0,
2423                 0x370d8, 0x370e0,
2424                 0x370ec, 0x3712c,
2425                 0x37134, 0x37150,
2426                 0x37158, 0x37158,
2427                 0x37160, 0x3718c,
2428                 0x3719c, 0x371ac,
2429                 0x371c0, 0x371c0,
2430                 0x371c8, 0x371d0,
2431                 0x371d8, 0x371e0,
2432                 0x371ec, 0x37290,
2433                 0x37298, 0x372c4,
2434                 0x372e4, 0x37390,
2435                 0x37398, 0x373c4,
2436                 0x373e4, 0x3742c,
2437                 0x37434, 0x37450,
2438                 0x37458, 0x37458,
2439                 0x37460, 0x3748c,
2440                 0x3749c, 0x374ac,
2441                 0x374c0, 0x374c0,
2442                 0x374c8, 0x374d0,
2443                 0x374d8, 0x374e0,
2444                 0x374ec, 0x3752c,
2445                 0x37534, 0x37550,
2446                 0x37558, 0x37558,
2447                 0x37560, 0x3758c,
2448                 0x3759c, 0x375ac,
2449                 0x375c0, 0x375c0,
2450                 0x375c8, 0x375d0,
2451                 0x375d8, 0x375e0,
2452                 0x375ec, 0x37690,
2453                 0x37698, 0x376c4,
2454                 0x376e4, 0x37790,
2455                 0x37798, 0x377c4,
2456                 0x377e4, 0x377fc,
2457                 0x37814, 0x37814,
2458                 0x37854, 0x37868,
2459                 0x37880, 0x3788c,
2460                 0x378c0, 0x378d0,
2461                 0x378e8, 0x378ec,
2462                 0x37900, 0x3792c,
2463                 0x37934, 0x37950,
2464                 0x37958, 0x37958,
2465                 0x37960, 0x3798c,
2466                 0x3799c, 0x379ac,
2467                 0x379c0, 0x379c0,
2468                 0x379c8, 0x379d0,
2469                 0x379d8, 0x379e0,
2470                 0x379ec, 0x37a90,
2471                 0x37a98, 0x37ac4,
2472                 0x37ae4, 0x37b10,
2473                 0x37b24, 0x37b28,
2474                 0x37b38, 0x37b50,
2475                 0x37bf0, 0x37c10,
2476                 0x37c24, 0x37c28,
2477                 0x37c38, 0x37c50,
2478                 0x37cf0, 0x37cfc,
2479                 0x40040, 0x40040,
2480                 0x40080, 0x40084,
2481                 0x40100, 0x40100,
2482                 0x40140, 0x401bc,
2483                 0x40200, 0x40214,
2484                 0x40228, 0x40228,
2485                 0x40240, 0x40258,
2486                 0x40280, 0x40280,
2487                 0x40304, 0x40304,
2488                 0x40330, 0x4033c,
2489                 0x41304, 0x413b8,
2490                 0x413c0, 0x413c8,
2491                 0x413d0, 0x413dc,
2492                 0x413f0, 0x413f0,
2493                 0x41400, 0x4140c,
2494                 0x41414, 0x4141c,
2495                 0x41480, 0x414d0,
2496                 0x44000, 0x4407c,
2497                 0x440c0, 0x441ac,
2498                 0x441b4, 0x4427c,
2499                 0x442c0, 0x443ac,
2500                 0x443b4, 0x4447c,
2501                 0x444c0, 0x445ac,
2502                 0x445b4, 0x4467c,
2503                 0x446c0, 0x447ac,
2504                 0x447b4, 0x4487c,
2505                 0x448c0, 0x449ac,
2506                 0x449b4, 0x44a7c,
2507                 0x44ac0, 0x44bac,
2508                 0x44bb4, 0x44c7c,
2509                 0x44cc0, 0x44dac,
2510                 0x44db4, 0x44e7c,
2511                 0x44ec0, 0x44fac,
2512                 0x44fb4, 0x4507c,
2513                 0x450c0, 0x451ac,
2514                 0x451b4, 0x451fc,
2515                 0x45800, 0x45804,
2516                 0x45810, 0x45830,
2517                 0x45840, 0x45860,
2518                 0x45868, 0x45868,
2519                 0x45880, 0x45884,
2520                 0x458a0, 0x458b0,
2521                 0x45a00, 0x45a04,
2522                 0x45a10, 0x45a30,
2523                 0x45a40, 0x45a60,
2524                 0x45a68, 0x45a68,
2525                 0x45a80, 0x45a84,
2526                 0x45aa0, 0x45ab0,
2527                 0x460c0, 0x460e4,
2528                 0x47000, 0x4703c,
2529                 0x47044, 0x4708c,
2530                 0x47200, 0x47250,
2531                 0x47400, 0x47408,
2532                 0x47414, 0x47420,
2533                 0x47600, 0x47618,
2534                 0x47800, 0x47814,
2535                 0x47820, 0x4782c,
2536                 0x50000, 0x50084,
2537                 0x50090, 0x500cc,
2538                 0x50300, 0x50384,
2539                 0x50400, 0x50400,
2540                 0x50800, 0x50884,
2541                 0x50890, 0x508cc,
2542                 0x50b00, 0x50b84,
2543                 0x50c00, 0x50c00,
2544                 0x51000, 0x51020,
2545                 0x51028, 0x510b0,
2546                 0x51300, 0x51324,
2547         };
2548
2549         u32 *buf_end = (u32 *)((char *)buf + buf_size);
2550         const unsigned int *reg_ranges;
2551         int reg_ranges_size, range;
2552         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2553
2554         /* Select the right set of register ranges to dump depending on the
2555          * adapter chip type.
2556          */
2557         switch (chip_version) {
2558         case CHELSIO_T4:
2559                 reg_ranges = t4_reg_ranges;
2560                 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2561                 break;
2562
2563         case CHELSIO_T5:
2564                 reg_ranges = t5_reg_ranges;
2565                 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2566                 break;
2567
2568         case CHELSIO_T6:
2569                 reg_ranges = t6_reg_ranges;
2570                 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2571                 break;
2572
2573         default:
2574                 dev_err(adap->pdev_dev,
2575                         "Unsupported chip version %d\n", chip_version);
2576                 return;
2577         }
2578
2579         /* Clear the register buffer and insert the appropriate register
2580          * values selected by the above register ranges.
2581          */
2582         memset(buf, 0, buf_size);
2583         for (range = 0; range < reg_ranges_size; range += 2) {
2584                 unsigned int reg = reg_ranges[range];
2585                 unsigned int last_reg = reg_ranges[range + 1];
2586                 u32 *bufp = (u32 *)((char *)buf + reg);
2587
2588                 /* Iterate across the register range filling in the register
2589                  * buffer but don't write past the end of the register buffer.
2590                  */
2591                 while (reg <= last_reg && bufp < buf_end) {
2592                         *bufp++ = t4_read_reg(adap, reg);
2593                         reg += sizeof(u32);
2594                 }
2595         }
2596 }
2597
2598 #define EEPROM_STAT_ADDR   0x7bfc
2599 #define VPD_SIZE           0x800
2600 #define VPD_BASE           0x400
2601 #define VPD_BASE_OLD       0
2602 #define VPD_LEN            1024
2603 #define CHELSIO_VPD_UNIQUE_ID 0x82
2604
2605 /**
2606  *      t4_seeprom_wp - enable/disable EEPROM write protection
2607  *      @adapter: the adapter
2608  *      @enable: whether to enable or disable write protection
2609  *
2610  *      Enables or disables write protection on the serial EEPROM.
2611  */
2612 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2613 {
2614         unsigned int v = enable ? 0xc : 0;
2615         int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2616         return ret < 0 ? ret : 0;
2617 }
2618
2619 /**
2620  *      t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2621  *      @adapter: adapter to read
2622  *      @p: where to store the parameters
2623  *
2624  *      Reads card parameters stored in VPD EEPROM.
2625  */
2626 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2627 {
2628         int i, ret = 0, addr;
2629         int ec, sn, pn, na;
2630         u8 *vpd, csum;
2631         unsigned int vpdr_len, kw_offset, id_len;
2632
2633         vpd = vmalloc(VPD_LEN);
2634         if (!vpd)
2635                 return -ENOMEM;
2636
2637         /* We have two VPD data structures stored in the adapter VPD area.
2638          * By default, Linux calculates the size of the VPD area by traversing
2639          * the first VPD area at offset 0x0, so we need to tell the OS what
2640          * our real VPD size is.
2641          */
2642         ret = pci_set_vpd_size(adapter->pdev, VPD_SIZE);
2643         if (ret < 0)
2644                 goto out;
2645
2646         /* Card information normally starts at VPD_BASE but early cards had
2647          * it at 0.
2648          */
2649         ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
2650         if (ret < 0)
2651                 goto out;
2652
2653         /* The VPD shall have a unique identifier specified by the PCI SIG.
2654          * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2655          * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2656          * is expected to automatically put this entry at the
2657          * beginning of the VPD.
2658          */
2659         addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2660
2661         ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2662         if (ret < 0)
2663                 goto out;
2664
2665         if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2666                 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2667                 ret = -EINVAL;
2668                 goto out;
2669         }
2670
2671         id_len = pci_vpd_lrdt_size(vpd);
2672         if (id_len > ID_LEN)
2673                 id_len = ID_LEN;
2674
2675         i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2676         if (i < 0) {
2677                 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2678                 ret = -EINVAL;
2679                 goto out;
2680         }
2681
2682         vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2683         kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2684         if (vpdr_len + kw_offset > VPD_LEN) {
2685                 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2686                 ret = -EINVAL;
2687                 goto out;
2688         }
2689
2690 #define FIND_VPD_KW(var, name) do { \
2691         var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2692         if (var < 0) { \
2693                 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2694                 ret = -EINVAL; \
2695                 goto out; \
2696         } \
2697         var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2698 } while (0)
2699
2700         FIND_VPD_KW(i, "RV");
2701         for (csum = 0; i >= 0; i--)
2702                 csum += vpd[i];
2703
2704         if (csum) {
2705                 dev_err(adapter->pdev_dev,
2706                         "corrupted VPD EEPROM, actual csum %u\n", csum);
2707                 ret = -EINVAL;
2708                 goto out;
2709         }
2710
2711         FIND_VPD_KW(ec, "EC");
2712         FIND_VPD_KW(sn, "SN");
2713         FIND_VPD_KW(pn, "PN");
2714         FIND_VPD_KW(na, "NA");
2715 #undef FIND_VPD_KW
2716
2717         memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2718         strim(p->id);
2719         memcpy(p->ec, vpd + ec, EC_LEN);
2720         strim(p->ec);
2721         i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2722         memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2723         strim(p->sn);
2724         i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2725         memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2726         strim(p->pn);
2727         memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2728         strim((char *)p->na);
2729
2730 out:
2731         vfree(vpd);
2732         return ret < 0 ? ret : 0;
2733 }
2734
2735 /**
2736  *      t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2737  *      @adapter: adapter to read
2738  *      @p: where to store the parameters
2739  *
2740  *      Reads card parameters stored in VPD EEPROM and retrieves the Core
2741  *      Clock.  This can only be called after a connection to the firmware
2742  *      is established.
2743  */
2744 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2745 {
2746         u32 cclk_param, cclk_val;
2747         int ret;
2748
2749         /* Grab the raw VPD parameters.
2750          */
2751         ret = t4_get_raw_vpd_params(adapter, p);
2752         if (ret)
2753                 return ret;
2754
2755         /* Ask firmware for the Core Clock since it knows how to translate the
2756          * Reference Clock ('V2') VPD field into a Core Clock value ...
2757          */
2758         cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2759                       FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2760         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2761                               1, &cclk_param, &cclk_val);
2762
2763         if (ret)
2764                 return ret;
2765         p->cclk = cclk_val;
2766
2767         return 0;
2768 }
2769
2770 /* serial flash and firmware constants */
2771 enum {
2772         SF_ATTEMPTS = 10,             /* max retries for SF operations */
2773
2774         /* flash command opcodes */
2775         SF_PROG_PAGE    = 2,          /* program page */
2776         SF_WR_DISABLE   = 4,          /* disable writes */
2777         SF_RD_STATUS    = 5,          /* read status register */
2778         SF_WR_ENABLE    = 6,          /* enable writes */
2779         SF_RD_DATA_FAST = 0xb,        /* read flash */
2780         SF_RD_ID        = 0x9f,       /* read ID */
2781         SF_ERASE_SECTOR = 0xd8,       /* erase sector */
2782
2783         FW_MAX_SIZE = 16 * SF_SEC_SIZE,
2784 };
2785
2786 /**
2787  *      sf1_read - read data from the serial flash
2788  *      @adapter: the adapter
2789  *      @byte_cnt: number of bytes to read
2790  *      @cont: whether another operation will be chained
2791  *      @lock: whether to lock SF for PL access only
2792  *      @valp: where to store the read data
2793  *
2794  *      Reads up to 4 bytes of data from the serial flash.  The location of
2795  *      the read needs to be specified prior to calling this by issuing the
2796  *      appropriate commands to the serial flash.
2797  */
2798 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2799                     int lock, u32 *valp)
2800 {
2801         int ret;
2802
2803         if (!byte_cnt || byte_cnt > 4)
2804                 return -EINVAL;
2805         if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2806                 return -EBUSY;
2807         t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2808                      SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2809         ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2810         if (!ret)
2811                 *valp = t4_read_reg(adapter, SF_DATA_A);
2812         return ret;
2813 }
2814
2815 /**
2816  *      sf1_write - write data to the serial flash
2817  *      @adapter: the adapter
2818  *      @byte_cnt: number of bytes to write
2819  *      @cont: whether another operation will be chained
2820  *      @lock: whether to lock SF for PL access only
2821  *      @val: value to write
2822  *
2823  *      Writes up to 4 bytes of data to the serial flash.  The location of
2824  *      the write needs to be specified prior to calling this by issuing the
2825  *      appropriate commands to the serial flash.
2826  */
2827 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2828                      int lock, u32 val)
2829 {
2830         if (!byte_cnt || byte_cnt > 4)
2831                 return -EINVAL;
2832         if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2833                 return -EBUSY;
2834         t4_write_reg(adapter, SF_DATA_A, val);
2835         t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2836                      SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2837         return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2838 }
2839
2840 /**
2841  *      flash_wait_op - wait for a flash operation to complete
2842  *      @adapter: the adapter
2843  *      @attempts: max number of polls of the status register
2844  *      @delay: delay between polls in ms
2845  *
2846  *      Wait for a flash operation to complete by polling the status register.
2847  */
2848 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
2849 {
2850         int ret;
2851         u32 status;
2852
2853         while (1) {
2854                 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
2855                     (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
2856                         return ret;
2857                 if (!(status & 1))
2858                         return 0;
2859                 if (--attempts == 0)
2860                         return -EAGAIN;
2861                 if (delay)
2862                         msleep(delay);
2863         }
2864 }
2865
2866 /**
2867  *      t4_read_flash - read words from serial flash
2868  *      @adapter: the adapter
2869  *      @addr: the start address for the read
2870  *      @nwords: how many 32-bit words to read
2871  *      @data: where to store the read data
2872  *      @byte_oriented: whether to store data as bytes or as words
2873  *
2874  *      Read the specified number of 32-bit words from the serial flash.
2875  *      If @byte_oriented is set the read data is stored as a byte array
2876  *      (i.e., big-endian), otherwise as 32-bit words in the platform's
2877  *      natural endianness.
2878  */
2879 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2880                   unsigned int nwords, u32 *data, int byte_oriented)
2881 {
2882         int ret;
2883
2884         if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
2885                 return -EINVAL;
2886
2887         addr = swab32(addr) | SF_RD_DATA_FAST;
2888
2889         if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
2890             (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
2891                 return ret;
2892
2893         for ( ; nwords; nwords--, data++) {
2894                 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2895                 if (nwords == 1)
2896                         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
2897                 if (ret)
2898                         return ret;
2899                 if (byte_oriented)
2900                         *data = (__force __u32)(cpu_to_be32(*data));
2901         }
2902         return 0;
2903 }
2904
2905 /**
2906  *      t4_write_flash - write up to a page of data to the serial flash
2907  *      @adapter: the adapter
2908  *      @addr: the start address to write
2909  *      @n: length of data to write in bytes
2910  *      @data: the data to write
2911  *
2912  *      Writes up to a page of data (256 bytes) to the serial flash starting
2913  *      at the given address.  All the data must be written to the same page.
2914  */
2915 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
2916                           unsigned int n, const u8 *data)
2917 {
2918         int ret;
2919         u32 buf[64];
2920         unsigned int i, c, left, val, offset = addr & 0xff;
2921
2922         if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
2923                 return -EINVAL;
2924
2925         val = swab32(addr) | SF_PROG_PAGE;
2926
2927         if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
2928             (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
2929                 goto unlock;
2930
2931         for (left = n; left; left -= c) {
2932                 c = min(left, 4U);
2933                 for (val = 0, i = 0; i < c; ++i)
2934                         val = (val << 8) + *data++;
2935
2936                 ret = sf1_write(adapter, c, c != left, 1, val);
2937                 if (ret)
2938                         goto unlock;
2939         }
2940         ret = flash_wait_op(adapter, 8, 1);
2941         if (ret)
2942                 goto unlock;
2943
2944         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
2945
2946         /* Read the page to verify the write succeeded */
2947         ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
2948         if (ret)
2949                 return ret;
2950
2951         if (memcmp(data - n, (u8 *)buf + offset, n)) {
2952                 dev_err(adapter->pdev_dev,
2953                         "failed to correctly write the flash page at %#x\n",
2954                         addr);
2955                 return -EIO;
2956         }
2957         return 0;
2958
2959 unlock:
2960         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
2961         return ret;
2962 }
2963
2964 /**
2965  *      t4_get_fw_version - read the firmware version
2966  *      @adapter: the adapter
2967  *      @vers: where to place the version
2968  *
2969  *      Reads the FW version from flash.
2970  */
2971 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
2972 {
2973         return t4_read_flash(adapter, FLASH_FW_START +
2974                              offsetof(struct fw_hdr, fw_ver), 1,
2975                              vers, 0);
2976 }
2977
2978 /**
2979  *      t4_get_bs_version - read the firmware bootstrap version
2980  *      @adapter: the adapter
2981  *      @vers: where to place the version
2982  *
2983  *      Reads the FW Bootstrap version from flash.
2984  */
2985 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
2986 {
2987         return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
2988                              offsetof(struct fw_hdr, fw_ver), 1,
2989                              vers, 0);
2990 }
2991
2992 /**
2993  *      t4_get_tp_version - read the TP microcode version
2994  *      @adapter: the adapter
2995  *      @vers: where to place the version
2996  *
2997  *      Reads the TP microcode version from flash.
2998  */
2999 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3000 {
3001         return t4_read_flash(adapter, FLASH_FW_START +
3002                              offsetof(struct fw_hdr, tp_microcode_ver),
3003                              1, vers, 0);
3004 }
3005
3006 /**
3007  *      t4_get_exprom_version - return the Expansion ROM version (if any)
3008  *      @adapter: the adapter
3009  *      @vers: where to place the version
3010  *
3011  *      Reads the Expansion ROM header from FLASH and returns the version
3012  *      number (if present) through the @vers return value pointer.  We return
3013  *      this in the Firmware Version Format since it's convenient.  Return
3014  *      0 on success, -ENOENT if no Expansion ROM is present.
3015  */
3016 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3017 {
3018         struct exprom_header {
3019                 unsigned char hdr_arr[16];      /* must start with 0x55aa */
3020                 unsigned char hdr_ver[4];       /* Expansion ROM version */
3021         } *hdr;
3022         u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3023                                            sizeof(u32))];
3024         int ret;
3025
3026         ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3027                             ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3028                             0);
3029         if (ret)
3030                 return ret;
3031
3032         hdr = (struct exprom_header *)exprom_header_buf;
3033         if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3034                 return -ENOENT;
3035
3036         *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
3037                  FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
3038                  FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
3039                  FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
3040         return 0;
3041 }
3042
3043 /**
3044  *      t4_check_fw_version - check if the FW is supported with this driver
3045  *      @adap: the adapter
3046  *
3047  *      Checks if an adapter's FW is compatible with the driver.  Returns 0
3048  *      if there's exact match, a negative error if the version could not be
3049  *      read or there's a major version mismatch
3050  */
3051 int t4_check_fw_version(struct adapter *adap)
3052 {
3053         int i, ret, major, minor, micro;
3054         int exp_major, exp_minor, exp_micro;
3055         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3056
3057         ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3058         /* Try multiple times before returning error */
3059         for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
3060                 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3061
3062         if (ret)
3063                 return ret;
3064
3065         major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3066         minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3067         micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3068
3069         switch (chip_version) {
3070         case CHELSIO_T4:
3071                 exp_major = T4FW_MIN_VERSION_MAJOR;
3072                 exp_minor = T4FW_MIN_VERSION_MINOR;
3073                 exp_micro = T4FW_MIN_VERSION_MICRO;
3074                 break;
3075         case CHELSIO_T5:
3076                 exp_major = T5FW_MIN_VERSION_MAJOR;
3077                 exp_minor = T5FW_MIN_VERSION_MINOR;
3078                 exp_micro = T5FW_MIN_VERSION_MICRO;
3079                 break;
3080         case CHELSIO_T6:
3081                 exp_major = T6FW_MIN_VERSION_MAJOR;
3082                 exp_minor = T6FW_MIN_VERSION_MINOR;
3083                 exp_micro = T6FW_MIN_VERSION_MICRO;
3084                 break;
3085         default:
3086                 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3087                         adap->chip);
3088                 return -EINVAL;
3089         }
3090
3091         if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3092             (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3093                 dev_err(adap->pdev_dev,
3094                         "Card has firmware version %u.%u.%u, minimum "
3095                         "supported firmware is %u.%u.%u.\n", major, minor,
3096                         micro, exp_major, exp_minor, exp_micro);
3097                 return -EFAULT;
3098         }
3099         return 0;
3100 }
3101
3102 /* Is the given firmware API compatible with the one the driver was compiled
3103  * with?
3104  */
3105 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3106 {
3107
3108         /* short circuit if it's the exact same firmware version */
3109         if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3110                 return 1;
3111
3112 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3113         if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3114             SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3115                 return 1;
3116 #undef SAME_INTF
3117
3118         return 0;
3119 }
3120
3121 /* The firmware in the filesystem is usable, but should it be installed?
3122  * This routine explains itself in detail if it indicates the filesystem
3123  * firmware should be installed.
3124  */
3125 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3126                                 int k, int c)
3127 {
3128         const char *reason;
3129
3130         if (!card_fw_usable) {
3131                 reason = "incompatible or unusable";
3132                 goto install;
3133         }
3134
3135         if (k > c) {
3136                 reason = "older than the version supported with this driver";
3137                 goto install;
3138         }
3139
3140         return 0;
3141
3142 install:
3143         dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3144                 "installing firmware %u.%u.%u.%u on card.\n",
3145                 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3146                 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3147                 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3148                 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3149
3150         return 1;
3151 }
3152
3153 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3154                const u8 *fw_data, unsigned int fw_size,
3155                struct fw_hdr *card_fw, enum dev_state state,
3156                int *reset)
3157 {
3158         int ret, card_fw_usable, fs_fw_usable;
3159         const struct fw_hdr *fs_fw;
3160         const struct fw_hdr *drv_fw;
3161
3162         drv_fw = &fw_info->fw_hdr;
3163
3164         /* Read the header of the firmware on the card */
3165         ret = -t4_read_flash(adap, FLASH_FW_START,
3166                             sizeof(*card_fw) / sizeof(uint32_t),
3167                             (uint32_t *)card_fw, 1);
3168         if (ret == 0) {
3169                 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3170         } else {
3171                 dev_err(adap->pdev_dev,
3172                         "Unable to read card's firmware header: %d\n", ret);
3173                 card_fw_usable = 0;
3174         }
3175
3176         if (fw_data != NULL) {
3177                 fs_fw = (const void *)fw_data;
3178                 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3179         } else {
3180                 fs_fw = NULL;
3181                 fs_fw_usable = 0;
3182         }
3183
3184         if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3185             (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3186                 /* Common case: the firmware on the card is an exact match and
3187                  * the filesystem one is an exact match too, or the filesystem
3188                  * one is absent/incompatible.
3189                  */
3190         } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3191                    should_install_fs_fw(adap, card_fw_usable,
3192                                         be32_to_cpu(fs_fw->fw_ver),
3193                                         be32_to_cpu(card_fw->fw_ver))) {
3194                 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data,
3195                                      fw_size, 0);
3196                 if (ret != 0) {
3197                         dev_err(adap->pdev_dev,
3198                                 "failed to install firmware: %d\n", ret);
3199                         goto bye;
3200                 }
3201
3202                 /* Installed successfully, update the cached header too. */
3203                 *card_fw = *fs_fw;
3204                 card_fw_usable = 1;
3205                 *reset = 0;     /* already reset as part of load_fw */
3206         }
3207
3208         if (!card_fw_usable) {
3209                 uint32_t d, c, k;
3210
3211                 d = be32_to_cpu(drv_fw->fw_ver);
3212                 c = be32_to_cpu(card_fw->fw_ver);
3213                 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3214
3215                 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3216                         "chip state %d, "
3217                         "driver compiled with %d.%d.%d.%d, "
3218                         "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3219                         state,
3220                         FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3221                         FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3222                         FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3223                         FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3224                         FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3225                         FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3226                 ret = EINVAL;
3227                 goto bye;
3228         }
3229
3230         /* We're using whatever's on the card and it's known to be good. */
3231         adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3232         adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3233
3234 bye:
3235         return ret;
3236 }
3237
3238 /**
3239  *      t4_flash_erase_sectors - erase a range of flash sectors
3240  *      @adapter: the adapter
3241  *      @start: the first sector to erase
3242  *      @end: the last sector to erase
3243  *
3244  *      Erases the sectors in the given inclusive range.
3245  */
3246 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3247 {
3248         int ret = 0;
3249
3250         if (end >= adapter->params.sf_nsec)
3251                 return -EINVAL;
3252
3253         while (start <= end) {
3254                 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3255                     (ret = sf1_write(adapter, 4, 0, 1,
3256                                      SF_ERASE_SECTOR | (start << 8))) != 0 ||
3257                     (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3258                         dev_err(adapter->pdev_dev,
3259                                 "erase of flash sector %d failed, error %d\n",
3260                                 start, ret);
3261                         break;
3262                 }
3263                 start++;
3264         }
3265         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3266         return ret;
3267 }
3268
3269 /**
3270  *      t4_flash_cfg_addr - return the address of the flash configuration file
3271  *      @adapter: the adapter
3272  *
3273  *      Return the address within the flash where the Firmware Configuration
3274  *      File is stored.
3275  */
3276 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3277 {
3278         if (adapter->params.sf_size == 0x100000)
3279                 return FLASH_FPGA_CFG_START;
3280         else
3281                 return FLASH_CFG_START;
3282 }
3283
3284 /* Return TRUE if the specified firmware matches the adapter.  I.e. T4
3285  * firmware for T4 adapters, T5 firmware for T5 adapters, etc.  We go ahead
3286  * and emit an error message for mismatched firmware to save our caller the
3287  * effort ...
3288  */
3289 static bool t4_fw_matches_chip(const struct adapter *adap,
3290                                const struct fw_hdr *hdr)
3291 {
3292         /* The expression below will return FALSE for any unsupported adapter
3293          * which will keep us "honest" in the future ...
3294          */
3295         if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3296             (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3297             (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3298                 return true;
3299
3300         dev_err(adap->pdev_dev,
3301                 "FW image (%d) is not suitable for this adapter (%d)\n",
3302                 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3303         return false;
3304 }
3305
3306 /**
3307  *      t4_load_fw - download firmware
3308  *      @adap: the adapter
3309  *      @fw_data: the firmware image to write
3310  *      @size: image size
3311  *
3312  *      Write the supplied firmware image to the card's serial flash.
3313  */
3314 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3315 {
3316         u32 csum;
3317         int ret, addr;
3318         unsigned int i;
3319         u8 first_page[SF_PAGE_SIZE];
3320         const __be32 *p = (const __be32 *)fw_data;
3321         const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3322         unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3323         unsigned int fw_img_start = adap->params.sf_fw_start;
3324         unsigned int fw_start_sec = fw_img_start / sf_sec_size;
3325
3326         if (!size) {
3327                 dev_err(adap->pdev_dev, "FW image has no data\n");
3328                 return -EINVAL;
3329         }
3330         if (size & 511) {
3331                 dev_err(adap->pdev_dev,
3332                         "FW image size not multiple of 512 bytes\n");
3333                 return -EINVAL;
3334         }
3335         if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3336                 dev_err(adap->pdev_dev,
3337                         "FW image size differs from size in FW header\n");
3338                 return -EINVAL;
3339         }
3340         if (size > FW_MAX_SIZE) {
3341                 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3342                         FW_MAX_SIZE);
3343                 return -EFBIG;
3344         }
3345         if (!t4_fw_matches_chip(adap, hdr))
3346                 return -EINVAL;
3347
3348         for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3349                 csum += be32_to_cpu(p[i]);
3350
3351         if (csum != 0xffffffff) {
3352                 dev_err(adap->pdev_dev,
3353                         "corrupted firmware image, checksum %#x\n", csum);
3354                 return -EINVAL;
3355         }
3356
3357         i = DIV_ROUND_UP(size, sf_sec_size);        /* # of sectors spanned */
3358         ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3359         if (ret)
3360                 goto out;
3361
3362         /*
3363          * We write the correct version at the end so the driver can see a bad
3364          * version if the FW write fails.  Start by writing a copy of the
3365          * first page with a bad version.
3366          */
3367         memcpy(first_page, fw_data, SF_PAGE_SIZE);
3368         ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3369         ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page);
3370         if (ret)
3371                 goto out;
3372
3373         addr = fw_img_start;
3374         for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3375                 addr += SF_PAGE_SIZE;
3376                 fw_data += SF_PAGE_SIZE;
3377                 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
3378                 if (ret)
3379                         goto out;
3380         }
3381
3382         ret = t4_write_flash(adap,
3383                              fw_img_start + offsetof(struct fw_hdr, fw_ver),
3384                              sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
3385 out:
3386         if (ret)
3387                 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3388                         ret);
3389         else
3390                 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3391         return ret;
3392 }
3393
3394 /**
3395  *      t4_phy_fw_ver - return current PHY firmware version
3396  *      @adap: the adapter
3397  *      @phy_fw_ver: return value buffer for PHY firmware version
3398  *
3399  *      Returns the current version of external PHY firmware on the
3400  *      adapter.
3401  */
3402 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3403 {
3404         u32 param, val;
3405         int ret;
3406
3407         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3408                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3409                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3410                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3411         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3412                               &param, &val);
3413         if (ret < 0)
3414                 return ret;
3415         *phy_fw_ver = val;
3416         return 0;
3417 }
3418
3419 /**
3420  *      t4_load_phy_fw - download port PHY firmware
3421  *      @adap: the adapter
3422  *      @win: the PCI-E Memory Window index to use for t4_memory_rw()
3423  *      @win_lock: the lock to use to guard the memory copy
3424  *      @phy_fw_version: function to check PHY firmware versions
3425  *      @phy_fw_data: the PHY firmware image to write
3426  *      @phy_fw_size: image size
3427  *
3428  *      Transfer the specified PHY firmware to the adapter.  If a non-NULL
3429  *      @phy_fw_version is supplied, then it will be used to determine if
3430  *      it's necessary to perform the transfer by comparing the version
3431  *      of any existing adapter PHY firmware with that of the passed in
3432  *      PHY firmware image.  If @win_lock is non-NULL then it will be used
3433  *      around the call to t4_memory_rw() which transfers the PHY firmware
3434  *      to the adapter.
3435  *
3436  *      A negative error number will be returned if an error occurs.  If
3437  *      version number support is available and there's no need to upgrade
3438  *      the firmware, 0 will be returned.  If firmware is successfully
3439  *      transferred to the adapter, 1 will be retured.
3440  *
3441  *      NOTE: some adapters only have local RAM to store the PHY firmware.  As
3442  *      a result, a RESET of the adapter would cause that RAM to lose its
3443  *      contents.  Thus, loading PHY firmware on such adapters must happen
3444  *      after any FW_RESET_CMDs ...
3445  */
3446 int t4_load_phy_fw(struct adapter *adap,
3447                    int win, spinlock_t *win_lock,
3448                    int (*phy_fw_version)(const u8 *, size_t),
3449                    const u8 *phy_fw_data, size_t phy_fw_size)
3450 {
3451         unsigned long mtype = 0, maddr = 0;
3452         u32 param, val;
3453         int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3454         int ret;
3455
3456         /* If we have version number support, then check to see if the adapter
3457          * already has up-to-date PHY firmware loaded.
3458          */
3459          if (phy_fw_version) {
3460                 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3461                 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3462                 if (ret < 0)
3463                         return ret;
3464
3465                 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3466                         CH_WARN(adap, "PHY Firmware already up-to-date, "
3467                                 "version %#x\n", cur_phy_fw_ver);
3468                         return 0;
3469                 }
3470         }
3471
3472         /* Ask the firmware where it wants us to copy the PHY firmware image.
3473          * The size of the file requires a special version of the READ coommand
3474          * which will pass the file size via the values field in PARAMS_CMD and
3475          * retrieve the return value from firmware and place it in the same
3476          * buffer values
3477          */
3478         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3479                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3480                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3481                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3482         val = phy_fw_size;
3483         ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3484                                  &param, &val, 1);
3485         if (ret < 0)
3486                 return ret;
3487         mtype = val >> 8;
3488         maddr = (val & 0xff) << 16;
3489
3490         /* Copy the supplied PHY Firmware image to the adapter memory location
3491          * allocated by the adapter firmware.
3492          */
3493         if (win_lock)
3494                 spin_lock_bh(win_lock);
3495         ret = t4_memory_rw(adap, win, mtype, maddr,
3496                            phy_fw_size, (__be32 *)phy_fw_data,
3497                            T4_MEMORY_WRITE);
3498         if (win_lock)
3499                 spin_unlock_bh(win_lock);
3500         if (ret)
3501                 return ret;
3502
3503         /* Tell the firmware that the PHY firmware image has been written to
3504          * RAM and it can now start copying it over to the PHYs.  The chip
3505          * firmware will RESET the affected PHYs as part of this operation
3506          * leaving them running the new PHY firmware image.
3507          */
3508         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3509                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3510                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3511                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3512         ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3513                                     &param, &val, 30000);
3514
3515         /* If we have version number support, then check to see that the new
3516          * firmware got loaded properly.
3517          */
3518         if (phy_fw_version) {
3519                 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3520                 if (ret < 0)
3521                         return ret;
3522
3523                 if (cur_phy_fw_ver != new_phy_fw_vers) {
3524                         CH_WARN(adap, "PHY Firmware did not update: "
3525                                 "version on adapter %#x, "
3526                                 "version flashed %#x\n",
3527                                 cur_phy_fw_ver, new_phy_fw_vers);
3528                         return -ENXIO;
3529                 }
3530         }
3531
3532         return 1;
3533 }
3534
3535 /**
3536  *      t4_fwcache - firmware cache operation
3537  *      @adap: the adapter
3538  *      @op  : the operation (flush or flush and invalidate)
3539  */
3540 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3541 {
3542         struct fw_params_cmd c;
3543
3544         memset(&c, 0, sizeof(c));
3545         c.op_to_vfn =
3546                 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3547                             FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3548                             FW_PARAMS_CMD_PFN_V(adap->pf) |
3549                             FW_PARAMS_CMD_VFN_V(0));
3550         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3551         c.param[0].mnem =
3552                 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3553                             FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3554         c.param[0].val = (__force __be32)op;
3555
3556         return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3557 }
3558
3559 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3560                         unsigned int *pif_req_wrptr,
3561                         unsigned int *pif_rsp_wrptr)
3562 {
3563         int i, j;
3564         u32 cfg, val, req, rsp;
3565
3566         cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3567         if (cfg & LADBGEN_F)
3568                 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3569
3570         val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3571         req = POLADBGWRPTR_G(val);
3572         rsp = PILADBGWRPTR_G(val);
3573         if (pif_req_wrptr)
3574                 *pif_req_wrptr = req;
3575         if (pif_rsp_wrptr)
3576                 *pif_rsp_wrptr = rsp;
3577
3578         for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3579                 for (j = 0; j < 6; j++) {
3580                         t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3581                                      PILADBGRDPTR_V(rsp));
3582                         *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3583                         *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3584                         req++;
3585                         rsp++;
3586                 }
3587                 req = (req + 2) & POLADBGRDPTR_M;
3588                 rsp = (rsp + 2) & PILADBGRDPTR_M;
3589         }
3590         t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3591 }
3592
3593 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3594 {
3595         u32 cfg;
3596         int i, j, idx;
3597
3598         cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3599         if (cfg & LADBGEN_F)
3600                 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3601
3602         for (i = 0; i < CIM_MALA_SIZE; i++) {
3603                 for (j = 0; j < 5; j++) {
3604                         idx = 8 * i + j;
3605                         t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3606                                      PILADBGRDPTR_V(idx));
3607                         *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3608                         *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3609                 }
3610         }
3611         t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3612 }
3613
3614 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3615 {
3616         unsigned int i, j;
3617
3618         for (i = 0; i < 8; i++) {
3619                 u32 *p = la_buf + i;
3620
3621                 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3622                 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3623                 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3624                 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3625                         *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3626         }
3627 }
3628
3629 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
3630                      FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_25G | \
3631                      FW_PORT_CAP_SPEED_40G | FW_PORT_CAP_SPEED_100G | \
3632                      FW_PORT_CAP_ANEG)
3633
3634 /**
3635  *      t4_link_l1cfg - apply link configuration to MAC/PHY
3636  *      @phy: the PHY to setup
3637  *      @mac: the MAC to setup
3638  *      @lc: the requested link configuration
3639  *
3640  *      Set up a port's MAC and PHY according to a desired link configuration.
3641  *      - If the PHY can auto-negotiate first decide what to advertise, then
3642  *        enable/disable auto-negotiation as desired, and reset.
3643  *      - If the PHY does not auto-negotiate just reset it.
3644  *      - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
3645  *        otherwise do it later based on the outcome of auto-negotiation.
3646  */
3647 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
3648                   struct link_config *lc)
3649 {
3650         struct fw_port_cmd c;
3651         unsigned int fc = 0, mdi = FW_PORT_CAP_MDI_V(FW_PORT_CAP_MDI_AUTO);
3652
3653         lc->link_ok = 0;
3654         if (lc->requested_fc & PAUSE_RX)
3655                 fc |= FW_PORT_CAP_FC_RX;
3656         if (lc->requested_fc & PAUSE_TX)
3657                 fc |= FW_PORT_CAP_FC_TX;
3658
3659         memset(&c, 0, sizeof(c));
3660         c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3661                                      FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3662                                      FW_PORT_CMD_PORTID_V(port));
3663         c.action_to_len16 =
3664                 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3665                             FW_LEN16(c));
3666
3667         if (!(lc->supported & FW_PORT_CAP_ANEG)) {
3668                 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
3669                                              fc);
3670                 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3671         } else if (lc->autoneg == AUTONEG_DISABLE) {
3672                 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc | mdi);
3673                 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3674         } else
3675                 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | mdi);
3676
3677         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3678 }
3679
3680 /**
3681  *      t4_restart_aneg - restart autonegotiation
3682  *      @adap: the adapter
3683  *      @mbox: mbox to use for the FW command
3684  *      @port: the port id
3685  *
3686  *      Restarts autonegotiation for the selected port.
3687  */
3688 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
3689 {
3690         struct fw_port_cmd c;
3691
3692         memset(&c, 0, sizeof(c));
3693         c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3694                                      FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3695                                      FW_PORT_CMD_PORTID_V(port));
3696         c.action_to_len16 =
3697                 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3698                             FW_LEN16(c));
3699         c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
3700         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3701 }
3702
3703 typedef void (*int_handler_t)(struct adapter *adap);
3704
3705 struct intr_info {
3706         unsigned int mask;       /* bits to check in interrupt status */
3707         const char *msg;         /* message to print or NULL */
3708         short stat_idx;          /* stat counter to increment or -1 */
3709         unsigned short fatal;    /* whether the condition reported is fatal */
3710         int_handler_t int_handler; /* platform-specific int handler */
3711 };
3712
3713 /**
3714  *      t4_handle_intr_status - table driven interrupt handler
3715  *      @adapter: the adapter that generated the interrupt
3716  *      @reg: the interrupt status register to process
3717  *      @acts: table of interrupt actions
3718  *
3719  *      A table driven interrupt handler that applies a set of masks to an
3720  *      interrupt status word and performs the corresponding actions if the
3721  *      interrupts described by the mask have occurred.  The actions include
3722  *      optionally emitting a warning or alert message.  The table is terminated
3723  *      by an entry specifying mask 0.  Returns the number of fatal interrupt
3724  *      conditions.
3725  */
3726 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
3727                                  const struct intr_info *acts)
3728 {
3729         int fatal = 0;
3730         unsigned int mask = 0;
3731         unsigned int status = t4_read_reg(adapter, reg);
3732
3733         for ( ; acts->mask; ++acts) {
3734                 if (!(status & acts->mask))
3735                         continue;
3736                 if (acts->fatal) {
3737                         fatal++;
3738                         dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3739                                   status & acts->mask);
3740                 } else if (acts->msg && printk_ratelimit())
3741                         dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3742                                  status & acts->mask);
3743                 if (acts->int_handler)
3744                         acts->int_handler(adapter);
3745                 mask |= acts->mask;
3746         }
3747         status &= mask;
3748         if (status)                           /* clear processed interrupts */
3749                 t4_write_reg(adapter, reg, status);
3750         return fatal;
3751 }
3752
3753 /*
3754  * Interrupt handler for the PCIE module.
3755  */
3756 static void pcie_intr_handler(struct adapter *adapter)
3757 {
3758         static const struct intr_info sysbus_intr_info[] = {
3759                 { RNPP_F, "RXNP array parity error", -1, 1 },
3760                 { RPCP_F, "RXPC array parity error", -1, 1 },
3761                 { RCIP_F, "RXCIF array parity error", -1, 1 },
3762                 { RCCP_F, "Rx completions control array parity error", -1, 1 },
3763                 { RFTP_F, "RXFT array parity error", -1, 1 },
3764                 { 0 }
3765         };
3766         static const struct intr_info pcie_port_intr_info[] = {
3767                 { TPCP_F, "TXPC array parity error", -1, 1 },
3768                 { TNPP_F, "TXNP array parity error", -1, 1 },
3769                 { TFTP_F, "TXFT array parity error", -1, 1 },
3770                 { TCAP_F, "TXCA array parity error", -1, 1 },
3771                 { TCIP_F, "TXCIF array parity error", -1, 1 },
3772                 { RCAP_F, "RXCA array parity error", -1, 1 },
3773                 { OTDD_F, "outbound request TLP discarded", -1, 1 },
3774                 { RDPE_F, "Rx data parity error", -1, 1 },
3775                 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
3776                 { 0 }
3777         };
3778         static const struct intr_info pcie_intr_info[] = {
3779                 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
3780                 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
3781                 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
3782                 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3783                 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3784                 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3785                 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3786                 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
3787                 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
3788                 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3789                 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
3790                 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3791                 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3792                 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
3793                 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3794                 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3795                 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
3796                 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3797                 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3798                 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3799                 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3800                 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
3801                 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
3802                 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3803                 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
3804                 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
3805                 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
3806                 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
3807                 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
3808                 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
3809                   -1, 0 },
3810                 { 0 }
3811         };
3812
3813         static struct intr_info t5_pcie_intr_info[] = {
3814                 { MSTGRPPERR_F, "Master Response Read Queue parity error",
3815                   -1, 1 },
3816                 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
3817                 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
3818                 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3819                 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3820                 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3821                 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3822                 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
3823                   -1, 1 },
3824                 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
3825                   -1, 1 },
3826                 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3827                 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
3828                 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3829                 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3830                 { DREQWRPERR_F, "PCI DMA channel write request parity error",
3831                   -1, 1 },
3832                 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3833                 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3834                 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
3835                 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3836                 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3837                 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3838                 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3839                 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
3840                 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
3841                 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3842                 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
3843                   -1, 1 },
3844                 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
3845                   -1, 1 },
3846                 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
3847                 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
3848                 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
3849                 { READRSPERR_F, "Outbound read error", -1, 0 },
3850                 { 0 }
3851         };
3852
3853         int fat;
3854
3855         if (is_t4(adapter->params.chip))
3856                 fat = t4_handle_intr_status(adapter,
3857                                 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
3858                                 sysbus_intr_info) +
3859                         t4_handle_intr_status(adapter,
3860                                         PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
3861                                         pcie_port_intr_info) +
3862                         t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3863                                               pcie_intr_info);
3864         else
3865                 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3866                                             t5_pcie_intr_info);
3867
3868         if (fat)
3869                 t4_fatal_err(adapter);
3870 }
3871
3872 /*
3873  * TP interrupt handler.
3874  */
3875 static void tp_intr_handler(struct adapter *adapter)
3876 {
3877         static const struct intr_info tp_intr_info[] = {
3878                 { 0x3fffffff, "TP parity error", -1, 1 },
3879                 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
3880                 { 0 }
3881         };
3882
3883         if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
3884                 t4_fatal_err(adapter);
3885 }
3886
3887 /*
3888  * SGE interrupt handler.
3889  */
3890 static void sge_intr_handler(struct adapter *adapter)
3891 {
3892         u64 v;
3893         u32 err;
3894
3895         static const struct intr_info sge_intr_info[] = {
3896                 { ERR_CPL_EXCEED_IQE_SIZE_F,
3897                   "SGE received CPL exceeding IQE size", -1, 1 },
3898                 { ERR_INVALID_CIDX_INC_F,
3899                   "SGE GTS CIDX increment too large", -1, 0 },
3900                 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
3901                 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
3902                 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
3903                   "SGE IQID > 1023 received CPL for FL", -1, 0 },
3904                 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
3905                   0 },
3906                 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
3907                   0 },
3908                 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
3909                   0 },
3910                 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
3911                   0 },
3912                 { ERR_ING_CTXT_PRIO_F,
3913                   "SGE too many priority ingress contexts", -1, 0 },
3914                 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
3915                 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
3916                 { 0 }
3917         };
3918
3919         static struct intr_info t4t5_sge_intr_info[] = {
3920                 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
3921                 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
3922                 { ERR_EGR_CTXT_PRIO_F,
3923                   "SGE too many priority egress contexts", -1, 0 },
3924                 { 0 }
3925         };
3926
3927         v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |
3928                 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);
3929         if (v) {
3930                 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
3931                                 (unsigned long long)v);
3932                 t4_write_reg(adapter, SGE_INT_CAUSE1_A, v);
3933                 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);
3934         }
3935
3936         v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
3937         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
3938                 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
3939                                            t4t5_sge_intr_info);
3940
3941         err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
3942         if (err & ERROR_QID_VALID_F) {
3943                 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
3944                         ERROR_QID_G(err));
3945                 if (err & UNCAPTURED_ERROR_F)
3946                         dev_err(adapter->pdev_dev,
3947                                 "SGE UNCAPTURED_ERROR set (clearing)\n");
3948                 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
3949                              UNCAPTURED_ERROR_F);
3950         }
3951
3952         if (v != 0)
3953                 t4_fatal_err(adapter);
3954 }
3955
3956 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
3957                       OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
3958 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
3959                       IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
3960
3961 /*
3962  * CIM interrupt handler.
3963  */
3964 static void cim_intr_handler(struct adapter *adapter)
3965 {
3966         static const struct intr_info cim_intr_info[] = {
3967                 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
3968                 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
3969                 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
3970                 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
3971                 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
3972                 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
3973                 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
3974                 { 0 }
3975         };
3976         static const struct intr_info cim_upintr_info[] = {
3977                 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
3978                 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
3979                 { ILLWRINT_F, "CIM illegal write", -1, 1 },
3980                 { ILLRDINT_F, "CIM illegal read", -1, 1 },
3981                 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
3982                 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
3983                 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
3984                 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
3985                 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
3986                 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
3987                 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
3988                 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
3989                 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
3990                 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
3991                 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
3992                 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
3993                 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
3994                 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
3995                 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
3996                 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
3997                 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
3998                 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
3999                 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
4000                 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
4001                 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
4002                 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
4003                 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
4004                 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
4005                 { 0 }
4006         };
4007
4008         int fat;
4009
4010         if (t4_read_reg(adapter, PCIE_FW_A) & PCIE_FW_ERR_F)
4011                 t4_report_fw_error(adapter);
4012
4013         fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
4014                                     cim_intr_info) +
4015               t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
4016                                     cim_upintr_info);
4017         if (fat)
4018                 t4_fatal_err(adapter);
4019 }
4020
4021 /*
4022  * ULP RX interrupt handler.
4023  */
4024 static void ulprx_intr_handler(struct adapter *adapter)
4025 {
4026         static const struct intr_info ulprx_intr_info[] = {
4027                 { 0x1800000, "ULPRX context error", -1, 1 },
4028                 { 0x7fffff, "ULPRX parity error", -1, 1 },
4029                 { 0 }
4030         };
4031
4032         if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
4033                 t4_fatal_err(adapter);
4034 }
4035
4036 /*
4037  * ULP TX interrupt handler.
4038  */
4039 static void ulptx_intr_handler(struct adapter *adapter)
4040 {
4041         static const struct intr_info ulptx_intr_info[] = {
4042                 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
4043                   0 },
4044                 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
4045                   0 },
4046                 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
4047                   0 },
4048                 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
4049                   0 },
4050                 { 0xfffffff, "ULPTX parity error", -1, 1 },
4051                 { 0 }
4052         };
4053
4054         if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
4055                 t4_fatal_err(adapter);
4056 }
4057
4058 /*
4059  * PM TX interrupt handler.
4060  */
4061 static void pmtx_intr_handler(struct adapter *adapter)
4062 {
4063         static const struct intr_info pmtx_intr_info[] = {
4064                 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4065                 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4066                 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4067                 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4068                 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4069                 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4070                 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4071                   -1, 1 },
4072                 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4073                 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4074                 { 0 }
4075         };
4076
4077         if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4078                 t4_fatal_err(adapter);
4079 }
4080
4081 /*
4082  * PM RX interrupt handler.
4083  */
4084 static void pmrx_intr_handler(struct adapter *adapter)
4085 {
4086         static const struct intr_info pmrx_intr_info[] = {
4087                 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4088                 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4089                 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4090                 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4091                   -1, 1 },
4092                 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4093                 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4094                 { 0 }
4095         };
4096
4097         if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4098                 t4_fatal_err(adapter);
4099 }
4100
4101 /*
4102  * CPL switch interrupt handler.
4103  */
4104 static void cplsw_intr_handler(struct adapter *adapter)
4105 {
4106         static const struct intr_info cplsw_intr_info[] = {
4107                 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4108                 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4109                 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4110                 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4111                 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4112                 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4113                 { 0 }
4114         };
4115
4116         if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4117                 t4_fatal_err(adapter);
4118 }
4119
4120 /*
4121  * LE interrupt handler.
4122  */
4123 static void le_intr_handler(struct adapter *adap)
4124 {
4125         enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4126         static const struct intr_info le_intr_info[] = {
4127                 { LIPMISS_F, "LE LIP miss", -1, 0 },
4128                 { LIP0_F, "LE 0 LIP error", -1, 0 },
4129                 { PARITYERR_F, "LE parity error", -1, 1 },
4130                 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4131                 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4132                 { 0 }
4133         };
4134
4135         static struct intr_info t6_le_intr_info[] = {
4136                 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4137                 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4138                 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4139                 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4140                 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4141                 { 0 }
4142         };
4143
4144         if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4145                                   (chip <= CHELSIO_T5) ?
4146                                   le_intr_info : t6_le_intr_info))
4147                 t4_fatal_err(adap);
4148 }
4149
4150 /*
4151  * MPS interrupt handler.
4152  */
4153 static void mps_intr_handler(struct adapter *adapter)
4154 {
4155         static const struct intr_info mps_rx_intr_info[] = {
4156                 { 0xffffff, "MPS Rx parity error", -1, 1 },
4157                 { 0 }
4158         };
4159         static const struct intr_info mps_tx_intr_info[] = {
4160                 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4161                 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4162                 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4163                   -1, 1 },
4164                 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4165                   -1, 1 },
4166                 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4167                 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4168                 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4169                 { 0 }
4170         };
4171         static const struct intr_info mps_trc_intr_info[] = {
4172                 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4173                 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4174                   -1, 1 },
4175                 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4176                 { 0 }
4177         };
4178         static const struct intr_info mps_stat_sram_intr_info[] = {
4179                 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4180                 { 0 }
4181         };
4182         static const struct intr_info mps_stat_tx_intr_info[] = {
4183                 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4184                 { 0 }
4185         };
4186         static const struct intr_info mps_stat_rx_intr_info[] = {
4187                 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4188                 { 0 }
4189         };
4190         static const struct intr_info mps_cls_intr_info[] = {
4191                 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4192                 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4193                 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4194                 { 0 }
4195         };
4196
4197         int fat;
4198
4199         fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4200                                     mps_rx_intr_info) +
4201               t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4202                                     mps_tx_intr_info) +
4203               t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4204                                     mps_trc_intr_info) +
4205               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4206                                     mps_stat_sram_intr_info) +
4207               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4208                                     mps_stat_tx_intr_info) +
4209               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4210                                     mps_stat_rx_intr_info) +
4211               t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4212                                     mps_cls_intr_info);
4213
4214         t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4215         t4_read_reg(adapter, MPS_INT_CAUSE_A);                    /* flush */
4216         if (fat)
4217                 t4_fatal_err(adapter);
4218 }
4219
4220 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4221                       ECC_UE_INT_CAUSE_F)
4222
4223 /*
4224  * EDC/MC interrupt handler.
4225  */
4226 static void mem_intr_handler(struct adapter *adapter, int idx)
4227 {
4228         static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4229
4230         unsigned int addr, cnt_addr, v;
4231
4232         if (idx <= MEM_EDC1) {
4233                 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4234                 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4235         } else if (idx == MEM_MC) {
4236                 if (is_t4(adapter->params.chip)) {
4237                         addr = MC_INT_CAUSE_A;
4238                         cnt_addr = MC_ECC_STATUS_A;
4239                 } else {
4240                         addr = MC_P_INT_CAUSE_A;
4241                         cnt_addr = MC_P_ECC_STATUS_A;
4242                 }
4243         } else {
4244                 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4245                 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4246         }
4247
4248         v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4249         if (v & PERR_INT_CAUSE_F)
4250                 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4251                           name[idx]);
4252         if (v & ECC_CE_INT_CAUSE_F) {
4253                 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4254
4255                 t4_edc_err_read(adapter, idx);
4256
4257                 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4258                 if (printk_ratelimit())
4259                         dev_warn(adapter->pdev_dev,
4260                                  "%u %s correctable ECC data error%s\n",
4261                                  cnt, name[idx], cnt > 1 ? "s" : "");
4262         }
4263         if (v & ECC_UE_INT_CAUSE_F)
4264                 dev_alert(adapter->pdev_dev,
4265                           "%s uncorrectable ECC data error\n", name[idx]);
4266
4267         t4_write_reg(adapter, addr, v);
4268         if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4269                 t4_fatal_err(adapter);
4270 }
4271
4272 /*
4273  * MA interrupt handler.
4274  */
4275 static void ma_intr_handler(struct adapter *adap)
4276 {
4277         u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4278
4279         if (status & MEM_PERR_INT_CAUSE_F) {
4280                 dev_alert(adap->pdev_dev,
4281                           "MA parity error, parity status %#x\n",
4282                           t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4283                 if (is_t5(adap->params.chip))
4284                         dev_alert(adap->pdev_dev,
4285                                   "MA parity error, parity status %#x\n",
4286                                   t4_read_reg(adap,
4287                                               MA_PARITY_ERROR_STATUS2_A));
4288         }
4289         if (status & MEM_WRAP_INT_CAUSE_F) {
4290                 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4291                 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4292                           "client %u to address %#x\n",
4293                           MEM_WRAP_CLIENT_NUM_G(v),
4294                           MEM_WRAP_ADDRESS_G(v) << 4);
4295         }
4296         t4_write_reg(adap, MA_INT_CAUSE_A, status);
4297         t4_fatal_err(adap);
4298 }
4299
4300 /*
4301  * SMB interrupt handler.
4302  */
4303 static void smb_intr_handler(struct adapter *adap)
4304 {
4305         static const struct intr_info smb_intr_info[] = {
4306                 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4307                 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4308                 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4309                 { 0 }
4310         };
4311
4312         if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4313                 t4_fatal_err(adap);
4314 }
4315
4316 /*
4317  * NC-SI interrupt handler.
4318  */
4319 static void ncsi_intr_handler(struct adapter *adap)
4320 {
4321         static const struct intr_info ncsi_intr_info[] = {
4322                 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4323                 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4324                 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4325                 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4326                 { 0 }
4327         };
4328
4329         if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4330                 t4_fatal_err(adap);
4331 }
4332
4333 /*
4334  * XGMAC interrupt handler.
4335  */
4336 static void xgmac_intr_handler(struct adapter *adap, int port)
4337 {
4338         u32 v, int_cause_reg;
4339
4340         if (is_t4(adap->params.chip))
4341                 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4342         else
4343                 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4344
4345         v = t4_read_reg(adap, int_cause_reg);
4346
4347         v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4348         if (!v)
4349                 return;
4350
4351         if (v & TXFIFO_PRTY_ERR_F)
4352                 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4353                           port);
4354         if (v & RXFIFO_PRTY_ERR_F)
4355                 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4356                           port);
4357         t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4358         t4_fatal_err(adap);
4359 }
4360
4361 /*
4362  * PL interrupt handler.
4363  */
4364 static void pl_intr_handler(struct adapter *adap)
4365 {
4366         static const struct intr_info pl_intr_info[] = {
4367                 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
4368                 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
4369                 { 0 }
4370         };
4371
4372         if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
4373                 t4_fatal_err(adap);
4374 }
4375
4376 #define PF_INTR_MASK (PFSW_F)
4377 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
4378                 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
4379                 CPL_SWITCH_F | SGE_F | ULP_TX_F)
4380
4381 /**
4382  *      t4_slow_intr_handler - control path interrupt handler
4383  *      @adapter: the adapter
4384  *
4385  *      T4 interrupt handler for non-data global interrupt events, e.g., errors.
4386  *      The designation 'slow' is because it involves register reads, while
4387  *      data interrupts typically don't involve any MMIOs.
4388  */
4389 int t4_slow_intr_handler(struct adapter *adapter)
4390 {
4391         u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
4392
4393         if (!(cause & GLBL_INTR_MASK))
4394                 return 0;
4395         if (cause & CIM_F)
4396                 cim_intr_handler(adapter);
4397         if (cause & MPS_F)
4398                 mps_intr_handler(adapter);
4399         if (cause & NCSI_F)
4400                 ncsi_intr_handler(adapter);
4401         if (cause & PL_F)
4402                 pl_intr_handler(adapter);
4403         if (cause & SMB_F)
4404                 smb_intr_handler(adapter);
4405         if (cause & XGMAC0_F)
4406                 xgmac_intr_handler(adapter, 0);
4407         if (cause & XGMAC1_F)
4408                 xgmac_intr_handler(adapter, 1);
4409         if (cause & XGMAC_KR0_F)
4410                 xgmac_intr_handler(adapter, 2);
4411         if (cause & XGMAC_KR1_F)
4412                 xgmac_intr_handler(adapter, 3);
4413         if (cause & PCIE_F)
4414                 pcie_intr_handler(adapter);
4415         if (cause & MC_F)
4416                 mem_intr_handler(adapter, MEM_MC);
4417         if (is_t5(adapter->params.chip) && (cause & MC1_F))
4418                 mem_intr_handler(adapter, MEM_MC1);
4419         if (cause & EDC0_F)
4420                 mem_intr_handler(adapter, MEM_EDC0);
4421         if (cause & EDC1_F)
4422                 mem_intr_handler(adapter, MEM_EDC1);
4423         if (cause & LE_F)
4424                 le_intr_handler(adapter);
4425         if (cause & TP_F)
4426                 tp_intr_handler(adapter);
4427         if (cause & MA_F)
4428                 ma_intr_handler(adapter);
4429         if (cause & PM_TX_F)
4430                 pmtx_intr_handler(adapter);
4431         if (cause & PM_RX_F)
4432                 pmrx_intr_handler(adapter);
4433         if (cause & ULP_RX_F)
4434                 ulprx_intr_handler(adapter);
4435         if (cause & CPL_SWITCH_F)
4436                 cplsw_intr_handler(adapter);
4437         if (cause & SGE_F)
4438                 sge_intr_handler(adapter);
4439         if (cause & ULP_TX_F)
4440                 ulptx_intr_handler(adapter);
4441
4442         /* Clear the interrupts just processed for which we are the master. */
4443         t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK);
4444         (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
4445         return 1;
4446 }
4447
4448 /**
4449  *      t4_intr_enable - enable interrupts
4450  *      @adapter: the adapter whose interrupts should be enabled
4451  *
4452  *      Enable PF-specific interrupts for the calling function and the top-level
4453  *      interrupt concentrator for global interrupts.  Interrupts are already
4454  *      enabled at each module, here we just enable the roots of the interrupt
4455  *      hierarchies.
4456  *
4457  *      Note: this function should be called only when the driver manages
4458  *      non PF-specific interrupts from the various HW modules.  Only one PCI
4459  *      function at a time should be doing this.
4460  */
4461 void t4_intr_enable(struct adapter *adapter)
4462 {
4463         u32 val = 0;
4464         u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4465         u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4466                         SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4467
4468         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4469                 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
4470         t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
4471                      ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
4472                      ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
4473                      ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
4474                      ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
4475                      ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
4476                      DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
4477         t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
4478         t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
4479 }
4480
4481 /**
4482  *      t4_intr_disable - disable interrupts
4483  *      @adapter: the adapter whose interrupts should be disabled
4484  *
4485  *      Disable interrupts.  We only disable the top-level interrupt
4486  *      concentrators.  The caller must be a PCI function managing global
4487  *      interrupts.
4488  */
4489 void t4_intr_disable(struct adapter *adapter)
4490 {
4491         u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4492         u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4493                         SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4494
4495         t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
4496         t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
4497 }
4498
4499 /**
4500  *      t4_config_rss_range - configure a portion of the RSS mapping table
4501  *      @adapter: the adapter
4502  *      @mbox: mbox to use for the FW command
4503  *      @viid: virtual interface whose RSS subtable is to be written
4504  *      @start: start entry in the table to write
4505  *      @n: how many table entries to write
4506  *      @rspq: values for the response queue lookup table
4507  *      @nrspq: number of values in @rspq
4508  *
4509  *      Programs the selected part of the VI's RSS mapping table with the
4510  *      provided values.  If @nrspq < @n the supplied values are used repeatedly
4511  *      until the full table range is populated.
4512  *
4513  *      The caller must ensure the values in @rspq are in the range allowed for
4514  *      @viid.
4515  */
4516 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
4517                         int start, int n, const u16 *rspq, unsigned int nrspq)
4518 {
4519         int ret;
4520         const u16 *rsp = rspq;
4521         const u16 *rsp_end = rspq + nrspq;
4522         struct fw_rss_ind_tbl_cmd cmd;
4523
4524         memset(&cmd, 0, sizeof(cmd));
4525         cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
4526                                FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4527                                FW_RSS_IND_TBL_CMD_VIID_V(viid));
4528         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
4529
4530         /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
4531         while (n > 0) {
4532                 int nq = min(n, 32);
4533                 __be32 *qp = &cmd.iq0_to_iq2;
4534
4535                 cmd.niqid = cpu_to_be16(nq);
4536                 cmd.startidx = cpu_to_be16(start);
4537
4538                 start += nq;
4539                 n -= nq;
4540
4541                 while (nq > 0) {
4542                         unsigned int v;
4543
4544                         v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
4545                         if (++rsp >= rsp_end)
4546                                 rsp = rspq;
4547                         v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
4548                         if (++rsp >= rsp_end)
4549                                 rsp = rspq;
4550                         v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
4551                         if (++rsp >= rsp_end)
4552                                 rsp = rspq;
4553
4554                         *qp++ = cpu_to_be32(v);
4555                         nq -= 3;
4556                 }
4557
4558                 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4559                 if (ret)
4560                         return ret;
4561         }
4562         return 0;
4563 }
4564
4565 /**
4566  *      t4_config_glbl_rss - configure the global RSS mode
4567  *      @adapter: the adapter
4568  *      @mbox: mbox to use for the FW command
4569  *      @mode: global RSS mode
4570  *      @flags: mode-specific flags
4571  *
4572  *      Sets the global RSS mode.
4573  */
4574 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
4575                        unsigned int flags)
4576 {
4577         struct fw_rss_glb_config_cmd c;
4578
4579         memset(&c, 0, sizeof(c));
4580         c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
4581                                     FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
4582         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4583         if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
4584                 c.u.manual.mode_pkd =
4585                         cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4586         } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
4587                 c.u.basicvirtual.mode_pkd =
4588                         cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4589                 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
4590         } else
4591                 return -EINVAL;
4592         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4593 }
4594
4595 /**
4596  *      t4_config_vi_rss - configure per VI RSS settings
4597  *      @adapter: the adapter
4598  *      @mbox: mbox to use for the FW command
4599  *      @viid: the VI id
4600  *      @flags: RSS flags
4601  *      @defq: id of the default RSS queue for the VI.
4602  *
4603  *      Configures VI-specific RSS properties.
4604  */
4605 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
4606                      unsigned int flags, unsigned int defq)
4607 {
4608         struct fw_rss_vi_config_cmd c;
4609
4610         memset(&c, 0, sizeof(c));
4611         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
4612                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4613                                    FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
4614         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4615         c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
4616                                         FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
4617         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4618 }
4619
4620 /* Read an RSS table row */
4621 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
4622 {
4623         t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
4624         return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
4625                                    5, 0, val);
4626 }
4627
4628 /**
4629  *      t4_read_rss - read the contents of the RSS mapping table
4630  *      @adapter: the adapter
4631  *      @map: holds the contents of the RSS mapping table
4632  *
4633  *      Reads the contents of the RSS hash->queue mapping table.
4634  */
4635 int t4_read_rss(struct adapter *adapter, u16 *map)
4636 {
4637         u32 val;
4638         int i, ret;
4639
4640         for (i = 0; i < RSS_NENTRIES / 2; ++i) {
4641                 ret = rd_rss_row(adapter, i, &val);
4642                 if (ret)
4643                         return ret;
4644                 *map++ = LKPTBLQUEUE0_G(val);
4645                 *map++ = LKPTBLQUEUE1_G(val);
4646         }
4647         return 0;
4648 }
4649
4650 static unsigned int t4_use_ldst(struct adapter *adap)
4651 {
4652         return (adap->flags & FW_OK) || !adap->use_bd;
4653 }
4654
4655 /**
4656  *      t4_fw_tp_pio_rw - Access TP PIO through LDST
4657  *      @adap: the adapter
4658  *      @vals: where the indirect register values are stored/written
4659  *      @nregs: how many indirect registers to read/write
4660  *      @start_idx: index of first indirect register to read/write
4661  *      @rw: Read (1) or Write (0)
4662  *
4663  *      Access TP PIO registers through LDST
4664  */
4665 static void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
4666                             unsigned int start_index, unsigned int rw)
4667 {
4668         int ret, i;
4669         int cmd = FW_LDST_ADDRSPC_TP_PIO;
4670         struct fw_ldst_cmd c;
4671
4672         for (i = 0 ; i < nregs; i++) {
4673                 memset(&c, 0, sizeof(c));
4674                 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
4675                                                 FW_CMD_REQUEST_F |
4676                                                 (rw ? FW_CMD_READ_F :
4677                                                       FW_CMD_WRITE_F) |
4678                                                 FW_LDST_CMD_ADDRSPACE_V(cmd));
4679                 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
4680
4681                 c.u.addrval.addr = cpu_to_be32(start_index + i);
4682                 c.u.addrval.val  = rw ? 0 : cpu_to_be32(vals[i]);
4683                 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
4684                 if (!ret && rw)
4685                         vals[i] = be32_to_cpu(c.u.addrval.val);
4686         }
4687 }
4688
4689 /**
4690  *      t4_read_rss_key - read the global RSS key
4691  *      @adap: the adapter
4692  *      @key: 10-entry array holding the 320-bit RSS key
4693  *
4694  *      Reads the global 320-bit RSS key.
4695  */
4696 void t4_read_rss_key(struct adapter *adap, u32 *key)
4697 {
4698         if (t4_use_ldst(adap))
4699                 t4_fw_tp_pio_rw(adap, key, 10, TP_RSS_SECRET_KEY0_A, 1);
4700         else
4701                 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4702                                  TP_RSS_SECRET_KEY0_A);
4703 }
4704
4705 /**
4706  *      t4_write_rss_key - program one of the RSS keys
4707  *      @adap: the adapter
4708  *      @key: 10-entry array holding the 320-bit RSS key
4709  *      @idx: which RSS key to write
4710  *
4711  *      Writes one of the RSS keys with the given 320-bit value.  If @idx is
4712  *      0..15 the corresponding entry in the RSS key table is written,
4713  *      otherwise the global RSS key is written.
4714  */
4715 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx)
4716 {
4717         u8 rss_key_addr_cnt = 16;
4718         u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
4719
4720         /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
4721          * allows access to key addresses 16-63 by using KeyWrAddrX
4722          * as index[5:4](upper 2) into key table
4723          */
4724         if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
4725             (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
4726                 rss_key_addr_cnt = 32;
4727
4728         if (t4_use_ldst(adap))
4729                 t4_fw_tp_pio_rw(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, 0);
4730         else
4731                 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4732                                   TP_RSS_SECRET_KEY0_A);
4733
4734         if (idx >= 0 && idx < rss_key_addr_cnt) {
4735                 if (rss_key_addr_cnt > 16)
4736                         t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4737                                      KEYWRADDRX_V(idx >> 4) |
4738                                      T6_VFWRADDR_V(idx) | KEYWREN_F);
4739                 else
4740                         t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4741                                      KEYWRADDR_V(idx) | KEYWREN_F);
4742         }
4743 }
4744
4745 /**
4746  *      t4_read_rss_pf_config - read PF RSS Configuration Table
4747  *      @adapter: the adapter
4748  *      @index: the entry in the PF RSS table to read
4749  *      @valp: where to store the returned value
4750  *
4751  *      Reads the PF RSS Configuration Table at the specified index and returns
4752  *      the value found there.
4753  */
4754 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
4755                            u32 *valp)
4756 {
4757         if (t4_use_ldst(adapter))
4758                 t4_fw_tp_pio_rw(adapter, valp, 1,
4759                                 TP_RSS_PF0_CONFIG_A + index, 1);
4760         else
4761                 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4762                                  valp, 1, TP_RSS_PF0_CONFIG_A + index);
4763 }
4764
4765 /**
4766  *      t4_read_rss_vf_config - read VF RSS Configuration Table
4767  *      @adapter: the adapter
4768  *      @index: the entry in the VF RSS table to read
4769  *      @vfl: where to store the returned VFL
4770  *      @vfh: where to store the returned VFH
4771  *
4772  *      Reads the VF RSS Configuration Table at the specified index and returns
4773  *      the (VFL, VFH) values found there.
4774  */
4775 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
4776                            u32 *vfl, u32 *vfh)
4777 {
4778         u32 vrt, mask, data;
4779
4780         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
4781                 mask = VFWRADDR_V(VFWRADDR_M);
4782                 data = VFWRADDR_V(index);
4783         } else {
4784                  mask =  T6_VFWRADDR_V(T6_VFWRADDR_M);
4785                  data = T6_VFWRADDR_V(index);
4786         }
4787
4788         /* Request that the index'th VF Table values be read into VFL/VFH.
4789          */
4790         vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
4791         vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
4792         vrt |= data | VFRDEN_F;
4793         t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
4794
4795         /* Grab the VFL/VFH values ...
4796          */
4797         if (t4_use_ldst(adapter)) {
4798                 t4_fw_tp_pio_rw(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, 1);
4799                 t4_fw_tp_pio_rw(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, 1);
4800         } else {
4801                 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4802                                  vfl, 1, TP_RSS_VFL_CONFIG_A);
4803                 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4804                                  vfh, 1, TP_RSS_VFH_CONFIG_A);
4805         }
4806 }
4807
4808 /**
4809  *      t4_read_rss_pf_map - read PF RSS Map
4810  *      @adapter: the adapter
4811  *
4812  *      Reads the PF RSS Map register and returns its value.
4813  */
4814 u32 t4_read_rss_pf_map(struct adapter *adapter)
4815 {
4816         u32 pfmap;
4817
4818         if (t4_use_ldst(adapter))
4819                 t4_fw_tp_pio_rw(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, 1);
4820         else
4821                 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4822                                  &pfmap, 1, TP_RSS_PF_MAP_A);
4823         return pfmap;
4824 }
4825
4826 /**
4827  *      t4_read_rss_pf_mask - read PF RSS Mask
4828  *      @adapter: the adapter
4829  *
4830  *      Reads the PF RSS Mask register and returns its value.
4831  */
4832 u32 t4_read_rss_pf_mask(struct adapter *adapter)
4833 {
4834         u32 pfmask;
4835
4836         if (t4_use_ldst(adapter))
4837                 t4_fw_tp_pio_rw(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, 1);
4838         else
4839                 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4840                                  &pfmask, 1, TP_RSS_PF_MSK_A);
4841         return pfmask;
4842 }
4843
4844 /**
4845  *      t4_tp_get_tcp_stats - read TP's TCP MIB counters
4846  *      @adap: the adapter
4847  *      @v4: holds the TCP/IP counter values
4848  *      @v6: holds the TCP/IPv6 counter values
4849  *
4850  *      Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
4851  *      Either @v4 or @v6 may be %NULL to skip the corresponding stats.
4852  */
4853 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
4854                          struct tp_tcp_stats *v6)
4855 {
4856         u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
4857
4858 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
4859 #define STAT(x)     val[STAT_IDX(x)]
4860 #define STAT64(x)   (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
4861
4862         if (v4) {
4863                 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4864                                  ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST_A);
4865                 v4->tcp_out_rsts = STAT(OUT_RST);
4866                 v4->tcp_in_segs  = STAT64(IN_SEG);
4867                 v4->tcp_out_segs = STAT64(OUT_SEG);
4868                 v4->tcp_retrans_segs = STAT64(RXT_SEG);
4869         }
4870         if (v6) {
4871                 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4872                                  ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST_A);
4873                 v6->tcp_out_rsts = STAT(OUT_RST);
4874                 v6->tcp_in_segs  = STAT64(IN_SEG);
4875                 v6->tcp_out_segs = STAT64(OUT_SEG);
4876                 v6->tcp_retrans_segs = STAT64(RXT_SEG);
4877         }
4878 #undef STAT64
4879 #undef STAT
4880 #undef STAT_IDX
4881 }
4882
4883 /**
4884  *      t4_tp_get_err_stats - read TP's error MIB counters
4885  *      @adap: the adapter
4886  *      @st: holds the counter values
4887  *
4888  *      Returns the values of TP's error counters.
4889  */
4890 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st)
4891 {
4892         int nchan = adap->params.arch.nchan;
4893
4894         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4895                          st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A);
4896         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4897                          st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A);
4898         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4899                          st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A);
4900         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4901                          st->tnl_cong_drops, nchan, TP_MIB_TNL_CNG_DROP_0_A);
4902         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4903                          st->ofld_chan_drops, nchan, TP_MIB_OFD_CHN_DROP_0_A);
4904         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4905                          st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A);
4906         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4907                          st->ofld_vlan_drops, nchan, TP_MIB_OFD_VLN_DROP_0_A);
4908         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4909                          st->tcp6_in_errs, nchan, TP_MIB_TCP_V6IN_ERR_0_A);
4910
4911         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4912                          &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A);
4913 }
4914
4915 /**
4916  *      t4_tp_get_cpl_stats - read TP's CPL MIB counters
4917  *      @adap: the adapter
4918  *      @st: holds the counter values
4919  *
4920  *      Returns the values of TP's CPL counters.
4921  */
4922 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st)
4923 {
4924         int nchan = adap->params.arch.nchan;
4925
4926         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->req,
4927                          nchan, TP_MIB_CPL_IN_REQ_0_A);
4928         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->rsp,
4929                          nchan, TP_MIB_CPL_OUT_RSP_0_A);
4930
4931 }
4932
4933 /**
4934  *      t4_tp_get_rdma_stats - read TP's RDMA MIB counters
4935  *      @adap: the adapter
4936  *      @st: holds the counter values
4937  *
4938  *      Returns the values of TP's RDMA counters.
4939  */
4940 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st)
4941 {
4942         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->rqe_dfr_pkt,
4943                          2, TP_MIB_RQE_DFR_PKT_A);
4944 }
4945
4946 /**
4947  *      t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
4948  *      @adap: the adapter
4949  *      @idx: the port index
4950  *      @st: holds the counter values
4951  *
4952  *      Returns the values of TP's FCoE counters for the selected port.
4953  */
4954 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
4955                        struct tp_fcoe_stats *st)
4956 {
4957         u32 val[2];
4958
4959         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_ddp,
4960                          1, TP_MIB_FCOE_DDP_0_A + idx);
4961         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_drop,
4962                          1, TP_MIB_FCOE_DROP_0_A + idx);
4963         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4964                          2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx);
4965         st->octets_ddp = ((u64)val[0] << 32) | val[1];
4966 }
4967
4968 /**
4969  *      t4_get_usm_stats - read TP's non-TCP DDP MIB counters
4970  *      @adap: the adapter
4971  *      @st: holds the counter values
4972  *
4973  *      Returns the values of TP's counters for non-TCP directly-placed packets.
4974  */
4975 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st)
4976 {
4977         u32 val[4];
4978
4979         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, 4,
4980                          TP_MIB_USM_PKTS_A);
4981         st->frames = val[0];
4982         st->drops = val[1];
4983         st->octets = ((u64)val[2] << 32) | val[3];
4984 }
4985
4986 /**
4987  *      t4_read_mtu_tbl - returns the values in the HW path MTU table
4988  *      @adap: the adapter
4989  *      @mtus: where to store the MTU values
4990  *      @mtu_log: where to store the MTU base-2 log (may be %NULL)
4991  *
4992  *      Reads the HW path MTU table.
4993  */
4994 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
4995 {
4996         u32 v;
4997         int i;
4998
4999         for (i = 0; i < NMTUS; ++i) {
5000                 t4_write_reg(adap, TP_MTU_TABLE_A,
5001                              MTUINDEX_V(0xff) | MTUVALUE_V(i));
5002                 v = t4_read_reg(adap, TP_MTU_TABLE_A);
5003                 mtus[i] = MTUVALUE_G(v);
5004                 if (mtu_log)
5005                         mtu_log[i] = MTUWIDTH_G(v);
5006         }
5007 }
5008
5009 /**
5010  *      t4_read_cong_tbl - reads the congestion control table
5011  *      @adap: the adapter
5012  *      @incr: where to store the alpha values
5013  *
5014  *      Reads the additive increments programmed into the HW congestion
5015  *      control table.
5016  */
5017 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5018 {
5019         unsigned int mtu, w;
5020
5021         for (mtu = 0; mtu < NMTUS; ++mtu)
5022                 for (w = 0; w < NCCTRL_WIN; ++w) {
5023                         t4_write_reg(adap, TP_CCTRL_TABLE_A,
5024                                      ROWINDEX_V(0xffff) | (mtu << 5) | w);
5025                         incr[mtu][w] = (u16)t4_read_reg(adap,
5026                                                 TP_CCTRL_TABLE_A) & 0x1fff;
5027                 }
5028 }
5029
5030 /**
5031  *      t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5032  *      @adap: the adapter
5033  *      @addr: the indirect TP register address
5034  *      @mask: specifies the field within the register to modify
5035  *      @val: new value for the field
5036  *
5037  *      Sets a field of an indirect TP register to the given value.
5038  */
5039 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5040                             unsigned int mask, unsigned int val)
5041 {
5042         t4_write_reg(adap, TP_PIO_ADDR_A, addr);
5043         val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
5044         t4_write_reg(adap, TP_PIO_DATA_A, val);
5045 }
5046
5047 /**
5048  *      init_cong_ctrl - initialize congestion control parameters
5049  *      @a: the alpha values for congestion control
5050  *      @b: the beta values for congestion control
5051  *
5052  *      Initialize the congestion control parameters.
5053  */
5054 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5055 {
5056         a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5057         a[9] = 2;
5058         a[10] = 3;
5059         a[11] = 4;
5060         a[12] = 5;
5061         a[13] = 6;
5062         a[14] = 7;
5063         a[15] = 8;
5064         a[16] = 9;
5065         a[17] = 10;
5066         a[18] = 14;
5067         a[19] = 17;
5068         a[20] = 21;
5069         a[21] = 25;
5070         a[22] = 30;
5071         a[23] = 35;
5072         a[24] = 45;
5073         a[25] = 60;
5074         a[26] = 80;
5075         a[27] = 100;
5076         a[28] = 200;
5077         a[29] = 300;
5078         a[30] = 400;
5079         a[31] = 500;
5080
5081         b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5082         b[9] = b[10] = 1;
5083         b[11] = b[12] = 2;
5084         b[13] = b[14] = b[15] = b[16] = 3;
5085         b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5086         b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5087         b[28] = b[29] = 6;
5088         b[30] = b[31] = 7;
5089 }
5090
5091 /* The minimum additive increment value for the congestion control table */
5092 #define CC_MIN_INCR 2U
5093
5094 /**
5095  *      t4_load_mtus - write the MTU and congestion control HW tables
5096  *      @adap: the adapter
5097  *      @mtus: the values for the MTU table
5098  *      @alpha: the values for the congestion control alpha parameter
5099  *      @beta: the values for the congestion control beta parameter
5100  *
5101  *      Write the HW MTU table with the supplied MTUs and the high-speed
5102  *      congestion control table with the supplied alpha, beta, and MTUs.
5103  *      We write the two tables together because the additive increments
5104  *      depend on the MTUs.
5105  */
5106 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5107                   const unsigned short *alpha, const unsigned short *beta)
5108 {
5109         static const unsigned int avg_pkts[NCCTRL_WIN] = {
5110                 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5111                 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5112                 28672, 40960, 57344, 81920, 114688, 163840, 229376
5113         };
5114
5115         unsigned int i, w;
5116
5117         for (i = 0; i < NMTUS; ++i) {
5118                 unsigned int mtu = mtus[i];
5119                 unsigned int log2 = fls(mtu);
5120
5121                 if (!(mtu & ((1 << log2) >> 2)))     /* round */
5122                         log2--;
5123                 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5124                              MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5125
5126                 for (w = 0; w < NCCTRL_WIN; ++w) {
5127                         unsigned int inc;
5128
5129                         inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5130                                   CC_MIN_INCR);
5131
5132                         t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5133                                      (w << 16) | (beta[w] << 13) | inc);
5134                 }
5135         }
5136 }
5137
5138 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5139  * clocks.  The formula is
5140  *
5141  * bytes/s = bytes256 * 256 * ClkFreq / 4096
5142  *
5143  * which is equivalent to
5144  *
5145  * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5146  */
5147 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5148 {
5149         u64 v = bytes256 * adap->params.vpd.cclk;
5150
5151         return v * 62 + v / 2;
5152 }
5153
5154 /**
5155  *      t4_get_chan_txrate - get the current per channel Tx rates
5156  *      @adap: the adapter
5157  *      @nic_rate: rates for NIC traffic
5158  *      @ofld_rate: rates for offloaded traffic
5159  *
5160  *      Return the current Tx rates in bytes/s for NIC and offloaded traffic
5161  *      for each channel.
5162  */
5163 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5164 {
5165         u32 v;
5166
5167         v = t4_read_reg(adap, TP_TX_TRATE_A);
5168         nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5169         nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5170         if (adap->params.arch.nchan == NCHAN) {
5171                 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5172                 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5173         }
5174
5175         v = t4_read_reg(adap, TP_TX_ORATE_A);
5176         ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5177         ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5178         if (adap->params.arch.nchan == NCHAN) {
5179                 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5180                 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5181         }
5182 }
5183
5184 /**
5185  *      t4_set_trace_filter - configure one of the tracing filters
5186  *      @adap: the adapter
5187  *      @tp: the desired trace filter parameters
5188  *      @idx: which filter to configure
5189  *      @enable: whether to enable or disable the filter
5190  *
5191  *      Configures one of the tracing filters available in HW.  If @enable is
5192  *      %0 @tp is not examined and may be %NULL. The user is responsible to
5193  *      set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5194  */
5195 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5196                         int idx, int enable)
5197 {
5198         int i, ofst = idx * 4;
5199         u32 data_reg, mask_reg, cfg;
5200         u32 multitrc = TRCMULTIFILTER_F;
5201
5202         if (!enable) {
5203                 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5204                 return 0;
5205         }
5206
5207         cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5208         if (cfg & TRCMULTIFILTER_F) {
5209                 /* If multiple tracers are enabled, then maximum
5210                  * capture size is 2.5KB (FIFO size of a single channel)
5211                  * minus 2 flits for CPL_TRACE_PKT header.
5212                  */
5213                 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5214                         return -EINVAL;
5215         } else {
5216                 /* If multiple tracers are disabled, to avoid deadlocks
5217                  * maximum packet capture size of 9600 bytes is recommended.
5218                  * Also in this mode, only trace0 can be enabled and running.
5219                  */
5220                 multitrc = 0;
5221                 if (tp->snap_len > 9600 || idx)
5222                         return -EINVAL;
5223         }
5224
5225         if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5226             tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5227             tp->min_len > TFMINPKTSIZE_M)
5228                 return -EINVAL;
5229
5230         /* stop the tracer we'll be changing */
5231         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5232
5233         idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5234         data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
5235         mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
5236
5237         for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5238                 t4_write_reg(adap, data_reg, tp->data[i]);
5239                 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5240         }
5241         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
5242                      TFCAPTUREMAX_V(tp->snap_len) |
5243                      TFMINPKTSIZE_V(tp->min_len));
5244         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
5245                      TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
5246                      (is_t4(adap->params.chip) ?
5247                      TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
5248                      T5_TFPORT_V(tp->port) | T5_TFEN_F |
5249                      T5_TFINVERTMATCH_V(tp->invert)));
5250
5251         return 0;
5252 }
5253
5254 /**
5255  *      t4_get_trace_filter - query one of the tracing filters
5256  *      @adap: the adapter
5257  *      @tp: the current trace filter parameters
5258  *      @idx: which trace filter to query
5259  *      @enabled: non-zero if the filter is enabled
5260  *
5261  *      Returns the current settings of one of the HW tracing filters.
5262  */
5263 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
5264                          int *enabled)
5265 {
5266         u32 ctla, ctlb;
5267         int i, ofst = idx * 4;
5268         u32 data_reg, mask_reg;
5269
5270         ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
5271         ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
5272
5273         if (is_t4(adap->params.chip)) {
5274                 *enabled = !!(ctla & TFEN_F);
5275                 tp->port =  TFPORT_G(ctla);
5276                 tp->invert = !!(ctla & TFINVERTMATCH_F);
5277         } else {
5278                 *enabled = !!(ctla & T5_TFEN_F);
5279                 tp->port = T5_TFPORT_G(ctla);
5280                 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
5281         }
5282         tp->snap_len = TFCAPTUREMAX_G(ctlb);
5283         tp->min_len = TFMINPKTSIZE_G(ctlb);
5284         tp->skip_ofst = TFOFFSET_G(ctla);
5285         tp->skip_len = TFLENGTH_G(ctla);
5286
5287         ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
5288         data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
5289         mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
5290
5291         for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5292                 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
5293                 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
5294         }
5295 }
5296
5297 /**
5298  *      t4_pmtx_get_stats - returns the HW stats from PMTX
5299  *      @adap: the adapter
5300  *      @cnt: where to store the count statistics
5301  *      @cycles: where to store the cycle statistics
5302  *
5303  *      Returns performance statistics from PMTX.
5304  */
5305 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5306 {
5307         int i;
5308         u32 data[2];
5309
5310         for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5311                 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
5312                 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
5313                 if (is_t4(adap->params.chip)) {
5314                         cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
5315                 } else {
5316                         t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
5317                                          PM_TX_DBG_DATA_A, data, 2,
5318                                          PM_TX_DBG_STAT_MSB_A);
5319                         cycles[i] = (((u64)data[0] << 32) | data[1]);
5320                 }
5321         }
5322 }
5323
5324 /**
5325  *      t4_pmrx_get_stats - returns the HW stats from PMRX
5326  *      @adap: the adapter
5327  *      @cnt: where to store the count statistics
5328  *      @cycles: where to store the cycle statistics
5329  *
5330  *      Returns performance statistics from PMRX.
5331  */
5332 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5333 {
5334         int i;
5335         u32 data[2];
5336
5337         for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5338                 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
5339                 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
5340                 if (is_t4(adap->params.chip)) {
5341                         cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
5342                 } else {
5343                         t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
5344                                          PM_RX_DBG_DATA_A, data, 2,
5345                                          PM_RX_DBG_STAT_MSB_A);
5346                         cycles[i] = (((u64)data[0] << 32) | data[1]);
5347                 }
5348         }
5349 }
5350
5351 /**
5352  *      t4_get_mps_bg_map - return the buffer groups associated with a port
5353  *      @adap: the adapter
5354  *      @idx: the port index
5355  *
5356  *      Returns a bitmap indicating which MPS buffer groups are associated
5357  *      with the given port.  Bit i is set if buffer group i is used by the
5358  *      port.
5359  */
5360 unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
5361 {
5362         u32 n = NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
5363
5364         if (n == 0)
5365                 return idx == 0 ? 0xf : 0;
5366         /* In T6 (which is a 2 port card),
5367          * port 0 is mapped to channel 0 and port 1 is mapped to channel 1.
5368          * For 2 port T4/T5 adapter,
5369          * port 0 is mapped to channel 0 and 1,
5370          * port 1 is mapped to channel 2 and 3.
5371          */
5372         if ((n == 1) &&
5373             (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5))
5374                 return idx < 2 ? (3 << (2 * idx)) : 0;
5375         return 1 << idx;
5376 }
5377
5378 /**
5379  *      t4_get_port_type_description - return Port Type string description
5380  *      @port_type: firmware Port Type enumeration
5381  */
5382 const char *t4_get_port_type_description(enum fw_port_type port_type)
5383 {
5384         static const char *const port_type_description[] = {
5385                 "R XFI",
5386                 "R XAUI",
5387                 "T SGMII",
5388                 "T XFI",
5389                 "T XAUI",
5390                 "KX4",
5391                 "CX4",
5392                 "KX",
5393                 "KR",
5394                 "R SFP+",
5395                 "KR/KX",
5396                 "KR/KX/KX4",
5397                 "R QSFP_10G",
5398                 "R QSA",
5399                 "R QSFP",
5400                 "R BP40_BA",
5401         };
5402
5403         if (port_type < ARRAY_SIZE(port_type_description))
5404                 return port_type_description[port_type];
5405         return "UNKNOWN";
5406 }
5407
5408 /**
5409  *      t4_get_port_stats_offset - collect port stats relative to a previous
5410  *                                 snapshot
5411  *      @adap: The adapter
5412  *      @idx: The port
5413  *      @stats: Current stats to fill
5414  *      @offset: Previous stats snapshot
5415  */
5416 void t4_get_port_stats_offset(struct adapter *adap, int idx,
5417                               struct port_stats *stats,
5418                               struct port_stats *offset)
5419 {
5420         u64 *s, *o;
5421         int i;
5422
5423         t4_get_port_stats(adap, idx, stats);
5424         for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
5425                         i < (sizeof(struct port_stats) / sizeof(u64));
5426                         i++, s++, o++)
5427                 *s -= *o;
5428 }
5429
5430 /**
5431  *      t4_get_port_stats - collect port statistics
5432  *      @adap: the adapter
5433  *      @idx: the port index
5434  *      @p: the stats structure to fill
5435  *
5436  *      Collect statistics related to the given port from HW.
5437  */
5438 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
5439 {
5440         u32 bgmap = t4_get_mps_bg_map(adap, idx);
5441
5442 #define GET_STAT(name) \
5443         t4_read_reg64(adap, \
5444         (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
5445         T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
5446 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5447
5448         p->tx_octets           = GET_STAT(TX_PORT_BYTES);
5449         p->tx_frames           = GET_STAT(TX_PORT_FRAMES);
5450         p->tx_bcast_frames     = GET_STAT(TX_PORT_BCAST);
5451         p->tx_mcast_frames     = GET_STAT(TX_PORT_MCAST);
5452         p->tx_ucast_frames     = GET_STAT(TX_PORT_UCAST);
5453         p->tx_error_frames     = GET_STAT(TX_PORT_ERROR);
5454         p->tx_frames_64        = GET_STAT(TX_PORT_64B);
5455         p->tx_frames_65_127    = GET_STAT(TX_PORT_65B_127B);
5456         p->tx_frames_128_255   = GET_STAT(TX_PORT_128B_255B);
5457         p->tx_frames_256_511   = GET_STAT(TX_PORT_256B_511B);
5458         p->tx_frames_512_1023  = GET_STAT(TX_PORT_512B_1023B);
5459         p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
5460         p->tx_frames_1519_max  = GET_STAT(TX_PORT_1519B_MAX);
5461         p->tx_drop             = GET_STAT(TX_PORT_DROP);
5462         p->tx_pause            = GET_STAT(TX_PORT_PAUSE);
5463         p->tx_ppp0             = GET_STAT(TX_PORT_PPP0);
5464         p->tx_ppp1             = GET_STAT(TX_PORT_PPP1);
5465         p->tx_ppp2             = GET_STAT(TX_PORT_PPP2);
5466         p->tx_ppp3             = GET_STAT(TX_PORT_PPP3);
5467         p->tx_ppp4             = GET_STAT(TX_PORT_PPP4);
5468         p->tx_ppp5             = GET_STAT(TX_PORT_PPP5);
5469         p->tx_ppp6             = GET_STAT(TX_PORT_PPP6);
5470         p->tx_ppp7             = GET_STAT(TX_PORT_PPP7);
5471
5472         p->rx_octets           = GET_STAT(RX_PORT_BYTES);
5473         p->rx_frames           = GET_STAT(RX_PORT_FRAMES);
5474         p->rx_bcast_frames     = GET_STAT(RX_PORT_BCAST);
5475         p->rx_mcast_frames     = GET_STAT(RX_PORT_MCAST);
5476         p->rx_ucast_frames     = GET_STAT(RX_PORT_UCAST);
5477         p->rx_too_long         = GET_STAT(RX_PORT_MTU_ERROR);
5478         p->rx_jabber           = GET_STAT(RX_PORT_MTU_CRC_ERROR);
5479         p->rx_fcs_err          = GET_STAT(RX_PORT_CRC_ERROR);
5480         p->rx_len_err          = GET_STAT(RX_PORT_LEN_ERROR);
5481         p->rx_symbol_err       = GET_STAT(RX_PORT_SYM_ERROR);
5482         p->rx_runt             = GET_STAT(RX_PORT_LESS_64B);
5483         p->rx_frames_64        = GET_STAT(RX_PORT_64B);
5484         p->rx_frames_65_127    = GET_STAT(RX_PORT_65B_127B);
5485         p->rx_frames_128_255   = GET_STAT(RX_PORT_128B_255B);
5486         p->rx_frames_256_511   = GET_STAT(RX_PORT_256B_511B);
5487         p->rx_frames_512_1023  = GET_STAT(RX_PORT_512B_1023B);
5488         p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
5489         p->rx_frames_1519_max  = GET_STAT(RX_PORT_1519B_MAX);
5490         p->rx_pause            = GET_STAT(RX_PORT_PAUSE);
5491         p->rx_ppp0             = GET_STAT(RX_PORT_PPP0);
5492         p->rx_ppp1             = GET_STAT(RX_PORT_PPP1);
5493         p->rx_ppp2             = GET_STAT(RX_PORT_PPP2);
5494         p->rx_ppp3             = GET_STAT(RX_PORT_PPP3);
5495         p->rx_ppp4             = GET_STAT(RX_PORT_PPP4);
5496         p->rx_ppp5             = GET_STAT(RX_PORT_PPP5);
5497         p->rx_ppp6             = GET_STAT(RX_PORT_PPP6);
5498         p->rx_ppp7             = GET_STAT(RX_PORT_PPP7);
5499
5500         p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
5501         p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
5502         p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
5503         p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
5504         p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
5505         p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
5506         p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
5507         p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
5508
5509 #undef GET_STAT
5510 #undef GET_STAT_COM
5511 }
5512
5513 /**
5514  *      t4_get_lb_stats - collect loopback port statistics
5515  *      @adap: the adapter
5516  *      @idx: the loopback port index
5517  *      @p: the stats structure to fill
5518  *
5519  *      Return HW statistics for the given loopback port.
5520  */
5521 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
5522 {
5523         u32 bgmap = t4_get_mps_bg_map(adap, idx);
5524
5525 #define GET_STAT(name) \
5526         t4_read_reg64(adap, \
5527         (is_t4(adap->params.chip) ? \
5528         PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
5529         T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
5530 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5531
5532         p->octets           = GET_STAT(BYTES);
5533         p->frames           = GET_STAT(FRAMES);
5534         p->bcast_frames     = GET_STAT(BCAST);
5535         p->mcast_frames     = GET_STAT(MCAST);
5536         p->ucast_frames     = GET_STAT(UCAST);
5537         p->error_frames     = GET_STAT(ERROR);
5538
5539         p->frames_64        = GET_STAT(64B);
5540         p->frames_65_127    = GET_STAT(65B_127B);
5541         p->frames_128_255   = GET_STAT(128B_255B);
5542         p->frames_256_511   = GET_STAT(256B_511B);
5543         p->frames_512_1023  = GET_STAT(512B_1023B);
5544         p->frames_1024_1518 = GET_STAT(1024B_1518B);
5545         p->frames_1519_max  = GET_STAT(1519B_MAX);
5546         p->drop             = GET_STAT(DROP_FRAMES);
5547
5548         p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
5549         p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
5550         p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
5551         p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
5552         p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
5553         p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
5554         p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
5555         p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
5556
5557 #undef GET_STAT
5558 #undef GET_STAT_COM
5559 }
5560
5561 /*     t4_mk_filtdelwr - create a delete filter WR
5562  *     @ftid: the filter ID
5563  *     @wr: the filter work request to populate
5564  *     @qid: ingress queue to receive the delete notification
5565  *
5566  *     Creates a filter work request to delete the supplied filter.  If @qid is
5567  *     negative the delete notification is suppressed.
5568  */
5569 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
5570 {
5571         memset(wr, 0, sizeof(*wr));
5572         wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
5573         wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
5574         wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
5575                                     FW_FILTER_WR_NOREPLY_V(qid < 0));
5576         wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
5577         if (qid >= 0)
5578                 wr->rx_chan_rx_rpl_iq =
5579                         cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
5580 }
5581
5582 #define INIT_CMD(var, cmd, rd_wr) do { \
5583         (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
5584                                         FW_CMD_REQUEST_F | \
5585                                         FW_CMD_##rd_wr##_F); \
5586         (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
5587 } while (0)
5588
5589 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
5590                           u32 addr, u32 val)
5591 {
5592         u32 ldst_addrspace;
5593         struct fw_ldst_cmd c;
5594
5595         memset(&c, 0, sizeof(c));
5596         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
5597         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5598                                         FW_CMD_REQUEST_F |
5599                                         FW_CMD_WRITE_F |
5600                                         ldst_addrspace);
5601         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5602         c.u.addrval.addr = cpu_to_be32(addr);
5603         c.u.addrval.val = cpu_to_be32(val);
5604
5605         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5606 }
5607
5608 /**
5609  *      t4_mdio_rd - read a PHY register through MDIO
5610  *      @adap: the adapter
5611  *      @mbox: mailbox to use for the FW command
5612  *      @phy_addr: the PHY address
5613  *      @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5614  *      @reg: the register to read
5615  *      @valp: where to store the value
5616  *
5617  *      Issues a FW command through the given mailbox to read a PHY register.
5618  */
5619 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5620                unsigned int mmd, unsigned int reg, u16 *valp)
5621 {
5622         int ret;
5623         u32 ldst_addrspace;
5624         struct fw_ldst_cmd c;
5625
5626         memset(&c, 0, sizeof(c));
5627         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5628         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5629                                         FW_CMD_REQUEST_F | FW_CMD_READ_F |
5630                                         ldst_addrspace);
5631         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5632         c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5633                                          FW_LDST_CMD_MMD_V(mmd));
5634         c.u.mdio.raddr = cpu_to_be16(reg);
5635
5636         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5637         if (ret == 0)
5638                 *valp = be16_to_cpu(c.u.mdio.rval);
5639         return ret;
5640 }
5641
5642 /**
5643  *      t4_mdio_wr - write a PHY register through MDIO
5644  *      @adap: the adapter
5645  *      @mbox: mailbox to use for the FW command
5646  *      @phy_addr: the PHY address
5647  *      @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5648  *      @reg: the register to write
5649  *      @valp: value to write
5650  *
5651  *      Issues a FW command through the given mailbox to write a PHY register.
5652  */
5653 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5654                unsigned int mmd, unsigned int reg, u16 val)
5655 {
5656         u32 ldst_addrspace;
5657         struct fw_ldst_cmd c;
5658
5659         memset(&c, 0, sizeof(c));
5660         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5661         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5662                                         FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5663                                         ldst_addrspace);
5664         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5665         c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5666                                          FW_LDST_CMD_MMD_V(mmd));
5667         c.u.mdio.raddr = cpu_to_be16(reg);
5668         c.u.mdio.rval = cpu_to_be16(val);
5669
5670         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5671 }
5672
5673 /**
5674  *      t4_sge_decode_idma_state - decode the idma state
5675  *      @adap: the adapter
5676  *      @state: the state idma is stuck in
5677  */
5678 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
5679 {
5680         static const char * const t4_decode[] = {
5681                 "IDMA_IDLE",
5682                 "IDMA_PUSH_MORE_CPL_FIFO",
5683                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5684                 "Not used",
5685                 "IDMA_PHYSADDR_SEND_PCIEHDR",
5686                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5687                 "IDMA_PHYSADDR_SEND_PAYLOAD",
5688                 "IDMA_SEND_FIFO_TO_IMSG",
5689                 "IDMA_FL_REQ_DATA_FL_PREP",
5690                 "IDMA_FL_REQ_DATA_FL",
5691                 "IDMA_FL_DROP",
5692                 "IDMA_FL_H_REQ_HEADER_FL",
5693                 "IDMA_FL_H_SEND_PCIEHDR",
5694                 "IDMA_FL_H_PUSH_CPL_FIFO",
5695                 "IDMA_FL_H_SEND_CPL",
5696                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5697                 "IDMA_FL_H_SEND_IP_HDR",
5698                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5699                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5700                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5701                 "IDMA_FL_D_SEND_PCIEHDR",
5702                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5703                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5704                 "IDMA_FL_SEND_PCIEHDR",
5705                 "IDMA_FL_PUSH_CPL_FIFO",
5706                 "IDMA_FL_SEND_CPL",
5707                 "IDMA_FL_SEND_PAYLOAD_FIRST",
5708                 "IDMA_FL_SEND_PAYLOAD",
5709                 "IDMA_FL_REQ_NEXT_DATA_FL",
5710                 "IDMA_FL_SEND_NEXT_PCIEHDR",
5711                 "IDMA_FL_SEND_PADDING",
5712                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5713                 "IDMA_FL_SEND_FIFO_TO_IMSG",
5714                 "IDMA_FL_REQ_DATAFL_DONE",
5715                 "IDMA_FL_REQ_HEADERFL_DONE",
5716         };
5717         static const char * const t5_decode[] = {
5718                 "IDMA_IDLE",
5719                 "IDMA_ALMOST_IDLE",
5720                 "IDMA_PUSH_MORE_CPL_FIFO",
5721                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5722                 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
5723                 "IDMA_PHYSADDR_SEND_PCIEHDR",
5724                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5725                 "IDMA_PHYSADDR_SEND_PAYLOAD",
5726                 "IDMA_SEND_FIFO_TO_IMSG",
5727                 "IDMA_FL_REQ_DATA_FL",
5728                 "IDMA_FL_DROP",
5729                 "IDMA_FL_DROP_SEND_INC",
5730                 "IDMA_FL_H_REQ_HEADER_FL",
5731                 "IDMA_FL_H_SEND_PCIEHDR",
5732                 "IDMA_FL_H_PUSH_CPL_FIFO",
5733                 "IDMA_FL_H_SEND_CPL",
5734                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5735                 "IDMA_FL_H_SEND_IP_HDR",
5736                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5737                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5738                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5739                 "IDMA_FL_D_SEND_PCIEHDR",
5740                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5741                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5742                 "IDMA_FL_SEND_PCIEHDR",
5743                 "IDMA_FL_PUSH_CPL_FIFO",
5744                 "IDMA_FL_SEND_CPL",
5745                 "IDMA_FL_SEND_PAYLOAD_FIRST",
5746                 "IDMA_FL_SEND_PAYLOAD",
5747                 "IDMA_FL_REQ_NEXT_DATA_FL",
5748                 "IDMA_FL_SEND_NEXT_PCIEHDR",
5749                 "IDMA_FL_SEND_PADDING",
5750                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5751         };
5752         static const char * const t6_decode[] = {
5753                 "IDMA_IDLE",
5754                 "IDMA_PUSH_MORE_CPL_FIFO",
5755                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5756                 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
5757                 "IDMA_PHYSADDR_SEND_PCIEHDR",
5758                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5759                 "IDMA_PHYSADDR_SEND_PAYLOAD",
5760                 "IDMA_FL_REQ_DATA_FL",
5761                 "IDMA_FL_DROP",
5762                 "IDMA_FL_DROP_SEND_INC",
5763                 "IDMA_FL_H_REQ_HEADER_FL",
5764                 "IDMA_FL_H_SEND_PCIEHDR",
5765                 "IDMA_FL_H_PUSH_CPL_FIFO",
5766                 "IDMA_FL_H_SEND_CPL",
5767                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5768                 "IDMA_FL_H_SEND_IP_HDR",
5769                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5770                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5771                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5772                 "IDMA_FL_D_SEND_PCIEHDR",
5773                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5774                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5775                 "IDMA_FL_SEND_PCIEHDR",
5776                 "IDMA_FL_PUSH_CPL_FIFO",
5777                 "IDMA_FL_SEND_CPL",
5778                 "IDMA_FL_SEND_PAYLOAD_FIRST",
5779                 "IDMA_FL_SEND_PAYLOAD",
5780                 "IDMA_FL_REQ_NEXT_DATA_FL",
5781                 "IDMA_FL_SEND_NEXT_PCIEHDR",
5782                 "IDMA_FL_SEND_PADDING",
5783                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5784         };
5785         static const u32 sge_regs[] = {
5786                 SGE_DEBUG_DATA_LOW_INDEX_2_A,
5787                 SGE_DEBUG_DATA_LOW_INDEX_3_A,
5788                 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
5789         };
5790         const char **sge_idma_decode;
5791         int sge_idma_decode_nstates;
5792         int i;
5793         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
5794
5795         /* Select the right set of decode strings to dump depending on the
5796          * adapter chip type.
5797          */
5798         switch (chip_version) {
5799         case CHELSIO_T4:
5800                 sge_idma_decode = (const char **)t4_decode;
5801                 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
5802                 break;
5803
5804         case CHELSIO_T5:
5805                 sge_idma_decode = (const char **)t5_decode;
5806                 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
5807                 break;
5808
5809         case CHELSIO_T6:
5810                 sge_idma_decode = (const char **)t6_decode;
5811                 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
5812                 break;
5813
5814         default:
5815                 dev_err(adapter->pdev_dev,
5816                         "Unsupported chip version %d\n", chip_version);
5817                 return;
5818         }
5819
5820         if (is_t4(adapter->params.chip)) {
5821                 sge_idma_decode = (const char **)t4_decode;
5822                 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
5823         } else {
5824                 sge_idma_decode = (const char **)t5_decode;
5825                 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
5826         }
5827
5828         if (state < sge_idma_decode_nstates)
5829                 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
5830         else
5831                 CH_WARN(adapter, "idma state %d unknown\n", state);
5832
5833         for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
5834                 CH_WARN(adapter, "SGE register %#x value %#x\n",
5835                         sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
5836 }
5837
5838 /**
5839  *      t4_sge_ctxt_flush - flush the SGE context cache
5840  *      @adap: the adapter
5841  *      @mbox: mailbox to use for the FW command
5842  *
5843  *      Issues a FW command through the given mailbox to flush the
5844  *      SGE context cache.
5845  */
5846 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
5847 {
5848         int ret;
5849         u32 ldst_addrspace;
5850         struct fw_ldst_cmd c;
5851
5852         memset(&c, 0, sizeof(c));
5853         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_SGE_EGRC);
5854         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5855                                         FW_CMD_REQUEST_F | FW_CMD_READ_F |
5856                                         ldst_addrspace);
5857         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5858         c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
5859
5860         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5861         return ret;
5862 }
5863
5864 /**
5865  *      t4_fw_hello - establish communication with FW
5866  *      @adap: the adapter
5867  *      @mbox: mailbox to use for the FW command
5868  *      @evt_mbox: mailbox to receive async FW events
5869  *      @master: specifies the caller's willingness to be the device master
5870  *      @state: returns the current device state (if non-NULL)
5871  *
5872  *      Issues a command to establish communication with FW.  Returns either
5873  *      an error (negative integer) or the mailbox of the Master PF.
5874  */
5875 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
5876                 enum dev_master master, enum dev_state *state)
5877 {
5878         int ret;
5879         struct fw_hello_cmd c;
5880         u32 v;
5881         unsigned int master_mbox;
5882         int retries = FW_CMD_HELLO_RETRIES;
5883
5884 retry:
5885         memset(&c, 0, sizeof(c));
5886         INIT_CMD(c, HELLO, WRITE);
5887         c.err_to_clearinit = cpu_to_be32(
5888                 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
5889                 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
5890                 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
5891                                         mbox : FW_HELLO_CMD_MBMASTER_M) |
5892                 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
5893                 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
5894                 FW_HELLO_CMD_CLEARINIT_F);
5895
5896         /*
5897          * Issue the HELLO command to the firmware.  If it's not successful
5898          * but indicates that we got a "busy" or "timeout" condition, retry
5899          * the HELLO until we exhaust our retry limit.  If we do exceed our
5900          * retry limit, check to see if the firmware left us any error
5901          * information and report that if so.
5902          */
5903         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5904         if (ret < 0) {
5905                 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
5906                         goto retry;
5907                 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
5908                         t4_report_fw_error(adap);
5909                 return ret;
5910         }
5911
5912         v = be32_to_cpu(c.err_to_clearinit);
5913         master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
5914         if (state) {
5915                 if (v & FW_HELLO_CMD_ERR_F)
5916                         *state = DEV_STATE_ERR;
5917                 else if (v & FW_HELLO_CMD_INIT_F)
5918                         *state = DEV_STATE_INIT;
5919                 else
5920                         *state = DEV_STATE_UNINIT;
5921         }
5922
5923         /*
5924          * If we're not the Master PF then we need to wait around for the
5925          * Master PF Driver to finish setting up the adapter.
5926          *
5927          * Note that we also do this wait if we're a non-Master-capable PF and
5928          * there is no current Master PF; a Master PF may show up momentarily
5929          * and we wouldn't want to fail pointlessly.  (This can happen when an
5930          * OS loads lots of different drivers rapidly at the same time).  In
5931          * this case, the Master PF returned by the firmware will be
5932          * PCIE_FW_MASTER_M so the test below will work ...
5933          */
5934         if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
5935             master_mbox != mbox) {
5936                 int waiting = FW_CMD_HELLO_TIMEOUT;
5937
5938                 /*
5939                  * Wait for the firmware to either indicate an error or
5940                  * initialized state.  If we see either of these we bail out
5941                  * and report the issue to the caller.  If we exhaust the
5942                  * "hello timeout" and we haven't exhausted our retries, try
5943                  * again.  Otherwise bail with a timeout error.
5944                  */
5945                 for (;;) {
5946                         u32 pcie_fw;
5947
5948                         msleep(50);
5949                         waiting -= 50;
5950
5951                         /*
5952                          * If neither Error nor Initialialized are indicated
5953                          * by the firmware keep waiting till we exaust our
5954                          * timeout ... and then retry if we haven't exhausted
5955                          * our retries ...
5956                          */
5957                         pcie_fw = t4_read_reg(adap, PCIE_FW_A);
5958                         if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
5959                                 if (waiting <= 0) {
5960                                         if (retries-- > 0)
5961                                                 goto retry;
5962
5963                                         return -ETIMEDOUT;
5964                                 }
5965                                 continue;
5966                         }
5967
5968                         /*
5969                          * We either have an Error or Initialized condition
5970                          * report errors preferentially.
5971                          */
5972                         if (state) {
5973                                 if (pcie_fw & PCIE_FW_ERR_F)
5974                                         *state = DEV_STATE_ERR;
5975                                 else if (pcie_fw & PCIE_FW_INIT_F)
5976                                         *state = DEV_STATE_INIT;
5977                         }
5978
5979                         /*
5980                          * If we arrived before a Master PF was selected and
5981                          * there's not a valid Master PF, grab its identity
5982                          * for our caller.
5983                          */
5984                         if (master_mbox == PCIE_FW_MASTER_M &&
5985                             (pcie_fw & PCIE_FW_MASTER_VLD_F))
5986                                 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
5987                         break;
5988                 }
5989         }
5990
5991         return master_mbox;
5992 }
5993
5994 /**
5995  *      t4_fw_bye - end communication with FW
5996  *      @adap: the adapter
5997  *      @mbox: mailbox to use for the FW command
5998  *
5999  *      Issues a command to terminate communication with FW.
6000  */
6001 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
6002 {
6003         struct fw_bye_cmd c;
6004
6005         memset(&c, 0, sizeof(c));
6006         INIT_CMD(c, BYE, WRITE);
6007         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6008 }
6009
6010 /**
6011  *      t4_init_cmd - ask FW to initialize the device
6012  *      @adap: the adapter
6013  *      @mbox: mailbox to use for the FW command
6014  *
6015  *      Issues a command to FW to partially initialize the device.  This
6016  *      performs initialization that generally doesn't depend on user input.
6017  */
6018 int t4_early_init(struct adapter *adap, unsigned int mbox)
6019 {
6020         struct fw_initialize_cmd c;
6021
6022         memset(&c, 0, sizeof(c));
6023         INIT_CMD(c, INITIALIZE, WRITE);
6024         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6025 }
6026
6027 /**
6028  *      t4_fw_reset - issue a reset to FW
6029  *      @adap: the adapter
6030  *      @mbox: mailbox to use for the FW command
6031  *      @reset: specifies the type of reset to perform
6032  *
6033  *      Issues a reset command of the specified type to FW.
6034  */
6035 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
6036 {
6037         struct fw_reset_cmd c;
6038
6039         memset(&c, 0, sizeof(c));
6040         INIT_CMD(c, RESET, WRITE);
6041         c.val = cpu_to_be32(reset);
6042         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6043 }
6044
6045 /**
6046  *      t4_fw_halt - issue a reset/halt to FW and put uP into RESET
6047  *      @adap: the adapter
6048  *      @mbox: mailbox to use for the FW RESET command (if desired)
6049  *      @force: force uP into RESET even if FW RESET command fails
6050  *
6051  *      Issues a RESET command to firmware (if desired) with a HALT indication
6052  *      and then puts the microprocessor into RESET state.  The RESET command
6053  *      will only be issued if a legitimate mailbox is provided (mbox <=
6054  *      PCIE_FW_MASTER_M).
6055  *
6056  *      This is generally used in order for the host to safely manipulate the
6057  *      adapter without fear of conflicting with whatever the firmware might
6058  *      be doing.  The only way out of this state is to RESTART the firmware
6059  *      ...
6060  */
6061 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
6062 {
6063         int ret = 0;
6064
6065         /*
6066          * If a legitimate mailbox is provided, issue a RESET command
6067          * with a HALT indication.
6068          */
6069         if (mbox <= PCIE_FW_MASTER_M) {
6070                 struct fw_reset_cmd c;
6071
6072                 memset(&c, 0, sizeof(c));
6073                 INIT_CMD(c, RESET, WRITE);
6074                 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
6075                 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
6076                 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6077         }
6078
6079         /*
6080          * Normally we won't complete the operation if the firmware RESET
6081          * command fails but if our caller insists we'll go ahead and put the
6082          * uP into RESET.  This can be useful if the firmware is hung or even
6083          * missing ...  We'll have to take the risk of putting the uP into
6084          * RESET without the cooperation of firmware in that case.
6085          *
6086          * We also force the firmware's HALT flag to be on in case we bypassed
6087          * the firmware RESET command above or we're dealing with old firmware
6088          * which doesn't have the HALT capability.  This will serve as a flag
6089          * for the incoming firmware to know that it's coming out of a HALT
6090          * rather than a RESET ... if it's new enough to understand that ...
6091          */
6092         if (ret == 0 || force) {
6093                 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
6094                 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
6095                                  PCIE_FW_HALT_F);
6096         }
6097
6098         /*
6099          * And we always return the result of the firmware RESET command
6100          * even when we force the uP into RESET ...
6101          */
6102         return ret;
6103 }
6104
6105 /**
6106  *      t4_fw_restart - restart the firmware by taking the uP out of RESET
6107  *      @adap: the adapter
6108  *      @reset: if we want to do a RESET to restart things
6109  *
6110  *      Restart firmware previously halted by t4_fw_halt().  On successful
6111  *      return the previous PF Master remains as the new PF Master and there
6112  *      is no need to issue a new HELLO command, etc.
6113  *
6114  *      We do this in two ways:
6115  *
6116  *       1. If we're dealing with newer firmware we'll simply want to take
6117  *          the chip's microprocessor out of RESET.  This will cause the
6118  *          firmware to start up from its start vector.  And then we'll loop
6119  *          until the firmware indicates it's started again (PCIE_FW.HALT
6120  *          reset to 0) or we timeout.
6121  *
6122  *       2. If we're dealing with older firmware then we'll need to RESET
6123  *          the chip since older firmware won't recognize the PCIE_FW.HALT
6124  *          flag and automatically RESET itself on startup.
6125  */
6126 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
6127 {
6128         if (reset) {
6129                 /*
6130                  * Since we're directing the RESET instead of the firmware
6131                  * doing it automatically, we need to clear the PCIE_FW.HALT
6132                  * bit.
6133                  */
6134                 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
6135
6136                 /*
6137                  * If we've been given a valid mailbox, first try to get the
6138                  * firmware to do the RESET.  If that works, great and we can
6139                  * return success.  Otherwise, if we haven't been given a
6140                  * valid mailbox or the RESET command failed, fall back to
6141                  * hitting the chip with a hammer.
6142                  */
6143                 if (mbox <= PCIE_FW_MASTER_M) {
6144                         t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6145                         msleep(100);
6146                         if (t4_fw_reset(adap, mbox,
6147                                         PIORST_F | PIORSTMODE_F) == 0)
6148                                 return 0;
6149                 }
6150
6151                 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
6152                 msleep(2000);
6153         } else {
6154                 int ms;
6155
6156                 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6157                 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
6158                         if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
6159                                 return 0;
6160                         msleep(100);
6161                         ms += 100;
6162                 }
6163                 return -ETIMEDOUT;
6164         }
6165         return 0;
6166 }
6167
6168 /**
6169  *      t4_fw_upgrade - perform all of the steps necessary to upgrade FW
6170  *      @adap: the adapter
6171  *      @mbox: mailbox to use for the FW RESET command (if desired)
6172  *      @fw_data: the firmware image to write
6173  *      @size: image size
6174  *      @force: force upgrade even if firmware doesn't cooperate
6175  *
6176  *      Perform all of the steps necessary for upgrading an adapter's
6177  *      firmware image.  Normally this requires the cooperation of the
6178  *      existing firmware in order to halt all existing activities
6179  *      but if an invalid mailbox token is passed in we skip that step
6180  *      (though we'll still put the adapter microprocessor into RESET in
6181  *      that case).
6182  *
6183  *      On successful return the new firmware will have been loaded and
6184  *      the adapter will have been fully RESET losing all previous setup
6185  *      state.  On unsuccessful return the adapter may be completely hosed ...
6186  *      positive errno indicates that the adapter is ~probably~ intact, a
6187  *      negative errno indicates that things are looking bad ...
6188  */
6189 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
6190                   const u8 *fw_data, unsigned int size, int force)
6191 {
6192         const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
6193         int reset, ret;
6194
6195         if (!t4_fw_matches_chip(adap, fw_hdr))
6196                 return -EINVAL;
6197
6198         ret = t4_fw_halt(adap, mbox, force);
6199         if (ret < 0 && !force)
6200                 return ret;
6201
6202         ret = t4_load_fw(adap, fw_data, size);
6203         if (ret < 0)
6204                 return ret;
6205
6206         /*
6207          * Older versions of the firmware don't understand the new
6208          * PCIE_FW.HALT flag and so won't know to perform a RESET when they
6209          * restart.  So for newly loaded older firmware we'll have to do the
6210          * RESET for it so it starts up on a clean slate.  We can tell if
6211          * the newly loaded firmware will handle this right by checking
6212          * its header flags to see if it advertises the capability.
6213          */
6214         reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
6215         return t4_fw_restart(adap, mbox, reset);
6216 }
6217
6218 /**
6219  *      t4_fl_pkt_align - return the fl packet alignment
6220  *      @adap: the adapter
6221  *
6222  *      T4 has a single field to specify the packing and padding boundary.
6223  *      T5 onwards has separate fields for this and hence the alignment for
6224  *      next packet offset is maximum of these two.
6225  *
6226  */
6227 int t4_fl_pkt_align(struct adapter *adap)
6228 {
6229         u32 sge_control, sge_control2;
6230         unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
6231
6232         sge_control = t4_read_reg(adap, SGE_CONTROL_A);
6233
6234         /* T4 uses a single control field to specify both the PCIe Padding and
6235          * Packing Boundary.  T5 introduced the ability to specify these
6236          * separately.  The actual Ingress Packet Data alignment boundary
6237          * within Packed Buffer Mode is the maximum of these two
6238          * specifications.  (Note that it makes no real practical sense to
6239          * have the Pading Boudary be larger than the Packing Boundary but you
6240          * could set the chip up that way and, in fact, legacy T4 code would
6241          * end doing this because it would initialize the Padding Boundary and
6242          * leave the Packing Boundary initialized to 0 (16 bytes).)
6243          * Padding Boundary values in T6 starts from 8B,
6244          * where as it is 32B for T4 and T5.
6245          */
6246         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
6247                 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
6248         else
6249                 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
6250
6251         ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
6252
6253         fl_align = ingpadboundary;
6254         if (!is_t4(adap->params.chip)) {
6255                 /* T5 has a weird interpretation of one of the PCIe Packing
6256                  * Boundary values.  No idea why ...
6257                  */
6258                 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
6259                 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
6260                 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
6261                         ingpackboundary = 16;
6262                 else
6263                         ingpackboundary = 1 << (ingpackboundary +
6264                                                 INGPACKBOUNDARY_SHIFT_X);
6265
6266                 fl_align = max(ingpadboundary, ingpackboundary);
6267         }
6268         return fl_align;
6269 }
6270
6271 /**
6272  *      t4_fixup_host_params - fix up host-dependent parameters
6273  *      @adap: the adapter
6274  *      @page_size: the host's Base Page Size
6275  *      @cache_line_size: the host's Cache Line Size
6276  *
6277  *      Various registers in T4 contain values which are dependent on the
6278  *      host's Base Page and Cache Line Sizes.  This function will fix all of
6279  *      those registers with the appropriate values as passed in ...
6280  */
6281 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
6282                          unsigned int cache_line_size)
6283 {
6284         unsigned int page_shift = fls(page_size) - 1;
6285         unsigned int sge_hps = page_shift - 10;
6286         unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
6287         unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
6288         unsigned int fl_align_log = fls(fl_align) - 1;
6289         unsigned int ingpad;
6290
6291         t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
6292                      HOSTPAGESIZEPF0_V(sge_hps) |
6293                      HOSTPAGESIZEPF1_V(sge_hps) |
6294                      HOSTPAGESIZEPF2_V(sge_hps) |
6295                      HOSTPAGESIZEPF3_V(sge_hps) |
6296                      HOSTPAGESIZEPF4_V(sge_hps) |
6297                      HOSTPAGESIZEPF5_V(sge_hps) |
6298                      HOSTPAGESIZEPF6_V(sge_hps) |
6299                      HOSTPAGESIZEPF7_V(sge_hps));
6300
6301         if (is_t4(adap->params.chip)) {
6302                 t4_set_reg_field(adap, SGE_CONTROL_A,
6303                                  INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6304                                  EGRSTATUSPAGESIZE_F,
6305                                  INGPADBOUNDARY_V(fl_align_log -
6306                                                   INGPADBOUNDARY_SHIFT_X) |
6307                                  EGRSTATUSPAGESIZE_V(stat_len != 64));
6308         } else {
6309                 /* T5 introduced the separation of the Free List Padding and
6310                  * Packing Boundaries.  Thus, we can select a smaller Padding
6311                  * Boundary to avoid uselessly chewing up PCIe Link and Memory
6312                  * Bandwidth, and use a Packing Boundary which is large enough
6313                  * to avoid false sharing between CPUs, etc.
6314                  *
6315                  * For the PCI Link, the smaller the Padding Boundary the
6316                  * better.  For the Memory Controller, a smaller Padding
6317                  * Boundary is better until we cross under the Memory Line
6318                  * Size (the minimum unit of transfer to/from Memory).  If we
6319                  * have a Padding Boundary which is smaller than the Memory
6320                  * Line Size, that'll involve a Read-Modify-Write cycle on the
6321                  * Memory Controller which is never good.  For T5 the smallest
6322                  * Padding Boundary which we can select is 32 bytes which is
6323                  * larger than any known Memory Controller Line Size so we'll
6324                  * use that.
6325                  *
6326                  * T5 has a different interpretation of the "0" value for the
6327                  * Packing Boundary.  This corresponds to 16 bytes instead of
6328                  * the expected 32 bytes.  We never have a Packing Boundary
6329                  * less than 32 bytes so we can't use that special value but
6330                  * on the other hand, if we wanted 32 bytes, the best we can
6331                  * really do is 64 bytes.
6332                 */
6333                 if (fl_align <= 32) {
6334                         fl_align = 64;
6335                         fl_align_log = 6;
6336                 }
6337
6338                 if (is_t5(adap->params.chip))
6339                         ingpad = INGPCIEBOUNDARY_32B_X;
6340                 else
6341                         ingpad = T6_INGPADBOUNDARY_32B_X;
6342
6343                 t4_set_reg_field(adap, SGE_CONTROL_A,
6344                                  INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6345                                  EGRSTATUSPAGESIZE_F,
6346                                  INGPADBOUNDARY_V(ingpad) |
6347                                  EGRSTATUSPAGESIZE_V(stat_len != 64));
6348                 t4_set_reg_field(adap, SGE_CONTROL2_A,
6349                                  INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
6350                                  INGPACKBOUNDARY_V(fl_align_log -
6351                                                    INGPACKBOUNDARY_SHIFT_X));
6352         }
6353         /*
6354          * Adjust various SGE Free List Host Buffer Sizes.
6355          *
6356          * This is something of a crock since we're using fixed indices into
6357          * the array which are also known by the sge.c code and the T4
6358          * Firmware Configuration File.  We need to come up with a much better
6359          * approach to managing this array.  For now, the first four entries
6360          * are:
6361          *
6362          *   0: Host Page Size
6363          *   1: 64KB
6364          *   2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
6365          *   3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
6366          *
6367          * For the single-MTU buffers in unpacked mode we need to include
6368          * space for the SGE Control Packet Shift, 14 byte Ethernet header,
6369          * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
6370          * Padding boundary.  All of these are accommodated in the Factory
6371          * Default Firmware Configuration File but we need to adjust it for
6372          * this host's cache line size.
6373          */
6374         t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
6375         t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
6376                      (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
6377                      & ~(fl_align-1));
6378         t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
6379                      (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
6380                      & ~(fl_align-1));
6381
6382         t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
6383
6384         return 0;
6385 }
6386
6387 /**
6388  *      t4_fw_initialize - ask FW to initialize the device
6389  *      @adap: the adapter
6390  *      @mbox: mailbox to use for the FW command
6391  *
6392  *      Issues a command to FW to partially initialize the device.  This
6393  *      performs initialization that generally doesn't depend on user input.
6394  */
6395 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
6396 {
6397         struct fw_initialize_cmd c;
6398
6399         memset(&c, 0, sizeof(c));
6400         INIT_CMD(c, INITIALIZE, WRITE);
6401         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6402 }
6403
6404 /**
6405  *      t4_query_params_rw - query FW or device parameters
6406  *      @adap: the adapter
6407  *      @mbox: mailbox to use for the FW command
6408  *      @pf: the PF
6409  *      @vf: the VF
6410  *      @nparams: the number of parameters
6411  *      @params: the parameter names
6412  *      @val: the parameter values
6413  *      @rw: Write and read flag
6414  *
6415  *      Reads the value of FW or device parameters.  Up to 7 parameters can be
6416  *      queried at once.
6417  */
6418 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
6419                        unsigned int vf, unsigned int nparams, const u32 *params,
6420                        u32 *val, int rw)
6421 {
6422         int i, ret;
6423         struct fw_params_cmd c;
6424         __be32 *p = &c.param[0].mnem;
6425
6426         if (nparams > 7)
6427                 return -EINVAL;
6428
6429         memset(&c, 0, sizeof(c));
6430         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6431                                   FW_CMD_REQUEST_F | FW_CMD_READ_F |
6432                                   FW_PARAMS_CMD_PFN_V(pf) |
6433                                   FW_PARAMS_CMD_VFN_V(vf));
6434         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6435
6436         for (i = 0; i < nparams; i++) {
6437                 *p++ = cpu_to_be32(*params++);
6438                 if (rw)
6439                         *p = cpu_to_be32(*(val + i));
6440                 p++;
6441         }
6442
6443         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6444         if (ret == 0)
6445                 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
6446                         *val++ = be32_to_cpu(*p);
6447         return ret;
6448 }
6449
6450 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6451                     unsigned int vf, unsigned int nparams, const u32 *params,
6452                     u32 *val)
6453 {
6454         return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
6455 }
6456
6457 /**
6458  *      t4_set_params_timeout - sets FW or device parameters
6459  *      @adap: the adapter
6460  *      @mbox: mailbox to use for the FW command
6461  *      @pf: the PF
6462  *      @vf: the VF
6463  *      @nparams: the number of parameters
6464  *      @params: the parameter names
6465  *      @val: the parameter values
6466  *      @timeout: the timeout time
6467  *
6468  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
6469  *      specified at once.
6470  */
6471 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
6472                           unsigned int pf, unsigned int vf,
6473                           unsigned int nparams, const u32 *params,
6474                           const u32 *val, int timeout)
6475 {
6476         struct fw_params_cmd c;
6477         __be32 *p = &c.param[0].mnem;
6478
6479         if (nparams > 7)
6480                 return -EINVAL;
6481
6482         memset(&c, 0, sizeof(c));
6483         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6484                                   FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6485                                   FW_PARAMS_CMD_PFN_V(pf) |
6486                                   FW_PARAMS_CMD_VFN_V(vf));
6487         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6488
6489         while (nparams--) {
6490                 *p++ = cpu_to_be32(*params++);
6491                 *p++ = cpu_to_be32(*val++);
6492         }
6493
6494         return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
6495 }
6496
6497 /**
6498  *      t4_set_params - sets FW or device parameters
6499  *      @adap: the adapter
6500  *      @mbox: mailbox to use for the FW command
6501  *      @pf: the PF
6502  *      @vf: the VF
6503  *      @nparams: the number of parameters
6504  *      @params: the parameter names
6505  *      @val: the parameter values
6506  *
6507  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
6508  *      specified at once.
6509  */
6510 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6511                   unsigned int vf, unsigned int nparams, const u32 *params,
6512                   const u32 *val)
6513 {
6514         return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
6515                                      FW_CMD_MAX_TIMEOUT);
6516 }
6517
6518 /**
6519  *      t4_cfg_pfvf - configure PF/VF resource limits
6520  *      @adap: the adapter
6521  *      @mbox: mailbox to use for the FW command
6522  *      @pf: the PF being configured
6523  *      @vf: the VF being configured
6524  *      @txq: the max number of egress queues
6525  *      @txq_eth_ctrl: the max number of egress Ethernet or control queues
6526  *      @rxqi: the max number of interrupt-capable ingress queues
6527  *      @rxq: the max number of interruptless ingress queues
6528  *      @tc: the PCI traffic class
6529  *      @vi: the max number of virtual interfaces
6530  *      @cmask: the channel access rights mask for the PF/VF
6531  *      @pmask: the port access rights mask for the PF/VF
6532  *      @nexact: the maximum number of exact MPS filters
6533  *      @rcaps: read capabilities
6534  *      @wxcaps: write/execute capabilities
6535  *
6536  *      Configures resource limits and capabilities for a physical or virtual
6537  *      function.
6538  */
6539 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
6540                 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
6541                 unsigned int rxqi, unsigned int rxq, unsigned int tc,
6542                 unsigned int vi, unsigned int cmask, unsigned int pmask,
6543                 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
6544 {
6545         struct fw_pfvf_cmd c;
6546
6547         memset(&c, 0, sizeof(c));
6548         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
6549                                   FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
6550                                   FW_PFVF_CMD_VFN_V(vf));
6551         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6552         c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
6553                                      FW_PFVF_CMD_NIQ_V(rxq));
6554         c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
6555                                     FW_PFVF_CMD_PMASK_V(pmask) |
6556                                     FW_PFVF_CMD_NEQ_V(txq));
6557         c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
6558                                       FW_PFVF_CMD_NVI_V(vi) |
6559                                       FW_PFVF_CMD_NEXACTF_V(nexact));
6560         c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
6561                                         FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
6562                                         FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
6563         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6564 }
6565
6566 /**
6567  *      t4_alloc_vi - allocate a virtual interface
6568  *      @adap: the adapter
6569  *      @mbox: mailbox to use for the FW command
6570  *      @port: physical port associated with the VI
6571  *      @pf: the PF owning the VI
6572  *      @vf: the VF owning the VI
6573  *      @nmac: number of MAC addresses needed (1 to 5)
6574  *      @mac: the MAC addresses of the VI
6575  *      @rss_size: size of RSS table slice associated with this VI
6576  *
6577  *      Allocates a virtual interface for the given physical port.  If @mac is
6578  *      not %NULL it contains the MAC addresses of the VI as assigned by FW.
6579  *      @mac should be large enough to hold @nmac Ethernet addresses, they are
6580  *      stored consecutively so the space needed is @nmac * 6 bytes.
6581  *      Returns a negative error number or the non-negative VI id.
6582  */
6583 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
6584                 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
6585                 unsigned int *rss_size)
6586 {
6587         int ret;
6588         struct fw_vi_cmd c;
6589
6590         memset(&c, 0, sizeof(c));
6591         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
6592                                   FW_CMD_WRITE_F | FW_CMD_EXEC_F |
6593                                   FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
6594         c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
6595         c.portid_pkd = FW_VI_CMD_PORTID_V(port);
6596         c.nmac = nmac - 1;
6597
6598         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6599         if (ret)
6600                 return ret;
6601
6602         if (mac) {
6603                 memcpy(mac, c.mac, sizeof(c.mac));
6604                 switch (nmac) {
6605                 case 5:
6606                         memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
6607                 case 4:
6608                         memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
6609                 case 3:
6610                         memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
6611                 case 2:
6612                         memcpy(mac + 6,  c.nmac0, sizeof(c.nmac0));
6613                 }
6614         }
6615         if (rss_size)
6616                 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
6617         return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
6618 }
6619
6620 /**
6621  *      t4_free_vi - free a virtual interface
6622  *      @adap: the adapter
6623  *      @mbox: mailbox to use for the FW command
6624  *      @pf: the PF owning the VI
6625  *      @vf: the VF owning the VI
6626  *      @viid: virtual interface identifiler
6627  *
6628  *      Free a previously allocated virtual interface.
6629  */
6630 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
6631                unsigned int vf, unsigned int viid)
6632 {
6633         struct fw_vi_cmd c;
6634
6635         memset(&c, 0, sizeof(c));
6636         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
6637                                   FW_CMD_REQUEST_F |
6638                                   FW_CMD_EXEC_F |
6639                                   FW_VI_CMD_PFN_V(pf) |
6640                                   FW_VI_CMD_VFN_V(vf));
6641         c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
6642         c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
6643
6644         return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6645 }
6646
6647 /**
6648  *      t4_set_rxmode - set Rx properties of a virtual interface
6649  *      @adap: the adapter
6650  *      @mbox: mailbox to use for the FW command
6651  *      @viid: the VI id
6652  *      @mtu: the new MTU or -1
6653  *      @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
6654  *      @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
6655  *      @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
6656  *      @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
6657  *      @sleep_ok: if true we may sleep while awaiting command completion
6658  *
6659  *      Sets Rx properties of a virtual interface.
6660  */
6661 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
6662                   int mtu, int promisc, int all_multi, int bcast, int vlanex,
6663                   bool sleep_ok)
6664 {
6665         struct fw_vi_rxmode_cmd c;
6666
6667         /* convert to FW values */
6668         if (mtu < 0)
6669                 mtu = FW_RXMODE_MTU_NO_CHG;
6670         if (promisc < 0)
6671                 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
6672         if (all_multi < 0)
6673                 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
6674         if (bcast < 0)
6675                 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
6676         if (vlanex < 0)
6677                 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
6678
6679         memset(&c, 0, sizeof(c));
6680         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
6681                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6682                                    FW_VI_RXMODE_CMD_VIID_V(viid));
6683         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6684         c.mtu_to_vlanexen =
6685                 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
6686                             FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
6687                             FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
6688                             FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
6689                             FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
6690         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
6691 }
6692
6693 /**
6694  *      t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
6695  *      @adap: the adapter
6696  *      @mbox: mailbox to use for the FW command
6697  *      @viid: the VI id
6698  *      @free: if true any existing filters for this VI id are first removed
6699  *      @naddr: the number of MAC addresses to allocate filters for (up to 7)
6700  *      @addr: the MAC address(es)
6701  *      @idx: where to store the index of each allocated filter
6702  *      @hash: pointer to hash address filter bitmap
6703  *      @sleep_ok: call is allowed to sleep
6704  *
6705  *      Allocates an exact-match filter for each of the supplied addresses and
6706  *      sets it to the corresponding address.  If @idx is not %NULL it should
6707  *      have at least @naddr entries, each of which will be set to the index of
6708  *      the filter allocated for the corresponding MAC address.  If a filter
6709  *      could not be allocated for an address its index is set to 0xffff.
6710  *      If @hash is not %NULL addresses that fail to allocate an exact filter
6711  *      are hashed and update the hash filter bitmap pointed at by @hash.
6712  *
6713  *      Returns a negative error number or the number of filters allocated.
6714  */
6715 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
6716                       unsigned int viid, bool free, unsigned int naddr,
6717                       const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
6718 {
6719         int offset, ret = 0;
6720         struct fw_vi_mac_cmd c;
6721         unsigned int nfilters = 0;
6722         unsigned int max_naddr = adap->params.arch.mps_tcam_size;
6723         unsigned int rem = naddr;
6724
6725         if (naddr > max_naddr)
6726                 return -EINVAL;
6727
6728         for (offset = 0; offset < naddr ; /**/) {
6729                 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
6730                                          rem : ARRAY_SIZE(c.u.exact));
6731                 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
6732                                                      u.exact[fw_naddr]), 16);
6733                 struct fw_vi_mac_exact *p;
6734                 int i;
6735
6736                 memset(&c, 0, sizeof(c));
6737                 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6738                                            FW_CMD_REQUEST_F |
6739                                            FW_CMD_WRITE_F |
6740                                            FW_CMD_EXEC_V(free) |
6741                                            FW_VI_MAC_CMD_VIID_V(viid));
6742                 c.freemacs_to_len16 =
6743                         cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
6744                                     FW_CMD_LEN16_V(len16));
6745
6746                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6747                         p->valid_to_idx =
6748                                 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
6749                                             FW_VI_MAC_CMD_IDX_V(
6750                                                     FW_VI_MAC_ADD_MAC));
6751                         memcpy(p->macaddr, addr[offset + i],
6752                                sizeof(p->macaddr));
6753                 }
6754
6755                 /* It's okay if we run out of space in our MAC address arena.
6756                  * Some of the addresses we submit may get stored so we need
6757                  * to run through the reply to see what the results were ...
6758                  */
6759                 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
6760                 if (ret && ret != -FW_ENOMEM)
6761                         break;
6762
6763                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6764                         u16 index = FW_VI_MAC_CMD_IDX_G(
6765                                         be16_to_cpu(p->valid_to_idx));
6766
6767                         if (idx)
6768                                 idx[offset + i] = (index >= max_naddr ?
6769                                                    0xffff : index);
6770                         if (index < max_naddr)
6771                                 nfilters++;
6772                         else if (hash)
6773                                 *hash |= (1ULL <<
6774                                           hash_mac_addr(addr[offset + i]));
6775                 }
6776
6777                 free = false;
6778                 offset += fw_naddr;
6779                 rem -= fw_naddr;
6780         }
6781
6782         if (ret == 0 || ret == -FW_ENOMEM)
6783                 ret = nfilters;
6784         return ret;
6785 }
6786
6787 /**
6788  *      t4_free_mac_filt - frees exact-match filters of given MAC addresses
6789  *      @adap: the adapter
6790  *      @mbox: mailbox to use for the FW command
6791  *      @viid: the VI id
6792  *      @naddr: the number of MAC addresses to allocate filters for (up to 7)
6793  *      @addr: the MAC address(es)
6794  *      @sleep_ok: call is allowed to sleep
6795  *
6796  *      Frees the exact-match filter for each of the supplied addresses
6797  *
6798  *      Returns a negative error number or the number of filters freed.
6799  */
6800 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
6801                      unsigned int viid, unsigned int naddr,
6802                      const u8 **addr, bool sleep_ok)
6803 {
6804         int offset, ret = 0;
6805         struct fw_vi_mac_cmd c;
6806         unsigned int nfilters = 0;
6807         unsigned int max_naddr = is_t4(adap->params.chip) ?
6808                                        NUM_MPS_CLS_SRAM_L_INSTANCES :
6809                                        NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
6810         unsigned int rem = naddr;
6811
6812         if (naddr > max_naddr)
6813                 return -EINVAL;
6814
6815         for (offset = 0; offset < (int)naddr ; /**/) {
6816                 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
6817                                          ? rem
6818                                          : ARRAY_SIZE(c.u.exact));
6819                 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
6820                                                      u.exact[fw_naddr]), 16);
6821                 struct fw_vi_mac_exact *p;
6822                 int i;
6823
6824                 memset(&c, 0, sizeof(c));
6825                 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6826                                      FW_CMD_REQUEST_F |
6827                                      FW_CMD_WRITE_F |
6828                                      FW_CMD_EXEC_V(0) |
6829                                      FW_VI_MAC_CMD_VIID_V(viid));
6830                 c.freemacs_to_len16 =
6831                                 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
6832                                             FW_CMD_LEN16_V(len16));
6833
6834                 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
6835                         p->valid_to_idx = cpu_to_be16(
6836                                 FW_VI_MAC_CMD_VALID_F |
6837                                 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
6838                         memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
6839                 }
6840
6841                 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
6842                 if (ret)
6843                         break;
6844
6845                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6846                         u16 index = FW_VI_MAC_CMD_IDX_G(
6847                                                 be16_to_cpu(p->valid_to_idx));
6848
6849                         if (index < max_naddr)
6850                                 nfilters++;
6851                 }
6852
6853                 offset += fw_naddr;
6854                 rem -= fw_naddr;
6855         }
6856
6857         if (ret == 0)
6858                 ret = nfilters;
6859         return ret;
6860 }
6861
6862 /**
6863  *      t4_change_mac - modifies the exact-match filter for a MAC address
6864  *      @adap: the adapter
6865  *      @mbox: mailbox to use for the FW command
6866  *      @viid: the VI id
6867  *      @idx: index of existing filter for old value of MAC address, or -1
6868  *      @addr: the new MAC address value
6869  *      @persist: whether a new MAC allocation should be persistent
6870  *      @add_smt: if true also add the address to the HW SMT
6871  *
6872  *      Modifies an exact-match filter and sets it to the new MAC address.
6873  *      Note that in general it is not possible to modify the value of a given
6874  *      filter so the generic way to modify an address filter is to free the one
6875  *      being used by the old address value and allocate a new filter for the
6876  *      new address value.  @idx can be -1 if the address is a new addition.
6877  *
6878  *      Returns a negative error number or the index of the filter with the new
6879  *      MAC value.
6880  */
6881 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
6882                   int idx, const u8 *addr, bool persist, bool add_smt)
6883 {
6884         int ret, mode;
6885         struct fw_vi_mac_cmd c;
6886         struct fw_vi_mac_exact *p = c.u.exact;
6887         unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
6888
6889         if (idx < 0)                             /* new allocation */
6890                 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
6891         mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
6892
6893         memset(&c, 0, sizeof(c));
6894         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6895                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6896                                    FW_VI_MAC_CMD_VIID_V(viid));
6897         c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
6898         p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
6899                                       FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
6900                                       FW_VI_MAC_CMD_IDX_V(idx));
6901         memcpy(p->macaddr, addr, sizeof(p->macaddr));
6902
6903         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6904         if (ret == 0) {
6905                 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
6906                 if (ret >= max_mac_addr)
6907                         ret = -ENOMEM;
6908         }
6909         return ret;
6910 }
6911
6912 /**
6913  *      t4_set_addr_hash - program the MAC inexact-match hash filter
6914  *      @adap: the adapter
6915  *      @mbox: mailbox to use for the FW command
6916  *      @viid: the VI id
6917  *      @ucast: whether the hash filter should also match unicast addresses
6918  *      @vec: the value to be written to the hash filter
6919  *      @sleep_ok: call is allowed to sleep
6920  *
6921  *      Sets the 64-bit inexact-match hash filter for a virtual interface.
6922  */
6923 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
6924                      bool ucast, u64 vec, bool sleep_ok)
6925 {
6926         struct fw_vi_mac_cmd c;
6927
6928         memset(&c, 0, sizeof(c));
6929         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6930                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6931                                    FW_VI_ENABLE_CMD_VIID_V(viid));
6932         c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
6933                                           FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
6934                                           FW_CMD_LEN16_V(1));
6935         c.u.hash.hashvec = cpu_to_be64(vec);
6936         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
6937 }
6938
6939 /**
6940  *      t4_enable_vi_params - enable/disable a virtual interface
6941  *      @adap: the adapter
6942  *      @mbox: mailbox to use for the FW command
6943  *      @viid: the VI id
6944  *      @rx_en: 1=enable Rx, 0=disable Rx
6945  *      @tx_en: 1=enable Tx, 0=disable Tx
6946  *      @dcb_en: 1=enable delivery of Data Center Bridging messages.
6947  *
6948  *      Enables/disables a virtual interface.  Note that setting DCB Enable
6949  *      only makes sense when enabling a Virtual Interface ...
6950  */
6951 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
6952                         unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
6953 {
6954         struct fw_vi_enable_cmd c;
6955
6956         memset(&c, 0, sizeof(c));
6957         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
6958                                    FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
6959                                    FW_VI_ENABLE_CMD_VIID_V(viid));
6960         c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
6961                                      FW_VI_ENABLE_CMD_EEN_V(tx_en) |
6962                                      FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
6963                                      FW_LEN16(c));
6964         return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
6965 }
6966
6967 /**
6968  *      t4_enable_vi - enable/disable a virtual interface
6969  *      @adap: the adapter
6970  *      @mbox: mailbox to use for the FW command
6971  *      @viid: the VI id
6972  *      @rx_en: 1=enable Rx, 0=disable Rx
6973  *      @tx_en: 1=enable Tx, 0=disable Tx
6974  *
6975  *      Enables/disables a virtual interface.
6976  */
6977 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
6978                  bool rx_en, bool tx_en)
6979 {
6980         return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
6981 }
6982
6983 /**
6984  *      t4_identify_port - identify a VI's port by blinking its LED
6985  *      @adap: the adapter
6986  *      @mbox: mailbox to use for the FW command
6987  *      @viid: the VI id
6988  *      @nblinks: how many times to blink LED at 2.5 Hz
6989  *
6990  *      Identifies a VI's port by blinking its LED.
6991  */
6992 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
6993                      unsigned int nblinks)
6994 {
6995         struct fw_vi_enable_cmd c;
6996
6997         memset(&c, 0, sizeof(c));
6998         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
6999                                    FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7000                                    FW_VI_ENABLE_CMD_VIID_V(viid));
7001         c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
7002         c.blinkdur = cpu_to_be16(nblinks);
7003         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7004 }
7005
7006 /**
7007  *      t4_iq_stop - stop an ingress queue and its FLs
7008  *      @adap: the adapter
7009  *      @mbox: mailbox to use for the FW command
7010  *      @pf: the PF owning the queues
7011  *      @vf: the VF owning the queues
7012  *      @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
7013  *      @iqid: ingress queue id
7014  *      @fl0id: FL0 queue id or 0xffff if no attached FL0
7015  *      @fl1id: FL1 queue id or 0xffff if no attached FL1
7016  *
7017  *      Stops an ingress queue and its associated FLs, if any.  This causes
7018  *      any current or future data/messages destined for these queues to be
7019  *      tossed.
7020  */
7021 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
7022                unsigned int vf, unsigned int iqtype, unsigned int iqid,
7023                unsigned int fl0id, unsigned int fl1id)
7024 {
7025         struct fw_iq_cmd c;
7026
7027         memset(&c, 0, sizeof(c));
7028         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7029                                   FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7030                                   FW_IQ_CMD_VFN_V(vf));
7031         c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_IQSTOP_F | FW_LEN16(c));
7032         c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7033         c.iqid = cpu_to_be16(iqid);
7034         c.fl0id = cpu_to_be16(fl0id);
7035         c.fl1id = cpu_to_be16(fl1id);
7036         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7037 }
7038
7039 /**
7040  *      t4_iq_free - free an ingress queue and its FLs
7041  *      @adap: the adapter
7042  *      @mbox: mailbox to use for the FW command
7043  *      @pf: the PF owning the queues
7044  *      @vf: the VF owning the queues
7045  *      @iqtype: the ingress queue type
7046  *      @iqid: ingress queue id
7047  *      @fl0id: FL0 queue id or 0xffff if no attached FL0
7048  *      @fl1id: FL1 queue id or 0xffff if no attached FL1
7049  *
7050  *      Frees an ingress queue and its associated FLs, if any.
7051  */
7052 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7053                unsigned int vf, unsigned int iqtype, unsigned int iqid,
7054                unsigned int fl0id, unsigned int fl1id)
7055 {
7056         struct fw_iq_cmd c;
7057
7058         memset(&c, 0, sizeof(c));
7059         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7060                                   FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7061                                   FW_IQ_CMD_VFN_V(vf));
7062         c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
7063         c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7064         c.iqid = cpu_to_be16(iqid);
7065         c.fl0id = cpu_to_be16(fl0id);
7066         c.fl1id = cpu_to_be16(fl1id);
7067         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7068 }
7069
7070 /**
7071  *      t4_eth_eq_free - free an Ethernet egress queue
7072  *      @adap: the adapter
7073  *      @mbox: mailbox to use for the FW command
7074  *      @pf: the PF owning the queue
7075  *      @vf: the VF owning the queue
7076  *      @eqid: egress queue id
7077  *
7078  *      Frees an Ethernet egress queue.
7079  */
7080 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7081                    unsigned int vf, unsigned int eqid)
7082 {
7083         struct fw_eq_eth_cmd c;
7084
7085         memset(&c, 0, sizeof(c));
7086         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
7087                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7088                                   FW_EQ_ETH_CMD_PFN_V(pf) |
7089                                   FW_EQ_ETH_CMD_VFN_V(vf));
7090         c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
7091         c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
7092         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7093 }
7094
7095 /**
7096  *      t4_ctrl_eq_free - free a control egress queue
7097  *      @adap: the adapter
7098  *      @mbox: mailbox to use for the FW command
7099  *      @pf: the PF owning the queue
7100  *      @vf: the VF owning the queue
7101  *      @eqid: egress queue id
7102  *
7103  *      Frees a control egress queue.
7104  */
7105 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7106                     unsigned int vf, unsigned int eqid)
7107 {
7108         struct fw_eq_ctrl_cmd c;
7109
7110         memset(&c, 0, sizeof(c));
7111         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
7112                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7113                                   FW_EQ_CTRL_CMD_PFN_V(pf) |
7114                                   FW_EQ_CTRL_CMD_VFN_V(vf));
7115         c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
7116         c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
7117         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7118 }
7119
7120 /**
7121  *      t4_ofld_eq_free - free an offload egress queue
7122  *      @adap: the adapter
7123  *      @mbox: mailbox to use for the FW command
7124  *      @pf: the PF owning the queue
7125  *      @vf: the VF owning the queue
7126  *      @eqid: egress queue id
7127  *
7128  *      Frees a control egress queue.
7129  */
7130 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7131                     unsigned int vf, unsigned int eqid)
7132 {
7133         struct fw_eq_ofld_cmd c;
7134
7135         memset(&c, 0, sizeof(c));
7136         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
7137                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7138                                   FW_EQ_OFLD_CMD_PFN_V(pf) |
7139                                   FW_EQ_OFLD_CMD_VFN_V(vf));
7140         c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
7141         c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
7142         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7143 }
7144
7145 /**
7146  *      t4_link_down_rc_str - return a string for a Link Down Reason Code
7147  *      @adap: the adapter
7148  *      @link_down_rc: Link Down Reason Code
7149  *
7150  *      Returns a string representation of the Link Down Reason Code.
7151  */
7152 static const char *t4_link_down_rc_str(unsigned char link_down_rc)
7153 {
7154         static const char * const reason[] = {
7155                 "Link Down",
7156                 "Remote Fault",
7157                 "Auto-negotiation Failure",
7158                 "Reserved",
7159                 "Insufficient Airflow",
7160                 "Unable To Determine Reason",
7161                 "No RX Signal Detected",
7162                 "Reserved",
7163         };
7164
7165         if (link_down_rc >= ARRAY_SIZE(reason))
7166                 return "Bad Reason Code";
7167
7168         return reason[link_down_rc];
7169 }
7170
7171 /**
7172  *      t4_handle_get_port_info - process a FW reply message
7173  *      @pi: the port info
7174  *      @rpl: start of the FW message
7175  *
7176  *      Processes a GET_PORT_INFO FW reply message.
7177  */
7178 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
7179 {
7180         const struct fw_port_cmd *p = (const void *)rpl;
7181         struct adapter *adap = pi->adapter;
7182
7183         /* link/module state change message */
7184         int speed = 0, fc = 0;
7185         struct link_config *lc;
7186         u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
7187         int link_ok = (stat & FW_PORT_CMD_LSTATUS_F) != 0;
7188         u32 mod = FW_PORT_CMD_MODTYPE_G(stat);
7189
7190         if (stat & FW_PORT_CMD_RXPAUSE_F)
7191                 fc |= PAUSE_RX;
7192         if (stat & FW_PORT_CMD_TXPAUSE_F)
7193                 fc |= PAUSE_TX;
7194         if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
7195                 speed = 100;
7196         else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
7197                 speed = 1000;
7198         else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
7199                 speed = 10000;
7200         else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))
7201                 speed = 25000;
7202         else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
7203                 speed = 40000;
7204         else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))
7205                 speed = 100000;
7206
7207         lc = &pi->link_cfg;
7208
7209         if (mod != pi->mod_type) {
7210                 pi->mod_type = mod;
7211                 t4_os_portmod_changed(adap, pi->port_id);
7212         }
7213         if (link_ok != lc->link_ok || speed != lc->speed ||
7214             fc != lc->fc) {     /* something changed */
7215                 if (!link_ok && lc->link_ok) {
7216                         unsigned char rc = FW_PORT_CMD_LINKDNRC_G(stat);
7217
7218                         lc->link_down_rc = rc;
7219                         dev_warn(adap->pdev_dev,
7220                                  "Port %d link down, reason: %s\n",
7221                                  pi->port_id, t4_link_down_rc_str(rc));
7222                 }
7223                 lc->link_ok = link_ok;
7224                 lc->speed = speed;
7225                 lc->fc = fc;
7226                 lc->supported = be16_to_cpu(p->u.info.pcap);
7227                 lc->lp_advertising = be16_to_cpu(p->u.info.lpacap);
7228                 t4_os_link_changed(adap, pi->port_id, link_ok);
7229         }
7230 }
7231
7232 /**
7233  *      t4_handle_fw_rpl - process a FW reply message
7234  *      @adap: the adapter
7235  *      @rpl: start of the FW message
7236  *
7237  *      Processes a FW message, such as link state change messages.
7238  */
7239 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
7240 {
7241         u8 opcode = *(const u8 *)rpl;
7242
7243         /* This might be a port command ... this simplifies the following
7244          * conditionals ...  We can get away with pre-dereferencing
7245          * action_to_len16 because it's in the first 16 bytes and all messages
7246          * will be at least that long.
7247          */
7248         const struct fw_port_cmd *p = (const void *)rpl;
7249         unsigned int action =
7250                 FW_PORT_CMD_ACTION_G(be32_to_cpu(p->action_to_len16));
7251
7252         if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
7253                 int i;
7254                 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
7255                 struct port_info *pi = NULL;
7256
7257                 for_each_port(adap, i) {
7258                         pi = adap2pinfo(adap, i);
7259                         if (pi->tx_chan == chan)
7260                                 break;
7261                 }
7262
7263                 t4_handle_get_port_info(pi, rpl);
7264         } else {
7265                 dev_warn(adap->pdev_dev, "Unknown firmware reply %d\n", opcode);
7266                 return -EINVAL;
7267         }
7268         return 0;
7269 }
7270
7271 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
7272 {
7273         u16 val;
7274
7275         if (pci_is_pcie(adapter->pdev)) {
7276                 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
7277                 p->speed = val & PCI_EXP_LNKSTA_CLS;
7278                 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
7279         }
7280 }
7281
7282 /**
7283  *      init_link_config - initialize a link's SW state
7284  *      @lc: structure holding the link state
7285  *      @caps: link capabilities
7286  *
7287  *      Initializes the SW state maintained for each link, including the link's
7288  *      capabilities and default speed/flow-control/autonegotiation settings.
7289  */
7290 static void init_link_config(struct link_config *lc, unsigned int caps)
7291 {
7292         lc->supported = caps;
7293         lc->lp_advertising = 0;
7294         lc->requested_speed = 0;
7295         lc->speed = 0;
7296         lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
7297         if (lc->supported & FW_PORT_CAP_ANEG) {
7298                 lc->advertising = lc->supported & ADVERT_MASK;
7299                 lc->autoneg = AUTONEG_ENABLE;
7300                 lc->requested_fc |= PAUSE_AUTONEG;
7301         } else {
7302                 lc->advertising = 0;
7303                 lc->autoneg = AUTONEG_DISABLE;
7304         }
7305 }
7306
7307 #define CIM_PF_NOACCESS 0xeeeeeeee
7308
7309 int t4_wait_dev_ready(void __iomem *regs)
7310 {
7311         u32 whoami;
7312
7313         whoami = readl(regs + PL_WHOAMI_A);
7314         if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
7315                 return 0;
7316
7317         msleep(500);
7318         whoami = readl(regs + PL_WHOAMI_A);
7319         return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
7320 }
7321
7322 struct flash_desc {
7323         u32 vendor_and_model_id;
7324         u32 size_mb;
7325 };
7326
7327 static int get_flash_params(struct adapter *adap)
7328 {
7329         /* Table for non-Numonix supported flash parts.  Numonix parts are left
7330          * to the preexisting code.  All flash parts have 64KB sectors.
7331          */
7332         static struct flash_desc supported_flash[] = {
7333                 { 0x150201, 4 << 20 },       /* Spansion 4MB S25FL032P */
7334         };
7335
7336         int ret;
7337         u32 info;
7338
7339         ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
7340         if (!ret)
7341                 ret = sf1_read(adap, 3, 0, 1, &info);
7342         t4_write_reg(adap, SF_OP_A, 0);                    /* unlock SF */
7343         if (ret)
7344                 return ret;
7345
7346         for (ret = 0; ret < ARRAY_SIZE(supported_flash); ++ret)
7347                 if (supported_flash[ret].vendor_and_model_id == info) {
7348                         adap->params.sf_size = supported_flash[ret].size_mb;
7349                         adap->params.sf_nsec =
7350                                 adap->params.sf_size / SF_SEC_SIZE;
7351                         return 0;
7352                 }
7353
7354         if ((info & 0xff) != 0x20)             /* not a Numonix flash */
7355                 return -EINVAL;
7356         info >>= 16;                           /* log2 of size */
7357         if (info >= 0x14 && info < 0x18)
7358                 adap->params.sf_nsec = 1 << (info - 16);
7359         else if (info == 0x18)
7360                 adap->params.sf_nsec = 64;
7361         else
7362                 return -EINVAL;
7363         adap->params.sf_size = 1 << info;
7364         adap->params.sf_fw_start =
7365                 t4_read_reg(adap, CIM_BOOT_CFG_A) & BOOTADDR_M;
7366
7367         if (adap->params.sf_size < FLASH_MIN_SIZE)
7368                 dev_warn(adap->pdev_dev, "WARNING!!! FLASH size %#x < %#x!!!\n",
7369                          adap->params.sf_size, FLASH_MIN_SIZE);
7370         return 0;
7371 }
7372
7373 static void set_pcie_completion_timeout(struct adapter *adapter, u8 range)
7374 {
7375         u16 val;
7376         u32 pcie_cap;
7377
7378         pcie_cap = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
7379         if (pcie_cap) {
7380                 pci_read_config_word(adapter->pdev,
7381                                      pcie_cap + PCI_EXP_DEVCTL2, &val);
7382                 val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
7383                 val |= range;
7384                 pci_write_config_word(adapter->pdev,
7385                                       pcie_cap + PCI_EXP_DEVCTL2, val);
7386         }
7387 }
7388
7389 /**
7390  *      t4_prep_adapter - prepare SW and HW for operation
7391  *      @adapter: the adapter
7392  *      @reset: if true perform a HW reset
7393  *
7394  *      Initialize adapter SW state for the various HW modules, set initial
7395  *      values for some adapter tunables, take PHYs out of reset, and
7396  *      initialize the MDIO interface.
7397  */
7398 int t4_prep_adapter(struct adapter *adapter)
7399 {
7400         int ret, ver;
7401         uint16_t device_id;
7402         u32 pl_rev;
7403
7404         get_pci_mode(adapter, &adapter->params.pci);
7405         pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
7406
7407         ret = get_flash_params(adapter);
7408         if (ret < 0) {
7409                 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
7410                 return ret;
7411         }
7412
7413         /* Retrieve adapter's device ID
7414          */
7415         pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
7416         ver = device_id >> 12;
7417         adapter->params.chip = 0;
7418         switch (ver) {
7419         case CHELSIO_T4:
7420                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
7421                 adapter->params.arch.sge_fl_db = DBPRIO_F;
7422                 adapter->params.arch.mps_tcam_size =
7423                                  NUM_MPS_CLS_SRAM_L_INSTANCES;
7424                 adapter->params.arch.mps_rplc_size = 128;
7425                 adapter->params.arch.nchan = NCHAN;
7426                 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
7427                 adapter->params.arch.vfcount = 128;
7428                 /* Congestion map is for 4 channels so that
7429                  * MPS can have 4 priority per port.
7430                  */
7431                 adapter->params.arch.cng_ch_bits_log = 2;
7432                 break;
7433         case CHELSIO_T5:
7434                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
7435                 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
7436                 adapter->params.arch.mps_tcam_size =
7437                                  NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7438                 adapter->params.arch.mps_rplc_size = 128;
7439                 adapter->params.arch.nchan = NCHAN;
7440                 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
7441                 adapter->params.arch.vfcount = 128;
7442                 adapter->params.arch.cng_ch_bits_log = 2;
7443                 break;
7444         case CHELSIO_T6:
7445                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
7446                 adapter->params.arch.sge_fl_db = 0;
7447                 adapter->params.arch.mps_tcam_size =
7448                                  NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7449                 adapter->params.arch.mps_rplc_size = 256;
7450                 adapter->params.arch.nchan = 2;
7451                 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
7452                 adapter->params.arch.vfcount = 256;
7453                 /* Congestion map will be for 2 channels so that
7454                  * MPS can have 8 priority per port.
7455                  */
7456                 adapter->params.arch.cng_ch_bits_log = 3;
7457                 break;
7458         default:
7459                 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
7460                         device_id);
7461                 return -EINVAL;
7462         }
7463
7464         adapter->params.cim_la_size = CIMLA_SIZE;
7465         init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
7466
7467         /*
7468          * Default port for debugging in case we can't reach FW.
7469          */
7470         adapter->params.nports = 1;
7471         adapter->params.portvec = 1;
7472         adapter->params.vpd.cclk = 50000;
7473
7474         /* Set pci completion timeout value to 4 seconds. */
7475         set_pcie_completion_timeout(adapter, 0xd);
7476         return 0;
7477 }
7478
7479 /**
7480  *      t4_bar2_sge_qregs - return BAR2 SGE Queue register information
7481  *      @adapter: the adapter
7482  *      @qid: the Queue ID
7483  *      @qtype: the Ingress or Egress type for @qid
7484  *      @user: true if this request is for a user mode queue
7485  *      @pbar2_qoffset: BAR2 Queue Offset
7486  *      @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
7487  *
7488  *      Returns the BAR2 SGE Queue Registers information associated with the
7489  *      indicated Absolute Queue ID.  These are passed back in return value
7490  *      pointers.  @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
7491  *      and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
7492  *
7493  *      This may return an error which indicates that BAR2 SGE Queue
7494  *      registers aren't available.  If an error is not returned, then the
7495  *      following values are returned:
7496  *
7497  *        *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
7498  *        *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
7499  *
7500  *      If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
7501  *      require the "Inferred Queue ID" ability may be used.  E.g. the
7502  *      Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
7503  *      then these "Inferred Queue ID" register may not be used.
7504  */
7505 int t4_bar2_sge_qregs(struct adapter *adapter,
7506                       unsigned int qid,
7507                       enum t4_bar2_qtype qtype,
7508                       int user,
7509                       u64 *pbar2_qoffset,
7510                       unsigned int *pbar2_qid)
7511 {
7512         unsigned int page_shift, page_size, qpp_shift, qpp_mask;
7513         u64 bar2_page_offset, bar2_qoffset;
7514         unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
7515
7516         /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
7517         if (!user && is_t4(adapter->params.chip))
7518                 return -EINVAL;
7519
7520         /* Get our SGE Page Size parameters.
7521          */
7522         page_shift = adapter->params.sge.hps + 10;
7523         page_size = 1 << page_shift;
7524
7525         /* Get the right Queues per Page parameters for our Queue.
7526          */
7527         qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
7528                      ? adapter->params.sge.eq_qpp
7529                      : adapter->params.sge.iq_qpp);
7530         qpp_mask = (1 << qpp_shift) - 1;
7531
7532         /*  Calculate the basics of the BAR2 SGE Queue register area:
7533          *  o The BAR2 page the Queue registers will be in.
7534          *  o The BAR2 Queue ID.
7535          *  o The BAR2 Queue ID Offset into the BAR2 page.
7536          */
7537         bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
7538         bar2_qid = qid & qpp_mask;
7539         bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
7540
7541         /* If the BAR2 Queue ID Offset is less than the Page Size, then the
7542          * hardware will infer the Absolute Queue ID simply from the writes to
7543          * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
7544          * BAR2 Queue ID of 0 for those writes).  Otherwise, we'll simply
7545          * write to the first BAR2 SGE Queue Area within the BAR2 Page with
7546          * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
7547          * from the BAR2 Page and BAR2 Queue ID.
7548          *
7549          * One important censequence of this is that some BAR2 SGE registers
7550          * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
7551          * there.  But other registers synthesize the SGE Queue ID purely
7552          * from the writes to the registers -- the Write Combined Doorbell
7553          * Buffer is a good example.  These BAR2 SGE Registers are only
7554          * available for those BAR2 SGE Register areas where the SGE Absolute
7555          * Queue ID can be inferred from simple writes.
7556          */
7557         bar2_qoffset = bar2_page_offset;
7558         bar2_qinferred = (bar2_qid_offset < page_size);
7559         if (bar2_qinferred) {
7560                 bar2_qoffset += bar2_qid_offset;
7561                 bar2_qid = 0;
7562         }
7563
7564         *pbar2_qoffset = bar2_qoffset;
7565         *pbar2_qid = bar2_qid;
7566         return 0;
7567 }
7568
7569 /**
7570  *      t4_init_devlog_params - initialize adapter->params.devlog
7571  *      @adap: the adapter
7572  *
7573  *      Initialize various fields of the adapter's Firmware Device Log
7574  *      Parameters structure.
7575  */
7576 int t4_init_devlog_params(struct adapter *adap)
7577 {
7578         struct devlog_params *dparams = &adap->params.devlog;
7579         u32 pf_dparams;
7580         unsigned int devlog_meminfo;
7581         struct fw_devlog_cmd devlog_cmd;
7582         int ret;
7583
7584         /* If we're dealing with newer firmware, the Device Log Paramerters
7585          * are stored in a designated register which allows us to access the
7586          * Device Log even if we can't talk to the firmware.
7587          */
7588         pf_dparams =
7589                 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
7590         if (pf_dparams) {
7591                 unsigned int nentries, nentries128;
7592
7593                 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
7594                 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
7595
7596                 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
7597                 nentries = (nentries128 + 1) * 128;
7598                 dparams->size = nentries * sizeof(struct fw_devlog_e);
7599
7600                 return 0;
7601         }
7602
7603         /* Otherwise, ask the firmware for it's Device Log Parameters.
7604          */
7605         memset(&devlog_cmd, 0, sizeof(devlog_cmd));
7606         devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
7607                                              FW_CMD_REQUEST_F | FW_CMD_READ_F);
7608         devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
7609         ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
7610                          &devlog_cmd);
7611         if (ret)
7612                 return ret;
7613
7614         devlog_meminfo =
7615                 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
7616         dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
7617         dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
7618         dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
7619
7620         return 0;
7621 }
7622
7623 /**
7624  *      t4_init_sge_params - initialize adap->params.sge
7625  *      @adapter: the adapter
7626  *
7627  *      Initialize various fields of the adapter's SGE Parameters structure.
7628  */
7629 int t4_init_sge_params(struct adapter *adapter)
7630 {
7631         struct sge_params *sge_params = &adapter->params.sge;
7632         u32 hps, qpp;
7633         unsigned int s_hps, s_qpp;
7634
7635         /* Extract the SGE Page Size for our PF.
7636          */
7637         hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
7638         s_hps = (HOSTPAGESIZEPF0_S +
7639                  (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
7640         sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
7641
7642         /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
7643          */
7644         s_qpp = (QUEUESPERPAGEPF0_S +
7645                 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
7646         qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
7647         sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
7648         qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
7649         sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
7650
7651         return 0;
7652 }
7653
7654 /**
7655  *      t4_init_tp_params - initialize adap->params.tp
7656  *      @adap: the adapter
7657  *
7658  *      Initialize various fields of the adapter's TP Parameters structure.
7659  */
7660 int t4_init_tp_params(struct adapter *adap)
7661 {
7662         int chan;
7663         u32 v;
7664
7665         v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
7666         adap->params.tp.tre = TIMERRESOLUTION_G(v);
7667         adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
7668
7669         /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
7670         for (chan = 0; chan < NCHAN; chan++)
7671                 adap->params.tp.tx_modq[chan] = chan;
7672
7673         /* Cache the adapter's Compressed Filter Mode and global Incress
7674          * Configuration.
7675          */
7676         if (t4_use_ldst(adap)) {
7677                 t4_fw_tp_pio_rw(adap, &adap->params.tp.vlan_pri_map, 1,
7678                                 TP_VLAN_PRI_MAP_A, 1);
7679                 t4_fw_tp_pio_rw(adap, &adap->params.tp.ingress_config, 1,
7680                                 TP_INGRESS_CONFIG_A, 1);
7681         } else {
7682                 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
7683                                  &adap->params.tp.vlan_pri_map, 1,
7684                                  TP_VLAN_PRI_MAP_A);
7685                 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
7686                                  &adap->params.tp.ingress_config, 1,
7687                                  TP_INGRESS_CONFIG_A);
7688         }
7689
7690         /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
7691          * shift positions of several elements of the Compressed Filter Tuple
7692          * for this adapter which we need frequently ...
7693          */
7694         adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
7695         adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
7696         adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
7697         adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
7698                                                                PROTOCOL_F);
7699
7700         /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
7701          * represents the presence of an Outer VLAN instead of a VNIC ID.
7702          */
7703         if ((adap->params.tp.ingress_config & VNIC_F) == 0)
7704                 adap->params.tp.vnic_shift = -1;
7705
7706         return 0;
7707 }
7708
7709 /**
7710  *      t4_filter_field_shift - calculate filter field shift
7711  *      @adap: the adapter
7712  *      @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
7713  *
7714  *      Return the shift position of a filter field within the Compressed
7715  *      Filter Tuple.  The filter field is specified via its selection bit
7716  *      within TP_VLAN_PRI_MAL (filter mode).  E.g. F_VLAN.
7717  */
7718 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
7719 {
7720         unsigned int filter_mode = adap->params.tp.vlan_pri_map;
7721         unsigned int sel;
7722         int field_shift;
7723
7724         if ((filter_mode & filter_sel) == 0)
7725                 return -1;
7726
7727         for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
7728                 switch (filter_mode & sel) {
7729                 case FCOE_F:
7730                         field_shift += FT_FCOE_W;
7731                         break;
7732                 case PORT_F:
7733                         field_shift += FT_PORT_W;
7734                         break;
7735                 case VNIC_ID_F:
7736                         field_shift += FT_VNIC_ID_W;
7737                         break;
7738                 case VLAN_F:
7739                         field_shift += FT_VLAN_W;
7740                         break;
7741                 case TOS_F:
7742                         field_shift += FT_TOS_W;
7743                         break;
7744                 case PROTOCOL_F:
7745                         field_shift += FT_PROTOCOL_W;
7746                         break;
7747                 case ETHERTYPE_F:
7748                         field_shift += FT_ETHERTYPE_W;
7749                         break;
7750                 case MACMATCH_F:
7751                         field_shift += FT_MACMATCH_W;
7752                         break;
7753                 case MPSHITTYPE_F:
7754                         field_shift += FT_MPSHITTYPE_W;
7755                         break;
7756                 case FRAGMENTATION_F:
7757                         field_shift += FT_FRAGMENTATION_W;
7758                         break;
7759                 }
7760         }
7761         return field_shift;
7762 }
7763
7764 int t4_init_rss_mode(struct adapter *adap, int mbox)
7765 {
7766         int i, ret;
7767         struct fw_rss_vi_config_cmd rvc;
7768
7769         memset(&rvc, 0, sizeof(rvc));
7770
7771         for_each_port(adap, i) {
7772                 struct port_info *p = adap2pinfo(adap, i);
7773
7774                 rvc.op_to_viid =
7775                         cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
7776                                     FW_CMD_REQUEST_F | FW_CMD_READ_F |
7777                                     FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
7778                 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
7779                 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
7780                 if (ret)
7781                         return ret;
7782                 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
7783         }
7784         return 0;
7785 }
7786
7787 /**
7788  *      t4_init_portinfo - allocate a virtual interface amd initialize port_info
7789  *      @pi: the port_info
7790  *      @mbox: mailbox to use for the FW command
7791  *      @port: physical port associated with the VI
7792  *      @pf: the PF owning the VI
7793  *      @vf: the VF owning the VI
7794  *      @mac: the MAC address of the VI
7795  *
7796  *      Allocates a virtual interface for the given physical port.  If @mac is
7797  *      not %NULL it contains the MAC address of the VI as assigned by FW.
7798  *      @mac should be large enough to hold an Ethernet address.
7799  *      Returns < 0 on error.
7800  */
7801 int t4_init_portinfo(struct port_info *pi, int mbox,
7802                      int port, int pf, int vf, u8 mac[])
7803 {
7804         int ret;
7805         struct fw_port_cmd c;
7806         unsigned int rss_size;
7807
7808         memset(&c, 0, sizeof(c));
7809         c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
7810                                      FW_CMD_REQUEST_F | FW_CMD_READ_F |
7811                                      FW_PORT_CMD_PORTID_V(port));
7812         c.action_to_len16 = cpu_to_be32(
7813                 FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO) |
7814                 FW_LEN16(c));
7815         ret = t4_wr_mbox(pi->adapter, mbox, &c, sizeof(c), &c);
7816         if (ret)
7817                 return ret;
7818
7819         ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac, &rss_size);
7820         if (ret < 0)
7821                 return ret;
7822
7823         pi->viid = ret;
7824         pi->tx_chan = port;
7825         pi->lport = port;
7826         pi->rss_size = rss_size;
7827
7828         ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
7829         pi->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP_F) ?
7830                 FW_PORT_CMD_MDIOADDR_G(ret) : -1;
7831         pi->port_type = FW_PORT_CMD_PTYPE_G(ret);
7832         pi->mod_type = FW_PORT_MOD_TYPE_NA;
7833
7834         init_link_config(&pi->link_cfg, be16_to_cpu(c.u.info.pcap));
7835         return 0;
7836 }
7837
7838 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
7839 {
7840         u8 addr[6];
7841         int ret, i, j = 0;
7842
7843         for_each_port(adap, i) {
7844                 struct port_info *pi = adap2pinfo(adap, i);
7845
7846                 while ((adap->params.portvec & (1 << j)) == 0)
7847                         j++;
7848
7849                 ret = t4_init_portinfo(pi, mbox, j, pf, vf, addr);
7850                 if (ret)
7851                         return ret;
7852
7853                 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
7854                 adap->port[i]->dev_port = j;
7855                 j++;
7856         }
7857         return 0;
7858 }
7859
7860 /**
7861  *      t4_read_cimq_cfg - read CIM queue configuration
7862  *      @adap: the adapter
7863  *      @base: holds the queue base addresses in bytes
7864  *      @size: holds the queue sizes in bytes
7865  *      @thres: holds the queue full thresholds in bytes
7866  *
7867  *      Returns the current configuration of the CIM queues, starting with
7868  *      the IBQs, then the OBQs.
7869  */
7870 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
7871 {
7872         unsigned int i, v;
7873         int cim_num_obq = is_t4(adap->params.chip) ?
7874                                 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
7875
7876         for (i = 0; i < CIM_NUM_IBQ; i++) {
7877                 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
7878                              QUENUMSELECT_V(i));
7879                 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7880                 /* value is in 256-byte units */
7881                 *base++ = CIMQBASE_G(v) * 256;
7882                 *size++ = CIMQSIZE_G(v) * 256;
7883                 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
7884         }
7885         for (i = 0; i < cim_num_obq; i++) {
7886                 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
7887                              QUENUMSELECT_V(i));
7888                 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7889                 /* value is in 256-byte units */
7890                 *base++ = CIMQBASE_G(v) * 256;
7891                 *size++ = CIMQSIZE_G(v) * 256;
7892         }
7893 }
7894
7895 /**
7896  *      t4_read_cim_ibq - read the contents of a CIM inbound queue
7897  *      @adap: the adapter
7898  *      @qid: the queue index
7899  *      @data: where to store the queue contents
7900  *      @n: capacity of @data in 32-bit words
7901  *
7902  *      Reads the contents of the selected CIM queue starting at address 0 up
7903  *      to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
7904  *      error and the number of 32-bit words actually read on success.
7905  */
7906 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
7907 {
7908         int i, err, attempts;
7909         unsigned int addr;
7910         const unsigned int nwords = CIM_IBQ_SIZE * 4;
7911
7912         if (qid > 5 || (n & 3))
7913                 return -EINVAL;
7914
7915         addr = qid * nwords;
7916         if (n > nwords)
7917                 n = nwords;
7918
7919         /* It might take 3-10ms before the IBQ debug read access is allowed.
7920          * Wait for 1 Sec with a delay of 1 usec.
7921          */
7922         attempts = 1000000;
7923
7924         for (i = 0; i < n; i++, addr++) {
7925                 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
7926                              IBQDBGEN_F);
7927                 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
7928                                       attempts, 1);
7929                 if (err)
7930                         return err;
7931                 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
7932         }
7933         t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
7934         return i;
7935 }
7936
7937 /**
7938  *      t4_read_cim_obq - read the contents of a CIM outbound queue
7939  *      @adap: the adapter
7940  *      @qid: the queue index
7941  *      @data: where to store the queue contents
7942  *      @n: capacity of @data in 32-bit words
7943  *
7944  *      Reads the contents of the selected CIM queue starting at address 0 up
7945  *      to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
7946  *      error and the number of 32-bit words actually read on success.
7947  */
7948 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
7949 {
7950         int i, err;
7951         unsigned int addr, v, nwords;
7952         int cim_num_obq = is_t4(adap->params.chip) ?
7953                                 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
7954
7955         if ((qid > (cim_num_obq - 1)) || (n & 3))
7956                 return -EINVAL;
7957
7958         t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
7959                      QUENUMSELECT_V(qid));
7960         v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7961
7962         addr = CIMQBASE_G(v) * 64;    /* muliple of 256 -> muliple of 4 */
7963         nwords = CIMQSIZE_G(v) * 64;  /* same */
7964         if (n > nwords)
7965                 n = nwords;
7966
7967         for (i = 0; i < n; i++, addr++) {
7968                 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
7969                              OBQDBGEN_F);
7970                 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
7971                                       2, 1);
7972                 if (err)
7973                         return err;
7974                 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
7975         }
7976         t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
7977         return i;
7978 }
7979
7980 /**
7981  *      t4_cim_read - read a block from CIM internal address space
7982  *      @adap: the adapter
7983  *      @addr: the start address within the CIM address space
7984  *      @n: number of words to read
7985  *      @valp: where to store the result
7986  *
7987  *      Reads a block of 4-byte words from the CIM intenal address space.
7988  */
7989 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
7990                 unsigned int *valp)
7991 {
7992         int ret = 0;
7993
7994         if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
7995                 return -EBUSY;
7996
7997         for ( ; !ret && n--; addr += 4) {
7998                 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
7999                 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
8000                                       0, 5, 2);
8001                 if (!ret)
8002                         *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
8003         }
8004         return ret;
8005 }
8006
8007 /**
8008  *      t4_cim_write - write a block into CIM internal address space
8009  *      @adap: the adapter
8010  *      @addr: the start address within the CIM address space
8011  *      @n: number of words to write
8012  *      @valp: set of values to write
8013  *
8014  *      Writes a block of 4-byte words into the CIM intenal address space.
8015  */
8016 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
8017                  const unsigned int *valp)
8018 {
8019         int ret = 0;
8020
8021         if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
8022                 return -EBUSY;
8023
8024         for ( ; !ret && n--; addr += 4) {
8025                 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
8026                 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
8027                 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
8028                                       0, 5, 2);
8029         }
8030         return ret;
8031 }
8032
8033 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
8034                          unsigned int val)
8035 {
8036         return t4_cim_write(adap, addr, 1, &val);
8037 }
8038
8039 /**
8040  *      t4_cim_read_la - read CIM LA capture buffer
8041  *      @adap: the adapter
8042  *      @la_buf: where to store the LA data
8043  *      @wrptr: the HW write pointer within the capture buffer
8044  *
8045  *      Reads the contents of the CIM LA buffer with the most recent entry at
8046  *      the end of the returned data and with the entry at @wrptr first.
8047  *      We try to leave the LA in the running state we find it in.
8048  */
8049 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
8050 {
8051         int i, ret;
8052         unsigned int cfg, val, idx;
8053
8054         ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
8055         if (ret)
8056                 return ret;
8057
8058         if (cfg & UPDBGLAEN_F) {        /* LA is running, freeze it */
8059                 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
8060                 if (ret)
8061                         return ret;
8062         }
8063
8064         ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
8065         if (ret)
8066                 goto restart;
8067
8068         idx = UPDBGLAWRPTR_G(val);
8069         if (wrptr)
8070                 *wrptr = idx;
8071
8072         for (i = 0; i < adap->params.cim_la_size; i++) {
8073                 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
8074                                     UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
8075                 if (ret)
8076                         break;
8077                 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
8078                 if (ret)
8079                         break;
8080                 if (val & UPDBGLARDEN_F) {
8081                         ret = -ETIMEDOUT;
8082                         break;
8083                 }
8084                 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
8085                 if (ret)
8086                         break;
8087                 idx = (idx + 1) & UPDBGLARDPTR_M;
8088         }
8089 restart:
8090         if (cfg & UPDBGLAEN_F) {
8091                 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
8092                                       cfg & ~UPDBGLARDEN_F);
8093                 if (!ret)
8094                         ret = r;
8095         }
8096         return ret;
8097 }
8098
8099 /**
8100  *      t4_tp_read_la - read TP LA capture buffer
8101  *      @adap: the adapter
8102  *      @la_buf: where to store the LA data
8103  *      @wrptr: the HW write pointer within the capture buffer
8104  *
8105  *      Reads the contents of the TP LA buffer with the most recent entry at
8106  *      the end of the returned data and with the entry at @wrptr first.
8107  *      We leave the LA in the running state we find it in.
8108  */
8109 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
8110 {
8111         bool last_incomplete;
8112         unsigned int i, cfg, val, idx;
8113
8114         cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
8115         if (cfg & DBGLAENABLE_F)                        /* freeze LA */
8116                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
8117                              adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
8118
8119         val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
8120         idx = DBGLAWPTR_G(val);
8121         last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
8122         if (last_incomplete)
8123                 idx = (idx + 1) & DBGLARPTR_M;
8124         if (wrptr)
8125                 *wrptr = idx;
8126
8127         val &= 0xffff;
8128         val &= ~DBGLARPTR_V(DBGLARPTR_M);
8129         val |= adap->params.tp.la_mask;
8130
8131         for (i = 0; i < TPLA_SIZE; i++) {
8132                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
8133                 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
8134                 idx = (idx + 1) & DBGLARPTR_M;
8135         }
8136
8137         /* Wipe out last entry if it isn't valid */
8138         if (last_incomplete)
8139                 la_buf[TPLA_SIZE - 1] = ~0ULL;
8140
8141         if (cfg & DBGLAENABLE_F)                    /* restore running state */
8142                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
8143                              cfg | adap->params.tp.la_mask);
8144 }
8145
8146 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
8147  * seconds).  If we find one of the SGE Ingress DMA State Machines in the same
8148  * state for more than the Warning Threshold then we'll issue a warning about
8149  * a potential hang.  We'll repeat the warning as the SGE Ingress DMA Channel
8150  * appears to be hung every Warning Repeat second till the situation clears.
8151  * If the situation clears, we'll note that as well.
8152  */
8153 #define SGE_IDMA_WARN_THRESH 1
8154 #define SGE_IDMA_WARN_REPEAT 300
8155
8156 /**
8157  *      t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
8158  *      @adapter: the adapter
8159  *      @idma: the adapter IDMA Monitor state
8160  *
8161  *      Initialize the state of an SGE Ingress DMA Monitor.
8162  */
8163 void t4_idma_monitor_init(struct adapter *adapter,
8164                           struct sge_idma_monitor_state *idma)
8165 {
8166         /* Initialize the state variables for detecting an SGE Ingress DMA
8167          * hang.  The SGE has internal counters which count up on each clock
8168          * tick whenever the SGE finds its Ingress DMA State Engines in the
8169          * same state they were on the previous clock tick.  The clock used is
8170          * the Core Clock so we have a limit on the maximum "time" they can
8171          * record; typically a very small number of seconds.  For instance,
8172          * with a 600MHz Core Clock, we can only count up to a bit more than
8173          * 7s.  So we'll synthesize a larger counter in order to not run the
8174          * risk of having the "timers" overflow and give us the flexibility to
8175          * maintain a Hung SGE State Machine of our own which operates across
8176          * a longer time frame.
8177          */
8178         idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
8179         idma->idma_stalled[0] = 0;
8180         idma->idma_stalled[1] = 0;
8181 }
8182
8183 /**
8184  *      t4_idma_monitor - monitor SGE Ingress DMA state
8185  *      @adapter: the adapter
8186  *      @idma: the adapter IDMA Monitor state
8187  *      @hz: number of ticks/second
8188  *      @ticks: number of ticks since the last IDMA Monitor call
8189  */
8190 void t4_idma_monitor(struct adapter *adapter,
8191                      struct sge_idma_monitor_state *idma,
8192                      int hz, int ticks)
8193 {
8194         int i, idma_same_state_cnt[2];
8195
8196          /* Read the SGE Debug Ingress DMA Same State Count registers.  These
8197           * are counters inside the SGE which count up on each clock when the
8198           * SGE finds its Ingress DMA State Engines in the same states they
8199           * were in the previous clock.  The counters will peg out at
8200           * 0xffffffff without wrapping around so once they pass the 1s
8201           * threshold they'll stay above that till the IDMA state changes.
8202           */
8203         t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
8204         idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
8205         idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8206
8207         for (i = 0; i < 2; i++) {
8208                 u32 debug0, debug11;
8209
8210                 /* If the Ingress DMA Same State Counter ("timer") is less
8211                  * than 1s, then we can reset our synthesized Stall Timer and
8212                  * continue.  If we have previously emitted warnings about a
8213                  * potential stalled Ingress Queue, issue a note indicating
8214                  * that the Ingress Queue has resumed forward progress.
8215                  */
8216                 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
8217                         if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
8218                                 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
8219                                          "resumed after %d seconds\n",
8220                                          i, idma->idma_qid[i],
8221                                          idma->idma_stalled[i] / hz);
8222                         idma->idma_stalled[i] = 0;
8223                         continue;
8224                 }
8225
8226                 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
8227                  * domain.  The first time we get here it'll be because we
8228                  * passed the 1s Threshold; each additional time it'll be
8229                  * because the RX Timer Callback is being fired on its regular
8230                  * schedule.
8231                  *
8232                  * If the stall is below our Potential Hung Ingress Queue
8233                  * Warning Threshold, continue.
8234                  */
8235                 if (idma->idma_stalled[i] == 0) {
8236                         idma->idma_stalled[i] = hz;
8237                         idma->idma_warn[i] = 0;
8238                 } else {
8239                         idma->idma_stalled[i] += ticks;
8240                         idma->idma_warn[i] -= ticks;
8241                 }
8242
8243                 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
8244                         continue;
8245
8246                 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
8247                  */
8248                 if (idma->idma_warn[i] > 0)
8249                         continue;
8250                 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
8251
8252                 /* Read and save the SGE IDMA State and Queue ID information.
8253                  * We do this every time in case it changes across time ...
8254                  * can't be too careful ...
8255                  */
8256                 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
8257                 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8258                 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
8259
8260                 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
8261                 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8262                 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
8263
8264                 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
8265                          "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
8266                          i, idma->idma_qid[i], idma->idma_state[i],
8267                          idma->idma_stalled[i] / hz,
8268                          debug0, debug11);
8269                 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
8270         }
8271 }
8272
8273 /**
8274  *      t4_set_vf_mac - Set MAC address for the specified VF
8275  *      @adapter: The adapter
8276  *      @vf: one of the VFs instantiated by the specified PF
8277  *      @naddr: the number of MAC addresses
8278  *      @addr: the MAC address(es) to be set to the specified VF
8279  */
8280 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
8281                       unsigned int naddr, u8 *addr)
8282 {
8283         struct fw_acl_mac_cmd cmd;
8284
8285         memset(&cmd, 0, sizeof(cmd));
8286         cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_MAC_CMD) |
8287                                     FW_CMD_REQUEST_F |
8288                                     FW_CMD_WRITE_F |
8289                                     FW_ACL_MAC_CMD_PFN_V(adapter->pf) |
8290                                     FW_ACL_MAC_CMD_VFN_V(vf));
8291
8292         /* Note: Do not enable the ACL */
8293         cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
8294         cmd.nmac = naddr;
8295
8296         switch (adapter->pf) {
8297         case 3:
8298                 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3));
8299                 break;
8300         case 2:
8301                 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2));
8302                 break;
8303         case 1:
8304                 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1));
8305                 break;
8306         case 0:
8307                 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0));
8308                 break;
8309         }
8310
8311         return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd);
8312 }
8313
8314 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
8315                     int rateunit, int ratemode, int channel, int class,
8316                     int minrate, int maxrate, int weight, int pktsize)
8317 {
8318         struct fw_sched_cmd cmd;
8319
8320         memset(&cmd, 0, sizeof(cmd));
8321         cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_SCHED_CMD) |
8322                                       FW_CMD_REQUEST_F |
8323                                       FW_CMD_WRITE_F);
8324         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
8325
8326         cmd.u.params.sc = FW_SCHED_SC_PARAMS;
8327         cmd.u.params.type = type;
8328         cmd.u.params.level = level;
8329         cmd.u.params.mode = mode;
8330         cmd.u.params.ch = channel;
8331         cmd.u.params.cl = class;
8332         cmd.u.params.unit = rateunit;
8333         cmd.u.params.rate = ratemode;
8334         cmd.u.params.min = cpu_to_be32(minrate);
8335         cmd.u.params.max = cpu_to_be32(maxrate);
8336         cmd.u.params.weight = cpu_to_be16(weight);
8337         cmd.u.params.pktsize = cpu_to_be16(pktsize);
8338
8339         return t4_wr_mbox_meat(adapter, adapter->mbox, &cmd, sizeof(cmd),
8340                                NULL, 1);
8341 }