2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/delay.h>
41 * t4_wait_op_done_val - wait until an operation is completed
42 * @adapter: the adapter performing the operation
43 * @reg: the register to check for completion
44 * @mask: a single-bit field within @reg that indicates completion
45 * @polarity: the value of the field when the operation is completed
46 * @attempts: number of check iterations
47 * @delay: delay in usecs between iterations
48 * @valp: where to store the value of the register at completion time
50 * Wait until an operation is completed by checking a bit in a register
51 * up to @attempts times. If @valp is not NULL the value of the register
52 * at the time it indicated completion is stored there. Returns 0 if the
53 * operation completes and -EAGAIN otherwise.
55 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
56 int polarity, int attempts, int delay, u32 *valp)
59 u32 val = t4_read_reg(adapter, reg);
61 if (!!(val & mask) == polarity) {
73 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
74 int polarity, int attempts, int delay)
76 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
81 * t4_set_reg_field - set a register field to a value
82 * @adapter: the adapter to program
83 * @addr: the register address
84 * @mask: specifies the portion of the register to modify
85 * @val: the new value for the register field
87 * Sets a register field specified by the supplied mask to the
90 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
93 u32 v = t4_read_reg(adapter, addr) & ~mask;
95 t4_write_reg(adapter, addr, v | val);
96 (void) t4_read_reg(adapter, addr); /* flush */
100 * t4_read_indirect - read indirectly addressed registers
102 * @addr_reg: register holding the indirect address
103 * @data_reg: register holding the value of the indirect register
104 * @vals: where the read register values are stored
105 * @nregs: how many indirect registers to read
106 * @start_idx: index of first indirect register to read
108 * Reads registers that are accessed indirectly through an address/data
111 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
112 unsigned int data_reg, u32 *vals,
113 unsigned int nregs, unsigned int start_idx)
116 t4_write_reg(adap, addr_reg, start_idx);
117 *vals++ = t4_read_reg(adap, data_reg);
123 * t4_write_indirect - write indirectly addressed registers
125 * @addr_reg: register holding the indirect addresses
126 * @data_reg: register holding the value for the indirect registers
127 * @vals: values to write
128 * @nregs: how many indirect registers to write
129 * @start_idx: address of first indirect register to write
131 * Writes a sequential block of registers that are accessed indirectly
132 * through an address/data register pair.
134 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
135 unsigned int data_reg, const u32 *vals,
136 unsigned int nregs, unsigned int start_idx)
139 t4_write_reg(adap, addr_reg, start_idx++);
140 t4_write_reg(adap, data_reg, *vals++);
145 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
146 * mechanism. This guarantees that we get the real value even if we're
147 * operating within a Virtual Machine and the Hypervisor is trapping our
148 * Configuration Space accesses.
150 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
152 u32 req = ENABLE | FUNCTION(adap->fn) | reg;
154 if (is_t4(adap->params.chip))
157 t4_write_reg(adap, PCIE_CFG_SPACE_REQ, req);
158 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA);
160 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
161 * Configuration Space read. (None of the other fields matter when
162 * ENABLE is 0 so a simple register write is easier than a
163 * read-modify-write via t4_set_reg_field().)
165 t4_write_reg(adap, PCIE_CFG_SPACE_REQ, 0);
169 * t4_report_fw_error - report firmware error
172 * The adapter firmware can indicate error conditions to the host.
173 * If the firmware has indicated an error, print out the reason for
174 * the firmware error.
176 static void t4_report_fw_error(struct adapter *adap)
178 static const char *const reason[] = {
179 "Crash", /* PCIE_FW_EVAL_CRASH */
180 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
181 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
182 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
183 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
184 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
185 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
186 "Reserved", /* reserved */
190 pcie_fw = t4_read_reg(adap, MA_PCIE_FW);
191 if (pcie_fw & FW_PCIE_FW_ERR)
192 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
193 reason[FW_PCIE_FW_EVAL_GET(pcie_fw)]);
197 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
199 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
202 for ( ; nflit; nflit--, mbox_addr += 8)
203 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
207 * Handle a FW assertion reported in a mailbox.
209 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
211 struct fw_debug_cmd asrt;
213 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
214 dev_alert(adap->pdev_dev,
215 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
216 asrt.u.assert.filename_0_7, ntohl(asrt.u.assert.line),
217 ntohl(asrt.u.assert.x), ntohl(asrt.u.assert.y));
220 static void dump_mbox(struct adapter *adap, int mbox, u32 data_reg)
222 dev_err(adap->pdev_dev,
223 "mbox %d: %llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
224 (unsigned long long)t4_read_reg64(adap, data_reg),
225 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
226 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
227 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
228 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
229 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
230 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
231 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
235 * t4_wr_mbox_meat - send a command to FW through the given mailbox
237 * @mbox: index of the mailbox to use
238 * @cmd: the command to write
239 * @size: command length in bytes
240 * @rpl: where to optionally store the reply
241 * @sleep_ok: if true we may sleep while awaiting command completion
243 * Sends the given command to FW through the selected mailbox and waits
244 * for the FW to execute the command. If @rpl is not %NULL it is used to
245 * store the FW's reply to the command. The command and its optional
246 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
247 * to respond. @sleep_ok determines whether we may sleep while awaiting
248 * the response. If sleeping is allowed we use progressive backoff
251 * The return value is 0 on success or a negative errno on failure. A
252 * failure can happen either because we are not able to execute the
253 * command or FW executes it but signals an error. In the latter case
254 * the return value is the error code indicated by FW (negated).
256 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
257 void *rpl, bool sleep_ok)
259 static const int delay[] = {
260 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
265 int i, ms, delay_idx;
266 const __be64 *p = cmd;
267 u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA);
268 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL);
270 if ((size & 15) || size > MBOX_LEN)
274 * If the device is off-line, as in EEH, commands will time out.
275 * Fail them early so we don't waste time waiting.
277 if (adap->pdev->error_state != pci_channel_io_normal)
280 v = MBOWNER_GET(t4_read_reg(adap, ctl_reg));
281 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
282 v = MBOWNER_GET(t4_read_reg(adap, ctl_reg));
284 if (v != MBOX_OWNER_DRV)
285 return v ? -EBUSY : -ETIMEDOUT;
287 for (i = 0; i < size; i += 8)
288 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
290 t4_write_reg(adap, ctl_reg, MBMSGVALID | MBOWNER(MBOX_OWNER_FW));
291 t4_read_reg(adap, ctl_reg); /* flush write */
296 for (i = 0; i < FW_CMD_MAX_TIMEOUT; i += ms) {
298 ms = delay[delay_idx]; /* last element may repeat */
299 if (delay_idx < ARRAY_SIZE(delay) - 1)
305 v = t4_read_reg(adap, ctl_reg);
306 if (MBOWNER_GET(v) == MBOX_OWNER_DRV) {
307 if (!(v & MBMSGVALID)) {
308 t4_write_reg(adap, ctl_reg, 0);
312 res = t4_read_reg64(adap, data_reg);
313 if (FW_CMD_OP_GET(res >> 32) == FW_DEBUG_CMD) {
314 fw_asrt(adap, data_reg);
315 res = FW_CMD_RETVAL(EIO);
317 get_mbox_rpl(adap, rpl, size / 8, data_reg);
319 if (FW_CMD_RETVAL_GET((int)res))
320 dump_mbox(adap, mbox, data_reg);
321 t4_write_reg(adap, ctl_reg, 0);
322 return -FW_CMD_RETVAL_GET((int)res);
326 dump_mbox(adap, mbox, data_reg);
327 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
328 *(const u8 *)cmd, mbox);
329 t4_report_fw_error(adap);
334 * t4_mc_read - read from MC through backdoor accesses
336 * @addr: address of first byte requested
337 * @idx: which MC to access
338 * @data: 64 bytes of data containing the requested address
339 * @ecc: where to store the corresponding 64-bit ECC word
341 * Read 64 bytes of data from MC starting at a 64-byte-aligned address
342 * that covers the requested address @addr. If @parity is not %NULL it
343 * is assigned the 64-bit ECC word for the read data.
345 int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
348 u32 mc_bist_cmd, mc_bist_cmd_addr, mc_bist_cmd_len;
349 u32 mc_bist_status_rdata, mc_bist_data_pattern;
351 if (is_t4(adap->params.chip)) {
352 mc_bist_cmd = MC_BIST_CMD;
353 mc_bist_cmd_addr = MC_BIST_CMD_ADDR;
354 mc_bist_cmd_len = MC_BIST_CMD_LEN;
355 mc_bist_status_rdata = MC_BIST_STATUS_RDATA;
356 mc_bist_data_pattern = MC_BIST_DATA_PATTERN;
358 mc_bist_cmd = MC_REG(MC_P_BIST_CMD, idx);
359 mc_bist_cmd_addr = MC_REG(MC_P_BIST_CMD_ADDR, idx);
360 mc_bist_cmd_len = MC_REG(MC_P_BIST_CMD_LEN, idx);
361 mc_bist_status_rdata = MC_REG(MC_P_BIST_STATUS_RDATA, idx);
362 mc_bist_data_pattern = MC_REG(MC_P_BIST_DATA_PATTERN, idx);
365 if (t4_read_reg(adap, mc_bist_cmd) & START_BIST)
367 t4_write_reg(adap, mc_bist_cmd_addr, addr & ~0x3fU);
368 t4_write_reg(adap, mc_bist_cmd_len, 64);
369 t4_write_reg(adap, mc_bist_data_pattern, 0xc);
370 t4_write_reg(adap, mc_bist_cmd, BIST_OPCODE(1) | START_BIST |
372 i = t4_wait_op_done(adap, mc_bist_cmd, START_BIST, 0, 10, 1);
376 #define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata, i)
378 for (i = 15; i >= 0; i--)
379 *data++ = htonl(t4_read_reg(adap, MC_DATA(i)));
381 *ecc = t4_read_reg64(adap, MC_DATA(16));
387 * t4_edc_read - read from EDC through backdoor accesses
389 * @idx: which EDC to access
390 * @addr: address of first byte requested
391 * @data: 64 bytes of data containing the requested address
392 * @ecc: where to store the corresponding 64-bit ECC word
394 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address
395 * that covers the requested address @addr. If @parity is not %NULL it
396 * is assigned the 64-bit ECC word for the read data.
398 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
401 u32 edc_bist_cmd, edc_bist_cmd_addr, edc_bist_cmd_len;
402 u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata;
404 if (is_t4(adap->params.chip)) {
405 edc_bist_cmd = EDC_REG(EDC_BIST_CMD, idx);
406 edc_bist_cmd_addr = EDC_REG(EDC_BIST_CMD_ADDR, idx);
407 edc_bist_cmd_len = EDC_REG(EDC_BIST_CMD_LEN, idx);
408 edc_bist_cmd_data_pattern = EDC_REG(EDC_BIST_DATA_PATTERN,
410 edc_bist_status_rdata = EDC_REG(EDC_BIST_STATUS_RDATA,
413 edc_bist_cmd = EDC_REG_T5(EDC_H_BIST_CMD, idx);
414 edc_bist_cmd_addr = EDC_REG_T5(EDC_H_BIST_CMD_ADDR, idx);
415 edc_bist_cmd_len = EDC_REG_T5(EDC_H_BIST_CMD_LEN, idx);
416 edc_bist_cmd_data_pattern =
417 EDC_REG_T5(EDC_H_BIST_DATA_PATTERN, idx);
418 edc_bist_status_rdata =
419 EDC_REG_T5(EDC_H_BIST_STATUS_RDATA, idx);
422 if (t4_read_reg(adap, edc_bist_cmd) & START_BIST)
424 t4_write_reg(adap, edc_bist_cmd_addr, addr & ~0x3fU);
425 t4_write_reg(adap, edc_bist_cmd_len, 64);
426 t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc);
427 t4_write_reg(adap, edc_bist_cmd,
428 BIST_OPCODE(1) | BIST_CMD_GAP(1) | START_BIST);
429 i = t4_wait_op_done(adap, edc_bist_cmd, START_BIST, 0, 10, 1);
433 #define EDC_DATA(i) (EDC_BIST_STATUS_REG(edc_bist_status_rdata, i))
435 for (i = 15; i >= 0; i--)
436 *data++ = htonl(t4_read_reg(adap, EDC_DATA(i)));
438 *ecc = t4_read_reg64(adap, EDC_DATA(16));
444 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
446 * @win: PCI-E Memory Window to use
447 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
448 * @addr: address within indicated memory type
449 * @len: amount of memory to transfer
450 * @buf: host memory buffer
451 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
453 * Reads/writes an [almost] arbitrary memory region in the firmware: the
454 * firmware memory address and host buffer must be aligned on 32-bit
455 * boudaries; the length may be arbitrary. The memory is transferred as
456 * a raw byte sequence from/to the firmware's memory. If this memory
457 * contains data structures which contain multi-byte integers, it's the
458 * caller's responsibility to perform appropriate byte order conversions.
460 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
461 u32 len, __be32 *buf, int dir)
463 u32 pos, offset, resid, memoffset;
464 u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
466 /* Argument sanity checks ...
471 /* It's convenient to be able to handle lengths which aren't a
472 * multiple of 32-bits because we often end up transferring files to
473 * the firmware. So we'll handle that by normalizing the length here
474 * and then handling any residual transfer at the end.
479 /* Offset into the region of memory which is being accessed
483 * MEM_MC0 = 2 -- For T5
484 * MEM_MC1 = 3 -- For T5
486 edc_size = EDRAM_SIZE_GET(t4_read_reg(adap, MA_EDRAM0_BAR));
487 if (mtype != MEM_MC1)
488 memoffset = (mtype * (edc_size * 1024 * 1024));
490 mc_size = EXT_MEM_SIZE_GET(t4_read_reg(adap,
492 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
495 /* Determine the PCIE_MEM_ACCESS_OFFSET */
496 addr = addr + memoffset;
498 /* Each PCI-E Memory Window is programmed with a window size -- or
499 * "aperture" -- which controls the granularity of its mapping onto
500 * adapter memory. We need to grab that aperture in order to know
501 * how to use the specified window. The window is also programmed
502 * with the base address of the Memory Window in BAR0's address
503 * space. For T4 this is an absolute PCI-E Bus Address. For T5
504 * the address is relative to BAR0.
506 mem_reg = t4_read_reg(adap,
507 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN,
509 mem_aperture = 1 << (GET_WINDOW(mem_reg) + 10);
510 mem_base = GET_PCIEOFST(mem_reg) << 10;
511 if (is_t4(adap->params.chip))
512 mem_base -= adap->t4_bar0;
513 win_pf = is_t4(adap->params.chip) ? 0 : V_PFNUM(adap->fn);
515 /* Calculate our initial PCI-E Memory Window Position and Offset into
518 pos = addr & ~(mem_aperture-1);
521 /* Set up initial PCI-E Memory Window to cover the start of our
522 * transfer. (Read it back to ensure that changes propagate before we
523 * attempt to use the new value.)
526 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win),
529 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win));
531 /* Transfer data to/from the adapter as long as there's an integral
532 * number of 32-bit transfers to complete.
535 if (dir == T4_MEMORY_READ)
536 *buf++ = (__force __be32) t4_read_reg(adap,
539 t4_write_reg(adap, mem_base + offset,
540 (__force u32) *buf++);
541 offset += sizeof(__be32);
542 len -= sizeof(__be32);
544 /* If we've reached the end of our current window aperture,
545 * move the PCI-E Memory Window on to the next. Note that
546 * doing this here after "len" may be 0 allows us to set up
547 * the PCI-E Memory Window for a possible final residual
550 if (offset == mem_aperture) {
554 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET,
557 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET,
562 /* If the original transfer had a length which wasn't a multiple of
563 * 32-bits, now's where we need to finish off the transfer of the
564 * residual amount. The PCI-E Memory Window has already been moved
565 * above (if necessary) to cover this final transfer.
575 if (dir == T4_MEMORY_READ) {
576 last.word = (__force __be32) t4_read_reg(adap,
578 for (bp = (unsigned char *)buf, i = resid; i < 4; i++)
579 bp[i] = last.byte[i];
582 for (i = resid; i < 4; i++)
584 t4_write_reg(adap, mem_base + offset,
585 (__force u32) last.word);
592 #define EEPROM_STAT_ADDR 0x7bfc
593 #define VPD_BASE 0x400
594 #define VPD_BASE_OLD 0
596 #define CHELSIO_VPD_UNIQUE_ID 0x82
599 * t4_seeprom_wp - enable/disable EEPROM write protection
600 * @adapter: the adapter
601 * @enable: whether to enable or disable write protection
603 * Enables or disables write protection on the serial EEPROM.
605 int t4_seeprom_wp(struct adapter *adapter, bool enable)
607 unsigned int v = enable ? 0xc : 0;
608 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
609 return ret < 0 ? ret : 0;
613 * get_vpd_params - read VPD parameters from VPD EEPROM
614 * @adapter: adapter to read
615 * @p: where to store the parameters
617 * Reads card parameters stored in VPD EEPROM.
619 int get_vpd_params(struct adapter *adapter, struct vpd_params *p)
621 u32 cclk_param, cclk_val;
625 unsigned int vpdr_len, kw_offset, id_len;
627 vpd = vmalloc(VPD_LEN);
631 ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
635 /* The VPD shall have a unique identifier specified by the PCI SIG.
636 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
637 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
638 * is expected to automatically put this entry at the
639 * beginning of the VPD.
641 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
643 ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
647 if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
648 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
653 id_len = pci_vpd_lrdt_size(vpd);
657 i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
659 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
664 vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
665 kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
666 if (vpdr_len + kw_offset > VPD_LEN) {
667 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
672 #define FIND_VPD_KW(var, name) do { \
673 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
675 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
679 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
682 FIND_VPD_KW(i, "RV");
683 for (csum = 0; i >= 0; i--)
687 dev_err(adapter->pdev_dev,
688 "corrupted VPD EEPROM, actual csum %u\n", csum);
693 FIND_VPD_KW(ec, "EC");
694 FIND_VPD_KW(sn, "SN");
695 FIND_VPD_KW(pn, "PN");
698 memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
700 memcpy(p->ec, vpd + ec, EC_LEN);
702 i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
703 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
705 i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
706 memcpy(p->pn, vpd + pn, min(i, PN_LEN));
710 * Ask firmware for the Core Clock since it knows how to translate the
711 * Reference Clock ('V2') VPD field into a Core Clock value ...
713 cclk_param = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
714 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK));
715 ret = t4_query_params(adapter, adapter->mbox, 0, 0,
716 1, &cclk_param, &cclk_val);
727 /* serial flash and firmware constants */
729 SF_ATTEMPTS = 10, /* max retries for SF operations */
731 /* flash command opcodes */
732 SF_PROG_PAGE = 2, /* program page */
733 SF_WR_DISABLE = 4, /* disable writes */
734 SF_RD_STATUS = 5, /* read status register */
735 SF_WR_ENABLE = 6, /* enable writes */
736 SF_RD_DATA_FAST = 0xb, /* read flash */
737 SF_RD_ID = 0x9f, /* read ID */
738 SF_ERASE_SECTOR = 0xd8, /* erase sector */
740 FW_MAX_SIZE = 16 * SF_SEC_SIZE,
744 * sf1_read - read data from the serial flash
745 * @adapter: the adapter
746 * @byte_cnt: number of bytes to read
747 * @cont: whether another operation will be chained
748 * @lock: whether to lock SF for PL access only
749 * @valp: where to store the read data
751 * Reads up to 4 bytes of data from the serial flash. The location of
752 * the read needs to be specified prior to calling this by issuing the
753 * appropriate commands to the serial flash.
755 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
760 if (!byte_cnt || byte_cnt > 4)
762 if (t4_read_reg(adapter, SF_OP) & SF_BUSY)
764 cont = cont ? SF_CONT : 0;
765 lock = lock ? SF_LOCK : 0;
766 t4_write_reg(adapter, SF_OP, lock | cont | BYTECNT(byte_cnt - 1));
767 ret = t4_wait_op_done(adapter, SF_OP, SF_BUSY, 0, SF_ATTEMPTS, 5);
769 *valp = t4_read_reg(adapter, SF_DATA);
774 * sf1_write - write data to the serial flash
775 * @adapter: the adapter
776 * @byte_cnt: number of bytes to write
777 * @cont: whether another operation will be chained
778 * @lock: whether to lock SF for PL access only
779 * @val: value to write
781 * Writes up to 4 bytes of data to the serial flash. The location of
782 * the write needs to be specified prior to calling this by issuing the
783 * appropriate commands to the serial flash.
785 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
788 if (!byte_cnt || byte_cnt > 4)
790 if (t4_read_reg(adapter, SF_OP) & SF_BUSY)
792 cont = cont ? SF_CONT : 0;
793 lock = lock ? SF_LOCK : 0;
794 t4_write_reg(adapter, SF_DATA, val);
795 t4_write_reg(adapter, SF_OP, lock |
796 cont | BYTECNT(byte_cnt - 1) | OP_WR);
797 return t4_wait_op_done(adapter, SF_OP, SF_BUSY, 0, SF_ATTEMPTS, 5);
801 * flash_wait_op - wait for a flash operation to complete
802 * @adapter: the adapter
803 * @attempts: max number of polls of the status register
804 * @delay: delay between polls in ms
806 * Wait for a flash operation to complete by polling the status register.
808 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
814 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
815 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
827 * t4_read_flash - read words from serial flash
828 * @adapter: the adapter
829 * @addr: the start address for the read
830 * @nwords: how many 32-bit words to read
831 * @data: where to store the read data
832 * @byte_oriented: whether to store data as bytes or as words
834 * Read the specified number of 32-bit words from the serial flash.
835 * If @byte_oriented is set the read data is stored as a byte array
836 * (i.e., big-endian), otherwise as 32-bit words in the platform's
839 static int t4_read_flash(struct adapter *adapter, unsigned int addr,
840 unsigned int nwords, u32 *data, int byte_oriented)
844 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
847 addr = swab32(addr) | SF_RD_DATA_FAST;
849 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
850 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
853 for ( ; nwords; nwords--, data++) {
854 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
856 t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
860 *data = (__force __u32) (htonl(*data));
866 * t4_write_flash - write up to a page of data to the serial flash
867 * @adapter: the adapter
868 * @addr: the start address to write
869 * @n: length of data to write in bytes
870 * @data: the data to write
872 * Writes up to a page of data (256 bytes) to the serial flash starting
873 * at the given address. All the data must be written to the same page.
875 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
876 unsigned int n, const u8 *data)
880 unsigned int i, c, left, val, offset = addr & 0xff;
882 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
885 val = swab32(addr) | SF_PROG_PAGE;
887 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
888 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
891 for (left = n; left; left -= c) {
893 for (val = 0, i = 0; i < c; ++i)
894 val = (val << 8) + *data++;
896 ret = sf1_write(adapter, c, c != left, 1, val);
900 ret = flash_wait_op(adapter, 8, 1);
904 t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
906 /* Read the page to verify the write succeeded */
907 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
911 if (memcmp(data - n, (u8 *)buf + offset, n)) {
912 dev_err(adapter->pdev_dev,
913 "failed to correctly write the flash page at %#x\n",
920 t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
925 * t4_get_fw_version - read the firmware version
926 * @adapter: the adapter
927 * @vers: where to place the version
929 * Reads the FW version from flash.
931 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
933 return t4_read_flash(adapter, FLASH_FW_START +
934 offsetof(struct fw_hdr, fw_ver), 1,
939 * t4_get_tp_version - read the TP microcode version
940 * @adapter: the adapter
941 * @vers: where to place the version
943 * Reads the TP microcode version from flash.
945 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
947 return t4_read_flash(adapter, FLASH_FW_START +
948 offsetof(struct fw_hdr, tp_microcode_ver),
952 /* Is the given firmware API compatible with the one the driver was compiled
955 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
958 /* short circuit if it's the exact same firmware version */
959 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
962 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
963 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
964 SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
971 /* The firmware in the filesystem is usable, but should it be installed?
972 * This routine explains itself in detail if it indicates the filesystem
973 * firmware should be installed.
975 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
980 if (!card_fw_usable) {
981 reason = "incompatible or unusable";
986 reason = "older than the version supported with this driver";
993 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
994 "installing firmware %u.%u.%u.%u on card.\n",
995 FW_HDR_FW_VER_MAJOR_GET(c), FW_HDR_FW_VER_MINOR_GET(c),
996 FW_HDR_FW_VER_MICRO_GET(c), FW_HDR_FW_VER_BUILD_GET(c), reason,
997 FW_HDR_FW_VER_MAJOR_GET(k), FW_HDR_FW_VER_MINOR_GET(k),
998 FW_HDR_FW_VER_MICRO_GET(k), FW_HDR_FW_VER_BUILD_GET(k));
1003 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
1004 const u8 *fw_data, unsigned int fw_size,
1005 struct fw_hdr *card_fw, enum dev_state state,
1008 int ret, card_fw_usable, fs_fw_usable;
1009 const struct fw_hdr *fs_fw;
1010 const struct fw_hdr *drv_fw;
1012 drv_fw = &fw_info->fw_hdr;
1014 /* Read the header of the firmware on the card */
1015 ret = -t4_read_flash(adap, FLASH_FW_START,
1016 sizeof(*card_fw) / sizeof(uint32_t),
1017 (uint32_t *)card_fw, 1);
1019 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
1021 dev_err(adap->pdev_dev,
1022 "Unable to read card's firmware header: %d\n", ret);
1026 if (fw_data != NULL) {
1027 fs_fw = (const void *)fw_data;
1028 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
1034 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
1035 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
1036 /* Common case: the firmware on the card is an exact match and
1037 * the filesystem one is an exact match too, or the filesystem
1038 * one is absent/incompatible.
1040 } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
1041 should_install_fs_fw(adap, card_fw_usable,
1042 be32_to_cpu(fs_fw->fw_ver),
1043 be32_to_cpu(card_fw->fw_ver))) {
1044 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data,
1047 dev_err(adap->pdev_dev,
1048 "failed to install firmware: %d\n", ret);
1052 /* Installed successfully, update the cached header too. */
1053 memcpy(card_fw, fs_fw, sizeof(*card_fw));
1055 *reset = 0; /* already reset as part of load_fw */
1058 if (!card_fw_usable) {
1061 d = be32_to_cpu(drv_fw->fw_ver);
1062 c = be32_to_cpu(card_fw->fw_ver);
1063 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
1065 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
1067 "driver compiled with %d.%d.%d.%d, "
1068 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
1070 FW_HDR_FW_VER_MAJOR_GET(d), FW_HDR_FW_VER_MINOR_GET(d),
1071 FW_HDR_FW_VER_MICRO_GET(d), FW_HDR_FW_VER_BUILD_GET(d),
1072 FW_HDR_FW_VER_MAJOR_GET(c), FW_HDR_FW_VER_MINOR_GET(c),
1073 FW_HDR_FW_VER_MICRO_GET(c), FW_HDR_FW_VER_BUILD_GET(c),
1074 FW_HDR_FW_VER_MAJOR_GET(k), FW_HDR_FW_VER_MINOR_GET(k),
1075 FW_HDR_FW_VER_MICRO_GET(k), FW_HDR_FW_VER_BUILD_GET(k));
1080 /* We're using whatever's on the card and it's known to be good. */
1081 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
1082 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
1089 * t4_flash_erase_sectors - erase a range of flash sectors
1090 * @adapter: the adapter
1091 * @start: the first sector to erase
1092 * @end: the last sector to erase
1094 * Erases the sectors in the given inclusive range.
1096 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
1100 if (end >= adapter->params.sf_nsec)
1103 while (start <= end) {
1104 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
1105 (ret = sf1_write(adapter, 4, 0, 1,
1106 SF_ERASE_SECTOR | (start << 8))) != 0 ||
1107 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
1108 dev_err(adapter->pdev_dev,
1109 "erase of flash sector %d failed, error %d\n",
1115 t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
1120 * t4_flash_cfg_addr - return the address of the flash configuration file
1121 * @adapter: the adapter
1123 * Return the address within the flash where the Firmware Configuration
1126 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
1128 if (adapter->params.sf_size == 0x100000)
1129 return FLASH_FPGA_CFG_START;
1131 return FLASH_CFG_START;
1134 /* Return TRUE if the specified firmware matches the adapter. I.e. T4
1135 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
1136 * and emit an error message for mismatched firmware to save our caller the
1139 static bool t4_fw_matches_chip(const struct adapter *adap,
1140 const struct fw_hdr *hdr)
1142 /* The expression below will return FALSE for any unsupported adapter
1143 * which will keep us "honest" in the future ...
1145 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
1146 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5))
1149 dev_err(adap->pdev_dev,
1150 "FW image (%d) is not suitable for this adapter (%d)\n",
1151 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
1156 * t4_load_fw - download firmware
1157 * @adap: the adapter
1158 * @fw_data: the firmware image to write
1161 * Write the supplied firmware image to the card's serial flash.
1163 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
1168 u8 first_page[SF_PAGE_SIZE];
1169 const __be32 *p = (const __be32 *)fw_data;
1170 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
1171 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
1172 unsigned int fw_img_start = adap->params.sf_fw_start;
1173 unsigned int fw_start_sec = fw_img_start / sf_sec_size;
1176 dev_err(adap->pdev_dev, "FW image has no data\n");
1180 dev_err(adap->pdev_dev,
1181 "FW image size not multiple of 512 bytes\n");
1184 if (ntohs(hdr->len512) * 512 != size) {
1185 dev_err(adap->pdev_dev,
1186 "FW image size differs from size in FW header\n");
1189 if (size > FW_MAX_SIZE) {
1190 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
1194 if (!t4_fw_matches_chip(adap, hdr))
1197 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
1198 csum += ntohl(p[i]);
1200 if (csum != 0xffffffff) {
1201 dev_err(adap->pdev_dev,
1202 "corrupted firmware image, checksum %#x\n", csum);
1206 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
1207 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
1212 * We write the correct version at the end so the driver can see a bad
1213 * version if the FW write fails. Start by writing a copy of the
1214 * first page with a bad version.
1216 memcpy(first_page, fw_data, SF_PAGE_SIZE);
1217 ((struct fw_hdr *)first_page)->fw_ver = htonl(0xffffffff);
1218 ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page);
1222 addr = fw_img_start;
1223 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
1224 addr += SF_PAGE_SIZE;
1225 fw_data += SF_PAGE_SIZE;
1226 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
1231 ret = t4_write_flash(adap,
1232 fw_img_start + offsetof(struct fw_hdr, fw_ver),
1233 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
1236 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
1241 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
1242 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \
1246 * t4_link_start - apply link configuration to MAC/PHY
1247 * @phy: the PHY to setup
1248 * @mac: the MAC to setup
1249 * @lc: the requested link configuration
1251 * Set up a port's MAC and PHY according to a desired link configuration.
1252 * - If the PHY can auto-negotiate first decide what to advertise, then
1253 * enable/disable auto-negotiation as desired, and reset.
1254 * - If the PHY does not auto-negotiate just reset it.
1255 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
1256 * otherwise do it later based on the outcome of auto-negotiation.
1258 int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
1259 struct link_config *lc)
1261 struct fw_port_cmd c;
1262 unsigned int fc = 0, mdi = FW_PORT_MDI(FW_PORT_MDI_AUTO);
1265 if (lc->requested_fc & PAUSE_RX)
1266 fc |= FW_PORT_CAP_FC_RX;
1267 if (lc->requested_fc & PAUSE_TX)
1268 fc |= FW_PORT_CAP_FC_TX;
1270 memset(&c, 0, sizeof(c));
1271 c.op_to_portid = htonl(FW_CMD_OP(FW_PORT_CMD) | FW_CMD_REQUEST |
1272 FW_CMD_EXEC | FW_PORT_CMD_PORTID(port));
1273 c.action_to_len16 = htonl(FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
1276 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
1277 c.u.l1cfg.rcap = htonl((lc->supported & ADVERT_MASK) | fc);
1278 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1279 } else if (lc->autoneg == AUTONEG_DISABLE) {
1280 c.u.l1cfg.rcap = htonl(lc->requested_speed | fc | mdi);
1281 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1283 c.u.l1cfg.rcap = htonl(lc->advertising | fc | mdi);
1285 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
1289 * t4_restart_aneg - restart autonegotiation
1290 * @adap: the adapter
1291 * @mbox: mbox to use for the FW command
1292 * @port: the port id
1294 * Restarts autonegotiation for the selected port.
1296 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
1298 struct fw_port_cmd c;
1300 memset(&c, 0, sizeof(c));
1301 c.op_to_portid = htonl(FW_CMD_OP(FW_PORT_CMD) | FW_CMD_REQUEST |
1302 FW_CMD_EXEC | FW_PORT_CMD_PORTID(port));
1303 c.action_to_len16 = htonl(FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
1305 c.u.l1cfg.rcap = htonl(FW_PORT_CAP_ANEG);
1306 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
1309 typedef void (*int_handler_t)(struct adapter *adap);
1312 unsigned int mask; /* bits to check in interrupt status */
1313 const char *msg; /* message to print or NULL */
1314 short stat_idx; /* stat counter to increment or -1 */
1315 unsigned short fatal; /* whether the condition reported is fatal */
1316 int_handler_t int_handler; /* platform-specific int handler */
1320 * t4_handle_intr_status - table driven interrupt handler
1321 * @adapter: the adapter that generated the interrupt
1322 * @reg: the interrupt status register to process
1323 * @acts: table of interrupt actions
1325 * A table driven interrupt handler that applies a set of masks to an
1326 * interrupt status word and performs the corresponding actions if the
1327 * interrupts described by the mask have occurred. The actions include
1328 * optionally emitting a warning or alert message. The table is terminated
1329 * by an entry specifying mask 0. Returns the number of fatal interrupt
1332 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
1333 const struct intr_info *acts)
1336 unsigned int mask = 0;
1337 unsigned int status = t4_read_reg(adapter, reg);
1339 for ( ; acts->mask; ++acts) {
1340 if (!(status & acts->mask))
1344 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
1345 status & acts->mask);
1346 } else if (acts->msg && printk_ratelimit())
1347 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
1348 status & acts->mask);
1349 if (acts->int_handler)
1350 acts->int_handler(adapter);
1354 if (status) /* clear processed interrupts */
1355 t4_write_reg(adapter, reg, status);
1360 * Interrupt handler for the PCIE module.
1362 static void pcie_intr_handler(struct adapter *adapter)
1364 static const struct intr_info sysbus_intr_info[] = {
1365 { RNPP, "RXNP array parity error", -1, 1 },
1366 { RPCP, "RXPC array parity error", -1, 1 },
1367 { RCIP, "RXCIF array parity error", -1, 1 },
1368 { RCCP, "Rx completions control array parity error", -1, 1 },
1369 { RFTP, "RXFT array parity error", -1, 1 },
1372 static const struct intr_info pcie_port_intr_info[] = {
1373 { TPCP, "TXPC array parity error", -1, 1 },
1374 { TNPP, "TXNP array parity error", -1, 1 },
1375 { TFTP, "TXFT array parity error", -1, 1 },
1376 { TCAP, "TXCA array parity error", -1, 1 },
1377 { TCIP, "TXCIF array parity error", -1, 1 },
1378 { RCAP, "RXCA array parity error", -1, 1 },
1379 { OTDD, "outbound request TLP discarded", -1, 1 },
1380 { RDPE, "Rx data parity error", -1, 1 },
1381 { TDUE, "Tx uncorrectable data error", -1, 1 },
1384 static const struct intr_info pcie_intr_info[] = {
1385 { MSIADDRLPERR, "MSI AddrL parity error", -1, 1 },
1386 { MSIADDRHPERR, "MSI AddrH parity error", -1, 1 },
1387 { MSIDATAPERR, "MSI data parity error", -1, 1 },
1388 { MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
1389 { MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
1390 { MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
1391 { MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
1392 { PIOCPLPERR, "PCI PIO completion FIFO parity error", -1, 1 },
1393 { PIOREQPERR, "PCI PIO request FIFO parity error", -1, 1 },
1394 { TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
1395 { CCNTPERR, "PCI CMD channel count parity error", -1, 1 },
1396 { CREQPERR, "PCI CMD channel request parity error", -1, 1 },
1397 { CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
1398 { DCNTPERR, "PCI DMA channel count parity error", -1, 1 },
1399 { DREQPERR, "PCI DMA channel request parity error", -1, 1 },
1400 { DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
1401 { HCNTPERR, "PCI HMA channel count parity error", -1, 1 },
1402 { HREQPERR, "PCI HMA channel request parity error", -1, 1 },
1403 { HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
1404 { CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
1405 { FIDPERR, "PCI FID parity error", -1, 1 },
1406 { INTXCLRPERR, "PCI INTx clear parity error", -1, 1 },
1407 { MATAGPERR, "PCI MA tag parity error", -1, 1 },
1408 { PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
1409 { RXCPLPERR, "PCI Rx completion parity error", -1, 1 },
1410 { RXWRPERR, "PCI Rx write parity error", -1, 1 },
1411 { RPLPERR, "PCI replay buffer parity error", -1, 1 },
1412 { PCIESINT, "PCI core secondary fault", -1, 1 },
1413 { PCIEPINT, "PCI core primary fault", -1, 1 },
1414 { UNXSPLCPLERR, "PCI unexpected split completion error", -1, 0 },
1418 static struct intr_info t5_pcie_intr_info[] = {
1419 { MSTGRPPERR, "Master Response Read Queue parity error",
1421 { MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 },
1422 { MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 },
1423 { MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
1424 { MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
1425 { MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
1426 { MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
1427 { PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error",
1429 { PIOREQGRPPERR, "PCI PIO request Group FIFO parity error",
1431 { TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
1432 { MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 },
1433 { CREQPERR, "PCI CMD channel request parity error", -1, 1 },
1434 { CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
1435 { DREQWRPERR, "PCI DMA channel write request parity error",
1437 { DREQPERR, "PCI DMA channel request parity error", -1, 1 },
1438 { DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
1439 { HREQWRPERR, "PCI HMA channel count parity error", -1, 1 },
1440 { HREQPERR, "PCI HMA channel request parity error", -1, 1 },
1441 { HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
1442 { CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
1443 { FIDPERR, "PCI FID parity error", -1, 1 },
1444 { VFIDPERR, "PCI INTx clear parity error", -1, 1 },
1445 { MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 },
1446 { PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
1447 { IPRXHDRGRPPERR, "PCI IP Rx header group parity error",
1449 { IPRXDATAGRPPERR, "PCI IP Rx data group parity error", -1, 1 },
1450 { RPLPERR, "PCI IP replay buffer parity error", -1, 1 },
1451 { IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 },
1452 { TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 },
1453 { READRSPERR, "Outbound read error", -1, 0 },
1459 if (is_t4(adapter->params.chip))
1460 fat = t4_handle_intr_status(adapter,
1461 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
1463 t4_handle_intr_status(adapter,
1464 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
1465 pcie_port_intr_info) +
1466 t4_handle_intr_status(adapter, PCIE_INT_CAUSE,
1469 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE,
1473 t4_fatal_err(adapter);
1477 * TP interrupt handler.
1479 static void tp_intr_handler(struct adapter *adapter)
1481 static const struct intr_info tp_intr_info[] = {
1482 { 0x3fffffff, "TP parity error", -1, 1 },
1483 { FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 },
1487 if (t4_handle_intr_status(adapter, TP_INT_CAUSE, tp_intr_info))
1488 t4_fatal_err(adapter);
1492 * SGE interrupt handler.
1494 static void sge_intr_handler(struct adapter *adapter)
1498 static const struct intr_info sge_intr_info[] = {
1499 { ERR_CPL_EXCEED_IQE_SIZE,
1500 "SGE received CPL exceeding IQE size", -1, 1 },
1501 { ERR_INVALID_CIDX_INC,
1502 "SGE GTS CIDX increment too large", -1, 0 },
1503 { ERR_CPL_OPCODE_0, "SGE received 0-length CPL", -1, 0 },
1504 { DBFIFO_LP_INT, NULL, -1, 0, t4_db_full },
1505 { DBFIFO_HP_INT, NULL, -1, 0, t4_db_full },
1506 { ERR_DROPPED_DB, NULL, -1, 0, t4_db_dropped },
1507 { ERR_DATA_CPL_ON_HIGH_QID1 | ERR_DATA_CPL_ON_HIGH_QID0,
1508 "SGE IQID > 1023 received CPL for FL", -1, 0 },
1509 { ERR_BAD_DB_PIDX3, "SGE DBP 3 pidx increment too large", -1,
1511 { ERR_BAD_DB_PIDX2, "SGE DBP 2 pidx increment too large", -1,
1513 { ERR_BAD_DB_PIDX1, "SGE DBP 1 pidx increment too large", -1,
1515 { ERR_BAD_DB_PIDX0, "SGE DBP 0 pidx increment too large", -1,
1517 { ERR_ING_CTXT_PRIO,
1518 "SGE too many priority ingress contexts", -1, 0 },
1519 { ERR_EGR_CTXT_PRIO,
1520 "SGE too many priority egress contexts", -1, 0 },
1521 { INGRESS_SIZE_ERR, "SGE illegal ingress QID", -1, 0 },
1522 { EGRESS_SIZE_ERR, "SGE illegal egress QID", -1, 0 },
1526 v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1) |
1527 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2) << 32);
1529 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
1530 (unsigned long long)v);
1531 t4_write_reg(adapter, SGE_INT_CAUSE1, v);
1532 t4_write_reg(adapter, SGE_INT_CAUSE2, v >> 32);
1535 if (t4_handle_intr_status(adapter, SGE_INT_CAUSE3, sge_intr_info) ||
1537 t4_fatal_err(adapter);
1541 * CIM interrupt handler.
1543 static void cim_intr_handler(struct adapter *adapter)
1545 static const struct intr_info cim_intr_info[] = {
1546 { PREFDROPINT, "CIM control register prefetch drop", -1, 1 },
1547 { OBQPARERR, "CIM OBQ parity error", -1, 1 },
1548 { IBQPARERR, "CIM IBQ parity error", -1, 1 },
1549 { MBUPPARERR, "CIM mailbox uP parity error", -1, 1 },
1550 { MBHOSTPARERR, "CIM mailbox host parity error", -1, 1 },
1551 { TIEQINPARERRINT, "CIM TIEQ outgoing parity error", -1, 1 },
1552 { TIEQOUTPARERRINT, "CIM TIEQ incoming parity error", -1, 1 },
1555 static const struct intr_info cim_upintr_info[] = {
1556 { RSVDSPACEINT, "CIM reserved space access", -1, 1 },
1557 { ILLTRANSINT, "CIM illegal transaction", -1, 1 },
1558 { ILLWRINT, "CIM illegal write", -1, 1 },
1559 { ILLRDINT, "CIM illegal read", -1, 1 },
1560 { ILLRDBEINT, "CIM illegal read BE", -1, 1 },
1561 { ILLWRBEINT, "CIM illegal write BE", -1, 1 },
1562 { SGLRDBOOTINT, "CIM single read from boot space", -1, 1 },
1563 { SGLWRBOOTINT, "CIM single write to boot space", -1, 1 },
1564 { BLKWRBOOTINT, "CIM block write to boot space", -1, 1 },
1565 { SGLRDFLASHINT, "CIM single read from flash space", -1, 1 },
1566 { SGLWRFLASHINT, "CIM single write to flash space", -1, 1 },
1567 { BLKWRFLASHINT, "CIM block write to flash space", -1, 1 },
1568 { SGLRDEEPROMINT, "CIM single EEPROM read", -1, 1 },
1569 { SGLWREEPROMINT, "CIM single EEPROM write", -1, 1 },
1570 { BLKRDEEPROMINT, "CIM block EEPROM read", -1, 1 },
1571 { BLKWREEPROMINT, "CIM block EEPROM write", -1, 1 },
1572 { SGLRDCTLINT , "CIM single read from CTL space", -1, 1 },
1573 { SGLWRCTLINT , "CIM single write to CTL space", -1, 1 },
1574 { BLKRDCTLINT , "CIM block read from CTL space", -1, 1 },
1575 { BLKWRCTLINT , "CIM block write to CTL space", -1, 1 },
1576 { SGLRDPLINT , "CIM single read from PL space", -1, 1 },
1577 { SGLWRPLINT , "CIM single write to PL space", -1, 1 },
1578 { BLKRDPLINT , "CIM block read from PL space", -1, 1 },
1579 { BLKWRPLINT , "CIM block write to PL space", -1, 1 },
1580 { REQOVRLOOKUPINT , "CIM request FIFO overwrite", -1, 1 },
1581 { RSPOVRLOOKUPINT , "CIM response FIFO overwrite", -1, 1 },
1582 { TIMEOUTINT , "CIM PIF timeout", -1, 1 },
1583 { TIMEOUTMAINT , "CIM PIF MA timeout", -1, 1 },
1589 if (t4_read_reg(adapter, MA_PCIE_FW) & FW_PCIE_FW_ERR)
1590 t4_report_fw_error(adapter);
1592 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE,
1594 t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE,
1597 t4_fatal_err(adapter);
1601 * ULP RX interrupt handler.
1603 static void ulprx_intr_handler(struct adapter *adapter)
1605 static const struct intr_info ulprx_intr_info[] = {
1606 { 0x1800000, "ULPRX context error", -1, 1 },
1607 { 0x7fffff, "ULPRX parity error", -1, 1 },
1611 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE, ulprx_intr_info))
1612 t4_fatal_err(adapter);
1616 * ULP TX interrupt handler.
1618 static void ulptx_intr_handler(struct adapter *adapter)
1620 static const struct intr_info ulptx_intr_info[] = {
1621 { PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds", -1,
1623 { PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds", -1,
1625 { PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds", -1,
1627 { PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds", -1,
1629 { 0xfffffff, "ULPTX parity error", -1, 1 },
1633 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE, ulptx_intr_info))
1634 t4_fatal_err(adapter);
1638 * PM TX interrupt handler.
1640 static void pmtx_intr_handler(struct adapter *adapter)
1642 static const struct intr_info pmtx_intr_info[] = {
1643 { PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large", -1, 1 },
1644 { PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large", -1, 1 },
1645 { PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large", -1, 1 },
1646 { ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1 },
1647 { PMTX_FRAMING_ERROR, "PMTX framing error", -1, 1 },
1648 { OESPI_PAR_ERROR, "PMTX oespi parity error", -1, 1 },
1649 { DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error", -1, 1 },
1650 { ICSPI_PAR_ERROR, "PMTX icspi parity error", -1, 1 },
1651 { C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error", -1, 1},
1655 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE, pmtx_intr_info))
1656 t4_fatal_err(adapter);
1660 * PM RX interrupt handler.
1662 static void pmrx_intr_handler(struct adapter *adapter)
1664 static const struct intr_info pmrx_intr_info[] = {
1665 { ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 },
1666 { PMRX_FRAMING_ERROR, "PMRX framing error", -1, 1 },
1667 { OCSPI_PAR_ERROR, "PMRX ocspi parity error", -1, 1 },
1668 { DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error", -1, 1 },
1669 { IESPI_PAR_ERROR, "PMRX iespi parity error", -1, 1 },
1670 { E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error", -1, 1},
1674 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE, pmrx_intr_info))
1675 t4_fatal_err(adapter);
1679 * CPL switch interrupt handler.
1681 static void cplsw_intr_handler(struct adapter *adapter)
1683 static const struct intr_info cplsw_intr_info[] = {
1684 { CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error", -1, 1 },
1685 { CIM_OVFL_ERROR, "CPLSW CIM overflow", -1, 1 },
1686 { TP_FRAMING_ERROR, "CPLSW TP framing error", -1, 1 },
1687 { SGE_FRAMING_ERROR, "CPLSW SGE framing error", -1, 1 },
1688 { CIM_FRAMING_ERROR, "CPLSW CIM framing error", -1, 1 },
1689 { ZERO_SWITCH_ERROR, "CPLSW no-switch error", -1, 1 },
1693 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE, cplsw_intr_info))
1694 t4_fatal_err(adapter);
1698 * LE interrupt handler.
1700 static void le_intr_handler(struct adapter *adap)
1702 static const struct intr_info le_intr_info[] = {
1703 { LIPMISS, "LE LIP miss", -1, 0 },
1704 { LIP0, "LE 0 LIP error", -1, 0 },
1705 { PARITYERR, "LE parity error", -1, 1 },
1706 { UNKNOWNCMD, "LE unknown command", -1, 1 },
1707 { REQQPARERR, "LE request queue parity error", -1, 1 },
1711 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE, le_intr_info))
1716 * MPS interrupt handler.
1718 static void mps_intr_handler(struct adapter *adapter)
1720 static const struct intr_info mps_rx_intr_info[] = {
1721 { 0xffffff, "MPS Rx parity error", -1, 1 },
1724 static const struct intr_info mps_tx_intr_info[] = {
1725 { TPFIFO, "MPS Tx TP FIFO parity error", -1, 1 },
1726 { NCSIFIFO, "MPS Tx NC-SI FIFO parity error", -1, 1 },
1727 { TXDATAFIFO, "MPS Tx data FIFO parity error", -1, 1 },
1728 { TXDESCFIFO, "MPS Tx desc FIFO parity error", -1, 1 },
1729 { BUBBLE, "MPS Tx underflow", -1, 1 },
1730 { SECNTERR, "MPS Tx SOP/EOP error", -1, 1 },
1731 { FRMERR, "MPS Tx framing error", -1, 1 },
1734 static const struct intr_info mps_trc_intr_info[] = {
1735 { FILTMEM, "MPS TRC filter parity error", -1, 1 },
1736 { PKTFIFO, "MPS TRC packet FIFO parity error", -1, 1 },
1737 { MISCPERR, "MPS TRC misc parity error", -1, 1 },
1740 static const struct intr_info mps_stat_sram_intr_info[] = {
1741 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
1744 static const struct intr_info mps_stat_tx_intr_info[] = {
1745 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
1748 static const struct intr_info mps_stat_rx_intr_info[] = {
1749 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
1752 static const struct intr_info mps_cls_intr_info[] = {
1753 { MATCHSRAM, "MPS match SRAM parity error", -1, 1 },
1754 { MATCHTCAM, "MPS match TCAM parity error", -1, 1 },
1755 { HASHSRAM, "MPS hash SRAM parity error", -1, 1 },
1761 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE,
1763 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE,
1765 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE,
1766 mps_trc_intr_info) +
1767 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM,
1768 mps_stat_sram_intr_info) +
1769 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO,
1770 mps_stat_tx_intr_info) +
1771 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO,
1772 mps_stat_rx_intr_info) +
1773 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE,
1776 t4_write_reg(adapter, MPS_INT_CAUSE, CLSINT | TRCINT |
1777 RXINT | TXINT | STATINT);
1778 t4_read_reg(adapter, MPS_INT_CAUSE); /* flush */
1780 t4_fatal_err(adapter);
1783 #define MEM_INT_MASK (PERR_INT_CAUSE | ECC_CE_INT_CAUSE | ECC_UE_INT_CAUSE)
1786 * EDC/MC interrupt handler.
1788 static void mem_intr_handler(struct adapter *adapter, int idx)
1790 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
1792 unsigned int addr, cnt_addr, v;
1794 if (idx <= MEM_EDC1) {
1795 addr = EDC_REG(EDC_INT_CAUSE, idx);
1796 cnt_addr = EDC_REG(EDC_ECC_STATUS, idx);
1797 } else if (idx == MEM_MC) {
1798 if (is_t4(adapter->params.chip)) {
1799 addr = MC_INT_CAUSE;
1800 cnt_addr = MC_ECC_STATUS;
1802 addr = MC_P_INT_CAUSE;
1803 cnt_addr = MC_P_ECC_STATUS;
1806 addr = MC_REG(MC_P_INT_CAUSE, 1);
1807 cnt_addr = MC_REG(MC_P_ECC_STATUS, 1);
1810 v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
1811 if (v & PERR_INT_CAUSE)
1812 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
1814 if (v & ECC_CE_INT_CAUSE) {
1815 u32 cnt = ECC_CECNT_GET(t4_read_reg(adapter, cnt_addr));
1817 t4_write_reg(adapter, cnt_addr, ECC_CECNT_MASK);
1818 if (printk_ratelimit())
1819 dev_warn(adapter->pdev_dev,
1820 "%u %s correctable ECC data error%s\n",
1821 cnt, name[idx], cnt > 1 ? "s" : "");
1823 if (v & ECC_UE_INT_CAUSE)
1824 dev_alert(adapter->pdev_dev,
1825 "%s uncorrectable ECC data error\n", name[idx]);
1827 t4_write_reg(adapter, addr, v);
1828 if (v & (PERR_INT_CAUSE | ECC_UE_INT_CAUSE))
1829 t4_fatal_err(adapter);
1833 * MA interrupt handler.
1835 static void ma_intr_handler(struct adapter *adap)
1837 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE);
1839 if (status & MEM_PERR_INT_CAUSE) {
1840 dev_alert(adap->pdev_dev,
1841 "MA parity error, parity status %#x\n",
1842 t4_read_reg(adap, MA_PARITY_ERROR_STATUS));
1843 if (is_t5(adap->params.chip))
1844 dev_alert(adap->pdev_dev,
1845 "MA parity error, parity status %#x\n",
1847 MA_PARITY_ERROR_STATUS2));
1849 if (status & MEM_WRAP_INT_CAUSE) {
1850 v = t4_read_reg(adap, MA_INT_WRAP_STATUS);
1851 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
1852 "client %u to address %#x\n",
1853 MEM_WRAP_CLIENT_NUM_GET(v),
1854 MEM_WRAP_ADDRESS_GET(v) << 4);
1856 t4_write_reg(adap, MA_INT_CAUSE, status);
1861 * SMB interrupt handler.
1863 static void smb_intr_handler(struct adapter *adap)
1865 static const struct intr_info smb_intr_info[] = {
1866 { MSTTXFIFOPARINT, "SMB master Tx FIFO parity error", -1, 1 },
1867 { MSTRXFIFOPARINT, "SMB master Rx FIFO parity error", -1, 1 },
1868 { SLVFIFOPARINT, "SMB slave FIFO parity error", -1, 1 },
1872 if (t4_handle_intr_status(adap, SMB_INT_CAUSE, smb_intr_info))
1877 * NC-SI interrupt handler.
1879 static void ncsi_intr_handler(struct adapter *adap)
1881 static const struct intr_info ncsi_intr_info[] = {
1882 { CIM_DM_PRTY_ERR, "NC-SI CIM parity error", -1, 1 },
1883 { MPS_DM_PRTY_ERR, "NC-SI MPS parity error", -1, 1 },
1884 { TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error", -1, 1 },
1885 { RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error", -1, 1 },
1889 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE, ncsi_intr_info))
1894 * XGMAC interrupt handler.
1896 static void xgmac_intr_handler(struct adapter *adap, int port)
1898 u32 v, int_cause_reg;
1900 if (is_t4(adap->params.chip))
1901 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE);
1903 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE);
1905 v = t4_read_reg(adap, int_cause_reg);
1907 v &= TXFIFO_PRTY_ERR | RXFIFO_PRTY_ERR;
1911 if (v & TXFIFO_PRTY_ERR)
1912 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
1914 if (v & RXFIFO_PRTY_ERR)
1915 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
1917 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE), v);
1922 * PL interrupt handler.
1924 static void pl_intr_handler(struct adapter *adap)
1926 static const struct intr_info pl_intr_info[] = {
1927 { FATALPERR, "T4 fatal parity error", -1, 1 },
1928 { PERRVFID, "PL VFID_MAP parity error", -1, 1 },
1932 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE, pl_intr_info))
1936 #define PF_INTR_MASK (PFSW)
1937 #define GLBL_INTR_MASK (CIM | MPS | PL | PCIE | MC | EDC0 | \
1938 EDC1 | LE | TP | MA | PM_TX | PM_RX | ULP_RX | \
1939 CPL_SWITCH | SGE | ULP_TX)
1942 * t4_slow_intr_handler - control path interrupt handler
1943 * @adapter: the adapter
1945 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
1946 * The designation 'slow' is because it involves register reads, while
1947 * data interrupts typically don't involve any MMIOs.
1949 int t4_slow_intr_handler(struct adapter *adapter)
1951 u32 cause = t4_read_reg(adapter, PL_INT_CAUSE);
1953 if (!(cause & GLBL_INTR_MASK))
1956 cim_intr_handler(adapter);
1958 mps_intr_handler(adapter);
1960 ncsi_intr_handler(adapter);
1962 pl_intr_handler(adapter);
1964 smb_intr_handler(adapter);
1966 xgmac_intr_handler(adapter, 0);
1968 xgmac_intr_handler(adapter, 1);
1969 if (cause & XGMAC_KR0)
1970 xgmac_intr_handler(adapter, 2);
1971 if (cause & XGMAC_KR1)
1972 xgmac_intr_handler(adapter, 3);
1974 pcie_intr_handler(adapter);
1976 mem_intr_handler(adapter, MEM_MC);
1977 if (!is_t4(adapter->params.chip) && (cause & MC1))
1978 mem_intr_handler(adapter, MEM_MC1);
1980 mem_intr_handler(adapter, MEM_EDC0);
1982 mem_intr_handler(adapter, MEM_EDC1);
1984 le_intr_handler(adapter);
1986 tp_intr_handler(adapter);
1988 ma_intr_handler(adapter);
1990 pmtx_intr_handler(adapter);
1992 pmrx_intr_handler(adapter);
1994 ulprx_intr_handler(adapter);
1995 if (cause & CPL_SWITCH)
1996 cplsw_intr_handler(adapter);
1998 sge_intr_handler(adapter);
2000 ulptx_intr_handler(adapter);
2002 /* Clear the interrupts just processed for which we are the master. */
2003 t4_write_reg(adapter, PL_INT_CAUSE, cause & GLBL_INTR_MASK);
2004 (void) t4_read_reg(adapter, PL_INT_CAUSE); /* flush */
2009 * t4_intr_enable - enable interrupts
2010 * @adapter: the adapter whose interrupts should be enabled
2012 * Enable PF-specific interrupts for the calling function and the top-level
2013 * interrupt concentrator for global interrupts. Interrupts are already
2014 * enabled at each module, here we just enable the roots of the interrupt
2017 * Note: this function should be called only when the driver manages
2018 * non PF-specific interrupts from the various HW modules. Only one PCI
2019 * function at a time should be doing this.
2021 void t4_intr_enable(struct adapter *adapter)
2023 u32 pf = SOURCEPF_GET(t4_read_reg(adapter, PL_WHOAMI));
2025 t4_write_reg(adapter, SGE_INT_ENABLE3, ERR_CPL_EXCEED_IQE_SIZE |
2026 ERR_INVALID_CIDX_INC | ERR_CPL_OPCODE_0 |
2027 ERR_DROPPED_DB | ERR_DATA_CPL_ON_HIGH_QID1 |
2028 ERR_DATA_CPL_ON_HIGH_QID0 | ERR_BAD_DB_PIDX3 |
2029 ERR_BAD_DB_PIDX2 | ERR_BAD_DB_PIDX1 |
2030 ERR_BAD_DB_PIDX0 | ERR_ING_CTXT_PRIO |
2031 ERR_EGR_CTXT_PRIO | INGRESS_SIZE_ERR |
2032 DBFIFO_HP_INT | DBFIFO_LP_INT |
2034 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE), PF_INTR_MASK);
2035 t4_set_reg_field(adapter, PL_INT_MAP0, 0, 1 << pf);
2039 * t4_intr_disable - disable interrupts
2040 * @adapter: the adapter whose interrupts should be disabled
2042 * Disable interrupts. We only disable the top-level interrupt
2043 * concentrators. The caller must be a PCI function managing global
2046 void t4_intr_disable(struct adapter *adapter)
2048 u32 pf = SOURCEPF_GET(t4_read_reg(adapter, PL_WHOAMI));
2050 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE), 0);
2051 t4_set_reg_field(adapter, PL_INT_MAP0, 1 << pf, 0);
2055 * hash_mac_addr - return the hash value of a MAC address
2056 * @addr: the 48-bit Ethernet MAC address
2058 * Hashes a MAC address according to the hash function used by HW inexact
2059 * (hash) address matching.
2061 static int hash_mac_addr(const u8 *addr)
2063 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
2064 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
2072 * t4_config_rss_range - configure a portion of the RSS mapping table
2073 * @adapter: the adapter
2074 * @mbox: mbox to use for the FW command
2075 * @viid: virtual interface whose RSS subtable is to be written
2076 * @start: start entry in the table to write
2077 * @n: how many table entries to write
2078 * @rspq: values for the response queue lookup table
2079 * @nrspq: number of values in @rspq
2081 * Programs the selected part of the VI's RSS mapping table with the
2082 * provided values. If @nrspq < @n the supplied values are used repeatedly
2083 * until the full table range is populated.
2085 * The caller must ensure the values in @rspq are in the range allowed for
2088 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
2089 int start, int n, const u16 *rspq, unsigned int nrspq)
2092 const u16 *rsp = rspq;
2093 const u16 *rsp_end = rspq + nrspq;
2094 struct fw_rss_ind_tbl_cmd cmd;
2096 memset(&cmd, 0, sizeof(cmd));
2097 cmd.op_to_viid = htonl(FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
2098 FW_CMD_REQUEST | FW_CMD_WRITE |
2099 FW_RSS_IND_TBL_CMD_VIID(viid));
2100 cmd.retval_len16 = htonl(FW_LEN16(cmd));
2102 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
2104 int nq = min(n, 32);
2105 __be32 *qp = &cmd.iq0_to_iq2;
2107 cmd.niqid = htons(nq);
2108 cmd.startidx = htons(start);
2116 v = FW_RSS_IND_TBL_CMD_IQ0(*rsp);
2117 if (++rsp >= rsp_end)
2119 v |= FW_RSS_IND_TBL_CMD_IQ1(*rsp);
2120 if (++rsp >= rsp_end)
2122 v |= FW_RSS_IND_TBL_CMD_IQ2(*rsp);
2123 if (++rsp >= rsp_end)
2130 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
2138 * t4_config_glbl_rss - configure the global RSS mode
2139 * @adapter: the adapter
2140 * @mbox: mbox to use for the FW command
2141 * @mode: global RSS mode
2142 * @flags: mode-specific flags
2144 * Sets the global RSS mode.
2146 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
2149 struct fw_rss_glb_config_cmd c;
2151 memset(&c, 0, sizeof(c));
2152 c.op_to_write = htonl(FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) |
2153 FW_CMD_REQUEST | FW_CMD_WRITE);
2154 c.retval_len16 = htonl(FW_LEN16(c));
2155 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
2156 c.u.manual.mode_pkd = htonl(FW_RSS_GLB_CONFIG_CMD_MODE(mode));
2157 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
2158 c.u.basicvirtual.mode_pkd =
2159 htonl(FW_RSS_GLB_CONFIG_CMD_MODE(mode));
2160 c.u.basicvirtual.synmapen_to_hashtoeplitz = htonl(flags);
2163 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
2167 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
2168 * @adap: the adapter
2169 * @v4: holds the TCP/IP counter values
2170 * @v6: holds the TCP/IPv6 counter values
2172 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
2173 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
2175 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
2176 struct tp_tcp_stats *v6)
2178 u32 val[TP_MIB_TCP_RXT_SEG_LO - TP_MIB_TCP_OUT_RST + 1];
2180 #define STAT_IDX(x) ((TP_MIB_TCP_##x) - TP_MIB_TCP_OUT_RST)
2181 #define STAT(x) val[STAT_IDX(x)]
2182 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
2185 t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, val,
2186 ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST);
2187 v4->tcpOutRsts = STAT(OUT_RST);
2188 v4->tcpInSegs = STAT64(IN_SEG);
2189 v4->tcpOutSegs = STAT64(OUT_SEG);
2190 v4->tcpRetransSegs = STAT64(RXT_SEG);
2193 t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, val,
2194 ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST);
2195 v6->tcpOutRsts = STAT(OUT_RST);
2196 v6->tcpInSegs = STAT64(IN_SEG);
2197 v6->tcpOutSegs = STAT64(OUT_SEG);
2198 v6->tcpRetransSegs = STAT64(RXT_SEG);
2206 * t4_read_mtu_tbl - returns the values in the HW path MTU table
2207 * @adap: the adapter
2208 * @mtus: where to store the MTU values
2209 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
2211 * Reads the HW path MTU table.
2213 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
2218 for (i = 0; i < NMTUS; ++i) {
2219 t4_write_reg(adap, TP_MTU_TABLE,
2220 MTUINDEX(0xff) | MTUVALUE(i));
2221 v = t4_read_reg(adap, TP_MTU_TABLE);
2222 mtus[i] = MTUVALUE_GET(v);
2224 mtu_log[i] = MTUWIDTH_GET(v);
2229 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
2230 * @adap: the adapter
2231 * @addr: the indirect TP register address
2232 * @mask: specifies the field within the register to modify
2233 * @val: new value for the field
2235 * Sets a field of an indirect TP register to the given value.
2237 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
2238 unsigned int mask, unsigned int val)
2240 t4_write_reg(adap, TP_PIO_ADDR, addr);
2241 val |= t4_read_reg(adap, TP_PIO_DATA) & ~mask;
2242 t4_write_reg(adap, TP_PIO_DATA, val);
2246 * init_cong_ctrl - initialize congestion control parameters
2247 * @a: the alpha values for congestion control
2248 * @b: the beta values for congestion control
2250 * Initialize the congestion control parameters.
2252 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
2254 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
2279 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
2282 b[13] = b[14] = b[15] = b[16] = 3;
2283 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
2284 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
2289 /* The minimum additive increment value for the congestion control table */
2290 #define CC_MIN_INCR 2U
2293 * t4_load_mtus - write the MTU and congestion control HW tables
2294 * @adap: the adapter
2295 * @mtus: the values for the MTU table
2296 * @alpha: the values for the congestion control alpha parameter
2297 * @beta: the values for the congestion control beta parameter
2299 * Write the HW MTU table with the supplied MTUs and the high-speed
2300 * congestion control table with the supplied alpha, beta, and MTUs.
2301 * We write the two tables together because the additive increments
2302 * depend on the MTUs.
2304 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
2305 const unsigned short *alpha, const unsigned short *beta)
2307 static const unsigned int avg_pkts[NCCTRL_WIN] = {
2308 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
2309 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
2310 28672, 40960, 57344, 81920, 114688, 163840, 229376
2315 for (i = 0; i < NMTUS; ++i) {
2316 unsigned int mtu = mtus[i];
2317 unsigned int log2 = fls(mtu);
2319 if (!(mtu & ((1 << log2) >> 2))) /* round */
2321 t4_write_reg(adap, TP_MTU_TABLE, MTUINDEX(i) |
2322 MTUWIDTH(log2) | MTUVALUE(mtu));
2324 for (w = 0; w < NCCTRL_WIN; ++w) {
2327 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
2330 t4_write_reg(adap, TP_CCTRL_TABLE, (i << 21) |
2331 (w << 16) | (beta[w] << 13) | inc);
2337 * get_mps_bg_map - return the buffer groups associated with a port
2338 * @adap: the adapter
2339 * @idx: the port index
2341 * Returns a bitmap indicating which MPS buffer groups are associated
2342 * with the given port. Bit i is set if buffer group i is used by the
2345 static unsigned int get_mps_bg_map(struct adapter *adap, int idx)
2347 u32 n = NUMPORTS_GET(t4_read_reg(adap, MPS_CMN_CTL));
2350 return idx == 0 ? 0xf : 0;
2352 return idx < 2 ? (3 << (2 * idx)) : 0;
2357 * t4_get_port_type_description - return Port Type string description
2358 * @port_type: firmware Port Type enumeration
2360 const char *t4_get_port_type_description(enum fw_port_type port_type)
2362 static const char *const port_type_description[] = {
2381 if (port_type < ARRAY_SIZE(port_type_description))
2382 return port_type_description[port_type];
2387 * t4_get_port_stats - collect port statistics
2388 * @adap: the adapter
2389 * @idx: the port index
2390 * @p: the stats structure to fill
2392 * Collect statistics related to the given port from HW.
2394 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
2396 u32 bgmap = get_mps_bg_map(adap, idx);
2398 #define GET_STAT(name) \
2399 t4_read_reg64(adap, \
2400 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
2401 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
2402 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
2404 p->tx_octets = GET_STAT(TX_PORT_BYTES);
2405 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
2406 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
2407 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
2408 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
2409 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
2410 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
2411 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
2412 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
2413 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
2414 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
2415 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
2416 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
2417 p->tx_drop = GET_STAT(TX_PORT_DROP);
2418 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
2419 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
2420 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
2421 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
2422 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
2423 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
2424 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
2425 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
2426 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
2428 p->rx_octets = GET_STAT(RX_PORT_BYTES);
2429 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
2430 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
2431 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
2432 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
2433 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
2434 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
2435 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
2436 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
2437 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
2438 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
2439 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
2440 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
2441 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
2442 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
2443 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
2444 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
2445 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
2446 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
2447 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
2448 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
2449 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
2450 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
2451 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
2452 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
2453 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
2454 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
2456 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
2457 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
2458 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
2459 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
2460 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
2461 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
2462 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
2463 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
2470 * t4_wol_magic_enable - enable/disable magic packet WoL
2471 * @adap: the adapter
2472 * @port: the physical port index
2473 * @addr: MAC address expected in magic packets, %NULL to disable
2475 * Enables/disables magic packet wake-on-LAN for the selected port.
2477 void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
2480 u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg;
2482 if (is_t4(adap->params.chip)) {
2483 mag_id_reg_l = PORT_REG(port, XGMAC_PORT_MAGIC_MACID_LO);
2484 mag_id_reg_h = PORT_REG(port, XGMAC_PORT_MAGIC_MACID_HI);
2485 port_cfg_reg = PORT_REG(port, XGMAC_PORT_CFG2);
2487 mag_id_reg_l = T5_PORT_REG(port, MAC_PORT_MAGIC_MACID_LO);
2488 mag_id_reg_h = T5_PORT_REG(port, MAC_PORT_MAGIC_MACID_HI);
2489 port_cfg_reg = T5_PORT_REG(port, MAC_PORT_CFG2);
2493 t4_write_reg(adap, mag_id_reg_l,
2494 (addr[2] << 24) | (addr[3] << 16) |
2495 (addr[4] << 8) | addr[5]);
2496 t4_write_reg(adap, mag_id_reg_h,
2497 (addr[0] << 8) | addr[1]);
2499 t4_set_reg_field(adap, port_cfg_reg, MAGICEN,
2500 addr ? MAGICEN : 0);
2504 * t4_wol_pat_enable - enable/disable pattern-based WoL
2505 * @adap: the adapter
2506 * @port: the physical port index
2507 * @map: bitmap of which HW pattern filters to set
2508 * @mask0: byte mask for bytes 0-63 of a packet
2509 * @mask1: byte mask for bytes 64-127 of a packet
2510 * @crc: Ethernet CRC for selected bytes
2511 * @enable: enable/disable switch
2513 * Sets the pattern filters indicated in @map to mask out the bytes
2514 * specified in @mask0/@mask1 in received packets and compare the CRC of
2515 * the resulting packet against @crc. If @enable is %true pattern-based
2516 * WoL is enabled, otherwise disabled.
2518 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
2519 u64 mask0, u64 mask1, unsigned int crc, bool enable)
2524 if (is_t4(adap->params.chip))
2525 port_cfg_reg = PORT_REG(port, XGMAC_PORT_CFG2);
2527 port_cfg_reg = T5_PORT_REG(port, MAC_PORT_CFG2);
2530 t4_set_reg_field(adap, port_cfg_reg, PATEN, 0);
2536 #define EPIO_REG(name) \
2537 (is_t4(adap->params.chip) ? PORT_REG(port, XGMAC_PORT_EPIO_##name) : \
2538 T5_PORT_REG(port, MAC_PORT_EPIO_##name))
2540 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32);
2541 t4_write_reg(adap, EPIO_REG(DATA2), mask1);
2542 t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32);
2544 for (i = 0; i < NWOL_PAT; i++, map >>= 1) {
2548 /* write byte masks */
2549 t4_write_reg(adap, EPIO_REG(DATA0), mask0);
2550 t4_write_reg(adap, EPIO_REG(OP), ADDRESS(i) | EPIOWR);
2551 t4_read_reg(adap, EPIO_REG(OP)); /* flush */
2552 if (t4_read_reg(adap, EPIO_REG(OP)) & SF_BUSY)
2556 t4_write_reg(adap, EPIO_REG(DATA0), crc);
2557 t4_write_reg(adap, EPIO_REG(OP), ADDRESS(i + 32) | EPIOWR);
2558 t4_read_reg(adap, EPIO_REG(OP)); /* flush */
2559 if (t4_read_reg(adap, EPIO_REG(OP)) & SF_BUSY)
2564 t4_set_reg_field(adap, PORT_REG(port, XGMAC_PORT_CFG2), 0, PATEN);
2568 /* t4_mk_filtdelwr - create a delete filter WR
2569 * @ftid: the filter ID
2570 * @wr: the filter work request to populate
2571 * @qid: ingress queue to receive the delete notification
2573 * Creates a filter work request to delete the supplied filter. If @qid is
2574 * negative the delete notification is suppressed.
2576 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
2578 memset(wr, 0, sizeof(*wr));
2579 wr->op_pkd = htonl(FW_WR_OP(FW_FILTER_WR));
2580 wr->len16_pkd = htonl(FW_WR_LEN16(sizeof(*wr) / 16));
2581 wr->tid_to_iq = htonl(V_FW_FILTER_WR_TID(ftid) |
2582 V_FW_FILTER_WR_NOREPLY(qid < 0));
2583 wr->del_filter_to_l2tix = htonl(F_FW_FILTER_WR_DEL_FILTER);
2585 wr->rx_chan_rx_rpl_iq = htons(V_FW_FILTER_WR_RX_RPL_IQ(qid));
2588 #define INIT_CMD(var, cmd, rd_wr) do { \
2589 (var).op_to_write = htonl(FW_CMD_OP(FW_##cmd##_CMD) | \
2590 FW_CMD_REQUEST | FW_CMD_##rd_wr); \
2591 (var).retval_len16 = htonl(FW_LEN16(var)); \
2594 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
2597 struct fw_ldst_cmd c;
2599 memset(&c, 0, sizeof(c));
2600 c.op_to_addrspace = htonl(FW_CMD_OP(FW_LDST_CMD) | FW_CMD_REQUEST |
2602 FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE));
2603 c.cycles_to_len16 = htonl(FW_LEN16(c));
2604 c.u.addrval.addr = htonl(addr);
2605 c.u.addrval.val = htonl(val);
2607 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2611 * t4_mdio_rd - read a PHY register through MDIO
2612 * @adap: the adapter
2613 * @mbox: mailbox to use for the FW command
2614 * @phy_addr: the PHY address
2615 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
2616 * @reg: the register to read
2617 * @valp: where to store the value
2619 * Issues a FW command through the given mailbox to read a PHY register.
2621 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
2622 unsigned int mmd, unsigned int reg, u16 *valp)
2625 struct fw_ldst_cmd c;
2627 memset(&c, 0, sizeof(c));
2628 c.op_to_addrspace = htonl(FW_CMD_OP(FW_LDST_CMD) | FW_CMD_REQUEST |
2629 FW_CMD_READ | FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO));
2630 c.cycles_to_len16 = htonl(FW_LEN16(c));
2631 c.u.mdio.paddr_mmd = htons(FW_LDST_CMD_PADDR(phy_addr) |
2632 FW_LDST_CMD_MMD(mmd));
2633 c.u.mdio.raddr = htons(reg);
2635 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2637 *valp = ntohs(c.u.mdio.rval);
2642 * t4_mdio_wr - write a PHY register through MDIO
2643 * @adap: the adapter
2644 * @mbox: mailbox to use for the FW command
2645 * @phy_addr: the PHY address
2646 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
2647 * @reg: the register to write
2648 * @valp: value to write
2650 * Issues a FW command through the given mailbox to write a PHY register.
2652 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
2653 unsigned int mmd, unsigned int reg, u16 val)
2655 struct fw_ldst_cmd c;
2657 memset(&c, 0, sizeof(c));
2658 c.op_to_addrspace = htonl(FW_CMD_OP(FW_LDST_CMD) | FW_CMD_REQUEST |
2659 FW_CMD_WRITE | FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO));
2660 c.cycles_to_len16 = htonl(FW_LEN16(c));
2661 c.u.mdio.paddr_mmd = htons(FW_LDST_CMD_PADDR(phy_addr) |
2662 FW_LDST_CMD_MMD(mmd));
2663 c.u.mdio.raddr = htons(reg);
2664 c.u.mdio.rval = htons(val);
2666 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2670 * t4_sge_decode_idma_state - decode the idma state
2671 * @adap: the adapter
2672 * @state: the state idma is stuck in
2674 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
2676 static const char * const t4_decode[] = {
2678 "IDMA_PUSH_MORE_CPL_FIFO",
2679 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
2681 "IDMA_PHYSADDR_SEND_PCIEHDR",
2682 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
2683 "IDMA_PHYSADDR_SEND_PAYLOAD",
2684 "IDMA_SEND_FIFO_TO_IMSG",
2685 "IDMA_FL_REQ_DATA_FL_PREP",
2686 "IDMA_FL_REQ_DATA_FL",
2688 "IDMA_FL_H_REQ_HEADER_FL",
2689 "IDMA_FL_H_SEND_PCIEHDR",
2690 "IDMA_FL_H_PUSH_CPL_FIFO",
2691 "IDMA_FL_H_SEND_CPL",
2692 "IDMA_FL_H_SEND_IP_HDR_FIRST",
2693 "IDMA_FL_H_SEND_IP_HDR",
2694 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
2695 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
2696 "IDMA_FL_H_SEND_IP_HDR_PADDING",
2697 "IDMA_FL_D_SEND_PCIEHDR",
2698 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
2699 "IDMA_FL_D_REQ_NEXT_DATA_FL",
2700 "IDMA_FL_SEND_PCIEHDR",
2701 "IDMA_FL_PUSH_CPL_FIFO",
2703 "IDMA_FL_SEND_PAYLOAD_FIRST",
2704 "IDMA_FL_SEND_PAYLOAD",
2705 "IDMA_FL_REQ_NEXT_DATA_FL",
2706 "IDMA_FL_SEND_NEXT_PCIEHDR",
2707 "IDMA_FL_SEND_PADDING",
2708 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
2709 "IDMA_FL_SEND_FIFO_TO_IMSG",
2710 "IDMA_FL_REQ_DATAFL_DONE",
2711 "IDMA_FL_REQ_HEADERFL_DONE",
2713 static const char * const t5_decode[] = {
2716 "IDMA_PUSH_MORE_CPL_FIFO",
2717 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
2718 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
2719 "IDMA_PHYSADDR_SEND_PCIEHDR",
2720 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
2721 "IDMA_PHYSADDR_SEND_PAYLOAD",
2722 "IDMA_SEND_FIFO_TO_IMSG",
2723 "IDMA_FL_REQ_DATA_FL",
2725 "IDMA_FL_DROP_SEND_INC",
2726 "IDMA_FL_H_REQ_HEADER_FL",
2727 "IDMA_FL_H_SEND_PCIEHDR",
2728 "IDMA_FL_H_PUSH_CPL_FIFO",
2729 "IDMA_FL_H_SEND_CPL",
2730 "IDMA_FL_H_SEND_IP_HDR_FIRST",
2731 "IDMA_FL_H_SEND_IP_HDR",
2732 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
2733 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
2734 "IDMA_FL_H_SEND_IP_HDR_PADDING",
2735 "IDMA_FL_D_SEND_PCIEHDR",
2736 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
2737 "IDMA_FL_D_REQ_NEXT_DATA_FL",
2738 "IDMA_FL_SEND_PCIEHDR",
2739 "IDMA_FL_PUSH_CPL_FIFO",
2741 "IDMA_FL_SEND_PAYLOAD_FIRST",
2742 "IDMA_FL_SEND_PAYLOAD",
2743 "IDMA_FL_REQ_NEXT_DATA_FL",
2744 "IDMA_FL_SEND_NEXT_PCIEHDR",
2745 "IDMA_FL_SEND_PADDING",
2746 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
2748 static const u32 sge_regs[] = {
2749 SGE_DEBUG_DATA_LOW_INDEX_2,
2750 SGE_DEBUG_DATA_LOW_INDEX_3,
2751 SGE_DEBUG_DATA_HIGH_INDEX_10,
2753 const char **sge_idma_decode;
2754 int sge_idma_decode_nstates;
2757 if (is_t4(adapter->params.chip)) {
2758 sge_idma_decode = (const char **)t4_decode;
2759 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
2761 sge_idma_decode = (const char **)t5_decode;
2762 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
2765 if (state < sge_idma_decode_nstates)
2766 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
2768 CH_WARN(adapter, "idma state %d unknown\n", state);
2770 for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
2771 CH_WARN(adapter, "SGE register %#x value %#x\n",
2772 sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
2776 * t4_fw_hello - establish communication with FW
2777 * @adap: the adapter
2778 * @mbox: mailbox to use for the FW command
2779 * @evt_mbox: mailbox to receive async FW events
2780 * @master: specifies the caller's willingness to be the device master
2781 * @state: returns the current device state (if non-NULL)
2783 * Issues a command to establish communication with FW. Returns either
2784 * an error (negative integer) or the mailbox of the Master PF.
2786 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
2787 enum dev_master master, enum dev_state *state)
2790 struct fw_hello_cmd c;
2792 unsigned int master_mbox;
2793 int retries = FW_CMD_HELLO_RETRIES;
2796 memset(&c, 0, sizeof(c));
2797 INIT_CMD(c, HELLO, WRITE);
2798 c.err_to_clearinit = htonl(
2799 FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
2800 FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
2801 FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox :
2802 FW_HELLO_CMD_MBMASTER_MASK) |
2803 FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
2804 FW_HELLO_CMD_STAGE(fw_hello_cmd_stage_os) |
2805 FW_HELLO_CMD_CLEARINIT);
2808 * Issue the HELLO command to the firmware. If it's not successful
2809 * but indicates that we got a "busy" or "timeout" condition, retry
2810 * the HELLO until we exhaust our retry limit. If we do exceed our
2811 * retry limit, check to see if the firmware left us any error
2812 * information and report that if so.
2814 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2816 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
2818 if (t4_read_reg(adap, MA_PCIE_FW) & FW_PCIE_FW_ERR)
2819 t4_report_fw_error(adap);
2823 v = ntohl(c.err_to_clearinit);
2824 master_mbox = FW_HELLO_CMD_MBMASTER_GET(v);
2826 if (v & FW_HELLO_CMD_ERR)
2827 *state = DEV_STATE_ERR;
2828 else if (v & FW_HELLO_CMD_INIT)
2829 *state = DEV_STATE_INIT;
2831 *state = DEV_STATE_UNINIT;
2835 * If we're not the Master PF then we need to wait around for the
2836 * Master PF Driver to finish setting up the adapter.
2838 * Note that we also do this wait if we're a non-Master-capable PF and
2839 * there is no current Master PF; a Master PF may show up momentarily
2840 * and we wouldn't want to fail pointlessly. (This can happen when an
2841 * OS loads lots of different drivers rapidly at the same time). In
2842 * this case, the Master PF returned by the firmware will be
2843 * FW_PCIE_FW_MASTER_MASK so the test below will work ...
2845 if ((v & (FW_HELLO_CMD_ERR|FW_HELLO_CMD_INIT)) == 0 &&
2846 master_mbox != mbox) {
2847 int waiting = FW_CMD_HELLO_TIMEOUT;
2850 * Wait for the firmware to either indicate an error or
2851 * initialized state. If we see either of these we bail out
2852 * and report the issue to the caller. If we exhaust the
2853 * "hello timeout" and we haven't exhausted our retries, try
2854 * again. Otherwise bail with a timeout error.
2863 * If neither Error nor Initialialized are indicated
2864 * by the firmware keep waiting till we exaust our
2865 * timeout ... and then retry if we haven't exhausted
2868 pcie_fw = t4_read_reg(adap, MA_PCIE_FW);
2869 if (!(pcie_fw & (FW_PCIE_FW_ERR|FW_PCIE_FW_INIT))) {
2880 * We either have an Error or Initialized condition
2881 * report errors preferentially.
2884 if (pcie_fw & FW_PCIE_FW_ERR)
2885 *state = DEV_STATE_ERR;
2886 else if (pcie_fw & FW_PCIE_FW_INIT)
2887 *state = DEV_STATE_INIT;
2891 * If we arrived before a Master PF was selected and
2892 * there's not a valid Master PF, grab its identity
2895 if (master_mbox == FW_PCIE_FW_MASTER_MASK &&
2896 (pcie_fw & FW_PCIE_FW_MASTER_VLD))
2897 master_mbox = FW_PCIE_FW_MASTER_GET(pcie_fw);
2906 * t4_fw_bye - end communication with FW
2907 * @adap: the adapter
2908 * @mbox: mailbox to use for the FW command
2910 * Issues a command to terminate communication with FW.
2912 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
2914 struct fw_bye_cmd c;
2916 memset(&c, 0, sizeof(c));
2917 INIT_CMD(c, BYE, WRITE);
2918 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2922 * t4_init_cmd - ask FW to initialize the device
2923 * @adap: the adapter
2924 * @mbox: mailbox to use for the FW command
2926 * Issues a command to FW to partially initialize the device. This
2927 * performs initialization that generally doesn't depend on user input.
2929 int t4_early_init(struct adapter *adap, unsigned int mbox)
2931 struct fw_initialize_cmd c;
2933 memset(&c, 0, sizeof(c));
2934 INIT_CMD(c, INITIALIZE, WRITE);
2935 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2939 * t4_fw_reset - issue a reset to FW
2940 * @adap: the adapter
2941 * @mbox: mailbox to use for the FW command
2942 * @reset: specifies the type of reset to perform
2944 * Issues a reset command of the specified type to FW.
2946 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
2948 struct fw_reset_cmd c;
2950 memset(&c, 0, sizeof(c));
2951 INIT_CMD(c, RESET, WRITE);
2952 c.val = htonl(reset);
2953 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2957 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
2958 * @adap: the adapter
2959 * @mbox: mailbox to use for the FW RESET command (if desired)
2960 * @force: force uP into RESET even if FW RESET command fails
2962 * Issues a RESET command to firmware (if desired) with a HALT indication
2963 * and then puts the microprocessor into RESET state. The RESET command
2964 * will only be issued if a legitimate mailbox is provided (mbox <=
2965 * FW_PCIE_FW_MASTER_MASK).
2967 * This is generally used in order for the host to safely manipulate the
2968 * adapter without fear of conflicting with whatever the firmware might
2969 * be doing. The only way out of this state is to RESTART the firmware
2972 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
2977 * If a legitimate mailbox is provided, issue a RESET command
2978 * with a HALT indication.
2980 if (mbox <= FW_PCIE_FW_MASTER_MASK) {
2981 struct fw_reset_cmd c;
2983 memset(&c, 0, sizeof(c));
2984 INIT_CMD(c, RESET, WRITE);
2985 c.val = htonl(PIORST | PIORSTMODE);
2986 c.halt_pkd = htonl(FW_RESET_CMD_HALT(1U));
2987 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2991 * Normally we won't complete the operation if the firmware RESET
2992 * command fails but if our caller insists we'll go ahead and put the
2993 * uP into RESET. This can be useful if the firmware is hung or even
2994 * missing ... We'll have to take the risk of putting the uP into
2995 * RESET without the cooperation of firmware in that case.
2997 * We also force the firmware's HALT flag to be on in case we bypassed
2998 * the firmware RESET command above or we're dealing with old firmware
2999 * which doesn't have the HALT capability. This will serve as a flag
3000 * for the incoming firmware to know that it's coming out of a HALT
3001 * rather than a RESET ... if it's new enough to understand that ...
3003 if (ret == 0 || force) {
3004 t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, UPCRST);
3005 t4_set_reg_field(adap, PCIE_FW, FW_PCIE_FW_HALT,
3010 * And we always return the result of the firmware RESET command
3011 * even when we force the uP into RESET ...
3017 * t4_fw_restart - restart the firmware by taking the uP out of RESET
3018 * @adap: the adapter
3019 * @reset: if we want to do a RESET to restart things
3021 * Restart firmware previously halted by t4_fw_halt(). On successful
3022 * return the previous PF Master remains as the new PF Master and there
3023 * is no need to issue a new HELLO command, etc.
3025 * We do this in two ways:
3027 * 1. If we're dealing with newer firmware we'll simply want to take
3028 * the chip's microprocessor out of RESET. This will cause the
3029 * firmware to start up from its start vector. And then we'll loop
3030 * until the firmware indicates it's started again (PCIE_FW.HALT
3031 * reset to 0) or we timeout.
3033 * 2. If we're dealing with older firmware then we'll need to RESET
3034 * the chip since older firmware won't recognize the PCIE_FW.HALT
3035 * flag and automatically RESET itself on startup.
3037 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
3041 * Since we're directing the RESET instead of the firmware
3042 * doing it automatically, we need to clear the PCIE_FW.HALT
3045 t4_set_reg_field(adap, PCIE_FW, FW_PCIE_FW_HALT, 0);
3048 * If we've been given a valid mailbox, first try to get the
3049 * firmware to do the RESET. If that works, great and we can
3050 * return success. Otherwise, if we haven't been given a
3051 * valid mailbox or the RESET command failed, fall back to
3052 * hitting the chip with a hammer.
3054 if (mbox <= FW_PCIE_FW_MASTER_MASK) {
3055 t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, 0);
3057 if (t4_fw_reset(adap, mbox,
3058 PIORST | PIORSTMODE) == 0)
3062 t4_write_reg(adap, PL_RST, PIORST | PIORSTMODE);
3067 t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, 0);
3068 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
3069 if (!(t4_read_reg(adap, PCIE_FW) & FW_PCIE_FW_HALT))
3080 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
3081 * @adap: the adapter
3082 * @mbox: mailbox to use for the FW RESET command (if desired)
3083 * @fw_data: the firmware image to write
3085 * @force: force upgrade even if firmware doesn't cooperate
3087 * Perform all of the steps necessary for upgrading an adapter's
3088 * firmware image. Normally this requires the cooperation of the
3089 * existing firmware in order to halt all existing activities
3090 * but if an invalid mailbox token is passed in we skip that step
3091 * (though we'll still put the adapter microprocessor into RESET in
3094 * On successful return the new firmware will have been loaded and
3095 * the adapter will have been fully RESET losing all previous setup
3096 * state. On unsuccessful return the adapter may be completely hosed ...
3097 * positive errno indicates that the adapter is ~probably~ intact, a
3098 * negative errno indicates that things are looking bad ...
3100 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
3101 const u8 *fw_data, unsigned int size, int force)
3103 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
3106 if (!t4_fw_matches_chip(adap, fw_hdr))
3109 ret = t4_fw_halt(adap, mbox, force);
3110 if (ret < 0 && !force)
3113 ret = t4_load_fw(adap, fw_data, size);
3118 * Older versions of the firmware don't understand the new
3119 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
3120 * restart. So for newly loaded older firmware we'll have to do the
3121 * RESET for it so it starts up on a clean slate. We can tell if
3122 * the newly loaded firmware will handle this right by checking
3123 * its header flags to see if it advertises the capability.
3125 reset = ((ntohl(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
3126 return t4_fw_restart(adap, mbox, reset);
3130 * t4_fixup_host_params - fix up host-dependent parameters
3131 * @adap: the adapter
3132 * @page_size: the host's Base Page Size
3133 * @cache_line_size: the host's Cache Line Size
3135 * Various registers in T4 contain values which are dependent on the
3136 * host's Base Page and Cache Line Sizes. This function will fix all of
3137 * those registers with the appropriate values as passed in ...
3139 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
3140 unsigned int cache_line_size)
3142 unsigned int page_shift = fls(page_size) - 1;
3143 unsigned int sge_hps = page_shift - 10;
3144 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
3145 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
3146 unsigned int fl_align_log = fls(fl_align) - 1;
3148 t4_write_reg(adap, SGE_HOST_PAGE_SIZE,
3149 HOSTPAGESIZEPF0(sge_hps) |
3150 HOSTPAGESIZEPF1(sge_hps) |
3151 HOSTPAGESIZEPF2(sge_hps) |
3152 HOSTPAGESIZEPF3(sge_hps) |
3153 HOSTPAGESIZEPF4(sge_hps) |
3154 HOSTPAGESIZEPF5(sge_hps) |
3155 HOSTPAGESIZEPF6(sge_hps) |
3156 HOSTPAGESIZEPF7(sge_hps));
3158 if (is_t4(adap->params.chip)) {
3159 t4_set_reg_field(adap, SGE_CONTROL,
3160 INGPADBOUNDARY_MASK |
3161 EGRSTATUSPAGESIZE_MASK,
3162 INGPADBOUNDARY(fl_align_log - 5) |
3163 EGRSTATUSPAGESIZE(stat_len != 64));
3165 /* T5 introduced the separation of the Free List Padding and
3166 * Packing Boundaries. Thus, we can select a smaller Padding
3167 * Boundary to avoid uselessly chewing up PCIe Link and Memory
3168 * Bandwidth, and use a Packing Boundary which is large enough
3169 * to avoid false sharing between CPUs, etc.
3171 * For the PCI Link, the smaller the Padding Boundary the
3172 * better. For the Memory Controller, a smaller Padding
3173 * Boundary is better until we cross under the Memory Line
3174 * Size (the minimum unit of transfer to/from Memory). If we
3175 * have a Padding Boundary which is smaller than the Memory
3176 * Line Size, that'll involve a Read-Modify-Write cycle on the
3177 * Memory Controller which is never good. For T5 the smallest
3178 * Padding Boundary which we can select is 32 bytes which is
3179 * larger than any known Memory Controller Line Size so we'll
3182 * T5 has a different interpretation of the "0" value for the
3183 * Packing Boundary. This corresponds to 16 bytes instead of
3184 * the expected 32 bytes. We never have a Packing Boundary
3185 * less than 32 bytes so we can't use that special value but
3186 * on the other hand, if we wanted 32 bytes, the best we can
3187 * really do is 64 bytes.
3189 if (fl_align <= 32) {
3193 t4_set_reg_field(adap, SGE_CONTROL,
3194 INGPADBOUNDARY_MASK |
3195 EGRSTATUSPAGESIZE_MASK,
3196 INGPADBOUNDARY(INGPCIEBOUNDARY_32B_X) |
3197 EGRSTATUSPAGESIZE(stat_len != 64));
3198 t4_set_reg_field(adap, SGE_CONTROL2_A,
3199 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
3200 INGPACKBOUNDARY_V(fl_align_log -
3201 INGPACKBOUNDARY_SHIFT_X));
3204 * Adjust various SGE Free List Host Buffer Sizes.
3206 * This is something of a crock since we're using fixed indices into
3207 * the array which are also known by the sge.c code and the T4
3208 * Firmware Configuration File. We need to come up with a much better
3209 * approach to managing this array. For now, the first four entries
3214 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
3215 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
3217 * For the single-MTU buffers in unpacked mode we need to include
3218 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
3219 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
3220 * Padding boundry. All of these are accommodated in the Factory
3221 * Default Firmware Configuration File but we need to adjust it for
3222 * this host's cache line size.
3224 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0, page_size);
3225 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2,
3226 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2) + fl_align-1)
3228 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3,
3229 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3) + fl_align-1)
3232 t4_write_reg(adap, ULP_RX_TDDP_PSZ, HPZ0(page_shift - 12));
3238 * t4_fw_initialize - ask FW to initialize the device
3239 * @adap: the adapter
3240 * @mbox: mailbox to use for the FW command
3242 * Issues a command to FW to partially initialize the device. This
3243 * performs initialization that generally doesn't depend on user input.
3245 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
3247 struct fw_initialize_cmd c;
3249 memset(&c, 0, sizeof(c));
3250 INIT_CMD(c, INITIALIZE, WRITE);
3251 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3255 * t4_query_params - query FW or device parameters
3256 * @adap: the adapter
3257 * @mbox: mailbox to use for the FW command
3260 * @nparams: the number of parameters
3261 * @params: the parameter names
3262 * @val: the parameter values
3264 * Reads the value of FW or device parameters. Up to 7 parameters can be
3267 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3268 unsigned int vf, unsigned int nparams, const u32 *params,
3272 struct fw_params_cmd c;
3273 __be32 *p = &c.param[0].mnem;
3278 memset(&c, 0, sizeof(c));
3279 c.op_to_vfn = htonl(FW_CMD_OP(FW_PARAMS_CMD) | FW_CMD_REQUEST |
3280 FW_CMD_READ | FW_PARAMS_CMD_PFN(pf) |
3281 FW_PARAMS_CMD_VFN(vf));
3282 c.retval_len16 = htonl(FW_LEN16(c));
3283 for (i = 0; i < nparams; i++, p += 2)
3284 *p = htonl(*params++);
3286 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3288 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
3294 * t4_set_params_nosleep - sets FW or device parameters
3295 * @adap: the adapter
3296 * @mbox: mailbox to use for the FW command
3299 * @nparams: the number of parameters
3300 * @params: the parameter names
3301 * @val: the parameter values
3303 * Does not ever sleep
3304 * Sets the value of FW or device parameters. Up to 7 parameters can be
3305 * specified at once.
3307 int t4_set_params_nosleep(struct adapter *adap, unsigned int mbox,
3308 unsigned int pf, unsigned int vf,
3309 unsigned int nparams, const u32 *params,
3312 struct fw_params_cmd c;
3313 __be32 *p = &c.param[0].mnem;
3318 memset(&c, 0, sizeof(c));
3319 c.op_to_vfn = cpu_to_be32(FW_CMD_OP(FW_PARAMS_CMD) |
3320 FW_CMD_REQUEST | FW_CMD_WRITE |
3321 FW_PARAMS_CMD_PFN(pf) |
3322 FW_PARAMS_CMD_VFN(vf));
3323 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3326 *p++ = cpu_to_be32(*params++);
3327 *p++ = cpu_to_be32(*val++);
3330 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
3334 * t4_set_params - sets FW or device parameters
3335 * @adap: the adapter
3336 * @mbox: mailbox to use for the FW command
3339 * @nparams: the number of parameters
3340 * @params: the parameter names
3341 * @val: the parameter values
3343 * Sets the value of FW or device parameters. Up to 7 parameters can be
3344 * specified at once.
3346 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3347 unsigned int vf, unsigned int nparams, const u32 *params,
3350 struct fw_params_cmd c;
3351 __be32 *p = &c.param[0].mnem;
3356 memset(&c, 0, sizeof(c));
3357 c.op_to_vfn = htonl(FW_CMD_OP(FW_PARAMS_CMD) | FW_CMD_REQUEST |
3358 FW_CMD_WRITE | FW_PARAMS_CMD_PFN(pf) |
3359 FW_PARAMS_CMD_VFN(vf));
3360 c.retval_len16 = htonl(FW_LEN16(c));
3362 *p++ = htonl(*params++);
3363 *p++ = htonl(*val++);
3366 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3370 * t4_cfg_pfvf - configure PF/VF resource limits
3371 * @adap: the adapter
3372 * @mbox: mailbox to use for the FW command
3373 * @pf: the PF being configured
3374 * @vf: the VF being configured
3375 * @txq: the max number of egress queues
3376 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
3377 * @rxqi: the max number of interrupt-capable ingress queues
3378 * @rxq: the max number of interruptless ingress queues
3379 * @tc: the PCI traffic class
3380 * @vi: the max number of virtual interfaces
3381 * @cmask: the channel access rights mask for the PF/VF
3382 * @pmask: the port access rights mask for the PF/VF
3383 * @nexact: the maximum number of exact MPS filters
3384 * @rcaps: read capabilities
3385 * @wxcaps: write/execute capabilities
3387 * Configures resource limits and capabilities for a physical or virtual
3390 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
3391 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
3392 unsigned int rxqi, unsigned int rxq, unsigned int tc,
3393 unsigned int vi, unsigned int cmask, unsigned int pmask,
3394 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
3396 struct fw_pfvf_cmd c;
3398 memset(&c, 0, sizeof(c));
3399 c.op_to_vfn = htonl(FW_CMD_OP(FW_PFVF_CMD) | FW_CMD_REQUEST |
3400 FW_CMD_WRITE | FW_PFVF_CMD_PFN(pf) |
3401 FW_PFVF_CMD_VFN(vf));
3402 c.retval_len16 = htonl(FW_LEN16(c));
3403 c.niqflint_niq = htonl(FW_PFVF_CMD_NIQFLINT(rxqi) |
3404 FW_PFVF_CMD_NIQ(rxq));
3405 c.type_to_neq = htonl(FW_PFVF_CMD_CMASK(cmask) |
3406 FW_PFVF_CMD_PMASK(pmask) |
3407 FW_PFVF_CMD_NEQ(txq));
3408 c.tc_to_nexactf = htonl(FW_PFVF_CMD_TC(tc) | FW_PFVF_CMD_NVI(vi) |
3409 FW_PFVF_CMD_NEXACTF(nexact));
3410 c.r_caps_to_nethctrl = htonl(FW_PFVF_CMD_R_CAPS(rcaps) |
3411 FW_PFVF_CMD_WX_CAPS(wxcaps) |
3412 FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl));
3413 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3417 * t4_alloc_vi - allocate a virtual interface
3418 * @adap: the adapter
3419 * @mbox: mailbox to use for the FW command
3420 * @port: physical port associated with the VI
3421 * @pf: the PF owning the VI
3422 * @vf: the VF owning the VI
3423 * @nmac: number of MAC addresses needed (1 to 5)
3424 * @mac: the MAC addresses of the VI
3425 * @rss_size: size of RSS table slice associated with this VI
3427 * Allocates a virtual interface for the given physical port. If @mac is
3428 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
3429 * @mac should be large enough to hold @nmac Ethernet addresses, they are
3430 * stored consecutively so the space needed is @nmac * 6 bytes.
3431 * Returns a negative error number or the non-negative VI id.
3433 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
3434 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
3435 unsigned int *rss_size)
3440 memset(&c, 0, sizeof(c));
3441 c.op_to_vfn = htonl(FW_CMD_OP(FW_VI_CMD) | FW_CMD_REQUEST |
3442 FW_CMD_WRITE | FW_CMD_EXEC |
3443 FW_VI_CMD_PFN(pf) | FW_VI_CMD_VFN(vf));
3444 c.alloc_to_len16 = htonl(FW_VI_CMD_ALLOC | FW_LEN16(c));
3445 c.portid_pkd = FW_VI_CMD_PORTID(port);
3448 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3453 memcpy(mac, c.mac, sizeof(c.mac));
3456 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
3458 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
3460 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
3462 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
3466 *rss_size = FW_VI_CMD_RSSSIZE_GET(ntohs(c.rsssize_pkd));
3467 return FW_VI_CMD_VIID_GET(ntohs(c.type_viid));
3471 * t4_set_rxmode - set Rx properties of a virtual interface
3472 * @adap: the adapter
3473 * @mbox: mailbox to use for the FW command
3475 * @mtu: the new MTU or -1
3476 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
3477 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
3478 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
3479 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
3480 * @sleep_ok: if true we may sleep while awaiting command completion
3482 * Sets Rx properties of a virtual interface.
3484 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
3485 int mtu, int promisc, int all_multi, int bcast, int vlanex,
3488 struct fw_vi_rxmode_cmd c;
3490 /* convert to FW values */
3492 mtu = FW_RXMODE_MTU_NO_CHG;
3494 promisc = FW_VI_RXMODE_CMD_PROMISCEN_MASK;
3496 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_MASK;
3498 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_MASK;
3500 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_MASK;
3502 memset(&c, 0, sizeof(c));
3503 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_RXMODE_CMD) | FW_CMD_REQUEST |
3504 FW_CMD_WRITE | FW_VI_RXMODE_CMD_VIID(viid));
3505 c.retval_len16 = htonl(FW_LEN16(c));
3506 c.mtu_to_vlanexen = htonl(FW_VI_RXMODE_CMD_MTU(mtu) |
3507 FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
3508 FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
3509 FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
3510 FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
3511 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
3515 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
3516 * @adap: the adapter
3517 * @mbox: mailbox to use for the FW command
3519 * @free: if true any existing filters for this VI id are first removed
3520 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
3521 * @addr: the MAC address(es)
3522 * @idx: where to store the index of each allocated filter
3523 * @hash: pointer to hash address filter bitmap
3524 * @sleep_ok: call is allowed to sleep
3526 * Allocates an exact-match filter for each of the supplied addresses and
3527 * sets it to the corresponding address. If @idx is not %NULL it should
3528 * have at least @naddr entries, each of which will be set to the index of
3529 * the filter allocated for the corresponding MAC address. If a filter
3530 * could not be allocated for an address its index is set to 0xffff.
3531 * If @hash is not %NULL addresses that fail to allocate an exact filter
3532 * are hashed and update the hash filter bitmap pointed at by @hash.
3534 * Returns a negative error number or the number of filters allocated.
3536 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
3537 unsigned int viid, bool free, unsigned int naddr,
3538 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
3541 struct fw_vi_mac_cmd c;
3542 struct fw_vi_mac_exact *p;
3543 unsigned int max_naddr = is_t4(adap->params.chip) ?
3544 NUM_MPS_CLS_SRAM_L_INSTANCES :
3545 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
3550 memset(&c, 0, sizeof(c));
3551 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_MAC_CMD) | FW_CMD_REQUEST |
3552 FW_CMD_WRITE | (free ? FW_CMD_EXEC : 0) |
3553 FW_VI_MAC_CMD_VIID(viid));
3554 c.freemacs_to_len16 = htonl(FW_VI_MAC_CMD_FREEMACS(free) |
3555 FW_CMD_LEN16((naddr + 2) / 2));
3557 for (i = 0, p = c.u.exact; i < naddr; i++, p++) {
3558 p->valid_to_idx = htons(FW_VI_MAC_CMD_VALID |
3559 FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC));
3560 memcpy(p->macaddr, addr[i], sizeof(p->macaddr));
3563 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
3567 for (i = 0, p = c.u.exact; i < naddr; i++, p++) {
3568 u16 index = FW_VI_MAC_CMD_IDX_GET(ntohs(p->valid_to_idx));
3571 idx[i] = index >= max_naddr ? 0xffff : index;
3572 if (index < max_naddr)
3575 *hash |= (1ULL << hash_mac_addr(addr[i]));
3581 * t4_change_mac - modifies the exact-match filter for a MAC address
3582 * @adap: the adapter
3583 * @mbox: mailbox to use for the FW command
3585 * @idx: index of existing filter for old value of MAC address, or -1
3586 * @addr: the new MAC address value
3587 * @persist: whether a new MAC allocation should be persistent
3588 * @add_smt: if true also add the address to the HW SMT
3590 * Modifies an exact-match filter and sets it to the new MAC address.
3591 * Note that in general it is not possible to modify the value of a given
3592 * filter so the generic way to modify an address filter is to free the one
3593 * being used by the old address value and allocate a new filter for the
3594 * new address value. @idx can be -1 if the address is a new addition.
3596 * Returns a negative error number or the index of the filter with the new
3599 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
3600 int idx, const u8 *addr, bool persist, bool add_smt)
3603 struct fw_vi_mac_cmd c;
3604 struct fw_vi_mac_exact *p = c.u.exact;
3605 unsigned int max_mac_addr = is_t4(adap->params.chip) ?
3606 NUM_MPS_CLS_SRAM_L_INSTANCES :
3607 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
3609 if (idx < 0) /* new allocation */
3610 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
3611 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
3613 memset(&c, 0, sizeof(c));
3614 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_MAC_CMD) | FW_CMD_REQUEST |
3615 FW_CMD_WRITE | FW_VI_MAC_CMD_VIID(viid));
3616 c.freemacs_to_len16 = htonl(FW_CMD_LEN16(1));
3617 p->valid_to_idx = htons(FW_VI_MAC_CMD_VALID |
3618 FW_VI_MAC_CMD_SMAC_RESULT(mode) |
3619 FW_VI_MAC_CMD_IDX(idx));
3620 memcpy(p->macaddr, addr, sizeof(p->macaddr));
3622 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3624 ret = FW_VI_MAC_CMD_IDX_GET(ntohs(p->valid_to_idx));
3625 if (ret >= max_mac_addr)
3632 * t4_set_addr_hash - program the MAC inexact-match hash filter
3633 * @adap: the adapter
3634 * @mbox: mailbox to use for the FW command
3636 * @ucast: whether the hash filter should also match unicast addresses
3637 * @vec: the value to be written to the hash filter
3638 * @sleep_ok: call is allowed to sleep
3640 * Sets the 64-bit inexact-match hash filter for a virtual interface.
3642 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
3643 bool ucast, u64 vec, bool sleep_ok)
3645 struct fw_vi_mac_cmd c;
3647 memset(&c, 0, sizeof(c));
3648 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_MAC_CMD) | FW_CMD_REQUEST |
3649 FW_CMD_WRITE | FW_VI_ENABLE_CMD_VIID(viid));
3650 c.freemacs_to_len16 = htonl(FW_VI_MAC_CMD_HASHVECEN |
3651 FW_VI_MAC_CMD_HASHUNIEN(ucast) |
3653 c.u.hash.hashvec = cpu_to_be64(vec);
3654 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
3658 * t4_enable_vi_params - enable/disable a virtual interface
3659 * @adap: the adapter
3660 * @mbox: mailbox to use for the FW command
3662 * @rx_en: 1=enable Rx, 0=disable Rx
3663 * @tx_en: 1=enable Tx, 0=disable Tx
3664 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
3666 * Enables/disables a virtual interface. Note that setting DCB Enable
3667 * only makes sense when enabling a Virtual Interface ...
3669 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
3670 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
3672 struct fw_vi_enable_cmd c;
3674 memset(&c, 0, sizeof(c));
3675 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_ENABLE_CMD) | FW_CMD_REQUEST |
3676 FW_CMD_EXEC | FW_VI_ENABLE_CMD_VIID(viid));
3678 c.ien_to_len16 = htonl(FW_VI_ENABLE_CMD_IEN(rx_en) |
3679 FW_VI_ENABLE_CMD_EEN(tx_en) | FW_LEN16(c) |
3680 FW_VI_ENABLE_CMD_DCB_INFO(dcb_en));
3681 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
3685 * t4_enable_vi - enable/disable a virtual interface
3686 * @adap: the adapter
3687 * @mbox: mailbox to use for the FW command
3689 * @rx_en: 1=enable Rx, 0=disable Rx
3690 * @tx_en: 1=enable Tx, 0=disable Tx
3692 * Enables/disables a virtual interface.
3694 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
3695 bool rx_en, bool tx_en)
3697 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
3701 * t4_identify_port - identify a VI's port by blinking its LED
3702 * @adap: the adapter
3703 * @mbox: mailbox to use for the FW command
3705 * @nblinks: how many times to blink LED at 2.5 Hz
3707 * Identifies a VI's port by blinking its LED.
3709 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
3710 unsigned int nblinks)
3712 struct fw_vi_enable_cmd c;
3714 memset(&c, 0, sizeof(c));
3715 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_ENABLE_CMD) | FW_CMD_REQUEST |
3716 FW_CMD_EXEC | FW_VI_ENABLE_CMD_VIID(viid));
3717 c.ien_to_len16 = htonl(FW_VI_ENABLE_CMD_LED | FW_LEN16(c));
3718 c.blinkdur = htons(nblinks);
3719 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3723 * t4_iq_free - free an ingress queue and its FLs
3724 * @adap: the adapter
3725 * @mbox: mailbox to use for the FW command
3726 * @pf: the PF owning the queues
3727 * @vf: the VF owning the queues
3728 * @iqtype: the ingress queue type
3729 * @iqid: ingress queue id
3730 * @fl0id: FL0 queue id or 0xffff if no attached FL0
3731 * @fl1id: FL1 queue id or 0xffff if no attached FL1
3733 * Frees an ingress queue and its associated FLs, if any.
3735 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3736 unsigned int vf, unsigned int iqtype, unsigned int iqid,
3737 unsigned int fl0id, unsigned int fl1id)
3741 memset(&c, 0, sizeof(c));
3742 c.op_to_vfn = htonl(FW_CMD_OP(FW_IQ_CMD) | FW_CMD_REQUEST |
3743 FW_CMD_EXEC | FW_IQ_CMD_PFN(pf) |
3745 c.alloc_to_len16 = htonl(FW_IQ_CMD_FREE | FW_LEN16(c));
3746 c.type_to_iqandstindex = htonl(FW_IQ_CMD_TYPE(iqtype));
3747 c.iqid = htons(iqid);
3748 c.fl0id = htons(fl0id);
3749 c.fl1id = htons(fl1id);
3750 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3754 * t4_eth_eq_free - free an Ethernet egress queue
3755 * @adap: the adapter
3756 * @mbox: mailbox to use for the FW command
3757 * @pf: the PF owning the queue
3758 * @vf: the VF owning the queue
3759 * @eqid: egress queue id
3761 * Frees an Ethernet egress queue.
3763 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3764 unsigned int vf, unsigned int eqid)
3766 struct fw_eq_eth_cmd c;
3768 memset(&c, 0, sizeof(c));
3769 c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_ETH_CMD) | FW_CMD_REQUEST |
3770 FW_CMD_EXEC | FW_EQ_ETH_CMD_PFN(pf) |
3771 FW_EQ_ETH_CMD_VFN(vf));
3772 c.alloc_to_len16 = htonl(FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
3773 c.eqid_pkd = htonl(FW_EQ_ETH_CMD_EQID(eqid));
3774 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3778 * t4_ctrl_eq_free - free a control egress queue
3779 * @adap: the adapter
3780 * @mbox: mailbox to use for the FW command
3781 * @pf: the PF owning the queue
3782 * @vf: the VF owning the queue
3783 * @eqid: egress queue id
3785 * Frees a control egress queue.
3787 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3788 unsigned int vf, unsigned int eqid)
3790 struct fw_eq_ctrl_cmd c;
3792 memset(&c, 0, sizeof(c));
3793 c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_CTRL_CMD) | FW_CMD_REQUEST |
3794 FW_CMD_EXEC | FW_EQ_CTRL_CMD_PFN(pf) |
3795 FW_EQ_CTRL_CMD_VFN(vf));
3796 c.alloc_to_len16 = htonl(FW_EQ_CTRL_CMD_FREE | FW_LEN16(c));
3797 c.cmpliqid_eqid = htonl(FW_EQ_CTRL_CMD_EQID(eqid));
3798 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3802 * t4_ofld_eq_free - free an offload egress queue
3803 * @adap: the adapter
3804 * @mbox: mailbox to use for the FW command
3805 * @pf: the PF owning the queue
3806 * @vf: the VF owning the queue
3807 * @eqid: egress queue id
3809 * Frees a control egress queue.
3811 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3812 unsigned int vf, unsigned int eqid)
3814 struct fw_eq_ofld_cmd c;
3816 memset(&c, 0, sizeof(c));
3817 c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_OFLD_CMD) | FW_CMD_REQUEST |
3818 FW_CMD_EXEC | FW_EQ_OFLD_CMD_PFN(pf) |
3819 FW_EQ_OFLD_CMD_VFN(vf));
3820 c.alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_FREE | FW_LEN16(c));
3821 c.eqid_pkd = htonl(FW_EQ_OFLD_CMD_EQID(eqid));
3822 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3826 * t4_handle_fw_rpl - process a FW reply message
3827 * @adap: the adapter
3828 * @rpl: start of the FW message
3830 * Processes a FW message, such as link state change messages.
3832 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
3834 u8 opcode = *(const u8 *)rpl;
3836 if (opcode == FW_PORT_CMD) { /* link/module state change message */
3837 int speed = 0, fc = 0;
3838 const struct fw_port_cmd *p = (void *)rpl;
3839 int chan = FW_PORT_CMD_PORTID_GET(ntohl(p->op_to_portid));
3840 int port = adap->chan_map[chan];
3841 struct port_info *pi = adap2pinfo(adap, port);
3842 struct link_config *lc = &pi->link_cfg;
3843 u32 stat = ntohl(p->u.info.lstatus_to_modtype);
3844 int link_ok = (stat & FW_PORT_CMD_LSTATUS) != 0;
3845 u32 mod = FW_PORT_CMD_MODTYPE_GET(stat);
3847 if (stat & FW_PORT_CMD_RXPAUSE)
3849 if (stat & FW_PORT_CMD_TXPAUSE)
3851 if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
3853 else if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
3855 else if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
3857 else if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
3860 if (link_ok != lc->link_ok || speed != lc->speed ||
3861 fc != lc->fc) { /* something changed */
3862 lc->link_ok = link_ok;
3865 lc->supported = be16_to_cpu(p->u.info.pcap);
3866 t4_os_link_changed(adap, port, link_ok);
3868 if (mod != pi->mod_type) {
3870 t4_os_portmod_changed(adap, port);
3876 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
3880 if (pci_is_pcie(adapter->pdev)) {
3881 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
3882 p->speed = val & PCI_EXP_LNKSTA_CLS;
3883 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
3888 * init_link_config - initialize a link's SW state
3889 * @lc: structure holding the link state
3890 * @caps: link capabilities
3892 * Initializes the SW state maintained for each link, including the link's
3893 * capabilities and default speed/flow-control/autonegotiation settings.
3895 static void init_link_config(struct link_config *lc, unsigned int caps)
3897 lc->supported = caps;
3898 lc->requested_speed = 0;
3900 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
3901 if (lc->supported & FW_PORT_CAP_ANEG) {
3902 lc->advertising = lc->supported & ADVERT_MASK;
3903 lc->autoneg = AUTONEG_ENABLE;
3904 lc->requested_fc |= PAUSE_AUTONEG;
3906 lc->advertising = 0;
3907 lc->autoneg = AUTONEG_DISABLE;
3911 #define CIM_PF_NOACCESS 0xeeeeeeee
3913 int t4_wait_dev_ready(void __iomem *regs)
3917 whoami = readl(regs + PL_WHOAMI);
3918 if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
3922 whoami = readl(regs + PL_WHOAMI);
3923 return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
3927 u32 vendor_and_model_id;
3931 static int get_flash_params(struct adapter *adap)
3933 /* Table for non-Numonix supported flash parts. Numonix parts are left
3934 * to the preexisting code. All flash parts have 64KB sectors.
3936 static struct flash_desc supported_flash[] = {
3937 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
3943 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
3945 ret = sf1_read(adap, 3, 0, 1, &info);
3946 t4_write_reg(adap, SF_OP, 0); /* unlock SF */
3950 for (ret = 0; ret < ARRAY_SIZE(supported_flash); ++ret)
3951 if (supported_flash[ret].vendor_and_model_id == info) {
3952 adap->params.sf_size = supported_flash[ret].size_mb;
3953 adap->params.sf_nsec =
3954 adap->params.sf_size / SF_SEC_SIZE;
3958 if ((info & 0xff) != 0x20) /* not a Numonix flash */
3960 info >>= 16; /* log2 of size */
3961 if (info >= 0x14 && info < 0x18)
3962 adap->params.sf_nsec = 1 << (info - 16);
3963 else if (info == 0x18)
3964 adap->params.sf_nsec = 64;
3967 adap->params.sf_size = 1 << info;
3968 adap->params.sf_fw_start =
3969 t4_read_reg(adap, CIM_BOOT_CFG) & BOOTADDR_MASK;
3971 if (adap->params.sf_size < FLASH_MIN_SIZE)
3972 dev_warn(adap->pdev_dev, "WARNING!!! FLASH size %#x < %#x!!!\n",
3973 adap->params.sf_size, FLASH_MIN_SIZE);
3978 * t4_prep_adapter - prepare SW and HW for operation
3979 * @adapter: the adapter
3980 * @reset: if true perform a HW reset
3982 * Initialize adapter SW state for the various HW modules, set initial
3983 * values for some adapter tunables, take PHYs out of reset, and
3984 * initialize the MDIO interface.
3986 int t4_prep_adapter(struct adapter *adapter)
3992 get_pci_mode(adapter, &adapter->params.pci);
3993 pl_rev = G_REV(t4_read_reg(adapter, PL_REV));
3995 ret = get_flash_params(adapter);
3997 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
4001 /* Retrieve adapter's device ID
4003 pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
4004 ver = device_id >> 12;
4005 adapter->params.chip = 0;
4008 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
4011 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4014 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
4019 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
4022 * Default port for debugging in case we can't reach FW.
4024 adapter->params.nports = 1;
4025 adapter->params.portvec = 1;
4026 adapter->params.vpd.cclk = 50000;
4031 * t4_init_tp_params - initialize adap->params.tp
4032 * @adap: the adapter
4034 * Initialize various fields of the adapter's TP Parameters structure.
4036 int t4_init_tp_params(struct adapter *adap)
4041 v = t4_read_reg(adap, TP_TIMER_RESOLUTION);
4042 adap->params.tp.tre = TIMERRESOLUTION_GET(v);
4043 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_GET(v);
4045 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
4046 for (chan = 0; chan < NCHAN; chan++)
4047 adap->params.tp.tx_modq[chan] = chan;
4049 /* Cache the adapter's Compressed Filter Mode and global Incress
4052 t4_read_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
4053 &adap->params.tp.vlan_pri_map, 1,
4055 t4_read_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
4056 &adap->params.tp.ingress_config, 1,
4059 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
4060 * shift positions of several elements of the Compressed Filter Tuple
4061 * for this adapter which we need frequently ...
4063 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, F_VLAN);
4064 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
4065 adap->params.tp.port_shift = t4_filter_field_shift(adap, F_PORT);
4066 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
4069 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
4070 * represents the presense of an Outer VLAN instead of a VNIC ID.
4072 if ((adap->params.tp.ingress_config & F_VNIC) == 0)
4073 adap->params.tp.vnic_shift = -1;
4079 * t4_filter_field_shift - calculate filter field shift
4080 * @adap: the adapter
4081 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
4083 * Return the shift position of a filter field within the Compressed
4084 * Filter Tuple. The filter field is specified via its selection bit
4085 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
4087 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
4089 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
4093 if ((filter_mode & filter_sel) == 0)
4096 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
4097 switch (filter_mode & sel) {
4099 field_shift += W_FT_FCOE;
4102 field_shift += W_FT_PORT;
4105 field_shift += W_FT_VNIC_ID;
4108 field_shift += W_FT_VLAN;
4111 field_shift += W_FT_TOS;
4114 field_shift += W_FT_PROTOCOL;
4117 field_shift += W_FT_ETHERTYPE;
4120 field_shift += W_FT_MACMATCH;
4123 field_shift += W_FT_MPSHITTYPE;
4125 case F_FRAGMENTATION:
4126 field_shift += W_FT_FRAGMENTATION;
4133 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
4137 struct fw_port_cmd c;
4138 struct fw_rss_vi_config_cmd rvc;
4140 memset(&c, 0, sizeof(c));
4141 memset(&rvc, 0, sizeof(rvc));
4143 for_each_port(adap, i) {
4144 unsigned int rss_size;
4145 struct port_info *p = adap2pinfo(adap, i);
4147 while ((adap->params.portvec & (1 << j)) == 0)
4150 c.op_to_portid = htonl(FW_CMD_OP(FW_PORT_CMD) |
4151 FW_CMD_REQUEST | FW_CMD_READ |
4152 FW_PORT_CMD_PORTID(j));
4153 c.action_to_len16 = htonl(
4154 FW_PORT_CMD_ACTION(FW_PORT_ACTION_GET_PORT_INFO) |
4156 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
4160 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
4167 p->rss_size = rss_size;
4168 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
4169 adap->port[i]->dev_port = j;
4171 ret = ntohl(c.u.info.lstatus_to_modtype);
4172 p->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP) ?
4173 FW_PORT_CMD_MDIOADDR_GET(ret) : -1;
4174 p->port_type = FW_PORT_CMD_PTYPE_GET(ret);
4175 p->mod_type = FW_PORT_MOD_TYPE_NA;
4177 rvc.op_to_viid = htonl(FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
4178 FW_CMD_REQUEST | FW_CMD_READ |
4179 FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
4180 rvc.retval_len16 = htonl(FW_LEN16(rvc));
4181 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
4184 p->rss_mode = ntohl(rvc.u.basicvirtual.defaultq_to_udpen);
4186 init_link_config(&p->link_cfg, ntohs(c.u.info.pcap));