2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/delay.h>
40 static int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
41 const u8 *fw_data, unsigned int size, int force);
43 * t4_wait_op_done_val - wait until an operation is completed
44 * @adapter: the adapter performing the operation
45 * @reg: the register to check for completion
46 * @mask: a single-bit field within @reg that indicates completion
47 * @polarity: the value of the field when the operation is completed
48 * @attempts: number of check iterations
49 * @delay: delay in usecs between iterations
50 * @valp: where to store the value of the register at completion time
52 * Wait until an operation is completed by checking a bit in a register
53 * up to @attempts times. If @valp is not NULL the value of the register
54 * at the time it indicated completion is stored there. Returns 0 if the
55 * operation completes and -EAGAIN otherwise.
57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
58 int polarity, int attempts, int delay, u32 *valp)
61 u32 val = t4_read_reg(adapter, reg);
63 if (!!(val & mask) == polarity) {
75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
76 int polarity, int attempts, int delay)
78 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
83 * t4_set_reg_field - set a register field to a value
84 * @adapter: the adapter to program
85 * @addr: the register address
86 * @mask: specifies the portion of the register to modify
87 * @val: the new value for the register field
89 * Sets a register field specified by the supplied mask to the
92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
95 u32 v = t4_read_reg(adapter, addr) & ~mask;
97 t4_write_reg(adapter, addr, v | val);
98 (void) t4_read_reg(adapter, addr); /* flush */
102 * t4_read_indirect - read indirectly addressed registers
104 * @addr_reg: register holding the indirect address
105 * @data_reg: register holding the value of the indirect register
106 * @vals: where the read register values are stored
107 * @nregs: how many indirect registers to read
108 * @start_idx: index of first indirect register to read
110 * Reads registers that are accessed indirectly through an address/data
113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
114 unsigned int data_reg, u32 *vals,
115 unsigned int nregs, unsigned int start_idx)
118 t4_write_reg(adap, addr_reg, start_idx);
119 *vals++ = t4_read_reg(adap, data_reg);
125 * t4_write_indirect - write indirectly addressed registers
127 * @addr_reg: register holding the indirect addresses
128 * @data_reg: register holding the value for the indirect registers
129 * @vals: values to write
130 * @nregs: how many indirect registers to write
131 * @start_idx: address of first indirect register to write
133 * Writes a sequential block of registers that are accessed indirectly
134 * through an address/data register pair.
136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
137 unsigned int data_reg, const u32 *vals,
138 unsigned int nregs, unsigned int start_idx)
141 t4_write_reg(adap, addr_reg, start_idx++);
142 t4_write_reg(adap, data_reg, *vals++);
147 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
148 * mechanism. This guarantees that we get the real value even if we're
149 * operating within a Virtual Machine and the Hypervisor is trapping our
150 * Configuration Space accesses.
152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
154 u32 req = ENABLE | FUNCTION(adap->fn) | reg;
156 if (is_t4(adap->params.chip))
159 t4_write_reg(adap, PCIE_CFG_SPACE_REQ, req);
160 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA);
162 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
163 * Configuration Space read. (None of the other fields matter when
164 * ENABLE is 0 so a simple register write is easier than a
165 * read-modify-write via t4_set_reg_field().)
167 t4_write_reg(adap, PCIE_CFG_SPACE_REQ, 0);
171 * t4_report_fw_error - report firmware error
174 * The adapter firmware can indicate error conditions to the host.
175 * If the firmware has indicated an error, print out the reason for
176 * the firmware error.
178 static void t4_report_fw_error(struct adapter *adap)
180 static const char *const reason[] = {
181 "Crash", /* PCIE_FW_EVAL_CRASH */
182 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
183 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
184 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
185 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
186 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
187 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
188 "Reserved", /* reserved */
192 pcie_fw = t4_read_reg(adap, MA_PCIE_FW);
193 if (pcie_fw & FW_PCIE_FW_ERR)
194 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
195 reason[FW_PCIE_FW_EVAL_GET(pcie_fw)]);
199 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
201 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
204 for ( ; nflit; nflit--, mbox_addr += 8)
205 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
209 * Handle a FW assertion reported in a mailbox.
211 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
213 struct fw_debug_cmd asrt;
215 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
216 dev_alert(adap->pdev_dev,
217 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
218 asrt.u.assert.filename_0_7, ntohl(asrt.u.assert.line),
219 ntohl(asrt.u.assert.x), ntohl(asrt.u.assert.y));
222 static void dump_mbox(struct adapter *adap, int mbox, u32 data_reg)
224 dev_err(adap->pdev_dev,
225 "mbox %d: %llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
226 (unsigned long long)t4_read_reg64(adap, data_reg),
227 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
228 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
229 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
230 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
231 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
232 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
233 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
237 * t4_wr_mbox_meat - send a command to FW through the given mailbox
239 * @mbox: index of the mailbox to use
240 * @cmd: the command to write
241 * @size: command length in bytes
242 * @rpl: where to optionally store the reply
243 * @sleep_ok: if true we may sleep while awaiting command completion
245 * Sends the given command to FW through the selected mailbox and waits
246 * for the FW to execute the command. If @rpl is not %NULL it is used to
247 * store the FW's reply to the command. The command and its optional
248 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
249 * to respond. @sleep_ok determines whether we may sleep while awaiting
250 * the response. If sleeping is allowed we use progressive backoff
253 * The return value is 0 on success or a negative errno on failure. A
254 * failure can happen either because we are not able to execute the
255 * command or FW executes it but signals an error. In the latter case
256 * the return value is the error code indicated by FW (negated).
258 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
259 void *rpl, bool sleep_ok)
261 static const int delay[] = {
262 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
267 int i, ms, delay_idx;
268 const __be64 *p = cmd;
269 u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA);
270 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL);
272 if ((size & 15) || size > MBOX_LEN)
276 * If the device is off-line, as in EEH, commands will time out.
277 * Fail them early so we don't waste time waiting.
279 if (adap->pdev->error_state != pci_channel_io_normal)
282 v = MBOWNER_GET(t4_read_reg(adap, ctl_reg));
283 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
284 v = MBOWNER_GET(t4_read_reg(adap, ctl_reg));
286 if (v != MBOX_OWNER_DRV)
287 return v ? -EBUSY : -ETIMEDOUT;
289 for (i = 0; i < size; i += 8)
290 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
292 t4_write_reg(adap, ctl_reg, MBMSGVALID | MBOWNER(MBOX_OWNER_FW));
293 t4_read_reg(adap, ctl_reg); /* flush write */
298 for (i = 0; i < FW_CMD_MAX_TIMEOUT; i += ms) {
300 ms = delay[delay_idx]; /* last element may repeat */
301 if (delay_idx < ARRAY_SIZE(delay) - 1)
307 v = t4_read_reg(adap, ctl_reg);
308 if (MBOWNER_GET(v) == MBOX_OWNER_DRV) {
309 if (!(v & MBMSGVALID)) {
310 t4_write_reg(adap, ctl_reg, 0);
314 res = t4_read_reg64(adap, data_reg);
315 if (FW_CMD_OP_GET(res >> 32) == FW_DEBUG_CMD) {
316 fw_asrt(adap, data_reg);
317 res = FW_CMD_RETVAL(EIO);
319 get_mbox_rpl(adap, rpl, size / 8, data_reg);
321 if (FW_CMD_RETVAL_GET((int)res))
322 dump_mbox(adap, mbox, data_reg);
323 t4_write_reg(adap, ctl_reg, 0);
324 return -FW_CMD_RETVAL_GET((int)res);
328 dump_mbox(adap, mbox, data_reg);
329 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
330 *(const u8 *)cmd, mbox);
331 t4_report_fw_error(adap);
336 * t4_mc_read - read from MC through backdoor accesses
338 * @addr: address of first byte requested
339 * @idx: which MC to access
340 * @data: 64 bytes of data containing the requested address
341 * @ecc: where to store the corresponding 64-bit ECC word
343 * Read 64 bytes of data from MC starting at a 64-byte-aligned address
344 * that covers the requested address @addr. If @parity is not %NULL it
345 * is assigned the 64-bit ECC word for the read data.
347 int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
350 u32 mc_bist_cmd, mc_bist_cmd_addr, mc_bist_cmd_len;
351 u32 mc_bist_status_rdata, mc_bist_data_pattern;
353 if (is_t4(adap->params.chip)) {
354 mc_bist_cmd = MC_BIST_CMD;
355 mc_bist_cmd_addr = MC_BIST_CMD_ADDR;
356 mc_bist_cmd_len = MC_BIST_CMD_LEN;
357 mc_bist_status_rdata = MC_BIST_STATUS_RDATA;
358 mc_bist_data_pattern = MC_BIST_DATA_PATTERN;
360 mc_bist_cmd = MC_REG(MC_P_BIST_CMD, idx);
361 mc_bist_cmd_addr = MC_REG(MC_P_BIST_CMD_ADDR, idx);
362 mc_bist_cmd_len = MC_REG(MC_P_BIST_CMD_LEN, idx);
363 mc_bist_status_rdata = MC_REG(MC_P_BIST_STATUS_RDATA, idx);
364 mc_bist_data_pattern = MC_REG(MC_P_BIST_DATA_PATTERN, idx);
367 if (t4_read_reg(adap, mc_bist_cmd) & START_BIST)
369 t4_write_reg(adap, mc_bist_cmd_addr, addr & ~0x3fU);
370 t4_write_reg(adap, mc_bist_cmd_len, 64);
371 t4_write_reg(adap, mc_bist_data_pattern, 0xc);
372 t4_write_reg(adap, mc_bist_cmd, BIST_OPCODE(1) | START_BIST |
374 i = t4_wait_op_done(adap, mc_bist_cmd, START_BIST, 0, 10, 1);
378 #define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata, i)
380 for (i = 15; i >= 0; i--)
381 *data++ = htonl(t4_read_reg(adap, MC_DATA(i)));
383 *ecc = t4_read_reg64(adap, MC_DATA(16));
389 * t4_edc_read - read from EDC through backdoor accesses
391 * @idx: which EDC to access
392 * @addr: address of first byte requested
393 * @data: 64 bytes of data containing the requested address
394 * @ecc: where to store the corresponding 64-bit ECC word
396 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address
397 * that covers the requested address @addr. If @parity is not %NULL it
398 * is assigned the 64-bit ECC word for the read data.
400 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
403 u32 edc_bist_cmd, edc_bist_cmd_addr, edc_bist_cmd_len;
404 u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata;
406 if (is_t4(adap->params.chip)) {
407 edc_bist_cmd = EDC_REG(EDC_BIST_CMD, idx);
408 edc_bist_cmd_addr = EDC_REG(EDC_BIST_CMD_ADDR, idx);
409 edc_bist_cmd_len = EDC_REG(EDC_BIST_CMD_LEN, idx);
410 edc_bist_cmd_data_pattern = EDC_REG(EDC_BIST_DATA_PATTERN,
412 edc_bist_status_rdata = EDC_REG(EDC_BIST_STATUS_RDATA,
415 edc_bist_cmd = EDC_REG_T5(EDC_H_BIST_CMD, idx);
416 edc_bist_cmd_addr = EDC_REG_T5(EDC_H_BIST_CMD_ADDR, idx);
417 edc_bist_cmd_len = EDC_REG_T5(EDC_H_BIST_CMD_LEN, idx);
418 edc_bist_cmd_data_pattern =
419 EDC_REG_T5(EDC_H_BIST_DATA_PATTERN, idx);
420 edc_bist_status_rdata =
421 EDC_REG_T5(EDC_H_BIST_STATUS_RDATA, idx);
424 if (t4_read_reg(adap, edc_bist_cmd) & START_BIST)
426 t4_write_reg(adap, edc_bist_cmd_addr, addr & ~0x3fU);
427 t4_write_reg(adap, edc_bist_cmd_len, 64);
428 t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc);
429 t4_write_reg(adap, edc_bist_cmd,
430 BIST_OPCODE(1) | BIST_CMD_GAP(1) | START_BIST);
431 i = t4_wait_op_done(adap, edc_bist_cmd, START_BIST, 0, 10, 1);
435 #define EDC_DATA(i) (EDC_BIST_STATUS_REG(edc_bist_status_rdata, i))
437 for (i = 15; i >= 0; i--)
438 *data++ = htonl(t4_read_reg(adap, EDC_DATA(i)));
440 *ecc = t4_read_reg64(adap, EDC_DATA(16));
446 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
448 * @win: PCI-E Memory Window to use
449 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
450 * @addr: address within indicated memory type
451 * @len: amount of memory to transfer
452 * @buf: host memory buffer
453 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
455 * Reads/writes an [almost] arbitrary memory region in the firmware: the
456 * firmware memory address and host buffer must be aligned on 32-bit
457 * boudaries; the length may be arbitrary. The memory is transferred as
458 * a raw byte sequence from/to the firmware's memory. If this memory
459 * contains data structures which contain multi-byte integers, it's the
460 * caller's responsibility to perform appropriate byte order conversions.
462 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
463 u32 len, __be32 *buf, int dir)
465 u32 pos, offset, resid, memoffset;
466 u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
468 /* Argument sanity checks ...
473 /* It's convenient to be able to handle lengths which aren't a
474 * multiple of 32-bits because we often end up transferring files to
475 * the firmware. So we'll handle that by normalizing the length here
476 * and then handling any residual transfer at the end.
481 /* Offset into the region of memory which is being accessed
485 * MEM_MC0 = 2 -- For T5
486 * MEM_MC1 = 3 -- For T5
488 edc_size = EDRAM_SIZE_GET(t4_read_reg(adap, MA_EDRAM0_BAR));
489 if (mtype != MEM_MC1)
490 memoffset = (mtype * (edc_size * 1024 * 1024));
492 mc_size = EXT_MEM_SIZE_GET(t4_read_reg(adap,
494 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
497 /* Determine the PCIE_MEM_ACCESS_OFFSET */
498 addr = addr + memoffset;
500 /* Each PCI-E Memory Window is programmed with a window size -- or
501 * "aperture" -- which controls the granularity of its mapping onto
502 * adapter memory. We need to grab that aperture in order to know
503 * how to use the specified window. The window is also programmed
504 * with the base address of the Memory Window in BAR0's address
505 * space. For T4 this is an absolute PCI-E Bus Address. For T5
506 * the address is relative to BAR0.
508 mem_reg = t4_read_reg(adap,
509 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN,
511 mem_aperture = 1 << (GET_WINDOW(mem_reg) + 10);
512 mem_base = GET_PCIEOFST(mem_reg) << 10;
513 if (is_t4(adap->params.chip))
514 mem_base -= adap->t4_bar0;
515 win_pf = is_t4(adap->params.chip) ? 0 : V_PFNUM(adap->fn);
517 /* Calculate our initial PCI-E Memory Window Position and Offset into
520 pos = addr & ~(mem_aperture-1);
523 /* Set up initial PCI-E Memory Window to cover the start of our
524 * transfer. (Read it back to ensure that changes propagate before we
525 * attempt to use the new value.)
528 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win),
531 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win));
533 /* Transfer data to/from the adapter as long as there's an integral
534 * number of 32-bit transfers to complete.
537 if (dir == T4_MEMORY_READ)
538 *buf++ = (__force __be32) t4_read_reg(adap,
541 t4_write_reg(adap, mem_base + offset,
542 (__force u32) *buf++);
543 offset += sizeof(__be32);
544 len -= sizeof(__be32);
546 /* If we've reached the end of our current window aperture,
547 * move the PCI-E Memory Window on to the next. Note that
548 * doing this here after "len" may be 0 allows us to set up
549 * the PCI-E Memory Window for a possible final residual
552 if (offset == mem_aperture) {
556 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET,
559 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET,
564 /* If the original transfer had a length which wasn't a multiple of
565 * 32-bits, now's where we need to finish off the transfer of the
566 * residual amount. The PCI-E Memory Window has already been moved
567 * above (if necessary) to cover this final transfer.
577 if (dir == T4_MEMORY_READ) {
578 last.word = (__force __be32) t4_read_reg(adap,
580 for (bp = (unsigned char *)buf, i = resid; i < 4; i++)
581 bp[i] = last.byte[i];
584 for (i = resid; i < 4; i++)
586 t4_write_reg(adap, mem_base + offset,
587 (__force u32) last.word);
594 #define EEPROM_STAT_ADDR 0x7bfc
595 #define VPD_BASE 0x400
596 #define VPD_BASE_OLD 0
598 #define CHELSIO_VPD_UNIQUE_ID 0x82
601 * t4_seeprom_wp - enable/disable EEPROM write protection
602 * @adapter: the adapter
603 * @enable: whether to enable or disable write protection
605 * Enables or disables write protection on the serial EEPROM.
607 int t4_seeprom_wp(struct adapter *adapter, bool enable)
609 unsigned int v = enable ? 0xc : 0;
610 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
611 return ret < 0 ? ret : 0;
615 * get_vpd_params - read VPD parameters from VPD EEPROM
616 * @adapter: adapter to read
617 * @p: where to store the parameters
619 * Reads card parameters stored in VPD EEPROM.
621 int get_vpd_params(struct adapter *adapter, struct vpd_params *p)
623 u32 cclk_param, cclk_val;
627 unsigned int vpdr_len, kw_offset, id_len;
629 vpd = vmalloc(VPD_LEN);
633 ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
637 /* The VPD shall have a unique identifier specified by the PCI SIG.
638 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
639 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
640 * is expected to automatically put this entry at the
641 * beginning of the VPD.
643 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
645 ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
649 if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
650 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
655 id_len = pci_vpd_lrdt_size(vpd);
659 i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
661 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
666 vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
667 kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
668 if (vpdr_len + kw_offset > VPD_LEN) {
669 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
674 #define FIND_VPD_KW(var, name) do { \
675 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
677 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
681 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
684 FIND_VPD_KW(i, "RV");
685 for (csum = 0; i >= 0; i--)
689 dev_err(adapter->pdev_dev,
690 "corrupted VPD EEPROM, actual csum %u\n", csum);
695 FIND_VPD_KW(ec, "EC");
696 FIND_VPD_KW(sn, "SN");
697 FIND_VPD_KW(pn, "PN");
700 memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
702 memcpy(p->ec, vpd + ec, EC_LEN);
704 i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
705 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
707 i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
708 memcpy(p->pn, vpd + pn, min(i, PN_LEN));
712 * Ask firmware for the Core Clock since it knows how to translate the
713 * Reference Clock ('V2') VPD field into a Core Clock value ...
715 cclk_param = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
716 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK));
717 ret = t4_query_params(adapter, adapter->mbox, 0, 0,
718 1, &cclk_param, &cclk_val);
729 /* serial flash and firmware constants */
731 SF_ATTEMPTS = 10, /* max retries for SF operations */
733 /* flash command opcodes */
734 SF_PROG_PAGE = 2, /* program page */
735 SF_WR_DISABLE = 4, /* disable writes */
736 SF_RD_STATUS = 5, /* read status register */
737 SF_WR_ENABLE = 6, /* enable writes */
738 SF_RD_DATA_FAST = 0xb, /* read flash */
739 SF_RD_ID = 0x9f, /* read ID */
740 SF_ERASE_SECTOR = 0xd8, /* erase sector */
742 FW_MAX_SIZE = 16 * SF_SEC_SIZE,
746 * sf1_read - read data from the serial flash
747 * @adapter: the adapter
748 * @byte_cnt: number of bytes to read
749 * @cont: whether another operation will be chained
750 * @lock: whether to lock SF for PL access only
751 * @valp: where to store the read data
753 * Reads up to 4 bytes of data from the serial flash. The location of
754 * the read needs to be specified prior to calling this by issuing the
755 * appropriate commands to the serial flash.
757 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
762 if (!byte_cnt || byte_cnt > 4)
764 if (t4_read_reg(adapter, SF_OP) & SF_BUSY)
766 cont = cont ? SF_CONT : 0;
767 lock = lock ? SF_LOCK : 0;
768 t4_write_reg(adapter, SF_OP, lock | cont | BYTECNT(byte_cnt - 1));
769 ret = t4_wait_op_done(adapter, SF_OP, SF_BUSY, 0, SF_ATTEMPTS, 5);
771 *valp = t4_read_reg(adapter, SF_DATA);
776 * sf1_write - write data to the serial flash
777 * @adapter: the adapter
778 * @byte_cnt: number of bytes to write
779 * @cont: whether another operation will be chained
780 * @lock: whether to lock SF for PL access only
781 * @val: value to write
783 * Writes up to 4 bytes of data to the serial flash. The location of
784 * the write needs to be specified prior to calling this by issuing the
785 * appropriate commands to the serial flash.
787 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
790 if (!byte_cnt || byte_cnt > 4)
792 if (t4_read_reg(adapter, SF_OP) & SF_BUSY)
794 cont = cont ? SF_CONT : 0;
795 lock = lock ? SF_LOCK : 0;
796 t4_write_reg(adapter, SF_DATA, val);
797 t4_write_reg(adapter, SF_OP, lock |
798 cont | BYTECNT(byte_cnt - 1) | OP_WR);
799 return t4_wait_op_done(adapter, SF_OP, SF_BUSY, 0, SF_ATTEMPTS, 5);
803 * flash_wait_op - wait for a flash operation to complete
804 * @adapter: the adapter
805 * @attempts: max number of polls of the status register
806 * @delay: delay between polls in ms
808 * Wait for a flash operation to complete by polling the status register.
810 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
816 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
817 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
829 * t4_read_flash - read words from serial flash
830 * @adapter: the adapter
831 * @addr: the start address for the read
832 * @nwords: how many 32-bit words to read
833 * @data: where to store the read data
834 * @byte_oriented: whether to store data as bytes or as words
836 * Read the specified number of 32-bit words from the serial flash.
837 * If @byte_oriented is set the read data is stored as a byte array
838 * (i.e., big-endian), otherwise as 32-bit words in the platform's
841 static int t4_read_flash(struct adapter *adapter, unsigned int addr,
842 unsigned int nwords, u32 *data, int byte_oriented)
846 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
849 addr = swab32(addr) | SF_RD_DATA_FAST;
851 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
852 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
855 for ( ; nwords; nwords--, data++) {
856 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
858 t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
862 *data = (__force __u32) (htonl(*data));
868 * t4_write_flash - write up to a page of data to the serial flash
869 * @adapter: the adapter
870 * @addr: the start address to write
871 * @n: length of data to write in bytes
872 * @data: the data to write
874 * Writes up to a page of data (256 bytes) to the serial flash starting
875 * at the given address. All the data must be written to the same page.
877 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
878 unsigned int n, const u8 *data)
882 unsigned int i, c, left, val, offset = addr & 0xff;
884 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
887 val = swab32(addr) | SF_PROG_PAGE;
889 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
890 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
893 for (left = n; left; left -= c) {
895 for (val = 0, i = 0; i < c; ++i)
896 val = (val << 8) + *data++;
898 ret = sf1_write(adapter, c, c != left, 1, val);
902 ret = flash_wait_op(adapter, 8, 1);
906 t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
908 /* Read the page to verify the write succeeded */
909 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
913 if (memcmp(data - n, (u8 *)buf + offset, n)) {
914 dev_err(adapter->pdev_dev,
915 "failed to correctly write the flash page at %#x\n",
922 t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
927 * t4_get_fw_version - read the firmware version
928 * @adapter: the adapter
929 * @vers: where to place the version
931 * Reads the FW version from flash.
933 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
935 return t4_read_flash(adapter, FLASH_FW_START +
936 offsetof(struct fw_hdr, fw_ver), 1,
941 * t4_get_tp_version - read the TP microcode version
942 * @adapter: the adapter
943 * @vers: where to place the version
945 * Reads the TP microcode version from flash.
947 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
949 return t4_read_flash(adapter, FLASH_FW_START +
950 offsetof(struct fw_hdr, tp_microcode_ver),
954 /* Is the given firmware API compatible with the one the driver was compiled
957 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
960 /* short circuit if it's the exact same firmware version */
961 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
964 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
965 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
966 SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
973 /* The firmware in the filesystem is usable, but should it be installed?
974 * This routine explains itself in detail if it indicates the filesystem
975 * firmware should be installed.
977 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
982 if (!card_fw_usable) {
983 reason = "incompatible or unusable";
988 reason = "older than the version supported with this driver";
995 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
996 "installing firmware %u.%u.%u.%u on card.\n",
997 FW_HDR_FW_VER_MAJOR_GET(c), FW_HDR_FW_VER_MINOR_GET(c),
998 FW_HDR_FW_VER_MICRO_GET(c), FW_HDR_FW_VER_BUILD_GET(c), reason,
999 FW_HDR_FW_VER_MAJOR_GET(k), FW_HDR_FW_VER_MINOR_GET(k),
1000 FW_HDR_FW_VER_MICRO_GET(k), FW_HDR_FW_VER_BUILD_GET(k));
1005 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
1006 const u8 *fw_data, unsigned int fw_size,
1007 struct fw_hdr *card_fw, enum dev_state state,
1010 int ret, card_fw_usable, fs_fw_usable;
1011 const struct fw_hdr *fs_fw;
1012 const struct fw_hdr *drv_fw;
1014 drv_fw = &fw_info->fw_hdr;
1016 /* Read the header of the firmware on the card */
1017 ret = -t4_read_flash(adap, FLASH_FW_START,
1018 sizeof(*card_fw) / sizeof(uint32_t),
1019 (uint32_t *)card_fw, 1);
1021 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
1023 dev_err(adap->pdev_dev,
1024 "Unable to read card's firmware header: %d\n", ret);
1028 if (fw_data != NULL) {
1029 fs_fw = (const void *)fw_data;
1030 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
1036 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
1037 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
1038 /* Common case: the firmware on the card is an exact match and
1039 * the filesystem one is an exact match too, or the filesystem
1040 * one is absent/incompatible.
1042 } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
1043 should_install_fs_fw(adap, card_fw_usable,
1044 be32_to_cpu(fs_fw->fw_ver),
1045 be32_to_cpu(card_fw->fw_ver))) {
1046 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data,
1049 dev_err(adap->pdev_dev,
1050 "failed to install firmware: %d\n", ret);
1054 /* Installed successfully, update the cached header too. */
1055 memcpy(card_fw, fs_fw, sizeof(*card_fw));
1057 *reset = 0; /* already reset as part of load_fw */
1060 if (!card_fw_usable) {
1063 d = be32_to_cpu(drv_fw->fw_ver);
1064 c = be32_to_cpu(card_fw->fw_ver);
1065 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
1067 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
1069 "driver compiled with %d.%d.%d.%d, "
1070 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
1072 FW_HDR_FW_VER_MAJOR_GET(d), FW_HDR_FW_VER_MINOR_GET(d),
1073 FW_HDR_FW_VER_MICRO_GET(d), FW_HDR_FW_VER_BUILD_GET(d),
1074 FW_HDR_FW_VER_MAJOR_GET(c), FW_HDR_FW_VER_MINOR_GET(c),
1075 FW_HDR_FW_VER_MICRO_GET(c), FW_HDR_FW_VER_BUILD_GET(c),
1076 FW_HDR_FW_VER_MAJOR_GET(k), FW_HDR_FW_VER_MINOR_GET(k),
1077 FW_HDR_FW_VER_MICRO_GET(k), FW_HDR_FW_VER_BUILD_GET(k));
1082 /* We're using whatever's on the card and it's known to be good. */
1083 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
1084 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
1091 * t4_flash_erase_sectors - erase a range of flash sectors
1092 * @adapter: the adapter
1093 * @start: the first sector to erase
1094 * @end: the last sector to erase
1096 * Erases the sectors in the given inclusive range.
1098 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
1102 if (end >= adapter->params.sf_nsec)
1105 while (start <= end) {
1106 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
1107 (ret = sf1_write(adapter, 4, 0, 1,
1108 SF_ERASE_SECTOR | (start << 8))) != 0 ||
1109 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
1110 dev_err(adapter->pdev_dev,
1111 "erase of flash sector %d failed, error %d\n",
1117 t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
1122 * t4_flash_cfg_addr - return the address of the flash configuration file
1123 * @adapter: the adapter
1125 * Return the address within the flash where the Firmware Configuration
1128 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
1130 if (adapter->params.sf_size == 0x100000)
1131 return FLASH_FPGA_CFG_START;
1133 return FLASH_CFG_START;
1137 * t4_load_fw - download firmware
1138 * @adap: the adapter
1139 * @fw_data: the firmware image to write
1142 * Write the supplied firmware image to the card's serial flash.
1144 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
1149 u8 first_page[SF_PAGE_SIZE];
1150 const __be32 *p = (const __be32 *)fw_data;
1151 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
1152 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
1153 unsigned int fw_img_start = adap->params.sf_fw_start;
1154 unsigned int fw_start_sec = fw_img_start / sf_sec_size;
1157 dev_err(adap->pdev_dev, "FW image has no data\n");
1161 dev_err(adap->pdev_dev,
1162 "FW image size not multiple of 512 bytes\n");
1165 if (ntohs(hdr->len512) * 512 != size) {
1166 dev_err(adap->pdev_dev,
1167 "FW image size differs from size in FW header\n");
1170 if (size > FW_MAX_SIZE) {
1171 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
1176 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
1177 csum += ntohl(p[i]);
1179 if (csum != 0xffffffff) {
1180 dev_err(adap->pdev_dev,
1181 "corrupted firmware image, checksum %#x\n", csum);
1185 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
1186 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
1191 * We write the correct version at the end so the driver can see a bad
1192 * version if the FW write fails. Start by writing a copy of the
1193 * first page with a bad version.
1195 memcpy(first_page, fw_data, SF_PAGE_SIZE);
1196 ((struct fw_hdr *)first_page)->fw_ver = htonl(0xffffffff);
1197 ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page);
1201 addr = fw_img_start;
1202 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
1203 addr += SF_PAGE_SIZE;
1204 fw_data += SF_PAGE_SIZE;
1205 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
1210 ret = t4_write_flash(adap,
1211 fw_img_start + offsetof(struct fw_hdr, fw_ver),
1212 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
1215 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
1220 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
1221 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \
1225 * t4_link_start - apply link configuration to MAC/PHY
1226 * @phy: the PHY to setup
1227 * @mac: the MAC to setup
1228 * @lc: the requested link configuration
1230 * Set up a port's MAC and PHY according to a desired link configuration.
1231 * - If the PHY can auto-negotiate first decide what to advertise, then
1232 * enable/disable auto-negotiation as desired, and reset.
1233 * - If the PHY does not auto-negotiate just reset it.
1234 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
1235 * otherwise do it later based on the outcome of auto-negotiation.
1237 int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
1238 struct link_config *lc)
1240 struct fw_port_cmd c;
1241 unsigned int fc = 0, mdi = FW_PORT_MDI(FW_PORT_MDI_AUTO);
1244 if (lc->requested_fc & PAUSE_RX)
1245 fc |= FW_PORT_CAP_FC_RX;
1246 if (lc->requested_fc & PAUSE_TX)
1247 fc |= FW_PORT_CAP_FC_TX;
1249 memset(&c, 0, sizeof(c));
1250 c.op_to_portid = htonl(FW_CMD_OP(FW_PORT_CMD) | FW_CMD_REQUEST |
1251 FW_CMD_EXEC | FW_PORT_CMD_PORTID(port));
1252 c.action_to_len16 = htonl(FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
1255 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
1256 c.u.l1cfg.rcap = htonl((lc->supported & ADVERT_MASK) | fc);
1257 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1258 } else if (lc->autoneg == AUTONEG_DISABLE) {
1259 c.u.l1cfg.rcap = htonl(lc->requested_speed | fc | mdi);
1260 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1262 c.u.l1cfg.rcap = htonl(lc->advertising | fc | mdi);
1264 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
1268 * t4_restart_aneg - restart autonegotiation
1269 * @adap: the adapter
1270 * @mbox: mbox to use for the FW command
1271 * @port: the port id
1273 * Restarts autonegotiation for the selected port.
1275 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
1277 struct fw_port_cmd c;
1279 memset(&c, 0, sizeof(c));
1280 c.op_to_portid = htonl(FW_CMD_OP(FW_PORT_CMD) | FW_CMD_REQUEST |
1281 FW_CMD_EXEC | FW_PORT_CMD_PORTID(port));
1282 c.action_to_len16 = htonl(FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
1284 c.u.l1cfg.rcap = htonl(FW_PORT_CAP_ANEG);
1285 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
1288 typedef void (*int_handler_t)(struct adapter *adap);
1291 unsigned int mask; /* bits to check in interrupt status */
1292 const char *msg; /* message to print or NULL */
1293 short stat_idx; /* stat counter to increment or -1 */
1294 unsigned short fatal; /* whether the condition reported is fatal */
1295 int_handler_t int_handler; /* platform-specific int handler */
1299 * t4_handle_intr_status - table driven interrupt handler
1300 * @adapter: the adapter that generated the interrupt
1301 * @reg: the interrupt status register to process
1302 * @acts: table of interrupt actions
1304 * A table driven interrupt handler that applies a set of masks to an
1305 * interrupt status word and performs the corresponding actions if the
1306 * interrupts described by the mask have occurred. The actions include
1307 * optionally emitting a warning or alert message. The table is terminated
1308 * by an entry specifying mask 0. Returns the number of fatal interrupt
1311 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
1312 const struct intr_info *acts)
1315 unsigned int mask = 0;
1316 unsigned int status = t4_read_reg(adapter, reg);
1318 for ( ; acts->mask; ++acts) {
1319 if (!(status & acts->mask))
1323 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
1324 status & acts->mask);
1325 } else if (acts->msg && printk_ratelimit())
1326 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
1327 status & acts->mask);
1328 if (acts->int_handler)
1329 acts->int_handler(adapter);
1333 if (status) /* clear processed interrupts */
1334 t4_write_reg(adapter, reg, status);
1339 * Interrupt handler for the PCIE module.
1341 static void pcie_intr_handler(struct adapter *adapter)
1343 static const struct intr_info sysbus_intr_info[] = {
1344 { RNPP, "RXNP array parity error", -1, 1 },
1345 { RPCP, "RXPC array parity error", -1, 1 },
1346 { RCIP, "RXCIF array parity error", -1, 1 },
1347 { RCCP, "Rx completions control array parity error", -1, 1 },
1348 { RFTP, "RXFT array parity error", -1, 1 },
1351 static const struct intr_info pcie_port_intr_info[] = {
1352 { TPCP, "TXPC array parity error", -1, 1 },
1353 { TNPP, "TXNP array parity error", -1, 1 },
1354 { TFTP, "TXFT array parity error", -1, 1 },
1355 { TCAP, "TXCA array parity error", -1, 1 },
1356 { TCIP, "TXCIF array parity error", -1, 1 },
1357 { RCAP, "RXCA array parity error", -1, 1 },
1358 { OTDD, "outbound request TLP discarded", -1, 1 },
1359 { RDPE, "Rx data parity error", -1, 1 },
1360 { TDUE, "Tx uncorrectable data error", -1, 1 },
1363 static const struct intr_info pcie_intr_info[] = {
1364 { MSIADDRLPERR, "MSI AddrL parity error", -1, 1 },
1365 { MSIADDRHPERR, "MSI AddrH parity error", -1, 1 },
1366 { MSIDATAPERR, "MSI data parity error", -1, 1 },
1367 { MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
1368 { MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
1369 { MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
1370 { MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
1371 { PIOCPLPERR, "PCI PIO completion FIFO parity error", -1, 1 },
1372 { PIOREQPERR, "PCI PIO request FIFO parity error", -1, 1 },
1373 { TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
1374 { CCNTPERR, "PCI CMD channel count parity error", -1, 1 },
1375 { CREQPERR, "PCI CMD channel request parity error", -1, 1 },
1376 { CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
1377 { DCNTPERR, "PCI DMA channel count parity error", -1, 1 },
1378 { DREQPERR, "PCI DMA channel request parity error", -1, 1 },
1379 { DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
1380 { HCNTPERR, "PCI HMA channel count parity error", -1, 1 },
1381 { HREQPERR, "PCI HMA channel request parity error", -1, 1 },
1382 { HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
1383 { CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
1384 { FIDPERR, "PCI FID parity error", -1, 1 },
1385 { INTXCLRPERR, "PCI INTx clear parity error", -1, 1 },
1386 { MATAGPERR, "PCI MA tag parity error", -1, 1 },
1387 { PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
1388 { RXCPLPERR, "PCI Rx completion parity error", -1, 1 },
1389 { RXWRPERR, "PCI Rx write parity error", -1, 1 },
1390 { RPLPERR, "PCI replay buffer parity error", -1, 1 },
1391 { PCIESINT, "PCI core secondary fault", -1, 1 },
1392 { PCIEPINT, "PCI core primary fault", -1, 1 },
1393 { UNXSPLCPLERR, "PCI unexpected split completion error", -1, 0 },
1397 static struct intr_info t5_pcie_intr_info[] = {
1398 { MSTGRPPERR, "Master Response Read Queue parity error",
1400 { MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 },
1401 { MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 },
1402 { MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
1403 { MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
1404 { MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
1405 { MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
1406 { PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error",
1408 { PIOREQGRPPERR, "PCI PIO request Group FIFO parity error",
1410 { TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
1411 { MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 },
1412 { CREQPERR, "PCI CMD channel request parity error", -1, 1 },
1413 { CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
1414 { DREQWRPERR, "PCI DMA channel write request parity error",
1416 { DREQPERR, "PCI DMA channel request parity error", -1, 1 },
1417 { DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
1418 { HREQWRPERR, "PCI HMA channel count parity error", -1, 1 },
1419 { HREQPERR, "PCI HMA channel request parity error", -1, 1 },
1420 { HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
1421 { CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
1422 { FIDPERR, "PCI FID parity error", -1, 1 },
1423 { VFIDPERR, "PCI INTx clear parity error", -1, 1 },
1424 { MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 },
1425 { PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
1426 { IPRXHDRGRPPERR, "PCI IP Rx header group parity error",
1428 { IPRXDATAGRPPERR, "PCI IP Rx data group parity error", -1, 1 },
1429 { RPLPERR, "PCI IP replay buffer parity error", -1, 1 },
1430 { IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 },
1431 { TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 },
1432 { READRSPERR, "Outbound read error", -1, 0 },
1438 if (is_t4(adapter->params.chip))
1439 fat = t4_handle_intr_status(adapter,
1440 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
1442 t4_handle_intr_status(adapter,
1443 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
1444 pcie_port_intr_info) +
1445 t4_handle_intr_status(adapter, PCIE_INT_CAUSE,
1448 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE,
1452 t4_fatal_err(adapter);
1456 * TP interrupt handler.
1458 static void tp_intr_handler(struct adapter *adapter)
1460 static const struct intr_info tp_intr_info[] = {
1461 { 0x3fffffff, "TP parity error", -1, 1 },
1462 { FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 },
1466 if (t4_handle_intr_status(adapter, TP_INT_CAUSE, tp_intr_info))
1467 t4_fatal_err(adapter);
1471 * SGE interrupt handler.
1473 static void sge_intr_handler(struct adapter *adapter)
1477 static const struct intr_info sge_intr_info[] = {
1478 { ERR_CPL_EXCEED_IQE_SIZE,
1479 "SGE received CPL exceeding IQE size", -1, 1 },
1480 { ERR_INVALID_CIDX_INC,
1481 "SGE GTS CIDX increment too large", -1, 0 },
1482 { ERR_CPL_OPCODE_0, "SGE received 0-length CPL", -1, 0 },
1483 { DBFIFO_LP_INT, NULL, -1, 0, t4_db_full },
1484 { DBFIFO_HP_INT, NULL, -1, 0, t4_db_full },
1485 { ERR_DROPPED_DB, NULL, -1, 0, t4_db_dropped },
1486 { ERR_DATA_CPL_ON_HIGH_QID1 | ERR_DATA_CPL_ON_HIGH_QID0,
1487 "SGE IQID > 1023 received CPL for FL", -1, 0 },
1488 { ERR_BAD_DB_PIDX3, "SGE DBP 3 pidx increment too large", -1,
1490 { ERR_BAD_DB_PIDX2, "SGE DBP 2 pidx increment too large", -1,
1492 { ERR_BAD_DB_PIDX1, "SGE DBP 1 pidx increment too large", -1,
1494 { ERR_BAD_DB_PIDX0, "SGE DBP 0 pidx increment too large", -1,
1496 { ERR_ING_CTXT_PRIO,
1497 "SGE too many priority ingress contexts", -1, 0 },
1498 { ERR_EGR_CTXT_PRIO,
1499 "SGE too many priority egress contexts", -1, 0 },
1500 { INGRESS_SIZE_ERR, "SGE illegal ingress QID", -1, 0 },
1501 { EGRESS_SIZE_ERR, "SGE illegal egress QID", -1, 0 },
1505 v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1) |
1506 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2) << 32);
1508 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
1509 (unsigned long long)v);
1510 t4_write_reg(adapter, SGE_INT_CAUSE1, v);
1511 t4_write_reg(adapter, SGE_INT_CAUSE2, v >> 32);
1514 if (t4_handle_intr_status(adapter, SGE_INT_CAUSE3, sge_intr_info) ||
1516 t4_fatal_err(adapter);
1520 * CIM interrupt handler.
1522 static void cim_intr_handler(struct adapter *adapter)
1524 static const struct intr_info cim_intr_info[] = {
1525 { PREFDROPINT, "CIM control register prefetch drop", -1, 1 },
1526 { OBQPARERR, "CIM OBQ parity error", -1, 1 },
1527 { IBQPARERR, "CIM IBQ parity error", -1, 1 },
1528 { MBUPPARERR, "CIM mailbox uP parity error", -1, 1 },
1529 { MBHOSTPARERR, "CIM mailbox host parity error", -1, 1 },
1530 { TIEQINPARERRINT, "CIM TIEQ outgoing parity error", -1, 1 },
1531 { TIEQOUTPARERRINT, "CIM TIEQ incoming parity error", -1, 1 },
1534 static const struct intr_info cim_upintr_info[] = {
1535 { RSVDSPACEINT, "CIM reserved space access", -1, 1 },
1536 { ILLTRANSINT, "CIM illegal transaction", -1, 1 },
1537 { ILLWRINT, "CIM illegal write", -1, 1 },
1538 { ILLRDINT, "CIM illegal read", -1, 1 },
1539 { ILLRDBEINT, "CIM illegal read BE", -1, 1 },
1540 { ILLWRBEINT, "CIM illegal write BE", -1, 1 },
1541 { SGLRDBOOTINT, "CIM single read from boot space", -1, 1 },
1542 { SGLWRBOOTINT, "CIM single write to boot space", -1, 1 },
1543 { BLKWRBOOTINT, "CIM block write to boot space", -1, 1 },
1544 { SGLRDFLASHINT, "CIM single read from flash space", -1, 1 },
1545 { SGLWRFLASHINT, "CIM single write to flash space", -1, 1 },
1546 { BLKWRFLASHINT, "CIM block write to flash space", -1, 1 },
1547 { SGLRDEEPROMINT, "CIM single EEPROM read", -1, 1 },
1548 { SGLWREEPROMINT, "CIM single EEPROM write", -1, 1 },
1549 { BLKRDEEPROMINT, "CIM block EEPROM read", -1, 1 },
1550 { BLKWREEPROMINT, "CIM block EEPROM write", -1, 1 },
1551 { SGLRDCTLINT , "CIM single read from CTL space", -1, 1 },
1552 { SGLWRCTLINT , "CIM single write to CTL space", -1, 1 },
1553 { BLKRDCTLINT , "CIM block read from CTL space", -1, 1 },
1554 { BLKWRCTLINT , "CIM block write to CTL space", -1, 1 },
1555 { SGLRDPLINT , "CIM single read from PL space", -1, 1 },
1556 { SGLWRPLINT , "CIM single write to PL space", -1, 1 },
1557 { BLKRDPLINT , "CIM block read from PL space", -1, 1 },
1558 { BLKWRPLINT , "CIM block write to PL space", -1, 1 },
1559 { REQOVRLOOKUPINT , "CIM request FIFO overwrite", -1, 1 },
1560 { RSPOVRLOOKUPINT , "CIM response FIFO overwrite", -1, 1 },
1561 { TIMEOUTINT , "CIM PIF timeout", -1, 1 },
1562 { TIMEOUTMAINT , "CIM PIF MA timeout", -1, 1 },
1568 if (t4_read_reg(adapter, MA_PCIE_FW) & FW_PCIE_FW_ERR)
1569 t4_report_fw_error(adapter);
1571 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE,
1573 t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE,
1576 t4_fatal_err(adapter);
1580 * ULP RX interrupt handler.
1582 static void ulprx_intr_handler(struct adapter *adapter)
1584 static const struct intr_info ulprx_intr_info[] = {
1585 { 0x1800000, "ULPRX context error", -1, 1 },
1586 { 0x7fffff, "ULPRX parity error", -1, 1 },
1590 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE, ulprx_intr_info))
1591 t4_fatal_err(adapter);
1595 * ULP TX interrupt handler.
1597 static void ulptx_intr_handler(struct adapter *adapter)
1599 static const struct intr_info ulptx_intr_info[] = {
1600 { PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds", -1,
1602 { PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds", -1,
1604 { PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds", -1,
1606 { PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds", -1,
1608 { 0xfffffff, "ULPTX parity error", -1, 1 },
1612 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE, ulptx_intr_info))
1613 t4_fatal_err(adapter);
1617 * PM TX interrupt handler.
1619 static void pmtx_intr_handler(struct adapter *adapter)
1621 static const struct intr_info pmtx_intr_info[] = {
1622 { PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large", -1, 1 },
1623 { PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large", -1, 1 },
1624 { PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large", -1, 1 },
1625 { ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1 },
1626 { PMTX_FRAMING_ERROR, "PMTX framing error", -1, 1 },
1627 { OESPI_PAR_ERROR, "PMTX oespi parity error", -1, 1 },
1628 { DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error", -1, 1 },
1629 { ICSPI_PAR_ERROR, "PMTX icspi parity error", -1, 1 },
1630 { C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error", -1, 1},
1634 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE, pmtx_intr_info))
1635 t4_fatal_err(adapter);
1639 * PM RX interrupt handler.
1641 static void pmrx_intr_handler(struct adapter *adapter)
1643 static const struct intr_info pmrx_intr_info[] = {
1644 { ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 },
1645 { PMRX_FRAMING_ERROR, "PMRX framing error", -1, 1 },
1646 { OCSPI_PAR_ERROR, "PMRX ocspi parity error", -1, 1 },
1647 { DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error", -1, 1 },
1648 { IESPI_PAR_ERROR, "PMRX iespi parity error", -1, 1 },
1649 { E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error", -1, 1},
1653 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE, pmrx_intr_info))
1654 t4_fatal_err(adapter);
1658 * CPL switch interrupt handler.
1660 static void cplsw_intr_handler(struct adapter *adapter)
1662 static const struct intr_info cplsw_intr_info[] = {
1663 { CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error", -1, 1 },
1664 { CIM_OVFL_ERROR, "CPLSW CIM overflow", -1, 1 },
1665 { TP_FRAMING_ERROR, "CPLSW TP framing error", -1, 1 },
1666 { SGE_FRAMING_ERROR, "CPLSW SGE framing error", -1, 1 },
1667 { CIM_FRAMING_ERROR, "CPLSW CIM framing error", -1, 1 },
1668 { ZERO_SWITCH_ERROR, "CPLSW no-switch error", -1, 1 },
1672 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE, cplsw_intr_info))
1673 t4_fatal_err(adapter);
1677 * LE interrupt handler.
1679 static void le_intr_handler(struct adapter *adap)
1681 static const struct intr_info le_intr_info[] = {
1682 { LIPMISS, "LE LIP miss", -1, 0 },
1683 { LIP0, "LE 0 LIP error", -1, 0 },
1684 { PARITYERR, "LE parity error", -1, 1 },
1685 { UNKNOWNCMD, "LE unknown command", -1, 1 },
1686 { REQQPARERR, "LE request queue parity error", -1, 1 },
1690 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE, le_intr_info))
1695 * MPS interrupt handler.
1697 static void mps_intr_handler(struct adapter *adapter)
1699 static const struct intr_info mps_rx_intr_info[] = {
1700 { 0xffffff, "MPS Rx parity error", -1, 1 },
1703 static const struct intr_info mps_tx_intr_info[] = {
1704 { TPFIFO, "MPS Tx TP FIFO parity error", -1, 1 },
1705 { NCSIFIFO, "MPS Tx NC-SI FIFO parity error", -1, 1 },
1706 { TXDATAFIFO, "MPS Tx data FIFO parity error", -1, 1 },
1707 { TXDESCFIFO, "MPS Tx desc FIFO parity error", -1, 1 },
1708 { BUBBLE, "MPS Tx underflow", -1, 1 },
1709 { SECNTERR, "MPS Tx SOP/EOP error", -1, 1 },
1710 { FRMERR, "MPS Tx framing error", -1, 1 },
1713 static const struct intr_info mps_trc_intr_info[] = {
1714 { FILTMEM, "MPS TRC filter parity error", -1, 1 },
1715 { PKTFIFO, "MPS TRC packet FIFO parity error", -1, 1 },
1716 { MISCPERR, "MPS TRC misc parity error", -1, 1 },
1719 static const struct intr_info mps_stat_sram_intr_info[] = {
1720 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
1723 static const struct intr_info mps_stat_tx_intr_info[] = {
1724 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
1727 static const struct intr_info mps_stat_rx_intr_info[] = {
1728 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
1731 static const struct intr_info mps_cls_intr_info[] = {
1732 { MATCHSRAM, "MPS match SRAM parity error", -1, 1 },
1733 { MATCHTCAM, "MPS match TCAM parity error", -1, 1 },
1734 { HASHSRAM, "MPS hash SRAM parity error", -1, 1 },
1740 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE,
1742 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE,
1744 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE,
1745 mps_trc_intr_info) +
1746 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM,
1747 mps_stat_sram_intr_info) +
1748 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO,
1749 mps_stat_tx_intr_info) +
1750 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO,
1751 mps_stat_rx_intr_info) +
1752 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE,
1755 t4_write_reg(adapter, MPS_INT_CAUSE, CLSINT | TRCINT |
1756 RXINT | TXINT | STATINT);
1757 t4_read_reg(adapter, MPS_INT_CAUSE); /* flush */
1759 t4_fatal_err(adapter);
1762 #define MEM_INT_MASK (PERR_INT_CAUSE | ECC_CE_INT_CAUSE | ECC_UE_INT_CAUSE)
1765 * EDC/MC interrupt handler.
1767 static void mem_intr_handler(struct adapter *adapter, int idx)
1769 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
1771 unsigned int addr, cnt_addr, v;
1773 if (idx <= MEM_EDC1) {
1774 addr = EDC_REG(EDC_INT_CAUSE, idx);
1775 cnt_addr = EDC_REG(EDC_ECC_STATUS, idx);
1776 } else if (idx == MEM_MC) {
1777 if (is_t4(adapter->params.chip)) {
1778 addr = MC_INT_CAUSE;
1779 cnt_addr = MC_ECC_STATUS;
1781 addr = MC_P_INT_CAUSE;
1782 cnt_addr = MC_P_ECC_STATUS;
1785 addr = MC_REG(MC_P_INT_CAUSE, 1);
1786 cnt_addr = MC_REG(MC_P_ECC_STATUS, 1);
1789 v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
1790 if (v & PERR_INT_CAUSE)
1791 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
1793 if (v & ECC_CE_INT_CAUSE) {
1794 u32 cnt = ECC_CECNT_GET(t4_read_reg(adapter, cnt_addr));
1796 t4_write_reg(adapter, cnt_addr, ECC_CECNT_MASK);
1797 if (printk_ratelimit())
1798 dev_warn(adapter->pdev_dev,
1799 "%u %s correctable ECC data error%s\n",
1800 cnt, name[idx], cnt > 1 ? "s" : "");
1802 if (v & ECC_UE_INT_CAUSE)
1803 dev_alert(adapter->pdev_dev,
1804 "%s uncorrectable ECC data error\n", name[idx]);
1806 t4_write_reg(adapter, addr, v);
1807 if (v & (PERR_INT_CAUSE | ECC_UE_INT_CAUSE))
1808 t4_fatal_err(adapter);
1812 * MA interrupt handler.
1814 static void ma_intr_handler(struct adapter *adap)
1816 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE);
1818 if (status & MEM_PERR_INT_CAUSE) {
1819 dev_alert(adap->pdev_dev,
1820 "MA parity error, parity status %#x\n",
1821 t4_read_reg(adap, MA_PARITY_ERROR_STATUS));
1822 if (is_t5(adap->params.chip))
1823 dev_alert(adap->pdev_dev,
1824 "MA parity error, parity status %#x\n",
1826 MA_PARITY_ERROR_STATUS2));
1828 if (status & MEM_WRAP_INT_CAUSE) {
1829 v = t4_read_reg(adap, MA_INT_WRAP_STATUS);
1830 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
1831 "client %u to address %#x\n",
1832 MEM_WRAP_CLIENT_NUM_GET(v),
1833 MEM_WRAP_ADDRESS_GET(v) << 4);
1835 t4_write_reg(adap, MA_INT_CAUSE, status);
1840 * SMB interrupt handler.
1842 static void smb_intr_handler(struct adapter *adap)
1844 static const struct intr_info smb_intr_info[] = {
1845 { MSTTXFIFOPARINT, "SMB master Tx FIFO parity error", -1, 1 },
1846 { MSTRXFIFOPARINT, "SMB master Rx FIFO parity error", -1, 1 },
1847 { SLVFIFOPARINT, "SMB slave FIFO parity error", -1, 1 },
1851 if (t4_handle_intr_status(adap, SMB_INT_CAUSE, smb_intr_info))
1856 * NC-SI interrupt handler.
1858 static void ncsi_intr_handler(struct adapter *adap)
1860 static const struct intr_info ncsi_intr_info[] = {
1861 { CIM_DM_PRTY_ERR, "NC-SI CIM parity error", -1, 1 },
1862 { MPS_DM_PRTY_ERR, "NC-SI MPS parity error", -1, 1 },
1863 { TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error", -1, 1 },
1864 { RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error", -1, 1 },
1868 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE, ncsi_intr_info))
1873 * XGMAC interrupt handler.
1875 static void xgmac_intr_handler(struct adapter *adap, int port)
1877 u32 v, int_cause_reg;
1879 if (is_t4(adap->params.chip))
1880 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE);
1882 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE);
1884 v = t4_read_reg(adap, int_cause_reg);
1886 v &= TXFIFO_PRTY_ERR | RXFIFO_PRTY_ERR;
1890 if (v & TXFIFO_PRTY_ERR)
1891 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
1893 if (v & RXFIFO_PRTY_ERR)
1894 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
1896 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE), v);
1901 * PL interrupt handler.
1903 static void pl_intr_handler(struct adapter *adap)
1905 static const struct intr_info pl_intr_info[] = {
1906 { FATALPERR, "T4 fatal parity error", -1, 1 },
1907 { PERRVFID, "PL VFID_MAP parity error", -1, 1 },
1911 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE, pl_intr_info))
1915 #define PF_INTR_MASK (PFSW)
1916 #define GLBL_INTR_MASK (CIM | MPS | PL | PCIE | MC | EDC0 | \
1917 EDC1 | LE | TP | MA | PM_TX | PM_RX | ULP_RX | \
1918 CPL_SWITCH | SGE | ULP_TX)
1921 * t4_slow_intr_handler - control path interrupt handler
1922 * @adapter: the adapter
1924 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
1925 * The designation 'slow' is because it involves register reads, while
1926 * data interrupts typically don't involve any MMIOs.
1928 int t4_slow_intr_handler(struct adapter *adapter)
1930 u32 cause = t4_read_reg(adapter, PL_INT_CAUSE);
1932 if (!(cause & GLBL_INTR_MASK))
1935 cim_intr_handler(adapter);
1937 mps_intr_handler(adapter);
1939 ncsi_intr_handler(adapter);
1941 pl_intr_handler(adapter);
1943 smb_intr_handler(adapter);
1945 xgmac_intr_handler(adapter, 0);
1947 xgmac_intr_handler(adapter, 1);
1948 if (cause & XGMAC_KR0)
1949 xgmac_intr_handler(adapter, 2);
1950 if (cause & XGMAC_KR1)
1951 xgmac_intr_handler(adapter, 3);
1953 pcie_intr_handler(adapter);
1955 mem_intr_handler(adapter, MEM_MC);
1956 if (!is_t4(adapter->params.chip) && (cause & MC1))
1957 mem_intr_handler(adapter, MEM_MC1);
1959 mem_intr_handler(adapter, MEM_EDC0);
1961 mem_intr_handler(adapter, MEM_EDC1);
1963 le_intr_handler(adapter);
1965 tp_intr_handler(adapter);
1967 ma_intr_handler(adapter);
1969 pmtx_intr_handler(adapter);
1971 pmrx_intr_handler(adapter);
1973 ulprx_intr_handler(adapter);
1974 if (cause & CPL_SWITCH)
1975 cplsw_intr_handler(adapter);
1977 sge_intr_handler(adapter);
1979 ulptx_intr_handler(adapter);
1981 /* Clear the interrupts just processed for which we are the master. */
1982 t4_write_reg(adapter, PL_INT_CAUSE, cause & GLBL_INTR_MASK);
1983 (void) t4_read_reg(adapter, PL_INT_CAUSE); /* flush */
1988 * t4_intr_enable - enable interrupts
1989 * @adapter: the adapter whose interrupts should be enabled
1991 * Enable PF-specific interrupts for the calling function and the top-level
1992 * interrupt concentrator for global interrupts. Interrupts are already
1993 * enabled at each module, here we just enable the roots of the interrupt
1996 * Note: this function should be called only when the driver manages
1997 * non PF-specific interrupts from the various HW modules. Only one PCI
1998 * function at a time should be doing this.
2000 void t4_intr_enable(struct adapter *adapter)
2002 u32 pf = SOURCEPF_GET(t4_read_reg(adapter, PL_WHOAMI));
2004 t4_write_reg(adapter, SGE_INT_ENABLE3, ERR_CPL_EXCEED_IQE_SIZE |
2005 ERR_INVALID_CIDX_INC | ERR_CPL_OPCODE_0 |
2006 ERR_DROPPED_DB | ERR_DATA_CPL_ON_HIGH_QID1 |
2007 ERR_DATA_CPL_ON_HIGH_QID0 | ERR_BAD_DB_PIDX3 |
2008 ERR_BAD_DB_PIDX2 | ERR_BAD_DB_PIDX1 |
2009 ERR_BAD_DB_PIDX0 | ERR_ING_CTXT_PRIO |
2010 ERR_EGR_CTXT_PRIO | INGRESS_SIZE_ERR |
2011 DBFIFO_HP_INT | DBFIFO_LP_INT |
2013 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE), PF_INTR_MASK);
2014 t4_set_reg_field(adapter, PL_INT_MAP0, 0, 1 << pf);
2018 * t4_intr_disable - disable interrupts
2019 * @adapter: the adapter whose interrupts should be disabled
2021 * Disable interrupts. We only disable the top-level interrupt
2022 * concentrators. The caller must be a PCI function managing global
2025 void t4_intr_disable(struct adapter *adapter)
2027 u32 pf = SOURCEPF_GET(t4_read_reg(adapter, PL_WHOAMI));
2029 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE), 0);
2030 t4_set_reg_field(adapter, PL_INT_MAP0, 1 << pf, 0);
2034 * hash_mac_addr - return the hash value of a MAC address
2035 * @addr: the 48-bit Ethernet MAC address
2037 * Hashes a MAC address according to the hash function used by HW inexact
2038 * (hash) address matching.
2040 static int hash_mac_addr(const u8 *addr)
2042 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
2043 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
2051 * t4_config_rss_range - configure a portion of the RSS mapping table
2052 * @adapter: the adapter
2053 * @mbox: mbox to use for the FW command
2054 * @viid: virtual interface whose RSS subtable is to be written
2055 * @start: start entry in the table to write
2056 * @n: how many table entries to write
2057 * @rspq: values for the response queue lookup table
2058 * @nrspq: number of values in @rspq
2060 * Programs the selected part of the VI's RSS mapping table with the
2061 * provided values. If @nrspq < @n the supplied values are used repeatedly
2062 * until the full table range is populated.
2064 * The caller must ensure the values in @rspq are in the range allowed for
2067 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
2068 int start, int n, const u16 *rspq, unsigned int nrspq)
2071 const u16 *rsp = rspq;
2072 const u16 *rsp_end = rspq + nrspq;
2073 struct fw_rss_ind_tbl_cmd cmd;
2075 memset(&cmd, 0, sizeof(cmd));
2076 cmd.op_to_viid = htonl(FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
2077 FW_CMD_REQUEST | FW_CMD_WRITE |
2078 FW_RSS_IND_TBL_CMD_VIID(viid));
2079 cmd.retval_len16 = htonl(FW_LEN16(cmd));
2081 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
2083 int nq = min(n, 32);
2084 __be32 *qp = &cmd.iq0_to_iq2;
2086 cmd.niqid = htons(nq);
2087 cmd.startidx = htons(start);
2095 v = FW_RSS_IND_TBL_CMD_IQ0(*rsp);
2096 if (++rsp >= rsp_end)
2098 v |= FW_RSS_IND_TBL_CMD_IQ1(*rsp);
2099 if (++rsp >= rsp_end)
2101 v |= FW_RSS_IND_TBL_CMD_IQ2(*rsp);
2102 if (++rsp >= rsp_end)
2109 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
2117 * t4_config_glbl_rss - configure the global RSS mode
2118 * @adapter: the adapter
2119 * @mbox: mbox to use for the FW command
2120 * @mode: global RSS mode
2121 * @flags: mode-specific flags
2123 * Sets the global RSS mode.
2125 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
2128 struct fw_rss_glb_config_cmd c;
2130 memset(&c, 0, sizeof(c));
2131 c.op_to_write = htonl(FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) |
2132 FW_CMD_REQUEST | FW_CMD_WRITE);
2133 c.retval_len16 = htonl(FW_LEN16(c));
2134 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
2135 c.u.manual.mode_pkd = htonl(FW_RSS_GLB_CONFIG_CMD_MODE(mode));
2136 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
2137 c.u.basicvirtual.mode_pkd =
2138 htonl(FW_RSS_GLB_CONFIG_CMD_MODE(mode));
2139 c.u.basicvirtual.synmapen_to_hashtoeplitz = htonl(flags);
2142 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
2146 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
2147 * @adap: the adapter
2148 * @v4: holds the TCP/IP counter values
2149 * @v6: holds the TCP/IPv6 counter values
2151 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
2152 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
2154 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
2155 struct tp_tcp_stats *v6)
2157 u32 val[TP_MIB_TCP_RXT_SEG_LO - TP_MIB_TCP_OUT_RST + 1];
2159 #define STAT_IDX(x) ((TP_MIB_TCP_##x) - TP_MIB_TCP_OUT_RST)
2160 #define STAT(x) val[STAT_IDX(x)]
2161 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
2164 t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, val,
2165 ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST);
2166 v4->tcpOutRsts = STAT(OUT_RST);
2167 v4->tcpInSegs = STAT64(IN_SEG);
2168 v4->tcpOutSegs = STAT64(OUT_SEG);
2169 v4->tcpRetransSegs = STAT64(RXT_SEG);
2172 t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, val,
2173 ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST);
2174 v6->tcpOutRsts = STAT(OUT_RST);
2175 v6->tcpInSegs = STAT64(IN_SEG);
2176 v6->tcpOutSegs = STAT64(OUT_SEG);
2177 v6->tcpRetransSegs = STAT64(RXT_SEG);
2185 * t4_read_mtu_tbl - returns the values in the HW path MTU table
2186 * @adap: the adapter
2187 * @mtus: where to store the MTU values
2188 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
2190 * Reads the HW path MTU table.
2192 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
2197 for (i = 0; i < NMTUS; ++i) {
2198 t4_write_reg(adap, TP_MTU_TABLE,
2199 MTUINDEX(0xff) | MTUVALUE(i));
2200 v = t4_read_reg(adap, TP_MTU_TABLE);
2201 mtus[i] = MTUVALUE_GET(v);
2203 mtu_log[i] = MTUWIDTH_GET(v);
2208 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
2209 * @adap: the adapter
2210 * @addr: the indirect TP register address
2211 * @mask: specifies the field within the register to modify
2212 * @val: new value for the field
2214 * Sets a field of an indirect TP register to the given value.
2216 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
2217 unsigned int mask, unsigned int val)
2219 t4_write_reg(adap, TP_PIO_ADDR, addr);
2220 val |= t4_read_reg(adap, TP_PIO_DATA) & ~mask;
2221 t4_write_reg(adap, TP_PIO_DATA, val);
2225 * init_cong_ctrl - initialize congestion control parameters
2226 * @a: the alpha values for congestion control
2227 * @b: the beta values for congestion control
2229 * Initialize the congestion control parameters.
2231 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
2233 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
2258 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
2261 b[13] = b[14] = b[15] = b[16] = 3;
2262 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
2263 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
2268 /* The minimum additive increment value for the congestion control table */
2269 #define CC_MIN_INCR 2U
2272 * t4_load_mtus - write the MTU and congestion control HW tables
2273 * @adap: the adapter
2274 * @mtus: the values for the MTU table
2275 * @alpha: the values for the congestion control alpha parameter
2276 * @beta: the values for the congestion control beta parameter
2278 * Write the HW MTU table with the supplied MTUs and the high-speed
2279 * congestion control table with the supplied alpha, beta, and MTUs.
2280 * We write the two tables together because the additive increments
2281 * depend on the MTUs.
2283 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
2284 const unsigned short *alpha, const unsigned short *beta)
2286 static const unsigned int avg_pkts[NCCTRL_WIN] = {
2287 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
2288 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
2289 28672, 40960, 57344, 81920, 114688, 163840, 229376
2294 for (i = 0; i < NMTUS; ++i) {
2295 unsigned int mtu = mtus[i];
2296 unsigned int log2 = fls(mtu);
2298 if (!(mtu & ((1 << log2) >> 2))) /* round */
2300 t4_write_reg(adap, TP_MTU_TABLE, MTUINDEX(i) |
2301 MTUWIDTH(log2) | MTUVALUE(mtu));
2303 for (w = 0; w < NCCTRL_WIN; ++w) {
2306 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
2309 t4_write_reg(adap, TP_CCTRL_TABLE, (i << 21) |
2310 (w << 16) | (beta[w] << 13) | inc);
2316 * get_mps_bg_map - return the buffer groups associated with a port
2317 * @adap: the adapter
2318 * @idx: the port index
2320 * Returns a bitmap indicating which MPS buffer groups are associated
2321 * with the given port. Bit i is set if buffer group i is used by the
2324 static unsigned int get_mps_bg_map(struct adapter *adap, int idx)
2326 u32 n = NUMPORTS_GET(t4_read_reg(adap, MPS_CMN_CTL));
2329 return idx == 0 ? 0xf : 0;
2331 return idx < 2 ? (3 << (2 * idx)) : 0;
2336 * t4_get_port_type_description - return Port Type string description
2337 * @port_type: firmware Port Type enumeration
2339 const char *t4_get_port_type_description(enum fw_port_type port_type)
2341 static const char *const port_type_description[] = {
2360 if (port_type < ARRAY_SIZE(port_type_description))
2361 return port_type_description[port_type];
2366 * t4_get_port_stats - collect port statistics
2367 * @adap: the adapter
2368 * @idx: the port index
2369 * @p: the stats structure to fill
2371 * Collect statistics related to the given port from HW.
2373 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
2375 u32 bgmap = get_mps_bg_map(adap, idx);
2377 #define GET_STAT(name) \
2378 t4_read_reg64(adap, \
2379 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
2380 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
2381 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
2383 p->tx_octets = GET_STAT(TX_PORT_BYTES);
2384 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
2385 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
2386 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
2387 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
2388 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
2389 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
2390 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
2391 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
2392 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
2393 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
2394 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
2395 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
2396 p->tx_drop = GET_STAT(TX_PORT_DROP);
2397 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
2398 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
2399 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
2400 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
2401 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
2402 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
2403 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
2404 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
2405 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
2407 p->rx_octets = GET_STAT(RX_PORT_BYTES);
2408 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
2409 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
2410 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
2411 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
2412 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
2413 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
2414 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
2415 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
2416 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
2417 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
2418 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
2419 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
2420 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
2421 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
2422 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
2423 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
2424 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
2425 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
2426 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
2427 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
2428 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
2429 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
2430 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
2431 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
2432 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
2433 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
2435 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
2436 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
2437 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
2438 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
2439 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
2440 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
2441 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
2442 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
2449 * t4_wol_magic_enable - enable/disable magic packet WoL
2450 * @adap: the adapter
2451 * @port: the physical port index
2452 * @addr: MAC address expected in magic packets, %NULL to disable
2454 * Enables/disables magic packet wake-on-LAN for the selected port.
2456 void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
2459 u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg;
2461 if (is_t4(adap->params.chip)) {
2462 mag_id_reg_l = PORT_REG(port, XGMAC_PORT_MAGIC_MACID_LO);
2463 mag_id_reg_h = PORT_REG(port, XGMAC_PORT_MAGIC_MACID_HI);
2464 port_cfg_reg = PORT_REG(port, XGMAC_PORT_CFG2);
2466 mag_id_reg_l = T5_PORT_REG(port, MAC_PORT_MAGIC_MACID_LO);
2467 mag_id_reg_h = T5_PORT_REG(port, MAC_PORT_MAGIC_MACID_HI);
2468 port_cfg_reg = T5_PORT_REG(port, MAC_PORT_CFG2);
2472 t4_write_reg(adap, mag_id_reg_l,
2473 (addr[2] << 24) | (addr[3] << 16) |
2474 (addr[4] << 8) | addr[5]);
2475 t4_write_reg(adap, mag_id_reg_h,
2476 (addr[0] << 8) | addr[1]);
2478 t4_set_reg_field(adap, port_cfg_reg, MAGICEN,
2479 addr ? MAGICEN : 0);
2483 * t4_wol_pat_enable - enable/disable pattern-based WoL
2484 * @adap: the adapter
2485 * @port: the physical port index
2486 * @map: bitmap of which HW pattern filters to set
2487 * @mask0: byte mask for bytes 0-63 of a packet
2488 * @mask1: byte mask for bytes 64-127 of a packet
2489 * @crc: Ethernet CRC for selected bytes
2490 * @enable: enable/disable switch
2492 * Sets the pattern filters indicated in @map to mask out the bytes
2493 * specified in @mask0/@mask1 in received packets and compare the CRC of
2494 * the resulting packet against @crc. If @enable is %true pattern-based
2495 * WoL is enabled, otherwise disabled.
2497 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
2498 u64 mask0, u64 mask1, unsigned int crc, bool enable)
2503 if (is_t4(adap->params.chip))
2504 port_cfg_reg = PORT_REG(port, XGMAC_PORT_CFG2);
2506 port_cfg_reg = T5_PORT_REG(port, MAC_PORT_CFG2);
2509 t4_set_reg_field(adap, port_cfg_reg, PATEN, 0);
2515 #define EPIO_REG(name) \
2516 (is_t4(adap->params.chip) ? PORT_REG(port, XGMAC_PORT_EPIO_##name) : \
2517 T5_PORT_REG(port, MAC_PORT_EPIO_##name))
2519 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32);
2520 t4_write_reg(adap, EPIO_REG(DATA2), mask1);
2521 t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32);
2523 for (i = 0; i < NWOL_PAT; i++, map >>= 1) {
2527 /* write byte masks */
2528 t4_write_reg(adap, EPIO_REG(DATA0), mask0);
2529 t4_write_reg(adap, EPIO_REG(OP), ADDRESS(i) | EPIOWR);
2530 t4_read_reg(adap, EPIO_REG(OP)); /* flush */
2531 if (t4_read_reg(adap, EPIO_REG(OP)) & SF_BUSY)
2535 t4_write_reg(adap, EPIO_REG(DATA0), crc);
2536 t4_write_reg(adap, EPIO_REG(OP), ADDRESS(i + 32) | EPIOWR);
2537 t4_read_reg(adap, EPIO_REG(OP)); /* flush */
2538 if (t4_read_reg(adap, EPIO_REG(OP)) & SF_BUSY)
2543 t4_set_reg_field(adap, PORT_REG(port, XGMAC_PORT_CFG2), 0, PATEN);
2547 /* t4_mk_filtdelwr - create a delete filter WR
2548 * @ftid: the filter ID
2549 * @wr: the filter work request to populate
2550 * @qid: ingress queue to receive the delete notification
2552 * Creates a filter work request to delete the supplied filter. If @qid is
2553 * negative the delete notification is suppressed.
2555 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
2557 memset(wr, 0, sizeof(*wr));
2558 wr->op_pkd = htonl(FW_WR_OP(FW_FILTER_WR));
2559 wr->len16_pkd = htonl(FW_WR_LEN16(sizeof(*wr) / 16));
2560 wr->tid_to_iq = htonl(V_FW_FILTER_WR_TID(ftid) |
2561 V_FW_FILTER_WR_NOREPLY(qid < 0));
2562 wr->del_filter_to_l2tix = htonl(F_FW_FILTER_WR_DEL_FILTER);
2564 wr->rx_chan_rx_rpl_iq = htons(V_FW_FILTER_WR_RX_RPL_IQ(qid));
2567 #define INIT_CMD(var, cmd, rd_wr) do { \
2568 (var).op_to_write = htonl(FW_CMD_OP(FW_##cmd##_CMD) | \
2569 FW_CMD_REQUEST | FW_CMD_##rd_wr); \
2570 (var).retval_len16 = htonl(FW_LEN16(var)); \
2573 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
2576 struct fw_ldst_cmd c;
2578 memset(&c, 0, sizeof(c));
2579 c.op_to_addrspace = htonl(FW_CMD_OP(FW_LDST_CMD) | FW_CMD_REQUEST |
2581 FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE));
2582 c.cycles_to_len16 = htonl(FW_LEN16(c));
2583 c.u.addrval.addr = htonl(addr);
2584 c.u.addrval.val = htonl(val);
2586 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2590 * t4_mdio_rd - read a PHY register through MDIO
2591 * @adap: the adapter
2592 * @mbox: mailbox to use for the FW command
2593 * @phy_addr: the PHY address
2594 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
2595 * @reg: the register to read
2596 * @valp: where to store the value
2598 * Issues a FW command through the given mailbox to read a PHY register.
2600 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
2601 unsigned int mmd, unsigned int reg, u16 *valp)
2604 struct fw_ldst_cmd c;
2606 memset(&c, 0, sizeof(c));
2607 c.op_to_addrspace = htonl(FW_CMD_OP(FW_LDST_CMD) | FW_CMD_REQUEST |
2608 FW_CMD_READ | FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO));
2609 c.cycles_to_len16 = htonl(FW_LEN16(c));
2610 c.u.mdio.paddr_mmd = htons(FW_LDST_CMD_PADDR(phy_addr) |
2611 FW_LDST_CMD_MMD(mmd));
2612 c.u.mdio.raddr = htons(reg);
2614 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2616 *valp = ntohs(c.u.mdio.rval);
2621 * t4_mdio_wr - write a PHY register through MDIO
2622 * @adap: the adapter
2623 * @mbox: mailbox to use for the FW command
2624 * @phy_addr: the PHY address
2625 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
2626 * @reg: the register to write
2627 * @valp: value to write
2629 * Issues a FW command through the given mailbox to write a PHY register.
2631 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
2632 unsigned int mmd, unsigned int reg, u16 val)
2634 struct fw_ldst_cmd c;
2636 memset(&c, 0, sizeof(c));
2637 c.op_to_addrspace = htonl(FW_CMD_OP(FW_LDST_CMD) | FW_CMD_REQUEST |
2638 FW_CMD_WRITE | FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO));
2639 c.cycles_to_len16 = htonl(FW_LEN16(c));
2640 c.u.mdio.paddr_mmd = htons(FW_LDST_CMD_PADDR(phy_addr) |
2641 FW_LDST_CMD_MMD(mmd));
2642 c.u.mdio.raddr = htons(reg);
2643 c.u.mdio.rval = htons(val);
2645 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2649 * t4_sge_decode_idma_state - decode the idma state
2650 * @adap: the adapter
2651 * @state: the state idma is stuck in
2653 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
2655 static const char * const t4_decode[] = {
2657 "IDMA_PUSH_MORE_CPL_FIFO",
2658 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
2660 "IDMA_PHYSADDR_SEND_PCIEHDR",
2661 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
2662 "IDMA_PHYSADDR_SEND_PAYLOAD",
2663 "IDMA_SEND_FIFO_TO_IMSG",
2664 "IDMA_FL_REQ_DATA_FL_PREP",
2665 "IDMA_FL_REQ_DATA_FL",
2667 "IDMA_FL_H_REQ_HEADER_FL",
2668 "IDMA_FL_H_SEND_PCIEHDR",
2669 "IDMA_FL_H_PUSH_CPL_FIFO",
2670 "IDMA_FL_H_SEND_CPL",
2671 "IDMA_FL_H_SEND_IP_HDR_FIRST",
2672 "IDMA_FL_H_SEND_IP_HDR",
2673 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
2674 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
2675 "IDMA_FL_H_SEND_IP_HDR_PADDING",
2676 "IDMA_FL_D_SEND_PCIEHDR",
2677 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
2678 "IDMA_FL_D_REQ_NEXT_DATA_FL",
2679 "IDMA_FL_SEND_PCIEHDR",
2680 "IDMA_FL_PUSH_CPL_FIFO",
2682 "IDMA_FL_SEND_PAYLOAD_FIRST",
2683 "IDMA_FL_SEND_PAYLOAD",
2684 "IDMA_FL_REQ_NEXT_DATA_FL",
2685 "IDMA_FL_SEND_NEXT_PCIEHDR",
2686 "IDMA_FL_SEND_PADDING",
2687 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
2688 "IDMA_FL_SEND_FIFO_TO_IMSG",
2689 "IDMA_FL_REQ_DATAFL_DONE",
2690 "IDMA_FL_REQ_HEADERFL_DONE",
2692 static const char * const t5_decode[] = {
2695 "IDMA_PUSH_MORE_CPL_FIFO",
2696 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
2697 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
2698 "IDMA_PHYSADDR_SEND_PCIEHDR",
2699 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
2700 "IDMA_PHYSADDR_SEND_PAYLOAD",
2701 "IDMA_SEND_FIFO_TO_IMSG",
2702 "IDMA_FL_REQ_DATA_FL",
2704 "IDMA_FL_DROP_SEND_INC",
2705 "IDMA_FL_H_REQ_HEADER_FL",
2706 "IDMA_FL_H_SEND_PCIEHDR",
2707 "IDMA_FL_H_PUSH_CPL_FIFO",
2708 "IDMA_FL_H_SEND_CPL",
2709 "IDMA_FL_H_SEND_IP_HDR_FIRST",
2710 "IDMA_FL_H_SEND_IP_HDR",
2711 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
2712 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
2713 "IDMA_FL_H_SEND_IP_HDR_PADDING",
2714 "IDMA_FL_D_SEND_PCIEHDR",
2715 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
2716 "IDMA_FL_D_REQ_NEXT_DATA_FL",
2717 "IDMA_FL_SEND_PCIEHDR",
2718 "IDMA_FL_PUSH_CPL_FIFO",
2720 "IDMA_FL_SEND_PAYLOAD_FIRST",
2721 "IDMA_FL_SEND_PAYLOAD",
2722 "IDMA_FL_REQ_NEXT_DATA_FL",
2723 "IDMA_FL_SEND_NEXT_PCIEHDR",
2724 "IDMA_FL_SEND_PADDING",
2725 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
2727 static const u32 sge_regs[] = {
2728 SGE_DEBUG_DATA_LOW_INDEX_2,
2729 SGE_DEBUG_DATA_LOW_INDEX_3,
2730 SGE_DEBUG_DATA_HIGH_INDEX_10,
2732 const char **sge_idma_decode;
2733 int sge_idma_decode_nstates;
2736 if (is_t4(adapter->params.chip)) {
2737 sge_idma_decode = (const char **)t4_decode;
2738 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
2740 sge_idma_decode = (const char **)t5_decode;
2741 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
2744 if (state < sge_idma_decode_nstates)
2745 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
2747 CH_WARN(adapter, "idma state %d unknown\n", state);
2749 for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
2750 CH_WARN(adapter, "SGE register %#x value %#x\n",
2751 sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
2755 * t4_fw_hello - establish communication with FW
2756 * @adap: the adapter
2757 * @mbox: mailbox to use for the FW command
2758 * @evt_mbox: mailbox to receive async FW events
2759 * @master: specifies the caller's willingness to be the device master
2760 * @state: returns the current device state (if non-NULL)
2762 * Issues a command to establish communication with FW. Returns either
2763 * an error (negative integer) or the mailbox of the Master PF.
2765 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
2766 enum dev_master master, enum dev_state *state)
2769 struct fw_hello_cmd c;
2771 unsigned int master_mbox;
2772 int retries = FW_CMD_HELLO_RETRIES;
2775 memset(&c, 0, sizeof(c));
2776 INIT_CMD(c, HELLO, WRITE);
2777 c.err_to_clearinit = htonl(
2778 FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
2779 FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
2780 FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox :
2781 FW_HELLO_CMD_MBMASTER_MASK) |
2782 FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
2783 FW_HELLO_CMD_STAGE(fw_hello_cmd_stage_os) |
2784 FW_HELLO_CMD_CLEARINIT);
2787 * Issue the HELLO command to the firmware. If it's not successful
2788 * but indicates that we got a "busy" or "timeout" condition, retry
2789 * the HELLO until we exhaust our retry limit. If we do exceed our
2790 * retry limit, check to see if the firmware left us any error
2791 * information and report that if so.
2793 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2795 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
2797 if (t4_read_reg(adap, MA_PCIE_FW) & FW_PCIE_FW_ERR)
2798 t4_report_fw_error(adap);
2802 v = ntohl(c.err_to_clearinit);
2803 master_mbox = FW_HELLO_CMD_MBMASTER_GET(v);
2805 if (v & FW_HELLO_CMD_ERR)
2806 *state = DEV_STATE_ERR;
2807 else if (v & FW_HELLO_CMD_INIT)
2808 *state = DEV_STATE_INIT;
2810 *state = DEV_STATE_UNINIT;
2814 * If we're not the Master PF then we need to wait around for the
2815 * Master PF Driver to finish setting up the adapter.
2817 * Note that we also do this wait if we're a non-Master-capable PF and
2818 * there is no current Master PF; a Master PF may show up momentarily
2819 * and we wouldn't want to fail pointlessly. (This can happen when an
2820 * OS loads lots of different drivers rapidly at the same time). In
2821 * this case, the Master PF returned by the firmware will be
2822 * FW_PCIE_FW_MASTER_MASK so the test below will work ...
2824 if ((v & (FW_HELLO_CMD_ERR|FW_HELLO_CMD_INIT)) == 0 &&
2825 master_mbox != mbox) {
2826 int waiting = FW_CMD_HELLO_TIMEOUT;
2829 * Wait for the firmware to either indicate an error or
2830 * initialized state. If we see either of these we bail out
2831 * and report the issue to the caller. If we exhaust the
2832 * "hello timeout" and we haven't exhausted our retries, try
2833 * again. Otherwise bail with a timeout error.
2842 * If neither Error nor Initialialized are indicated
2843 * by the firmware keep waiting till we exaust our
2844 * timeout ... and then retry if we haven't exhausted
2847 pcie_fw = t4_read_reg(adap, MA_PCIE_FW);
2848 if (!(pcie_fw & (FW_PCIE_FW_ERR|FW_PCIE_FW_INIT))) {
2859 * We either have an Error or Initialized condition
2860 * report errors preferentially.
2863 if (pcie_fw & FW_PCIE_FW_ERR)
2864 *state = DEV_STATE_ERR;
2865 else if (pcie_fw & FW_PCIE_FW_INIT)
2866 *state = DEV_STATE_INIT;
2870 * If we arrived before a Master PF was selected and
2871 * there's not a valid Master PF, grab its identity
2874 if (master_mbox == FW_PCIE_FW_MASTER_MASK &&
2875 (pcie_fw & FW_PCIE_FW_MASTER_VLD))
2876 master_mbox = FW_PCIE_FW_MASTER_GET(pcie_fw);
2885 * t4_fw_bye - end communication with FW
2886 * @adap: the adapter
2887 * @mbox: mailbox to use for the FW command
2889 * Issues a command to terminate communication with FW.
2891 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
2893 struct fw_bye_cmd c;
2895 memset(&c, 0, sizeof(c));
2896 INIT_CMD(c, BYE, WRITE);
2897 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2901 * t4_init_cmd - ask FW to initialize the device
2902 * @adap: the adapter
2903 * @mbox: mailbox to use for the FW command
2905 * Issues a command to FW to partially initialize the device. This
2906 * performs initialization that generally doesn't depend on user input.
2908 int t4_early_init(struct adapter *adap, unsigned int mbox)
2910 struct fw_initialize_cmd c;
2912 memset(&c, 0, sizeof(c));
2913 INIT_CMD(c, INITIALIZE, WRITE);
2914 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2918 * t4_fw_reset - issue a reset to FW
2919 * @adap: the adapter
2920 * @mbox: mailbox to use for the FW command
2921 * @reset: specifies the type of reset to perform
2923 * Issues a reset command of the specified type to FW.
2925 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
2927 struct fw_reset_cmd c;
2929 memset(&c, 0, sizeof(c));
2930 INIT_CMD(c, RESET, WRITE);
2931 c.val = htonl(reset);
2932 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2936 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
2937 * @adap: the adapter
2938 * @mbox: mailbox to use for the FW RESET command (if desired)
2939 * @force: force uP into RESET even if FW RESET command fails
2941 * Issues a RESET command to firmware (if desired) with a HALT indication
2942 * and then puts the microprocessor into RESET state. The RESET command
2943 * will only be issued if a legitimate mailbox is provided (mbox <=
2944 * FW_PCIE_FW_MASTER_MASK).
2946 * This is generally used in order for the host to safely manipulate the
2947 * adapter without fear of conflicting with whatever the firmware might
2948 * be doing. The only way out of this state is to RESTART the firmware
2951 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
2956 * If a legitimate mailbox is provided, issue a RESET command
2957 * with a HALT indication.
2959 if (mbox <= FW_PCIE_FW_MASTER_MASK) {
2960 struct fw_reset_cmd c;
2962 memset(&c, 0, sizeof(c));
2963 INIT_CMD(c, RESET, WRITE);
2964 c.val = htonl(PIORST | PIORSTMODE);
2965 c.halt_pkd = htonl(FW_RESET_CMD_HALT(1U));
2966 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2970 * Normally we won't complete the operation if the firmware RESET
2971 * command fails but if our caller insists we'll go ahead and put the
2972 * uP into RESET. This can be useful if the firmware is hung or even
2973 * missing ... We'll have to take the risk of putting the uP into
2974 * RESET without the cooperation of firmware in that case.
2976 * We also force the firmware's HALT flag to be on in case we bypassed
2977 * the firmware RESET command above or we're dealing with old firmware
2978 * which doesn't have the HALT capability. This will serve as a flag
2979 * for the incoming firmware to know that it's coming out of a HALT
2980 * rather than a RESET ... if it's new enough to understand that ...
2982 if (ret == 0 || force) {
2983 t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, UPCRST);
2984 t4_set_reg_field(adap, PCIE_FW, FW_PCIE_FW_HALT,
2989 * And we always return the result of the firmware RESET command
2990 * even when we force the uP into RESET ...
2996 * t4_fw_restart - restart the firmware by taking the uP out of RESET
2997 * @adap: the adapter
2998 * @reset: if we want to do a RESET to restart things
3000 * Restart firmware previously halted by t4_fw_halt(). On successful
3001 * return the previous PF Master remains as the new PF Master and there
3002 * is no need to issue a new HELLO command, etc.
3004 * We do this in two ways:
3006 * 1. If we're dealing with newer firmware we'll simply want to take
3007 * the chip's microprocessor out of RESET. This will cause the
3008 * firmware to start up from its start vector. And then we'll loop
3009 * until the firmware indicates it's started again (PCIE_FW.HALT
3010 * reset to 0) or we timeout.
3012 * 2. If we're dealing with older firmware then we'll need to RESET
3013 * the chip since older firmware won't recognize the PCIE_FW.HALT
3014 * flag and automatically RESET itself on startup.
3016 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
3020 * Since we're directing the RESET instead of the firmware
3021 * doing it automatically, we need to clear the PCIE_FW.HALT
3024 t4_set_reg_field(adap, PCIE_FW, FW_PCIE_FW_HALT, 0);
3027 * If we've been given a valid mailbox, first try to get the
3028 * firmware to do the RESET. If that works, great and we can
3029 * return success. Otherwise, if we haven't been given a
3030 * valid mailbox or the RESET command failed, fall back to
3031 * hitting the chip with a hammer.
3033 if (mbox <= FW_PCIE_FW_MASTER_MASK) {
3034 t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, 0);
3036 if (t4_fw_reset(adap, mbox,
3037 PIORST | PIORSTMODE) == 0)
3041 t4_write_reg(adap, PL_RST, PIORST | PIORSTMODE);
3046 t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, 0);
3047 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
3048 if (!(t4_read_reg(adap, PCIE_FW) & FW_PCIE_FW_HALT))
3059 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
3060 * @adap: the adapter
3061 * @mbox: mailbox to use for the FW RESET command (if desired)
3062 * @fw_data: the firmware image to write
3064 * @force: force upgrade even if firmware doesn't cooperate
3066 * Perform all of the steps necessary for upgrading an adapter's
3067 * firmware image. Normally this requires the cooperation of the
3068 * existing firmware in order to halt all existing activities
3069 * but if an invalid mailbox token is passed in we skip that step
3070 * (though we'll still put the adapter microprocessor into RESET in
3073 * On successful return the new firmware will have been loaded and
3074 * the adapter will have been fully RESET losing all previous setup
3075 * state. On unsuccessful return the adapter may be completely hosed ...
3076 * positive errno indicates that the adapter is ~probably~ intact, a
3077 * negative errno indicates that things are looking bad ...
3079 static int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
3080 const u8 *fw_data, unsigned int size, int force)
3082 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
3085 ret = t4_fw_halt(adap, mbox, force);
3086 if (ret < 0 && !force)
3089 ret = t4_load_fw(adap, fw_data, size);
3094 * Older versions of the firmware don't understand the new
3095 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
3096 * restart. So for newly loaded older firmware we'll have to do the
3097 * RESET for it so it starts up on a clean slate. We can tell if
3098 * the newly loaded firmware will handle this right by checking
3099 * its header flags to see if it advertises the capability.
3101 reset = ((ntohl(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
3102 return t4_fw_restart(adap, mbox, reset);
3106 * t4_fixup_host_params - fix up host-dependent parameters
3107 * @adap: the adapter
3108 * @page_size: the host's Base Page Size
3109 * @cache_line_size: the host's Cache Line Size
3111 * Various registers in T4 contain values which are dependent on the
3112 * host's Base Page and Cache Line Sizes. This function will fix all of
3113 * those registers with the appropriate values as passed in ...
3115 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
3116 unsigned int cache_line_size)
3118 unsigned int page_shift = fls(page_size) - 1;
3119 unsigned int sge_hps = page_shift - 10;
3120 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
3121 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
3122 unsigned int fl_align_log = fls(fl_align) - 1;
3124 t4_write_reg(adap, SGE_HOST_PAGE_SIZE,
3125 HOSTPAGESIZEPF0(sge_hps) |
3126 HOSTPAGESIZEPF1(sge_hps) |
3127 HOSTPAGESIZEPF2(sge_hps) |
3128 HOSTPAGESIZEPF3(sge_hps) |
3129 HOSTPAGESIZEPF4(sge_hps) |
3130 HOSTPAGESIZEPF5(sge_hps) |
3131 HOSTPAGESIZEPF6(sge_hps) |
3132 HOSTPAGESIZEPF7(sge_hps));
3134 t4_set_reg_field(adap, SGE_CONTROL,
3135 INGPADBOUNDARY_MASK |
3136 EGRSTATUSPAGESIZE_MASK,
3137 INGPADBOUNDARY(fl_align_log - 5) |
3138 EGRSTATUSPAGESIZE(stat_len != 64));
3141 * Adjust various SGE Free List Host Buffer Sizes.
3143 * This is something of a crock since we're using fixed indices into
3144 * the array which are also known by the sge.c code and the T4
3145 * Firmware Configuration File. We need to come up with a much better
3146 * approach to managing this array. For now, the first four entries
3151 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
3152 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
3154 * For the single-MTU buffers in unpacked mode we need to include
3155 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
3156 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
3157 * Padding boundry. All of these are accommodated in the Factory
3158 * Default Firmware Configuration File but we need to adjust it for
3159 * this host's cache line size.
3161 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0, page_size);
3162 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2,
3163 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2) + fl_align-1)
3165 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3,
3166 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3) + fl_align-1)
3169 t4_write_reg(adap, ULP_RX_TDDP_PSZ, HPZ0(page_shift - 12));
3175 * t4_fw_initialize - ask FW to initialize the device
3176 * @adap: the adapter
3177 * @mbox: mailbox to use for the FW command
3179 * Issues a command to FW to partially initialize the device. This
3180 * performs initialization that generally doesn't depend on user input.
3182 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
3184 struct fw_initialize_cmd c;
3186 memset(&c, 0, sizeof(c));
3187 INIT_CMD(c, INITIALIZE, WRITE);
3188 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3192 * t4_query_params - query FW or device parameters
3193 * @adap: the adapter
3194 * @mbox: mailbox to use for the FW command
3197 * @nparams: the number of parameters
3198 * @params: the parameter names
3199 * @val: the parameter values
3201 * Reads the value of FW or device parameters. Up to 7 parameters can be
3204 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3205 unsigned int vf, unsigned int nparams, const u32 *params,
3209 struct fw_params_cmd c;
3210 __be32 *p = &c.param[0].mnem;
3215 memset(&c, 0, sizeof(c));
3216 c.op_to_vfn = htonl(FW_CMD_OP(FW_PARAMS_CMD) | FW_CMD_REQUEST |
3217 FW_CMD_READ | FW_PARAMS_CMD_PFN(pf) |
3218 FW_PARAMS_CMD_VFN(vf));
3219 c.retval_len16 = htonl(FW_LEN16(c));
3220 for (i = 0; i < nparams; i++, p += 2)
3221 *p = htonl(*params++);
3223 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3225 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
3231 * t4_set_params_nosleep - sets FW or device parameters
3232 * @adap: the adapter
3233 * @mbox: mailbox to use for the FW command
3236 * @nparams: the number of parameters
3237 * @params: the parameter names
3238 * @val: the parameter values
3240 * Does not ever sleep
3241 * Sets the value of FW or device parameters. Up to 7 parameters can be
3242 * specified at once.
3244 int t4_set_params_nosleep(struct adapter *adap, unsigned int mbox,
3245 unsigned int pf, unsigned int vf,
3246 unsigned int nparams, const u32 *params,
3249 struct fw_params_cmd c;
3250 __be32 *p = &c.param[0].mnem;
3255 memset(&c, 0, sizeof(c));
3256 c.op_to_vfn = cpu_to_be32(FW_CMD_OP(FW_PARAMS_CMD) |
3257 FW_CMD_REQUEST | FW_CMD_WRITE |
3258 FW_PARAMS_CMD_PFN(pf) |
3259 FW_PARAMS_CMD_VFN(vf));
3260 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3263 *p++ = cpu_to_be32(*params++);
3264 *p++ = cpu_to_be32(*val++);
3267 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
3271 * t4_set_params - sets FW or device parameters
3272 * @adap: the adapter
3273 * @mbox: mailbox to use for the FW command
3276 * @nparams: the number of parameters
3277 * @params: the parameter names
3278 * @val: the parameter values
3280 * Sets the value of FW or device parameters. Up to 7 parameters can be
3281 * specified at once.
3283 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3284 unsigned int vf, unsigned int nparams, const u32 *params,
3287 struct fw_params_cmd c;
3288 __be32 *p = &c.param[0].mnem;
3293 memset(&c, 0, sizeof(c));
3294 c.op_to_vfn = htonl(FW_CMD_OP(FW_PARAMS_CMD) | FW_CMD_REQUEST |
3295 FW_CMD_WRITE | FW_PARAMS_CMD_PFN(pf) |
3296 FW_PARAMS_CMD_VFN(vf));
3297 c.retval_len16 = htonl(FW_LEN16(c));
3299 *p++ = htonl(*params++);
3300 *p++ = htonl(*val++);
3303 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3307 * t4_cfg_pfvf - configure PF/VF resource limits
3308 * @adap: the adapter
3309 * @mbox: mailbox to use for the FW command
3310 * @pf: the PF being configured
3311 * @vf: the VF being configured
3312 * @txq: the max number of egress queues
3313 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
3314 * @rxqi: the max number of interrupt-capable ingress queues
3315 * @rxq: the max number of interruptless ingress queues
3316 * @tc: the PCI traffic class
3317 * @vi: the max number of virtual interfaces
3318 * @cmask: the channel access rights mask for the PF/VF
3319 * @pmask: the port access rights mask for the PF/VF
3320 * @nexact: the maximum number of exact MPS filters
3321 * @rcaps: read capabilities
3322 * @wxcaps: write/execute capabilities
3324 * Configures resource limits and capabilities for a physical or virtual
3327 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
3328 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
3329 unsigned int rxqi, unsigned int rxq, unsigned int tc,
3330 unsigned int vi, unsigned int cmask, unsigned int pmask,
3331 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
3333 struct fw_pfvf_cmd c;
3335 memset(&c, 0, sizeof(c));
3336 c.op_to_vfn = htonl(FW_CMD_OP(FW_PFVF_CMD) | FW_CMD_REQUEST |
3337 FW_CMD_WRITE | FW_PFVF_CMD_PFN(pf) |
3338 FW_PFVF_CMD_VFN(vf));
3339 c.retval_len16 = htonl(FW_LEN16(c));
3340 c.niqflint_niq = htonl(FW_PFVF_CMD_NIQFLINT(rxqi) |
3341 FW_PFVF_CMD_NIQ(rxq));
3342 c.type_to_neq = htonl(FW_PFVF_CMD_CMASK(cmask) |
3343 FW_PFVF_CMD_PMASK(pmask) |
3344 FW_PFVF_CMD_NEQ(txq));
3345 c.tc_to_nexactf = htonl(FW_PFVF_CMD_TC(tc) | FW_PFVF_CMD_NVI(vi) |
3346 FW_PFVF_CMD_NEXACTF(nexact));
3347 c.r_caps_to_nethctrl = htonl(FW_PFVF_CMD_R_CAPS(rcaps) |
3348 FW_PFVF_CMD_WX_CAPS(wxcaps) |
3349 FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl));
3350 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3354 * t4_alloc_vi - allocate a virtual interface
3355 * @adap: the adapter
3356 * @mbox: mailbox to use for the FW command
3357 * @port: physical port associated with the VI
3358 * @pf: the PF owning the VI
3359 * @vf: the VF owning the VI
3360 * @nmac: number of MAC addresses needed (1 to 5)
3361 * @mac: the MAC addresses of the VI
3362 * @rss_size: size of RSS table slice associated with this VI
3364 * Allocates a virtual interface for the given physical port. If @mac is
3365 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
3366 * @mac should be large enough to hold @nmac Ethernet addresses, they are
3367 * stored consecutively so the space needed is @nmac * 6 bytes.
3368 * Returns a negative error number or the non-negative VI id.
3370 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
3371 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
3372 unsigned int *rss_size)
3377 memset(&c, 0, sizeof(c));
3378 c.op_to_vfn = htonl(FW_CMD_OP(FW_VI_CMD) | FW_CMD_REQUEST |
3379 FW_CMD_WRITE | FW_CMD_EXEC |
3380 FW_VI_CMD_PFN(pf) | FW_VI_CMD_VFN(vf));
3381 c.alloc_to_len16 = htonl(FW_VI_CMD_ALLOC | FW_LEN16(c));
3382 c.portid_pkd = FW_VI_CMD_PORTID(port);
3385 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3390 memcpy(mac, c.mac, sizeof(c.mac));
3393 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
3395 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
3397 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
3399 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
3403 *rss_size = FW_VI_CMD_RSSSIZE_GET(ntohs(c.rsssize_pkd));
3404 return FW_VI_CMD_VIID_GET(ntohs(c.type_viid));
3408 * t4_set_rxmode - set Rx properties of a virtual interface
3409 * @adap: the adapter
3410 * @mbox: mailbox to use for the FW command
3412 * @mtu: the new MTU or -1
3413 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
3414 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
3415 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
3416 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
3417 * @sleep_ok: if true we may sleep while awaiting command completion
3419 * Sets Rx properties of a virtual interface.
3421 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
3422 int mtu, int promisc, int all_multi, int bcast, int vlanex,
3425 struct fw_vi_rxmode_cmd c;
3427 /* convert to FW values */
3429 mtu = FW_RXMODE_MTU_NO_CHG;
3431 promisc = FW_VI_RXMODE_CMD_PROMISCEN_MASK;
3433 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_MASK;
3435 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_MASK;
3437 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_MASK;
3439 memset(&c, 0, sizeof(c));
3440 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_RXMODE_CMD) | FW_CMD_REQUEST |
3441 FW_CMD_WRITE | FW_VI_RXMODE_CMD_VIID(viid));
3442 c.retval_len16 = htonl(FW_LEN16(c));
3443 c.mtu_to_vlanexen = htonl(FW_VI_RXMODE_CMD_MTU(mtu) |
3444 FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
3445 FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
3446 FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
3447 FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
3448 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
3452 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
3453 * @adap: the adapter
3454 * @mbox: mailbox to use for the FW command
3456 * @free: if true any existing filters for this VI id are first removed
3457 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
3458 * @addr: the MAC address(es)
3459 * @idx: where to store the index of each allocated filter
3460 * @hash: pointer to hash address filter bitmap
3461 * @sleep_ok: call is allowed to sleep
3463 * Allocates an exact-match filter for each of the supplied addresses and
3464 * sets it to the corresponding address. If @idx is not %NULL it should
3465 * have at least @naddr entries, each of which will be set to the index of
3466 * the filter allocated for the corresponding MAC address. If a filter
3467 * could not be allocated for an address its index is set to 0xffff.
3468 * If @hash is not %NULL addresses that fail to allocate an exact filter
3469 * are hashed and update the hash filter bitmap pointed at by @hash.
3471 * Returns a negative error number or the number of filters allocated.
3473 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
3474 unsigned int viid, bool free, unsigned int naddr,
3475 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
3478 struct fw_vi_mac_cmd c;
3479 struct fw_vi_mac_exact *p;
3480 unsigned int max_naddr = is_t4(adap->params.chip) ?
3481 NUM_MPS_CLS_SRAM_L_INSTANCES :
3482 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
3487 memset(&c, 0, sizeof(c));
3488 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_MAC_CMD) | FW_CMD_REQUEST |
3489 FW_CMD_WRITE | (free ? FW_CMD_EXEC : 0) |
3490 FW_VI_MAC_CMD_VIID(viid));
3491 c.freemacs_to_len16 = htonl(FW_VI_MAC_CMD_FREEMACS(free) |
3492 FW_CMD_LEN16((naddr + 2) / 2));
3494 for (i = 0, p = c.u.exact; i < naddr; i++, p++) {
3495 p->valid_to_idx = htons(FW_VI_MAC_CMD_VALID |
3496 FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC));
3497 memcpy(p->macaddr, addr[i], sizeof(p->macaddr));
3500 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
3504 for (i = 0, p = c.u.exact; i < naddr; i++, p++) {
3505 u16 index = FW_VI_MAC_CMD_IDX_GET(ntohs(p->valid_to_idx));
3508 idx[i] = index >= max_naddr ? 0xffff : index;
3509 if (index < max_naddr)
3512 *hash |= (1ULL << hash_mac_addr(addr[i]));
3518 * t4_change_mac - modifies the exact-match filter for a MAC address
3519 * @adap: the adapter
3520 * @mbox: mailbox to use for the FW command
3522 * @idx: index of existing filter for old value of MAC address, or -1
3523 * @addr: the new MAC address value
3524 * @persist: whether a new MAC allocation should be persistent
3525 * @add_smt: if true also add the address to the HW SMT
3527 * Modifies an exact-match filter and sets it to the new MAC address.
3528 * Note that in general it is not possible to modify the value of a given
3529 * filter so the generic way to modify an address filter is to free the one
3530 * being used by the old address value and allocate a new filter for the
3531 * new address value. @idx can be -1 if the address is a new addition.
3533 * Returns a negative error number or the index of the filter with the new
3536 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
3537 int idx, const u8 *addr, bool persist, bool add_smt)
3540 struct fw_vi_mac_cmd c;
3541 struct fw_vi_mac_exact *p = c.u.exact;
3542 unsigned int max_mac_addr = is_t4(adap->params.chip) ?
3543 NUM_MPS_CLS_SRAM_L_INSTANCES :
3544 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
3546 if (idx < 0) /* new allocation */
3547 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
3548 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
3550 memset(&c, 0, sizeof(c));
3551 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_MAC_CMD) | FW_CMD_REQUEST |
3552 FW_CMD_WRITE | FW_VI_MAC_CMD_VIID(viid));
3553 c.freemacs_to_len16 = htonl(FW_CMD_LEN16(1));
3554 p->valid_to_idx = htons(FW_VI_MAC_CMD_VALID |
3555 FW_VI_MAC_CMD_SMAC_RESULT(mode) |
3556 FW_VI_MAC_CMD_IDX(idx));
3557 memcpy(p->macaddr, addr, sizeof(p->macaddr));
3559 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3561 ret = FW_VI_MAC_CMD_IDX_GET(ntohs(p->valid_to_idx));
3562 if (ret >= max_mac_addr)
3569 * t4_set_addr_hash - program the MAC inexact-match hash filter
3570 * @adap: the adapter
3571 * @mbox: mailbox to use for the FW command
3573 * @ucast: whether the hash filter should also match unicast addresses
3574 * @vec: the value to be written to the hash filter
3575 * @sleep_ok: call is allowed to sleep
3577 * Sets the 64-bit inexact-match hash filter for a virtual interface.
3579 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
3580 bool ucast, u64 vec, bool sleep_ok)
3582 struct fw_vi_mac_cmd c;
3584 memset(&c, 0, sizeof(c));
3585 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_MAC_CMD) | FW_CMD_REQUEST |
3586 FW_CMD_WRITE | FW_VI_ENABLE_CMD_VIID(viid));
3587 c.freemacs_to_len16 = htonl(FW_VI_MAC_CMD_HASHVECEN |
3588 FW_VI_MAC_CMD_HASHUNIEN(ucast) |
3590 c.u.hash.hashvec = cpu_to_be64(vec);
3591 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
3595 * t4_enable_vi_params - enable/disable a virtual interface
3596 * @adap: the adapter
3597 * @mbox: mailbox to use for the FW command
3599 * @rx_en: 1=enable Rx, 0=disable Rx
3600 * @tx_en: 1=enable Tx, 0=disable Tx
3601 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
3603 * Enables/disables a virtual interface. Note that setting DCB Enable
3604 * only makes sense when enabling a Virtual Interface ...
3606 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
3607 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
3609 struct fw_vi_enable_cmd c;
3611 memset(&c, 0, sizeof(c));
3612 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_ENABLE_CMD) | FW_CMD_REQUEST |
3613 FW_CMD_EXEC | FW_VI_ENABLE_CMD_VIID(viid));
3615 c.ien_to_len16 = htonl(FW_VI_ENABLE_CMD_IEN(rx_en) |
3616 FW_VI_ENABLE_CMD_EEN(tx_en) | FW_LEN16(c) |
3617 FW_VI_ENABLE_CMD_DCB_INFO(dcb_en));
3618 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
3622 * t4_enable_vi - enable/disable a virtual interface
3623 * @adap: the adapter
3624 * @mbox: mailbox to use for the FW command
3626 * @rx_en: 1=enable Rx, 0=disable Rx
3627 * @tx_en: 1=enable Tx, 0=disable Tx
3629 * Enables/disables a virtual interface.
3631 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
3632 bool rx_en, bool tx_en)
3634 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
3638 * t4_identify_port - identify a VI's port by blinking its LED
3639 * @adap: the adapter
3640 * @mbox: mailbox to use for the FW command
3642 * @nblinks: how many times to blink LED at 2.5 Hz
3644 * Identifies a VI's port by blinking its LED.
3646 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
3647 unsigned int nblinks)
3649 struct fw_vi_enable_cmd c;
3651 memset(&c, 0, sizeof(c));
3652 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_ENABLE_CMD) | FW_CMD_REQUEST |
3653 FW_CMD_EXEC | FW_VI_ENABLE_CMD_VIID(viid));
3654 c.ien_to_len16 = htonl(FW_VI_ENABLE_CMD_LED | FW_LEN16(c));
3655 c.blinkdur = htons(nblinks);
3656 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3660 * t4_iq_free - free an ingress queue and its FLs
3661 * @adap: the adapter
3662 * @mbox: mailbox to use for the FW command
3663 * @pf: the PF owning the queues
3664 * @vf: the VF owning the queues
3665 * @iqtype: the ingress queue type
3666 * @iqid: ingress queue id
3667 * @fl0id: FL0 queue id or 0xffff if no attached FL0
3668 * @fl1id: FL1 queue id or 0xffff if no attached FL1
3670 * Frees an ingress queue and its associated FLs, if any.
3672 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3673 unsigned int vf, unsigned int iqtype, unsigned int iqid,
3674 unsigned int fl0id, unsigned int fl1id)
3678 memset(&c, 0, sizeof(c));
3679 c.op_to_vfn = htonl(FW_CMD_OP(FW_IQ_CMD) | FW_CMD_REQUEST |
3680 FW_CMD_EXEC | FW_IQ_CMD_PFN(pf) |
3682 c.alloc_to_len16 = htonl(FW_IQ_CMD_FREE | FW_LEN16(c));
3683 c.type_to_iqandstindex = htonl(FW_IQ_CMD_TYPE(iqtype));
3684 c.iqid = htons(iqid);
3685 c.fl0id = htons(fl0id);
3686 c.fl1id = htons(fl1id);
3687 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3691 * t4_eth_eq_free - free an Ethernet egress queue
3692 * @adap: the adapter
3693 * @mbox: mailbox to use for the FW command
3694 * @pf: the PF owning the queue
3695 * @vf: the VF owning the queue
3696 * @eqid: egress queue id
3698 * Frees an Ethernet egress queue.
3700 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3701 unsigned int vf, unsigned int eqid)
3703 struct fw_eq_eth_cmd c;
3705 memset(&c, 0, sizeof(c));
3706 c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_ETH_CMD) | FW_CMD_REQUEST |
3707 FW_CMD_EXEC | FW_EQ_ETH_CMD_PFN(pf) |
3708 FW_EQ_ETH_CMD_VFN(vf));
3709 c.alloc_to_len16 = htonl(FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
3710 c.eqid_pkd = htonl(FW_EQ_ETH_CMD_EQID(eqid));
3711 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3715 * t4_ctrl_eq_free - free a control egress queue
3716 * @adap: the adapter
3717 * @mbox: mailbox to use for the FW command
3718 * @pf: the PF owning the queue
3719 * @vf: the VF owning the queue
3720 * @eqid: egress queue id
3722 * Frees a control egress queue.
3724 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3725 unsigned int vf, unsigned int eqid)
3727 struct fw_eq_ctrl_cmd c;
3729 memset(&c, 0, sizeof(c));
3730 c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_CTRL_CMD) | FW_CMD_REQUEST |
3731 FW_CMD_EXEC | FW_EQ_CTRL_CMD_PFN(pf) |
3732 FW_EQ_CTRL_CMD_VFN(vf));
3733 c.alloc_to_len16 = htonl(FW_EQ_CTRL_CMD_FREE | FW_LEN16(c));
3734 c.cmpliqid_eqid = htonl(FW_EQ_CTRL_CMD_EQID(eqid));
3735 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3739 * t4_ofld_eq_free - free an offload egress queue
3740 * @adap: the adapter
3741 * @mbox: mailbox to use for the FW command
3742 * @pf: the PF owning the queue
3743 * @vf: the VF owning the queue
3744 * @eqid: egress queue id
3746 * Frees a control egress queue.
3748 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3749 unsigned int vf, unsigned int eqid)
3751 struct fw_eq_ofld_cmd c;
3753 memset(&c, 0, sizeof(c));
3754 c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_OFLD_CMD) | FW_CMD_REQUEST |
3755 FW_CMD_EXEC | FW_EQ_OFLD_CMD_PFN(pf) |
3756 FW_EQ_OFLD_CMD_VFN(vf));
3757 c.alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_FREE | FW_LEN16(c));
3758 c.eqid_pkd = htonl(FW_EQ_OFLD_CMD_EQID(eqid));
3759 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3763 * t4_handle_fw_rpl - process a FW reply message
3764 * @adap: the adapter
3765 * @rpl: start of the FW message
3767 * Processes a FW message, such as link state change messages.
3769 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
3771 u8 opcode = *(const u8 *)rpl;
3773 if (opcode == FW_PORT_CMD) { /* link/module state change message */
3774 int speed = 0, fc = 0;
3775 const struct fw_port_cmd *p = (void *)rpl;
3776 int chan = FW_PORT_CMD_PORTID_GET(ntohl(p->op_to_portid));
3777 int port = adap->chan_map[chan];
3778 struct port_info *pi = adap2pinfo(adap, port);
3779 struct link_config *lc = &pi->link_cfg;
3780 u32 stat = ntohl(p->u.info.lstatus_to_modtype);
3781 int link_ok = (stat & FW_PORT_CMD_LSTATUS) != 0;
3782 u32 mod = FW_PORT_CMD_MODTYPE_GET(stat);
3784 if (stat & FW_PORT_CMD_RXPAUSE)
3786 if (stat & FW_PORT_CMD_TXPAUSE)
3788 if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
3790 else if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
3792 else if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
3794 else if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
3797 if (link_ok != lc->link_ok || speed != lc->speed ||
3798 fc != lc->fc) { /* something changed */
3799 lc->link_ok = link_ok;
3802 lc->supported = be16_to_cpu(p->u.info.pcap);
3803 t4_os_link_changed(adap, port, link_ok);
3805 if (mod != pi->mod_type) {
3807 t4_os_portmod_changed(adap, port);
3813 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
3817 if (pci_is_pcie(adapter->pdev)) {
3818 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
3819 p->speed = val & PCI_EXP_LNKSTA_CLS;
3820 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
3825 * init_link_config - initialize a link's SW state
3826 * @lc: structure holding the link state
3827 * @caps: link capabilities
3829 * Initializes the SW state maintained for each link, including the link's
3830 * capabilities and default speed/flow-control/autonegotiation settings.
3832 static void init_link_config(struct link_config *lc, unsigned int caps)
3834 lc->supported = caps;
3835 lc->requested_speed = 0;
3837 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
3838 if (lc->supported & FW_PORT_CAP_ANEG) {
3839 lc->advertising = lc->supported & ADVERT_MASK;
3840 lc->autoneg = AUTONEG_ENABLE;
3841 lc->requested_fc |= PAUSE_AUTONEG;
3843 lc->advertising = 0;
3844 lc->autoneg = AUTONEG_DISABLE;
3848 #define CIM_PF_NOACCESS 0xeeeeeeee
3850 int t4_wait_dev_ready(void __iomem *regs)
3854 whoami = readl(regs + PL_WHOAMI);
3855 if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
3859 whoami = readl(regs + PL_WHOAMI);
3860 return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
3864 u32 vendor_and_model_id;
3868 static int get_flash_params(struct adapter *adap)
3870 /* Table for non-Numonix supported flash parts. Numonix parts are left
3871 * to the preexisting code. All flash parts have 64KB sectors.
3873 static struct flash_desc supported_flash[] = {
3874 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
3880 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
3882 ret = sf1_read(adap, 3, 0, 1, &info);
3883 t4_write_reg(adap, SF_OP, 0); /* unlock SF */
3887 for (ret = 0; ret < ARRAY_SIZE(supported_flash); ++ret)
3888 if (supported_flash[ret].vendor_and_model_id == info) {
3889 adap->params.sf_size = supported_flash[ret].size_mb;
3890 adap->params.sf_nsec =
3891 adap->params.sf_size / SF_SEC_SIZE;
3895 if ((info & 0xff) != 0x20) /* not a Numonix flash */
3897 info >>= 16; /* log2 of size */
3898 if (info >= 0x14 && info < 0x18)
3899 adap->params.sf_nsec = 1 << (info - 16);
3900 else if (info == 0x18)
3901 adap->params.sf_nsec = 64;
3904 adap->params.sf_size = 1 << info;
3905 adap->params.sf_fw_start =
3906 t4_read_reg(adap, CIM_BOOT_CFG) & BOOTADDR_MASK;
3908 if (adap->params.sf_size < FLASH_MIN_SIZE)
3909 dev_warn(adap->pdev_dev, "WARNING!!! FLASH size %#x < %#x!!!\n",
3910 adap->params.sf_size, FLASH_MIN_SIZE);
3915 * t4_prep_adapter - prepare SW and HW for operation
3916 * @adapter: the adapter
3917 * @reset: if true perform a HW reset
3919 * Initialize adapter SW state for the various HW modules, set initial
3920 * values for some adapter tunables, take PHYs out of reset, and
3921 * initialize the MDIO interface.
3923 int t4_prep_adapter(struct adapter *adapter)
3929 get_pci_mode(adapter, &adapter->params.pci);
3930 pl_rev = G_REV(t4_read_reg(adapter, PL_REV));
3932 ret = get_flash_params(adapter);
3934 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
3938 /* Retrieve adapter's device ID
3940 pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
3941 ver = device_id >> 12;
3942 adapter->params.chip = 0;
3945 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
3948 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
3951 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
3956 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
3959 * Default port for debugging in case we can't reach FW.
3961 adapter->params.nports = 1;
3962 adapter->params.portvec = 1;
3963 adapter->params.vpd.cclk = 50000;
3968 * t4_init_tp_params - initialize adap->params.tp
3969 * @adap: the adapter
3971 * Initialize various fields of the adapter's TP Parameters structure.
3973 int t4_init_tp_params(struct adapter *adap)
3978 v = t4_read_reg(adap, TP_TIMER_RESOLUTION);
3979 adap->params.tp.tre = TIMERRESOLUTION_GET(v);
3980 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_GET(v);
3982 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
3983 for (chan = 0; chan < NCHAN; chan++)
3984 adap->params.tp.tx_modq[chan] = chan;
3986 /* Cache the adapter's Compressed Filter Mode and global Incress
3989 t4_read_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
3990 &adap->params.tp.vlan_pri_map, 1,
3992 t4_read_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
3993 &adap->params.tp.ingress_config, 1,
3996 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
3997 * shift positions of several elements of the Compressed Filter Tuple
3998 * for this adapter which we need frequently ...
4000 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, F_VLAN);
4001 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
4002 adap->params.tp.port_shift = t4_filter_field_shift(adap, F_PORT);
4003 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
4006 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
4007 * represents the presense of an Outer VLAN instead of a VNIC ID.
4009 if ((adap->params.tp.ingress_config & F_VNIC) == 0)
4010 adap->params.tp.vnic_shift = -1;
4016 * t4_filter_field_shift - calculate filter field shift
4017 * @adap: the adapter
4018 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
4020 * Return the shift position of a filter field within the Compressed
4021 * Filter Tuple. The filter field is specified via its selection bit
4022 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
4024 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
4026 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
4030 if ((filter_mode & filter_sel) == 0)
4033 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
4034 switch (filter_mode & sel) {
4036 field_shift += W_FT_FCOE;
4039 field_shift += W_FT_PORT;
4042 field_shift += W_FT_VNIC_ID;
4045 field_shift += W_FT_VLAN;
4048 field_shift += W_FT_TOS;
4051 field_shift += W_FT_PROTOCOL;
4054 field_shift += W_FT_ETHERTYPE;
4057 field_shift += W_FT_MACMATCH;
4060 field_shift += W_FT_MPSHITTYPE;
4062 case F_FRAGMENTATION:
4063 field_shift += W_FT_FRAGMENTATION;
4070 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
4074 struct fw_port_cmd c;
4075 struct fw_rss_vi_config_cmd rvc;
4077 memset(&c, 0, sizeof(c));
4078 memset(&rvc, 0, sizeof(rvc));
4080 for_each_port(adap, i) {
4081 unsigned int rss_size;
4082 struct port_info *p = adap2pinfo(adap, i);
4084 while ((adap->params.portvec & (1 << j)) == 0)
4087 c.op_to_portid = htonl(FW_CMD_OP(FW_PORT_CMD) |
4088 FW_CMD_REQUEST | FW_CMD_READ |
4089 FW_PORT_CMD_PORTID(j));
4090 c.action_to_len16 = htonl(
4091 FW_PORT_CMD_ACTION(FW_PORT_ACTION_GET_PORT_INFO) |
4093 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
4097 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
4104 p->rss_size = rss_size;
4105 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
4106 adap->port[i]->dev_port = j;
4108 ret = ntohl(c.u.info.lstatus_to_modtype);
4109 p->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP) ?
4110 FW_PORT_CMD_MDIOADDR_GET(ret) : -1;
4111 p->port_type = FW_PORT_CMD_PTYPE_GET(ret);
4112 p->mod_type = FW_PORT_MOD_TYPE_NA;
4114 rvc.op_to_viid = htonl(FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
4115 FW_CMD_REQUEST | FW_CMD_READ |
4116 FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
4117 rvc.retval_len16 = htonl(FW_LEN16(rvc));
4118 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
4121 p->rss_mode = ntohl(rvc.u.basicvirtual.defaultq_to_udpen);
4123 init_link_config(&p->link_cfg, ntohs(c.u.info.pcap));