drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2009-2014 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #ifndef _T4FW_INTERFACE_H_
  36 #define _T4FW_INTERFACE_H_
  37
  38 enum fw_retval {
  39         FW_SUCCESS              = 0,    /* completed successfully */
  40         FW_EPERM                = 1,    /* operation not permitted */
  41         FW_ENOENT               = 2,    /* no such file or directory */
  42         FW_EIO                  = 5,    /* input/output error; hw bad */
  43         FW_ENOEXEC              = 8,    /* exec format error; inv microcode */
  44         FW_EAGAIN               = 11,   /* try again */
  45         FW_ENOMEM               = 12,   /* out of memory */
  46         FW_EFAULT               = 14,   /* bad address; fw bad */
  47         FW_EBUSY                = 16,   /* resource busy */
  48         FW_EEXIST               = 17,   /* file exists */
  49         FW_ENODEV               = 19,   /* no such device */
  50         FW_EINVAL               = 22,   /* invalid argument */
  51         FW_ENOSPC               = 28,   /* no space left on device */
  52         FW_ENOSYS               = 38,   /* functionality not implemented */
  53         FW_ENODATA              = 61,   /* no data available */
  54         FW_EPROTO               = 71,   /* protocol error */
  55         FW_EADDRINUSE           = 98,   /* address already in use */
  56         FW_EADDRNOTAVAIL        = 99,   /* cannot assigned requested address */
  57         FW_ENETDOWN             = 100,  /* network is down */
  58         FW_ENETUNREACH          = 101,  /* network is unreachable */
  59         FW_ENOBUFS              = 105,  /* no buffer space available */
  60         FW_ETIMEDOUT            = 110,  /* timeout */
  61         FW_EINPROGRESS          = 115,  /* fw internal */
  62         FW_SCSI_ABORT_REQUESTED = 128,  /* */
  63         FW_SCSI_ABORT_TIMEDOUT  = 129,  /* */
  64         FW_SCSI_ABORTED         = 130,  /* */
  65         FW_SCSI_CLOSE_REQUESTED = 131,  /* */
  66         FW_ERR_LINK_DOWN        = 132,  /* */
  67         FW_RDEV_NOT_READY       = 133,  /* */
  68         FW_ERR_RDEV_LOST        = 134,  /* */
  69         FW_ERR_RDEV_LOGO        = 135,  /* */
  70         FW_FCOE_NO_XCHG         = 136,  /* */
  71         FW_SCSI_RSP_ERR         = 137,  /* */
  72         FW_ERR_RDEV_IMPL_LOGO   = 138,  /* */
  73         FW_SCSI_UNDER_FLOW_ERR  = 139,  /* */
  74         FW_SCSI_OVER_FLOW_ERR   = 140,  /* */
  75         FW_SCSI_DDP_ERR         = 141,  /* DDP error*/
  76         FW_SCSI_TASK_ERR        = 142,  /* No SCSI tasks available */
  77 };
  78
  79 #define FW_T4VF_SGE_BASE_ADDR      0x0000
  80 #define FW_T4VF_MPS_BASE_ADDR      0x0100
  81 #define FW_T4VF_PL_BASE_ADDR       0x0200
  82 #define FW_T4VF_MBDATA_BASE_ADDR   0x0240
  83 #define FW_T4VF_CIM_BASE_ADDR      0x0300
  84
  85 enum fw_wr_opcodes {
  86         FW_FILTER_WR                   = 0x02,
  87         FW_ULPTX_WR                    = 0x04,
  88         FW_TP_WR                       = 0x05,
  89         FW_ETH_TX_PKT_WR               = 0x08,
  90         FW_OFLD_CONNECTION_WR          = 0x2f,
  91         FW_FLOWC_WR                    = 0x0a,
  92         FW_OFLD_TX_DATA_WR             = 0x0b,
  93         FW_CMD_WR                      = 0x10,
  94         FW_ETH_TX_PKT_VM_WR            = 0x11,
  95         FW_RI_RES_WR                   = 0x0c,
  96         FW_RI_INIT_WR                  = 0x0d,
  97         FW_RI_RDMA_WRITE_WR            = 0x14,
  98         FW_RI_SEND_WR                  = 0x15,
  99         FW_RI_RDMA_READ_WR             = 0x16,
 100         FW_RI_RECV_WR                  = 0x17,
 101         FW_RI_BIND_MW_WR               = 0x18,
 102         FW_RI_FR_NSMR_WR               = 0x19,
 103         FW_RI_INV_LSTAG_WR             = 0x1a,
 104         FW_ISCSI_TX_DATA_WR            = 0x45,
 105         FW_LASTC2E_WR                  = 0x70
 106 };
 107
 108 struct fw_wr_hdr {
 109         __be32 hi;
 110         __be32 lo;
 111 };
 112
 113 /* work request opcode (hi) */
 114 #define FW_WR_OP_S      24
 115 #define FW_WR_OP_M      0xff
 116 #define FW_WR_OP_V(x)   ((x) << FW_WR_OP_S)
 117 #define FW_WR_OP_G(x)   (((x) >> FW_WR_OP_S) & FW_WR_OP_M)
 118
 119 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */
 120 #define FW_WR_ATOMIC_S          23
 121 #define FW_WR_ATOMIC_V(x)       ((x) << FW_WR_ATOMIC_S)
 122
 123 /* flush flag (hi) - firmware flushes flushable work request buffered
 124  * in the flow context.
 125  */
 126 #define FW_WR_FLUSH_S     22
 127 #define FW_WR_FLUSH_V(x)  ((x) << FW_WR_FLUSH_S)
 128
 129 /* completion flag (hi) - firmware generates a cpl_fw6_ack */
 130 #define FW_WR_COMPL_S     21
 131 #define FW_WR_COMPL_V(x)  ((x) << FW_WR_COMPL_S)
 132 #define FW_WR_COMPL_F     FW_WR_COMPL_V(1U)
 133
 134 /* work request immediate data length (hi) */
 135 #define FW_WR_IMMDLEN_S 0
 136 #define FW_WR_IMMDLEN_M 0xff
 137 #define FW_WR_IMMDLEN_V(x)      ((x) << FW_WR_IMMDLEN_S)
 138
 139 /* egress queue status update to associated ingress queue entry (lo) */
 140 #define FW_WR_EQUIQ_S           31
 141 #define FW_WR_EQUIQ_V(x)        ((x) << FW_WR_EQUIQ_S)
 142 #define FW_WR_EQUIQ_F           FW_WR_EQUIQ_V(1U)
 143
 144 /* egress queue status update to egress queue status entry (lo) */
 145 #define FW_WR_EQUEQ_S           30
 146 #define FW_WR_EQUEQ_V(x)        ((x) << FW_WR_EQUEQ_S)
 147 #define FW_WR_EQUEQ_F           FW_WR_EQUEQ_V(1U)
 148
 149 /* flow context identifier (lo) */
 150 #define FW_WR_FLOWID_S          8
 151 #define FW_WR_FLOWID_V(x)       ((x) << FW_WR_FLOWID_S)
 152
 153 /* length in units of 16-bytes (lo) */
 154 #define FW_WR_LEN16_S           0
 155 #define FW_WR_LEN16_V(x)        ((x) << FW_WR_LEN16_S)
 156
 157 #define HW_TPL_FR_MT_PR_IV_P_FC         0X32B
 158 #define HW_TPL_FR_MT_PR_OV_P_FC         0X327
 159
 160 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
 161 enum fw_filter_wr_cookie {
 162         FW_FILTER_WR_SUCCESS,
 163         FW_FILTER_WR_FLT_ADDED,
 164         FW_FILTER_WR_FLT_DELETED,
 165         FW_FILTER_WR_SMT_TBL_FULL,
 166         FW_FILTER_WR_EINVAL,
 167 };
 168
 169 struct fw_filter_wr {
 170         __be32 op_pkd;
 171         __be32 len16_pkd;
 172         __be64 r3;
 173         __be32 tid_to_iq;
 174         __be32 del_filter_to_l2tix;
 175         __be16 ethtype;
 176         __be16 ethtypem;
 177         __u8   frag_to_ovlan_vldm;
 178         __u8   smac_sel;
 179         __be16 rx_chan_rx_rpl_iq;
 180         __be32 maci_to_matchtypem;
 181         __u8   ptcl;
 182         __u8   ptclm;
 183         __u8   ttyp;
 184         __u8   ttypm;
 185         __be16 ivlan;
 186         __be16 ivlanm;
 187         __be16 ovlan;
 188         __be16 ovlanm;
 189         __u8   lip[16];
 190         __u8   lipm[16];
 191         __u8   fip[16];
 192         __u8   fipm[16];
 193         __be16 lp;
 194         __be16 lpm;
 195         __be16 fp;
 196         __be16 fpm;
 197         __be16 r7;
 198         __u8   sma[6];
 199 };
 200
 201 #define FW_FILTER_WR_TID_S      12
 202 #define FW_FILTER_WR_TID_M      0xfffff
 203 #define FW_FILTER_WR_TID_V(x)   ((x) << FW_FILTER_WR_TID_S)
 204 #define FW_FILTER_WR_TID_G(x)   \
 205         (((x) >> FW_FILTER_WR_TID_S) & FW_FILTER_WR_TID_M)
 206
 207 #define FW_FILTER_WR_RQTYPE_S           11
 208 #define FW_FILTER_WR_RQTYPE_M           0x1
 209 #define FW_FILTER_WR_RQTYPE_V(x)        ((x) << FW_FILTER_WR_RQTYPE_S)
 210 #define FW_FILTER_WR_RQTYPE_G(x)        \
 211         (((x) >> FW_FILTER_WR_RQTYPE_S) & FW_FILTER_WR_RQTYPE_M)
 212 #define FW_FILTER_WR_RQTYPE_F   FW_FILTER_WR_RQTYPE_V(1U)
 213
 214 #define FW_FILTER_WR_NOREPLY_S          10
 215 #define FW_FILTER_WR_NOREPLY_M          0x1
 216 #define FW_FILTER_WR_NOREPLY_V(x)       ((x) << FW_FILTER_WR_NOREPLY_S)
 217 #define FW_FILTER_WR_NOREPLY_G(x)       \
 218         (((x) >> FW_FILTER_WR_NOREPLY_S) & FW_FILTER_WR_NOREPLY_M)
 219 #define FW_FILTER_WR_NOREPLY_F  FW_FILTER_WR_NOREPLY_V(1U)
 220
 221 #define FW_FILTER_WR_IQ_S       0
 222 #define FW_FILTER_WR_IQ_M       0x3ff
 223 #define FW_FILTER_WR_IQ_V(x)    ((x) << FW_FILTER_WR_IQ_S)
 224 #define FW_FILTER_WR_IQ_G(x)    \
 225         (((x) >> FW_FILTER_WR_IQ_S) & FW_FILTER_WR_IQ_M)
 226
 227 #define FW_FILTER_WR_DEL_FILTER_S       31
 228 #define FW_FILTER_WR_DEL_FILTER_M       0x1
 229 #define FW_FILTER_WR_DEL_FILTER_V(x)    ((x) << FW_FILTER_WR_DEL_FILTER_S)
 230 #define FW_FILTER_WR_DEL_FILTER_G(x)    \
 231         (((x) >> FW_FILTER_WR_DEL_FILTER_S) & FW_FILTER_WR_DEL_FILTER_M)
 232 #define FW_FILTER_WR_DEL_FILTER_F       FW_FILTER_WR_DEL_FILTER_V(1U)
 233
 234 #define FW_FILTER_WR_RPTTID_S           25
 235 #define FW_FILTER_WR_RPTTID_M           0x1
 236 #define FW_FILTER_WR_RPTTID_V(x)        ((x) << FW_FILTER_WR_RPTTID_S)
 237 #define FW_FILTER_WR_RPTTID_G(x)        \
 238         (((x) >> FW_FILTER_WR_RPTTID_S) & FW_FILTER_WR_RPTTID_M)
 239 #define FW_FILTER_WR_RPTTID_F   FW_FILTER_WR_RPTTID_V(1U)
 240
 241 #define FW_FILTER_WR_DROP_S     24
 242 #define FW_FILTER_WR_DROP_M     0x1
 243 #define FW_FILTER_WR_DROP_V(x)  ((x) << FW_FILTER_WR_DROP_S)
 244 #define FW_FILTER_WR_DROP_G(x)  \
 245         (((x) >> FW_FILTER_WR_DROP_S) & FW_FILTER_WR_DROP_M)
 246 #define FW_FILTER_WR_DROP_F     FW_FILTER_WR_DROP_V(1U)
 247
 248 #define FW_FILTER_WR_DIRSTEER_S         23
 249 #define FW_FILTER_WR_DIRSTEER_M         0x1
 250 #define FW_FILTER_WR_DIRSTEER_V(x)      ((x) << FW_FILTER_WR_DIRSTEER_S)
 251 #define FW_FILTER_WR_DIRSTEER_G(x)      \
 252         (((x) >> FW_FILTER_WR_DIRSTEER_S) & FW_FILTER_WR_DIRSTEER_M)
 253 #define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1U)
 254
 255 #define FW_FILTER_WR_MASKHASH_S         22
 256 #define FW_FILTER_WR_MASKHASH_M         0x1
 257 #define FW_FILTER_WR_MASKHASH_V(x)      ((x) << FW_FILTER_WR_MASKHASH_S)
 258 #define FW_FILTER_WR_MASKHASH_G(x)      \
 259         (((x) >> FW_FILTER_WR_MASKHASH_S) & FW_FILTER_WR_MASKHASH_M)
 260 #define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1U)
 261
 262 #define FW_FILTER_WR_DIRSTEERHASH_S     21
 263 #define FW_FILTER_WR_DIRSTEERHASH_M     0x1
 264 #define FW_FILTER_WR_DIRSTEERHASH_V(x)  ((x) << FW_FILTER_WR_DIRSTEERHASH_S)
 265 #define FW_FILTER_WR_DIRSTEERHASH_G(x)  \
 266         (((x) >> FW_FILTER_WR_DIRSTEERHASH_S) & FW_FILTER_WR_DIRSTEERHASH_M)
 267 #define FW_FILTER_WR_DIRSTEERHASH_F     FW_FILTER_WR_DIRSTEERHASH_V(1U)
 268
 269 #define FW_FILTER_WR_LPBK_S     20
 270 #define FW_FILTER_WR_LPBK_M     0x1
 271 #define FW_FILTER_WR_LPBK_V(x)  ((x) << FW_FILTER_WR_LPBK_S)
 272 #define FW_FILTER_WR_LPBK_G(x)  \
 273         (((x) >> FW_FILTER_WR_LPBK_S) & FW_FILTER_WR_LPBK_M)
 274 #define FW_FILTER_WR_LPBK_F     FW_FILTER_WR_LPBK_V(1U)
 275
 276 #define FW_FILTER_WR_DMAC_S     19
 277 #define FW_FILTER_WR_DMAC_M     0x1
 278 #define FW_FILTER_WR_DMAC_V(x)  ((x) << FW_FILTER_WR_DMAC_S)
 279 #define FW_FILTER_WR_DMAC_G(x)  \
 280         (((x) >> FW_FILTER_WR_DMAC_S) & FW_FILTER_WR_DMAC_M)
 281 #define FW_FILTER_WR_DMAC_F     FW_FILTER_WR_DMAC_V(1U)
 282
 283 #define FW_FILTER_WR_SMAC_S     18
 284 #define FW_FILTER_WR_SMAC_M     0x1
 285 #define FW_FILTER_WR_SMAC_V(x)  ((x) << FW_FILTER_WR_SMAC_S)
 286 #define FW_FILTER_WR_SMAC_G(x)  \
 287         (((x) >> FW_FILTER_WR_SMAC_S) & FW_FILTER_WR_SMAC_M)
 288 #define FW_FILTER_WR_SMAC_F     FW_FILTER_WR_SMAC_V(1U)
 289
 290 #define FW_FILTER_WR_INSVLAN_S          17
 291 #define FW_FILTER_WR_INSVLAN_M          0x1
 292 #define FW_FILTER_WR_INSVLAN_V(x)       ((x) << FW_FILTER_WR_INSVLAN_S)
 293 #define FW_FILTER_WR_INSVLAN_G(x)       \
 294         (((x) >> FW_FILTER_WR_INSVLAN_S) & FW_FILTER_WR_INSVLAN_M)
 295 #define FW_FILTER_WR_INSVLAN_F  FW_FILTER_WR_INSVLAN_V(1U)
 296
 297 #define FW_FILTER_WR_RMVLAN_S           16
 298 #define FW_FILTER_WR_RMVLAN_M           0x1
 299 #define FW_FILTER_WR_RMVLAN_V(x)        ((x) << FW_FILTER_WR_RMVLAN_S)
 300 #define FW_FILTER_WR_RMVLAN_G(x)        \
 301         (((x) >> FW_FILTER_WR_RMVLAN_S) & FW_FILTER_WR_RMVLAN_M)
 302 #define FW_FILTER_WR_RMVLAN_F   FW_FILTER_WR_RMVLAN_V(1U)
 303
 304 #define FW_FILTER_WR_HITCNTS_S          15
 305 #define FW_FILTER_WR_HITCNTS_M          0x1
 306 #define FW_FILTER_WR_HITCNTS_V(x)       ((x) << FW_FILTER_WR_HITCNTS_S)
 307 #define FW_FILTER_WR_HITCNTS_G(x)       \
 308         (((x) >> FW_FILTER_WR_HITCNTS_S) & FW_FILTER_WR_HITCNTS_M)
 309 #define FW_FILTER_WR_HITCNTS_F  FW_FILTER_WR_HITCNTS_V(1U)
 310
 311 #define FW_FILTER_WR_TXCHAN_S           13
 312 #define FW_FILTER_WR_TXCHAN_M           0x3
 313 #define FW_FILTER_WR_TXCHAN_V(x)        ((x) << FW_FILTER_WR_TXCHAN_S)
 314 #define FW_FILTER_WR_TXCHAN_G(x)        \
 315         (((x) >> FW_FILTER_WR_TXCHAN_S) & FW_FILTER_WR_TXCHAN_M)
 316
 317 #define FW_FILTER_WR_PRIO_S     12
 318 #define FW_FILTER_WR_PRIO_M     0x1
 319 #define FW_FILTER_WR_PRIO_V(x)  ((x) << FW_FILTER_WR_PRIO_S)
 320 #define FW_FILTER_WR_PRIO_G(x)  \
 321         (((x) >> FW_FILTER_WR_PRIO_S) & FW_FILTER_WR_PRIO_M)
 322 #define FW_FILTER_WR_PRIO_F     FW_FILTER_WR_PRIO_V(1U)
 323
 324 #define FW_FILTER_WR_L2TIX_S    0
 325 #define FW_FILTER_WR_L2TIX_M    0xfff
 326 #define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S)
 327 #define FW_FILTER_WR_L2TIX_G(x) \
 328         (((x) >> FW_FILTER_WR_L2TIX_S) & FW_FILTER_WR_L2TIX_M)
 329
 330 #define FW_FILTER_WR_FRAG_S     7
 331 #define FW_FILTER_WR_FRAG_M     0x1
 332 #define FW_FILTER_WR_FRAG_V(x)  ((x) << FW_FILTER_WR_FRAG_S)
 333 #define FW_FILTER_WR_FRAG_G(x)  \
 334         (((x) >> FW_FILTER_WR_FRAG_S) & FW_FILTER_WR_FRAG_M)
 335 #define FW_FILTER_WR_FRAG_F     FW_FILTER_WR_FRAG_V(1U)
 336
 337 #define FW_FILTER_WR_FRAGM_S    6
 338 #define FW_FILTER_WR_FRAGM_M    0x1
 339 #define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S)
 340 #define FW_FILTER_WR_FRAGM_G(x) \
 341         (((x) >> FW_FILTER_WR_FRAGM_S) & FW_FILTER_WR_FRAGM_M)
 342 #define FW_FILTER_WR_FRAGM_F    FW_FILTER_WR_FRAGM_V(1U)
 343
 344 #define FW_FILTER_WR_IVLAN_VLD_S        5
 345 #define FW_FILTER_WR_IVLAN_VLD_M        0x1
 346 #define FW_FILTER_WR_IVLAN_VLD_V(x)     ((x) << FW_FILTER_WR_IVLAN_VLD_S)
 347 #define FW_FILTER_WR_IVLAN_VLD_G(x)     \
 348         (((x) >> FW_FILTER_WR_IVLAN_VLD_S) & FW_FILTER_WR_IVLAN_VLD_M)
 349 #define FW_FILTER_WR_IVLAN_VLD_F        FW_FILTER_WR_IVLAN_VLD_V(1U)
 350
 351 #define FW_FILTER_WR_OVLAN_VLD_S        4
 352 #define FW_FILTER_WR_OVLAN_VLD_M        0x1
 353 #define FW_FILTER_WR_OVLAN_VLD_V(x)     ((x) << FW_FILTER_WR_OVLAN_VLD_S)
 354 #define FW_FILTER_WR_OVLAN_VLD_G(x)     \
 355         (((x) >> FW_FILTER_WR_OVLAN_VLD_S) & FW_FILTER_WR_OVLAN_VLD_M)
 356 #define FW_FILTER_WR_OVLAN_VLD_F        FW_FILTER_WR_OVLAN_VLD_V(1U)
 357
 358 #define FW_FILTER_WR_IVLAN_VLDM_S       3
 359 #define FW_FILTER_WR_IVLAN_VLDM_M       0x1
 360 #define FW_FILTER_WR_IVLAN_VLDM_V(x)    ((x) << FW_FILTER_WR_IVLAN_VLDM_S)
 361 #define FW_FILTER_WR_IVLAN_VLDM_G(x)    \
 362         (((x) >> FW_FILTER_WR_IVLAN_VLDM_S) & FW_FILTER_WR_IVLAN_VLDM_M)
 363 #define FW_FILTER_WR_IVLAN_VLDM_F       FW_FILTER_WR_IVLAN_VLDM_V(1U)
 364
 365 #define FW_FILTER_WR_OVLAN_VLDM_S       2
 366 #define FW_FILTER_WR_OVLAN_VLDM_M       0x1
 367 #define FW_FILTER_WR_OVLAN_VLDM_V(x)    ((x) << FW_FILTER_WR_OVLAN_VLDM_S)
 368 #define FW_FILTER_WR_OVLAN_VLDM_G(x)    \
 369         (((x) >> FW_FILTER_WR_OVLAN_VLDM_S) & FW_FILTER_WR_OVLAN_VLDM_M)
 370 #define FW_FILTER_WR_OVLAN_VLDM_F       FW_FILTER_WR_OVLAN_VLDM_V(1U)
 371
 372 #define FW_FILTER_WR_RX_CHAN_S          15
 373 #define FW_FILTER_WR_RX_CHAN_M          0x1
 374 #define FW_FILTER_WR_RX_CHAN_V(x)       ((x) << FW_FILTER_WR_RX_CHAN_S)
 375 #define FW_FILTER_WR_RX_CHAN_G(x)       \
 376         (((x) >> FW_FILTER_WR_RX_CHAN_S) & FW_FILTER_WR_RX_CHAN_M)
 377 #define FW_FILTER_WR_RX_CHAN_F  FW_FILTER_WR_RX_CHAN_V(1U)
 378
 379 #define FW_FILTER_WR_RX_RPL_IQ_S        0
 380 #define FW_FILTER_WR_RX_RPL_IQ_M        0x3ff
 381 #define FW_FILTER_WR_RX_RPL_IQ_V(x)     ((x) << FW_FILTER_WR_RX_RPL_IQ_S)
 382 #define FW_FILTER_WR_RX_RPL_IQ_G(x)     \
 383         (((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M)
 384
 385 #define FW_FILTER_WR_MACI_S     23
 386 #define FW_FILTER_WR_MACI_M     0x1ff
 387 #define FW_FILTER_WR_MACI_V(x)  ((x) << FW_FILTER_WR_MACI_S)
 388 #define FW_FILTER_WR_MACI_G(x)  \
 389         (((x) >> FW_FILTER_WR_MACI_S) & FW_FILTER_WR_MACI_M)
 390
 391 #define FW_FILTER_WR_MACIM_S    14
 392 #define FW_FILTER_WR_MACIM_M    0x1ff
 393 #define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S)
 394 #define FW_FILTER_WR_MACIM_G(x) \
 395         (((x) >> FW_FILTER_WR_MACIM_S) & FW_FILTER_WR_MACIM_M)
 396
 397 #define FW_FILTER_WR_FCOE_S     13
 398 #define FW_FILTER_WR_FCOE_M     0x1
 399 #define FW_FILTER_WR_FCOE_V(x)  ((x) << FW_FILTER_WR_FCOE_S)
 400 #define FW_FILTER_WR_FCOE_G(x)  \
 401         (((x) >> FW_FILTER_WR_FCOE_S) & FW_FILTER_WR_FCOE_M)
 402 #define FW_FILTER_WR_FCOE_F     FW_FILTER_WR_FCOE_V(1U)
 403
 404 #define FW_FILTER_WR_FCOEM_S    12
 405 #define FW_FILTER_WR_FCOEM_M    0x1
 406 #define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S)
 407 #define FW_FILTER_WR_FCOEM_G(x) \
 408         (((x) >> FW_FILTER_WR_FCOEM_S) & FW_FILTER_WR_FCOEM_M)
 409 #define FW_FILTER_WR_FCOEM_F    FW_FILTER_WR_FCOEM_V(1U)
 410
 411 #define FW_FILTER_WR_PORT_S     9
 412 #define FW_FILTER_WR_PORT_M     0x7
 413 #define FW_FILTER_WR_PORT_V(x)  ((x) << FW_FILTER_WR_PORT_S)
 414 #define FW_FILTER_WR_PORT_G(x)  \
 415         (((x) >> FW_FILTER_WR_PORT_S) & FW_FILTER_WR_PORT_M)
 416
 417 #define FW_FILTER_WR_PORTM_S    6
 418 #define FW_FILTER_WR_PORTM_M    0x7
 419 #define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S)
 420 #define FW_FILTER_WR_PORTM_G(x) \
 421         (((x) >> FW_FILTER_WR_PORTM_S) & FW_FILTER_WR_PORTM_M)
 422
 423 #define FW_FILTER_WR_MATCHTYPE_S        3
 424 #define FW_FILTER_WR_MATCHTYPE_M        0x7
 425 #define FW_FILTER_WR_MATCHTYPE_V(x)     ((x) << FW_FILTER_WR_MATCHTYPE_S)
 426 #define FW_FILTER_WR_MATCHTYPE_G(x)     \
 427         (((x) >> FW_FILTER_WR_MATCHTYPE_S) & FW_FILTER_WR_MATCHTYPE_M)
 428
 429 #define FW_FILTER_WR_MATCHTYPEM_S       0
 430 #define FW_FILTER_WR_MATCHTYPEM_M       0x7
 431 #define FW_FILTER_WR_MATCHTYPEM_V(x)    ((x) << FW_FILTER_WR_MATCHTYPEM_S)
 432 #define FW_FILTER_WR_MATCHTYPEM_G(x)    \
 433         (((x) >> FW_FILTER_WR_MATCHTYPEM_S) & FW_FILTER_WR_MATCHTYPEM_M)
 434
 435 struct fw_ulptx_wr {
 436         __be32 op_to_compl;
 437         __be32 flowid_len16;
 438         u64 cookie;
 439 };
 440
 441 struct fw_tp_wr {
 442         __be32 op_to_immdlen;
 443         __be32 flowid_len16;
 444         u64 cookie;
 445 };
 446
 447 struct fw_eth_tx_pkt_wr {
 448         __be32 op_immdlen;
 449         __be32 equiq_to_len16;
 450         __be64 r3;
 451 };
 452
 453 struct fw_ofld_connection_wr {
 454         __be32 op_compl;
 455         __be32 len16_pkd;
 456         __u64  cookie;
 457         __be64 r2;
 458         __be64 r3;
 459         struct fw_ofld_connection_le {
 460                 __be32 version_cpl;
 461                 __be32 filter;
 462                 __be32 r1;
 463                 __be16 lport;
 464                 __be16 pport;
 465                 union fw_ofld_connection_leip {
 466                         struct fw_ofld_connection_le_ipv4 {
 467                                 __be32 pip;
 468                                 __be32 lip;
 469                                 __be64 r0;
 470                                 __be64 r1;
 471                                 __be64 r2;
 472                         } ipv4;
 473                         struct fw_ofld_connection_le_ipv6 {
 474                                 __be64 pip_hi;
 475                                 __be64 pip_lo;
 476                                 __be64 lip_hi;
 477                                 __be64 lip_lo;
 478                         } ipv6;
 479                 } u;
 480         } le;
 481         struct fw_ofld_connection_tcb {
 482                 __be32 t_state_to_astid;
 483                 __be16 cplrxdataack_cplpassacceptrpl;
 484                 __be16 rcv_adv;
 485                 __be32 rcv_nxt;
 486                 __be32 tx_max;
 487                 __be64 opt0;
 488                 __be32 opt2;
 489                 __be32 r1;
 490                 __be64 r2;
 491                 __be64 r3;
 492         } tcb;
 493 };
 494
 495 #define FW_OFLD_CONNECTION_WR_VERSION_S                31
 496 #define FW_OFLD_CONNECTION_WR_VERSION_M                0x1
 497 #define FW_OFLD_CONNECTION_WR_VERSION_V(x)     \
 498         ((x) << FW_OFLD_CONNECTION_WR_VERSION_S)
 499 #define FW_OFLD_CONNECTION_WR_VERSION_G(x)     \
 500         (((x) >> FW_OFLD_CONNECTION_WR_VERSION_S) & \
 501         FW_OFLD_CONNECTION_WR_VERSION_M)
 502 #define FW_OFLD_CONNECTION_WR_VERSION_F        \
 503         FW_OFLD_CONNECTION_WR_VERSION_V(1U)
 504
 505 #define FW_OFLD_CONNECTION_WR_CPL_S    30
 506 #define FW_OFLD_CONNECTION_WR_CPL_M    0x1
 507 #define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S)
 508 #define FW_OFLD_CONNECTION_WR_CPL_G(x) \
 509         (((x) >> FW_OFLD_CONNECTION_WR_CPL_S) & FW_OFLD_CONNECTION_WR_CPL_M)
 510 #define FW_OFLD_CONNECTION_WR_CPL_F    FW_OFLD_CONNECTION_WR_CPL_V(1U)
 511
 512 #define FW_OFLD_CONNECTION_WR_T_STATE_S                28
 513 #define FW_OFLD_CONNECTION_WR_T_STATE_M                0xf
 514 #define FW_OFLD_CONNECTION_WR_T_STATE_V(x)     \
 515         ((x) << FW_OFLD_CONNECTION_WR_T_STATE_S)
 516 #define FW_OFLD_CONNECTION_WR_T_STATE_G(x)     \
 517         (((x) >> FW_OFLD_CONNECTION_WR_T_STATE_S) & \
 518         FW_OFLD_CONNECTION_WR_T_STATE_M)
 519
 520 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_S      24
 521 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_M      0xf
 522 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x)   \
 523         ((x) << FW_OFLD_CONNECTION_WR_RCV_SCALE_S)
 524 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x)   \
 525         (((x) >> FW_OFLD_CONNECTION_WR_RCV_SCALE_S) & \
 526         FW_OFLD_CONNECTION_WR_RCV_SCALE_M)
 527
 528 #define FW_OFLD_CONNECTION_WR_ASTID_S          0
 529 #define FW_OFLD_CONNECTION_WR_ASTID_M          0xffffff
 530 #define FW_OFLD_CONNECTION_WR_ASTID_V(x)       \
 531         ((x) << FW_OFLD_CONNECTION_WR_ASTID_S)
 532 #define FW_OFLD_CONNECTION_WR_ASTID_G(x)       \
 533         (((x) >> FW_OFLD_CONNECTION_WR_ASTID_S) & FW_OFLD_CONNECTION_WR_ASTID_M)
 534
 535 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S   15
 536 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M   0x1
 537 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x)        \
 538         ((x) << FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S)
 539 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x)        \
 540         (((x) >> FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) & \
 541         FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M)
 542 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F   \
 543         FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(1U)
 544
 545 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S       14
 546 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M       0x1
 547 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x)    \
 548         ((x) << FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S)
 549 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x)    \
 550         (((x) >> FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) & \
 551         FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M)
 552 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F       \
 553         FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(1U)
 554
 555 enum fw_flowc_mnem {
 556         FW_FLOWC_MNEM_PFNVFN,           /* PFN [15:8] VFN [7:0] */
 557         FW_FLOWC_MNEM_CH,
 558         FW_FLOWC_MNEM_PORT,
 559         FW_FLOWC_MNEM_IQID,
 560         FW_FLOWC_MNEM_SNDNXT,
 561         FW_FLOWC_MNEM_RCVNXT,
 562         FW_FLOWC_MNEM_SNDBUF,
 563         FW_FLOWC_MNEM_MSS,
 564         FW_FLOWC_MNEM_TXDATAPLEN_MAX,
 565         FW_FLOWC_MNEM_TCPSTATE,
 566         FW_FLOWC_MNEM_EOSTATE,
 567         FW_FLOWC_MNEM_SCHEDCLASS,
 568         FW_FLOWC_MNEM_DCBPRIO,
 569         FW_FLOWC_MNEM_SND_SCALE,
 570         FW_FLOWC_MNEM_RCV_SCALE,
 571 };
 572
 573 struct fw_flowc_mnemval {
 574         u8 mnemonic;
 575         u8 r4[3];
 576         __be32 val;
 577 };
 578
 579 struct fw_flowc_wr {
 580         __be32 op_to_nparams;
 581         __be32 flowid_len16;
 582         struct fw_flowc_mnemval mnemval[0];
 583 };
 584
 585 #define FW_FLOWC_WR_NPARAMS_S           0
 586 #define FW_FLOWC_WR_NPARAMS_V(x)        ((x) << FW_FLOWC_WR_NPARAMS_S)
 587
 588 struct fw_ofld_tx_data_wr {
 589         __be32 op_to_immdlen;
 590         __be32 flowid_len16;
 591         __be32 plen;
 592         __be32 tunnel_to_proxy;
 593 };
 594
 595 #define FW_OFLD_TX_DATA_WR_TUNNEL_S     19
 596 #define FW_OFLD_TX_DATA_WR_TUNNEL_V(x)  ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S)
 597
 598 #define FW_OFLD_TX_DATA_WR_SAVE_S       18
 599 #define FW_OFLD_TX_DATA_WR_SAVE_V(x)    ((x) << FW_OFLD_TX_DATA_WR_SAVE_S)
 600
 601 #define FW_OFLD_TX_DATA_WR_FLUSH_S      17
 602 #define FW_OFLD_TX_DATA_WR_FLUSH_V(x)   ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S)
 603 #define FW_OFLD_TX_DATA_WR_FLUSH_F      FW_OFLD_TX_DATA_WR_FLUSH_V(1U)
 604
 605 #define FW_OFLD_TX_DATA_WR_URGENT_S     16
 606 #define FW_OFLD_TX_DATA_WR_URGENT_V(x)  ((x) << FW_OFLD_TX_DATA_WR_URGENT_S)
 607
 608 #define FW_OFLD_TX_DATA_WR_MORE_S       15
 609 #define FW_OFLD_TX_DATA_WR_MORE_V(x)    ((x) << FW_OFLD_TX_DATA_WR_MORE_S)
 610
 611 #define FW_OFLD_TX_DATA_WR_SHOVE_S      14
 612 #define FW_OFLD_TX_DATA_WR_SHOVE_V(x)   ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S)
 613 #define FW_OFLD_TX_DATA_WR_SHOVE_F      FW_OFLD_TX_DATA_WR_SHOVE_V(1U)
 614
 615 #define FW_OFLD_TX_DATA_WR_ULPMODE_S    10
 616 #define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S)
 617
 618 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S         6
 619 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x)      \
 620         ((x) << FW_OFLD_TX_DATA_WR_ULPSUBMODE_S)
 621
 622 struct fw_cmd_wr {
 623         __be32 op_dma;
 624         __be32 len16_pkd;
 625         __be64 cookie_daddr;
 626 };
 627
 628 #define FW_CMD_WR_DMA_S         17
 629 #define FW_CMD_WR_DMA_V(x)      ((x) << FW_CMD_WR_DMA_S)
 630
 631 struct fw_eth_tx_pkt_vm_wr {
 632         __be32 op_immdlen;
 633         __be32 equiq_to_len16;
 634         __be32 r3[2];
 635         u8 ethmacdst[6];
 636         u8 ethmacsrc[6];
 637         __be16 ethtype;
 638         __be16 vlantci;
 639 };
 640
 641 #define FW_CMD_MAX_TIMEOUT 10000
 642
 643 /*
 644  * If a host driver does a HELLO and discovers that there's already a MASTER
 645  * selected, we may have to wait for that MASTER to finish issuing RESET,
 646  * configuration and INITIALIZE commands.  Also, there's a possibility that
 647  * our own HELLO may get lost if it happens right as the MASTER is issuign a
 648  * RESET command, so we need to be willing to make a few retries of our HELLO.
 649  */
 650 #define FW_CMD_HELLO_TIMEOUT    (3 * FW_CMD_MAX_TIMEOUT)
 651 #define FW_CMD_HELLO_RETRIES    3
 652
 653
 654 enum fw_cmd_opcodes {
 655         FW_LDST_CMD                    = 0x01,
 656         FW_RESET_CMD                   = 0x03,
 657         FW_HELLO_CMD                   = 0x04,
 658         FW_BYE_CMD                     = 0x05,
 659         FW_INITIALIZE_CMD              = 0x06,
 660         FW_CAPS_CONFIG_CMD             = 0x07,
 661         FW_PARAMS_CMD                  = 0x08,
 662         FW_PFVF_CMD                    = 0x09,
 663         FW_IQ_CMD                      = 0x10,
 664         FW_EQ_MNGT_CMD                 = 0x11,
 665         FW_EQ_ETH_CMD                  = 0x12,
 666         FW_EQ_CTRL_CMD                 = 0x13,
 667         FW_EQ_OFLD_CMD                 = 0x21,
 668         FW_VI_CMD                      = 0x14,
 669         FW_VI_MAC_CMD                  = 0x15,
 670         FW_VI_RXMODE_CMD               = 0x16,
 671         FW_VI_ENABLE_CMD               = 0x17,
 672         FW_ACL_MAC_CMD                 = 0x18,
 673         FW_ACL_VLAN_CMD                = 0x19,
 674         FW_VI_STATS_CMD                = 0x1a,
 675         FW_PORT_CMD                    = 0x1b,
 676         FW_PORT_STATS_CMD              = 0x1c,
 677         FW_PORT_LB_STATS_CMD           = 0x1d,
 678         FW_PORT_TRACE_CMD              = 0x1e,
 679         FW_PORT_TRACE_MMAP_CMD         = 0x1f,
 680         FW_RSS_IND_TBL_CMD             = 0x20,
 681         FW_RSS_GLB_CONFIG_CMD          = 0x22,
 682         FW_RSS_VI_CONFIG_CMD           = 0x23,
 683         FW_DEVLOG_CMD                  = 0x25,
 684         FW_CLIP_CMD                    = 0x28,
 685         FW_LASTC2E_CMD                 = 0x40,
 686         FW_ERROR_CMD                   = 0x80,
 687         FW_DEBUG_CMD                   = 0x81,
 688 };
 689
 690 enum fw_cmd_cap {
 691         FW_CMD_CAP_PF                  = 0x01,
 692         FW_CMD_CAP_DMAQ                = 0x02,
 693         FW_CMD_CAP_PORT                = 0x04,
 694         FW_CMD_CAP_PORTPROMISC         = 0x08,
 695         FW_CMD_CAP_PORTSTATS           = 0x10,
 696         FW_CMD_CAP_VF                  = 0x80,
 697 };
 698
 699 /*
 700  * Generic command header flit0
 701  */
 702 struct fw_cmd_hdr {
 703         __be32 hi;
 704         __be32 lo;
 705 };
 706
 707 #define FW_CMD_OP_S             24
 708 #define FW_CMD_OP_M             0xff
 709 #define FW_CMD_OP_V(x)          ((x) << FW_CMD_OP_S)
 710 #define FW_CMD_OP_G(x)          (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M)
 711
 712 #define FW_CMD_REQUEST_S        23
 713 #define FW_CMD_REQUEST_V(x)     ((x) << FW_CMD_REQUEST_S)
 714 #define FW_CMD_REQUEST_F        FW_CMD_REQUEST_V(1U)
 715
 716 #define FW_CMD_READ_S           22
 717 #define FW_CMD_READ_V(x)        ((x) << FW_CMD_READ_S)
 718 #define FW_CMD_READ_F           FW_CMD_READ_V(1U)
 719
 720 #define FW_CMD_WRITE_S          21
 721 #define FW_CMD_WRITE_V(x)       ((x) << FW_CMD_WRITE_S)
 722 #define FW_CMD_WRITE_F          FW_CMD_WRITE_V(1U)
 723
 724 #define FW_CMD_EXEC_S           20
 725 #define FW_CMD_EXEC_V(x)        ((x) << FW_CMD_EXEC_S)
 726 #define FW_CMD_EXEC_F           FW_CMD_EXEC_V(1U)
 727
 728 #define FW_CMD_RAMASK_S         20
 729 #define FW_CMD_RAMASK_V(x)      ((x) << FW_CMD_RAMASK_S)
 730
 731 #define FW_CMD_RETVAL_S         8
 732 #define FW_CMD_RETVAL_M         0xff
 733 #define FW_CMD_RETVAL_V(x)      ((x) << FW_CMD_RETVAL_S)
 734 #define FW_CMD_RETVAL_G(x)      (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M)
 735
 736 #define FW_CMD_LEN16_S          0
 737 #define FW_CMD_LEN16_V(x)       ((x) << FW_CMD_LEN16_S)
 738
 739 #define FW_LEN16(fw_struct)     FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
 740
 741 enum fw_ldst_addrspc {
 742         FW_LDST_ADDRSPC_FIRMWARE  = 0x0001,
 743         FW_LDST_ADDRSPC_SGE_EGRC  = 0x0008,
 744         FW_LDST_ADDRSPC_SGE_INGC  = 0x0009,
 745         FW_LDST_ADDRSPC_SGE_FLMC  = 0x000a,
 746         FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
 747         FW_LDST_ADDRSPC_TP_PIO    = 0x0010,
 748         FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
 749         FW_LDST_ADDRSPC_TP_MIB    = 0x0012,
 750         FW_LDST_ADDRSPC_MDIO      = 0x0018,
 751         FW_LDST_ADDRSPC_MPS       = 0x0020,
 752         FW_LDST_ADDRSPC_FUNC      = 0x0028,
 753         FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
 754 };
 755
 756 enum fw_ldst_mps_fid {
 757         FW_LDST_MPS_ATRB,
 758         FW_LDST_MPS_RPLC
 759 };
 760
 761 enum fw_ldst_func_access_ctl {
 762         FW_LDST_FUNC_ACC_CTL_VIID,
 763         FW_LDST_FUNC_ACC_CTL_FID
 764 };
 765
 766 enum fw_ldst_func_mod_index {
 767         FW_LDST_FUNC_MPS
 768 };
 769
 770 struct fw_ldst_cmd {
 771         __be32 op_to_addrspace;
 772         __be32 cycles_to_len16;
 773         union fw_ldst {
 774                 struct fw_ldst_addrval {
 775                         __be32 addr;
 776                         __be32 val;
 777                 } addrval;
 778                 struct fw_ldst_idctxt {
 779                         __be32 physid;
 780                         __be32 msg_ctxtflush;
 781                         __be32 ctxt_data7;
 782                         __be32 ctxt_data6;
 783                         __be32 ctxt_data5;
 784                         __be32 ctxt_data4;
 785                         __be32 ctxt_data3;
 786                         __be32 ctxt_data2;
 787                         __be32 ctxt_data1;
 788                         __be32 ctxt_data0;
 789                 } idctxt;
 790                 struct fw_ldst_mdio {
 791                         __be16 paddr_mmd;
 792                         __be16 raddr;
 793                         __be16 vctl;
 794                         __be16 rval;
 795                 } mdio;
 796                 struct fw_ldst_cim_rq {
 797                         u8 req_first64[8];
 798                         u8 req_second64[8];
 799                         u8 resp_first64[8];
 800                         u8 resp_second64[8];
 801                         __be32 r3[2];
 802                 } cim_rq;
 803                 union fw_ldst_mps {
 804                         struct fw_ldst_mps_rplc {
 805                                 __be16 fid_idx;
 806                                 __be16 rplcpf_pkd;
 807                                 __be32 rplc255_224;
 808                                 __be32 rplc223_192;
 809                                 __be32 rplc191_160;
 810                                 __be32 rplc159_128;
 811                                 __be32 rplc127_96;
 812                                 __be32 rplc95_64;
 813                                 __be32 rplc63_32;
 814                                 __be32 rplc31_0;
 815                         } rplc;
 816                         struct fw_ldst_mps_atrb {
 817                                 __be16 fid_mpsid;
 818                                 __be16 r2[3];
 819                                 __be32 r3[2];
 820                                 __be32 r4;
 821                                 __be32 atrb;
 822                                 __be16 vlan[16];
 823                         } atrb;
 824                 } mps;
 825                 struct fw_ldst_func {
 826                         u8 access_ctl;
 827                         u8 mod_index;
 828                         __be16 ctl_id;
 829                         __be32 offset;
 830                         __be64 data0;
 831                         __be64 data1;
 832                 } func;
 833                 struct fw_ldst_pcie {
 834                         u8 ctrl_to_fn;
 835                         u8 bnum;
 836                         u8 r;
 837                         u8 ext_r;
 838                         u8 select_naccess;
 839                         u8 pcie_fn;
 840                         __be16 nset_pkd;
 841                         __be32 data[12];
 842                 } pcie;
 843                 struct fw_ldst_i2c_deprecated {
 844                         u8 pid_pkd;
 845                         u8 base;
 846                         u8 boffset;
 847                         u8 data;
 848                         __be32 r9;
 849                 } i2c_deprecated;
 850                 struct fw_ldst_i2c {
 851                         u8 pid;
 852                         u8 did;
 853                         u8 boffset;
 854                         u8 blen;
 855                         __be32 r9;
 856                         __u8   data[48];
 857                 } i2c;
 858                 struct fw_ldst_le {
 859                         __be32 index;
 860                         __be32 r9;
 861                         u8 val[33];
 862                         u8 r11[7];
 863                 } le;
 864         } u;
 865 };
 866
 867 #define FW_LDST_CMD_ADDRSPACE_S         0
 868 #define FW_LDST_CMD_ADDRSPACE_V(x)      ((x) << FW_LDST_CMD_ADDRSPACE_S)
 869
 870 #define FW_LDST_CMD_MSG_S       31
 871 #define FW_LDST_CMD_MSG_V(x)    ((x) << FW_LDST_CMD_MSG_S)
 872
 873 #define FW_LDST_CMD_CTXTFLUSH_S         30
 874 #define FW_LDST_CMD_CTXTFLUSH_V(x)      ((x) << FW_LDST_CMD_CTXTFLUSH_S)
 875 #define FW_LDST_CMD_CTXTFLUSH_F         FW_LDST_CMD_CTXTFLUSH_V(1U)
 876
 877 #define FW_LDST_CMD_PADDR_S     8
 878 #define FW_LDST_CMD_PADDR_V(x)  ((x) << FW_LDST_CMD_PADDR_S)
 879
 880 #define FW_LDST_CMD_MMD_S       0
 881 #define FW_LDST_CMD_MMD_V(x)    ((x) << FW_LDST_CMD_MMD_S)
 882
 883 #define FW_LDST_CMD_FID_S       15
 884 #define FW_LDST_CMD_FID_V(x)    ((x) << FW_LDST_CMD_FID_S)
 885
 886 #define FW_LDST_CMD_IDX_S       0
 887 #define FW_LDST_CMD_IDX_V(x)    ((x) << FW_LDST_CMD_IDX_S)
 888
 889 #define FW_LDST_CMD_RPLCPF_S    0
 890 #define FW_LDST_CMD_RPLCPF_V(x) ((x) << FW_LDST_CMD_RPLCPF_S)
 891
 892 #define FW_LDST_CMD_LC_S        4
 893 #define FW_LDST_CMD_LC_V(x)     ((x) << FW_LDST_CMD_LC_S)
 894 #define FW_LDST_CMD_LC_F        FW_LDST_CMD_LC_V(1U)
 895
 896 #define FW_LDST_CMD_FN_S        0
 897 #define FW_LDST_CMD_FN_V(x)     ((x) << FW_LDST_CMD_FN_S)
 898
 899 #define FW_LDST_CMD_NACCESS_S           0
 900 #define FW_LDST_CMD_NACCESS_V(x)        ((x) << FW_LDST_CMD_NACCESS_S)
 901
 902 struct fw_reset_cmd {
 903         __be32 op_to_write;
 904         __be32 retval_len16;
 905         __be32 val;
 906         __be32 halt_pkd;
 907 };
 908
 909 #define FW_RESET_CMD_HALT_S     31
 910 #define FW_RESET_CMD_HALT_M     0x1
 911 #define FW_RESET_CMD_HALT_V(x)  ((x) << FW_RESET_CMD_HALT_S)
 912 #define FW_RESET_CMD_HALT_G(x)  \
 913         (((x) >> FW_RESET_CMD_HALT_S) & FW_RESET_CMD_HALT_M)
 914 #define FW_RESET_CMD_HALT_F     FW_RESET_CMD_HALT_V(1U)
 915
 916 enum fw_hellow_cmd {
 917         fw_hello_cmd_stage_os           = 0x0
 918 };
 919
 920 struct fw_hello_cmd {
 921         __be32 op_to_write;
 922         __be32 retval_len16;
 923         __be32 err_to_clearinit;
 924         __be32 fwrev;
 925 };
 926
 927 #define FW_HELLO_CMD_ERR_S      31
 928 #define FW_HELLO_CMD_ERR_V(x)   ((x) << FW_HELLO_CMD_ERR_S)
 929 #define FW_HELLO_CMD_ERR_F      FW_HELLO_CMD_ERR_V(1U)
 930
 931 #define FW_HELLO_CMD_INIT_S     30
 932 #define FW_HELLO_CMD_INIT_V(x)  ((x) << FW_HELLO_CMD_INIT_S)
 933 #define FW_HELLO_CMD_INIT_F     FW_HELLO_CMD_INIT_V(1U)
 934
 935 #define FW_HELLO_CMD_MASTERDIS_S        29
 936 #define FW_HELLO_CMD_MASTERDIS_V(x)     ((x) << FW_HELLO_CMD_MASTERDIS_S)
 937
 938 #define FW_HELLO_CMD_MASTERFORCE_S      28
 939 #define FW_HELLO_CMD_MASTERFORCE_V(x)   ((x) << FW_HELLO_CMD_MASTERFORCE_S)
 940
 941 #define FW_HELLO_CMD_MBMASTER_S         24
 942 #define FW_HELLO_CMD_MBMASTER_M         0xfU
 943 #define FW_HELLO_CMD_MBMASTER_V(x)      ((x) << FW_HELLO_CMD_MBMASTER_S)
 944 #define FW_HELLO_CMD_MBMASTER_G(x)      \
 945         (((x) >> FW_HELLO_CMD_MBMASTER_S) & FW_HELLO_CMD_MBMASTER_M)
 946
 947 #define FW_HELLO_CMD_MBASYNCNOTINT_S    23
 948 #define FW_HELLO_CMD_MBASYNCNOTINT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOTINT_S)
 949
 950 #define FW_HELLO_CMD_MBASYNCNOT_S       20
 951 #define FW_HELLO_CMD_MBASYNCNOT_V(x)    ((x) << FW_HELLO_CMD_MBASYNCNOT_S)
 952
 953 #define FW_HELLO_CMD_STAGE_S            17
 954 #define FW_HELLO_CMD_STAGE_V(x)         ((x) << FW_HELLO_CMD_STAGE_S)
 955
 956 #define FW_HELLO_CMD_CLEARINIT_S        16
 957 #define FW_HELLO_CMD_CLEARINIT_V(x)     ((x) << FW_HELLO_CMD_CLEARINIT_S)
 958 #define FW_HELLO_CMD_CLEARINIT_F        FW_HELLO_CMD_CLEARINIT_V(1U)
 959
 960 struct fw_bye_cmd {
 961         __be32 op_to_write;
 962         __be32 retval_len16;
 963         __be64 r3;
 964 };
 965
 966 struct fw_initialize_cmd {
 967         __be32 op_to_write;
 968         __be32 retval_len16;
 969         __be64 r3;
 970 };
 971
 972 enum fw_caps_config_hm {
 973         FW_CAPS_CONFIG_HM_PCIE          = 0x00000001,
 974         FW_CAPS_CONFIG_HM_PL            = 0x00000002,
 975         FW_CAPS_CONFIG_HM_SGE           = 0x00000004,
 976         FW_CAPS_CONFIG_HM_CIM           = 0x00000008,
 977         FW_CAPS_CONFIG_HM_ULPTX         = 0x00000010,
 978         FW_CAPS_CONFIG_HM_TP            = 0x00000020,
 979         FW_CAPS_CONFIG_HM_ULPRX         = 0x00000040,
 980         FW_CAPS_CONFIG_HM_PMRX          = 0x00000080,
 981         FW_CAPS_CONFIG_HM_PMTX          = 0x00000100,
 982         FW_CAPS_CONFIG_HM_MC            = 0x00000200,
 983         FW_CAPS_CONFIG_HM_LE            = 0x00000400,
 984         FW_CAPS_CONFIG_HM_MPS           = 0x00000800,
 985         FW_CAPS_CONFIG_HM_XGMAC         = 0x00001000,
 986         FW_CAPS_CONFIG_HM_CPLSWITCH     = 0x00002000,
 987         FW_CAPS_CONFIG_HM_T4DBG         = 0x00004000,
 988         FW_CAPS_CONFIG_HM_MI            = 0x00008000,
 989         FW_CAPS_CONFIG_HM_I2CM          = 0x00010000,
 990         FW_CAPS_CONFIG_HM_NCSI          = 0x00020000,
 991         FW_CAPS_CONFIG_HM_SMB           = 0x00040000,
 992         FW_CAPS_CONFIG_HM_MA            = 0x00080000,
 993         FW_CAPS_CONFIG_HM_EDRAM         = 0x00100000,
 994         FW_CAPS_CONFIG_HM_PMU           = 0x00200000,
 995         FW_CAPS_CONFIG_HM_UART          = 0x00400000,
 996         FW_CAPS_CONFIG_HM_SF            = 0x00800000,
 997 };
 998
 999 enum fw_caps_config_nbm {
1000         FW_CAPS_CONFIG_NBM_IPMI         = 0x00000001,
1001         FW_CAPS_CONFIG_NBM_NCSI         = 0x00000002,
1002 };
1003
1004 enum fw_caps_config_link {
1005         FW_CAPS_CONFIG_LINK_PPP         = 0x00000001,
1006         FW_CAPS_CONFIG_LINK_QFC         = 0x00000002,
1007         FW_CAPS_CONFIG_LINK_DCBX        = 0x00000004,
1008 };
1009
1010 enum fw_caps_config_switch {
1011         FW_CAPS_CONFIG_SWITCH_INGRESS   = 0x00000001,
1012         FW_CAPS_CONFIG_SWITCH_EGRESS    = 0x00000002,
1013 };
1014
1015 enum fw_caps_config_nic {
1016         FW_CAPS_CONFIG_NIC              = 0x00000001,
1017         FW_CAPS_CONFIG_NIC_VM           = 0x00000002,
1018 };
1019
1020 enum fw_caps_config_ofld {
1021         FW_CAPS_CONFIG_OFLD             = 0x00000001,
1022 };
1023
1024 enum fw_caps_config_rdma {
1025         FW_CAPS_CONFIG_RDMA_RDDP        = 0x00000001,
1026         FW_CAPS_CONFIG_RDMA_RDMAC       = 0x00000002,
1027 };
1028
1029 enum fw_caps_config_iscsi {
1030         FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
1031         FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
1032         FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
1033         FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
1034 };
1035
1036 enum fw_caps_config_fcoe {
1037         FW_CAPS_CONFIG_FCOE_INITIATOR   = 0x00000001,
1038         FW_CAPS_CONFIG_FCOE_TARGET      = 0x00000002,
1039         FW_CAPS_CONFIG_FCOE_CTRL_OFLD   = 0x00000004,
1040 };
1041
1042 enum fw_memtype_cf {
1043         FW_MEMTYPE_CF_EDC0              = 0x0,
1044         FW_MEMTYPE_CF_EDC1              = 0x1,
1045         FW_MEMTYPE_CF_EXTMEM            = 0x2,
1046         FW_MEMTYPE_CF_FLASH             = 0x4,
1047         FW_MEMTYPE_CF_INTERNAL          = 0x5,
1048         FW_MEMTYPE_CF_EXTMEM1           = 0x6,
1049 };
1050
1051 struct fw_caps_config_cmd {
1052         __be32 op_to_write;
1053         __be32 cfvalid_to_len16;
1054         __be32 r2;
1055         __be32 hwmbitmap;
1056         __be16 nbmcaps;
1057         __be16 linkcaps;
1058         __be16 switchcaps;
1059         __be16 r3;
1060         __be16 niccaps;
1061         __be16 ofldcaps;
1062         __be16 rdmacaps;
1063         __be16 r4;
1064         __be16 iscsicaps;
1065         __be16 fcoecaps;
1066         __be32 cfcsum;
1067         __be32 finiver;
1068         __be32 finicsum;
1069 };
1070
1071 #define FW_CAPS_CONFIG_CMD_CFVALID_S    27
1072 #define FW_CAPS_CONFIG_CMD_CFVALID_V(x) ((x) << FW_CAPS_CONFIG_CMD_CFVALID_S)
1073 #define FW_CAPS_CONFIG_CMD_CFVALID_F    FW_CAPS_CONFIG_CMD_CFVALID_V(1U)
1074
1075 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S         24
1076 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(x)      \
1077         ((x) << FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S)
1078
1079 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S      16
1080 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(x)   \
1081         ((x) << FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S)
1082
1083 /*
1084  * params command mnemonics
1085  */
1086 enum fw_params_mnem {
1087         FW_PARAMS_MNEM_DEV              = 1,    /* device params */
1088         FW_PARAMS_MNEM_PFVF             = 2,    /* function params */
1089         FW_PARAMS_MNEM_REG              = 3,    /* limited register access */
1090         FW_PARAMS_MNEM_DMAQ             = 4,    /* dma queue params */
1091         FW_PARAMS_MNEM_CHNET            = 5,    /* chnet params */
1092         FW_PARAMS_MNEM_LAST
1093 };
1094
1095 /*
1096  * device parameters
1097  */
1098 enum fw_params_param_dev {
1099         FW_PARAMS_PARAM_DEV_CCLK        = 0x00, /* chip core clock in khz */
1100         FW_PARAMS_PARAM_DEV_PORTVEC     = 0x01, /* the port vector */
1101         FW_PARAMS_PARAM_DEV_NTID        = 0x02, /* reads the number of TIDs
1102                                                  * allocated by the device's
1103                                                  * Lookup Engine
1104                                                  */
1105         FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
1106         FW_PARAMS_PARAM_DEV_INTVER_NIC  = 0x04,
1107         FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05,
1108         FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06,
1109         FW_PARAMS_PARAM_DEV_INTVER_RI   = 0x07,
1110         FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08,
1111         FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09,
1112         FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A,
1113         FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
1114         FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
1115         FW_PARAMS_PARAM_DEV_CF = 0x0D,
1116         FW_PARAMS_PARAM_DEV_PHYFW = 0x0F,
1117         FW_PARAMS_PARAM_DEV_DIAG = 0x11,
1118         FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD */
1119         FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER = 0x14, /* max supported adap IRD */
1120         FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
1121         FW_PARAMS_PARAM_DEV_FWCACHE = 0x18,
1122 };
1123
1124 /*
1125  * physical and virtual function parameters
1126  */
1127 enum fw_params_param_pfvf {
1128         FW_PARAMS_PARAM_PFVF_RWXCAPS    = 0x00,
1129         FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
1130         FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
1131         FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
1132         FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
1133         FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
1134         FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
1135         FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
1136         FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
1137         FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
1138         FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
1139         FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
1140         FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
1141         FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
1142         FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
1143         FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
1144         FW_PARAMS_PARAM_PFVF_RQ_END     = 0x10,
1145         FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
1146         FW_PARAMS_PARAM_PFVF_PBL_END    = 0x12,
1147         FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
1148         FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
1149         FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
1150         FW_PARAMS_PARAM_PFVF_SQRQ_END   = 0x16,
1151         FW_PARAMS_PARAM_PFVF_CQ_START   = 0x17,
1152         FW_PARAMS_PARAM_PFVF_CQ_END     = 0x18,
1153         FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
1154         FW_PARAMS_PARAM_PFVF_VIID       = 0x24,
1155         FW_PARAMS_PARAM_PFVF_CPMASK     = 0x25,
1156         FW_PARAMS_PARAM_PFVF_OCQ_START  = 0x26,
1157         FW_PARAMS_PARAM_PFVF_OCQ_END    = 0x27,
1158         FW_PARAMS_PARAM_PFVF_CONM_MAP   = 0x28,
1159         FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
1160         FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
1161         FW_PARAMS_PARAM_PFVF_EQ_START   = 0x2B,
1162         FW_PARAMS_PARAM_PFVF_EQ_END     = 0x2C,
1163         FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
1164         FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
1165         FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
1166         FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31
1167 };
1168
1169 /*
1170  * dma queue parameters
1171  */
1172 enum fw_params_param_dmaq {
1173         FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
1174         FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
1175         FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
1176         FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
1177         FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
1178         FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
1179         FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
1180 };
1181
1182 enum fw_params_param_dev_phyfw {
1183         FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00,
1184         FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01,
1185 };
1186
1187 enum fw_params_param_dev_diag {
1188         FW_PARAM_DEV_DIAG_TMP           = 0x00,
1189         FW_PARAM_DEV_DIAG_VDD           = 0x01,
1190 };
1191
1192 enum fw_params_param_dev_fwcache {
1193         FW_PARAM_DEV_FWCACHE_FLUSH      = 0x00,
1194         FW_PARAM_DEV_FWCACHE_FLUSHINV   = 0x01,
1195 };
1196
1197 #define FW_PARAMS_MNEM_S        24
1198 #define FW_PARAMS_MNEM_V(x)     ((x) << FW_PARAMS_MNEM_S)
1199
1200 #define FW_PARAMS_PARAM_X_S     16
1201 #define FW_PARAMS_PARAM_X_V(x)  ((x) << FW_PARAMS_PARAM_X_S)
1202
1203 #define FW_PARAMS_PARAM_Y_S     8
1204 #define FW_PARAMS_PARAM_Y_M     0xffU
1205 #define FW_PARAMS_PARAM_Y_V(x)  ((x) << FW_PARAMS_PARAM_Y_S)
1206 #define FW_PARAMS_PARAM_Y_G(x)  (((x) >> FW_PARAMS_PARAM_Y_S) &\
1207                 FW_PARAMS_PARAM_Y_M)
1208
1209 #define FW_PARAMS_PARAM_Z_S     0
1210 #define FW_PARAMS_PARAM_Z_M     0xffu
1211 #define FW_PARAMS_PARAM_Z_V(x)  ((x) << FW_PARAMS_PARAM_Z_S)
1212 #define FW_PARAMS_PARAM_Z_G(x)  (((x) >> FW_PARAMS_PARAM_Z_S) &\
1213                 FW_PARAMS_PARAM_Z_M)
1214
1215 #define FW_PARAMS_PARAM_XYZ_S           0
1216 #define FW_PARAMS_PARAM_XYZ_V(x)        ((x) << FW_PARAMS_PARAM_XYZ_S)
1217
1218 #define FW_PARAMS_PARAM_YZ_S            0
1219 #define FW_PARAMS_PARAM_YZ_V(x)         ((x) << FW_PARAMS_PARAM_YZ_S)
1220
1221 struct fw_params_cmd {
1222         __be32 op_to_vfn;
1223         __be32 retval_len16;
1224         struct fw_params_param {
1225                 __be32 mnem;
1226                 __be32 val;
1227         } param[7];
1228 };
1229
1230 #define FW_PARAMS_CMD_PFN_S     8
1231 #define FW_PARAMS_CMD_PFN_V(x)  ((x) << FW_PARAMS_CMD_PFN_S)
1232
1233 #define FW_PARAMS_CMD_VFN_S     0
1234 #define FW_PARAMS_CMD_VFN_V(x)  ((x) << FW_PARAMS_CMD_VFN_S)
1235
1236 struct fw_pfvf_cmd {
1237         __be32 op_to_vfn;
1238         __be32 retval_len16;
1239         __be32 niqflint_niq;
1240         __be32 type_to_neq;
1241         __be32 tc_to_nexactf;
1242         __be32 r_caps_to_nethctrl;
1243         __be16 nricq;
1244         __be16 nriqp;
1245         __be32 r4;
1246 };
1247
1248 #define FW_PFVF_CMD_PFN_S       8
1249 #define FW_PFVF_CMD_PFN_V(x)    ((x) << FW_PFVF_CMD_PFN_S)
1250
1251 #define FW_PFVF_CMD_VFN_S       0
1252 #define FW_PFVF_CMD_VFN_V(x)    ((x) << FW_PFVF_CMD_VFN_S)
1253
1254 #define FW_PFVF_CMD_NIQFLINT_S          20
1255 #define FW_PFVF_CMD_NIQFLINT_M          0xfff
1256 #define FW_PFVF_CMD_NIQFLINT_V(x)       ((x) << FW_PFVF_CMD_NIQFLINT_S)
1257 #define FW_PFVF_CMD_NIQFLINT_G(x)       \
1258         (((x) >> FW_PFVF_CMD_NIQFLINT_S) & FW_PFVF_CMD_NIQFLINT_M)
1259
1260 #define FW_PFVF_CMD_NIQ_S       0
1261 #define FW_PFVF_CMD_NIQ_M       0xfffff
1262 #define FW_PFVF_CMD_NIQ_V(x)    ((x) << FW_PFVF_CMD_NIQ_S)
1263 #define FW_PFVF_CMD_NIQ_G(x)    \
1264         (((x) >> FW_PFVF_CMD_NIQ_S) & FW_PFVF_CMD_NIQ_M)
1265
1266 #define FW_PFVF_CMD_TYPE_S      31
1267 #define FW_PFVF_CMD_TYPE_M      0x1
1268 #define FW_PFVF_CMD_TYPE_V(x)   ((x) << FW_PFVF_CMD_TYPE_S)
1269 #define FW_PFVF_CMD_TYPE_G(x)   \
1270         (((x) >> FW_PFVF_CMD_TYPE_S) & FW_PFVF_CMD_TYPE_M)
1271 #define FW_PFVF_CMD_TYPE_F      FW_PFVF_CMD_TYPE_V(1U)
1272
1273 #define FW_PFVF_CMD_CMASK_S     24
1274 #define FW_PFVF_CMD_CMASK_M     0xf
1275 #define FW_PFVF_CMD_CMASK_V(x)  ((x) << FW_PFVF_CMD_CMASK_S)
1276 #define FW_PFVF_CMD_CMASK_G(x)  \
1277         (((x) >> FW_PFVF_CMD_CMASK_S) & FW_PFVF_CMD_CMASK_M)
1278
1279 #define FW_PFVF_CMD_PMASK_S     20
1280 #define FW_PFVF_CMD_PMASK_M     0xf
1281 #define FW_PFVF_CMD_PMASK_V(x)  ((x) << FW_PFVF_CMD_PMASK_S)
1282 #define FW_PFVF_CMD_PMASK_G(x) \
1283         (((x) >> FW_PFVF_CMD_PMASK_S) & FW_PFVF_CMD_PMASK_M)
1284
1285 #define FW_PFVF_CMD_NEQ_S       0
1286 #define FW_PFVF_CMD_NEQ_M       0xfffff
1287 #define FW_PFVF_CMD_NEQ_V(x)    ((x) << FW_PFVF_CMD_NEQ_S)
1288 #define FW_PFVF_CMD_NEQ_G(x)    \
1289         (((x) >> FW_PFVF_CMD_NEQ_S) & FW_PFVF_CMD_NEQ_M)
1290
1291 #define FW_PFVF_CMD_TC_S        24
1292 #define FW_PFVF_CMD_TC_M        0xff
1293 #define FW_PFVF_CMD_TC_V(x)     ((x) << FW_PFVF_CMD_TC_S)
1294 #define FW_PFVF_CMD_TC_G(x)     (((x) >> FW_PFVF_CMD_TC_S) & FW_PFVF_CMD_TC_M)
1295
1296 #define FW_PFVF_CMD_NVI_S       16
1297 #define FW_PFVF_CMD_NVI_M       0xff
1298 #define FW_PFVF_CMD_NVI_V(x)    ((x) << FW_PFVF_CMD_NVI_S)
1299 #define FW_PFVF_CMD_NVI_G(x)    (((x) >> FW_PFVF_CMD_NVI_S) & FW_PFVF_CMD_NVI_M)
1300
1301 #define FW_PFVF_CMD_NEXACTF_S           0
1302 #define FW_PFVF_CMD_NEXACTF_M           0xffff
1303 #define FW_PFVF_CMD_NEXACTF_V(x)        ((x) << FW_PFVF_CMD_NEXACTF_S)
1304 #define FW_PFVF_CMD_NEXACTF_G(x)        \
1305         (((x) >> FW_PFVF_CMD_NEXACTF_S) & FW_PFVF_CMD_NEXACTF_M)
1306
1307 #define FW_PFVF_CMD_R_CAPS_S    24
1308 #define FW_PFVF_CMD_R_CAPS_M    0xff
1309 #define FW_PFVF_CMD_R_CAPS_V(x) ((x) << FW_PFVF_CMD_R_CAPS_S)
1310 #define FW_PFVF_CMD_R_CAPS_G(x) \
1311         (((x) >> FW_PFVF_CMD_R_CAPS_S) & FW_PFVF_CMD_R_CAPS_M)
1312
1313 #define FW_PFVF_CMD_WX_CAPS_S           16
1314 #define FW_PFVF_CMD_WX_CAPS_M           0xff
1315 #define FW_PFVF_CMD_WX_CAPS_V(x)        ((x) << FW_PFVF_CMD_WX_CAPS_S)
1316 #define FW_PFVF_CMD_WX_CAPS_G(x)        \
1317         (((x) >> FW_PFVF_CMD_WX_CAPS_S) & FW_PFVF_CMD_WX_CAPS_M)
1318
1319 #define FW_PFVF_CMD_NETHCTRL_S          0
1320 #define FW_PFVF_CMD_NETHCTRL_M          0xffff
1321 #define FW_PFVF_CMD_NETHCTRL_V(x)       ((x) << FW_PFVF_CMD_NETHCTRL_S)
1322 #define FW_PFVF_CMD_NETHCTRL_G(x)       \
1323         (((x) >> FW_PFVF_CMD_NETHCTRL_S) & FW_PFVF_CMD_NETHCTRL_M)
1324
1325 enum fw_iq_type {
1326         FW_IQ_TYPE_FL_INT_CAP,
1327         FW_IQ_TYPE_NO_FL_INT_CAP
1328 };
1329
1330 struct fw_iq_cmd {
1331         __be32 op_to_vfn;
1332         __be32 alloc_to_len16;
1333         __be16 physiqid;
1334         __be16 iqid;
1335         __be16 fl0id;
1336         __be16 fl1id;
1337         __be32 type_to_iqandstindex;
1338         __be16 iqdroprss_to_iqesize;
1339         __be16 iqsize;
1340         __be64 iqaddr;
1341         __be32 iqns_to_fl0congen;
1342         __be16 fl0dcaen_to_fl0cidxfthresh;
1343         __be16 fl0size;
1344         __be64 fl0addr;
1345         __be32 fl1cngchmap_to_fl1congen;
1346         __be16 fl1dcaen_to_fl1cidxfthresh;
1347         __be16 fl1size;
1348         __be64 fl1addr;
1349 };
1350
1351 #define FW_IQ_CMD_PFN_S         8
1352 #define FW_IQ_CMD_PFN_V(x)      ((x) << FW_IQ_CMD_PFN_S)
1353
1354 #define FW_IQ_CMD_VFN_S         0
1355 #define FW_IQ_CMD_VFN_V(x)      ((x) << FW_IQ_CMD_VFN_S)
1356
1357 #define FW_IQ_CMD_ALLOC_S       31
1358 #define FW_IQ_CMD_ALLOC_V(x)    ((x) << FW_IQ_CMD_ALLOC_S)
1359 #define FW_IQ_CMD_ALLOC_F       FW_IQ_CMD_ALLOC_V(1U)
1360
1361 #define FW_IQ_CMD_FREE_S        30
1362 #define FW_IQ_CMD_FREE_V(x)     ((x) << FW_IQ_CMD_FREE_S)
1363 #define FW_IQ_CMD_FREE_F        FW_IQ_CMD_FREE_V(1U)
1364
1365 #define FW_IQ_CMD_MODIFY_S      29
1366 #define FW_IQ_CMD_MODIFY_V(x)   ((x) << FW_IQ_CMD_MODIFY_S)
1367 #define FW_IQ_CMD_MODIFY_F      FW_IQ_CMD_MODIFY_V(1U)
1368
1369 #define FW_IQ_CMD_IQSTART_S     28
1370 #define FW_IQ_CMD_IQSTART_V(x)  ((x) << FW_IQ_CMD_IQSTART_S)
1371 #define FW_IQ_CMD_IQSTART_F     FW_IQ_CMD_IQSTART_V(1U)
1372
1373 #define FW_IQ_CMD_IQSTOP_S      27
1374 #define FW_IQ_CMD_IQSTOP_V(x)   ((x) << FW_IQ_CMD_IQSTOP_S)
1375 #define FW_IQ_CMD_IQSTOP_F      FW_IQ_CMD_IQSTOP_V(1U)
1376
1377 #define FW_IQ_CMD_TYPE_S        29
1378 #define FW_IQ_CMD_TYPE_V(x)     ((x) << FW_IQ_CMD_TYPE_S)
1379
1380 #define FW_IQ_CMD_IQASYNCH_S    28
1381 #define FW_IQ_CMD_IQASYNCH_V(x) ((x) << FW_IQ_CMD_IQASYNCH_S)
1382
1383 #define FW_IQ_CMD_VIID_S        16
1384 #define FW_IQ_CMD_VIID_V(x)     ((x) << FW_IQ_CMD_VIID_S)
1385
1386 #define FW_IQ_CMD_IQANDST_S     15
1387 #define FW_IQ_CMD_IQANDST_V(x)  ((x) << FW_IQ_CMD_IQANDST_S)
1388
1389 #define FW_IQ_CMD_IQANUS_S      14
1390 #define FW_IQ_CMD_IQANUS_V(x)   ((x) << FW_IQ_CMD_IQANUS_S)
1391
1392 #define FW_IQ_CMD_IQANUD_S      12
1393 #define FW_IQ_CMD_IQANUD_V(x)   ((x) << FW_IQ_CMD_IQANUD_S)
1394
1395 #define FW_IQ_CMD_IQANDSTINDEX_S        0
1396 #define FW_IQ_CMD_IQANDSTINDEX_V(x)     ((x) << FW_IQ_CMD_IQANDSTINDEX_S)
1397
1398 #define FW_IQ_CMD_IQDROPRSS_S           15
1399 #define FW_IQ_CMD_IQDROPRSS_V(x)        ((x) << FW_IQ_CMD_IQDROPRSS_S)
1400 #define FW_IQ_CMD_IQDROPRSS_F   FW_IQ_CMD_IQDROPRSS_V(1U)
1401
1402 #define FW_IQ_CMD_IQGTSMODE_S           14
1403 #define FW_IQ_CMD_IQGTSMODE_V(x)        ((x) << FW_IQ_CMD_IQGTSMODE_S)
1404 #define FW_IQ_CMD_IQGTSMODE_F           FW_IQ_CMD_IQGTSMODE_V(1U)
1405
1406 #define FW_IQ_CMD_IQPCIECH_S    12
1407 #define FW_IQ_CMD_IQPCIECH_V(x) ((x) << FW_IQ_CMD_IQPCIECH_S)
1408
1409 #define FW_IQ_CMD_IQDCAEN_S     11
1410 #define FW_IQ_CMD_IQDCAEN_V(x)  ((x) << FW_IQ_CMD_IQDCAEN_S)
1411
1412 #define FW_IQ_CMD_IQDCACPU_S    6
1413 #define FW_IQ_CMD_IQDCACPU_V(x) ((x) << FW_IQ_CMD_IQDCACPU_S)
1414
1415 #define FW_IQ_CMD_IQINTCNTTHRESH_S      4
1416 #define FW_IQ_CMD_IQINTCNTTHRESH_V(x)   ((x) << FW_IQ_CMD_IQINTCNTTHRESH_S)
1417
1418 #define FW_IQ_CMD_IQO_S         3
1419 #define FW_IQ_CMD_IQO_V(x)      ((x) << FW_IQ_CMD_IQO_S)
1420 #define FW_IQ_CMD_IQO_F         FW_IQ_CMD_IQO_V(1U)
1421
1422 #define FW_IQ_CMD_IQCPRIO_S     2
1423 #define FW_IQ_CMD_IQCPRIO_V(x)  ((x) << FW_IQ_CMD_IQCPRIO_S)
1424
1425 #define FW_IQ_CMD_IQESIZE_S     0
1426 #define FW_IQ_CMD_IQESIZE_V(x)  ((x) << FW_IQ_CMD_IQESIZE_S)
1427
1428 #define FW_IQ_CMD_IQNS_S        31
1429 #define FW_IQ_CMD_IQNS_V(x)     ((x) << FW_IQ_CMD_IQNS_S)
1430
1431 #define FW_IQ_CMD_IQRO_S        30
1432 #define FW_IQ_CMD_IQRO_V(x)     ((x) << FW_IQ_CMD_IQRO_S)
1433
1434 #define FW_IQ_CMD_IQFLINTIQHSEN_S       28
1435 #define FW_IQ_CMD_IQFLINTIQHSEN_V(x)    ((x) << FW_IQ_CMD_IQFLINTIQHSEN_S)
1436
1437 #define FW_IQ_CMD_IQFLINTCONGEN_S       27
1438 #define FW_IQ_CMD_IQFLINTCONGEN_V(x)    ((x) << FW_IQ_CMD_IQFLINTCONGEN_S)
1439 #define FW_IQ_CMD_IQFLINTCONGEN_F       FW_IQ_CMD_IQFLINTCONGEN_V(1U)
1440
1441 #define FW_IQ_CMD_IQFLINTISCSIC_S       26
1442 #define FW_IQ_CMD_IQFLINTISCSIC_V(x)    ((x) << FW_IQ_CMD_IQFLINTISCSIC_S)
1443
1444 #define FW_IQ_CMD_FL0CNGCHMAP_S         20
1445 #define FW_IQ_CMD_FL0CNGCHMAP_V(x)      ((x) << FW_IQ_CMD_FL0CNGCHMAP_S)
1446
1447 #define FW_IQ_CMD_FL0CACHELOCK_S        15
1448 #define FW_IQ_CMD_FL0CACHELOCK_V(x)     ((x) << FW_IQ_CMD_FL0CACHELOCK_S)
1449
1450 #define FW_IQ_CMD_FL0DBP_S      14
1451 #define FW_IQ_CMD_FL0DBP_V(x)   ((x) << FW_IQ_CMD_FL0DBP_S)
1452
1453 #define FW_IQ_CMD_FL0DATANS_S           13
1454 #define FW_IQ_CMD_FL0DATANS_V(x)        ((x) << FW_IQ_CMD_FL0DATANS_S)
1455
1456 #define FW_IQ_CMD_FL0DATARO_S           12
1457 #define FW_IQ_CMD_FL0DATARO_V(x)        ((x) << FW_IQ_CMD_FL0DATARO_S)
1458 #define FW_IQ_CMD_FL0DATARO_F           FW_IQ_CMD_FL0DATARO_V(1U)
1459
1460 #define FW_IQ_CMD_FL0CONGCIF_S          11
1461 #define FW_IQ_CMD_FL0CONGCIF_V(x)       ((x) << FW_IQ_CMD_FL0CONGCIF_S)
1462 #define FW_IQ_CMD_FL0CONGCIF_F          FW_IQ_CMD_FL0CONGCIF_V(1U)
1463
1464 #define FW_IQ_CMD_FL0ONCHIP_S           10
1465 #define FW_IQ_CMD_FL0ONCHIP_V(x)        ((x) << FW_IQ_CMD_FL0ONCHIP_S)
1466
1467 #define FW_IQ_CMD_FL0STATUSPGNS_S       9
1468 #define FW_IQ_CMD_FL0STATUSPGNS_V(x)    ((x) << FW_IQ_CMD_FL0STATUSPGNS_S)
1469
1470 #define FW_IQ_CMD_FL0STATUSPGRO_S       8
1471 #define FW_IQ_CMD_FL0STATUSPGRO_V(x)    ((x) << FW_IQ_CMD_FL0STATUSPGRO_S)
1472
1473 #define FW_IQ_CMD_FL0FETCHNS_S          7
1474 #define FW_IQ_CMD_FL0FETCHNS_V(x)       ((x) << FW_IQ_CMD_FL0FETCHNS_S)
1475
1476 #define FW_IQ_CMD_FL0FETCHRO_S          6
1477 #define FW_IQ_CMD_FL0FETCHRO_V(x)       ((x) << FW_IQ_CMD_FL0FETCHRO_S)
1478 #define FW_IQ_CMD_FL0FETCHRO_F          FW_IQ_CMD_FL0FETCHRO_V(1U)
1479
1480 #define FW_IQ_CMD_FL0HOSTFCMODE_S       4
1481 #define FW_IQ_CMD_FL0HOSTFCMODE_V(x)    ((x) << FW_IQ_CMD_FL0HOSTFCMODE_S)
1482
1483 #define FW_IQ_CMD_FL0CPRIO_S    3
1484 #define FW_IQ_CMD_FL0CPRIO_V(x) ((x) << FW_IQ_CMD_FL0CPRIO_S)
1485
1486 #define FW_IQ_CMD_FL0PADEN_S    2
1487 #define FW_IQ_CMD_FL0PADEN_V(x) ((x) << FW_IQ_CMD_FL0PADEN_S)
1488 #define FW_IQ_CMD_FL0PADEN_F    FW_IQ_CMD_FL0PADEN_V(1U)
1489
1490 #define FW_IQ_CMD_FL0PACKEN_S           1
1491 #define FW_IQ_CMD_FL0PACKEN_V(x)        ((x) << FW_IQ_CMD_FL0PACKEN_S)
1492 #define FW_IQ_CMD_FL0PACKEN_F           FW_IQ_CMD_FL0PACKEN_V(1U)
1493
1494 #define FW_IQ_CMD_FL0CONGEN_S           0
1495 #define FW_IQ_CMD_FL0CONGEN_V(x)        ((x) << FW_IQ_CMD_FL0CONGEN_S)
1496 #define FW_IQ_CMD_FL0CONGEN_F           FW_IQ_CMD_FL0CONGEN_V(1U)
1497
1498 #define FW_IQ_CMD_FL0DCAEN_S    15
1499 #define FW_IQ_CMD_FL0DCAEN_V(x) ((x) << FW_IQ_CMD_FL0DCAEN_S)
1500
1501 #define FW_IQ_CMD_FL0DCACPU_S           10
1502 #define FW_IQ_CMD_FL0DCACPU_V(x)        ((x) << FW_IQ_CMD_FL0DCACPU_S)
1503
1504 #define FW_IQ_CMD_FL0FBMIN_S    7
1505 #define FW_IQ_CMD_FL0FBMIN_V(x) ((x) << FW_IQ_CMD_FL0FBMIN_S)
1506
1507 #define FW_IQ_CMD_FL0FBMAX_S    4
1508 #define FW_IQ_CMD_FL0FBMAX_V(x) ((x) << FW_IQ_CMD_FL0FBMAX_S)
1509
1510 #define FW_IQ_CMD_FL0CIDXFTHRESHO_S     3
1511 #define FW_IQ_CMD_FL0CIDXFTHRESHO_V(x)  ((x) << FW_IQ_CMD_FL0CIDXFTHRESHO_S)
1512 #define FW_IQ_CMD_FL0CIDXFTHRESHO_F     FW_IQ_CMD_FL0CIDXFTHRESHO_V(1U)
1513
1514 #define FW_IQ_CMD_FL0CIDXFTHRESH_S      0
1515 #define FW_IQ_CMD_FL0CIDXFTHRESH_V(x)   ((x) << FW_IQ_CMD_FL0CIDXFTHRESH_S)
1516
1517 #define FW_IQ_CMD_FL1CNGCHMAP_S         20
1518 #define FW_IQ_CMD_FL1CNGCHMAP_V(x)      ((x) << FW_IQ_CMD_FL1CNGCHMAP_S)
1519
1520 #define FW_IQ_CMD_FL1CACHELOCK_S        15
1521 #define FW_IQ_CMD_FL1CACHELOCK_V(x)     ((x) << FW_IQ_CMD_FL1CACHELOCK_S)
1522
1523 #define FW_IQ_CMD_FL1DBP_S      14
1524 #define FW_IQ_CMD_FL1DBP_V(x)   ((x) << FW_IQ_CMD_FL1DBP_S)
1525
1526 #define FW_IQ_CMD_FL1DATANS_S           13
1527 #define FW_IQ_CMD_FL1DATANS_V(x)        ((x) << FW_IQ_CMD_FL1DATANS_S)
1528
1529 #define FW_IQ_CMD_FL1DATARO_S           12
1530 #define FW_IQ_CMD_FL1DATARO_V(x)        ((x) << FW_IQ_CMD_FL1DATARO_S)
1531
1532 #define FW_IQ_CMD_FL1CONGCIF_S          11
1533 #define FW_IQ_CMD_FL1CONGCIF_V(x)       ((x) << FW_IQ_CMD_FL1CONGCIF_S)
1534
1535 #define FW_IQ_CMD_FL1ONCHIP_S           10
1536 #define FW_IQ_CMD_FL1ONCHIP_V(x)        ((x) << FW_IQ_CMD_FL1ONCHIP_S)
1537
1538 #define FW_IQ_CMD_FL1STATUSPGNS_S       9
1539 #define FW_IQ_CMD_FL1STATUSPGNS_V(x)    ((x) << FW_IQ_CMD_FL1STATUSPGNS_S)
1540
1541 #define FW_IQ_CMD_FL1STATUSPGRO_S       8
1542 #define FW_IQ_CMD_FL1STATUSPGRO_V(x)    ((x) << FW_IQ_CMD_FL1STATUSPGRO_S)
1543
1544 #define FW_IQ_CMD_FL1FETCHNS_S          7
1545 #define FW_IQ_CMD_FL1FETCHNS_V(x)       ((x) << FW_IQ_CMD_FL1FETCHNS_S)
1546
1547 #define FW_IQ_CMD_FL1FETCHRO_S          6
1548 #define FW_IQ_CMD_FL1FETCHRO_V(x)       ((x) << FW_IQ_CMD_FL1FETCHRO_S)
1549
1550 #define FW_IQ_CMD_FL1HOSTFCMODE_S       4
1551 #define FW_IQ_CMD_FL1HOSTFCMODE_V(x)    ((x) << FW_IQ_CMD_FL1HOSTFCMODE_S)
1552
1553 #define FW_IQ_CMD_FL1CPRIO_S    3
1554 #define FW_IQ_CMD_FL1CPRIO_V(x) ((x) << FW_IQ_CMD_FL1CPRIO_S)
1555
1556 #define FW_IQ_CMD_FL1PADEN_S    2
1557 #define FW_IQ_CMD_FL1PADEN_V(x) ((x) << FW_IQ_CMD_FL1PADEN_S)
1558 #define FW_IQ_CMD_FL1PADEN_F    FW_IQ_CMD_FL1PADEN_V(1U)
1559
1560 #define FW_IQ_CMD_FL1PACKEN_S           1
1561 #define FW_IQ_CMD_FL1PACKEN_V(x)        ((x) << FW_IQ_CMD_FL1PACKEN_S)
1562 #define FW_IQ_CMD_FL1PACKEN_F   FW_IQ_CMD_FL1PACKEN_V(1U)
1563
1564 #define FW_IQ_CMD_FL1CONGEN_S           0
1565 #define FW_IQ_CMD_FL1CONGEN_V(x)        ((x) << FW_IQ_CMD_FL1CONGEN_S)
1566 #define FW_IQ_CMD_FL1CONGEN_F   FW_IQ_CMD_FL1CONGEN_V(1U)
1567
1568 #define FW_IQ_CMD_FL1DCAEN_S    15
1569 #define FW_IQ_CMD_FL1DCAEN_V(x) ((x) << FW_IQ_CMD_FL1DCAEN_S)
1570
1571 #define FW_IQ_CMD_FL1DCACPU_S           10
1572 #define FW_IQ_CMD_FL1DCACPU_V(x)        ((x) << FW_IQ_CMD_FL1DCACPU_S)
1573
1574 #define FW_IQ_CMD_FL1FBMIN_S    7
1575 #define FW_IQ_CMD_FL1FBMIN_V(x) ((x) << FW_IQ_CMD_FL1FBMIN_S)
1576
1577 #define FW_IQ_CMD_FL1FBMAX_S    4
1578 #define FW_IQ_CMD_FL1FBMAX_V(x) ((x) << FW_IQ_CMD_FL1FBMAX_S)
1579
1580 #define FW_IQ_CMD_FL1CIDXFTHRESHO_S     3
1581 #define FW_IQ_CMD_FL1CIDXFTHRESHO_V(x)  ((x) << FW_IQ_CMD_FL1CIDXFTHRESHO_S)
1582 #define FW_IQ_CMD_FL1CIDXFTHRESHO_F     FW_IQ_CMD_FL1CIDXFTHRESHO_V(1U)
1583
1584 #define FW_IQ_CMD_FL1CIDXFTHRESH_S      0
1585 #define FW_IQ_CMD_FL1CIDXFTHRESH_V(x)   ((x) << FW_IQ_CMD_FL1CIDXFTHRESH_S)
1586
1587 struct fw_eq_eth_cmd {
1588         __be32 op_to_vfn;
1589         __be32 alloc_to_len16;
1590         __be32 eqid_pkd;
1591         __be32 physeqid_pkd;
1592         __be32 fetchszm_to_iqid;
1593         __be32 dcaen_to_eqsize;
1594         __be64 eqaddr;
1595         __be32 viid_pkd;
1596         __be32 r8_lo;
1597         __be64 r9;
1598 };
1599
1600 #define FW_EQ_ETH_CMD_PFN_S     8
1601 #define FW_EQ_ETH_CMD_PFN_V(x)  ((x) << FW_EQ_ETH_CMD_PFN_S)
1602
1603 #define FW_EQ_ETH_CMD_VFN_S     0
1604 #define FW_EQ_ETH_CMD_VFN_V(x)  ((x) << FW_EQ_ETH_CMD_VFN_S)
1605
1606 #define FW_EQ_ETH_CMD_ALLOC_S           31
1607 #define FW_EQ_ETH_CMD_ALLOC_V(x)        ((x) << FW_EQ_ETH_CMD_ALLOC_S)
1608 #define FW_EQ_ETH_CMD_ALLOC_F   FW_EQ_ETH_CMD_ALLOC_V(1U)
1609
1610 #define FW_EQ_ETH_CMD_FREE_S    30
1611 #define FW_EQ_ETH_CMD_FREE_V(x) ((x) << FW_EQ_ETH_CMD_FREE_S)
1612 #define FW_EQ_ETH_CMD_FREE_F    FW_EQ_ETH_CMD_FREE_V(1U)
1613
1614 #define FW_EQ_ETH_CMD_MODIFY_S          29
1615 #define FW_EQ_ETH_CMD_MODIFY_V(x)       ((x) << FW_EQ_ETH_CMD_MODIFY_S)
1616 #define FW_EQ_ETH_CMD_MODIFY_F  FW_EQ_ETH_CMD_MODIFY_V(1U)
1617
1618 #define FW_EQ_ETH_CMD_EQSTART_S         28
1619 #define FW_EQ_ETH_CMD_EQSTART_V(x)      ((x) << FW_EQ_ETH_CMD_EQSTART_S)
1620 #define FW_EQ_ETH_CMD_EQSTART_F FW_EQ_ETH_CMD_EQSTART_V(1U)
1621
1622 #define FW_EQ_ETH_CMD_EQSTOP_S          27
1623 #define FW_EQ_ETH_CMD_EQSTOP_V(x)       ((x) << FW_EQ_ETH_CMD_EQSTOP_S)
1624 #define FW_EQ_ETH_CMD_EQSTOP_F  FW_EQ_ETH_CMD_EQSTOP_V(1U)
1625
1626 #define FW_EQ_ETH_CMD_EQID_S    0
1627 #define FW_EQ_ETH_CMD_EQID_M    0xfffff
1628 #define FW_EQ_ETH_CMD_EQID_V(x) ((x) << FW_EQ_ETH_CMD_EQID_S)
1629 #define FW_EQ_ETH_CMD_EQID_G(x) \
1630         (((x) >> FW_EQ_ETH_CMD_EQID_S) & FW_EQ_ETH_CMD_EQID_M)
1631
1632 #define FW_EQ_ETH_CMD_PHYSEQID_S        0
1633 #define FW_EQ_ETH_CMD_PHYSEQID_M        0xfffff
1634 #define FW_EQ_ETH_CMD_PHYSEQID_V(x)     ((x) << FW_EQ_ETH_CMD_PHYSEQID_S)
1635 #define FW_EQ_ETH_CMD_PHYSEQID_G(x)     \
1636         (((x) >> FW_EQ_ETH_CMD_PHYSEQID_S) & FW_EQ_ETH_CMD_PHYSEQID_M)
1637
1638 #define FW_EQ_ETH_CMD_FETCHSZM_S        26
1639 #define FW_EQ_ETH_CMD_FETCHSZM_V(x)     ((x) << FW_EQ_ETH_CMD_FETCHSZM_S)
1640 #define FW_EQ_ETH_CMD_FETCHSZM_F        FW_EQ_ETH_CMD_FETCHSZM_V(1U)
1641
1642 #define FW_EQ_ETH_CMD_STATUSPGNS_S      25
1643 #define FW_EQ_ETH_CMD_STATUSPGNS_V(x)   ((x) << FW_EQ_ETH_CMD_STATUSPGNS_S)
1644
1645 #define FW_EQ_ETH_CMD_STATUSPGRO_S      24
1646 #define FW_EQ_ETH_CMD_STATUSPGRO_V(x)   ((x) << FW_EQ_ETH_CMD_STATUSPGRO_S)
1647
1648 #define FW_EQ_ETH_CMD_FETCHNS_S         23
1649 #define FW_EQ_ETH_CMD_FETCHNS_V(x)      ((x) << FW_EQ_ETH_CMD_FETCHNS_S)
1650
1651 #define FW_EQ_ETH_CMD_FETCHRO_S         22
1652 #define FW_EQ_ETH_CMD_FETCHRO_V(x)      ((x) << FW_EQ_ETH_CMD_FETCHRO_S)
1653 #define FW_EQ_ETH_CMD_FETCHRO_F         FW_EQ_ETH_CMD_FETCHRO_V(1U)
1654
1655 #define FW_EQ_ETH_CMD_HOSTFCMODE_S      20
1656 #define FW_EQ_ETH_CMD_HOSTFCMODE_V(x)   ((x) << FW_EQ_ETH_CMD_HOSTFCMODE_S)
1657
1658 #define FW_EQ_ETH_CMD_CPRIO_S           19
1659 #define FW_EQ_ETH_CMD_CPRIO_V(x)        ((x) << FW_EQ_ETH_CMD_CPRIO_S)
1660
1661 #define FW_EQ_ETH_CMD_ONCHIP_S          18
1662 #define FW_EQ_ETH_CMD_ONCHIP_V(x)       ((x) << FW_EQ_ETH_CMD_ONCHIP_S)
1663
1664 #define FW_EQ_ETH_CMD_PCIECHN_S         16
1665 #define FW_EQ_ETH_CMD_PCIECHN_V(x)      ((x) << FW_EQ_ETH_CMD_PCIECHN_S)
1666
1667 #define FW_EQ_ETH_CMD_IQID_S    0
1668 #define FW_EQ_ETH_CMD_IQID_V(x) ((x) << FW_EQ_ETH_CMD_IQID_S)
1669
1670 #define FW_EQ_ETH_CMD_DCAEN_S           31
1671 #define FW_EQ_ETH_CMD_DCAEN_V(x)        ((x) << FW_EQ_ETH_CMD_DCAEN_S)
1672
1673 #define FW_EQ_ETH_CMD_DCACPU_S          26
1674 #define FW_EQ_ETH_CMD_DCACPU_V(x)       ((x) << FW_EQ_ETH_CMD_DCACPU_S)
1675
1676 #define FW_EQ_ETH_CMD_FBMIN_S           23
1677 #define FW_EQ_ETH_CMD_FBMIN_V(x)        ((x) << FW_EQ_ETH_CMD_FBMIN_S)
1678
1679 #define FW_EQ_ETH_CMD_FBMAX_S           20
1680 #define FW_EQ_ETH_CMD_FBMAX_V(x)        ((x) << FW_EQ_ETH_CMD_FBMAX_S)
1681
1682 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_S    19
1683 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESHO_S)
1684
1685 #define FW_EQ_ETH_CMD_CIDXFTHRESH_S     16
1686 #define FW_EQ_ETH_CMD_CIDXFTHRESH_V(x)  ((x) << FW_EQ_ETH_CMD_CIDXFTHRESH_S)
1687
1688 #define FW_EQ_ETH_CMD_EQSIZE_S          0
1689 #define FW_EQ_ETH_CMD_EQSIZE_V(x)       ((x) << FW_EQ_ETH_CMD_EQSIZE_S)
1690
1691 #define FW_EQ_ETH_CMD_AUTOEQUEQE_S      30
1692 #define FW_EQ_ETH_CMD_AUTOEQUEQE_V(x)   ((x) << FW_EQ_ETH_CMD_AUTOEQUEQE_S)
1693 #define FW_EQ_ETH_CMD_AUTOEQUEQE_F      FW_EQ_ETH_CMD_AUTOEQUEQE_V(1U)
1694
1695 #define FW_EQ_ETH_CMD_VIID_S    16
1696 #define FW_EQ_ETH_CMD_VIID_V(x) ((x) << FW_EQ_ETH_CMD_VIID_S)
1697
1698 struct fw_eq_ctrl_cmd {
1699         __be32 op_to_vfn;
1700         __be32 alloc_to_len16;
1701         __be32 cmpliqid_eqid;
1702         __be32 physeqid_pkd;
1703         __be32 fetchszm_to_iqid;
1704         __be32 dcaen_to_eqsize;
1705         __be64 eqaddr;
1706 };
1707
1708 #define FW_EQ_CTRL_CMD_PFN_S    8
1709 #define FW_EQ_CTRL_CMD_PFN_V(x) ((x) << FW_EQ_CTRL_CMD_PFN_S)
1710
1711 #define FW_EQ_CTRL_CMD_VFN_S    0
1712 #define FW_EQ_CTRL_CMD_VFN_V(x) ((x) << FW_EQ_CTRL_CMD_VFN_S)
1713
1714 #define FW_EQ_CTRL_CMD_ALLOC_S          31
1715 #define FW_EQ_CTRL_CMD_ALLOC_V(x)       ((x) << FW_EQ_CTRL_CMD_ALLOC_S)
1716 #define FW_EQ_CTRL_CMD_ALLOC_F          FW_EQ_CTRL_CMD_ALLOC_V(1U)
1717
1718 #define FW_EQ_CTRL_CMD_FREE_S           30
1719 #define FW_EQ_CTRL_CMD_FREE_V(x)        ((x) << FW_EQ_CTRL_CMD_FREE_S)
1720 #define FW_EQ_CTRL_CMD_FREE_F           FW_EQ_CTRL_CMD_FREE_V(1U)
1721
1722 #define FW_EQ_CTRL_CMD_MODIFY_S         29
1723 #define FW_EQ_CTRL_CMD_MODIFY_V(x)      ((x) << FW_EQ_CTRL_CMD_MODIFY_S)
1724 #define FW_EQ_CTRL_CMD_MODIFY_F         FW_EQ_CTRL_CMD_MODIFY_V(1U)
1725
1726 #define FW_EQ_CTRL_CMD_EQSTART_S        28
1727 #define FW_EQ_CTRL_CMD_EQSTART_V(x)     ((x) << FW_EQ_CTRL_CMD_EQSTART_S)
1728 #define FW_EQ_CTRL_CMD_EQSTART_F        FW_EQ_CTRL_CMD_EQSTART_V(1U)
1729
1730 #define FW_EQ_CTRL_CMD_EQSTOP_S         27
1731 #define FW_EQ_CTRL_CMD_EQSTOP_V(x)      ((x) << FW_EQ_CTRL_CMD_EQSTOP_S)
1732 #define FW_EQ_CTRL_CMD_EQSTOP_F         FW_EQ_CTRL_CMD_EQSTOP_V(1U)
1733
1734 #define FW_EQ_CTRL_CMD_CMPLIQID_S       20
1735 #define FW_EQ_CTRL_CMD_CMPLIQID_V(x)    ((x) << FW_EQ_CTRL_CMD_CMPLIQID_S)
1736
1737 #define FW_EQ_CTRL_CMD_EQID_S           0
1738 #define FW_EQ_CTRL_CMD_EQID_M           0xfffff
1739 #define FW_EQ_CTRL_CMD_EQID_V(x)        ((x) << FW_EQ_CTRL_CMD_EQID_S)
1740 #define FW_EQ_CTRL_CMD_EQID_G(x)        \
1741         (((x) >> FW_EQ_CTRL_CMD_EQID_S) & FW_EQ_CTRL_CMD_EQID_M)
1742
1743 #define FW_EQ_CTRL_CMD_PHYSEQID_S       0
1744 #define FW_EQ_CTRL_CMD_PHYSEQID_M       0xfffff
1745 #define FW_EQ_CTRL_CMD_PHYSEQID_G(x)    \
1746         (((x) >> FW_EQ_CTRL_CMD_PHYSEQID_S) & FW_EQ_CTRL_CMD_PHYSEQID_M)
1747
1748 #define FW_EQ_CTRL_CMD_FETCHSZM_S       26
1749 #define FW_EQ_CTRL_CMD_FETCHSZM_V(x)    ((x) << FW_EQ_CTRL_CMD_FETCHSZM_S)
1750 #define FW_EQ_CTRL_CMD_FETCHSZM_F       FW_EQ_CTRL_CMD_FETCHSZM_V(1U)
1751
1752 #define FW_EQ_CTRL_CMD_STATUSPGNS_S     25
1753 #define FW_EQ_CTRL_CMD_STATUSPGNS_V(x)  ((x) << FW_EQ_CTRL_CMD_STATUSPGNS_S)
1754 #define FW_EQ_CTRL_CMD_STATUSPGNS_F     FW_EQ_CTRL_CMD_STATUSPGNS_V(1U)
1755
1756 #define FW_EQ_CTRL_CMD_STATUSPGRO_S     24
1757 #define FW_EQ_CTRL_CMD_STATUSPGRO_V(x)  ((x) << FW_EQ_CTRL_CMD_STATUSPGRO_S)
1758 #define FW_EQ_CTRL_CMD_STATUSPGRO_F     FW_EQ_CTRL_CMD_STATUSPGRO_V(1U)
1759
1760 #define FW_EQ_CTRL_CMD_FETCHNS_S        23
1761 #define FW_EQ_CTRL_CMD_FETCHNS_V(x)     ((x) << FW_EQ_CTRL_CMD_FETCHNS_S)
1762 #define FW_EQ_CTRL_CMD_FETCHNS_F        FW_EQ_CTRL_CMD_FETCHNS_V(1U)
1763
1764 #define FW_EQ_CTRL_CMD_FETCHRO_S        22
1765 #define FW_EQ_CTRL_CMD_FETCHRO_V(x)     ((x) << FW_EQ_CTRL_CMD_FETCHRO_S)
1766 #define FW_EQ_CTRL_CMD_FETCHRO_F        FW_EQ_CTRL_CMD_FETCHRO_V(1U)
1767
1768 #define FW_EQ_CTRL_CMD_HOSTFCMODE_S     20
1769 #define FW_EQ_CTRL_CMD_HOSTFCMODE_V(x)  ((x) << FW_EQ_CTRL_CMD_HOSTFCMODE_S)
1770
1771 #define FW_EQ_CTRL_CMD_CPRIO_S          19
1772 #define FW_EQ_CTRL_CMD_CPRIO_V(x)       ((x) << FW_EQ_CTRL_CMD_CPRIO_S)
1773
1774 #define FW_EQ_CTRL_CMD_ONCHIP_S         18
1775 #define FW_EQ_CTRL_CMD_ONCHIP_V(x)      ((x) << FW_EQ_CTRL_CMD_ONCHIP_S)
1776
1777 #define FW_EQ_CTRL_CMD_PCIECHN_S        16
1778 #define FW_EQ_CTRL_CMD_PCIECHN_V(x)     ((x) << FW_EQ_CTRL_CMD_PCIECHN_S)
1779
1780 #define FW_EQ_CTRL_CMD_IQID_S           0
1781 #define FW_EQ_CTRL_CMD_IQID_V(x)        ((x) << FW_EQ_CTRL_CMD_IQID_S)
1782
1783 #define FW_EQ_CTRL_CMD_DCAEN_S          31
1784 #define FW_EQ_CTRL_CMD_DCAEN_V(x)       ((x) << FW_EQ_CTRL_CMD_DCAEN_S)
1785
1786 #define FW_EQ_CTRL_CMD_DCACPU_S         26
1787 #define FW_EQ_CTRL_CMD_DCACPU_V(x)      ((x) << FW_EQ_CTRL_CMD_DCACPU_S)
1788
1789 #define FW_EQ_CTRL_CMD_FBMIN_S          23
1790 #define FW_EQ_CTRL_CMD_FBMIN_V(x)       ((x) << FW_EQ_CTRL_CMD_FBMIN_S)
1791
1792 #define FW_EQ_CTRL_CMD_FBMAX_S          20
1793 #define FW_EQ_CTRL_CMD_FBMAX_V(x)       ((x) << FW_EQ_CTRL_CMD_FBMAX_S)
1794
1795 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_S           19
1796 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_V(x)        \
1797         ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESHO_S)
1798
1799 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_S    16
1800 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESH_S)
1801
1802 #define FW_EQ_CTRL_CMD_EQSIZE_S         0
1803 #define FW_EQ_CTRL_CMD_EQSIZE_V(x)      ((x) << FW_EQ_CTRL_CMD_EQSIZE_S)
1804
1805 struct fw_eq_ofld_cmd {
1806         __be32 op_to_vfn;
1807         __be32 alloc_to_len16;
1808         __be32 eqid_pkd;
1809         __be32 physeqid_pkd;
1810         __be32 fetchszm_to_iqid;
1811         __be32 dcaen_to_eqsize;
1812         __be64 eqaddr;
1813 };
1814
1815 #define FW_EQ_OFLD_CMD_PFN_S    8
1816 #define FW_EQ_OFLD_CMD_PFN_V(x) ((x) << FW_EQ_OFLD_CMD_PFN_S)
1817
1818 #define FW_EQ_OFLD_CMD_VFN_S    0
1819 #define FW_EQ_OFLD_CMD_VFN_V(x) ((x) << FW_EQ_OFLD_CMD_VFN_S)
1820
1821 #define FW_EQ_OFLD_CMD_ALLOC_S          31
1822 #define FW_EQ_OFLD_CMD_ALLOC_V(x)       ((x) << FW_EQ_OFLD_CMD_ALLOC_S)
1823 #define FW_EQ_OFLD_CMD_ALLOC_F          FW_EQ_OFLD_CMD_ALLOC_V(1U)
1824
1825 #define FW_EQ_OFLD_CMD_FREE_S           30
1826 #define FW_EQ_OFLD_CMD_FREE_V(x)        ((x) << FW_EQ_OFLD_CMD_FREE_S)
1827 #define FW_EQ_OFLD_CMD_FREE_F           FW_EQ_OFLD_CMD_FREE_V(1U)
1828
1829 #define FW_EQ_OFLD_CMD_MODIFY_S         29
1830 #define FW_EQ_OFLD_CMD_MODIFY_V(x)      ((x) << FW_EQ_OFLD_CMD_MODIFY_S)
1831 #define FW_EQ_OFLD_CMD_MODIFY_F         FW_EQ_OFLD_CMD_MODIFY_V(1U)
1832
1833 #define FW_EQ_OFLD_CMD_EQSTART_S        28
1834 #define FW_EQ_OFLD_CMD_EQSTART_V(x)     ((x) << FW_EQ_OFLD_CMD_EQSTART_S)
1835 #define FW_EQ_OFLD_CMD_EQSTART_F        FW_EQ_OFLD_CMD_EQSTART_V(1U)
1836
1837 #define FW_EQ_OFLD_CMD_EQSTOP_S         27
1838 #define FW_EQ_OFLD_CMD_EQSTOP_V(x)      ((x) << FW_EQ_OFLD_CMD_EQSTOP_S)
1839 #define FW_EQ_OFLD_CMD_EQSTOP_F         FW_EQ_OFLD_CMD_EQSTOP_V(1U)
1840
1841 #define FW_EQ_OFLD_CMD_EQID_S           0
1842 #define FW_EQ_OFLD_CMD_EQID_M           0xfffff
1843 #define FW_EQ_OFLD_CMD_EQID_V(x)        ((x) << FW_EQ_OFLD_CMD_EQID_S)
1844 #define FW_EQ_OFLD_CMD_EQID_G(x)        \
1845         (((x) >> FW_EQ_OFLD_CMD_EQID_S) & FW_EQ_OFLD_CMD_EQID_M)
1846
1847 #define FW_EQ_OFLD_CMD_PHYSEQID_S       0
1848 #define FW_EQ_OFLD_CMD_PHYSEQID_M       0xfffff
1849 #define FW_EQ_OFLD_CMD_PHYSEQID_G(x)    \
1850         (((x) >> FW_EQ_OFLD_CMD_PHYSEQID_S) & FW_EQ_OFLD_CMD_PHYSEQID_M)
1851
1852 #define FW_EQ_OFLD_CMD_FETCHSZM_S       26
1853 #define FW_EQ_OFLD_CMD_FETCHSZM_V(x)    ((x) << FW_EQ_OFLD_CMD_FETCHSZM_S)
1854
1855 #define FW_EQ_OFLD_CMD_STATUSPGNS_S     25
1856 #define FW_EQ_OFLD_CMD_STATUSPGNS_V(x)  ((x) << FW_EQ_OFLD_CMD_STATUSPGNS_S)
1857
1858 #define FW_EQ_OFLD_CMD_STATUSPGRO_S     24
1859 #define FW_EQ_OFLD_CMD_STATUSPGRO_V(x)  ((x) << FW_EQ_OFLD_CMD_STATUSPGRO_S)
1860
1861 #define FW_EQ_OFLD_CMD_FETCHNS_S        23
1862 #define FW_EQ_OFLD_CMD_FETCHNS_V(x)     ((x) << FW_EQ_OFLD_CMD_FETCHNS_S)
1863
1864 #define FW_EQ_OFLD_CMD_FETCHRO_S        22
1865 #define FW_EQ_OFLD_CMD_FETCHRO_V(x)     ((x) << FW_EQ_OFLD_CMD_FETCHRO_S)
1866 #define FW_EQ_OFLD_CMD_FETCHRO_F        FW_EQ_OFLD_CMD_FETCHRO_V(1U)
1867
1868 #define FW_EQ_OFLD_CMD_HOSTFCMODE_S     20
1869 #define FW_EQ_OFLD_CMD_HOSTFCMODE_V(x)  ((x) << FW_EQ_OFLD_CMD_HOSTFCMODE_S)
1870
1871 #define FW_EQ_OFLD_CMD_CPRIO_S          19
1872 #define FW_EQ_OFLD_CMD_CPRIO_V(x)       ((x) << FW_EQ_OFLD_CMD_CPRIO_S)
1873
1874 #define FW_EQ_OFLD_CMD_ONCHIP_S         18
1875 #define FW_EQ_OFLD_CMD_ONCHIP_V(x)      ((x) << FW_EQ_OFLD_CMD_ONCHIP_S)
1876
1877 #define FW_EQ_OFLD_CMD_PCIECHN_S        16
1878 #define FW_EQ_OFLD_CMD_PCIECHN_V(x)     ((x) << FW_EQ_OFLD_CMD_PCIECHN_S)
1879
1880 #define FW_EQ_OFLD_CMD_IQID_S           0
1881 #define FW_EQ_OFLD_CMD_IQID_V(x)        ((x) << FW_EQ_OFLD_CMD_IQID_S)
1882
1883 #define FW_EQ_OFLD_CMD_DCAEN_S          31
1884 #define FW_EQ_OFLD_CMD_DCAEN_V(x)       ((x) << FW_EQ_OFLD_CMD_DCAEN_S)
1885
1886 #define FW_EQ_OFLD_CMD_DCACPU_S         26
1887 #define FW_EQ_OFLD_CMD_DCACPU_V(x)      ((x) << FW_EQ_OFLD_CMD_DCACPU_S)
1888
1889 #define FW_EQ_OFLD_CMD_FBMIN_S          23
1890 #define FW_EQ_OFLD_CMD_FBMIN_V(x)       ((x) << FW_EQ_OFLD_CMD_FBMIN_S)
1891
1892 #define FW_EQ_OFLD_CMD_FBMAX_S          20
1893 #define FW_EQ_OFLD_CMD_FBMAX_V(x)       ((x) << FW_EQ_OFLD_CMD_FBMAX_S)
1894
1895 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_S           19
1896 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_V(x)        \
1897         ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESHO_S)
1898
1899 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_S    16
1900 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESH_S)
1901
1902 #define FW_EQ_OFLD_CMD_EQSIZE_S         0
1903 #define FW_EQ_OFLD_CMD_EQSIZE_V(x)      ((x) << FW_EQ_OFLD_CMD_EQSIZE_S)
1904
1905 /*
1906  * Macros for VIID parsing:
1907  * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
1908  */
1909
1910 #define FW_VIID_PFN_S           8
1911 #define FW_VIID_PFN_M           0x7
1912 #define FW_VIID_PFN_G(x)        (((x) >> FW_VIID_PFN_S) & FW_VIID_PFN_M)
1913
1914 #define FW_VIID_VIVLD_S         7
1915 #define FW_VIID_VIVLD_M         0x1
1916 #define FW_VIID_VIVLD_G(x)      (((x) >> FW_VIID_VIVLD_S) & FW_VIID_VIVLD_M)
1917
1918 #define FW_VIID_VIN_S           0
1919 #define FW_VIID_VIN_M           0x7F
1920 #define FW_VIID_VIN_G(x)        (((x) >> FW_VIID_VIN_S) & FW_VIID_VIN_M)
1921
1922 struct fw_vi_cmd {
1923         __be32 op_to_vfn;
1924         __be32 alloc_to_len16;
1925         __be16 type_viid;
1926         u8 mac[6];
1927         u8 portid_pkd;
1928         u8 nmac;
1929         u8 nmac0[6];
1930         __be16 rsssize_pkd;
1931         u8 nmac1[6];
1932         __be16 idsiiq_pkd;
1933         u8 nmac2[6];
1934         __be16 idseiq_pkd;
1935         u8 nmac3[6];
1936         __be64 r9;
1937         __be64 r10;
1938 };
1939
1940 #define FW_VI_CMD_PFN_S         8
1941 #define FW_VI_CMD_PFN_V(x)      ((x) << FW_VI_CMD_PFN_S)
1942
1943 #define FW_VI_CMD_VFN_S         0
1944 #define FW_VI_CMD_VFN_V(x)      ((x) << FW_VI_CMD_VFN_S)
1945
1946 #define FW_VI_CMD_ALLOC_S       31
1947 #define FW_VI_CMD_ALLOC_V(x)    ((x) << FW_VI_CMD_ALLOC_S)
1948 #define FW_VI_CMD_ALLOC_F       FW_VI_CMD_ALLOC_V(1U)
1949
1950 #define FW_VI_CMD_FREE_S        30
1951 #define FW_VI_CMD_FREE_V(x)     ((x) << FW_VI_CMD_FREE_S)
1952 #define FW_VI_CMD_FREE_F        FW_VI_CMD_FREE_V(1U)
1953
1954 #define FW_VI_CMD_VIID_S        0
1955 #define FW_VI_CMD_VIID_M        0xfff
1956 #define FW_VI_CMD_VIID_V(x)     ((x) << FW_VI_CMD_VIID_S)
1957 #define FW_VI_CMD_VIID_G(x)     (((x) >> FW_VI_CMD_VIID_S) & FW_VI_CMD_VIID_M)
1958
1959 #define FW_VI_CMD_PORTID_S      4
1960 #define FW_VI_CMD_PORTID_M      0xf
1961 #define FW_VI_CMD_PORTID_V(x)   ((x) << FW_VI_CMD_PORTID_S)
1962 #define FW_VI_CMD_PORTID_G(x)   \
1963         (((x) >> FW_VI_CMD_PORTID_S) & FW_VI_CMD_PORTID_M)
1964
1965 #define FW_VI_CMD_RSSSIZE_S     0
1966 #define FW_VI_CMD_RSSSIZE_M     0x7ff
1967 #define FW_VI_CMD_RSSSIZE_G(x)  \
1968         (((x) >> FW_VI_CMD_RSSSIZE_S) & FW_VI_CMD_RSSSIZE_M)
1969
1970 /* Special VI_MAC command index ids */
1971 #define FW_VI_MAC_ADD_MAC               0x3FF
1972 #define FW_VI_MAC_ADD_PERSIST_MAC       0x3FE
1973 #define FW_VI_MAC_MAC_BASED_FREE        0x3FD
1974 #define FW_CLS_TCAM_NUM_ENTRIES         336
1975
1976 enum fw_vi_mac_smac {
1977         FW_VI_MAC_MPS_TCAM_ENTRY,
1978         FW_VI_MAC_MPS_TCAM_ONLY,
1979         FW_VI_MAC_SMT_ONLY,
1980         FW_VI_MAC_SMT_AND_MPSTCAM
1981 };
1982
1983 enum fw_vi_mac_result {
1984         FW_VI_MAC_R_SUCCESS,
1985         FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
1986         FW_VI_MAC_R_SMAC_FAIL,
1987         FW_VI_MAC_R_F_ACL_CHECK
1988 };
1989
1990 struct fw_vi_mac_cmd {
1991         __be32 op_to_viid;
1992         __be32 freemacs_to_len16;
1993         union fw_vi_mac {
1994                 struct fw_vi_mac_exact {
1995                         __be16 valid_to_idx;
1996                         u8 macaddr[6];
1997                 } exact[7];
1998                 struct fw_vi_mac_hash {
1999                         __be64 hashvec;
2000                 } hash;
2001         } u;
2002 };
2003
2004 #define FW_VI_MAC_CMD_VIID_S    0
2005 #define FW_VI_MAC_CMD_VIID_V(x) ((x) << FW_VI_MAC_CMD_VIID_S)
2006
2007 #define FW_VI_MAC_CMD_FREEMACS_S        31
2008 #define FW_VI_MAC_CMD_FREEMACS_V(x)     ((x) << FW_VI_MAC_CMD_FREEMACS_S)
2009
2010 #define FW_VI_MAC_CMD_HASHVECEN_S       23
2011 #define FW_VI_MAC_CMD_HASHVECEN_V(x)    ((x) << FW_VI_MAC_CMD_HASHVECEN_S)
2012 #define FW_VI_MAC_CMD_HASHVECEN_F       FW_VI_MAC_CMD_HASHVECEN_V(1U)
2013
2014 #define FW_VI_MAC_CMD_HASHUNIEN_S       22
2015 #define FW_VI_MAC_CMD_HASHUNIEN_V(x)    ((x) << FW_VI_MAC_CMD_HASHUNIEN_S)
2016
2017 #define FW_VI_MAC_CMD_VALID_S           15
2018 #define FW_VI_MAC_CMD_VALID_V(x)        ((x) << FW_VI_MAC_CMD_VALID_S)
2019 #define FW_VI_MAC_CMD_VALID_F   FW_VI_MAC_CMD_VALID_V(1U)
2020
2021 #define FW_VI_MAC_CMD_PRIO_S    12
2022 #define FW_VI_MAC_CMD_PRIO_V(x) ((x) << FW_VI_MAC_CMD_PRIO_S)
2023
2024 #define FW_VI_MAC_CMD_SMAC_RESULT_S     10
2025 #define FW_VI_MAC_CMD_SMAC_RESULT_M     0x3
2026 #define FW_VI_MAC_CMD_SMAC_RESULT_V(x)  ((x) << FW_VI_MAC_CMD_SMAC_RESULT_S)
2027 #define FW_VI_MAC_CMD_SMAC_RESULT_G(x)  \
2028         (((x) >> FW_VI_MAC_CMD_SMAC_RESULT_S) & FW_VI_MAC_CMD_SMAC_RESULT_M)
2029
2030 #define FW_VI_MAC_CMD_IDX_S     0
2031 #define FW_VI_MAC_CMD_IDX_M     0x3ff
2032 #define FW_VI_MAC_CMD_IDX_V(x)  ((x) << FW_VI_MAC_CMD_IDX_S)
2033 #define FW_VI_MAC_CMD_IDX_G(x)  \
2034         (((x) >> FW_VI_MAC_CMD_IDX_S) & FW_VI_MAC_CMD_IDX_M)
2035
2036 #define FW_RXMODE_MTU_NO_CHG    65535
2037
2038 struct fw_vi_rxmode_cmd {
2039         __be32 op_to_viid;
2040         __be32 retval_len16;
2041         __be32 mtu_to_vlanexen;
2042         __be32 r4_lo;
2043 };
2044
2045 #define FW_VI_RXMODE_CMD_VIID_S         0
2046 #define FW_VI_RXMODE_CMD_VIID_V(x)      ((x) << FW_VI_RXMODE_CMD_VIID_S)
2047
2048 #define FW_VI_RXMODE_CMD_MTU_S          16
2049 #define FW_VI_RXMODE_CMD_MTU_M          0xffff
2050 #define FW_VI_RXMODE_CMD_MTU_V(x)       ((x) << FW_VI_RXMODE_CMD_MTU_S)
2051
2052 #define FW_VI_RXMODE_CMD_PROMISCEN_S    14
2053 #define FW_VI_RXMODE_CMD_PROMISCEN_M    0x3
2054 #define FW_VI_RXMODE_CMD_PROMISCEN_V(x) ((x) << FW_VI_RXMODE_CMD_PROMISCEN_S)
2055
2056 #define FW_VI_RXMODE_CMD_ALLMULTIEN_S           12
2057 #define FW_VI_RXMODE_CMD_ALLMULTIEN_M           0x3
2058 #define FW_VI_RXMODE_CMD_ALLMULTIEN_V(x)        \
2059         ((x) << FW_VI_RXMODE_CMD_ALLMULTIEN_S)
2060
2061 #define FW_VI_RXMODE_CMD_BROADCASTEN_S          10
2062 #define FW_VI_RXMODE_CMD_BROADCASTEN_M          0x3
2063 #define FW_VI_RXMODE_CMD_BROADCASTEN_V(x)       \
2064         ((x) << FW_VI_RXMODE_CMD_BROADCASTEN_S)
2065
2066 #define FW_VI_RXMODE_CMD_VLANEXEN_S     8
2067 #define FW_VI_RXMODE_CMD_VLANEXEN_M     0x3
2068 #define FW_VI_RXMODE_CMD_VLANEXEN_V(x)  ((x) << FW_VI_RXMODE_CMD_VLANEXEN_S)
2069
2070 struct fw_vi_enable_cmd {
2071         __be32 op_to_viid;
2072         __be32 ien_to_len16;
2073         __be16 blinkdur;
2074         __be16 r3;
2075         __be32 r4;
2076 };
2077
2078 #define FW_VI_ENABLE_CMD_VIID_S         0
2079 #define FW_VI_ENABLE_CMD_VIID_V(x)      ((x) << FW_VI_ENABLE_CMD_VIID_S)
2080
2081 #define FW_VI_ENABLE_CMD_IEN_S          31
2082 #define FW_VI_ENABLE_CMD_IEN_V(x)       ((x) << FW_VI_ENABLE_CMD_IEN_S)
2083
2084 #define FW_VI_ENABLE_CMD_EEN_S          30
2085 #define FW_VI_ENABLE_CMD_EEN_V(x)       ((x) << FW_VI_ENABLE_CMD_EEN_S)
2086
2087 #define FW_VI_ENABLE_CMD_LED_S          29
2088 #define FW_VI_ENABLE_CMD_LED_V(x)       ((x) << FW_VI_ENABLE_CMD_LED_S)
2089 #define FW_VI_ENABLE_CMD_LED_F  FW_VI_ENABLE_CMD_LED_V(1U)
2090
2091 #define FW_VI_ENABLE_CMD_DCB_INFO_S     28
2092 #define FW_VI_ENABLE_CMD_DCB_INFO_V(x)  ((x) << FW_VI_ENABLE_CMD_DCB_INFO_S)
2093
2094 /* VI VF stats offset definitions */
2095 #define VI_VF_NUM_STATS 16
2096 enum fw_vi_stats_vf_index {
2097         FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
2098         FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
2099         FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
2100         FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
2101         FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
2102         FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
2103         FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
2104         FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
2105         FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
2106         FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
2107         FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
2108         FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
2109         FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
2110         FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
2111         FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
2112         FW_VI_VF_STAT_RX_ERR_FRAMES_IX
2113 };
2114
2115 /* VI PF stats offset definitions */
2116 #define VI_PF_NUM_STATS 17
2117 enum fw_vi_stats_pf_index {
2118         FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
2119         FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
2120         FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
2121         FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
2122         FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
2123         FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
2124         FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
2125         FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
2126         FW_VI_PF_STAT_RX_BYTES_IX,
2127         FW_VI_PF_STAT_RX_FRAMES_IX,
2128         FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
2129         FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
2130         FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
2131         FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
2132         FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
2133         FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
2134         FW_VI_PF_STAT_RX_ERR_FRAMES_IX
2135 };
2136
2137 struct fw_vi_stats_cmd {
2138         __be32 op_to_viid;
2139         __be32 retval_len16;
2140         union fw_vi_stats {
2141                 struct fw_vi_stats_ctl {
2142                         __be16 nstats_ix;
2143                         __be16 r6;
2144                         __be32 r7;
2145                         __be64 stat0;
2146                         __be64 stat1;
2147                         __be64 stat2;
2148                         __be64 stat3;
2149                         __be64 stat4;
2150                         __be64 stat5;
2151                 } ctl;
2152                 struct fw_vi_stats_pf {
2153                         __be64 tx_bcast_bytes;
2154                         __be64 tx_bcast_frames;
2155                         __be64 tx_mcast_bytes;
2156                         __be64 tx_mcast_frames;
2157                         __be64 tx_ucast_bytes;
2158                         __be64 tx_ucast_frames;
2159                         __be64 tx_offload_bytes;
2160                         __be64 tx_offload_frames;
2161                         __be64 rx_pf_bytes;
2162                         __be64 rx_pf_frames;
2163                         __be64 rx_bcast_bytes;
2164                         __be64 rx_bcast_frames;
2165                         __be64 rx_mcast_bytes;
2166                         __be64 rx_mcast_frames;
2167                         __be64 rx_ucast_bytes;
2168                         __be64 rx_ucast_frames;
2169                         __be64 rx_err_frames;
2170                 } pf;
2171                 struct fw_vi_stats_vf {
2172                         __be64 tx_bcast_bytes;
2173                         __be64 tx_bcast_frames;
2174                         __be64 tx_mcast_bytes;
2175                         __be64 tx_mcast_frames;
2176                         __be64 tx_ucast_bytes;
2177                         __be64 tx_ucast_frames;
2178                         __be64 tx_drop_frames;
2179                         __be64 tx_offload_bytes;
2180                         __be64 tx_offload_frames;
2181                         __be64 rx_bcast_bytes;
2182                         __be64 rx_bcast_frames;
2183                         __be64 rx_mcast_bytes;
2184                         __be64 rx_mcast_frames;
2185                         __be64 rx_ucast_bytes;
2186                         __be64 rx_ucast_frames;
2187                         __be64 rx_err_frames;
2188                 } vf;
2189         } u;
2190 };
2191
2192 #define FW_VI_STATS_CMD_VIID_S          0
2193 #define FW_VI_STATS_CMD_VIID_V(x)       ((x) << FW_VI_STATS_CMD_VIID_S)
2194
2195 #define FW_VI_STATS_CMD_NSTATS_S        12
2196 #define FW_VI_STATS_CMD_NSTATS_V(x)     ((x) << FW_VI_STATS_CMD_NSTATS_S)
2197
2198 #define FW_VI_STATS_CMD_IX_S    0
2199 #define FW_VI_STATS_CMD_IX_V(x) ((x) << FW_VI_STATS_CMD_IX_S)
2200
2201 struct fw_acl_mac_cmd {
2202         __be32 op_to_vfn;
2203         __be32 en_to_len16;
2204         u8 nmac;
2205         u8 r3[7];
2206         __be16 r4;
2207         u8 macaddr0[6];
2208         __be16 r5;
2209         u8 macaddr1[6];
2210         __be16 r6;
2211         u8 macaddr2[6];
2212         __be16 r7;
2213         u8 macaddr3[6];
2214 };
2215
2216 #define FW_ACL_MAC_CMD_PFN_S    8
2217 #define FW_ACL_MAC_CMD_PFN_V(x) ((x) << FW_ACL_MAC_CMD_PFN_S)
2218
2219 #define FW_ACL_MAC_CMD_VFN_S    0
2220 #define FW_ACL_MAC_CMD_VFN_V(x) ((x) << FW_ACL_MAC_CMD_VFN_S)
2221
2222 #define FW_ACL_MAC_CMD_EN_S     31
2223 #define FW_ACL_MAC_CMD_EN_V(x)  ((x) << FW_ACL_MAC_CMD_EN_S)
2224
2225 struct fw_acl_vlan_cmd {
2226         __be32 op_to_vfn;
2227         __be32 en_to_len16;
2228         u8 nvlan;
2229         u8 dropnovlan_fm;
2230         u8 r3_lo[6];
2231         __be16 vlanid[16];
2232 };
2233
2234 #define FW_ACL_VLAN_CMD_PFN_S           8
2235 #define FW_ACL_VLAN_CMD_PFN_V(x)        ((x) << FW_ACL_VLAN_CMD_PFN_S)
2236
2237 #define FW_ACL_VLAN_CMD_VFN_S           0
2238 #define FW_ACL_VLAN_CMD_VFN_V(x)        ((x) << FW_ACL_VLAN_CMD_VFN_S)
2239
2240 #define FW_ACL_VLAN_CMD_EN_S    31
2241 #define FW_ACL_VLAN_CMD_EN_V(x) ((x) << FW_ACL_VLAN_CMD_EN_S)
2242
2243 #define FW_ACL_VLAN_CMD_DROPNOVLAN_S    7
2244 #define FW_ACL_VLAN_CMD_DROPNOVLAN_V(x) ((x) << FW_ACL_VLAN_CMD_DROPNOVLAN_S)
2245
2246 #define FW_ACL_VLAN_CMD_FM_S    6
2247 #define FW_ACL_VLAN_CMD_FM_V(x) ((x) << FW_ACL_VLAN_CMD_FM_S)
2248
2249 enum fw_port_cap {
2250         FW_PORT_CAP_SPEED_100M          = 0x0001,
2251         FW_PORT_CAP_SPEED_1G            = 0x0002,
2252         FW_PORT_CAP_SPEED_25G           = 0x0004,
2253         FW_PORT_CAP_SPEED_10G           = 0x0008,
2254         FW_PORT_CAP_SPEED_40G           = 0x0010,
2255         FW_PORT_CAP_SPEED_100G          = 0x0020,
2256         FW_PORT_CAP_FC_RX               = 0x0040,
2257         FW_PORT_CAP_FC_TX               = 0x0080,
2258         FW_PORT_CAP_ANEG                = 0x0100,
2259         FW_PORT_CAP_MDIX                = 0x0200,
2260         FW_PORT_CAP_MDIAUTO             = 0x0400,
2261         FW_PORT_CAP_FEC                 = 0x0800,
2262         FW_PORT_CAP_TECHKR              = 0x1000,
2263         FW_PORT_CAP_TECHKX4             = 0x2000,
2264         FW_PORT_CAP_802_3_PAUSE         = 0x4000,
2265         FW_PORT_CAP_802_3_ASM_DIR       = 0x8000,
2266 };
2267
2268 #define FW_PORT_CAP_SPEED_S     0
2269 #define FW_PORT_CAP_SPEED_M     0x3f
2270 #define FW_PORT_CAP_SPEED_V(x)  ((x) << FW_PORT_CAP_SPEED_S)
2271 #define FW_PORT_CAP_SPEED_G(x) \
2272         (((x) >> FW_PORT_CAP_SPEED_S) & FW_PORT_CAP_SPEED_M)
2273
2274 enum fw_port_mdi {
2275         FW_PORT_CAP_MDI_UNCHANGED,
2276         FW_PORT_CAP_MDI_AUTO,
2277         FW_PORT_CAP_MDI_F_STRAIGHT,
2278         FW_PORT_CAP_MDI_F_CROSSOVER
2279 };
2280
2281 #define FW_PORT_CAP_MDI_S 9
2282 #define FW_PORT_CAP_MDI_V(x) ((x) << FW_PORT_CAP_MDI_S)
2283
2284 enum fw_port_action {
2285         FW_PORT_ACTION_L1_CFG           = 0x0001,
2286         FW_PORT_ACTION_L2_CFG           = 0x0002,
2287         FW_PORT_ACTION_GET_PORT_INFO    = 0x0003,
2288         FW_PORT_ACTION_L2_PPP_CFG       = 0x0004,
2289         FW_PORT_ACTION_L2_DCB_CFG       = 0x0005,
2290         FW_PORT_ACTION_DCB_READ_TRANS   = 0x0006,
2291         FW_PORT_ACTION_DCB_READ_RECV    = 0x0007,
2292         FW_PORT_ACTION_DCB_READ_DET     = 0x0008,
2293         FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
2294         FW_PORT_ACTION_L1_LOW_PWR_EN    = 0x0011,
2295         FW_PORT_ACTION_L2_WOL_MODE_EN   = 0x0012,
2296         FW_PORT_ACTION_LPBK_TO_NORMAL   = 0x0020,
2297         FW_PORT_ACTION_L1_LPBK          = 0x0021,
2298         FW_PORT_ACTION_L1_PMA_LPBK      = 0x0022,
2299         FW_PORT_ACTION_L1_PCS_LPBK      = 0x0023,
2300         FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024,
2301         FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025,
2302         FW_PORT_ACTION_PHY_RESET        = 0x0040,
2303         FW_PORT_ACTION_PMA_RESET        = 0x0041,
2304         FW_PORT_ACTION_PCS_RESET        = 0x0042,
2305         FW_PORT_ACTION_PHYXS_RESET      = 0x0043,
2306         FW_PORT_ACTION_DTEXS_REEST      = 0x0044,
2307         FW_PORT_ACTION_AN_RESET         = 0x0045
2308 };
2309
2310 enum fw_port_l2cfg_ctlbf {
2311         FW_PORT_L2_CTLBF_OVLAN0 = 0x01,
2312         FW_PORT_L2_CTLBF_OVLAN1 = 0x02,
2313         FW_PORT_L2_CTLBF_OVLAN2 = 0x04,
2314         FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
2315         FW_PORT_L2_CTLBF_IVLAN  = 0x10,
2316         FW_PORT_L2_CTLBF_TXIPG  = 0x20
2317 };
2318
2319 enum fw_port_dcb_versions {
2320         FW_PORT_DCB_VER_UNKNOWN,
2321         FW_PORT_DCB_VER_CEE1D0,
2322         FW_PORT_DCB_VER_CEE1D01,
2323         FW_PORT_DCB_VER_IEEE,
2324         FW_PORT_DCB_VER_AUTO = 7
2325 };
2326
2327 enum fw_port_dcb_cfg {
2328         FW_PORT_DCB_CFG_PG      = 0x01,
2329         FW_PORT_DCB_CFG_PFC     = 0x02,
2330         FW_PORT_DCB_CFG_APPL    = 0x04
2331 };
2332
2333 enum fw_port_dcb_cfg_rc {
2334         FW_PORT_DCB_CFG_SUCCESS = 0x0,
2335         FW_PORT_DCB_CFG_ERROR   = 0x1
2336 };
2337
2338 enum fw_port_dcb_type {
2339         FW_PORT_DCB_TYPE_PGID           = 0x00,
2340         FW_PORT_DCB_TYPE_PGRATE         = 0x01,
2341         FW_PORT_DCB_TYPE_PRIORATE       = 0x02,
2342         FW_PORT_DCB_TYPE_PFC            = 0x03,
2343         FW_PORT_DCB_TYPE_APP_ID         = 0x04,
2344         FW_PORT_DCB_TYPE_CONTROL        = 0x05,
2345 };
2346
2347 enum fw_port_dcb_feature_state {
2348         FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0,
2349         FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1,
2350         FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2,
2351         FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3,
2352 };
2353
2354 struct fw_port_cmd {
2355         __be32 op_to_portid;
2356         __be32 action_to_len16;
2357         union fw_port {
2358                 struct fw_port_l1cfg {
2359                         __be32 rcap;
2360                         __be32 r;
2361                 } l1cfg;
2362                 struct fw_port_l2cfg {
2363                         __u8   ctlbf;
2364                         __u8   ovlan3_to_ivlan0;
2365                         __be16 ivlantype;
2366                         __be16 txipg_force_pinfo;
2367                         __be16 mtu;
2368                         __be16 ovlan0mask;
2369                         __be16 ovlan0type;
2370                         __be16 ovlan1mask;
2371                         __be16 ovlan1type;
2372                         __be16 ovlan2mask;
2373                         __be16 ovlan2type;
2374                         __be16 ovlan3mask;
2375                         __be16 ovlan3type;
2376                 } l2cfg;
2377                 struct fw_port_info {
2378                         __be32 lstatus_to_modtype;
2379                         __be16 pcap;
2380                         __be16 acap;
2381                         __be16 mtu;
2382                         __u8   cbllen;
2383                         __u8   auxlinfo;
2384                         __u8   dcbxdis_pkd;
2385                         __u8   r8_lo;
2386                         __be16 lpacap;
2387                         __be64 r9;
2388                 } info;
2389                 struct fw_port_diags {
2390                         __u8   diagop;
2391                         __u8   r[3];
2392                         __be32 diagval;
2393                 } diags;
2394                 union fw_port_dcb {
2395                         struct fw_port_dcb_pgid {
2396                                 __u8   type;
2397                                 __u8   apply_pkd;
2398                                 __u8   r10_lo[2];
2399                                 __be32 pgid;
2400                                 __be64 r11;
2401                         } pgid;
2402                         struct fw_port_dcb_pgrate {
2403                                 __u8   type;
2404                                 __u8   apply_pkd;
2405                                 __u8   r10_lo[5];
2406                                 __u8   num_tcs_supported;
2407                                 __u8   pgrate[8];
2408                                 __u8   tsa[8];
2409                         } pgrate;
2410                         struct fw_port_dcb_priorate {
2411                                 __u8   type;
2412                                 __u8   apply_pkd;
2413                                 __u8   r10_lo[6];
2414                                 __u8   strict_priorate[8];
2415                         } priorate;
2416                         struct fw_port_dcb_pfc {
2417                                 __u8   type;
2418                                 __u8   pfcen;
2419                                 __u8   r10[5];
2420                                 __u8   max_pfc_tcs;
2421                                 __be64 r11;
2422                         } pfc;
2423                         struct fw_port_app_priority {
2424                                 __u8   type;
2425                                 __u8   r10[2];
2426                                 __u8   idx;
2427                                 __u8   user_prio_map;
2428                                 __u8   sel_field;
2429                                 __be16 protocolid;
2430                                 __be64 r12;
2431                         } app_priority;
2432                         struct fw_port_dcb_control {
2433                                 __u8   type;
2434                                 __u8   all_syncd_pkd;
2435                                 __be16 dcb_version_to_app_state;
2436                                 __be32 r11;
2437                                 __be64 r12;
2438                         } control;
2439                 } dcb;
2440         } u;
2441 };
2442
2443 #define FW_PORT_CMD_READ_S      22
2444 #define FW_PORT_CMD_READ_V(x)   ((x) << FW_PORT_CMD_READ_S)
2445 #define FW_PORT_CMD_READ_F      FW_PORT_CMD_READ_V(1U)
2446
2447 #define FW_PORT_CMD_PORTID_S    0
2448 #define FW_PORT_CMD_PORTID_M    0xf
2449 #define FW_PORT_CMD_PORTID_V(x) ((x) << FW_PORT_CMD_PORTID_S)
2450 #define FW_PORT_CMD_PORTID_G(x) \
2451         (((x) >> FW_PORT_CMD_PORTID_S) & FW_PORT_CMD_PORTID_M)
2452
2453 #define FW_PORT_CMD_ACTION_S    16
2454 #define FW_PORT_CMD_ACTION_M    0xffff
2455 #define FW_PORT_CMD_ACTION_V(x) ((x) << FW_PORT_CMD_ACTION_S)
2456 #define FW_PORT_CMD_ACTION_G(x) \
2457         (((x) >> FW_PORT_CMD_ACTION_S) & FW_PORT_CMD_ACTION_M)
2458
2459 #define FW_PORT_CMD_OVLAN3_S    7
2460 #define FW_PORT_CMD_OVLAN3_V(x) ((x) << FW_PORT_CMD_OVLAN3_S)
2461
2462 #define FW_PORT_CMD_OVLAN2_S    6
2463 #define FW_PORT_CMD_OVLAN2_V(x) ((x) << FW_PORT_CMD_OVLAN2_S)
2464
2465 #define FW_PORT_CMD_OVLAN1_S    5
2466 #define FW_PORT_CMD_OVLAN1_V(x) ((x) << FW_PORT_CMD_OVLAN1_S)
2467
2468 #define FW_PORT_CMD_OVLAN0_S    4
2469 #define FW_PORT_CMD_OVLAN0_V(x) ((x) << FW_PORT_CMD_OVLAN0_S)
2470
2471 #define FW_PORT_CMD_IVLAN0_S    3
2472 #define FW_PORT_CMD_IVLAN0_V(x) ((x) << FW_PORT_CMD_IVLAN0_S)
2473
2474 #define FW_PORT_CMD_TXIPG_S     3
2475 #define FW_PORT_CMD_TXIPG_V(x)  ((x) << FW_PORT_CMD_TXIPG_S)
2476
2477 #define FW_PORT_CMD_LSTATUS_S           31
2478 #define FW_PORT_CMD_LSTATUS_M           0x1
2479 #define FW_PORT_CMD_LSTATUS_V(x)        ((x) << FW_PORT_CMD_LSTATUS_S)
2480 #define FW_PORT_CMD_LSTATUS_G(x)        \
2481         (((x) >> FW_PORT_CMD_LSTATUS_S) & FW_PORT_CMD_LSTATUS_M)
2482 #define FW_PORT_CMD_LSTATUS_F   FW_PORT_CMD_LSTATUS_V(1U)
2483
2484 #define FW_PORT_CMD_LSPEED_S    24
2485 #define FW_PORT_CMD_LSPEED_M    0x3f
2486 #define FW_PORT_CMD_LSPEED_V(x) ((x) << FW_PORT_CMD_LSPEED_S)
2487 #define FW_PORT_CMD_LSPEED_G(x) \
2488         (((x) >> FW_PORT_CMD_LSPEED_S) & FW_PORT_CMD_LSPEED_M)
2489
2490 #define FW_PORT_CMD_TXPAUSE_S           23
2491 #define FW_PORT_CMD_TXPAUSE_V(x)        ((x) << FW_PORT_CMD_TXPAUSE_S)
2492 #define FW_PORT_CMD_TXPAUSE_F   FW_PORT_CMD_TXPAUSE_V(1U)
2493
2494 #define FW_PORT_CMD_RXPAUSE_S           22
2495 #define FW_PORT_CMD_RXPAUSE_V(x)        ((x) << FW_PORT_CMD_RXPAUSE_S)
2496 #define FW_PORT_CMD_RXPAUSE_F   FW_PORT_CMD_RXPAUSE_V(1U)
2497
2498 #define FW_PORT_CMD_MDIOCAP_S           21
2499 #define FW_PORT_CMD_MDIOCAP_V(x)        ((x) << FW_PORT_CMD_MDIOCAP_S)
2500 #define FW_PORT_CMD_MDIOCAP_F   FW_PORT_CMD_MDIOCAP_V(1U)
2501
2502 #define FW_PORT_CMD_MDIOADDR_S          16
2503 #define FW_PORT_CMD_MDIOADDR_M          0x1f
2504 #define FW_PORT_CMD_MDIOADDR_G(x)       \
2505         (((x) >> FW_PORT_CMD_MDIOADDR_S) & FW_PORT_CMD_MDIOADDR_M)
2506
2507 #define FW_PORT_CMD_LPTXPAUSE_S         15
2508 #define FW_PORT_CMD_LPTXPAUSE_V(x)      ((x) << FW_PORT_CMD_LPTXPAUSE_S)
2509 #define FW_PORT_CMD_LPTXPAUSE_F FW_PORT_CMD_LPTXPAUSE_V(1U)
2510
2511 #define FW_PORT_CMD_LPRXPAUSE_S         14
2512 #define FW_PORT_CMD_LPRXPAUSE_V(x)      ((x) << FW_PORT_CMD_LPRXPAUSE_S)
2513 #define FW_PORT_CMD_LPRXPAUSE_F FW_PORT_CMD_LPRXPAUSE_V(1U)
2514
2515 #define FW_PORT_CMD_PTYPE_S     8
2516 #define FW_PORT_CMD_PTYPE_M     0x1f
2517 #define FW_PORT_CMD_PTYPE_G(x)  \
2518         (((x) >> FW_PORT_CMD_PTYPE_S) & FW_PORT_CMD_PTYPE_M)
2519
2520 #define FW_PORT_CMD_LINKDNRC_S          5
2521 #define FW_PORT_CMD_LINKDNRC_M          0x7
2522 #define FW_PORT_CMD_LINKDNRC_G(x)       \
2523         (((x) >> FW_PORT_CMD_LINKDNRC_S) & FW_PORT_CMD_LINKDNRC_M)
2524
2525 #define FW_PORT_CMD_MODTYPE_S           0
2526 #define FW_PORT_CMD_MODTYPE_M           0x1f
2527 #define FW_PORT_CMD_MODTYPE_V(x)        ((x) << FW_PORT_CMD_MODTYPE_S)
2528 #define FW_PORT_CMD_MODTYPE_G(x)        \
2529         (((x) >> FW_PORT_CMD_MODTYPE_S) & FW_PORT_CMD_MODTYPE_M)
2530
2531 #define FW_PORT_CMD_DCBXDIS_S           7
2532 #define FW_PORT_CMD_DCBXDIS_V(x)        ((x) << FW_PORT_CMD_DCBXDIS_S)
2533 #define FW_PORT_CMD_DCBXDIS_F   FW_PORT_CMD_DCBXDIS_V(1U)
2534
2535 #define FW_PORT_CMD_APPLY_S     7
2536 #define FW_PORT_CMD_APPLY_V(x)  ((x) << FW_PORT_CMD_APPLY_S)
2537 #define FW_PORT_CMD_APPLY_F     FW_PORT_CMD_APPLY_V(1U)
2538
2539 #define FW_PORT_CMD_ALL_SYNCD_S         7
2540 #define FW_PORT_CMD_ALL_SYNCD_V(x)      ((x) << FW_PORT_CMD_ALL_SYNCD_S)
2541 #define FW_PORT_CMD_ALL_SYNCD_F FW_PORT_CMD_ALL_SYNCD_V(1U)
2542
2543 #define FW_PORT_CMD_DCB_VERSION_S       12
2544 #define FW_PORT_CMD_DCB_VERSION_M       0x7
2545 #define FW_PORT_CMD_DCB_VERSION_G(x)    \
2546         (((x) >> FW_PORT_CMD_DCB_VERSION_S) & FW_PORT_CMD_DCB_VERSION_M)
2547
2548 enum fw_port_type {
2549         FW_PORT_TYPE_FIBER_XFI,
2550         FW_PORT_TYPE_FIBER_XAUI,
2551         FW_PORT_TYPE_BT_SGMII,
2552         FW_PORT_TYPE_BT_XFI,
2553         FW_PORT_TYPE_BT_XAUI,
2554         FW_PORT_TYPE_KX4,
2555         FW_PORT_TYPE_CX4,
2556         FW_PORT_TYPE_KX,
2557         FW_PORT_TYPE_KR,
2558         FW_PORT_TYPE_SFP,
2559         FW_PORT_TYPE_BP_AP,
2560         FW_PORT_TYPE_BP4_AP,
2561         FW_PORT_TYPE_QSFP_10G,
2562         FW_PORT_TYPE_QSA,
2563         FW_PORT_TYPE_QSFP,
2564         FW_PORT_TYPE_BP40_BA,
2565         FW_PORT_TYPE_KR4_100G,
2566         FW_PORT_TYPE_CR4_QSFP,
2567         FW_PORT_TYPE_CR_QSFP,
2568         FW_PORT_TYPE_CR2_QSFP,
2569         FW_PORT_TYPE_SFP28,
2570
2571         FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_M
2572 };
2573
2574 enum fw_port_module_type {
2575         FW_PORT_MOD_TYPE_NA,
2576         FW_PORT_MOD_TYPE_LR,
2577         FW_PORT_MOD_TYPE_SR,
2578         FW_PORT_MOD_TYPE_ER,
2579         FW_PORT_MOD_TYPE_TWINAX_PASSIVE,
2580         FW_PORT_MOD_TYPE_TWINAX_ACTIVE,
2581         FW_PORT_MOD_TYPE_LRM,
2582         FW_PORT_MOD_TYPE_ERROR          = FW_PORT_CMD_MODTYPE_M - 3,
2583         FW_PORT_MOD_TYPE_UNKNOWN        = FW_PORT_CMD_MODTYPE_M - 2,
2584         FW_PORT_MOD_TYPE_NOTSUPPORTED   = FW_PORT_CMD_MODTYPE_M - 1,
2585
2586         FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_M
2587 };
2588
2589 enum fw_port_mod_sub_type {
2590         FW_PORT_MOD_SUB_TYPE_NA,
2591         FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
2592         FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
2593         FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
2594         FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
2595         FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
2596         FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
2597
2598         /* The following will never been in the VPD.  They are TWINAX cable
2599          * lengths decoded from SFP+ module i2c PROMs.  These should
2600          * almost certainly go somewhere else ...
2601          */
2602         FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
2603         FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
2604         FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
2605         FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
2606 };
2607
2608 enum fw_port_stats_tx_index {
2609         FW_STAT_TX_PORT_BYTES_IX = 0,
2610         FW_STAT_TX_PORT_FRAMES_IX,
2611         FW_STAT_TX_PORT_BCAST_IX,
2612         FW_STAT_TX_PORT_MCAST_IX,
2613         FW_STAT_TX_PORT_UCAST_IX,
2614         FW_STAT_TX_PORT_ERROR_IX,
2615         FW_STAT_TX_PORT_64B_IX,
2616         FW_STAT_TX_PORT_65B_127B_IX,
2617         FW_STAT_TX_PORT_128B_255B_IX,
2618         FW_STAT_TX_PORT_256B_511B_IX,
2619         FW_STAT_TX_PORT_512B_1023B_IX,
2620         FW_STAT_TX_PORT_1024B_1518B_IX,
2621         FW_STAT_TX_PORT_1519B_MAX_IX,
2622         FW_STAT_TX_PORT_DROP_IX,
2623         FW_STAT_TX_PORT_PAUSE_IX,
2624         FW_STAT_TX_PORT_PPP0_IX,
2625         FW_STAT_TX_PORT_PPP1_IX,
2626         FW_STAT_TX_PORT_PPP2_IX,
2627         FW_STAT_TX_PORT_PPP3_IX,
2628         FW_STAT_TX_PORT_PPP4_IX,
2629         FW_STAT_TX_PORT_PPP5_IX,
2630         FW_STAT_TX_PORT_PPP6_IX,
2631         FW_STAT_TX_PORT_PPP7_IX,
2632         FW_NUM_PORT_TX_STATS
2633 };
2634
2635 enum fw_port_stat_rx_index {
2636         FW_STAT_RX_PORT_BYTES_IX = 0,
2637         FW_STAT_RX_PORT_FRAMES_IX,
2638         FW_STAT_RX_PORT_BCAST_IX,
2639         FW_STAT_RX_PORT_MCAST_IX,
2640         FW_STAT_RX_PORT_UCAST_IX,
2641         FW_STAT_RX_PORT_MTU_ERROR_IX,
2642         FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
2643         FW_STAT_RX_PORT_CRC_ERROR_IX,
2644         FW_STAT_RX_PORT_LEN_ERROR_IX,
2645         FW_STAT_RX_PORT_SYM_ERROR_IX,
2646         FW_STAT_RX_PORT_64B_IX,
2647         FW_STAT_RX_PORT_65B_127B_IX,
2648         FW_STAT_RX_PORT_128B_255B_IX,
2649         FW_STAT_RX_PORT_256B_511B_IX,
2650         FW_STAT_RX_PORT_512B_1023B_IX,
2651         FW_STAT_RX_PORT_1024B_1518B_IX,
2652         FW_STAT_RX_PORT_1519B_MAX_IX,
2653         FW_STAT_RX_PORT_PAUSE_IX,
2654         FW_STAT_RX_PORT_PPP0_IX,
2655         FW_STAT_RX_PORT_PPP1_IX,
2656         FW_STAT_RX_PORT_PPP2_IX,
2657         FW_STAT_RX_PORT_PPP3_IX,
2658         FW_STAT_RX_PORT_PPP4_IX,
2659         FW_STAT_RX_PORT_PPP5_IX,
2660         FW_STAT_RX_PORT_PPP6_IX,
2661         FW_STAT_RX_PORT_PPP7_IX,
2662         FW_STAT_RX_PORT_LESS_64B_IX,
2663         FW_STAT_RX_PORT_MAC_ERROR_IX,
2664         FW_NUM_PORT_RX_STATS
2665 };
2666
2667 /* port stats */
2668 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + FW_NUM_PORT_RX_STATS)
2669
2670 struct fw_port_stats_cmd {
2671         __be32 op_to_portid;
2672         __be32 retval_len16;
2673         union fw_port_stats {
2674                 struct fw_port_stats_ctl {
2675                         u8 nstats_bg_bm;
2676                         u8 tx_ix;
2677                         __be16 r6;
2678                         __be32 r7;
2679                         __be64 stat0;
2680                         __be64 stat1;
2681                         __be64 stat2;
2682                         __be64 stat3;
2683                         __be64 stat4;
2684                         __be64 stat5;
2685                 } ctl;
2686                 struct fw_port_stats_all {
2687                         __be64 tx_bytes;
2688                         __be64 tx_frames;
2689                         __be64 tx_bcast;
2690                         __be64 tx_mcast;
2691                         __be64 tx_ucast;
2692                         __be64 tx_error;
2693                         __be64 tx_64b;
2694                         __be64 tx_65b_127b;
2695                         __be64 tx_128b_255b;
2696                         __be64 tx_256b_511b;
2697                         __be64 tx_512b_1023b;
2698                         __be64 tx_1024b_1518b;
2699                         __be64 tx_1519b_max;
2700                         __be64 tx_drop;
2701                         __be64 tx_pause;
2702                         __be64 tx_ppp0;
2703                         __be64 tx_ppp1;
2704                         __be64 tx_ppp2;
2705                         __be64 tx_ppp3;
2706                         __be64 tx_ppp4;
2707                         __be64 tx_ppp5;
2708                         __be64 tx_ppp6;
2709                         __be64 tx_ppp7;
2710                         __be64 rx_bytes;
2711                         __be64 rx_frames;
2712                         __be64 rx_bcast;
2713                         __be64 rx_mcast;
2714                         __be64 rx_ucast;
2715                         __be64 rx_mtu_error;
2716                         __be64 rx_mtu_crc_error;
2717                         __be64 rx_crc_error;
2718                         __be64 rx_len_error;
2719                         __be64 rx_sym_error;
2720                         __be64 rx_64b;
2721                         __be64 rx_65b_127b;
2722                         __be64 rx_128b_255b;
2723                         __be64 rx_256b_511b;
2724                         __be64 rx_512b_1023b;
2725                         __be64 rx_1024b_1518b;
2726                         __be64 rx_1519b_max;
2727                         __be64 rx_pause;
2728                         __be64 rx_ppp0;
2729                         __be64 rx_ppp1;
2730                         __be64 rx_ppp2;
2731                         __be64 rx_ppp3;
2732                         __be64 rx_ppp4;
2733                         __be64 rx_ppp5;
2734                         __be64 rx_ppp6;
2735                         __be64 rx_ppp7;
2736                         __be64 rx_less_64b;
2737                         __be64 rx_bg_drop;
2738                         __be64 rx_bg_trunc;
2739                 } all;
2740         } u;
2741 };
2742
2743 /* port loopback stats */
2744 #define FW_NUM_LB_STATS 16
2745 enum fw_port_lb_stats_index {
2746         FW_STAT_LB_PORT_BYTES_IX,
2747         FW_STAT_LB_PORT_FRAMES_IX,
2748         FW_STAT_LB_PORT_BCAST_IX,
2749         FW_STAT_LB_PORT_MCAST_IX,
2750         FW_STAT_LB_PORT_UCAST_IX,
2751         FW_STAT_LB_PORT_ERROR_IX,
2752         FW_STAT_LB_PORT_64B_IX,
2753         FW_STAT_LB_PORT_65B_127B_IX,
2754         FW_STAT_LB_PORT_128B_255B_IX,
2755         FW_STAT_LB_PORT_256B_511B_IX,
2756         FW_STAT_LB_PORT_512B_1023B_IX,
2757         FW_STAT_LB_PORT_1024B_1518B_IX,
2758         FW_STAT_LB_PORT_1519B_MAX_IX,
2759         FW_STAT_LB_PORT_DROP_FRAMES_IX
2760 };
2761
2762 struct fw_port_lb_stats_cmd {
2763         __be32 op_to_lbport;
2764         __be32 retval_len16;
2765         union fw_port_lb_stats {
2766                 struct fw_port_lb_stats_ctl {
2767                         u8 nstats_bg_bm;
2768                         u8 ix_pkd;
2769                         __be16 r6;
2770                         __be32 r7;
2771                         __be64 stat0;
2772                         __be64 stat1;
2773                         __be64 stat2;
2774                         __be64 stat3;
2775                         __be64 stat4;
2776                         __be64 stat5;
2777                 } ctl;
2778                 struct fw_port_lb_stats_all {
2779                         __be64 tx_bytes;
2780                         __be64 tx_frames;
2781                         __be64 tx_bcast;
2782                         __be64 tx_mcast;
2783                         __be64 tx_ucast;
2784                         __be64 tx_error;
2785                         __be64 tx_64b;
2786                         __be64 tx_65b_127b;
2787                         __be64 tx_128b_255b;
2788                         __be64 tx_256b_511b;
2789                         __be64 tx_512b_1023b;
2790                         __be64 tx_1024b_1518b;
2791                         __be64 tx_1519b_max;
2792                         __be64 rx_lb_drop;
2793                         __be64 rx_lb_trunc;
2794                 } all;
2795         } u;
2796 };
2797
2798 struct fw_rss_ind_tbl_cmd {
2799         __be32 op_to_viid;
2800         __be32 retval_len16;
2801         __be16 niqid;
2802         __be16 startidx;
2803         __be32 r3;
2804         __be32 iq0_to_iq2;
2805         __be32 iq3_to_iq5;
2806         __be32 iq6_to_iq8;
2807         __be32 iq9_to_iq11;
2808         __be32 iq12_to_iq14;
2809         __be32 iq15_to_iq17;
2810         __be32 iq18_to_iq20;
2811         __be32 iq21_to_iq23;
2812         __be32 iq24_to_iq26;
2813         __be32 iq27_to_iq29;
2814         __be32 iq30_iq31;
2815         __be32 r15_lo;
2816 };
2817
2818 #define FW_RSS_IND_TBL_CMD_VIID_S       0
2819 #define FW_RSS_IND_TBL_CMD_VIID_V(x)    ((x) << FW_RSS_IND_TBL_CMD_VIID_S)
2820
2821 #define FW_RSS_IND_TBL_CMD_IQ0_S        20
2822 #define FW_RSS_IND_TBL_CMD_IQ0_V(x)     ((x) << FW_RSS_IND_TBL_CMD_IQ0_S)
2823
2824 #define FW_RSS_IND_TBL_CMD_IQ1_S        10
2825 #define FW_RSS_IND_TBL_CMD_IQ1_V(x)     ((x) << FW_RSS_IND_TBL_CMD_IQ1_S)
2826
2827 #define FW_RSS_IND_TBL_CMD_IQ2_S        0
2828 #define FW_RSS_IND_TBL_CMD_IQ2_V(x)     ((x) << FW_RSS_IND_TBL_CMD_IQ2_S)
2829
2830 struct fw_rss_glb_config_cmd {
2831         __be32 op_to_write;
2832         __be32 retval_len16;
2833         union fw_rss_glb_config {
2834                 struct fw_rss_glb_config_manual {
2835                         __be32 mode_pkd;
2836                         __be32 r3;
2837                         __be64 r4;
2838                         __be64 r5;
2839                 } manual;
2840                 struct fw_rss_glb_config_basicvirtual {
2841                         __be32 mode_pkd;
2842                         __be32 synmapen_to_hashtoeplitz;
2843                         __be64 r8;
2844                         __be64 r9;
2845                 } basicvirtual;
2846         } u;
2847 };
2848
2849 #define FW_RSS_GLB_CONFIG_CMD_MODE_S    28
2850 #define FW_RSS_GLB_CONFIG_CMD_MODE_M    0xf
2851 #define FW_RSS_GLB_CONFIG_CMD_MODE_V(x) ((x) << FW_RSS_GLB_CONFIG_CMD_MODE_S)
2852 #define FW_RSS_GLB_CONFIG_CMD_MODE_G(x) \
2853         (((x) >> FW_RSS_GLB_CONFIG_CMD_MODE_S) & FW_RSS_GLB_CONFIG_CMD_MODE_M)
2854
2855 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL       0
2856 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
2857
2858 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S        8
2859 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(x)     \
2860         ((x) << FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S)
2861 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F        \
2862         FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(1U)
2863
2864 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S           7
2865 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(x)        \
2866         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S)
2867 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F   \
2868         FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(1U)
2869
2870 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S           6
2871 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(x)        \
2872         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S)
2873 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F   \
2874         FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(1U)
2875
2876 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S           5
2877 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(x)        \
2878         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S)
2879 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F   \
2880         FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(1U)
2881
2882 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S           4
2883 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(x)        \
2884         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S)
2885 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F   \
2886         FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(1U)
2887
2888 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S        3
2889 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(x)     \
2890         ((x) << FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S)
2891 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F        \
2892         FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(1U)
2893
2894 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S        2
2895 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(x)     \
2896         ((x) << FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S)
2897 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F        \
2898         FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(1U)
2899
2900 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S       1
2901 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(x)    \
2902         ((x) << FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S)
2903 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F       \
2904         FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(1U)
2905
2906 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S    0
2907 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(x) \
2908         ((x) << FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S)
2909 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F    \
2910         FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(1U)
2911
2912 struct fw_rss_vi_config_cmd {
2913         __be32 op_to_viid;
2914 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0)
2915         __be32 retval_len16;
2916         union fw_rss_vi_config {
2917                 struct fw_rss_vi_config_manual {
2918                         __be64 r3;
2919                         __be64 r4;
2920                         __be64 r5;
2921                 } manual;
2922                 struct fw_rss_vi_config_basicvirtual {
2923                         __be32 r6;
2924                         __be32 defaultq_to_udpen;
2925                         __be64 r9;
2926                         __be64 r10;
2927                 } basicvirtual;
2928         } u;
2929 };
2930
2931 #define FW_RSS_VI_CONFIG_CMD_VIID_S     0
2932 #define FW_RSS_VI_CONFIG_CMD_VIID_V(x)  ((x) << FW_RSS_VI_CONFIG_CMD_VIID_S)
2933
2934 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S         16
2935 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M         0x3ff
2936 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(x)      \
2937         ((x) << FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S)
2938 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(x)      \
2939         (((x) >> FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) & \
2940          FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M)
2941
2942 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S     4
2943 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(x)  \
2944         ((x) << FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S)
2945 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F     \
2946         FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(1U)
2947
2948 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S      3
2949 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(x)   \
2950         ((x) << FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S)
2951 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F      \
2952         FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(1U)
2953
2954 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S     2
2955 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(x)  \
2956         ((x) << FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S)
2957 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F     \
2958         FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(1U)
2959
2960 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S      1
2961 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(x)   \
2962         ((x) << FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S)
2963 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F      \
2964         FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(1U)
2965
2966 #define FW_RSS_VI_CONFIG_CMD_UDPEN_S    0
2967 #define FW_RSS_VI_CONFIG_CMD_UDPEN_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_UDPEN_S)
2968 #define FW_RSS_VI_CONFIG_CMD_UDPEN_F    FW_RSS_VI_CONFIG_CMD_UDPEN_V(1U)
2969
2970 struct fw_clip_cmd {
2971         __be32 op_to_write;
2972         __be32 alloc_to_len16;
2973         __be64 ip_hi;
2974         __be64 ip_lo;
2975         __be32 r4[2];
2976 };
2977
2978 #define FW_CLIP_CMD_ALLOC_S     31
2979 #define FW_CLIP_CMD_ALLOC_V(x)  ((x) << FW_CLIP_CMD_ALLOC_S)
2980 #define FW_CLIP_CMD_ALLOC_F     FW_CLIP_CMD_ALLOC_V(1U)
2981
2982 #define FW_CLIP_CMD_FREE_S      30
2983 #define FW_CLIP_CMD_FREE_V(x)   ((x) << FW_CLIP_CMD_FREE_S)
2984 #define FW_CLIP_CMD_FREE_F      FW_CLIP_CMD_FREE_V(1U)
2985
2986 enum fw_error_type {
2987         FW_ERROR_TYPE_EXCEPTION         = 0x0,
2988         FW_ERROR_TYPE_HWMODULE          = 0x1,
2989         FW_ERROR_TYPE_WR                = 0x2,
2990         FW_ERROR_TYPE_ACL               = 0x3,
2991 };
2992
2993 struct fw_error_cmd {
2994         __be32 op_to_type;
2995         __be32 len16_pkd;
2996         union fw_error {
2997                 struct fw_error_exception {
2998                         __be32 info[6];
2999                 } exception;
3000                 struct fw_error_hwmodule {
3001                         __be32 regaddr;
3002                         __be32 regval;
3003                 } hwmodule;
3004                 struct fw_error_wr {
3005                         __be16 cidx;
3006                         __be16 pfn_vfn;
3007                         __be32 eqid;
3008                         u8 wrhdr[16];
3009                 } wr;
3010                 struct fw_error_acl {
3011                         __be16 cidx;
3012                         __be16 pfn_vfn;
3013                         __be32 eqid;
3014                         __be16 mv_pkd;
3015                         u8 val[6];
3016                         __be64 r4;
3017                 } acl;
3018         } u;
3019 };
3020
3021 struct fw_debug_cmd {
3022         __be32 op_type;
3023         __be32 len16_pkd;
3024         union fw_debug {
3025                 struct fw_debug_assert {
3026                         __be32 fcid;
3027                         __be32 line;
3028                         __be32 x;
3029                         __be32 y;
3030                         u8 filename_0_7[8];
3031                         u8 filename_8_15[8];
3032                         __be64 r3;
3033                 } assert;
3034                 struct fw_debug_prt {
3035                         __be16 dprtstridx;
3036                         __be16 r3[3];
3037                         __be32 dprtstrparam0;
3038                         __be32 dprtstrparam1;
3039                         __be32 dprtstrparam2;
3040                         __be32 dprtstrparam3;
3041                 } prt;
3042         } u;
3043 };
3044
3045 #define FW_DEBUG_CMD_TYPE_S     0
3046 #define FW_DEBUG_CMD_TYPE_M     0xff
3047 #define FW_DEBUG_CMD_TYPE_G(x)  \
3048         (((x) >> FW_DEBUG_CMD_TYPE_S) & FW_DEBUG_CMD_TYPE_M)
3049
3050 #define PCIE_FW_ERR_S           31
3051 #define PCIE_FW_ERR_V(x)        ((x) << PCIE_FW_ERR_S)
3052 #define PCIE_FW_ERR_F           PCIE_FW_ERR_V(1U)
3053
3054 #define PCIE_FW_INIT_S          30
3055 #define PCIE_FW_INIT_V(x)       ((x) << PCIE_FW_INIT_S)
3056 #define PCIE_FW_INIT_F          PCIE_FW_INIT_V(1U)
3057
3058 #define PCIE_FW_HALT_S          29
3059 #define PCIE_FW_HALT_V(x)       ((x) << PCIE_FW_HALT_S)
3060 #define PCIE_FW_HALT_F          PCIE_FW_HALT_V(1U)
3061
3062 #define PCIE_FW_EVAL_S          24
3063 #define PCIE_FW_EVAL_M          0x7
3064 #define PCIE_FW_EVAL_G(x)       (((x) >> PCIE_FW_EVAL_S) & PCIE_FW_EVAL_M)
3065
3066 #define PCIE_FW_MASTER_VLD_S    15
3067 #define PCIE_FW_MASTER_VLD_V(x) ((x) << PCIE_FW_MASTER_VLD_S)
3068 #define PCIE_FW_MASTER_VLD_F    PCIE_FW_MASTER_VLD_V(1U)
3069
3070 #define PCIE_FW_MASTER_S        12
3071 #define PCIE_FW_MASTER_M        0x7
3072 #define PCIE_FW_MASTER_V(x)     ((x) << PCIE_FW_MASTER_S)
3073 #define PCIE_FW_MASTER_G(x)     (((x) >> PCIE_FW_MASTER_S) & PCIE_FW_MASTER_M)
3074
3075 struct fw_hdr {
3076         u8 ver;
3077         u8 chip;                        /* terminator chip type */
3078         __be16  len512;                 /* bin length in units of 512-bytes */
3079         __be32  fw_ver;                 /* firmware version */
3080         __be32  tp_microcode_ver;
3081         u8 intfver_nic;
3082         u8 intfver_vnic;
3083         u8 intfver_ofld;
3084         u8 intfver_ri;
3085         u8 intfver_iscsipdu;
3086         u8 intfver_iscsi;
3087         u8 intfver_fcoepdu;
3088         u8 intfver_fcoe;
3089         __u32   reserved2;
3090         __u32   reserved3;
3091         __u32   reserved4;
3092         __be32  flags;
3093         __be32  reserved6[23];
3094 };
3095
3096 enum fw_hdr_chip {
3097         FW_HDR_CHIP_T4,
3098         FW_HDR_CHIP_T5,
3099         FW_HDR_CHIP_T6
3100 };
3101
3102 #define FW_HDR_FW_VER_MAJOR_S   24
3103 #define FW_HDR_FW_VER_MAJOR_M   0xff
3104 #define FW_HDR_FW_VER_MAJOR_V(x) \
3105         ((x) << FW_HDR_FW_VER_MAJOR_S)
3106 #define FW_HDR_FW_VER_MAJOR_G(x) \
3107         (((x) >> FW_HDR_FW_VER_MAJOR_S) & FW_HDR_FW_VER_MAJOR_M)
3108
3109 #define FW_HDR_FW_VER_MINOR_S   16
3110 #define FW_HDR_FW_VER_MINOR_M   0xff
3111 #define FW_HDR_FW_VER_MINOR_V(x) \
3112         ((x) << FW_HDR_FW_VER_MINOR_S)
3113 #define FW_HDR_FW_VER_MINOR_G(x) \
3114         (((x) >> FW_HDR_FW_VER_MINOR_S) & FW_HDR_FW_VER_MINOR_M)
3115
3116 #define FW_HDR_FW_VER_MICRO_S   8
3117 #define FW_HDR_FW_VER_MICRO_M   0xff
3118 #define FW_HDR_FW_VER_MICRO_V(x) \
3119         ((x) << FW_HDR_FW_VER_MICRO_S)
3120 #define FW_HDR_FW_VER_MICRO_G(x) \
3121         (((x) >> FW_HDR_FW_VER_MICRO_S) & FW_HDR_FW_VER_MICRO_M)
3122
3123 #define FW_HDR_FW_VER_BUILD_S   0
3124 #define FW_HDR_FW_VER_BUILD_M   0xff
3125 #define FW_HDR_FW_VER_BUILD_V(x) \
3126         ((x) << FW_HDR_FW_VER_BUILD_S)
3127 #define FW_HDR_FW_VER_BUILD_G(x) \
3128         (((x) >> FW_HDR_FW_VER_BUILD_S) & FW_HDR_FW_VER_BUILD_M)
3129
3130 enum fw_hdr_intfver {
3131         FW_HDR_INTFVER_NIC      = 0x00,
3132         FW_HDR_INTFVER_VNIC     = 0x00,
3133         FW_HDR_INTFVER_OFLD     = 0x00,
3134         FW_HDR_INTFVER_RI       = 0x00,
3135         FW_HDR_INTFVER_ISCSIPDU = 0x00,
3136         FW_HDR_INTFVER_ISCSI    = 0x00,
3137         FW_HDR_INTFVER_FCOEPDU  = 0x00,
3138         FW_HDR_INTFVER_FCOE     = 0x00,
3139 };
3140
3141 enum fw_hdr_flags {
3142         FW_HDR_FLAGS_RESET_HALT = 0x00000001,
3143 };
3144
3145 /* length of the formatting string  */
3146 #define FW_DEVLOG_FMT_LEN       192
3147
3148 /* maximum number of the formatting string parameters */
3149 #define FW_DEVLOG_FMT_PARAMS_NUM 8
3150
3151 /* priority levels */
3152 enum fw_devlog_level {
3153         FW_DEVLOG_LEVEL_EMERG   = 0x0,
3154         FW_DEVLOG_LEVEL_CRIT    = 0x1,
3155         FW_DEVLOG_LEVEL_ERR     = 0x2,
3156         FW_DEVLOG_LEVEL_NOTICE  = 0x3,
3157         FW_DEVLOG_LEVEL_INFO    = 0x4,
3158         FW_DEVLOG_LEVEL_DEBUG   = 0x5,
3159         FW_DEVLOG_LEVEL_MAX     = 0x5,
3160 };
3161
3162 /* facilities that may send a log message */
3163 enum fw_devlog_facility {
3164         FW_DEVLOG_FACILITY_CORE         = 0x00,
3165         FW_DEVLOG_FACILITY_CF           = 0x01,
3166         FW_DEVLOG_FACILITY_SCHED        = 0x02,
3167         FW_DEVLOG_FACILITY_TIMER        = 0x04,
3168         FW_DEVLOG_FACILITY_RES          = 0x06,
3169         FW_DEVLOG_FACILITY_HW           = 0x08,
3170         FW_DEVLOG_FACILITY_FLR          = 0x10,
3171         FW_DEVLOG_FACILITY_DMAQ         = 0x12,
3172         FW_DEVLOG_FACILITY_PHY          = 0x14,
3173         FW_DEVLOG_FACILITY_MAC          = 0x16,
3174         FW_DEVLOG_FACILITY_PORT         = 0x18,
3175         FW_DEVLOG_FACILITY_VI           = 0x1A,
3176         FW_DEVLOG_FACILITY_FILTER       = 0x1C,
3177         FW_DEVLOG_FACILITY_ACL          = 0x1E,
3178         FW_DEVLOG_FACILITY_TM           = 0x20,
3179         FW_DEVLOG_FACILITY_QFC          = 0x22,
3180         FW_DEVLOG_FACILITY_DCB          = 0x24,
3181         FW_DEVLOG_FACILITY_ETH          = 0x26,
3182         FW_DEVLOG_FACILITY_OFLD         = 0x28,
3183         FW_DEVLOG_FACILITY_RI           = 0x2A,
3184         FW_DEVLOG_FACILITY_ISCSI        = 0x2C,
3185         FW_DEVLOG_FACILITY_FCOE         = 0x2E,
3186         FW_DEVLOG_FACILITY_FOISCSI      = 0x30,
3187         FW_DEVLOG_FACILITY_FOFCOE       = 0x32,
3188         FW_DEVLOG_FACILITY_CHNET        = 0x34,
3189         FW_DEVLOG_FACILITY_MAX          = 0x34,
3190 };
3191
3192 /* log message format */
3193 struct fw_devlog_e {
3194         __be64  timestamp;
3195         __be32  seqno;
3196         __be16  reserved1;
3197         __u8    level;
3198         __u8    facility;
3199         __u8    fmt[FW_DEVLOG_FMT_LEN];
3200         __be32  params[FW_DEVLOG_FMT_PARAMS_NUM];
3201         __be32  reserved3[4];
3202 };
3203
3204 struct fw_devlog_cmd {
3205         __be32 op_to_write;
3206         __be32 retval_len16;
3207         __u8   level;
3208         __u8   r2[7];
3209         __be32 memtype_devlog_memaddr16_devlog;
3210         __be32 memsize_devlog;
3211         __be32 r3[2];
3212 };
3213
3214 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S          28
3215 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M          0xf
3216 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(x)       \
3217         (((x) >> FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S) & \
3218          FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M)
3219
3220 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S        0
3221 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M        0xfffffff
3222 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(x)     \
3223         (((x) >> FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S) & \
3224          FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M)
3225
3226 /* P C I E   F W   P F 7   R E G I S T E R */
3227
3228 /* PF7 stores the Firmware Device Log parameters which allows Host Drivers to
3229  * access the "devlog" which needing to contact firmware.  The encoding is
3230  * mostly the same as that returned by the DEVLOG command except for the size
3231  * which is encoded as the number of entries in multiples-1 of 128 here rather
3232  * than the memory size as is done in the DEVLOG command.  Thus, 0 means 128
3233  * and 15 means 2048.  This of course in turn constrains the allowed values
3234  * for the devlog size ...
3235  */
3236 #define PCIE_FW_PF_DEVLOG               7
3237
3238 #define PCIE_FW_PF_DEVLOG_NENTRIES128_S 28
3239 #define PCIE_FW_PF_DEVLOG_NENTRIES128_M 0xf
3240 #define PCIE_FW_PF_DEVLOG_NENTRIES128_V(x) \
3241         ((x) << PCIE_FW_PF_DEVLOG_NENTRIES128_S)
3242 #define PCIE_FW_PF_DEVLOG_NENTRIES128_G(x) \
3243         (((x) >> PCIE_FW_PF_DEVLOG_NENTRIES128_S) & \
3244          PCIE_FW_PF_DEVLOG_NENTRIES128_M)
3245
3246 #define PCIE_FW_PF_DEVLOG_ADDR16_S      4
3247 #define PCIE_FW_PF_DEVLOG_ADDR16_M      0xffffff
3248 #define PCIE_FW_PF_DEVLOG_ADDR16_V(x)   ((x) << PCIE_FW_PF_DEVLOG_ADDR16_S)
3249 #define PCIE_FW_PF_DEVLOG_ADDR16_G(x) \
3250         (((x) >> PCIE_FW_PF_DEVLOG_ADDR16_S) & PCIE_FW_PF_DEVLOG_ADDR16_M)
3251
3252 #define PCIE_FW_PF_DEVLOG_MEMTYPE_S     0
3253 #define PCIE_FW_PF_DEVLOG_MEMTYPE_M     0xf
3254 #define PCIE_FW_PF_DEVLOG_MEMTYPE_V(x)  ((x) << PCIE_FW_PF_DEVLOG_MEMTYPE_S)
3255 #define PCIE_FW_PF_DEVLOG_MEMTYPE_G(x) \
3256         (((x) >> PCIE_FW_PF_DEVLOG_MEMTYPE_S) & PCIE_FW_PF_DEVLOG_MEMTYPE_M)
3257
3258 #endif /* _T4FW_INTERFACE_H_ */