drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2009-2014 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #ifndef _T4FW_INTERFACE_H_
  36 #define _T4FW_INTERFACE_H_
  37
  38 enum fw_retval {
  39         FW_SUCCESS              = 0,    /* completed sucessfully */
  40         FW_EPERM                = 1,    /* operation not permitted */
  41         FW_ENOENT               = 2,    /* no such file or directory */
  42         FW_EIO                  = 5,    /* input/output error; hw bad */
  43         FW_ENOEXEC              = 8,    /* exec format error; inv microcode */
  44         FW_EAGAIN               = 11,   /* try again */
  45         FW_ENOMEM               = 12,   /* out of memory */
  46         FW_EFAULT               = 14,   /* bad address; fw bad */
  47         FW_EBUSY                = 16,   /* resource busy */
  48         FW_EEXIST               = 17,   /* file exists */
  49         FW_ENODEV               = 19,   /* no such device */
  50         FW_EINVAL               = 22,   /* invalid argument */
  51         FW_ENOSPC               = 28,   /* no space left on device */
  52         FW_ENOSYS               = 38,   /* functionality not implemented */
  53         FW_ENODATA              = 61,   /* no data available */
  54         FW_EPROTO               = 71,   /* protocol error */
  55         FW_EADDRINUSE           = 98,   /* address already in use */
  56         FW_EADDRNOTAVAIL        = 99,   /* cannot assigned requested address */
  57         FW_ENETDOWN             = 100,  /* network is down */
  58         FW_ENETUNREACH          = 101,  /* network is unreachable */
  59         FW_ENOBUFS              = 105,  /* no buffer space available */
  60         FW_ETIMEDOUT            = 110,  /* timeout */
  61         FW_EINPROGRESS          = 115,  /* fw internal */
  62         FW_SCSI_ABORT_REQUESTED = 128,  /* */
  63         FW_SCSI_ABORT_TIMEDOUT  = 129,  /* */
  64         FW_SCSI_ABORTED         = 130,  /* */
  65         FW_SCSI_CLOSE_REQUESTED = 131,  /* */
  66         FW_ERR_LINK_DOWN        = 132,  /* */
  67         FW_RDEV_NOT_READY       = 133,  /* */
  68         FW_ERR_RDEV_LOST        = 134,  /* */
  69         FW_ERR_RDEV_LOGO        = 135,  /* */
  70         FW_FCOE_NO_XCHG         = 136,  /* */
  71         FW_SCSI_RSP_ERR         = 137,  /* */
  72         FW_ERR_RDEV_IMPL_LOGO   = 138,  /* */
  73         FW_SCSI_UNDER_FLOW_ERR  = 139,  /* */
  74         FW_SCSI_OVER_FLOW_ERR   = 140,  /* */
  75         FW_SCSI_DDP_ERR         = 141,  /* DDP error*/
  76         FW_SCSI_TASK_ERR        = 142,  /* No SCSI tasks available */
  77 };
  78
  79 #define FW_T4VF_SGE_BASE_ADDR      0x0000
  80 #define FW_T4VF_MPS_BASE_ADDR      0x0100
  81 #define FW_T4VF_PL_BASE_ADDR       0x0200
  82 #define FW_T4VF_MBDATA_BASE_ADDR   0x0240
  83 #define FW_T4VF_CIM_BASE_ADDR      0x0300
  84
  85 enum fw_wr_opcodes {
  86         FW_FILTER_WR                   = 0x02,
  87         FW_ULPTX_WR                    = 0x04,
  88         FW_TP_WR                       = 0x05,
  89         FW_ETH_TX_PKT_WR               = 0x08,
  90         FW_OFLD_CONNECTION_WR          = 0x2f,
  91         FW_FLOWC_WR                    = 0x0a,
  92         FW_OFLD_TX_DATA_WR             = 0x0b,
  93         FW_CMD_WR                      = 0x10,
  94         FW_ETH_TX_PKT_VM_WR            = 0x11,
  95         FW_RI_RES_WR                   = 0x0c,
  96         FW_RI_INIT_WR                  = 0x0d,
  97         FW_RI_RDMA_WRITE_WR            = 0x14,
  98         FW_RI_SEND_WR                  = 0x15,
  99         FW_RI_RDMA_READ_WR             = 0x16,
 100         FW_RI_RECV_WR                  = 0x17,
 101         FW_RI_BIND_MW_WR               = 0x18,
 102         FW_RI_FR_NSMR_WR               = 0x19,
 103         FW_RI_INV_LSTAG_WR             = 0x1a,
 104         FW_LASTC2E_WR                  = 0x40
 105 };
 106
 107 struct fw_wr_hdr {
 108         __be32 hi;
 109         __be32 lo;
 110 };
 111
 112 #define FW_WR_OP(x)      ((x) << 24)
 113 #define FW_WR_OP_GET(x)  (((x) >> 24) & 0xff)
 114 #define FW_WR_ATOMIC(x)  ((x) << 23)
 115 #define FW_WR_FLUSH(x)   ((x) << 22)
 116 #define FW_WR_COMPL(x)   ((x) << 21)
 117 #define FW_WR_IMMDLEN_MASK 0xff
 118 #define FW_WR_IMMDLEN(x) ((x) << 0)
 119
 120 #define FW_WR_EQUIQ     (1U << 31)
 121 #define FW_WR_EQUEQ     (1U << 30)
 122 #define FW_WR_FLOWID(x) ((x) << 8)
 123 #define FW_WR_LEN16(x)  ((x) << 0)
 124
 125 #define HW_TPL_FR_MT_PR_IV_P_FC         0X32B
 126 #define HW_TPL_FR_MT_PR_OV_P_FC         0X327
 127
 128 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
 129 enum fw_filter_wr_cookie {
 130         FW_FILTER_WR_SUCCESS,
 131         FW_FILTER_WR_FLT_ADDED,
 132         FW_FILTER_WR_FLT_DELETED,
 133         FW_FILTER_WR_SMT_TBL_FULL,
 134         FW_FILTER_WR_EINVAL,
 135 };
 136
 137 struct fw_filter_wr {
 138         __be32 op_pkd;
 139         __be32 len16_pkd;
 140         __be64 r3;
 141         __be32 tid_to_iq;
 142         __be32 del_filter_to_l2tix;
 143         __be16 ethtype;
 144         __be16 ethtypem;
 145         __u8   frag_to_ovlan_vldm;
 146         __u8   smac_sel;
 147         __be16 rx_chan_rx_rpl_iq;
 148         __be32 maci_to_matchtypem;
 149         __u8   ptcl;
 150         __u8   ptclm;
 151         __u8   ttyp;
 152         __u8   ttypm;
 153         __be16 ivlan;
 154         __be16 ivlanm;
 155         __be16 ovlan;
 156         __be16 ovlanm;
 157         __u8   lip[16];
 158         __u8   lipm[16];
 159         __u8   fip[16];
 160         __u8   fipm[16];
 161         __be16 lp;
 162         __be16 lpm;
 163         __be16 fp;
 164         __be16 fpm;
 165         __be16 r7;
 166         __u8   sma[6];
 167 };
 168
 169 #define S_FW_FILTER_WR_TID      12
 170 #define M_FW_FILTER_WR_TID      0xfffff
 171 #define V_FW_FILTER_WR_TID(x)   ((x) << S_FW_FILTER_WR_TID)
 172 #define G_FW_FILTER_WR_TID(x)   \
 173         (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID)
 174
 175 #define S_FW_FILTER_WR_RQTYPE           11
 176 #define M_FW_FILTER_WR_RQTYPE           0x1
 177 #define V_FW_FILTER_WR_RQTYPE(x)        ((x) << S_FW_FILTER_WR_RQTYPE)
 178 #define G_FW_FILTER_WR_RQTYPE(x)        \
 179         (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE)
 180 #define F_FW_FILTER_WR_RQTYPE   V_FW_FILTER_WR_RQTYPE(1U)
 181
 182 #define S_FW_FILTER_WR_NOREPLY          10
 183 #define M_FW_FILTER_WR_NOREPLY          0x1
 184 #define V_FW_FILTER_WR_NOREPLY(x)       ((x) << S_FW_FILTER_WR_NOREPLY)
 185 #define G_FW_FILTER_WR_NOREPLY(x)       \
 186         (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY)
 187 #define F_FW_FILTER_WR_NOREPLY  V_FW_FILTER_WR_NOREPLY(1U)
 188
 189 #define S_FW_FILTER_WR_IQ       0
 190 #define M_FW_FILTER_WR_IQ       0x3ff
 191 #define V_FW_FILTER_WR_IQ(x)    ((x) << S_FW_FILTER_WR_IQ)
 192 #define G_FW_FILTER_WR_IQ(x)    \
 193         (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ)
 194
 195 #define S_FW_FILTER_WR_DEL_FILTER       31
 196 #define M_FW_FILTER_WR_DEL_FILTER       0x1
 197 #define V_FW_FILTER_WR_DEL_FILTER(x)    ((x) << S_FW_FILTER_WR_DEL_FILTER)
 198 #define G_FW_FILTER_WR_DEL_FILTER(x)    \
 199         (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER)
 200 #define F_FW_FILTER_WR_DEL_FILTER       V_FW_FILTER_WR_DEL_FILTER(1U)
 201
 202 #define S_FW_FILTER_WR_RPTTID           25
 203 #define M_FW_FILTER_WR_RPTTID           0x1
 204 #define V_FW_FILTER_WR_RPTTID(x)        ((x) << S_FW_FILTER_WR_RPTTID)
 205 #define G_FW_FILTER_WR_RPTTID(x)        \
 206         (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID)
 207 #define F_FW_FILTER_WR_RPTTID   V_FW_FILTER_WR_RPTTID(1U)
 208
 209 #define S_FW_FILTER_WR_DROP     24
 210 #define M_FW_FILTER_WR_DROP     0x1
 211 #define V_FW_FILTER_WR_DROP(x)  ((x) << S_FW_FILTER_WR_DROP)
 212 #define G_FW_FILTER_WR_DROP(x)  \
 213         (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP)
 214 #define F_FW_FILTER_WR_DROP     V_FW_FILTER_WR_DROP(1U)
 215
 216 #define S_FW_FILTER_WR_DIRSTEER         23
 217 #define M_FW_FILTER_WR_DIRSTEER         0x1
 218 #define V_FW_FILTER_WR_DIRSTEER(x)      ((x) << S_FW_FILTER_WR_DIRSTEER)
 219 #define G_FW_FILTER_WR_DIRSTEER(x)      \
 220         (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER)
 221 #define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U)
 222
 223 #define S_FW_FILTER_WR_MASKHASH         22
 224 #define M_FW_FILTER_WR_MASKHASH         0x1
 225 #define V_FW_FILTER_WR_MASKHASH(x)      ((x) << S_FW_FILTER_WR_MASKHASH)
 226 #define G_FW_FILTER_WR_MASKHASH(x)      \
 227         (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH)
 228 #define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U)
 229
 230 #define S_FW_FILTER_WR_DIRSTEERHASH     21
 231 #define M_FW_FILTER_WR_DIRSTEERHASH     0x1
 232 #define V_FW_FILTER_WR_DIRSTEERHASH(x)  ((x) << S_FW_FILTER_WR_DIRSTEERHASH)
 233 #define G_FW_FILTER_WR_DIRSTEERHASH(x)  \
 234         (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH)
 235 #define F_FW_FILTER_WR_DIRSTEERHASH     V_FW_FILTER_WR_DIRSTEERHASH(1U)
 236
 237 #define S_FW_FILTER_WR_LPBK     20
 238 #define M_FW_FILTER_WR_LPBK     0x1
 239 #define V_FW_FILTER_WR_LPBK(x)  ((x) << S_FW_FILTER_WR_LPBK)
 240 #define G_FW_FILTER_WR_LPBK(x)  \
 241         (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK)
 242 #define F_FW_FILTER_WR_LPBK     V_FW_FILTER_WR_LPBK(1U)
 243
 244 #define S_FW_FILTER_WR_DMAC     19
 245 #define M_FW_FILTER_WR_DMAC     0x1
 246 #define V_FW_FILTER_WR_DMAC(x)  ((x) << S_FW_FILTER_WR_DMAC)
 247 #define G_FW_FILTER_WR_DMAC(x)  \
 248         (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC)
 249 #define F_FW_FILTER_WR_DMAC     V_FW_FILTER_WR_DMAC(1U)
 250
 251 #define S_FW_FILTER_WR_SMAC     18
 252 #define M_FW_FILTER_WR_SMAC     0x1
 253 #define V_FW_FILTER_WR_SMAC(x)  ((x) << S_FW_FILTER_WR_SMAC)
 254 #define G_FW_FILTER_WR_SMAC(x)  \
 255         (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC)
 256 #define F_FW_FILTER_WR_SMAC     V_FW_FILTER_WR_SMAC(1U)
 257
 258 #define S_FW_FILTER_WR_INSVLAN          17
 259 #define M_FW_FILTER_WR_INSVLAN          0x1
 260 #define V_FW_FILTER_WR_INSVLAN(x)       ((x) << S_FW_FILTER_WR_INSVLAN)
 261 #define G_FW_FILTER_WR_INSVLAN(x)       \
 262         (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN)
 263 #define F_FW_FILTER_WR_INSVLAN  V_FW_FILTER_WR_INSVLAN(1U)
 264
 265 #define S_FW_FILTER_WR_RMVLAN           16
 266 #define M_FW_FILTER_WR_RMVLAN           0x1
 267 #define V_FW_FILTER_WR_RMVLAN(x)        ((x) << S_FW_FILTER_WR_RMVLAN)
 268 #define G_FW_FILTER_WR_RMVLAN(x)        \
 269         (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN)
 270 #define F_FW_FILTER_WR_RMVLAN   V_FW_FILTER_WR_RMVLAN(1U)
 271
 272 #define S_FW_FILTER_WR_HITCNTS          15
 273 #define M_FW_FILTER_WR_HITCNTS          0x1
 274 #define V_FW_FILTER_WR_HITCNTS(x)       ((x) << S_FW_FILTER_WR_HITCNTS)
 275 #define G_FW_FILTER_WR_HITCNTS(x)       \
 276         (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS)
 277 #define F_FW_FILTER_WR_HITCNTS  V_FW_FILTER_WR_HITCNTS(1U)
 278
 279 #define S_FW_FILTER_WR_TXCHAN           13
 280 #define M_FW_FILTER_WR_TXCHAN           0x3
 281 #define V_FW_FILTER_WR_TXCHAN(x)        ((x) << S_FW_FILTER_WR_TXCHAN)
 282 #define G_FW_FILTER_WR_TXCHAN(x)        \
 283         (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN)
 284
 285 #define S_FW_FILTER_WR_PRIO     12
 286 #define M_FW_FILTER_WR_PRIO     0x1
 287 #define V_FW_FILTER_WR_PRIO(x)  ((x) << S_FW_FILTER_WR_PRIO)
 288 #define G_FW_FILTER_WR_PRIO(x)  \
 289         (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO)
 290 #define F_FW_FILTER_WR_PRIO     V_FW_FILTER_WR_PRIO(1U)
 291
 292 #define S_FW_FILTER_WR_L2TIX    0
 293 #define M_FW_FILTER_WR_L2TIX    0xfff
 294 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX)
 295 #define G_FW_FILTER_WR_L2TIX(x) \
 296         (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX)
 297
 298 #define S_FW_FILTER_WR_FRAG     7
 299 #define M_FW_FILTER_WR_FRAG     0x1
 300 #define V_FW_FILTER_WR_FRAG(x)  ((x) << S_FW_FILTER_WR_FRAG)
 301 #define G_FW_FILTER_WR_FRAG(x)  \
 302         (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG)
 303 #define F_FW_FILTER_WR_FRAG     V_FW_FILTER_WR_FRAG(1U)
 304
 305 #define S_FW_FILTER_WR_FRAGM    6
 306 #define M_FW_FILTER_WR_FRAGM    0x1
 307 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM)
 308 #define G_FW_FILTER_WR_FRAGM(x) \
 309         (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM)
 310 #define F_FW_FILTER_WR_FRAGM    V_FW_FILTER_WR_FRAGM(1U)
 311
 312 #define S_FW_FILTER_WR_IVLAN_VLD        5
 313 #define M_FW_FILTER_WR_IVLAN_VLD        0x1
 314 #define V_FW_FILTER_WR_IVLAN_VLD(x)     ((x) << S_FW_FILTER_WR_IVLAN_VLD)
 315 #define G_FW_FILTER_WR_IVLAN_VLD(x)     \
 316         (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD)
 317 #define F_FW_FILTER_WR_IVLAN_VLD        V_FW_FILTER_WR_IVLAN_VLD(1U)
 318
 319 #define S_FW_FILTER_WR_OVLAN_VLD        4
 320 #define M_FW_FILTER_WR_OVLAN_VLD        0x1
 321 #define V_FW_FILTER_WR_OVLAN_VLD(x)     ((x) << S_FW_FILTER_WR_OVLAN_VLD)
 322 #define G_FW_FILTER_WR_OVLAN_VLD(x)     \
 323         (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD)
 324 #define F_FW_FILTER_WR_OVLAN_VLD        V_FW_FILTER_WR_OVLAN_VLD(1U)
 325
 326 #define S_FW_FILTER_WR_IVLAN_VLDM       3
 327 #define M_FW_FILTER_WR_IVLAN_VLDM       0x1
 328 #define V_FW_FILTER_WR_IVLAN_VLDM(x)    ((x) << S_FW_FILTER_WR_IVLAN_VLDM)
 329 #define G_FW_FILTER_WR_IVLAN_VLDM(x)    \
 330         (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM)
 331 #define F_FW_FILTER_WR_IVLAN_VLDM       V_FW_FILTER_WR_IVLAN_VLDM(1U)
 332
 333 #define S_FW_FILTER_WR_OVLAN_VLDM       2
 334 #define M_FW_FILTER_WR_OVLAN_VLDM       0x1
 335 #define V_FW_FILTER_WR_OVLAN_VLDM(x)    ((x) << S_FW_FILTER_WR_OVLAN_VLDM)
 336 #define G_FW_FILTER_WR_OVLAN_VLDM(x)    \
 337         (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM)
 338 #define F_FW_FILTER_WR_OVLAN_VLDM       V_FW_FILTER_WR_OVLAN_VLDM(1U)
 339
 340 #define S_FW_FILTER_WR_RX_CHAN          15
 341 #define M_FW_FILTER_WR_RX_CHAN          0x1
 342 #define V_FW_FILTER_WR_RX_CHAN(x)       ((x) << S_FW_FILTER_WR_RX_CHAN)
 343 #define G_FW_FILTER_WR_RX_CHAN(x)       \
 344         (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN)
 345 #define F_FW_FILTER_WR_RX_CHAN  V_FW_FILTER_WR_RX_CHAN(1U)
 346
 347 #define S_FW_FILTER_WR_RX_RPL_IQ        0
 348 #define M_FW_FILTER_WR_RX_RPL_IQ        0x3ff
 349 #define V_FW_FILTER_WR_RX_RPL_IQ(x)     ((x) << S_FW_FILTER_WR_RX_RPL_IQ)
 350 #define G_FW_FILTER_WR_RX_RPL_IQ(x)     \
 351         (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ)
 352
 353 #define S_FW_FILTER_WR_MACI     23
 354 #define M_FW_FILTER_WR_MACI     0x1ff
 355 #define V_FW_FILTER_WR_MACI(x)  ((x) << S_FW_FILTER_WR_MACI)
 356 #define G_FW_FILTER_WR_MACI(x)  \
 357         (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI)
 358
 359 #define S_FW_FILTER_WR_MACIM    14
 360 #define M_FW_FILTER_WR_MACIM    0x1ff
 361 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM)
 362 #define G_FW_FILTER_WR_MACIM(x) \
 363         (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM)
 364
 365 #define S_FW_FILTER_WR_FCOE     13
 366 #define M_FW_FILTER_WR_FCOE     0x1
 367 #define V_FW_FILTER_WR_FCOE(x)  ((x) << S_FW_FILTER_WR_FCOE)
 368 #define G_FW_FILTER_WR_FCOE(x)  \
 369         (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE)
 370 #define F_FW_FILTER_WR_FCOE     V_FW_FILTER_WR_FCOE(1U)
 371
 372 #define S_FW_FILTER_WR_FCOEM    12
 373 #define M_FW_FILTER_WR_FCOEM    0x1
 374 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM)
 375 #define G_FW_FILTER_WR_FCOEM(x) \
 376         (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM)
 377 #define F_FW_FILTER_WR_FCOEM    V_FW_FILTER_WR_FCOEM(1U)
 378
 379 #define S_FW_FILTER_WR_PORT     9
 380 #define M_FW_FILTER_WR_PORT     0x7
 381 #define V_FW_FILTER_WR_PORT(x)  ((x) << S_FW_FILTER_WR_PORT)
 382 #define G_FW_FILTER_WR_PORT(x)  \
 383         (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT)
 384
 385 #define S_FW_FILTER_WR_PORTM    6
 386 #define M_FW_FILTER_WR_PORTM    0x7
 387 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM)
 388 #define G_FW_FILTER_WR_PORTM(x) \
 389         (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM)
 390
 391 #define S_FW_FILTER_WR_MATCHTYPE        3
 392 #define M_FW_FILTER_WR_MATCHTYPE        0x7
 393 #define V_FW_FILTER_WR_MATCHTYPE(x)     ((x) << S_FW_FILTER_WR_MATCHTYPE)
 394 #define G_FW_FILTER_WR_MATCHTYPE(x)     \
 395         (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE)
 396
 397 #define S_FW_FILTER_WR_MATCHTYPEM       0
 398 #define M_FW_FILTER_WR_MATCHTYPEM       0x7
 399 #define V_FW_FILTER_WR_MATCHTYPEM(x)    ((x) << S_FW_FILTER_WR_MATCHTYPEM)
 400 #define G_FW_FILTER_WR_MATCHTYPEM(x)    \
 401         (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM)
 402
 403 struct fw_ulptx_wr {
 404         __be32 op_to_compl;
 405         __be32 flowid_len16;
 406         u64 cookie;
 407 };
 408
 409 struct fw_tp_wr {
 410         __be32 op_to_immdlen;
 411         __be32 flowid_len16;
 412         u64 cookie;
 413 };
 414
 415 struct fw_eth_tx_pkt_wr {
 416         __be32 op_immdlen;
 417         __be32 equiq_to_len16;
 418         __be64 r3;
 419 };
 420
 421 struct fw_ofld_connection_wr {
 422         __be32 op_compl;
 423         __be32 len16_pkd;
 424         __u64  cookie;
 425         __be64 r2;
 426         __be64 r3;
 427         struct fw_ofld_connection_le {
 428                 __be32 version_cpl;
 429                 __be32 filter;
 430                 __be32 r1;
 431                 __be16 lport;
 432                 __be16 pport;
 433                 union fw_ofld_connection_leip {
 434                         struct fw_ofld_connection_le_ipv4 {
 435                                 __be32 pip;
 436                                 __be32 lip;
 437                                 __be64 r0;
 438                                 __be64 r1;
 439                                 __be64 r2;
 440                         } ipv4;
 441                         struct fw_ofld_connection_le_ipv6 {
 442                                 __be64 pip_hi;
 443                                 __be64 pip_lo;
 444                                 __be64 lip_hi;
 445                                 __be64 lip_lo;
 446                         } ipv6;
 447                 } u;
 448         } le;
 449         struct fw_ofld_connection_tcb {
 450                 __be32 t_state_to_astid;
 451                 __be16 cplrxdataack_cplpassacceptrpl;
 452                 __be16 rcv_adv;
 453                 __be32 rcv_nxt;
 454                 __be32 tx_max;
 455                 __be64 opt0;
 456                 __be32 opt2;
 457                 __be32 r1;
 458                 __be64 r2;
 459                 __be64 r3;
 460         } tcb;
 461 };
 462
 463 #define S_FW_OFLD_CONNECTION_WR_VERSION                31
 464 #define M_FW_OFLD_CONNECTION_WR_VERSION                0x1
 465 #define V_FW_OFLD_CONNECTION_WR_VERSION(x)     \
 466         ((x) << S_FW_OFLD_CONNECTION_WR_VERSION)
 467 #define G_FW_OFLD_CONNECTION_WR_VERSION(x)     \
 468         (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \
 469         M_FW_OFLD_CONNECTION_WR_VERSION)
 470 #define F_FW_OFLD_CONNECTION_WR_VERSION        \
 471         V_FW_OFLD_CONNECTION_WR_VERSION(1U)
 472
 473 #define S_FW_OFLD_CONNECTION_WR_CPL    30
 474 #define M_FW_OFLD_CONNECTION_WR_CPL    0x1
 475 #define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL)
 476 #define G_FW_OFLD_CONNECTION_WR_CPL(x) \
 477         (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL)
 478 #define F_FW_OFLD_CONNECTION_WR_CPL    V_FW_OFLD_CONNECTION_WR_CPL(1U)
 479
 480 #define S_FW_OFLD_CONNECTION_WR_T_STATE                28
 481 #define M_FW_OFLD_CONNECTION_WR_T_STATE                0xf
 482 #define V_FW_OFLD_CONNECTION_WR_T_STATE(x)     \
 483         ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE)
 484 #define G_FW_OFLD_CONNECTION_WR_T_STATE(x)     \
 485         (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \
 486         M_FW_OFLD_CONNECTION_WR_T_STATE)
 487
 488 #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE      24
 489 #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE      0xf
 490 #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x)   \
 491         ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE)
 492 #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x)   \
 493         (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \
 494         M_FW_OFLD_CONNECTION_WR_RCV_SCALE)
 495
 496 #define S_FW_OFLD_CONNECTION_WR_ASTID          0
 497 #define M_FW_OFLD_CONNECTION_WR_ASTID          0xffffff
 498 #define V_FW_OFLD_CONNECTION_WR_ASTID(x)       \
 499         ((x) << S_FW_OFLD_CONNECTION_WR_ASTID)
 500 #define G_FW_OFLD_CONNECTION_WR_ASTID(x)       \
 501         (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID)
 502
 503 #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK   15
 504 #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK   0x1
 505 #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x)        \
 506         ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
 507 #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x)        \
 508         (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \
 509         M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
 510 #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK   \
 511         V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U)
 512
 513 #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL       14
 514 #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL       0x1
 515 #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x)    \
 516         ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
 517 #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x)    \
 518         (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \
 519         M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
 520 #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL       \
 521         V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U)
 522
 523 enum fw_flowc_mnem {
 524         FW_FLOWC_MNEM_PFNVFN,           /* PFN [15:8] VFN [7:0] */
 525         FW_FLOWC_MNEM_CH,
 526         FW_FLOWC_MNEM_PORT,
 527         FW_FLOWC_MNEM_IQID,
 528         FW_FLOWC_MNEM_SNDNXT,
 529         FW_FLOWC_MNEM_RCVNXT,
 530         FW_FLOWC_MNEM_SNDBUF,
 531         FW_FLOWC_MNEM_MSS,
 532 };
 533
 534 struct fw_flowc_mnemval {
 535         u8 mnemonic;
 536         u8 r4[3];
 537         __be32 val;
 538 };
 539
 540 struct fw_flowc_wr {
 541         __be32 op_to_nparams;
 542 #define FW_FLOWC_WR_NPARAMS(x)  ((x) << 0)
 543         __be32 flowid_len16;
 544         struct fw_flowc_mnemval mnemval[0];
 545 };
 546
 547 struct fw_ofld_tx_data_wr {
 548         __be32 op_to_immdlen;
 549         __be32 flowid_len16;
 550         __be32 plen;
 551         __be32 tunnel_to_proxy;
 552 #define FW_OFLD_TX_DATA_WR_TUNNEL(x)     ((x) << 19)
 553 #define FW_OFLD_TX_DATA_WR_SAVE(x)       ((x) << 18)
 554 #define FW_OFLD_TX_DATA_WR_FLUSH(x)      ((x) << 17)
 555 #define FW_OFLD_TX_DATA_WR_URGENT(x)     ((x) << 16)
 556 #define FW_OFLD_TX_DATA_WR_MORE(x)       ((x) << 15)
 557 #define FW_OFLD_TX_DATA_WR_SHOVE(x)      ((x) << 14)
 558 #define FW_OFLD_TX_DATA_WR_ULPMODE(x)    ((x) << 10)
 559 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) ((x) << 6)
 560 };
 561
 562 struct fw_cmd_wr {
 563         __be32 op_dma;
 564 #define FW_CMD_WR_DMA (1U << 17)
 565         __be32 len16_pkd;
 566         __be64 cookie_daddr;
 567 };
 568
 569 struct fw_eth_tx_pkt_vm_wr {
 570         __be32 op_immdlen;
 571         __be32 equiq_to_len16;
 572         __be32 r3[2];
 573         u8 ethmacdst[6];
 574         u8 ethmacsrc[6];
 575         __be16 ethtype;
 576         __be16 vlantci;
 577 };
 578
 579 #define FW_CMD_MAX_TIMEOUT 10000
 580
 581 /*
 582  * If a host driver does a HELLO and discovers that there's already a MASTER
 583  * selected, we may have to wait for that MASTER to finish issuing RESET,
 584  * configuration and INITIALIZE commands.  Also, there's a possibility that
 585  * our own HELLO may get lost if it happens right as the MASTER is issuign a
 586  * RESET command, so we need to be willing to make a few retries of our HELLO.
 587  */
 588 #define FW_CMD_HELLO_TIMEOUT    (3 * FW_CMD_MAX_TIMEOUT)
 589 #define FW_CMD_HELLO_RETRIES    3
 590
 591
 592 enum fw_cmd_opcodes {
 593         FW_LDST_CMD                    = 0x01,
 594         FW_RESET_CMD                   = 0x03,
 595         FW_HELLO_CMD                   = 0x04,
 596         FW_BYE_CMD                     = 0x05,
 597         FW_INITIALIZE_CMD              = 0x06,
 598         FW_CAPS_CONFIG_CMD             = 0x07,
 599         FW_PARAMS_CMD                  = 0x08,
 600         FW_PFVF_CMD                    = 0x09,
 601         FW_IQ_CMD                      = 0x10,
 602         FW_EQ_MNGT_CMD                 = 0x11,
 603         FW_EQ_ETH_CMD                  = 0x12,
 604         FW_EQ_CTRL_CMD                 = 0x13,
 605         FW_EQ_OFLD_CMD                 = 0x21,
 606         FW_VI_CMD                      = 0x14,
 607         FW_VI_MAC_CMD                  = 0x15,
 608         FW_VI_RXMODE_CMD               = 0x16,
 609         FW_VI_ENABLE_CMD               = 0x17,
 610         FW_ACL_MAC_CMD                 = 0x18,
 611         FW_ACL_VLAN_CMD                = 0x19,
 612         FW_VI_STATS_CMD                = 0x1a,
 613         FW_PORT_CMD                    = 0x1b,
 614         FW_PORT_STATS_CMD              = 0x1c,
 615         FW_PORT_LB_STATS_CMD           = 0x1d,
 616         FW_PORT_TRACE_CMD              = 0x1e,
 617         FW_PORT_TRACE_MMAP_CMD         = 0x1f,
 618         FW_RSS_IND_TBL_CMD             = 0x20,
 619         FW_RSS_GLB_CONFIG_CMD          = 0x22,
 620         FW_RSS_VI_CONFIG_CMD           = 0x23,
 621         FW_CLIP_CMD                    = 0x28,
 622         FW_LASTC2E_CMD                 = 0x40,
 623         FW_ERROR_CMD                   = 0x80,
 624         FW_DEBUG_CMD                   = 0x81,
 625 };
 626
 627 enum fw_cmd_cap {
 628         FW_CMD_CAP_PF                  = 0x01,
 629         FW_CMD_CAP_DMAQ                = 0x02,
 630         FW_CMD_CAP_PORT                = 0x04,
 631         FW_CMD_CAP_PORTPROMISC         = 0x08,
 632         FW_CMD_CAP_PORTSTATS           = 0x10,
 633         FW_CMD_CAP_VF                  = 0x80,
 634 };
 635
 636 /*
 637  * Generic command header flit0
 638  */
 639 struct fw_cmd_hdr {
 640         __be32 hi;
 641         __be32 lo;
 642 };
 643
 644 #define FW_CMD_OP(x)            ((x) << 24)
 645 #define FW_CMD_OP_GET(x)        (((x) >> 24) & 0xff)
 646 #define FW_CMD_REQUEST          (1U << 23)
 647 #define FW_CMD_REQUEST_GET(x)   (((x) >> 23) & 0x1)
 648 #define FW_CMD_READ             (1U << 22)
 649 #define FW_CMD_WRITE            (1U << 21)
 650 #define FW_CMD_EXEC             (1U << 20)
 651 #define FW_CMD_RAMASK(x)        ((x) << 20)
 652 #define FW_CMD_RETVAL(x)        ((x) << 8)
 653 #define FW_CMD_RETVAL_GET(x)    (((x) >> 8) & 0xff)
 654 #define FW_CMD_LEN16(x)         ((x) << 0)
 655 #define FW_LEN16(fw_struct)     FW_CMD_LEN16(sizeof(fw_struct) / 16)
 656
 657 enum fw_ldst_addrspc {
 658         FW_LDST_ADDRSPC_FIRMWARE  = 0x0001,
 659         FW_LDST_ADDRSPC_SGE_EGRC  = 0x0008,
 660         FW_LDST_ADDRSPC_SGE_INGC  = 0x0009,
 661         FW_LDST_ADDRSPC_SGE_FLMC  = 0x000a,
 662         FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
 663         FW_LDST_ADDRSPC_TP_PIO    = 0x0010,
 664         FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
 665         FW_LDST_ADDRSPC_TP_MIB    = 0x0012,
 666         FW_LDST_ADDRSPC_MDIO      = 0x0018,
 667         FW_LDST_ADDRSPC_MPS       = 0x0020,
 668         FW_LDST_ADDRSPC_FUNC      = 0x0028,
 669         FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
 670 };
 671
 672 enum fw_ldst_mps_fid {
 673         FW_LDST_MPS_ATRB,
 674         FW_LDST_MPS_RPLC
 675 };
 676
 677 enum fw_ldst_func_access_ctl {
 678         FW_LDST_FUNC_ACC_CTL_VIID,
 679         FW_LDST_FUNC_ACC_CTL_FID
 680 };
 681
 682 enum fw_ldst_func_mod_index {
 683         FW_LDST_FUNC_MPS
 684 };
 685
 686 struct fw_ldst_cmd {
 687         __be32 op_to_addrspace;
 688 #define FW_LDST_CMD_ADDRSPACE(x) ((x) << 0)
 689         __be32 cycles_to_len16;
 690         union fw_ldst {
 691                 struct fw_ldst_addrval {
 692                         __be32 addr;
 693                         __be32 val;
 694                 } addrval;
 695                 struct fw_ldst_idctxt {
 696                         __be32 physid;
 697                         __be32 msg_pkd;
 698                         __be32 ctxt_data7;
 699                         __be32 ctxt_data6;
 700                         __be32 ctxt_data5;
 701                         __be32 ctxt_data4;
 702                         __be32 ctxt_data3;
 703                         __be32 ctxt_data2;
 704                         __be32 ctxt_data1;
 705                         __be32 ctxt_data0;
 706                 } idctxt;
 707                 struct fw_ldst_mdio {
 708                         __be16 paddr_mmd;
 709                         __be16 raddr;
 710                         __be16 vctl;
 711                         __be16 rval;
 712                 } mdio;
 713                 struct fw_ldst_mps {
 714                         __be16 fid_ctl;
 715                         __be16 rplcpf_pkd;
 716                         __be32 rplc127_96;
 717                         __be32 rplc95_64;
 718                         __be32 rplc63_32;
 719                         __be32 rplc31_0;
 720                         __be32 atrb;
 721                         __be16 vlan[16];
 722                 } mps;
 723                 struct fw_ldst_func {
 724                         u8 access_ctl;
 725                         u8 mod_index;
 726                         __be16 ctl_id;
 727                         __be32 offset;
 728                         __be64 data0;
 729                         __be64 data1;
 730                 } func;
 731                 struct fw_ldst_pcie {
 732                         u8 ctrl_to_fn;
 733                         u8 bnum;
 734                         u8 r;
 735                         u8 ext_r;
 736                         u8 select_naccess;
 737                         u8 pcie_fn;
 738                         __be16 nset_pkd;
 739                         __be32 data[12];
 740                 } pcie;
 741         } u;
 742 };
 743
 744 #define FW_LDST_CMD_MSG(x)      ((x) << 31)
 745 #define FW_LDST_CMD_PADDR(x)    ((x) << 8)
 746 #define FW_LDST_CMD_MMD(x)      ((x) << 0)
 747 #define FW_LDST_CMD_FID(x)      ((x) << 15)
 748 #define FW_LDST_CMD_CTL(x)      ((x) << 0)
 749 #define FW_LDST_CMD_RPLCPF(x)   ((x) << 0)
 750 #define FW_LDST_CMD_LC          (1U << 4)
 751 #define FW_LDST_CMD_NACCESS(x)  ((x) << 0)
 752 #define FW_LDST_CMD_FN(x)       ((x) << 0)
 753
 754 struct fw_reset_cmd {
 755         __be32 op_to_write;
 756         __be32 retval_len16;
 757         __be32 val;
 758         __be32 halt_pkd;
 759 };
 760
 761 #define FW_RESET_CMD_HALT_SHIFT    31
 762 #define FW_RESET_CMD_HALT_MASK     0x1
 763 #define FW_RESET_CMD_HALT(x)       ((x) << FW_RESET_CMD_HALT_SHIFT)
 764 #define FW_RESET_CMD_HALT_GET(x)  \
 765         (((x) >> FW_RESET_CMD_HALT_SHIFT) & FW_RESET_CMD_HALT_MASK)
 766
 767 enum fw_hellow_cmd {
 768         fw_hello_cmd_stage_os           = 0x0
 769 };
 770
 771 struct fw_hello_cmd {
 772         __be32 op_to_write;
 773         __be32 retval_len16;
 774         __be32 err_to_clearinit;
 775 #define FW_HELLO_CMD_ERR            (1U << 31)
 776 #define FW_HELLO_CMD_INIT           (1U << 30)
 777 #define FW_HELLO_CMD_MASTERDIS(x)   ((x) << 29)
 778 #define FW_HELLO_CMD_MASTERFORCE(x) ((x) << 28)
 779 #define FW_HELLO_CMD_MBMASTER_MASK   0xfU
 780 #define FW_HELLO_CMD_MBMASTER_SHIFT  24
 781 #define FW_HELLO_CMD_MBMASTER(x)     ((x) << FW_HELLO_CMD_MBMASTER_SHIFT)
 782 #define FW_HELLO_CMD_MBMASTER_GET(x) \
 783         (((x) >> FW_HELLO_CMD_MBMASTER_SHIFT) & FW_HELLO_CMD_MBMASTER_MASK)
 784 #define FW_HELLO_CMD_MBASYNCNOTINT(x)   ((x) << 23)
 785 #define FW_HELLO_CMD_MBASYNCNOT(x)  ((x) << 20)
 786 #define FW_HELLO_CMD_STAGE(x)       ((x) << 17)
 787 #define FW_HELLO_CMD_CLEARINIT      (1U << 16)
 788         __be32 fwrev;
 789 };
 790
 791 struct fw_bye_cmd {
 792         __be32 op_to_write;
 793         __be32 retval_len16;
 794         __be64 r3;
 795 };
 796
 797 struct fw_initialize_cmd {
 798         __be32 op_to_write;
 799         __be32 retval_len16;
 800         __be64 r3;
 801 };
 802
 803 enum fw_caps_config_hm {
 804         FW_CAPS_CONFIG_HM_PCIE          = 0x00000001,
 805         FW_CAPS_CONFIG_HM_PL            = 0x00000002,
 806         FW_CAPS_CONFIG_HM_SGE           = 0x00000004,
 807         FW_CAPS_CONFIG_HM_CIM           = 0x00000008,
 808         FW_CAPS_CONFIG_HM_ULPTX         = 0x00000010,
 809         FW_CAPS_CONFIG_HM_TP            = 0x00000020,
 810         FW_CAPS_CONFIG_HM_ULPRX         = 0x00000040,
 811         FW_CAPS_CONFIG_HM_PMRX          = 0x00000080,
 812         FW_CAPS_CONFIG_HM_PMTX          = 0x00000100,
 813         FW_CAPS_CONFIG_HM_MC            = 0x00000200,
 814         FW_CAPS_CONFIG_HM_LE            = 0x00000400,
 815         FW_CAPS_CONFIG_HM_MPS           = 0x00000800,
 816         FW_CAPS_CONFIG_HM_XGMAC         = 0x00001000,
 817         FW_CAPS_CONFIG_HM_CPLSWITCH     = 0x00002000,
 818         FW_CAPS_CONFIG_HM_T4DBG         = 0x00004000,
 819         FW_CAPS_CONFIG_HM_MI            = 0x00008000,
 820         FW_CAPS_CONFIG_HM_I2CM          = 0x00010000,
 821         FW_CAPS_CONFIG_HM_NCSI          = 0x00020000,
 822         FW_CAPS_CONFIG_HM_SMB           = 0x00040000,
 823         FW_CAPS_CONFIG_HM_MA            = 0x00080000,
 824         FW_CAPS_CONFIG_HM_EDRAM         = 0x00100000,
 825         FW_CAPS_CONFIG_HM_PMU           = 0x00200000,
 826         FW_CAPS_CONFIG_HM_UART          = 0x00400000,
 827         FW_CAPS_CONFIG_HM_SF            = 0x00800000,
 828 };
 829
 830 enum fw_caps_config_nbm {
 831         FW_CAPS_CONFIG_NBM_IPMI         = 0x00000001,
 832         FW_CAPS_CONFIG_NBM_NCSI         = 0x00000002,
 833 };
 834
 835 enum fw_caps_config_link {
 836         FW_CAPS_CONFIG_LINK_PPP         = 0x00000001,
 837         FW_CAPS_CONFIG_LINK_QFC         = 0x00000002,
 838         FW_CAPS_CONFIG_LINK_DCBX        = 0x00000004,
 839 };
 840
 841 enum fw_caps_config_switch {
 842         FW_CAPS_CONFIG_SWITCH_INGRESS   = 0x00000001,
 843         FW_CAPS_CONFIG_SWITCH_EGRESS    = 0x00000002,
 844 };
 845
 846 enum fw_caps_config_nic {
 847         FW_CAPS_CONFIG_NIC              = 0x00000001,
 848         FW_CAPS_CONFIG_NIC_VM           = 0x00000002,
 849 };
 850
 851 enum fw_caps_config_ofld {
 852         FW_CAPS_CONFIG_OFLD             = 0x00000001,
 853 };
 854
 855 enum fw_caps_config_rdma {
 856         FW_CAPS_CONFIG_RDMA_RDDP        = 0x00000001,
 857         FW_CAPS_CONFIG_RDMA_RDMAC       = 0x00000002,
 858 };
 859
 860 enum fw_caps_config_iscsi {
 861         FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
 862         FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
 863         FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
 864         FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
 865 };
 866
 867 enum fw_caps_config_fcoe {
 868         FW_CAPS_CONFIG_FCOE_INITIATOR   = 0x00000001,
 869         FW_CAPS_CONFIG_FCOE_TARGET      = 0x00000002,
 870         FW_CAPS_CONFIG_FCOE_CTRL_OFLD   = 0x00000004,
 871 };
 872
 873 enum fw_memtype_cf {
 874         FW_MEMTYPE_CF_EDC0              = 0x0,
 875         FW_MEMTYPE_CF_EDC1              = 0x1,
 876         FW_MEMTYPE_CF_EXTMEM            = 0x2,
 877         FW_MEMTYPE_CF_FLASH             = 0x4,
 878         FW_MEMTYPE_CF_INTERNAL          = 0x5,
 879 };
 880
 881 struct fw_caps_config_cmd {
 882         __be32 op_to_write;
 883         __be32 cfvalid_to_len16;
 884         __be32 r2;
 885         __be32 hwmbitmap;
 886         __be16 nbmcaps;
 887         __be16 linkcaps;
 888         __be16 switchcaps;
 889         __be16 r3;
 890         __be16 niccaps;
 891         __be16 ofldcaps;
 892         __be16 rdmacaps;
 893         __be16 r4;
 894         __be16 iscsicaps;
 895         __be16 fcoecaps;
 896         __be32 cfcsum;
 897         __be32 finiver;
 898         __be32 finicsum;
 899 };
 900
 901 #define FW_CAPS_CONFIG_CMD_CFVALID          (1U << 27)
 902 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x)    ((x) << 24)
 903 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) ((x) << 16)
 904
 905 /*
 906  * params command mnemonics
 907  */
 908 enum fw_params_mnem {
 909         FW_PARAMS_MNEM_DEV              = 1,    /* device params */
 910         FW_PARAMS_MNEM_PFVF             = 2,    /* function params */
 911         FW_PARAMS_MNEM_REG              = 3,    /* limited register access */
 912         FW_PARAMS_MNEM_DMAQ             = 4,    /* dma queue params */
 913         FW_PARAMS_MNEM_LAST
 914 };
 915
 916 /*
 917  * device parameters
 918  */
 919 enum fw_params_param_dev {
 920         FW_PARAMS_PARAM_DEV_CCLK        = 0x00, /* chip core clock in khz */
 921         FW_PARAMS_PARAM_DEV_PORTVEC     = 0x01, /* the port vector */
 922         FW_PARAMS_PARAM_DEV_NTID        = 0x02, /* reads the number of TIDs
 923                                                  * allocated by the device's
 924                                                  * Lookup Engine
 925                                                  */
 926         FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
 927         FW_PARAMS_PARAM_DEV_INTVER_NIC  = 0x04,
 928         FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05,
 929         FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06,
 930         FW_PARAMS_PARAM_DEV_INTVER_RI   = 0x07,
 931         FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08,
 932         FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09,
 933         FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A,
 934         FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
 935         FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
 936         FW_PARAMS_PARAM_DEV_CF = 0x0D,
 937         FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD */
 938         FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER = 0x14, /* max supported adap IRD */
 939         FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
 940 };
 941
 942 /*
 943  * physical and virtual function parameters
 944  */
 945 enum fw_params_param_pfvf {
 946         FW_PARAMS_PARAM_PFVF_RWXCAPS    = 0x00,
 947         FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
 948         FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
 949         FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
 950         FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
 951         FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
 952         FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
 953         FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
 954         FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
 955         FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
 956         FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
 957         FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
 958         FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
 959         FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
 960         FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
 961         FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
 962         FW_PARAMS_PARAM_PFVF_RQ_END     = 0x10,
 963         FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
 964         FW_PARAMS_PARAM_PFVF_PBL_END    = 0x12,
 965         FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
 966         FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
 967         FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
 968         FW_PARAMS_PARAM_PFVF_SQRQ_END   = 0x16,
 969         FW_PARAMS_PARAM_PFVF_CQ_START   = 0x17,
 970         FW_PARAMS_PARAM_PFVF_CQ_END     = 0x18,
 971         FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
 972         FW_PARAMS_PARAM_PFVF_VIID       = 0x24,
 973         FW_PARAMS_PARAM_PFVF_CPMASK     = 0x25,
 974         FW_PARAMS_PARAM_PFVF_OCQ_START  = 0x26,
 975         FW_PARAMS_PARAM_PFVF_OCQ_END    = 0x27,
 976         FW_PARAMS_PARAM_PFVF_CONM_MAP   = 0x28,
 977         FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
 978         FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
 979         FW_PARAMS_PARAM_PFVF_EQ_START   = 0x2B,
 980         FW_PARAMS_PARAM_PFVF_EQ_END     = 0x2C,
 981         FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
 982         FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
 983         FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
 984         FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31
 985 };
 986
 987 /*
 988  * dma queue parameters
 989  */
 990 enum fw_params_param_dmaq {
 991         FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
 992         FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
 993         FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
 994         FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
 995         FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
 996         FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
 997 };
 998
 999 #define FW_PARAMS_MNEM(x)      ((x) << 24)
1000 #define FW_PARAMS_PARAM_X(x)   ((x) << 16)
1001 #define FW_PARAMS_PARAM_Y_SHIFT  8
1002 #define FW_PARAMS_PARAM_Y_MASK   0xffU
1003 #define FW_PARAMS_PARAM_Y(x)     ((x) << FW_PARAMS_PARAM_Y_SHIFT)
1004 #define FW_PARAMS_PARAM_Y_GET(x) (((x) >> FW_PARAMS_PARAM_Y_SHIFT) &\
1005                 FW_PARAMS_PARAM_Y_MASK)
1006 #define FW_PARAMS_PARAM_Z_SHIFT  0
1007 #define FW_PARAMS_PARAM_Z_MASK   0xffu
1008 #define FW_PARAMS_PARAM_Z(x)     ((x) << FW_PARAMS_PARAM_Z_SHIFT)
1009 #define FW_PARAMS_PARAM_Z_GET(x) (((x) >> FW_PARAMS_PARAM_Z_SHIFT) &\
1010                 FW_PARAMS_PARAM_Z_MASK)
1011 #define FW_PARAMS_PARAM_XYZ(x) ((x) << 0)
1012 #define FW_PARAMS_PARAM_YZ(x)  ((x) << 0)
1013
1014 struct fw_params_cmd {
1015         __be32 op_to_vfn;
1016         __be32 retval_len16;
1017         struct fw_params_param {
1018                 __be32 mnem;
1019                 __be32 val;
1020         } param[7];
1021 };
1022
1023 #define FW_PARAMS_CMD_PFN(x) ((x) << 8)
1024 #define FW_PARAMS_CMD_VFN(x) ((x) << 0)
1025
1026 struct fw_pfvf_cmd {
1027         __be32 op_to_vfn;
1028         __be32 retval_len16;
1029         __be32 niqflint_niq;
1030         __be32 type_to_neq;
1031         __be32 tc_to_nexactf;
1032         __be32 r_caps_to_nethctrl;
1033         __be16 nricq;
1034         __be16 nriqp;
1035         __be32 r4;
1036 };
1037
1038 #define FW_PFVF_CMD_PFN(x) ((x) << 8)
1039 #define FW_PFVF_CMD_VFN(x) ((x) << 0)
1040
1041 #define FW_PFVF_CMD_NIQFLINT(x) ((x) << 20)
1042 #define FW_PFVF_CMD_NIQFLINT_GET(x) (((x) >> 20) & 0xfff)
1043
1044 #define FW_PFVF_CMD_NIQ(x) ((x) << 0)
1045 #define FW_PFVF_CMD_NIQ_GET(x) (((x) >> 0) & 0xfffff)
1046
1047 #define FW_PFVF_CMD_TYPE (1 << 31)
1048 #define FW_PFVF_CMD_TYPE_GET(x) (((x) >> 31) & 0x1)
1049
1050 #define FW_PFVF_CMD_CMASK(x) ((x) << 24)
1051 #define FW_PFVF_CMD_CMASK_MASK 0xf
1052 #define FW_PFVF_CMD_CMASK_GET(x) (((x) >> 24) & FW_PFVF_CMD_CMASK_MASK)
1053
1054 #define FW_PFVF_CMD_PMASK(x) ((x) << 20)
1055 #define FW_PFVF_CMD_PMASK_MASK 0xf
1056 #define FW_PFVF_CMD_PMASK_GET(x) (((x) >> 20) & FW_PFVF_CMD_PMASK_MASK)
1057
1058 #define FW_PFVF_CMD_NEQ(x) ((x) << 0)
1059 #define FW_PFVF_CMD_NEQ_GET(x) (((x) >> 0) & 0xfffff)
1060
1061 #define FW_PFVF_CMD_TC(x) ((x) << 24)
1062 #define FW_PFVF_CMD_TC_GET(x) (((x) >> 24) & 0xff)
1063
1064 #define FW_PFVF_CMD_NVI(x) ((x) << 16)
1065 #define FW_PFVF_CMD_NVI_GET(x) (((x) >> 16) & 0xff)
1066
1067 #define FW_PFVF_CMD_NEXACTF(x) ((x) << 0)
1068 #define FW_PFVF_CMD_NEXACTF_GET(x) (((x) >> 0) & 0xffff)
1069
1070 #define FW_PFVF_CMD_R_CAPS(x) ((x) << 24)
1071 #define FW_PFVF_CMD_R_CAPS_GET(x) (((x) >> 24) & 0xff)
1072
1073 #define FW_PFVF_CMD_WX_CAPS(x) ((x) << 16)
1074 #define FW_PFVF_CMD_WX_CAPS_GET(x) (((x) >> 16) & 0xff)
1075
1076 #define FW_PFVF_CMD_NETHCTRL(x) ((x) << 0)
1077 #define FW_PFVF_CMD_NETHCTRL_GET(x) (((x) >> 0) & 0xffff)
1078
1079 enum fw_iq_type {
1080         FW_IQ_TYPE_FL_INT_CAP,
1081         FW_IQ_TYPE_NO_FL_INT_CAP
1082 };
1083
1084 struct fw_iq_cmd {
1085         __be32 op_to_vfn;
1086         __be32 alloc_to_len16;
1087         __be16 physiqid;
1088         __be16 iqid;
1089         __be16 fl0id;
1090         __be16 fl1id;
1091         __be32 type_to_iqandstindex;
1092         __be16 iqdroprss_to_iqesize;
1093         __be16 iqsize;
1094         __be64 iqaddr;
1095         __be32 iqns_to_fl0congen;
1096         __be16 fl0dcaen_to_fl0cidxfthresh;
1097         __be16 fl0size;
1098         __be64 fl0addr;
1099         __be32 fl1cngchmap_to_fl1congen;
1100         __be16 fl1dcaen_to_fl1cidxfthresh;
1101         __be16 fl1size;
1102         __be64 fl1addr;
1103 };
1104
1105 #define FW_IQ_CMD_PFN(x) ((x) << 8)
1106 #define FW_IQ_CMD_VFN(x) ((x) << 0)
1107
1108 #define FW_IQ_CMD_ALLOC (1U << 31)
1109 #define FW_IQ_CMD_FREE (1U << 30)
1110 #define FW_IQ_CMD_MODIFY (1U << 29)
1111 #define FW_IQ_CMD_IQSTART(x) ((x) << 28)
1112 #define FW_IQ_CMD_IQSTOP(x) ((x) << 27)
1113
1114 #define FW_IQ_CMD_TYPE(x) ((x) << 29)
1115 #define FW_IQ_CMD_IQASYNCH(x) ((x) << 28)
1116 #define FW_IQ_CMD_VIID(x) ((x) << 16)
1117 #define FW_IQ_CMD_IQANDST(x) ((x) << 15)
1118 #define FW_IQ_CMD_IQANUS(x) ((x) << 14)
1119 #define FW_IQ_CMD_IQANUD(x) ((x) << 12)
1120 #define FW_IQ_CMD_IQANDSTINDEX(x) ((x) << 0)
1121
1122 #define FW_IQ_CMD_IQDROPRSS (1U << 15)
1123 #define FW_IQ_CMD_IQGTSMODE (1U << 14)
1124 #define FW_IQ_CMD_IQPCIECH(x) ((x) << 12)
1125 #define FW_IQ_CMD_IQDCAEN(x) ((x) << 11)
1126 #define FW_IQ_CMD_IQDCACPU(x) ((x) << 6)
1127 #define FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << 4)
1128 #define FW_IQ_CMD_IQO (1U << 3)
1129 #define FW_IQ_CMD_IQCPRIO(x) ((x) << 2)
1130 #define FW_IQ_CMD_IQESIZE(x) ((x) << 0)
1131
1132 #define FW_IQ_CMD_IQNS(x) ((x) << 31)
1133 #define FW_IQ_CMD_IQRO(x) ((x) << 30)
1134 #define FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << 28)
1135 #define FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << 27)
1136 #define FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << 26)
1137 #define FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << 20)
1138 #define FW_IQ_CMD_FL0CACHELOCK(x) ((x) << 15)
1139 #define FW_IQ_CMD_FL0DBP(x) ((x) << 14)
1140 #define FW_IQ_CMD_FL0DATANS(x) ((x) << 13)
1141 #define FW_IQ_CMD_FL0DATARO(x) ((x) << 12)
1142 #define FW_IQ_CMD_FL0CONGCIF(x) ((x) << 11)
1143 #define FW_IQ_CMD_FL0ONCHIP(x) ((x) << 10)
1144 #define FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << 9)
1145 #define FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << 8)
1146 #define FW_IQ_CMD_FL0FETCHNS(x) ((x) << 7)
1147 #define FW_IQ_CMD_FL0FETCHRO(x) ((x) << 6)
1148 #define FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << 4)
1149 #define FW_IQ_CMD_FL0CPRIO(x) ((x) << 3)
1150 #define FW_IQ_CMD_FL0PADEN(x) ((x) << 2)
1151 #define FW_IQ_CMD_FL0PACKEN(x) ((x) << 1)
1152 #define FW_IQ_CMD_FL0CONGEN (1U << 0)
1153
1154 #define FW_IQ_CMD_FL0DCAEN(x) ((x) << 15)
1155 #define FW_IQ_CMD_FL0DCACPU(x) ((x) << 10)
1156 #define FW_IQ_CMD_FL0FBMIN(x) ((x) << 7)
1157 #define FW_IQ_CMD_FL0FBMAX(x) ((x) << 4)
1158 #define FW_IQ_CMD_FL0CIDXFTHRESHO (1U << 3)
1159 #define FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << 0)
1160
1161 #define FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << 20)
1162 #define FW_IQ_CMD_FL1CACHELOCK(x) ((x) << 15)
1163 #define FW_IQ_CMD_FL1DBP(x) ((x) << 14)
1164 #define FW_IQ_CMD_FL1DATANS(x) ((x) << 13)
1165 #define FW_IQ_CMD_FL1DATARO(x) ((x) << 12)
1166 #define FW_IQ_CMD_FL1CONGCIF(x) ((x) << 11)
1167 #define FW_IQ_CMD_FL1ONCHIP(x) ((x) << 10)
1168 #define FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << 9)
1169 #define FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << 8)
1170 #define FW_IQ_CMD_FL1FETCHNS(x) ((x) << 7)
1171 #define FW_IQ_CMD_FL1FETCHRO(x) ((x) << 6)
1172 #define FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << 4)
1173 #define FW_IQ_CMD_FL1CPRIO(x) ((x) << 3)
1174 #define FW_IQ_CMD_FL1PADEN (1U << 2)
1175 #define FW_IQ_CMD_FL1PACKEN (1U << 1)
1176 #define FW_IQ_CMD_FL1CONGEN (1U << 0)
1177
1178 #define FW_IQ_CMD_FL1DCAEN(x) ((x) << 15)
1179 #define FW_IQ_CMD_FL1DCACPU(x) ((x) << 10)
1180 #define FW_IQ_CMD_FL1FBMIN(x) ((x) << 7)
1181 #define FW_IQ_CMD_FL1FBMAX(x) ((x) << 4)
1182 #define FW_IQ_CMD_FL1CIDXFTHRESHO (1U << 3)
1183 #define FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << 0)
1184
1185 struct fw_eq_eth_cmd {
1186         __be32 op_to_vfn;
1187         __be32 alloc_to_len16;
1188         __be32 eqid_pkd;
1189         __be32 physeqid_pkd;
1190         __be32 fetchszm_to_iqid;
1191         __be32 dcaen_to_eqsize;
1192         __be64 eqaddr;
1193         __be32 viid_pkd;
1194         __be32 r8_lo;
1195         __be64 r9;
1196 };
1197
1198 #define FW_EQ_ETH_CMD_PFN(x) ((x) << 8)
1199 #define FW_EQ_ETH_CMD_VFN(x) ((x) << 0)
1200 #define FW_EQ_ETH_CMD_ALLOC (1U << 31)
1201 #define FW_EQ_ETH_CMD_FREE (1U << 30)
1202 #define FW_EQ_ETH_CMD_MODIFY (1U << 29)
1203 #define FW_EQ_ETH_CMD_EQSTART (1U << 28)
1204 #define FW_EQ_ETH_CMD_EQSTOP (1U << 27)
1205
1206 #define FW_EQ_ETH_CMD_EQID(x) ((x) << 0)
1207 #define FW_EQ_ETH_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
1208 #define FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << 0)
1209 #define FW_EQ_ETH_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff)
1210
1211 #define FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << 26)
1212 #define FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << 25)
1213 #define FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << 24)
1214 #define FW_EQ_ETH_CMD_FETCHNS(x) ((x) << 23)
1215 #define FW_EQ_ETH_CMD_FETCHRO(x) ((x) << 22)
1216 #define FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << 20)
1217 #define FW_EQ_ETH_CMD_CPRIO(x) ((x) << 19)
1218 #define FW_EQ_ETH_CMD_ONCHIP(x) ((x) << 18)
1219 #define FW_EQ_ETH_CMD_PCIECHN(x) ((x) << 16)
1220 #define FW_EQ_ETH_CMD_IQID(x) ((x) << 0)
1221
1222 #define FW_EQ_ETH_CMD_DCAEN(x) ((x) << 31)
1223 #define FW_EQ_ETH_CMD_DCACPU(x) ((x) << 26)
1224 #define FW_EQ_ETH_CMD_FBMIN(x) ((x) << 23)
1225 #define FW_EQ_ETH_CMD_FBMAX(x) ((x) << 20)
1226 #define FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << 19)
1227 #define FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << 16)
1228 #define FW_EQ_ETH_CMD_EQSIZE(x) ((x) << 0)
1229
1230 #define FW_EQ_ETH_CMD_AUTOEQUEQE (1U << 30)
1231 #define FW_EQ_ETH_CMD_VIID(x) ((x) << 16)
1232
1233 struct fw_eq_ctrl_cmd {
1234         __be32 op_to_vfn;
1235         __be32 alloc_to_len16;
1236         __be32 cmpliqid_eqid;
1237         __be32 physeqid_pkd;
1238         __be32 fetchszm_to_iqid;
1239         __be32 dcaen_to_eqsize;
1240         __be64 eqaddr;
1241 };
1242
1243 #define FW_EQ_CTRL_CMD_PFN(x) ((x) << 8)
1244 #define FW_EQ_CTRL_CMD_VFN(x) ((x) << 0)
1245
1246 #define FW_EQ_CTRL_CMD_ALLOC (1U << 31)
1247 #define FW_EQ_CTRL_CMD_FREE (1U << 30)
1248 #define FW_EQ_CTRL_CMD_MODIFY (1U << 29)
1249 #define FW_EQ_CTRL_CMD_EQSTART (1U << 28)
1250 #define FW_EQ_CTRL_CMD_EQSTOP (1U << 27)
1251
1252 #define FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << 20)
1253 #define FW_EQ_CTRL_CMD_EQID(x) ((x) << 0)
1254 #define FW_EQ_CTRL_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
1255 #define FW_EQ_CTRL_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff)
1256
1257 #define FW_EQ_CTRL_CMD_FETCHSZM (1U << 26)
1258 #define FW_EQ_CTRL_CMD_STATUSPGNS (1U << 25)
1259 #define FW_EQ_CTRL_CMD_STATUSPGRO (1U << 24)
1260 #define FW_EQ_CTRL_CMD_FETCHNS (1U << 23)
1261 #define FW_EQ_CTRL_CMD_FETCHRO (1U << 22)
1262 #define FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << 20)
1263 #define FW_EQ_CTRL_CMD_CPRIO(x) ((x) << 19)
1264 #define FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << 18)
1265 #define FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << 16)
1266 #define FW_EQ_CTRL_CMD_IQID(x) ((x) << 0)
1267
1268 #define FW_EQ_CTRL_CMD_DCAEN(x) ((x) << 31)
1269 #define FW_EQ_CTRL_CMD_DCACPU(x) ((x) << 26)
1270 #define FW_EQ_CTRL_CMD_FBMIN(x) ((x) << 23)
1271 #define FW_EQ_CTRL_CMD_FBMAX(x) ((x) << 20)
1272 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) ((x) << 19)
1273 #define FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << 16)
1274 #define FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << 0)
1275
1276 struct fw_eq_ofld_cmd {
1277         __be32 op_to_vfn;
1278         __be32 alloc_to_len16;
1279         __be32 eqid_pkd;
1280         __be32 physeqid_pkd;
1281         __be32 fetchszm_to_iqid;
1282         __be32 dcaen_to_eqsize;
1283         __be64 eqaddr;
1284 };
1285
1286 #define FW_EQ_OFLD_CMD_PFN(x) ((x) << 8)
1287 #define FW_EQ_OFLD_CMD_VFN(x) ((x) << 0)
1288
1289 #define FW_EQ_OFLD_CMD_ALLOC (1U << 31)
1290 #define FW_EQ_OFLD_CMD_FREE (1U << 30)
1291 #define FW_EQ_OFLD_CMD_MODIFY (1U << 29)
1292 #define FW_EQ_OFLD_CMD_EQSTART (1U << 28)
1293 #define FW_EQ_OFLD_CMD_EQSTOP (1U << 27)
1294
1295 #define FW_EQ_OFLD_CMD_EQID(x) ((x) << 0)
1296 #define FW_EQ_OFLD_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
1297 #define FW_EQ_OFLD_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff)
1298
1299 #define FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << 26)
1300 #define FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << 25)
1301 #define FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << 24)
1302 #define FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << 23)
1303 #define FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << 22)
1304 #define FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << 20)
1305 #define FW_EQ_OFLD_CMD_CPRIO(x) ((x) << 19)
1306 #define FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << 18)
1307 #define FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << 16)
1308 #define FW_EQ_OFLD_CMD_IQID(x) ((x) << 0)
1309
1310 #define FW_EQ_OFLD_CMD_DCAEN(x) ((x) << 31)
1311 #define FW_EQ_OFLD_CMD_DCACPU(x) ((x) << 26)
1312 #define FW_EQ_OFLD_CMD_FBMIN(x) ((x) << 23)
1313 #define FW_EQ_OFLD_CMD_FBMAX(x) ((x) << 20)
1314 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) ((x) << 19)
1315 #define FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << 16)
1316 #define FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << 0)
1317
1318 /*
1319  * Macros for VIID parsing:
1320  * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
1321  */
1322 #define FW_VIID_PFN_GET(x) (((x) >> 8) & 0x7)
1323 #define FW_VIID_VIVLD_GET(x) (((x) >> 7) & 0x1)
1324 #define FW_VIID_VIN_GET(x) (((x) >> 0) & 0x7F)
1325
1326 struct fw_vi_cmd {
1327         __be32 op_to_vfn;
1328         __be32 alloc_to_len16;
1329         __be16 type_viid;
1330         u8 mac[6];
1331         u8 portid_pkd;
1332         u8 nmac;
1333         u8 nmac0[6];
1334         __be16 rsssize_pkd;
1335         u8 nmac1[6];
1336         __be16 idsiiq_pkd;
1337         u8 nmac2[6];
1338         __be16 idseiq_pkd;
1339         u8 nmac3[6];
1340         __be64 r9;
1341         __be64 r10;
1342 };
1343
1344 #define FW_VI_CMD_PFN(x) ((x) << 8)
1345 #define FW_VI_CMD_VFN(x) ((x) << 0)
1346 #define FW_VI_CMD_ALLOC (1U << 31)
1347 #define FW_VI_CMD_FREE (1U << 30)
1348 #define FW_VI_CMD_VIID(x) ((x) << 0)
1349 #define FW_VI_CMD_VIID_GET(x) ((x) & 0xfff)
1350 #define FW_VI_CMD_PORTID(x) ((x) << 4)
1351 #define FW_VI_CMD_PORTID_GET(x) (((x) >> 4) & 0xf)
1352 #define FW_VI_CMD_RSSSIZE_GET(x) (((x) >> 0) & 0x7ff)
1353
1354 /* Special VI_MAC command index ids */
1355 #define FW_VI_MAC_ADD_MAC               0x3FF
1356 #define FW_VI_MAC_ADD_PERSIST_MAC       0x3FE
1357 #define FW_VI_MAC_MAC_BASED_FREE        0x3FD
1358 #define FW_CLS_TCAM_NUM_ENTRIES         336
1359
1360 enum fw_vi_mac_smac {
1361         FW_VI_MAC_MPS_TCAM_ENTRY,
1362         FW_VI_MAC_MPS_TCAM_ONLY,
1363         FW_VI_MAC_SMT_ONLY,
1364         FW_VI_MAC_SMT_AND_MPSTCAM
1365 };
1366
1367 enum fw_vi_mac_result {
1368         FW_VI_MAC_R_SUCCESS,
1369         FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
1370         FW_VI_MAC_R_SMAC_FAIL,
1371         FW_VI_MAC_R_F_ACL_CHECK
1372 };
1373
1374 struct fw_vi_mac_cmd {
1375         __be32 op_to_viid;
1376         __be32 freemacs_to_len16;
1377         union fw_vi_mac {
1378                 struct fw_vi_mac_exact {
1379                         __be16 valid_to_idx;
1380                         u8 macaddr[6];
1381                 } exact[7];
1382                 struct fw_vi_mac_hash {
1383                         __be64 hashvec;
1384                 } hash;
1385         } u;
1386 };
1387
1388 #define FW_VI_MAC_CMD_VIID(x) ((x) << 0)
1389 #define FW_VI_MAC_CMD_FREEMACS(x) ((x) << 31)
1390 #define FW_VI_MAC_CMD_HASHVECEN (1U << 23)
1391 #define FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << 22)
1392 #define FW_VI_MAC_CMD_VALID (1U << 15)
1393 #define FW_VI_MAC_CMD_PRIO(x) ((x) << 12)
1394 #define FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << 10)
1395 #define FW_VI_MAC_CMD_SMAC_RESULT_GET(x) (((x) >> 10) & 0x3)
1396 #define FW_VI_MAC_CMD_IDX(x) ((x) << 0)
1397 #define FW_VI_MAC_CMD_IDX_GET(x) (((x) >> 0) & 0x3ff)
1398
1399 #define FW_RXMODE_MTU_NO_CHG    65535
1400
1401 struct fw_vi_rxmode_cmd {
1402         __be32 op_to_viid;
1403         __be32 retval_len16;
1404         __be32 mtu_to_vlanexen;
1405         __be32 r4_lo;
1406 };
1407
1408 #define FW_VI_RXMODE_CMD_VIID(x) ((x) << 0)
1409 #define FW_VI_RXMODE_CMD_MTU_MASK 0xffff
1410 #define FW_VI_RXMODE_CMD_MTU(x) ((x) << 16)
1411 #define FW_VI_RXMODE_CMD_PROMISCEN_MASK 0x3
1412 #define FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << 14)
1413 #define FW_VI_RXMODE_CMD_ALLMULTIEN_MASK 0x3
1414 #define FW_VI_RXMODE_CMD_ALLMULTIEN(x) ((x) << 12)
1415 #define FW_VI_RXMODE_CMD_BROADCASTEN_MASK 0x3
1416 #define FW_VI_RXMODE_CMD_BROADCASTEN(x) ((x) << 10)
1417 #define FW_VI_RXMODE_CMD_VLANEXEN_MASK 0x3
1418 #define FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << 8)
1419
1420 struct fw_vi_enable_cmd {
1421         __be32 op_to_viid;
1422         __be32 ien_to_len16;
1423         __be16 blinkdur;
1424         __be16 r3;
1425         __be32 r4;
1426 };
1427
1428 #define FW_VI_ENABLE_CMD_VIID(x) ((x) << 0)
1429 #define FW_VI_ENABLE_CMD_IEN(x) ((x) << 31)
1430 #define FW_VI_ENABLE_CMD_EEN(x) ((x) << 30)
1431 #define FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << 28)
1432 #define FW_VI_ENABLE_CMD_LED (1U << 29)
1433
1434 /* VI VF stats offset definitions */
1435 #define VI_VF_NUM_STATS 16
1436 enum fw_vi_stats_vf_index {
1437         FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
1438         FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
1439         FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
1440         FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
1441         FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
1442         FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
1443         FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
1444         FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
1445         FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
1446         FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
1447         FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
1448         FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
1449         FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
1450         FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
1451         FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
1452         FW_VI_VF_STAT_RX_ERR_FRAMES_IX
1453 };
1454
1455 /* VI PF stats offset definitions */
1456 #define VI_PF_NUM_STATS 17
1457 enum fw_vi_stats_pf_index {
1458         FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
1459         FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
1460         FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
1461         FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
1462         FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
1463         FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
1464         FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
1465         FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
1466         FW_VI_PF_STAT_RX_BYTES_IX,
1467         FW_VI_PF_STAT_RX_FRAMES_IX,
1468         FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
1469         FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
1470         FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
1471         FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
1472         FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
1473         FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
1474         FW_VI_PF_STAT_RX_ERR_FRAMES_IX
1475 };
1476
1477 struct fw_vi_stats_cmd {
1478         __be32 op_to_viid;
1479         __be32 retval_len16;
1480         union fw_vi_stats {
1481                 struct fw_vi_stats_ctl {
1482                         __be16 nstats_ix;
1483                         __be16 r6;
1484                         __be32 r7;
1485                         __be64 stat0;
1486                         __be64 stat1;
1487                         __be64 stat2;
1488                         __be64 stat3;
1489                         __be64 stat4;
1490                         __be64 stat5;
1491                 } ctl;
1492                 struct fw_vi_stats_pf {
1493                         __be64 tx_bcast_bytes;
1494                         __be64 tx_bcast_frames;
1495                         __be64 tx_mcast_bytes;
1496                         __be64 tx_mcast_frames;
1497                         __be64 tx_ucast_bytes;
1498                         __be64 tx_ucast_frames;
1499                         __be64 tx_offload_bytes;
1500                         __be64 tx_offload_frames;
1501                         __be64 rx_pf_bytes;
1502                         __be64 rx_pf_frames;
1503                         __be64 rx_bcast_bytes;
1504                         __be64 rx_bcast_frames;
1505                         __be64 rx_mcast_bytes;
1506                         __be64 rx_mcast_frames;
1507                         __be64 rx_ucast_bytes;
1508                         __be64 rx_ucast_frames;
1509                         __be64 rx_err_frames;
1510                 } pf;
1511                 struct fw_vi_stats_vf {
1512                         __be64 tx_bcast_bytes;
1513                         __be64 tx_bcast_frames;
1514                         __be64 tx_mcast_bytes;
1515                         __be64 tx_mcast_frames;
1516                         __be64 tx_ucast_bytes;
1517                         __be64 tx_ucast_frames;
1518                         __be64 tx_drop_frames;
1519                         __be64 tx_offload_bytes;
1520                         __be64 tx_offload_frames;
1521                         __be64 rx_bcast_bytes;
1522                         __be64 rx_bcast_frames;
1523                         __be64 rx_mcast_bytes;
1524                         __be64 rx_mcast_frames;
1525                         __be64 rx_ucast_bytes;
1526                         __be64 rx_ucast_frames;
1527                         __be64 rx_err_frames;
1528                 } vf;
1529         } u;
1530 };
1531
1532 #define FW_VI_STATS_CMD_VIID(x) ((x) << 0)
1533 #define FW_VI_STATS_CMD_NSTATS(x) ((x) << 12)
1534 #define FW_VI_STATS_CMD_IX(x) ((x) << 0)
1535
1536 struct fw_acl_mac_cmd {
1537         __be32 op_to_vfn;
1538         __be32 en_to_len16;
1539         u8 nmac;
1540         u8 r3[7];
1541         __be16 r4;
1542         u8 macaddr0[6];
1543         __be16 r5;
1544         u8 macaddr1[6];
1545         __be16 r6;
1546         u8 macaddr2[6];
1547         __be16 r7;
1548         u8 macaddr3[6];
1549 };
1550
1551 #define FW_ACL_MAC_CMD_PFN(x) ((x) << 8)
1552 #define FW_ACL_MAC_CMD_VFN(x) ((x) << 0)
1553 #define FW_ACL_MAC_CMD_EN(x) ((x) << 31)
1554
1555 struct fw_acl_vlan_cmd {
1556         __be32 op_to_vfn;
1557         __be32 en_to_len16;
1558         u8 nvlan;
1559         u8 dropnovlan_fm;
1560         u8 r3_lo[6];
1561         __be16 vlanid[16];
1562 };
1563
1564 #define FW_ACL_VLAN_CMD_PFN(x) ((x) << 8)
1565 #define FW_ACL_VLAN_CMD_VFN(x) ((x) << 0)
1566 #define FW_ACL_VLAN_CMD_EN(x) ((x) << 31)
1567 #define FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << 7)
1568 #define FW_ACL_VLAN_CMD_FM(x) ((x) << 6)
1569
1570 enum fw_port_cap {
1571         FW_PORT_CAP_SPEED_100M          = 0x0001,
1572         FW_PORT_CAP_SPEED_1G            = 0x0002,
1573         FW_PORT_CAP_SPEED_2_5G          = 0x0004,
1574         FW_PORT_CAP_SPEED_10G           = 0x0008,
1575         FW_PORT_CAP_SPEED_40G           = 0x0010,
1576         FW_PORT_CAP_SPEED_100G          = 0x0020,
1577         FW_PORT_CAP_FC_RX               = 0x0040,
1578         FW_PORT_CAP_FC_TX               = 0x0080,
1579         FW_PORT_CAP_ANEG                = 0x0100,
1580         FW_PORT_CAP_MDI_0               = 0x0200,
1581         FW_PORT_CAP_MDI_1               = 0x0400,
1582         FW_PORT_CAP_BEAN                = 0x0800,
1583         FW_PORT_CAP_PMA_LPBK            = 0x1000,
1584         FW_PORT_CAP_PCS_LPBK            = 0x2000,
1585         FW_PORT_CAP_PHYXS_LPBK          = 0x4000,
1586         FW_PORT_CAP_FAR_END_LPBK        = 0x8000,
1587 };
1588
1589 enum fw_port_mdi {
1590         FW_PORT_MDI_UNCHANGED,
1591         FW_PORT_MDI_AUTO,
1592         FW_PORT_MDI_F_STRAIGHT,
1593         FW_PORT_MDI_F_CROSSOVER
1594 };
1595
1596 #define FW_PORT_MDI(x) ((x) << 9)
1597
1598 enum fw_port_action {
1599         FW_PORT_ACTION_L1_CFG           = 0x0001,
1600         FW_PORT_ACTION_L2_CFG           = 0x0002,
1601         FW_PORT_ACTION_GET_PORT_INFO    = 0x0003,
1602         FW_PORT_ACTION_L2_PPP_CFG       = 0x0004,
1603         FW_PORT_ACTION_L2_DCB_CFG       = 0x0005,
1604         FW_PORT_ACTION_DCB_READ_TRANS   = 0x0006,
1605         FW_PORT_ACTION_DCB_READ_RECV    = 0x0007,
1606         FW_PORT_ACTION_DCB_READ_DET     = 0x0008,
1607         FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
1608         FW_PORT_ACTION_L1_LOW_PWR_EN    = 0x0011,
1609         FW_PORT_ACTION_L2_WOL_MODE_EN   = 0x0012,
1610         FW_PORT_ACTION_LPBK_TO_NORMAL   = 0x0020,
1611         FW_PORT_ACTION_L1_LPBK          = 0x0021,
1612         FW_PORT_ACTION_L1_PMA_LPBK      = 0x0022,
1613         FW_PORT_ACTION_L1_PCS_LPBK      = 0x0023,
1614         FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024,
1615         FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025,
1616         FW_PORT_ACTION_PHY_RESET        = 0x0040,
1617         FW_PORT_ACTION_PMA_RESET        = 0x0041,
1618         FW_PORT_ACTION_PCS_RESET        = 0x0042,
1619         FW_PORT_ACTION_PHYXS_RESET      = 0x0043,
1620         FW_PORT_ACTION_DTEXS_REEST      = 0x0044,
1621         FW_PORT_ACTION_AN_RESET         = 0x0045
1622 };
1623
1624 enum fw_port_l2cfg_ctlbf {
1625         FW_PORT_L2_CTLBF_OVLAN0 = 0x01,
1626         FW_PORT_L2_CTLBF_OVLAN1 = 0x02,
1627         FW_PORT_L2_CTLBF_OVLAN2 = 0x04,
1628         FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
1629         FW_PORT_L2_CTLBF_IVLAN  = 0x10,
1630         FW_PORT_L2_CTLBF_TXIPG  = 0x20
1631 };
1632
1633 enum fw_port_dcb_versions {
1634         FW_PORT_DCB_VER_UNKNOWN,
1635         FW_PORT_DCB_VER_CEE1D0,
1636         FW_PORT_DCB_VER_CEE1D01,
1637         FW_PORT_DCB_VER_IEEE,
1638         FW_PORT_DCB_VER_AUTO = 7
1639 };
1640
1641 enum fw_port_dcb_cfg {
1642         FW_PORT_DCB_CFG_PG      = 0x01,
1643         FW_PORT_DCB_CFG_PFC     = 0x02,
1644         FW_PORT_DCB_CFG_APPL    = 0x04
1645 };
1646
1647 enum fw_port_dcb_cfg_rc {
1648         FW_PORT_DCB_CFG_SUCCESS = 0x0,
1649         FW_PORT_DCB_CFG_ERROR   = 0x1
1650 };
1651
1652 enum fw_port_dcb_type {
1653         FW_PORT_DCB_TYPE_PGID           = 0x00,
1654         FW_PORT_DCB_TYPE_PGRATE         = 0x01,
1655         FW_PORT_DCB_TYPE_PRIORATE       = 0x02,
1656         FW_PORT_DCB_TYPE_PFC            = 0x03,
1657         FW_PORT_DCB_TYPE_APP_ID         = 0x04,
1658         FW_PORT_DCB_TYPE_CONTROL        = 0x05,
1659 };
1660
1661 enum fw_port_dcb_feature_state {
1662         FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0,
1663         FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1,
1664         FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2,
1665         FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3,
1666 };
1667
1668 struct fw_port_cmd {
1669         __be32 op_to_portid;
1670         __be32 action_to_len16;
1671         union fw_port {
1672                 struct fw_port_l1cfg {
1673                         __be32 rcap;
1674                         __be32 r;
1675                 } l1cfg;
1676                 struct fw_port_l2cfg {
1677                         __u8   ctlbf;
1678                         __u8   ovlan3_to_ivlan0;
1679                         __be16 ivlantype;
1680                         __be16 txipg_force_pinfo;
1681                         __be16 mtu;
1682                         __be16 ovlan0mask;
1683                         __be16 ovlan0type;
1684                         __be16 ovlan1mask;
1685                         __be16 ovlan1type;
1686                         __be16 ovlan2mask;
1687                         __be16 ovlan2type;
1688                         __be16 ovlan3mask;
1689                         __be16 ovlan3type;
1690                 } l2cfg;
1691                 struct fw_port_info {
1692                         __be32 lstatus_to_modtype;
1693                         __be16 pcap;
1694                         __be16 acap;
1695                         __be16 mtu;
1696                         __u8   cbllen;
1697                         __u8   auxlinfo;
1698                         __u8   dcbxdis_pkd;
1699                         __u8   r8_lo[3];
1700                         __be64 r9;
1701                 } info;
1702                 struct fw_port_diags {
1703                         __u8   diagop;
1704                         __u8   r[3];
1705                         __be32 diagval;
1706                 } diags;
1707                 union fw_port_dcb {
1708                         struct fw_port_dcb_pgid {
1709                                 __u8   type;
1710                                 __u8   apply_pkd;
1711                                 __u8   r10_lo[2];
1712                                 __be32 pgid;
1713                                 __be64 r11;
1714                         } pgid;
1715                         struct fw_port_dcb_pgrate {
1716                                 __u8   type;
1717                                 __u8   apply_pkd;
1718                                 __u8   r10_lo[5];
1719                                 __u8   num_tcs_supported;
1720                                 __u8   pgrate[8];
1721                                 __u8   tsa[8];
1722                         } pgrate;
1723                         struct fw_port_dcb_priorate {
1724                                 __u8   type;
1725                                 __u8   apply_pkd;
1726                                 __u8   r10_lo[6];
1727                                 __u8   strict_priorate[8];
1728                         } priorate;
1729                         struct fw_port_dcb_pfc {
1730                                 __u8   type;
1731                                 __u8   pfcen;
1732                                 __u8   r10[5];
1733                                 __u8   max_pfc_tcs;
1734                                 __be64 r11;
1735                         } pfc;
1736                         struct fw_port_app_priority {
1737                                 __u8   type;
1738                                 __u8   r10[2];
1739                                 __u8   idx;
1740                                 __u8   user_prio_map;
1741                                 __u8   sel_field;
1742                                 __be16 protocolid;
1743                                 __be64 r12;
1744                         } app_priority;
1745                         struct fw_port_dcb_control {
1746                                 __u8   type;
1747                                 __u8   all_syncd_pkd;
1748                                 __be16 dcb_version_to_app_state;
1749                                 __be32 r11;
1750                                 __be64 r12;
1751                         } control;
1752                 } dcb;
1753         } u;
1754 };
1755
1756 #define FW_PORT_CMD_READ (1U << 22)
1757
1758 #define FW_PORT_CMD_PORTID(x) ((x) << 0)
1759 #define FW_PORT_CMD_PORTID_GET(x) (((x) >> 0) & 0xf)
1760
1761 #define FW_PORT_CMD_ACTION(x) ((x) << 16)
1762 #define FW_PORT_CMD_ACTION_GET(x) (((x) >> 16) & 0xffff)
1763
1764 #define FW_PORT_CMD_CTLBF(x) ((x) << 10)
1765 #define FW_PORT_CMD_OVLAN3(x) ((x) << 7)
1766 #define FW_PORT_CMD_OVLAN2(x) ((x) << 6)
1767 #define FW_PORT_CMD_OVLAN1(x) ((x) << 5)
1768 #define FW_PORT_CMD_OVLAN0(x) ((x) << 4)
1769 #define FW_PORT_CMD_IVLAN0(x) ((x) << 3)
1770
1771 #define FW_PORT_CMD_TXIPG(x) ((x) << 19)
1772
1773 #define FW_PORT_CMD_LSTATUS (1U << 31)
1774 #define FW_PORT_CMD_LSTATUS_GET(x) (((x) >> 31) & 0x1)
1775 #define FW_PORT_CMD_LSPEED(x) ((x) << 24)
1776 #define FW_PORT_CMD_LSPEED_GET(x) (((x) >> 24) & 0x3f)
1777 #define FW_PORT_CMD_TXPAUSE (1U << 23)
1778 #define FW_PORT_CMD_RXPAUSE (1U << 22)
1779 #define FW_PORT_CMD_MDIOCAP (1U << 21)
1780 #define FW_PORT_CMD_MDIOADDR_GET(x) (((x) >> 16) & 0x1f)
1781 #define FW_PORT_CMD_LPTXPAUSE (1U << 15)
1782 #define FW_PORT_CMD_LPRXPAUSE (1U << 14)
1783 #define FW_PORT_CMD_PTYPE_MASK 0x1f
1784 #define FW_PORT_CMD_PTYPE_GET(x) (((x) >> 8) & FW_PORT_CMD_PTYPE_MASK)
1785 #define FW_PORT_CMD_MODTYPE_MASK 0x1f
1786 #define FW_PORT_CMD_MODTYPE_GET(x) (((x) >> 0) & FW_PORT_CMD_MODTYPE_MASK)
1787
1788 #define FW_PORT_CMD_DCBXDIS (1U << 7)
1789 #define FW_PORT_CMD_APPLY (1U <<  7)
1790 #define FW_PORT_CMD_ALL_SYNCD (1U << 7)
1791 #define FW_PORT_CMD_DCB_VERSION_GET(x) (((x) >> 8) & 0xf)
1792
1793 #define FW_PORT_CMD_PPPEN(x) ((x) << 31)
1794 #define FW_PORT_CMD_TPSRC(x) ((x) << 28)
1795 #define FW_PORT_CMD_NCSISRC(x) ((x) << 24)
1796
1797 #define FW_PORT_CMD_CH0(x) ((x) << 20)
1798 #define FW_PORT_CMD_CH1(x) ((x) << 16)
1799 #define FW_PORT_CMD_CH2(x) ((x) << 12)
1800 #define FW_PORT_CMD_CH3(x) ((x) << 8)
1801 #define FW_PORT_CMD_NCSICH(x) ((x) << 4)
1802
1803 enum fw_port_type {
1804         FW_PORT_TYPE_FIBER_XFI,
1805         FW_PORT_TYPE_FIBER_XAUI,
1806         FW_PORT_TYPE_BT_SGMII,
1807         FW_PORT_TYPE_BT_XFI,
1808         FW_PORT_TYPE_BT_XAUI,
1809         FW_PORT_TYPE_KX4,
1810         FW_PORT_TYPE_CX4,
1811         FW_PORT_TYPE_KX,
1812         FW_PORT_TYPE_KR,
1813         FW_PORT_TYPE_SFP,
1814         FW_PORT_TYPE_BP_AP,
1815         FW_PORT_TYPE_BP4_AP,
1816         FW_PORT_TYPE_QSFP_10G,
1817         FW_PORT_TYPE_QSFP,
1818         FW_PORT_TYPE_BP40_BA,
1819
1820         FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_MASK
1821 };
1822
1823 enum fw_port_module_type {
1824         FW_PORT_MOD_TYPE_NA,
1825         FW_PORT_MOD_TYPE_LR,
1826         FW_PORT_MOD_TYPE_SR,
1827         FW_PORT_MOD_TYPE_ER,
1828         FW_PORT_MOD_TYPE_TWINAX_PASSIVE,
1829         FW_PORT_MOD_TYPE_TWINAX_ACTIVE,
1830         FW_PORT_MOD_TYPE_LRM,
1831         FW_PORT_MOD_TYPE_ERROR          = FW_PORT_CMD_MODTYPE_MASK - 3,
1832         FW_PORT_MOD_TYPE_UNKNOWN        = FW_PORT_CMD_MODTYPE_MASK - 2,
1833         FW_PORT_MOD_TYPE_NOTSUPPORTED   = FW_PORT_CMD_MODTYPE_MASK - 1,
1834
1835         FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_MASK
1836 };
1837
1838 enum fw_port_mod_sub_type {
1839         FW_PORT_MOD_SUB_TYPE_NA,
1840         FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
1841         FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
1842         FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
1843         FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
1844         FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
1845         FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
1846
1847         /* The following will never been in the VPD.  They are TWINAX cable
1848          * lengths decoded from SFP+ module i2c PROMs.  These should
1849          * almost certainly go somewhere else ...
1850          */
1851         FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
1852         FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
1853         FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
1854         FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
1855 };
1856
1857 /* port stats */
1858 #define FW_NUM_PORT_STATS 50
1859 #define FW_NUM_PORT_TX_STATS 23
1860 #define FW_NUM_PORT_RX_STATS 27
1861
1862 enum fw_port_stats_tx_index {
1863         FW_STAT_TX_PORT_BYTES_IX,
1864         FW_STAT_TX_PORT_FRAMES_IX,
1865         FW_STAT_TX_PORT_BCAST_IX,
1866         FW_STAT_TX_PORT_MCAST_IX,
1867         FW_STAT_TX_PORT_UCAST_IX,
1868         FW_STAT_TX_PORT_ERROR_IX,
1869         FW_STAT_TX_PORT_64B_IX,
1870         FW_STAT_TX_PORT_65B_127B_IX,
1871         FW_STAT_TX_PORT_128B_255B_IX,
1872         FW_STAT_TX_PORT_256B_511B_IX,
1873         FW_STAT_TX_PORT_512B_1023B_IX,
1874         FW_STAT_TX_PORT_1024B_1518B_IX,
1875         FW_STAT_TX_PORT_1519B_MAX_IX,
1876         FW_STAT_TX_PORT_DROP_IX,
1877         FW_STAT_TX_PORT_PAUSE_IX,
1878         FW_STAT_TX_PORT_PPP0_IX,
1879         FW_STAT_TX_PORT_PPP1_IX,
1880         FW_STAT_TX_PORT_PPP2_IX,
1881         FW_STAT_TX_PORT_PPP3_IX,
1882         FW_STAT_TX_PORT_PPP4_IX,
1883         FW_STAT_TX_PORT_PPP5_IX,
1884         FW_STAT_TX_PORT_PPP6_IX,
1885         FW_STAT_TX_PORT_PPP7_IX
1886 };
1887
1888 enum fw_port_stat_rx_index {
1889         FW_STAT_RX_PORT_BYTES_IX,
1890         FW_STAT_RX_PORT_FRAMES_IX,
1891         FW_STAT_RX_PORT_BCAST_IX,
1892         FW_STAT_RX_PORT_MCAST_IX,
1893         FW_STAT_RX_PORT_UCAST_IX,
1894         FW_STAT_RX_PORT_MTU_ERROR_IX,
1895         FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
1896         FW_STAT_RX_PORT_CRC_ERROR_IX,
1897         FW_STAT_RX_PORT_LEN_ERROR_IX,
1898         FW_STAT_RX_PORT_SYM_ERROR_IX,
1899         FW_STAT_RX_PORT_64B_IX,
1900         FW_STAT_RX_PORT_65B_127B_IX,
1901         FW_STAT_RX_PORT_128B_255B_IX,
1902         FW_STAT_RX_PORT_256B_511B_IX,
1903         FW_STAT_RX_PORT_512B_1023B_IX,
1904         FW_STAT_RX_PORT_1024B_1518B_IX,
1905         FW_STAT_RX_PORT_1519B_MAX_IX,
1906         FW_STAT_RX_PORT_PAUSE_IX,
1907         FW_STAT_RX_PORT_PPP0_IX,
1908         FW_STAT_RX_PORT_PPP1_IX,
1909         FW_STAT_RX_PORT_PPP2_IX,
1910         FW_STAT_RX_PORT_PPP3_IX,
1911         FW_STAT_RX_PORT_PPP4_IX,
1912         FW_STAT_RX_PORT_PPP5_IX,
1913         FW_STAT_RX_PORT_PPP6_IX,
1914         FW_STAT_RX_PORT_PPP7_IX,
1915         FW_STAT_RX_PORT_LESS_64B_IX
1916 };
1917
1918 struct fw_port_stats_cmd {
1919         __be32 op_to_portid;
1920         __be32 retval_len16;
1921         union fw_port_stats {
1922                 struct fw_port_stats_ctl {
1923                         u8 nstats_bg_bm;
1924                         u8 tx_ix;
1925                         __be16 r6;
1926                         __be32 r7;
1927                         __be64 stat0;
1928                         __be64 stat1;
1929                         __be64 stat2;
1930                         __be64 stat3;
1931                         __be64 stat4;
1932                         __be64 stat5;
1933                 } ctl;
1934                 struct fw_port_stats_all {
1935                         __be64 tx_bytes;
1936                         __be64 tx_frames;
1937                         __be64 tx_bcast;
1938                         __be64 tx_mcast;
1939                         __be64 tx_ucast;
1940                         __be64 tx_error;
1941                         __be64 tx_64b;
1942                         __be64 tx_65b_127b;
1943                         __be64 tx_128b_255b;
1944                         __be64 tx_256b_511b;
1945                         __be64 tx_512b_1023b;
1946                         __be64 tx_1024b_1518b;
1947                         __be64 tx_1519b_max;
1948                         __be64 tx_drop;
1949                         __be64 tx_pause;
1950                         __be64 tx_ppp0;
1951                         __be64 tx_ppp1;
1952                         __be64 tx_ppp2;
1953                         __be64 tx_ppp3;
1954                         __be64 tx_ppp4;
1955                         __be64 tx_ppp5;
1956                         __be64 tx_ppp6;
1957                         __be64 tx_ppp7;
1958                         __be64 rx_bytes;
1959                         __be64 rx_frames;
1960                         __be64 rx_bcast;
1961                         __be64 rx_mcast;
1962                         __be64 rx_ucast;
1963                         __be64 rx_mtu_error;
1964                         __be64 rx_mtu_crc_error;
1965                         __be64 rx_crc_error;
1966                         __be64 rx_len_error;
1967                         __be64 rx_sym_error;
1968                         __be64 rx_64b;
1969                         __be64 rx_65b_127b;
1970                         __be64 rx_128b_255b;
1971                         __be64 rx_256b_511b;
1972                         __be64 rx_512b_1023b;
1973                         __be64 rx_1024b_1518b;
1974                         __be64 rx_1519b_max;
1975                         __be64 rx_pause;
1976                         __be64 rx_ppp0;
1977                         __be64 rx_ppp1;
1978                         __be64 rx_ppp2;
1979                         __be64 rx_ppp3;
1980                         __be64 rx_ppp4;
1981                         __be64 rx_ppp5;
1982                         __be64 rx_ppp6;
1983                         __be64 rx_ppp7;
1984                         __be64 rx_less_64b;
1985                         __be64 rx_bg_drop;
1986                         __be64 rx_bg_trunc;
1987                 } all;
1988         } u;
1989 };
1990
1991 #define FW_PORT_STATS_CMD_NSTATS(x) ((x) << 4)
1992 #define FW_PORT_STATS_CMD_BG_BM(x) ((x) << 0)
1993 #define FW_PORT_STATS_CMD_TX(x) ((x) << 7)
1994 #define FW_PORT_STATS_CMD_IX(x) ((x) << 0)
1995
1996 /* port loopback stats */
1997 #define FW_NUM_LB_STATS 16
1998 enum fw_port_lb_stats_index {
1999         FW_STAT_LB_PORT_BYTES_IX,
2000         FW_STAT_LB_PORT_FRAMES_IX,
2001         FW_STAT_LB_PORT_BCAST_IX,
2002         FW_STAT_LB_PORT_MCAST_IX,
2003         FW_STAT_LB_PORT_UCAST_IX,
2004         FW_STAT_LB_PORT_ERROR_IX,
2005         FW_STAT_LB_PORT_64B_IX,
2006         FW_STAT_LB_PORT_65B_127B_IX,
2007         FW_STAT_LB_PORT_128B_255B_IX,
2008         FW_STAT_LB_PORT_256B_511B_IX,
2009         FW_STAT_LB_PORT_512B_1023B_IX,
2010         FW_STAT_LB_PORT_1024B_1518B_IX,
2011         FW_STAT_LB_PORT_1519B_MAX_IX,
2012         FW_STAT_LB_PORT_DROP_FRAMES_IX
2013 };
2014
2015 struct fw_port_lb_stats_cmd {
2016         __be32 op_to_lbport;
2017         __be32 retval_len16;
2018         union fw_port_lb_stats {
2019                 struct fw_port_lb_stats_ctl {
2020                         u8 nstats_bg_bm;
2021                         u8 ix_pkd;
2022                         __be16 r6;
2023                         __be32 r7;
2024                         __be64 stat0;
2025                         __be64 stat1;
2026                         __be64 stat2;
2027                         __be64 stat3;
2028                         __be64 stat4;
2029                         __be64 stat5;
2030                 } ctl;
2031                 struct fw_port_lb_stats_all {
2032                         __be64 tx_bytes;
2033                         __be64 tx_frames;
2034                         __be64 tx_bcast;
2035                         __be64 tx_mcast;
2036                         __be64 tx_ucast;
2037                         __be64 tx_error;
2038                         __be64 tx_64b;
2039                         __be64 tx_65b_127b;
2040                         __be64 tx_128b_255b;
2041                         __be64 tx_256b_511b;
2042                         __be64 tx_512b_1023b;
2043                         __be64 tx_1024b_1518b;
2044                         __be64 tx_1519b_max;
2045                         __be64 rx_lb_drop;
2046                         __be64 rx_lb_trunc;
2047                 } all;
2048         } u;
2049 };
2050
2051 #define FW_PORT_LB_STATS_CMD_LBPORT(x) ((x) << 0)
2052 #define FW_PORT_LB_STATS_CMD_NSTATS(x) ((x) << 4)
2053 #define FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << 0)
2054 #define FW_PORT_LB_STATS_CMD_IX(x) ((x) << 0)
2055
2056 struct fw_rss_ind_tbl_cmd {
2057         __be32 op_to_viid;
2058 #define FW_RSS_IND_TBL_CMD_VIID(x) ((x) << 0)
2059         __be32 retval_len16;
2060         __be16 niqid;
2061         __be16 startidx;
2062         __be32 r3;
2063         __be32 iq0_to_iq2;
2064 #define FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << 20)
2065 #define FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << 10)
2066 #define FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << 0)
2067         __be32 iq3_to_iq5;
2068         __be32 iq6_to_iq8;
2069         __be32 iq9_to_iq11;
2070         __be32 iq12_to_iq14;
2071         __be32 iq15_to_iq17;
2072         __be32 iq18_to_iq20;
2073         __be32 iq21_to_iq23;
2074         __be32 iq24_to_iq26;
2075         __be32 iq27_to_iq29;
2076         __be32 iq30_iq31;
2077         __be32 r15_lo;
2078 };
2079
2080 struct fw_rss_glb_config_cmd {
2081         __be32 op_to_write;
2082         __be32 retval_len16;
2083         union fw_rss_glb_config {
2084                 struct fw_rss_glb_config_manual {
2085                         __be32 mode_pkd;
2086                         __be32 r3;
2087                         __be64 r4;
2088                         __be64 r5;
2089                 } manual;
2090                 struct fw_rss_glb_config_basicvirtual {
2091                         __be32 mode_pkd;
2092                         __be32 synmapen_to_hashtoeplitz;
2093 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN      (1U << 8)
2094 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 (1U << 7)
2095 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 (1U << 6)
2096 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 (1U << 5)
2097 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 (1U << 4)
2098 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN      (1U << 3)
2099 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN      (1U << 2)
2100 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP     (1U << 1)
2101 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ  (1U << 0)
2102                         __be64 r8;
2103                         __be64 r9;
2104                 } basicvirtual;
2105         } u;
2106 };
2107
2108 #define FW_RSS_GLB_CONFIG_CMD_MODE(x)   ((x) << 28)
2109 #define FW_RSS_GLB_CONFIG_CMD_MODE_GET(x) (((x) >> 28) & 0xf)
2110
2111 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL       0
2112 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
2113
2114 struct fw_rss_vi_config_cmd {
2115         __be32 op_to_viid;
2116 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0)
2117         __be32 retval_len16;
2118         union fw_rss_vi_config {
2119                 struct fw_rss_vi_config_manual {
2120                         __be64 r3;
2121                         __be64 r4;
2122                         __be64 r5;
2123                 } manual;
2124                 struct fw_rss_vi_config_basicvirtual {
2125                         __be32 r6;
2126                         __be32 defaultq_to_udpen;
2127 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x)  ((x) << 16)
2128 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_GET(x) (((x) >> 16) & 0x3ff)
2129 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN (1U << 4)
2130 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN  (1U << 3)
2131 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN (1U << 2)
2132 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN  (1U << 1)
2133 #define FW_RSS_VI_CONFIG_CMD_UDPEN        (1U << 0)
2134                         __be64 r9;
2135                         __be64 r10;
2136                 } basicvirtual;
2137         } u;
2138 };
2139
2140 struct fw_clip_cmd {
2141         __be32 op_to_write;
2142         __be32 alloc_to_len16;
2143         __be64 ip_hi;
2144         __be64 ip_lo;
2145         __be32 r4[2];
2146 };
2147
2148 #define S_FW_CLIP_CMD_ALLOC     31
2149 #define M_FW_CLIP_CMD_ALLOC     0x1
2150 #define V_FW_CLIP_CMD_ALLOC(x)  ((x) << S_FW_CLIP_CMD_ALLOC)
2151 #define G_FW_CLIP_CMD_ALLOC(x)  \
2152         (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC)
2153 #define F_FW_CLIP_CMD_ALLOC     V_FW_CLIP_CMD_ALLOC(1U)
2154
2155 #define S_FW_CLIP_CMD_FREE      30
2156 #define M_FW_CLIP_CMD_FREE      0x1
2157 #define V_FW_CLIP_CMD_FREE(x)   ((x) << S_FW_CLIP_CMD_FREE)
2158 #define G_FW_CLIP_CMD_FREE(x)   \
2159         (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE)
2160 #define F_FW_CLIP_CMD_FREE      V_FW_CLIP_CMD_FREE(1U)
2161
2162 enum fw_error_type {
2163         FW_ERROR_TYPE_EXCEPTION         = 0x0,
2164         FW_ERROR_TYPE_HWMODULE          = 0x1,
2165         FW_ERROR_TYPE_WR                = 0x2,
2166         FW_ERROR_TYPE_ACL               = 0x3,
2167 };
2168
2169 struct fw_error_cmd {
2170         __be32 op_to_type;
2171         __be32 len16_pkd;
2172         union fw_error {
2173                 struct fw_error_exception {
2174                         __be32 info[6];
2175                 } exception;
2176                 struct fw_error_hwmodule {
2177                         __be32 regaddr;
2178                         __be32 regval;
2179                 } hwmodule;
2180                 struct fw_error_wr {
2181                         __be16 cidx;
2182                         __be16 pfn_vfn;
2183                         __be32 eqid;
2184                         u8 wrhdr[16];
2185                 } wr;
2186                 struct fw_error_acl {
2187                         __be16 cidx;
2188                         __be16 pfn_vfn;
2189                         __be32 eqid;
2190                         __be16 mv_pkd;
2191                         u8 val[6];
2192                         __be64 r4;
2193                 } acl;
2194         } u;
2195 };
2196
2197 struct fw_debug_cmd {
2198         __be32 op_type;
2199 #define FW_DEBUG_CMD_TYPE_GET(x) ((x) & 0xff)
2200         __be32 len16_pkd;
2201         union fw_debug {
2202                 struct fw_debug_assert {
2203                         __be32 fcid;
2204                         __be32 line;
2205                         __be32 x;
2206                         __be32 y;
2207                         u8 filename_0_7[8];
2208                         u8 filename_8_15[8];
2209                         __be64 r3;
2210                 } assert;
2211                 struct fw_debug_prt {
2212                         __be16 dprtstridx;
2213                         __be16 r3[3];
2214                         __be32 dprtstrparam0;
2215                         __be32 dprtstrparam1;
2216                         __be32 dprtstrparam2;
2217                         __be32 dprtstrparam3;
2218                 } prt;
2219         } u;
2220 };
2221
2222 #define FW_PCIE_FW_ERR           (1U << 31)
2223 #define FW_PCIE_FW_INIT          (1U << 30)
2224 #define FW_PCIE_FW_HALT          (1U << 29)
2225 #define FW_PCIE_FW_MASTER_VLD    (1U << 15)
2226 #define FW_PCIE_FW_MASTER_MASK   0x7
2227 #define FW_PCIE_FW_MASTER_SHIFT  12
2228 #define FW_PCIE_FW_MASTER(x)     ((x) << FW_PCIE_FW_MASTER_SHIFT)
2229 #define FW_PCIE_FW_MASTER_GET(x) (((x) >> FW_PCIE_FW_MASTER_SHIFT) & \
2230                                  FW_PCIE_FW_MASTER_MASK)
2231
2232 struct fw_hdr {
2233         u8 ver;
2234         u8 chip;                        /* terminator chip type */
2235         __be16  len512;                 /* bin length in units of 512-bytes */
2236         __be32  fw_ver;                 /* firmware version */
2237         __be32  tp_microcode_ver;
2238         u8 intfver_nic;
2239         u8 intfver_vnic;
2240         u8 intfver_ofld;
2241         u8 intfver_ri;
2242         u8 intfver_iscsipdu;
2243         u8 intfver_iscsi;
2244         u8 intfver_fcoepdu;
2245         u8 intfver_fcoe;
2246         __u32   reserved2;
2247         __u32   reserved3;
2248         __u32   reserved4;
2249         __be32  flags;
2250         __be32  reserved6[23];
2251 };
2252
2253 enum fw_hdr_chip {
2254         FW_HDR_CHIP_T4,
2255         FW_HDR_CHIP_T5
2256 };
2257
2258 #define FW_HDR_FW_VER_MAJOR_GET(x) (((x) >> 24) & 0xff)
2259 #define FW_HDR_FW_VER_MINOR_GET(x) (((x) >> 16) & 0xff)
2260 #define FW_HDR_FW_VER_MICRO_GET(x) (((x) >> 8) & 0xff)
2261 #define FW_HDR_FW_VER_BUILD_GET(x) (((x) >> 0) & 0xff)
2262
2263 enum fw_hdr_intfver {
2264         FW_HDR_INTFVER_NIC      = 0x00,
2265         FW_HDR_INTFVER_VNIC     = 0x00,
2266         FW_HDR_INTFVER_OFLD     = 0x00,
2267         FW_HDR_INTFVER_RI       = 0x00,
2268         FW_HDR_INTFVER_ISCSIPDU = 0x00,
2269         FW_HDR_INTFVER_ISCSI    = 0x00,
2270         FW_HDR_INTFVER_FCOEPDU  = 0x00,
2271         FW_HDR_INTFVER_FCOE     = 0x00,
2272 };
2273
2274 enum fw_hdr_flags {
2275         FW_HDR_FLAGS_RESET_HALT = 0x00000001,
2276 };
2277
2278 #endif /* _T4FW_INTERFACE_H_ */