drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2009-2014 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #ifndef _T4FW_INTERFACE_H_
  36 #define _T4FW_INTERFACE_H_
  37
  38 enum fw_retval {
  39         FW_SUCCESS              = 0,    /* completed sucessfully */
  40         FW_EPERM                = 1,    /* operation not permitted */
  41         FW_ENOENT               = 2,    /* no such file or directory */
  42         FW_EIO                  = 5,    /* input/output error; hw bad */
  43         FW_ENOEXEC              = 8,    /* exec format error; inv microcode */
  44         FW_EAGAIN               = 11,   /* try again */
  45         FW_ENOMEM               = 12,   /* out of memory */
  46         FW_EFAULT               = 14,   /* bad address; fw bad */
  47         FW_EBUSY                = 16,   /* resource busy */
  48         FW_EEXIST               = 17,   /* file exists */
  49         FW_ENODEV               = 19,   /* no such device */
  50         FW_EINVAL               = 22,   /* invalid argument */
  51         FW_ENOSPC               = 28,   /* no space left on device */
  52         FW_ENOSYS               = 38,   /* functionality not implemented */
  53         FW_ENODATA              = 61,   /* no data available */
  54         FW_EPROTO               = 71,   /* protocol error */
  55         FW_EADDRINUSE           = 98,   /* address already in use */
  56         FW_EADDRNOTAVAIL        = 99,   /* cannot assigned requested address */
  57         FW_ENETDOWN             = 100,  /* network is down */
  58         FW_ENETUNREACH          = 101,  /* network is unreachable */
  59         FW_ENOBUFS              = 105,  /* no buffer space available */
  60         FW_ETIMEDOUT            = 110,  /* timeout */
  61         FW_EINPROGRESS          = 115,  /* fw internal */
  62         FW_SCSI_ABORT_REQUESTED = 128,  /* */
  63         FW_SCSI_ABORT_TIMEDOUT  = 129,  /* */
  64         FW_SCSI_ABORTED         = 130,  /* */
  65         FW_SCSI_CLOSE_REQUESTED = 131,  /* */
  66         FW_ERR_LINK_DOWN        = 132,  /* */
  67         FW_RDEV_NOT_READY       = 133,  /* */
  68         FW_ERR_RDEV_LOST        = 134,  /* */
  69         FW_ERR_RDEV_LOGO        = 135,  /* */
  70         FW_FCOE_NO_XCHG         = 136,  /* */
  71         FW_SCSI_RSP_ERR         = 137,  /* */
  72         FW_ERR_RDEV_IMPL_LOGO   = 138,  /* */
  73         FW_SCSI_UNDER_FLOW_ERR  = 139,  /* */
  74         FW_SCSI_OVER_FLOW_ERR   = 140,  /* */
  75         FW_SCSI_DDP_ERR         = 141,  /* DDP error*/
  76         FW_SCSI_TASK_ERR        = 142,  /* No SCSI tasks available */
  77 };
  78
  79 #define FW_T4VF_SGE_BASE_ADDR      0x0000
  80 #define FW_T4VF_MPS_BASE_ADDR      0x0100
  81 #define FW_T4VF_PL_BASE_ADDR       0x0200
  82 #define FW_T4VF_MBDATA_BASE_ADDR   0x0240
  83 #define FW_T4VF_CIM_BASE_ADDR      0x0300
  84
  85 enum fw_wr_opcodes {
  86         FW_FILTER_WR                   = 0x02,
  87         FW_ULPTX_WR                    = 0x04,
  88         FW_TP_WR                       = 0x05,
  89         FW_ETH_TX_PKT_WR               = 0x08,
  90         FW_OFLD_CONNECTION_WR          = 0x2f,
  91         FW_FLOWC_WR                    = 0x0a,
  92         FW_OFLD_TX_DATA_WR             = 0x0b,
  93         FW_CMD_WR                      = 0x10,
  94         FW_ETH_TX_PKT_VM_WR            = 0x11,
  95         FW_RI_RES_WR                   = 0x0c,
  96         FW_RI_INIT_WR                  = 0x0d,
  97         FW_RI_RDMA_WRITE_WR            = 0x14,
  98         FW_RI_SEND_WR                  = 0x15,
  99         FW_RI_RDMA_READ_WR             = 0x16,
 100         FW_RI_RECV_WR                  = 0x17,
 101         FW_RI_BIND_MW_WR               = 0x18,
 102         FW_RI_FR_NSMR_WR               = 0x19,
 103         FW_RI_INV_LSTAG_WR             = 0x1a,
 104         FW_LASTC2E_WR                  = 0x40
 105 };
 106
 107 struct fw_wr_hdr {
 108         __be32 hi;
 109         __be32 lo;
 110 };
 111
 112 /* work request opcode (hi) */
 113 #define FW_WR_OP_S      24
 114 #define FW_WR_OP_M      0xff
 115 #define FW_WR_OP_V(x)   ((x) << FW_WR_OP_S)
 116 #define FW_WR_OP_G(x)   (((x) >> FW_WR_OP_S) & FW_WR_OP_M)
 117
 118 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */
 119 #define FW_WR_ATOMIC_S          23
 120 #define FW_WR_ATOMIC_V(x)       ((x) << FW_WR_ATOMIC_S)
 121
 122 /* flush flag (hi) - firmware flushes flushable work request buffered
 123  * in the flow context.
 124  */
 125 #define FW_WR_FLUSH_S     22
 126 #define FW_WR_FLUSH_V(x)  ((x) << FW_WR_FLUSH_S)
 127
 128 /* completion flag (hi) - firmware generates a cpl_fw6_ack */
 129 #define FW_WR_COMPL_S     21
 130 #define FW_WR_COMPL_V(x)  ((x) << FW_WR_COMPL_S)
 131 #define FW_WR_COMPL_F     FW_WR_COMPL_V(1U)
 132
 133 /* work request immediate data length (hi) */
 134 #define FW_WR_IMMDLEN_S 0
 135 #define FW_WR_IMMDLEN_M 0xff
 136 #define FW_WR_IMMDLEN_V(x)      ((x) << FW_WR_IMMDLEN_S)
 137
 138 /* egress queue status update to associated ingress queue entry (lo) */
 139 #define FW_WR_EQUIQ_S           31
 140 #define FW_WR_EQUIQ_V(x)        ((x) << FW_WR_EQUIQ_S)
 141 #define FW_WR_EQUIQ_F           FW_WR_EQUIQ_V(1U)
 142
 143 /* egress queue status update to egress queue status entry (lo) */
 144 #define FW_WR_EQUEQ_S           30
 145 #define FW_WR_EQUEQ_V(x)        ((x) << FW_WR_EQUEQ_S)
 146 #define FW_WR_EQUEQ_F           FW_WR_EQUEQ_V(1U)
 147
 148 /* flow context identifier (lo) */
 149 #define FW_WR_FLOWID_S          8
 150 #define FW_WR_FLOWID_V(x)       ((x) << FW_WR_FLOWID_S)
 151
 152 /* length in units of 16-bytes (lo) */
 153 #define FW_WR_LEN16_S           0
 154 #define FW_WR_LEN16_V(x)        ((x) << FW_WR_LEN16_S)
 155
 156 #define HW_TPL_FR_MT_PR_IV_P_FC         0X32B
 157 #define HW_TPL_FR_MT_PR_OV_P_FC         0X327
 158
 159 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
 160 enum fw_filter_wr_cookie {
 161         FW_FILTER_WR_SUCCESS,
 162         FW_FILTER_WR_FLT_ADDED,
 163         FW_FILTER_WR_FLT_DELETED,
 164         FW_FILTER_WR_SMT_TBL_FULL,
 165         FW_FILTER_WR_EINVAL,
 166 };
 167
 168 struct fw_filter_wr {
 169         __be32 op_pkd;
 170         __be32 len16_pkd;
 171         __be64 r3;
 172         __be32 tid_to_iq;
 173         __be32 del_filter_to_l2tix;
 174         __be16 ethtype;
 175         __be16 ethtypem;
 176         __u8   frag_to_ovlan_vldm;
 177         __u8   smac_sel;
 178         __be16 rx_chan_rx_rpl_iq;
 179         __be32 maci_to_matchtypem;
 180         __u8   ptcl;
 181         __u8   ptclm;
 182         __u8   ttyp;
 183         __u8   ttypm;
 184         __be16 ivlan;
 185         __be16 ivlanm;
 186         __be16 ovlan;
 187         __be16 ovlanm;
 188         __u8   lip[16];
 189         __u8   lipm[16];
 190         __u8   fip[16];
 191         __u8   fipm[16];
 192         __be16 lp;
 193         __be16 lpm;
 194         __be16 fp;
 195         __be16 fpm;
 196         __be16 r7;
 197         __u8   sma[6];
 198 };
 199
 200 #define FW_FILTER_WR_TID_S      12
 201 #define FW_FILTER_WR_TID_M      0xfffff
 202 #define FW_FILTER_WR_TID_V(x)   ((x) << FW_FILTER_WR_TID_S)
 203 #define FW_FILTER_WR_TID_G(x)   \
 204         (((x) >> FW_FILTER_WR_TID_S) & FW_FILTER_WR_TID_M)
 205
 206 #define FW_FILTER_WR_RQTYPE_S           11
 207 #define FW_FILTER_WR_RQTYPE_M           0x1
 208 #define FW_FILTER_WR_RQTYPE_V(x)        ((x) << FW_FILTER_WR_RQTYPE_S)
 209 #define FW_FILTER_WR_RQTYPE_G(x)        \
 210         (((x) >> FW_FILTER_WR_RQTYPE_S) & FW_FILTER_WR_RQTYPE_M)
 211 #define FW_FILTER_WR_RQTYPE_F   FW_FILTER_WR_RQTYPE_V(1U)
 212
 213 #define FW_FILTER_WR_NOREPLY_S          10
 214 #define FW_FILTER_WR_NOREPLY_M          0x1
 215 #define FW_FILTER_WR_NOREPLY_V(x)       ((x) << FW_FILTER_WR_NOREPLY_S)
 216 #define FW_FILTER_WR_NOREPLY_G(x)       \
 217         (((x) >> FW_FILTER_WR_NOREPLY_S) & FW_FILTER_WR_NOREPLY_M)
 218 #define FW_FILTER_WR_NOREPLY_F  FW_FILTER_WR_NOREPLY_V(1U)
 219
 220 #define FW_FILTER_WR_IQ_S       0
 221 #define FW_FILTER_WR_IQ_M       0x3ff
 222 #define FW_FILTER_WR_IQ_V(x)    ((x) << FW_FILTER_WR_IQ_S)
 223 #define FW_FILTER_WR_IQ_G(x)    \
 224         (((x) >> FW_FILTER_WR_IQ_S) & FW_FILTER_WR_IQ_M)
 225
 226 #define FW_FILTER_WR_DEL_FILTER_S       31
 227 #define FW_FILTER_WR_DEL_FILTER_M       0x1
 228 #define FW_FILTER_WR_DEL_FILTER_V(x)    ((x) << FW_FILTER_WR_DEL_FILTER_S)
 229 #define FW_FILTER_WR_DEL_FILTER_G(x)    \
 230         (((x) >> FW_FILTER_WR_DEL_FILTER_S) & FW_FILTER_WR_DEL_FILTER_M)
 231 #define FW_FILTER_WR_DEL_FILTER_F       FW_FILTER_WR_DEL_FILTER_V(1U)
 232
 233 #define FW_FILTER_WR_RPTTID_S           25
 234 #define FW_FILTER_WR_RPTTID_M           0x1
 235 #define FW_FILTER_WR_RPTTID_V(x)        ((x) << FW_FILTER_WR_RPTTID_S)
 236 #define FW_FILTER_WR_RPTTID_G(x)        \
 237         (((x) >> FW_FILTER_WR_RPTTID_S) & FW_FILTER_WR_RPTTID_M)
 238 #define FW_FILTER_WR_RPTTID_F   FW_FILTER_WR_RPTTID_V(1U)
 239
 240 #define FW_FILTER_WR_DROP_S     24
 241 #define FW_FILTER_WR_DROP_M     0x1
 242 #define FW_FILTER_WR_DROP_V(x)  ((x) << FW_FILTER_WR_DROP_S)
 243 #define FW_FILTER_WR_DROP_G(x)  \
 244         (((x) >> FW_FILTER_WR_DROP_S) & FW_FILTER_WR_DROP_M)
 245 #define FW_FILTER_WR_DROP_F     FW_FILTER_WR_DROP_V(1U)
 246
 247 #define FW_FILTER_WR_DIRSTEER_S         23
 248 #define FW_FILTER_WR_DIRSTEER_M         0x1
 249 #define FW_FILTER_WR_DIRSTEER_V(x)      ((x) << FW_FILTER_WR_DIRSTEER_S)
 250 #define FW_FILTER_WR_DIRSTEER_G(x)      \
 251         (((x) >> FW_FILTER_WR_DIRSTEER_S) & FW_FILTER_WR_DIRSTEER_M)
 252 #define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1U)
 253
 254 #define FW_FILTER_WR_MASKHASH_S         22
 255 #define FW_FILTER_WR_MASKHASH_M         0x1
 256 #define FW_FILTER_WR_MASKHASH_V(x)      ((x) << FW_FILTER_WR_MASKHASH_S)
 257 #define FW_FILTER_WR_MASKHASH_G(x)      \
 258         (((x) >> FW_FILTER_WR_MASKHASH_S) & FW_FILTER_WR_MASKHASH_M)
 259 #define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1U)
 260
 261 #define FW_FILTER_WR_DIRSTEERHASH_S     21
 262 #define FW_FILTER_WR_DIRSTEERHASH_M     0x1
 263 #define FW_FILTER_WR_DIRSTEERHASH_V(x)  ((x) << FW_FILTER_WR_DIRSTEERHASH_S)
 264 #define FW_FILTER_WR_DIRSTEERHASH_G(x)  \
 265         (((x) >> FW_FILTER_WR_DIRSTEERHASH_S) & FW_FILTER_WR_DIRSTEERHASH_M)
 266 #define FW_FILTER_WR_DIRSTEERHASH_F     FW_FILTER_WR_DIRSTEERHASH_V(1U)
 267
 268 #define FW_FILTER_WR_LPBK_S     20
 269 #define FW_FILTER_WR_LPBK_M     0x1
 270 #define FW_FILTER_WR_LPBK_V(x)  ((x) << FW_FILTER_WR_LPBK_S)
 271 #define FW_FILTER_WR_LPBK_G(x)  \
 272         (((x) >> FW_FILTER_WR_LPBK_S) & FW_FILTER_WR_LPBK_M)
 273 #define FW_FILTER_WR_LPBK_F     FW_FILTER_WR_LPBK_V(1U)
 274
 275 #define FW_FILTER_WR_DMAC_S     19
 276 #define FW_FILTER_WR_DMAC_M     0x1
 277 #define FW_FILTER_WR_DMAC_V(x)  ((x) << FW_FILTER_WR_DMAC_S)
 278 #define FW_FILTER_WR_DMAC_G(x)  \
 279         (((x) >> FW_FILTER_WR_DMAC_S) & FW_FILTER_WR_DMAC_M)
 280 #define FW_FILTER_WR_DMAC_F     FW_FILTER_WR_DMAC_V(1U)
 281
 282 #define FW_FILTER_WR_SMAC_S     18
 283 #define FW_FILTER_WR_SMAC_M     0x1
 284 #define FW_FILTER_WR_SMAC_V(x)  ((x) << FW_FILTER_WR_SMAC_S)
 285 #define FW_FILTER_WR_SMAC_G(x)  \
 286         (((x) >> FW_FILTER_WR_SMAC_S) & FW_FILTER_WR_SMAC_M)
 287 #define FW_FILTER_WR_SMAC_F     FW_FILTER_WR_SMAC_V(1U)
 288
 289 #define FW_FILTER_WR_INSVLAN_S          17
 290 #define FW_FILTER_WR_INSVLAN_M          0x1
 291 #define FW_FILTER_WR_INSVLAN_V(x)       ((x) << FW_FILTER_WR_INSVLAN_S)
 292 #define FW_FILTER_WR_INSVLAN_G(x)       \
 293         (((x) >> FW_FILTER_WR_INSVLAN_S) & FW_FILTER_WR_INSVLAN_M)
 294 #define FW_FILTER_WR_INSVLAN_F  FW_FILTER_WR_INSVLAN_V(1U)
 295
 296 #define FW_FILTER_WR_RMVLAN_S           16
 297 #define FW_FILTER_WR_RMVLAN_M           0x1
 298 #define FW_FILTER_WR_RMVLAN_V(x)        ((x) << FW_FILTER_WR_RMVLAN_S)
 299 #define FW_FILTER_WR_RMVLAN_G(x)        \
 300         (((x) >> FW_FILTER_WR_RMVLAN_S) & FW_FILTER_WR_RMVLAN_M)
 301 #define FW_FILTER_WR_RMVLAN_F   FW_FILTER_WR_RMVLAN_V(1U)
 302
 303 #define FW_FILTER_WR_HITCNTS_S          15
 304 #define FW_FILTER_WR_HITCNTS_M          0x1
 305 #define FW_FILTER_WR_HITCNTS_V(x)       ((x) << FW_FILTER_WR_HITCNTS_S)
 306 #define FW_FILTER_WR_HITCNTS_G(x)       \
 307         (((x) >> FW_FILTER_WR_HITCNTS_S) & FW_FILTER_WR_HITCNTS_M)
 308 #define FW_FILTER_WR_HITCNTS_F  FW_FILTER_WR_HITCNTS_V(1U)
 309
 310 #define FW_FILTER_WR_TXCHAN_S           13
 311 #define FW_FILTER_WR_TXCHAN_M           0x3
 312 #define FW_FILTER_WR_TXCHAN_V(x)        ((x) << FW_FILTER_WR_TXCHAN_S)
 313 #define FW_FILTER_WR_TXCHAN_G(x)        \
 314         (((x) >> FW_FILTER_WR_TXCHAN_S) & FW_FILTER_WR_TXCHAN_M)
 315
 316 #define FW_FILTER_WR_PRIO_S     12
 317 #define FW_FILTER_WR_PRIO_M     0x1
 318 #define FW_FILTER_WR_PRIO_V(x)  ((x) << FW_FILTER_WR_PRIO_S)
 319 #define FW_FILTER_WR_PRIO_G(x)  \
 320         (((x) >> FW_FILTER_WR_PRIO_S) & FW_FILTER_WR_PRIO_M)
 321 #define FW_FILTER_WR_PRIO_F     FW_FILTER_WR_PRIO_V(1U)
 322
 323 #define FW_FILTER_WR_L2TIX_S    0
 324 #define FW_FILTER_WR_L2TIX_M    0xfff
 325 #define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S)
 326 #define FW_FILTER_WR_L2TIX_G(x) \
 327         (((x) >> FW_FILTER_WR_L2TIX_S) & FW_FILTER_WR_L2TIX_M)
 328
 329 #define FW_FILTER_WR_FRAG_S     7
 330 #define FW_FILTER_WR_FRAG_M     0x1
 331 #define FW_FILTER_WR_FRAG_V(x)  ((x) << FW_FILTER_WR_FRAG_S)
 332 #define FW_FILTER_WR_FRAG_G(x)  \
 333         (((x) >> FW_FILTER_WR_FRAG_S) & FW_FILTER_WR_FRAG_M)
 334 #define FW_FILTER_WR_FRAG_F     FW_FILTER_WR_FRAG_V(1U)
 335
 336 #define FW_FILTER_WR_FRAGM_S    6
 337 #define FW_FILTER_WR_FRAGM_M    0x1
 338 #define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S)
 339 #define FW_FILTER_WR_FRAGM_G(x) \
 340         (((x) >> FW_FILTER_WR_FRAGM_S) & FW_FILTER_WR_FRAGM_M)
 341 #define FW_FILTER_WR_FRAGM_F    FW_FILTER_WR_FRAGM_V(1U)
 342
 343 #define FW_FILTER_WR_IVLAN_VLD_S        5
 344 #define FW_FILTER_WR_IVLAN_VLD_M        0x1
 345 #define FW_FILTER_WR_IVLAN_VLD_V(x)     ((x) << FW_FILTER_WR_IVLAN_VLD_S)
 346 #define FW_FILTER_WR_IVLAN_VLD_G(x)     \
 347         (((x) >> FW_FILTER_WR_IVLAN_VLD_S) & FW_FILTER_WR_IVLAN_VLD_M)
 348 #define FW_FILTER_WR_IVLAN_VLD_F        FW_FILTER_WR_IVLAN_VLD_V(1U)
 349
 350 #define FW_FILTER_WR_OVLAN_VLD_S        4
 351 #define FW_FILTER_WR_OVLAN_VLD_M        0x1
 352 #define FW_FILTER_WR_OVLAN_VLD_V(x)     ((x) << FW_FILTER_WR_OVLAN_VLD_S)
 353 #define FW_FILTER_WR_OVLAN_VLD_G(x)     \
 354         (((x) >> FW_FILTER_WR_OVLAN_VLD_S) & FW_FILTER_WR_OVLAN_VLD_M)
 355 #define FW_FILTER_WR_OVLAN_VLD_F        FW_FILTER_WR_OVLAN_VLD_V(1U)
 356
 357 #define FW_FILTER_WR_IVLAN_VLDM_S       3
 358 #define FW_FILTER_WR_IVLAN_VLDM_M       0x1
 359 #define FW_FILTER_WR_IVLAN_VLDM_V(x)    ((x) << FW_FILTER_WR_IVLAN_VLDM_S)
 360 #define FW_FILTER_WR_IVLAN_VLDM_G(x)    \
 361         (((x) >> FW_FILTER_WR_IVLAN_VLDM_S) & FW_FILTER_WR_IVLAN_VLDM_M)
 362 #define FW_FILTER_WR_IVLAN_VLDM_F       FW_FILTER_WR_IVLAN_VLDM_V(1U)
 363
 364 #define FW_FILTER_WR_OVLAN_VLDM_S       2
 365 #define FW_FILTER_WR_OVLAN_VLDM_M       0x1
 366 #define FW_FILTER_WR_OVLAN_VLDM_V(x)    ((x) << FW_FILTER_WR_OVLAN_VLDM_S)
 367 #define FW_FILTER_WR_OVLAN_VLDM_G(x)    \
 368         (((x) >> FW_FILTER_WR_OVLAN_VLDM_S) & FW_FILTER_WR_OVLAN_VLDM_M)
 369 #define FW_FILTER_WR_OVLAN_VLDM_F       FW_FILTER_WR_OVLAN_VLDM_V(1U)
 370
 371 #define FW_FILTER_WR_RX_CHAN_S          15
 372 #define FW_FILTER_WR_RX_CHAN_M          0x1
 373 #define FW_FILTER_WR_RX_CHAN_V(x)       ((x) << FW_FILTER_WR_RX_CHAN_S)
 374 #define FW_FILTER_WR_RX_CHAN_G(x)       \
 375         (((x) >> FW_FILTER_WR_RX_CHAN_S) & FW_FILTER_WR_RX_CHAN_M)
 376 #define FW_FILTER_WR_RX_CHAN_F  FW_FILTER_WR_RX_CHAN_V(1U)
 377
 378 #define FW_FILTER_WR_RX_RPL_IQ_S        0
 379 #define FW_FILTER_WR_RX_RPL_IQ_M        0x3ff
 380 #define FW_FILTER_WR_RX_RPL_IQ_V(x)     ((x) << FW_FILTER_WR_RX_RPL_IQ_S)
 381 #define FW_FILTER_WR_RX_RPL_IQ_G(x)     \
 382         (((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M)
 383
 384 #define FW_FILTER_WR_MACI_S     23
 385 #define FW_FILTER_WR_MACI_M     0x1ff
 386 #define FW_FILTER_WR_MACI_V(x)  ((x) << FW_FILTER_WR_MACI_S)
 387 #define FW_FILTER_WR_MACI_G(x)  \
 388         (((x) >> FW_FILTER_WR_MACI_S) & FW_FILTER_WR_MACI_M)
 389
 390 #define FW_FILTER_WR_MACIM_S    14
 391 #define FW_FILTER_WR_MACIM_M    0x1ff
 392 #define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S)
 393 #define FW_FILTER_WR_MACIM_G(x) \
 394         (((x) >> FW_FILTER_WR_MACIM_S) & FW_FILTER_WR_MACIM_M)
 395
 396 #define FW_FILTER_WR_FCOE_S     13
 397 #define FW_FILTER_WR_FCOE_M     0x1
 398 #define FW_FILTER_WR_FCOE_V(x)  ((x) << FW_FILTER_WR_FCOE_S)
 399 #define FW_FILTER_WR_FCOE_G(x)  \
 400         (((x) >> FW_FILTER_WR_FCOE_S) & FW_FILTER_WR_FCOE_M)
 401 #define FW_FILTER_WR_FCOE_F     FW_FILTER_WR_FCOE_V(1U)
 402
 403 #define FW_FILTER_WR_FCOEM_S    12
 404 #define FW_FILTER_WR_FCOEM_M    0x1
 405 #define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S)
 406 #define FW_FILTER_WR_FCOEM_G(x) \
 407         (((x) >> FW_FILTER_WR_FCOEM_S) & FW_FILTER_WR_FCOEM_M)
 408 #define FW_FILTER_WR_FCOEM_F    FW_FILTER_WR_FCOEM_V(1U)
 409
 410 #define FW_FILTER_WR_PORT_S     9
 411 #define FW_FILTER_WR_PORT_M     0x7
 412 #define FW_FILTER_WR_PORT_V(x)  ((x) << FW_FILTER_WR_PORT_S)
 413 #define FW_FILTER_WR_PORT_G(x)  \
 414         (((x) >> FW_FILTER_WR_PORT_S) & FW_FILTER_WR_PORT_M)
 415
 416 #define FW_FILTER_WR_PORTM_S    6
 417 #define FW_FILTER_WR_PORTM_M    0x7
 418 #define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S)
 419 #define FW_FILTER_WR_PORTM_G(x) \
 420         (((x) >> FW_FILTER_WR_PORTM_S) & FW_FILTER_WR_PORTM_M)
 421
 422 #define FW_FILTER_WR_MATCHTYPE_S        3
 423 #define FW_FILTER_WR_MATCHTYPE_M        0x7
 424 #define FW_FILTER_WR_MATCHTYPE_V(x)     ((x) << FW_FILTER_WR_MATCHTYPE_S)
 425 #define FW_FILTER_WR_MATCHTYPE_G(x)     \
 426         (((x) >> FW_FILTER_WR_MATCHTYPE_S) & FW_FILTER_WR_MATCHTYPE_M)
 427
 428 #define FW_FILTER_WR_MATCHTYPEM_S       0
 429 #define FW_FILTER_WR_MATCHTYPEM_M       0x7
 430 #define FW_FILTER_WR_MATCHTYPEM_V(x)    ((x) << FW_FILTER_WR_MATCHTYPEM_S)
 431 #define FW_FILTER_WR_MATCHTYPEM_G(x)    \
 432         (((x) >> FW_FILTER_WR_MATCHTYPEM_S) & FW_FILTER_WR_MATCHTYPEM_M)
 433
 434 struct fw_ulptx_wr {
 435         __be32 op_to_compl;
 436         __be32 flowid_len16;
 437         u64 cookie;
 438 };
 439
 440 struct fw_tp_wr {
 441         __be32 op_to_immdlen;
 442         __be32 flowid_len16;
 443         u64 cookie;
 444 };
 445
 446 struct fw_eth_tx_pkt_wr {
 447         __be32 op_immdlen;
 448         __be32 equiq_to_len16;
 449         __be64 r3;
 450 };
 451
 452 struct fw_ofld_connection_wr {
 453         __be32 op_compl;
 454         __be32 len16_pkd;
 455         __u64  cookie;
 456         __be64 r2;
 457         __be64 r3;
 458         struct fw_ofld_connection_le {
 459                 __be32 version_cpl;
 460                 __be32 filter;
 461                 __be32 r1;
 462                 __be16 lport;
 463                 __be16 pport;
 464                 union fw_ofld_connection_leip {
 465                         struct fw_ofld_connection_le_ipv4 {
 466                                 __be32 pip;
 467                                 __be32 lip;
 468                                 __be64 r0;
 469                                 __be64 r1;
 470                                 __be64 r2;
 471                         } ipv4;
 472                         struct fw_ofld_connection_le_ipv6 {
 473                                 __be64 pip_hi;
 474                                 __be64 pip_lo;
 475                                 __be64 lip_hi;
 476                                 __be64 lip_lo;
 477                         } ipv6;
 478                 } u;
 479         } le;
 480         struct fw_ofld_connection_tcb {
 481                 __be32 t_state_to_astid;
 482                 __be16 cplrxdataack_cplpassacceptrpl;
 483                 __be16 rcv_adv;
 484                 __be32 rcv_nxt;
 485                 __be32 tx_max;
 486                 __be64 opt0;
 487                 __be32 opt2;
 488                 __be32 r1;
 489                 __be64 r2;
 490                 __be64 r3;
 491         } tcb;
 492 };
 493
 494 #define FW_OFLD_CONNECTION_WR_VERSION_S                31
 495 #define FW_OFLD_CONNECTION_WR_VERSION_M                0x1
 496 #define FW_OFLD_CONNECTION_WR_VERSION_V(x)     \
 497         ((x) << FW_OFLD_CONNECTION_WR_VERSION_S)
 498 #define FW_OFLD_CONNECTION_WR_VERSION_G(x)     \
 499         (((x) >> FW_OFLD_CONNECTION_WR_VERSION_S) & \
 500         FW_OFLD_CONNECTION_WR_VERSION_M)
 501 #define FW_OFLD_CONNECTION_WR_VERSION_F        \
 502         FW_OFLD_CONNECTION_WR_VERSION_V(1U)
 503
 504 #define FW_OFLD_CONNECTION_WR_CPL_S    30
 505 #define FW_OFLD_CONNECTION_WR_CPL_M    0x1
 506 #define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S)
 507 #define FW_OFLD_CONNECTION_WR_CPL_G(x) \
 508         (((x) >> FW_OFLD_CONNECTION_WR_CPL_S) & FW_OFLD_CONNECTION_WR_CPL_M)
 509 #define FW_OFLD_CONNECTION_WR_CPL_F    FW_OFLD_CONNECTION_WR_CPL_V(1U)
 510
 511 #define FW_OFLD_CONNECTION_WR_T_STATE_S                28
 512 #define FW_OFLD_CONNECTION_WR_T_STATE_M                0xf
 513 #define FW_OFLD_CONNECTION_WR_T_STATE_V(x)     \
 514         ((x) << FW_OFLD_CONNECTION_WR_T_STATE_S)
 515 #define FW_OFLD_CONNECTION_WR_T_STATE_G(x)     \
 516         (((x) >> FW_OFLD_CONNECTION_WR_T_STATE_S) & \
 517         FW_OFLD_CONNECTION_WR_T_STATE_M)
 518
 519 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_S      24
 520 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_M      0xf
 521 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x)   \
 522         ((x) << FW_OFLD_CONNECTION_WR_RCV_SCALE_S)
 523 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x)   \
 524         (((x) >> FW_OFLD_CONNECTION_WR_RCV_SCALE_S) & \
 525         FW_OFLD_CONNECTION_WR_RCV_SCALE_M)
 526
 527 #define FW_OFLD_CONNECTION_WR_ASTID_S          0
 528 #define FW_OFLD_CONNECTION_WR_ASTID_M          0xffffff
 529 #define FW_OFLD_CONNECTION_WR_ASTID_V(x)       \
 530         ((x) << FW_OFLD_CONNECTION_WR_ASTID_S)
 531 #define FW_OFLD_CONNECTION_WR_ASTID_G(x)       \
 532         (((x) >> FW_OFLD_CONNECTION_WR_ASTID_S) & FW_OFLD_CONNECTION_WR_ASTID_M)
 533
 534 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S   15
 535 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M   0x1
 536 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x)        \
 537         ((x) << FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S)
 538 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x)        \
 539         (((x) >> FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) & \
 540         FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M)
 541 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F   \
 542         FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(1U)
 543
 544 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S       14
 545 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M       0x1
 546 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x)    \
 547         ((x) << FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S)
 548 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x)    \
 549         (((x) >> FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) & \
 550         FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M)
 551 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F       \
 552         FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(1U)
 553
 554 enum fw_flowc_mnem {
 555         FW_FLOWC_MNEM_PFNVFN,           /* PFN [15:8] VFN [7:0] */
 556         FW_FLOWC_MNEM_CH,
 557         FW_FLOWC_MNEM_PORT,
 558         FW_FLOWC_MNEM_IQID,
 559         FW_FLOWC_MNEM_SNDNXT,
 560         FW_FLOWC_MNEM_RCVNXT,
 561         FW_FLOWC_MNEM_SNDBUF,
 562         FW_FLOWC_MNEM_MSS,
 563         FW_FLOWC_MNEM_TXDATAPLEN_MAX,
 564 };
 565
 566 struct fw_flowc_mnemval {
 567         u8 mnemonic;
 568         u8 r4[3];
 569         __be32 val;
 570 };
 571
 572 struct fw_flowc_wr {
 573         __be32 op_to_nparams;
 574         __be32 flowid_len16;
 575         struct fw_flowc_mnemval mnemval[0];
 576 };
 577
 578 #define FW_FLOWC_WR_NPARAMS_S           0
 579 #define FW_FLOWC_WR_NPARAMS_V(x)        ((x) << FW_FLOWC_WR_NPARAMS_S)
 580
 581 struct fw_ofld_tx_data_wr {
 582         __be32 op_to_immdlen;
 583         __be32 flowid_len16;
 584         __be32 plen;
 585         __be32 tunnel_to_proxy;
 586 };
 587
 588 #define FW_OFLD_TX_DATA_WR_TUNNEL_S     19
 589 #define FW_OFLD_TX_DATA_WR_TUNNEL_V(x)  ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S)
 590
 591 #define FW_OFLD_TX_DATA_WR_SAVE_S       18
 592 #define FW_OFLD_TX_DATA_WR_SAVE_V(x)    ((x) << FW_OFLD_TX_DATA_WR_SAVE_S)
 593
 594 #define FW_OFLD_TX_DATA_WR_FLUSH_S      17
 595 #define FW_OFLD_TX_DATA_WR_FLUSH_V(x)   ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S)
 596 #define FW_OFLD_TX_DATA_WR_FLUSH_F      FW_OFLD_TX_DATA_WR_FLUSH_V(1U)
 597
 598 #define FW_OFLD_TX_DATA_WR_URGENT_S     16
 599 #define FW_OFLD_TX_DATA_WR_URGENT_V(x)  ((x) << FW_OFLD_TX_DATA_WR_URGENT_S)
 600
 601 #define FW_OFLD_TX_DATA_WR_MORE_S       15
 602 #define FW_OFLD_TX_DATA_WR_MORE_V(x)    ((x) << FW_OFLD_TX_DATA_WR_MORE_S)
 603
 604 #define FW_OFLD_TX_DATA_WR_SHOVE_S      14
 605 #define FW_OFLD_TX_DATA_WR_SHOVE_V(x)   ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S)
 606 #define FW_OFLD_TX_DATA_WR_SHOVE_F      FW_OFLD_TX_DATA_WR_SHOVE_V(1U)
 607
 608 #define FW_OFLD_TX_DATA_WR_ULPMODE_S    10
 609 #define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S)
 610
 611 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S         6
 612 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x)      \
 613         ((x) << FW_OFLD_TX_DATA_WR_ULPSUBMODE_S)
 614
 615 struct fw_cmd_wr {
 616         __be32 op_dma;
 617         __be32 len16_pkd;
 618         __be64 cookie_daddr;
 619 };
 620
 621 #define FW_CMD_WR_DMA_S         17
 622 #define FW_CMD_WR_DMA_V(x)      ((x) << FW_CMD_WR_DMA_S)
 623
 624 struct fw_eth_tx_pkt_vm_wr {
 625         __be32 op_immdlen;
 626         __be32 equiq_to_len16;
 627         __be32 r3[2];
 628         u8 ethmacdst[6];
 629         u8 ethmacsrc[6];
 630         __be16 ethtype;
 631         __be16 vlantci;
 632 };
 633
 634 #define FW_CMD_MAX_TIMEOUT 10000
 635
 636 /*
 637  * If a host driver does a HELLO and discovers that there's already a MASTER
 638  * selected, we may have to wait for that MASTER to finish issuing RESET,
 639  * configuration and INITIALIZE commands.  Also, there's a possibility that
 640  * our own HELLO may get lost if it happens right as the MASTER is issuign a
 641  * RESET command, so we need to be willing to make a few retries of our HELLO.
 642  */
 643 #define FW_CMD_HELLO_TIMEOUT    (3 * FW_CMD_MAX_TIMEOUT)
 644 #define FW_CMD_HELLO_RETRIES    3
 645
 646
 647 enum fw_cmd_opcodes {
 648         FW_LDST_CMD                    = 0x01,
 649         FW_RESET_CMD                   = 0x03,
 650         FW_HELLO_CMD                   = 0x04,
 651         FW_BYE_CMD                     = 0x05,
 652         FW_INITIALIZE_CMD              = 0x06,
 653         FW_CAPS_CONFIG_CMD             = 0x07,
 654         FW_PARAMS_CMD                  = 0x08,
 655         FW_PFVF_CMD                    = 0x09,
 656         FW_IQ_CMD                      = 0x10,
 657         FW_EQ_MNGT_CMD                 = 0x11,
 658         FW_EQ_ETH_CMD                  = 0x12,
 659         FW_EQ_CTRL_CMD                 = 0x13,
 660         FW_EQ_OFLD_CMD                 = 0x21,
 661         FW_VI_CMD                      = 0x14,
 662         FW_VI_MAC_CMD                  = 0x15,
 663         FW_VI_RXMODE_CMD               = 0x16,
 664         FW_VI_ENABLE_CMD               = 0x17,
 665         FW_ACL_MAC_CMD                 = 0x18,
 666         FW_ACL_VLAN_CMD                = 0x19,
 667         FW_VI_STATS_CMD                = 0x1a,
 668         FW_PORT_CMD                    = 0x1b,
 669         FW_PORT_STATS_CMD              = 0x1c,
 670         FW_PORT_LB_STATS_CMD           = 0x1d,
 671         FW_PORT_TRACE_CMD              = 0x1e,
 672         FW_PORT_TRACE_MMAP_CMD         = 0x1f,
 673         FW_RSS_IND_TBL_CMD             = 0x20,
 674         FW_RSS_GLB_CONFIG_CMD          = 0x22,
 675         FW_RSS_VI_CONFIG_CMD           = 0x23,
 676         FW_CLIP_CMD                    = 0x28,
 677         FW_LASTC2E_CMD                 = 0x40,
 678         FW_ERROR_CMD                   = 0x80,
 679         FW_DEBUG_CMD                   = 0x81,
 680 };
 681
 682 enum fw_cmd_cap {
 683         FW_CMD_CAP_PF                  = 0x01,
 684         FW_CMD_CAP_DMAQ                = 0x02,
 685         FW_CMD_CAP_PORT                = 0x04,
 686         FW_CMD_CAP_PORTPROMISC         = 0x08,
 687         FW_CMD_CAP_PORTSTATS           = 0x10,
 688         FW_CMD_CAP_VF                  = 0x80,
 689 };
 690
 691 /*
 692  * Generic command header flit0
 693  */
 694 struct fw_cmd_hdr {
 695         __be32 hi;
 696         __be32 lo;
 697 };
 698
 699 #define FW_CMD_OP_S             24
 700 #define FW_CMD_OP_M             0xff
 701 #define FW_CMD_OP_V(x)          ((x) << FW_CMD_OP_S)
 702 #define FW_CMD_OP_G(x)          (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M)
 703
 704 #define FW_CMD_REQUEST_S        23
 705 #define FW_CMD_REQUEST_V(x)     ((x) << FW_CMD_REQUEST_S)
 706 #define FW_CMD_REQUEST_F        FW_CMD_REQUEST_V(1U)
 707
 708 #define FW_CMD_READ_S           22
 709 #define FW_CMD_READ_V(x)        ((x) << FW_CMD_READ_S)
 710 #define FW_CMD_READ_F           FW_CMD_READ_V(1U)
 711
 712 #define FW_CMD_WRITE_S          21
 713 #define FW_CMD_WRITE_V(x)       ((x) << FW_CMD_WRITE_S)
 714 #define FW_CMD_WRITE_F          FW_CMD_WRITE_V(1U)
 715
 716 #define FW_CMD_EXEC_S           20
 717 #define FW_CMD_EXEC_V(x)        ((x) << FW_CMD_EXEC_S)
 718 #define FW_CMD_EXEC_F           FW_CMD_EXEC_V(1U)
 719
 720 #define FW_CMD_RAMASK_S         20
 721 #define FW_CMD_RAMASK_V(x)      ((x) << FW_CMD_RAMASK_S)
 722
 723 #define FW_CMD_RETVAL_S         8
 724 #define FW_CMD_RETVAL_M         0xff
 725 #define FW_CMD_RETVAL_V(x)      ((x) << FW_CMD_RETVAL_S)
 726 #define FW_CMD_RETVAL_G(x)      (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M)
 727
 728 #define FW_CMD_LEN16_S          0
 729 #define FW_CMD_LEN16_V(x)       ((x) << FW_CMD_LEN16_S)
 730
 731 #define FW_LEN16(fw_struct)     FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
 732
 733 enum fw_ldst_addrspc {
 734         FW_LDST_ADDRSPC_FIRMWARE  = 0x0001,
 735         FW_LDST_ADDRSPC_SGE_EGRC  = 0x0008,
 736         FW_LDST_ADDRSPC_SGE_INGC  = 0x0009,
 737         FW_LDST_ADDRSPC_SGE_FLMC  = 0x000a,
 738         FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
 739         FW_LDST_ADDRSPC_TP_PIO    = 0x0010,
 740         FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
 741         FW_LDST_ADDRSPC_TP_MIB    = 0x0012,
 742         FW_LDST_ADDRSPC_MDIO      = 0x0018,
 743         FW_LDST_ADDRSPC_MPS       = 0x0020,
 744         FW_LDST_ADDRSPC_FUNC      = 0x0028,
 745         FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
 746 };
 747
 748 enum fw_ldst_mps_fid {
 749         FW_LDST_MPS_ATRB,
 750         FW_LDST_MPS_RPLC
 751 };
 752
 753 enum fw_ldst_func_access_ctl {
 754         FW_LDST_FUNC_ACC_CTL_VIID,
 755         FW_LDST_FUNC_ACC_CTL_FID
 756 };
 757
 758 enum fw_ldst_func_mod_index {
 759         FW_LDST_FUNC_MPS
 760 };
 761
 762 struct fw_ldst_cmd {
 763         __be32 op_to_addrspace;
 764 #define FW_LDST_CMD_ADDRSPACE_S         0
 765 #define FW_LDST_CMD_ADDRSPACE_V(x)      ((x) << FW_LDST_CMD_ADDRSPACE_S)
 766         __be32 cycles_to_len16;
 767         union fw_ldst {
 768                 struct fw_ldst_addrval {
 769                         __be32 addr;
 770                         __be32 val;
 771                 } addrval;
 772                 struct fw_ldst_idctxt {
 773                         __be32 physid;
 774                         __be32 msg_pkd;
 775                         __be32 ctxt_data7;
 776                         __be32 ctxt_data6;
 777                         __be32 ctxt_data5;
 778                         __be32 ctxt_data4;
 779                         __be32 ctxt_data3;
 780                         __be32 ctxt_data2;
 781                         __be32 ctxt_data1;
 782                         __be32 ctxt_data0;
 783                 } idctxt;
 784                 struct fw_ldst_mdio {
 785                         __be16 paddr_mmd;
 786                         __be16 raddr;
 787                         __be16 vctl;
 788                         __be16 rval;
 789                 } mdio;
 790                 struct fw_ldst_mps {
 791                         __be16 fid_ctl;
 792                         __be16 rplcpf_pkd;
 793                         __be32 rplc127_96;
 794                         __be32 rplc95_64;
 795                         __be32 rplc63_32;
 796                         __be32 rplc31_0;
 797                         __be32 atrb;
 798                         __be16 vlan[16];
 799                 } mps;
 800                 struct fw_ldst_func {
 801                         u8 access_ctl;
 802                         u8 mod_index;
 803                         __be16 ctl_id;
 804                         __be32 offset;
 805                         __be64 data0;
 806                         __be64 data1;
 807                 } func;
 808                 struct fw_ldst_pcie {
 809                         u8 ctrl_to_fn;
 810                         u8 bnum;
 811                         u8 r;
 812                         u8 ext_r;
 813                         u8 select_naccess;
 814                         u8 pcie_fn;
 815                         __be16 nset_pkd;
 816                         __be32 data[12];
 817                 } pcie;
 818         } u;
 819 };
 820
 821 #define FW_LDST_CMD_MSG_S       31
 822 #define FW_LDST_CMD_MSG_V(x)    ((x) << FW_LDST_CMD_MSG_S)
 823
 824 #define FW_LDST_CMD_PADDR_S     8
 825 #define FW_LDST_CMD_PADDR_V(x)  ((x) << FW_LDST_CMD_PADDR_S)
 826
 827 #define FW_LDST_CMD_MMD_S       0
 828 #define FW_LDST_CMD_MMD_V(x)    ((x) << FW_LDST_CMD_MMD_S)
 829
 830 #define FW_LDST_CMD_FID_S       15
 831 #define FW_LDST_CMD_FID_V(x)    ((x) << FW_LDST_CMD_FID_S)
 832
 833 #define FW_LDST_CMD_CTL_S       0
 834 #define FW_LDST_CMD_CTL_V(x)    ((x) << FW_LDST_CMD_CTL_S)
 835
 836 #define FW_LDST_CMD_RPLCPF_S    0
 837 #define FW_LDST_CMD_RPLCPF_V(x) ((x) << FW_LDST_CMD_RPLCPF_S)
 838
 839 #define FW_LDST_CMD_LC_S        4
 840 #define FW_LDST_CMD_LC_V(x)     ((x) << FW_LDST_CMD_LC_S)
 841 #define FW_LDST_CMD_LC_F        FW_LDST_CMD_LC_V(1U)
 842
 843 #define FW_LDST_CMD_FN_S        0
 844 #define FW_LDST_CMD_FN_V(x)     ((x) << FW_LDST_CMD_FN_S)
 845
 846 #define FW_LDST_CMD_NACCESS_S           0
 847 #define FW_LDST_CMD_NACCESS_V(x)        ((x) << FW_LDST_CMD_NACCESS_S)
 848
 849 struct fw_reset_cmd {
 850         __be32 op_to_write;
 851         __be32 retval_len16;
 852         __be32 val;
 853         __be32 halt_pkd;
 854 };
 855
 856 #define FW_RESET_CMD_HALT_S     31
 857 #define FW_RESET_CMD_HALT_M     0x1
 858 #define FW_RESET_CMD_HALT_V(x)  ((x) << FW_RESET_CMD_HALT_S)
 859 #define FW_RESET_CMD_HALT_G(x)  \
 860         (((x) >> FW_RESET_CMD_HALT_S) & FW_RESET_CMD_HALT_M)
 861 #define FW_RESET_CMD_HALT_F     FW_RESET_CMD_HALT_V(1U)
 862
 863 enum fw_hellow_cmd {
 864         fw_hello_cmd_stage_os           = 0x0
 865 };
 866
 867 struct fw_hello_cmd {
 868         __be32 op_to_write;
 869         __be32 retval_len16;
 870         __be32 err_to_clearinit;
 871         __be32 fwrev;
 872 };
 873
 874 #define FW_HELLO_CMD_ERR_S      31
 875 #define FW_HELLO_CMD_ERR_V(x)   ((x) << FW_HELLO_CMD_ERR_S)
 876 #define FW_HELLO_CMD_ERR_F      FW_HELLO_CMD_ERR_V(1U)
 877
 878 #define FW_HELLO_CMD_INIT_S     30
 879 #define FW_HELLO_CMD_INIT_V(x)  ((x) << FW_HELLO_CMD_INIT_S)
 880 #define FW_HELLO_CMD_INIT_F     FW_HELLO_CMD_INIT_V(1U)
 881
 882 #define FW_HELLO_CMD_MASTERDIS_S        29
 883 #define FW_HELLO_CMD_MASTERDIS_V(x)     ((x) << FW_HELLO_CMD_MASTERDIS_S)
 884
 885 #define FW_HELLO_CMD_MASTERFORCE_S      28
 886 #define FW_HELLO_CMD_MASTERFORCE_V(x)   ((x) << FW_HELLO_CMD_MASTERFORCE_S)
 887
 888 #define FW_HELLO_CMD_MBMASTER_S         24
 889 #define FW_HELLO_CMD_MBMASTER_M         0xfU
 890 #define FW_HELLO_CMD_MBMASTER_V(x)      ((x) << FW_HELLO_CMD_MBMASTER_S)
 891 #define FW_HELLO_CMD_MBMASTER_G(x)      \
 892         (((x) >> FW_HELLO_CMD_MBMASTER_S) & FW_HELLO_CMD_MBMASTER_M)
 893
 894 #define FW_HELLO_CMD_MBASYNCNOTINT_S    23
 895 #define FW_HELLO_CMD_MBASYNCNOTINT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOTINT_S)
 896
 897 #define FW_HELLO_CMD_MBASYNCNOT_S       20
 898 #define FW_HELLO_CMD_MBASYNCNOT_V(x)    ((x) << FW_HELLO_CMD_MBASYNCNOT_S)
 899
 900 #define FW_HELLO_CMD_STAGE_S            17
 901 #define FW_HELLO_CMD_STAGE_V(x)         ((x) << FW_HELLO_CMD_STAGE_S)
 902
 903 #define FW_HELLO_CMD_CLEARINIT_S        16
 904 #define FW_HELLO_CMD_CLEARINIT_V(x)     ((x) << FW_HELLO_CMD_CLEARINIT_S)
 905 #define FW_HELLO_CMD_CLEARINIT_F        FW_HELLO_CMD_CLEARINIT_V(1U)
 906
 907 struct fw_bye_cmd {
 908         __be32 op_to_write;
 909         __be32 retval_len16;
 910         __be64 r3;
 911 };
 912
 913 struct fw_initialize_cmd {
 914         __be32 op_to_write;
 915         __be32 retval_len16;
 916         __be64 r3;
 917 };
 918
 919 enum fw_caps_config_hm {
 920         FW_CAPS_CONFIG_HM_PCIE          = 0x00000001,
 921         FW_CAPS_CONFIG_HM_PL            = 0x00000002,
 922         FW_CAPS_CONFIG_HM_SGE           = 0x00000004,
 923         FW_CAPS_CONFIG_HM_CIM           = 0x00000008,
 924         FW_CAPS_CONFIG_HM_ULPTX         = 0x00000010,
 925         FW_CAPS_CONFIG_HM_TP            = 0x00000020,
 926         FW_CAPS_CONFIG_HM_ULPRX         = 0x00000040,
 927         FW_CAPS_CONFIG_HM_PMRX          = 0x00000080,
 928         FW_CAPS_CONFIG_HM_PMTX          = 0x00000100,
 929         FW_CAPS_CONFIG_HM_MC            = 0x00000200,
 930         FW_CAPS_CONFIG_HM_LE            = 0x00000400,
 931         FW_CAPS_CONFIG_HM_MPS           = 0x00000800,
 932         FW_CAPS_CONFIG_HM_XGMAC         = 0x00001000,
 933         FW_CAPS_CONFIG_HM_CPLSWITCH     = 0x00002000,
 934         FW_CAPS_CONFIG_HM_T4DBG         = 0x00004000,
 935         FW_CAPS_CONFIG_HM_MI            = 0x00008000,
 936         FW_CAPS_CONFIG_HM_I2CM          = 0x00010000,
 937         FW_CAPS_CONFIG_HM_NCSI          = 0x00020000,
 938         FW_CAPS_CONFIG_HM_SMB           = 0x00040000,
 939         FW_CAPS_CONFIG_HM_MA            = 0x00080000,
 940         FW_CAPS_CONFIG_HM_EDRAM         = 0x00100000,
 941         FW_CAPS_CONFIG_HM_PMU           = 0x00200000,
 942         FW_CAPS_CONFIG_HM_UART          = 0x00400000,
 943         FW_CAPS_CONFIG_HM_SF            = 0x00800000,
 944 };
 945
 946 enum fw_caps_config_nbm {
 947         FW_CAPS_CONFIG_NBM_IPMI         = 0x00000001,
 948         FW_CAPS_CONFIG_NBM_NCSI         = 0x00000002,
 949 };
 950
 951 enum fw_caps_config_link {
 952         FW_CAPS_CONFIG_LINK_PPP         = 0x00000001,
 953         FW_CAPS_CONFIG_LINK_QFC         = 0x00000002,
 954         FW_CAPS_CONFIG_LINK_DCBX        = 0x00000004,
 955 };
 956
 957 enum fw_caps_config_switch {
 958         FW_CAPS_CONFIG_SWITCH_INGRESS   = 0x00000001,
 959         FW_CAPS_CONFIG_SWITCH_EGRESS    = 0x00000002,
 960 };
 961
 962 enum fw_caps_config_nic {
 963         FW_CAPS_CONFIG_NIC              = 0x00000001,
 964         FW_CAPS_CONFIG_NIC_VM           = 0x00000002,
 965 };
 966
 967 enum fw_caps_config_ofld {
 968         FW_CAPS_CONFIG_OFLD             = 0x00000001,
 969 };
 970
 971 enum fw_caps_config_rdma {
 972         FW_CAPS_CONFIG_RDMA_RDDP        = 0x00000001,
 973         FW_CAPS_CONFIG_RDMA_RDMAC       = 0x00000002,
 974 };
 975
 976 enum fw_caps_config_iscsi {
 977         FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
 978         FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
 979         FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
 980         FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
 981 };
 982
 983 enum fw_caps_config_fcoe {
 984         FW_CAPS_CONFIG_FCOE_INITIATOR   = 0x00000001,
 985         FW_CAPS_CONFIG_FCOE_TARGET      = 0x00000002,
 986         FW_CAPS_CONFIG_FCOE_CTRL_OFLD   = 0x00000004,
 987 };
 988
 989 enum fw_memtype_cf {
 990         FW_MEMTYPE_CF_EDC0              = 0x0,
 991         FW_MEMTYPE_CF_EDC1              = 0x1,
 992         FW_MEMTYPE_CF_EXTMEM            = 0x2,
 993         FW_MEMTYPE_CF_FLASH             = 0x4,
 994         FW_MEMTYPE_CF_INTERNAL          = 0x5,
 995 };
 996
 997 struct fw_caps_config_cmd {
 998         __be32 op_to_write;
 999         __be32 cfvalid_to_len16;
1000         __be32 r2;
1001         __be32 hwmbitmap;
1002         __be16 nbmcaps;
1003         __be16 linkcaps;
1004         __be16 switchcaps;
1005         __be16 r3;
1006         __be16 niccaps;
1007         __be16 ofldcaps;
1008         __be16 rdmacaps;
1009         __be16 r4;
1010         __be16 iscsicaps;
1011         __be16 fcoecaps;
1012         __be32 cfcsum;
1013         __be32 finiver;
1014         __be32 finicsum;
1015 };
1016
1017 #define FW_CAPS_CONFIG_CMD_CFVALID_S    27
1018 #define FW_CAPS_CONFIG_CMD_CFVALID_V(x) ((x) << FW_CAPS_CONFIG_CMD_CFVALID_S)
1019 #define FW_CAPS_CONFIG_CMD_CFVALID_F    FW_CAPS_CONFIG_CMD_CFVALID_V(1U)
1020
1021 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S         24
1022 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(x)      \
1023         ((x) << FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S)
1024
1025 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S      16
1026 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(x)   \
1027         ((x) << FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S)
1028
1029 /*
1030  * params command mnemonics
1031  */
1032 enum fw_params_mnem {
1033         FW_PARAMS_MNEM_DEV              = 1,    /* device params */
1034         FW_PARAMS_MNEM_PFVF             = 2,    /* function params */
1035         FW_PARAMS_MNEM_REG              = 3,    /* limited register access */
1036         FW_PARAMS_MNEM_DMAQ             = 4,    /* dma queue params */
1037         FW_PARAMS_MNEM_LAST
1038 };
1039
1040 /*
1041  * device parameters
1042  */
1043 enum fw_params_param_dev {
1044         FW_PARAMS_PARAM_DEV_CCLK        = 0x00, /* chip core clock in khz */
1045         FW_PARAMS_PARAM_DEV_PORTVEC     = 0x01, /* the port vector */
1046         FW_PARAMS_PARAM_DEV_NTID        = 0x02, /* reads the number of TIDs
1047                                                  * allocated by the device's
1048                                                  * Lookup Engine
1049                                                  */
1050         FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
1051         FW_PARAMS_PARAM_DEV_INTVER_NIC  = 0x04,
1052         FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05,
1053         FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06,
1054         FW_PARAMS_PARAM_DEV_INTVER_RI   = 0x07,
1055         FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08,
1056         FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09,
1057         FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A,
1058         FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
1059         FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
1060         FW_PARAMS_PARAM_DEV_CF = 0x0D,
1061         FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD */
1062         FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER = 0x14, /* max supported adap IRD */
1063         FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
1064 };
1065
1066 /*
1067  * physical and virtual function parameters
1068  */
1069 enum fw_params_param_pfvf {
1070         FW_PARAMS_PARAM_PFVF_RWXCAPS    = 0x00,
1071         FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
1072         FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
1073         FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
1074         FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
1075         FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
1076         FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
1077         FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
1078         FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
1079         FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
1080         FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
1081         FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
1082         FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
1083         FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
1084         FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
1085         FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
1086         FW_PARAMS_PARAM_PFVF_RQ_END     = 0x10,
1087         FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
1088         FW_PARAMS_PARAM_PFVF_PBL_END    = 0x12,
1089         FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
1090         FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
1091         FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
1092         FW_PARAMS_PARAM_PFVF_SQRQ_END   = 0x16,
1093         FW_PARAMS_PARAM_PFVF_CQ_START   = 0x17,
1094         FW_PARAMS_PARAM_PFVF_CQ_END     = 0x18,
1095         FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
1096         FW_PARAMS_PARAM_PFVF_VIID       = 0x24,
1097         FW_PARAMS_PARAM_PFVF_CPMASK     = 0x25,
1098         FW_PARAMS_PARAM_PFVF_OCQ_START  = 0x26,
1099         FW_PARAMS_PARAM_PFVF_OCQ_END    = 0x27,
1100         FW_PARAMS_PARAM_PFVF_CONM_MAP   = 0x28,
1101         FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
1102         FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
1103         FW_PARAMS_PARAM_PFVF_EQ_START   = 0x2B,
1104         FW_PARAMS_PARAM_PFVF_EQ_END     = 0x2C,
1105         FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
1106         FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
1107         FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
1108         FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31
1109 };
1110
1111 /*
1112  * dma queue parameters
1113  */
1114 enum fw_params_param_dmaq {
1115         FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
1116         FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
1117         FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
1118         FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
1119         FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
1120         FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
1121 };
1122
1123 #define FW_PARAMS_MNEM_S        24
1124 #define FW_PARAMS_MNEM_V(x)     ((x) << FW_PARAMS_MNEM_S)
1125
1126 #define FW_PARAMS_PARAM_X_S     16
1127 #define FW_PARAMS_PARAM_X_V(x)  ((x) << FW_PARAMS_PARAM_X_S)
1128
1129 #define FW_PARAMS_PARAM_Y_S     8
1130 #define FW_PARAMS_PARAM_Y_M     0xffU
1131 #define FW_PARAMS_PARAM_Y_V(x)  ((x) << FW_PARAMS_PARAM_Y_S)
1132 #define FW_PARAMS_PARAM_Y_G(x)  (((x) >> FW_PARAMS_PARAM_Y_S) &\
1133                 FW_PARAMS_PARAM_Y_M)
1134
1135 #define FW_PARAMS_PARAM_Z_S     0
1136 #define FW_PARAMS_PARAM_Z_M     0xffu
1137 #define FW_PARAMS_PARAM_Z_V(x)  ((x) << FW_PARAMS_PARAM_Z_S)
1138 #define FW_PARAMS_PARAM_Z_G(x)  (((x) >> FW_PARAMS_PARAM_Z_S) &\
1139                 FW_PARAMS_PARAM_Z_M)
1140
1141 #define FW_PARAMS_PARAM_XYZ_S           0
1142 #define FW_PARAMS_PARAM_XYZ_V(x)        ((x) << FW_PARAMS_PARAM_XYZ_S)
1143
1144 #define FW_PARAMS_PARAM_YZ_S            0
1145 #define FW_PARAMS_PARAM_YZ_V(x)         ((x) << FW_PARAMS_PARAM_YZ_S)
1146
1147 struct fw_params_cmd {
1148         __be32 op_to_vfn;
1149         __be32 retval_len16;
1150         struct fw_params_param {
1151                 __be32 mnem;
1152                 __be32 val;
1153         } param[7];
1154 };
1155
1156 #define FW_PARAMS_CMD_PFN_S     8
1157 #define FW_PARAMS_CMD_PFN_V(x)  ((x) << FW_PARAMS_CMD_PFN_S)
1158
1159 #define FW_PARAMS_CMD_VFN_S     0
1160 #define FW_PARAMS_CMD_VFN_V(x)  ((x) << FW_PARAMS_CMD_VFN_S)
1161
1162 struct fw_pfvf_cmd {
1163         __be32 op_to_vfn;
1164         __be32 retval_len16;
1165         __be32 niqflint_niq;
1166         __be32 type_to_neq;
1167         __be32 tc_to_nexactf;
1168         __be32 r_caps_to_nethctrl;
1169         __be16 nricq;
1170         __be16 nriqp;
1171         __be32 r4;
1172 };
1173
1174 #define FW_PFVF_CMD_PFN_S       8
1175 #define FW_PFVF_CMD_PFN_V(x)    ((x) << FW_PFVF_CMD_PFN_S)
1176
1177 #define FW_PFVF_CMD_VFN_S       0
1178 #define FW_PFVF_CMD_VFN_V(x)    ((x) << FW_PFVF_CMD_VFN_S)
1179
1180 #define FW_PFVF_CMD_NIQFLINT_S          20
1181 #define FW_PFVF_CMD_NIQFLINT_M          0xfff
1182 #define FW_PFVF_CMD_NIQFLINT_V(x)       ((x) << FW_PFVF_CMD_NIQFLINT_S)
1183 #define FW_PFVF_CMD_NIQFLINT_G(x)       \
1184         (((x) >> FW_PFVF_CMD_NIQFLINT_S) & FW_PFVF_CMD_NIQFLINT_M)
1185
1186 #define FW_PFVF_CMD_NIQ_S       0
1187 #define FW_PFVF_CMD_NIQ_M       0xfffff
1188 #define FW_PFVF_CMD_NIQ_V(x)    ((x) << FW_PFVF_CMD_NIQ_S)
1189 #define FW_PFVF_CMD_NIQ_G(x)    \
1190         (((x) >> FW_PFVF_CMD_NIQ_S) & FW_PFVF_CMD_NIQ_M)
1191
1192 #define FW_PFVF_CMD_TYPE_S      31
1193 #define FW_PFVF_CMD_TYPE_M      0x1
1194 #define FW_PFVF_CMD_TYPE_V(x)   ((x) << FW_PFVF_CMD_TYPE_S)
1195 #define FW_PFVF_CMD_TYPE_G(x)   \
1196         (((x) >> FW_PFVF_CMD_TYPE_S) & FW_PFVF_CMD_TYPE_M)
1197 #define FW_PFVF_CMD_TYPE_F      FW_PFVF_CMD_TYPE_V(1U)
1198
1199 #define FW_PFVF_CMD_CMASK_S     24
1200 #define FW_PFVF_CMD_CMASK_M     0xf
1201 #define FW_PFVF_CMD_CMASK_V(x)  ((x) << FW_PFVF_CMD_CMASK_S)
1202 #define FW_PFVF_CMD_CMASK_G(x)  \
1203         (((x) >> FW_PFVF_CMD_CMASK_S) & FW_PFVF_CMD_CMASK_M)
1204
1205 #define FW_PFVF_CMD_PMASK_S     20
1206 #define FW_PFVF_CMD_PMASK_M     0xf
1207 #define FW_PFVF_CMD_PMASK_V(x)  ((x) << FW_PFVF_CMD_PMASK_S)
1208 #define FW_PFVF_CMD_PMASK_G(x) \
1209         (((x) >> FW_PFVF_CMD_PMASK_S) & FW_PFVF_CMD_PMASK_M)
1210
1211 #define FW_PFVF_CMD_NEQ_S       0
1212 #define FW_PFVF_CMD_NEQ_M       0xfffff
1213 #define FW_PFVF_CMD_NEQ_V(x)    ((x) << FW_PFVF_CMD_NEQ_S)
1214 #define FW_PFVF_CMD_NEQ_G(x)    \
1215         (((x) >> FW_PFVF_CMD_NEQ_S) & FW_PFVF_CMD_NEQ_M)
1216
1217 #define FW_PFVF_CMD_TC_S        24
1218 #define FW_PFVF_CMD_TC_M        0xff
1219 #define FW_PFVF_CMD_TC_V(x)     ((x) << FW_PFVF_CMD_TC_S)
1220 #define FW_PFVF_CMD_TC_G(x)     (((x) >> FW_PFVF_CMD_TC_S) & FW_PFVF_CMD_TC_M)
1221
1222 #define FW_PFVF_CMD_NVI_S       16
1223 #define FW_PFVF_CMD_NVI_M       0xff
1224 #define FW_PFVF_CMD_NVI_V(x)    ((x) << FW_PFVF_CMD_NVI_S)
1225 #define FW_PFVF_CMD_NVI_G(x)    (((x) >> FW_PFVF_CMD_NVI_S) & FW_PFVF_CMD_NVI_M)
1226
1227 #define FW_PFVF_CMD_NEXACTF_S           0
1228 #define FW_PFVF_CMD_NEXACTF_M           0xffff
1229 #define FW_PFVF_CMD_NEXACTF_V(x)        ((x) << FW_PFVF_CMD_NEXACTF_S)
1230 #define FW_PFVF_CMD_NEXACTF_G(x)        \
1231         (((x) >> FW_PFVF_CMD_NEXACTF_S) & FW_PFVF_CMD_NEXACTF_M)
1232
1233 #define FW_PFVF_CMD_R_CAPS_S    24
1234 #define FW_PFVF_CMD_R_CAPS_M    0xff
1235 #define FW_PFVF_CMD_R_CAPS_V(x) ((x) << FW_PFVF_CMD_R_CAPS_S)
1236 #define FW_PFVF_CMD_R_CAPS_G(x) \
1237         (((x) >> FW_PFVF_CMD_R_CAPS_S) & FW_PFVF_CMD_R_CAPS_M)
1238
1239 #define FW_PFVF_CMD_WX_CAPS_S           16
1240 #define FW_PFVF_CMD_WX_CAPS_M           0xff
1241 #define FW_PFVF_CMD_WX_CAPS_V(x)        ((x) << FW_PFVF_CMD_WX_CAPS_S)
1242 #define FW_PFVF_CMD_WX_CAPS_G(x)        \
1243         (((x) >> FW_PFVF_CMD_WX_CAPS_S) & FW_PFVF_CMD_WX_CAPS_M)
1244
1245 #define FW_PFVF_CMD_NETHCTRL_S          0
1246 #define FW_PFVF_CMD_NETHCTRL_M          0xffff
1247 #define FW_PFVF_CMD_NETHCTRL_V(x)       ((x) << FW_PFVF_CMD_NETHCTRL_S)
1248 #define FW_PFVF_CMD_NETHCTRL_G(x)       \
1249         (((x) >> FW_PFVF_CMD_NETHCTRL_S) & FW_PFVF_CMD_NETHCTRL_M)
1250
1251 enum fw_iq_type {
1252         FW_IQ_TYPE_FL_INT_CAP,
1253         FW_IQ_TYPE_NO_FL_INT_CAP
1254 };
1255
1256 struct fw_iq_cmd {
1257         __be32 op_to_vfn;
1258         __be32 alloc_to_len16;
1259         __be16 physiqid;
1260         __be16 iqid;
1261         __be16 fl0id;
1262         __be16 fl1id;
1263         __be32 type_to_iqandstindex;
1264         __be16 iqdroprss_to_iqesize;
1265         __be16 iqsize;
1266         __be64 iqaddr;
1267         __be32 iqns_to_fl0congen;
1268         __be16 fl0dcaen_to_fl0cidxfthresh;
1269         __be16 fl0size;
1270         __be64 fl0addr;
1271         __be32 fl1cngchmap_to_fl1congen;
1272         __be16 fl1dcaen_to_fl1cidxfthresh;
1273         __be16 fl1size;
1274         __be64 fl1addr;
1275 };
1276
1277 #define FW_IQ_CMD_PFN_S         8
1278 #define FW_IQ_CMD_PFN_V(x)      ((x) << FW_IQ_CMD_PFN_S)
1279
1280 #define FW_IQ_CMD_VFN_S         0
1281 #define FW_IQ_CMD_VFN_V(x)      ((x) << FW_IQ_CMD_VFN_S)
1282
1283 #define FW_IQ_CMD_ALLOC_S       31
1284 #define FW_IQ_CMD_ALLOC_V(x)    ((x) << FW_IQ_CMD_ALLOC_S)
1285 #define FW_IQ_CMD_ALLOC_F       FW_IQ_CMD_ALLOC_V(1U)
1286
1287 #define FW_IQ_CMD_FREE_S        30
1288 #define FW_IQ_CMD_FREE_V(x)     ((x) << FW_IQ_CMD_FREE_S)
1289 #define FW_IQ_CMD_FREE_F        FW_IQ_CMD_FREE_V(1U)
1290
1291 #define FW_IQ_CMD_MODIFY_S      29
1292 #define FW_IQ_CMD_MODIFY_V(x)   ((x) << FW_IQ_CMD_MODIFY_S)
1293 #define FW_IQ_CMD_MODIFY_F      FW_IQ_CMD_MODIFY_V(1U)
1294
1295 #define FW_IQ_CMD_IQSTART_S     28
1296 #define FW_IQ_CMD_IQSTART_V(x)  ((x) << FW_IQ_CMD_IQSTART_S)
1297 #define FW_IQ_CMD_IQSTART_F     FW_IQ_CMD_IQSTART_V(1U)
1298
1299 #define FW_IQ_CMD_IQSTOP_S      27
1300 #define FW_IQ_CMD_IQSTOP_V(x)   ((x) << FW_IQ_CMD_IQSTOP_S)
1301 #define FW_IQ_CMD_IQSTOP_F      FW_IQ_CMD_IQSTOP_V(1U)
1302
1303 #define FW_IQ_CMD_TYPE_S        29
1304 #define FW_IQ_CMD_TYPE_V(x)     ((x) << FW_IQ_CMD_TYPE_S)
1305
1306 #define FW_IQ_CMD_IQASYNCH_S    28
1307 #define FW_IQ_CMD_IQASYNCH_V(x) ((x) << FW_IQ_CMD_IQASYNCH_S)
1308
1309 #define FW_IQ_CMD_VIID_S        16
1310 #define FW_IQ_CMD_VIID_V(x)     ((x) << FW_IQ_CMD_VIID_S)
1311
1312 #define FW_IQ_CMD_IQANDST_S     15
1313 #define FW_IQ_CMD_IQANDST_V(x)  ((x) << FW_IQ_CMD_IQANDST_S)
1314
1315 #define FW_IQ_CMD_IQANUS_S      14
1316 #define FW_IQ_CMD_IQANUS_V(x)   ((x) << FW_IQ_CMD_IQANUS_S)
1317
1318 #define FW_IQ_CMD_IQANUD_S      12
1319 #define FW_IQ_CMD_IQANUD_V(x)   ((x) << FW_IQ_CMD_IQANUD_S)
1320
1321 #define FW_IQ_CMD_IQANDSTINDEX_S        0
1322 #define FW_IQ_CMD_IQANDSTINDEX_V(x)     ((x) << FW_IQ_CMD_IQANDSTINDEX_S)
1323
1324 #define FW_IQ_CMD_IQDROPRSS_S           15
1325 #define FW_IQ_CMD_IQDROPRSS_V(x)        ((x) << FW_IQ_CMD_IQDROPRSS_S)
1326 #define FW_IQ_CMD_IQDROPRSS_F   FW_IQ_CMD_IQDROPRSS_V(1U)
1327
1328 #define FW_IQ_CMD_IQGTSMODE_S           14
1329 #define FW_IQ_CMD_IQGTSMODE_V(x)        ((x) << FW_IQ_CMD_IQGTSMODE_S)
1330 #define FW_IQ_CMD_IQGTSMODE_F           FW_IQ_CMD_IQGTSMODE_V(1U)
1331
1332 #define FW_IQ_CMD_IQPCIECH_S    12
1333 #define FW_IQ_CMD_IQPCIECH_V(x) ((x) << FW_IQ_CMD_IQPCIECH_S)
1334
1335 #define FW_IQ_CMD_IQDCAEN_S     11
1336 #define FW_IQ_CMD_IQDCAEN_V(x)  ((x) << FW_IQ_CMD_IQDCAEN_S)
1337
1338 #define FW_IQ_CMD_IQDCACPU_S    6
1339 #define FW_IQ_CMD_IQDCACPU_V(x) ((x) << FW_IQ_CMD_IQDCACPU_S)
1340
1341 #define FW_IQ_CMD_IQINTCNTTHRESH_S      4
1342 #define FW_IQ_CMD_IQINTCNTTHRESH_V(x)   ((x) << FW_IQ_CMD_IQINTCNTTHRESH_S)
1343
1344 #define FW_IQ_CMD_IQO_S         3
1345 #define FW_IQ_CMD_IQO_V(x)      ((x) << FW_IQ_CMD_IQO_S)
1346 #define FW_IQ_CMD_IQO_F         FW_IQ_CMD_IQO_V(1U)
1347
1348 #define FW_IQ_CMD_IQCPRIO_S     2
1349 #define FW_IQ_CMD_IQCPRIO_V(x)  ((x) << FW_IQ_CMD_IQCPRIO_S)
1350
1351 #define FW_IQ_CMD_IQESIZE_S     0
1352 #define FW_IQ_CMD_IQESIZE_V(x)  ((x) << FW_IQ_CMD_IQESIZE_S)
1353
1354 #define FW_IQ_CMD_IQNS_S        31
1355 #define FW_IQ_CMD_IQNS_V(x)     ((x) << FW_IQ_CMD_IQNS_S)
1356
1357 #define FW_IQ_CMD_IQRO_S        30
1358 #define FW_IQ_CMD_IQRO_V(x)     ((x) << FW_IQ_CMD_IQRO_S)
1359
1360 #define FW_IQ_CMD_IQFLINTIQHSEN_S       28
1361 #define FW_IQ_CMD_IQFLINTIQHSEN_V(x)    ((x) << FW_IQ_CMD_IQFLINTIQHSEN_S)
1362
1363 #define FW_IQ_CMD_IQFLINTCONGEN_S       27
1364 #define FW_IQ_CMD_IQFLINTCONGEN_V(x)    ((x) << FW_IQ_CMD_IQFLINTCONGEN_S)
1365
1366 #define FW_IQ_CMD_IQFLINTISCSIC_S       26
1367 #define FW_IQ_CMD_IQFLINTISCSIC_V(x)    ((x) << FW_IQ_CMD_IQFLINTISCSIC_S)
1368
1369 #define FW_IQ_CMD_FL0CNGCHMAP_S         20
1370 #define FW_IQ_CMD_FL0CNGCHMAP_V(x)      ((x) << FW_IQ_CMD_FL0CNGCHMAP_S)
1371
1372 #define FW_IQ_CMD_FL0CACHELOCK_S        15
1373 #define FW_IQ_CMD_FL0CACHELOCK_V(x)     ((x) << FW_IQ_CMD_FL0CACHELOCK_S)
1374
1375 #define FW_IQ_CMD_FL0DBP_S      14
1376 #define FW_IQ_CMD_FL0DBP_V(x)   ((x) << FW_IQ_CMD_FL0DBP_S)
1377
1378 #define FW_IQ_CMD_FL0DATANS_S           13
1379 #define FW_IQ_CMD_FL0DATANS_V(x)        ((x) << FW_IQ_CMD_FL0DATANS_S)
1380
1381 #define FW_IQ_CMD_FL0DATARO_S           12
1382 #define FW_IQ_CMD_FL0DATARO_V(x)        ((x) << FW_IQ_CMD_FL0DATARO_S)
1383 #define FW_IQ_CMD_FL0DATARO_F           FW_IQ_CMD_FL0DATARO_V(1U)
1384
1385 #define FW_IQ_CMD_FL0CONGCIF_S          11
1386 #define FW_IQ_CMD_FL0CONGCIF_V(x)       ((x) << FW_IQ_CMD_FL0CONGCIF_S)
1387
1388 #define FW_IQ_CMD_FL0ONCHIP_S           10
1389 #define FW_IQ_CMD_FL0ONCHIP_V(x)        ((x) << FW_IQ_CMD_FL0ONCHIP_S)
1390
1391 #define FW_IQ_CMD_FL0STATUSPGNS_S       9
1392 #define FW_IQ_CMD_FL0STATUSPGNS_V(x)    ((x) << FW_IQ_CMD_FL0STATUSPGNS_S)
1393
1394 #define FW_IQ_CMD_FL0STATUSPGRO_S       8
1395 #define FW_IQ_CMD_FL0STATUSPGRO_V(x)    ((x) << FW_IQ_CMD_FL0STATUSPGRO_S)
1396
1397 #define FW_IQ_CMD_FL0FETCHNS_S          7
1398 #define FW_IQ_CMD_FL0FETCHNS_V(x)       ((x) << FW_IQ_CMD_FL0FETCHNS_S)
1399
1400 #define FW_IQ_CMD_FL0FETCHRO_S          6
1401 #define FW_IQ_CMD_FL0FETCHRO_V(x)       ((x) << FW_IQ_CMD_FL0FETCHRO_S)
1402 #define FW_IQ_CMD_FL0FETCHRO_F          FW_IQ_CMD_FL0FETCHRO_V(1U)
1403
1404 #define FW_IQ_CMD_FL0HOSTFCMODE_S       4
1405 #define FW_IQ_CMD_FL0HOSTFCMODE_V(x)    ((x) << FW_IQ_CMD_FL0HOSTFCMODE_S)
1406
1407 #define FW_IQ_CMD_FL0CPRIO_S    3
1408 #define FW_IQ_CMD_FL0CPRIO_V(x) ((x) << FW_IQ_CMD_FL0CPRIO_S)
1409
1410 #define FW_IQ_CMD_FL0PADEN_S    2
1411 #define FW_IQ_CMD_FL0PADEN_V(x) ((x) << FW_IQ_CMD_FL0PADEN_S)
1412 #define FW_IQ_CMD_FL0PADEN_F    FW_IQ_CMD_FL0PADEN_V(1U)
1413
1414 #define FW_IQ_CMD_FL0PACKEN_S           1
1415 #define FW_IQ_CMD_FL0PACKEN_V(x)        ((x) << FW_IQ_CMD_FL0PACKEN_S)
1416 #define FW_IQ_CMD_FL0PACKEN_F           FW_IQ_CMD_FL0PACKEN_V(1U)
1417
1418 #define FW_IQ_CMD_FL0CONGEN_S           0
1419 #define FW_IQ_CMD_FL0CONGEN_V(x)        ((x) << FW_IQ_CMD_FL0CONGEN_S)
1420 #define FW_IQ_CMD_FL0CONGEN_F           FW_IQ_CMD_FL0CONGEN_V(1U)
1421
1422 #define FW_IQ_CMD_FL0DCAEN_S    15
1423 #define FW_IQ_CMD_FL0DCAEN_V(x) ((x) << FW_IQ_CMD_FL0DCAEN_S)
1424
1425 #define FW_IQ_CMD_FL0DCACPU_S           10
1426 #define FW_IQ_CMD_FL0DCACPU_V(x)        ((x) << FW_IQ_CMD_FL0DCACPU_S)
1427
1428 #define FW_IQ_CMD_FL0FBMIN_S    7
1429 #define FW_IQ_CMD_FL0FBMIN_V(x) ((x) << FW_IQ_CMD_FL0FBMIN_S)
1430
1431 #define FW_IQ_CMD_FL0FBMAX_S    4
1432 #define FW_IQ_CMD_FL0FBMAX_V(x) ((x) << FW_IQ_CMD_FL0FBMAX_S)
1433
1434 #define FW_IQ_CMD_FL0CIDXFTHRESHO_S     3
1435 #define FW_IQ_CMD_FL0CIDXFTHRESHO_V(x)  ((x) << FW_IQ_CMD_FL0CIDXFTHRESHO_S)
1436 #define FW_IQ_CMD_FL0CIDXFTHRESHO_F     FW_IQ_CMD_FL0CIDXFTHRESHO_V(1U)
1437
1438 #define FW_IQ_CMD_FL0CIDXFTHRESH_S      0
1439 #define FW_IQ_CMD_FL0CIDXFTHRESH_V(x)   ((x) << FW_IQ_CMD_FL0CIDXFTHRESH_S)
1440
1441 #define FW_IQ_CMD_FL1CNGCHMAP_S         20
1442 #define FW_IQ_CMD_FL1CNGCHMAP_V(x)      ((x) << FW_IQ_CMD_FL1CNGCHMAP_S)
1443
1444 #define FW_IQ_CMD_FL1CACHELOCK_S        15
1445 #define FW_IQ_CMD_FL1CACHELOCK_V(x)     ((x) << FW_IQ_CMD_FL1CACHELOCK_S)
1446
1447 #define FW_IQ_CMD_FL1DBP_S      14
1448 #define FW_IQ_CMD_FL1DBP_V(x)   ((x) << FW_IQ_CMD_FL1DBP_S)
1449
1450 #define FW_IQ_CMD_FL1DATANS_S           13
1451 #define FW_IQ_CMD_FL1DATANS_V(x)        ((x) << FW_IQ_CMD_FL1DATANS_S)
1452
1453 #define FW_IQ_CMD_FL1DATARO_S           12
1454 #define FW_IQ_CMD_FL1DATARO_V(x)        ((x) << FW_IQ_CMD_FL1DATARO_S)
1455
1456 #define FW_IQ_CMD_FL1CONGCIF_S          11
1457 #define FW_IQ_CMD_FL1CONGCIF_V(x)       ((x) << FW_IQ_CMD_FL1CONGCIF_S)
1458
1459 #define FW_IQ_CMD_FL1ONCHIP_S           10
1460 #define FW_IQ_CMD_FL1ONCHIP_V(x)        ((x) << FW_IQ_CMD_FL1ONCHIP_S)
1461
1462 #define FW_IQ_CMD_FL1STATUSPGNS_S       9
1463 #define FW_IQ_CMD_FL1STATUSPGNS_V(x)    ((x) << FW_IQ_CMD_FL1STATUSPGNS_S)
1464
1465 #define FW_IQ_CMD_FL1STATUSPGRO_S       8
1466 #define FW_IQ_CMD_FL1STATUSPGRO_V(x)    ((x) << FW_IQ_CMD_FL1STATUSPGRO_S)
1467
1468 #define FW_IQ_CMD_FL1FETCHNS_S          7
1469 #define FW_IQ_CMD_FL1FETCHNS_V(x)       ((x) << FW_IQ_CMD_FL1FETCHNS_S)
1470
1471 #define FW_IQ_CMD_FL1FETCHRO_S          6
1472 #define FW_IQ_CMD_FL1FETCHRO_V(x)       ((x) << FW_IQ_CMD_FL1FETCHRO_S)
1473
1474 #define FW_IQ_CMD_FL1HOSTFCMODE_S       4
1475 #define FW_IQ_CMD_FL1HOSTFCMODE_V(x)    ((x) << FW_IQ_CMD_FL1HOSTFCMODE_S)
1476
1477 #define FW_IQ_CMD_FL1CPRIO_S    3
1478 #define FW_IQ_CMD_FL1CPRIO_V(x) ((x) << FW_IQ_CMD_FL1CPRIO_S)
1479
1480 #define FW_IQ_CMD_FL1PADEN_S    2
1481 #define FW_IQ_CMD_FL1PADEN_V(x) ((x) << FW_IQ_CMD_FL1PADEN_S)
1482 #define FW_IQ_CMD_FL1PADEN_F    FW_IQ_CMD_FL1PADEN_V(1U)
1483
1484 #define FW_IQ_CMD_FL1PACKEN_S           1
1485 #define FW_IQ_CMD_FL1PACKEN_V(x)        ((x) << FW_IQ_CMD_FL1PACKEN_S)
1486 #define FW_IQ_CMD_FL1PACKEN_F   FW_IQ_CMD_FL1PACKEN_V(1U)
1487
1488 #define FW_IQ_CMD_FL1CONGEN_S           0
1489 #define FW_IQ_CMD_FL1CONGEN_V(x)        ((x) << FW_IQ_CMD_FL1CONGEN_S)
1490 #define FW_IQ_CMD_FL1CONGEN_F   FW_IQ_CMD_FL1CONGEN_V(1U)
1491
1492 #define FW_IQ_CMD_FL1DCAEN_S    15
1493 #define FW_IQ_CMD_FL1DCAEN_V(x) ((x) << FW_IQ_CMD_FL1DCAEN_S)
1494
1495 #define FW_IQ_CMD_FL1DCACPU_S           10
1496 #define FW_IQ_CMD_FL1DCACPU_V(x)        ((x) << FW_IQ_CMD_FL1DCACPU_S)
1497
1498 #define FW_IQ_CMD_FL1FBMIN_S    7
1499 #define FW_IQ_CMD_FL1FBMIN_V(x) ((x) << FW_IQ_CMD_FL1FBMIN_S)
1500
1501 #define FW_IQ_CMD_FL1FBMAX_S    4
1502 #define FW_IQ_CMD_FL1FBMAX_V(x) ((x) << FW_IQ_CMD_FL1FBMAX_S)
1503
1504 #define FW_IQ_CMD_FL1CIDXFTHRESHO_S     3
1505 #define FW_IQ_CMD_FL1CIDXFTHRESHO_V(x)  ((x) << FW_IQ_CMD_FL1CIDXFTHRESHO_S)
1506 #define FW_IQ_CMD_FL1CIDXFTHRESHO_F     FW_IQ_CMD_FL1CIDXFTHRESHO_V(1U)
1507
1508 #define FW_IQ_CMD_FL1CIDXFTHRESH_S      0
1509 #define FW_IQ_CMD_FL1CIDXFTHRESH_V(x)   ((x) << FW_IQ_CMD_FL1CIDXFTHRESH_S)
1510
1511 struct fw_eq_eth_cmd {
1512         __be32 op_to_vfn;
1513         __be32 alloc_to_len16;
1514         __be32 eqid_pkd;
1515         __be32 physeqid_pkd;
1516         __be32 fetchszm_to_iqid;
1517         __be32 dcaen_to_eqsize;
1518         __be64 eqaddr;
1519         __be32 viid_pkd;
1520         __be32 r8_lo;
1521         __be64 r9;
1522 };
1523
1524 #define FW_EQ_ETH_CMD_PFN_S     8
1525 #define FW_EQ_ETH_CMD_PFN_V(x)  ((x) << FW_EQ_ETH_CMD_PFN_S)
1526
1527 #define FW_EQ_ETH_CMD_VFN_S     0
1528 #define FW_EQ_ETH_CMD_VFN_V(x)  ((x) << FW_EQ_ETH_CMD_VFN_S)
1529
1530 #define FW_EQ_ETH_CMD_ALLOC_S           31
1531 #define FW_EQ_ETH_CMD_ALLOC_V(x)        ((x) << FW_EQ_ETH_CMD_ALLOC_S)
1532 #define FW_EQ_ETH_CMD_ALLOC_F   FW_EQ_ETH_CMD_ALLOC_V(1U)
1533
1534 #define FW_EQ_ETH_CMD_FREE_S    30
1535 #define FW_EQ_ETH_CMD_FREE_V(x) ((x) << FW_EQ_ETH_CMD_FREE_S)
1536 #define FW_EQ_ETH_CMD_FREE_F    FW_EQ_ETH_CMD_FREE_V(1U)
1537
1538 #define FW_EQ_ETH_CMD_MODIFY_S          29
1539 #define FW_EQ_ETH_CMD_MODIFY_V(x)       ((x) << FW_EQ_ETH_CMD_MODIFY_S)
1540 #define FW_EQ_ETH_CMD_MODIFY_F  FW_EQ_ETH_CMD_MODIFY_V(1U)
1541
1542 #define FW_EQ_ETH_CMD_EQSTART_S         28
1543 #define FW_EQ_ETH_CMD_EQSTART_V(x)      ((x) << FW_EQ_ETH_CMD_EQSTART_S)
1544 #define FW_EQ_ETH_CMD_EQSTART_F FW_EQ_ETH_CMD_EQSTART_V(1U)
1545
1546 #define FW_EQ_ETH_CMD_EQSTOP_S          27
1547 #define FW_EQ_ETH_CMD_EQSTOP_V(x)       ((x) << FW_EQ_ETH_CMD_EQSTOP_S)
1548 #define FW_EQ_ETH_CMD_EQSTOP_F  FW_EQ_ETH_CMD_EQSTOP_V(1U)
1549
1550 #define FW_EQ_ETH_CMD_EQID_S    0
1551 #define FW_EQ_ETH_CMD_EQID_M    0xfffff
1552 #define FW_EQ_ETH_CMD_EQID_V(x) ((x) << FW_EQ_ETH_CMD_EQID_S)
1553 #define FW_EQ_ETH_CMD_EQID_G(x) \
1554         (((x) >> FW_EQ_ETH_CMD_EQID_S) & FW_EQ_ETH_CMD_EQID_M)
1555
1556 #define FW_EQ_ETH_CMD_PHYSEQID_S        0
1557 #define FW_EQ_ETH_CMD_PHYSEQID_M        0xfffff
1558 #define FW_EQ_ETH_CMD_PHYSEQID_V(x)     ((x) << FW_EQ_ETH_CMD_PHYSEQID_S)
1559 #define FW_EQ_ETH_CMD_PHYSEQID_G(x)     \
1560         (((x) >> FW_EQ_ETH_CMD_PHYSEQID_S) & FW_EQ_ETH_CMD_PHYSEQID_M)
1561
1562 #define FW_EQ_ETH_CMD_FETCHSZM_S        26
1563 #define FW_EQ_ETH_CMD_FETCHSZM_V(x)     ((x) << FW_EQ_ETH_CMD_FETCHSZM_S)
1564 #define FW_EQ_ETH_CMD_FETCHSZM_F        FW_EQ_ETH_CMD_FETCHSZM_V(1U)
1565
1566 #define FW_EQ_ETH_CMD_STATUSPGNS_S      25
1567 #define FW_EQ_ETH_CMD_STATUSPGNS_V(x)   ((x) << FW_EQ_ETH_CMD_STATUSPGNS_S)
1568
1569 #define FW_EQ_ETH_CMD_STATUSPGRO_S      24
1570 #define FW_EQ_ETH_CMD_STATUSPGRO_V(x)   ((x) << FW_EQ_ETH_CMD_STATUSPGRO_S)
1571
1572 #define FW_EQ_ETH_CMD_FETCHNS_S         23
1573 #define FW_EQ_ETH_CMD_FETCHNS_V(x)      ((x) << FW_EQ_ETH_CMD_FETCHNS_S)
1574
1575 #define FW_EQ_ETH_CMD_FETCHRO_S         22
1576 #define FW_EQ_ETH_CMD_FETCHRO_V(x)      ((x) << FW_EQ_ETH_CMD_FETCHRO_S)
1577
1578 #define FW_EQ_ETH_CMD_HOSTFCMODE_S      20
1579 #define FW_EQ_ETH_CMD_HOSTFCMODE_V(x)   ((x) << FW_EQ_ETH_CMD_HOSTFCMODE_S)
1580
1581 #define FW_EQ_ETH_CMD_CPRIO_S           19
1582 #define FW_EQ_ETH_CMD_CPRIO_V(x)        ((x) << FW_EQ_ETH_CMD_CPRIO_S)
1583
1584 #define FW_EQ_ETH_CMD_ONCHIP_S          18
1585 #define FW_EQ_ETH_CMD_ONCHIP_V(x)       ((x) << FW_EQ_ETH_CMD_ONCHIP_S)
1586
1587 #define FW_EQ_ETH_CMD_PCIECHN_S         16
1588 #define FW_EQ_ETH_CMD_PCIECHN_V(x)      ((x) << FW_EQ_ETH_CMD_PCIECHN_S)
1589
1590 #define FW_EQ_ETH_CMD_IQID_S    0
1591 #define FW_EQ_ETH_CMD_IQID_V(x) ((x) << FW_EQ_ETH_CMD_IQID_S)
1592
1593 #define FW_EQ_ETH_CMD_DCAEN_S           31
1594 #define FW_EQ_ETH_CMD_DCAEN_V(x)        ((x) << FW_EQ_ETH_CMD_DCAEN_S)
1595
1596 #define FW_EQ_ETH_CMD_DCACPU_S          26
1597 #define FW_EQ_ETH_CMD_DCACPU_V(x)       ((x) << FW_EQ_ETH_CMD_DCACPU_S)
1598
1599 #define FW_EQ_ETH_CMD_FBMIN_S           23
1600 #define FW_EQ_ETH_CMD_FBMIN_V(x)        ((x) << FW_EQ_ETH_CMD_FBMIN_S)
1601
1602 #define FW_EQ_ETH_CMD_FBMAX_S           20
1603 #define FW_EQ_ETH_CMD_FBMAX_V(x)        ((x) << FW_EQ_ETH_CMD_FBMAX_S)
1604
1605 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_S    19
1606 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESHO_S)
1607
1608 #define FW_EQ_ETH_CMD_CIDXFTHRESH_S     16
1609 #define FW_EQ_ETH_CMD_CIDXFTHRESH_V(x)  ((x) << FW_EQ_ETH_CMD_CIDXFTHRESH_S)
1610
1611 #define FW_EQ_ETH_CMD_EQSIZE_S          0
1612 #define FW_EQ_ETH_CMD_EQSIZE_V(x)       ((x) << FW_EQ_ETH_CMD_EQSIZE_S)
1613
1614 #define FW_EQ_ETH_CMD_AUTOEQUEQE_S      30
1615 #define FW_EQ_ETH_CMD_AUTOEQUEQE_V(x)   ((x) << FW_EQ_ETH_CMD_AUTOEQUEQE_S)
1616 #define FW_EQ_ETH_CMD_AUTOEQUEQE_F      FW_EQ_ETH_CMD_AUTOEQUEQE_V(1U)
1617
1618 #define FW_EQ_ETH_CMD_VIID_S    16
1619 #define FW_EQ_ETH_CMD_VIID_V(x) ((x) << FW_EQ_ETH_CMD_VIID_S)
1620
1621 struct fw_eq_ctrl_cmd {
1622         __be32 op_to_vfn;
1623         __be32 alloc_to_len16;
1624         __be32 cmpliqid_eqid;
1625         __be32 physeqid_pkd;
1626         __be32 fetchszm_to_iqid;
1627         __be32 dcaen_to_eqsize;
1628         __be64 eqaddr;
1629 };
1630
1631 #define FW_EQ_CTRL_CMD_PFN_S    8
1632 #define FW_EQ_CTRL_CMD_PFN_V(x) ((x) << FW_EQ_CTRL_CMD_PFN_S)
1633
1634 #define FW_EQ_CTRL_CMD_VFN_S    0
1635 #define FW_EQ_CTRL_CMD_VFN_V(x) ((x) << FW_EQ_CTRL_CMD_VFN_S)
1636
1637 #define FW_EQ_CTRL_CMD_ALLOC_S          31
1638 #define FW_EQ_CTRL_CMD_ALLOC_V(x)       ((x) << FW_EQ_CTRL_CMD_ALLOC_S)
1639 #define FW_EQ_CTRL_CMD_ALLOC_F          FW_EQ_CTRL_CMD_ALLOC_V(1U)
1640
1641 #define FW_EQ_CTRL_CMD_FREE_S           30
1642 #define FW_EQ_CTRL_CMD_FREE_V(x)        ((x) << FW_EQ_CTRL_CMD_FREE_S)
1643 #define FW_EQ_CTRL_CMD_FREE_F           FW_EQ_CTRL_CMD_FREE_V(1U)
1644
1645 #define FW_EQ_CTRL_CMD_MODIFY_S         29
1646 #define FW_EQ_CTRL_CMD_MODIFY_V(x)      ((x) << FW_EQ_CTRL_CMD_MODIFY_S)
1647 #define FW_EQ_CTRL_CMD_MODIFY_F         FW_EQ_CTRL_CMD_MODIFY_V(1U)
1648
1649 #define FW_EQ_CTRL_CMD_EQSTART_S        28
1650 #define FW_EQ_CTRL_CMD_EQSTART_V(x)     ((x) << FW_EQ_CTRL_CMD_EQSTART_S)
1651 #define FW_EQ_CTRL_CMD_EQSTART_F        FW_EQ_CTRL_CMD_EQSTART_V(1U)
1652
1653 #define FW_EQ_CTRL_CMD_EQSTOP_S         27
1654 #define FW_EQ_CTRL_CMD_EQSTOP_V(x)      ((x) << FW_EQ_CTRL_CMD_EQSTOP_S)
1655 #define FW_EQ_CTRL_CMD_EQSTOP_F         FW_EQ_CTRL_CMD_EQSTOP_V(1U)
1656
1657 #define FW_EQ_CTRL_CMD_CMPLIQID_S       20
1658 #define FW_EQ_CTRL_CMD_CMPLIQID_V(x)    ((x) << FW_EQ_CTRL_CMD_CMPLIQID_S)
1659
1660 #define FW_EQ_CTRL_CMD_EQID_S           0
1661 #define FW_EQ_CTRL_CMD_EQID_M           0xfffff
1662 #define FW_EQ_CTRL_CMD_EQID_V(x)        ((x) << FW_EQ_CTRL_CMD_EQID_S)
1663 #define FW_EQ_CTRL_CMD_EQID_G(x)        \
1664         (((x) >> FW_EQ_CTRL_CMD_EQID_S) & FW_EQ_CTRL_CMD_EQID_M)
1665
1666 #define FW_EQ_CTRL_CMD_PHYSEQID_S       0
1667 #define FW_EQ_CTRL_CMD_PHYSEQID_M       0xfffff
1668 #define FW_EQ_CTRL_CMD_PHYSEQID_G(x)    \
1669         (((x) >> FW_EQ_CTRL_CMD_PHYSEQID_S) & FW_EQ_CTRL_CMD_PHYSEQID_M)
1670
1671 #define FW_EQ_CTRL_CMD_FETCHSZM_S       26
1672 #define FW_EQ_CTRL_CMD_FETCHSZM_V(x)    ((x) << FW_EQ_CTRL_CMD_FETCHSZM_S)
1673 #define FW_EQ_CTRL_CMD_FETCHSZM_F       FW_EQ_CTRL_CMD_FETCHSZM_V(1U)
1674
1675 #define FW_EQ_CTRL_CMD_STATUSPGNS_S     25
1676 #define FW_EQ_CTRL_CMD_STATUSPGNS_V(x)  ((x) << FW_EQ_CTRL_CMD_STATUSPGNS_S)
1677 #define FW_EQ_CTRL_CMD_STATUSPGNS_F     FW_EQ_CTRL_CMD_STATUSPGNS_V(1U)
1678
1679 #define FW_EQ_CTRL_CMD_STATUSPGRO_S     24
1680 #define FW_EQ_CTRL_CMD_STATUSPGRO_V(x)  ((x) << FW_EQ_CTRL_CMD_STATUSPGRO_S)
1681 #define FW_EQ_CTRL_CMD_STATUSPGRO_F     FW_EQ_CTRL_CMD_STATUSPGRO_V(1U)
1682
1683 #define FW_EQ_CTRL_CMD_FETCHNS_S        23
1684 #define FW_EQ_CTRL_CMD_FETCHNS_V(x)     ((x) << FW_EQ_CTRL_CMD_FETCHNS_S)
1685 #define FW_EQ_CTRL_CMD_FETCHNS_F        FW_EQ_CTRL_CMD_FETCHNS_V(1U)
1686
1687 #define FW_EQ_CTRL_CMD_FETCHRO_S        22
1688 #define FW_EQ_CTRL_CMD_FETCHRO_V(x)     ((x) << FW_EQ_CTRL_CMD_FETCHRO_S)
1689 #define FW_EQ_CTRL_CMD_FETCHRO_F        FW_EQ_CTRL_CMD_FETCHRO_V(1U)
1690
1691 #define FW_EQ_CTRL_CMD_HOSTFCMODE_S     20
1692 #define FW_EQ_CTRL_CMD_HOSTFCMODE_V(x)  ((x) << FW_EQ_CTRL_CMD_HOSTFCMODE_S)
1693
1694 #define FW_EQ_CTRL_CMD_CPRIO_S          19
1695 #define FW_EQ_CTRL_CMD_CPRIO_V(x)       ((x) << FW_EQ_CTRL_CMD_CPRIO_S)
1696
1697 #define FW_EQ_CTRL_CMD_ONCHIP_S         18
1698 #define FW_EQ_CTRL_CMD_ONCHIP_V(x)      ((x) << FW_EQ_CTRL_CMD_ONCHIP_S)
1699
1700 #define FW_EQ_CTRL_CMD_PCIECHN_S        16
1701 #define FW_EQ_CTRL_CMD_PCIECHN_V(x)     ((x) << FW_EQ_CTRL_CMD_PCIECHN_S)
1702
1703 #define FW_EQ_CTRL_CMD_IQID_S           0
1704 #define FW_EQ_CTRL_CMD_IQID_V(x)        ((x) << FW_EQ_CTRL_CMD_IQID_S)
1705
1706 #define FW_EQ_CTRL_CMD_DCAEN_S          31
1707 #define FW_EQ_CTRL_CMD_DCAEN_V(x)       ((x) << FW_EQ_CTRL_CMD_DCAEN_S)
1708
1709 #define FW_EQ_CTRL_CMD_DCACPU_S         26
1710 #define FW_EQ_CTRL_CMD_DCACPU_V(x)      ((x) << FW_EQ_CTRL_CMD_DCACPU_S)
1711
1712 #define FW_EQ_CTRL_CMD_FBMIN_S          23
1713 #define FW_EQ_CTRL_CMD_FBMIN_V(x)       ((x) << FW_EQ_CTRL_CMD_FBMIN_S)
1714
1715 #define FW_EQ_CTRL_CMD_FBMAX_S          20
1716 #define FW_EQ_CTRL_CMD_FBMAX_V(x)       ((x) << FW_EQ_CTRL_CMD_FBMAX_S)
1717
1718 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_S           19
1719 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_V(x)        \
1720         ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESHO_S)
1721
1722 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_S    16
1723 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESH_S)
1724
1725 #define FW_EQ_CTRL_CMD_EQSIZE_S         0
1726 #define FW_EQ_CTRL_CMD_EQSIZE_V(x)      ((x) << FW_EQ_CTRL_CMD_EQSIZE_S)
1727
1728 struct fw_eq_ofld_cmd {
1729         __be32 op_to_vfn;
1730         __be32 alloc_to_len16;
1731         __be32 eqid_pkd;
1732         __be32 physeqid_pkd;
1733         __be32 fetchszm_to_iqid;
1734         __be32 dcaen_to_eqsize;
1735         __be64 eqaddr;
1736 };
1737
1738 #define FW_EQ_OFLD_CMD_PFN_S    8
1739 #define FW_EQ_OFLD_CMD_PFN_V(x) ((x) << FW_EQ_OFLD_CMD_PFN_S)
1740
1741 #define FW_EQ_OFLD_CMD_VFN_S    0
1742 #define FW_EQ_OFLD_CMD_VFN_V(x) ((x) << FW_EQ_OFLD_CMD_VFN_S)
1743
1744 #define FW_EQ_OFLD_CMD_ALLOC_S          31
1745 #define FW_EQ_OFLD_CMD_ALLOC_V(x)       ((x) << FW_EQ_OFLD_CMD_ALLOC_S)
1746 #define FW_EQ_OFLD_CMD_ALLOC_F          FW_EQ_OFLD_CMD_ALLOC_V(1U)
1747
1748 #define FW_EQ_OFLD_CMD_FREE_S           30
1749 #define FW_EQ_OFLD_CMD_FREE_V(x)        ((x) << FW_EQ_OFLD_CMD_FREE_S)
1750 #define FW_EQ_OFLD_CMD_FREE_F           FW_EQ_OFLD_CMD_FREE_V(1U)
1751
1752 #define FW_EQ_OFLD_CMD_MODIFY_S         29
1753 #define FW_EQ_OFLD_CMD_MODIFY_V(x)      ((x) << FW_EQ_OFLD_CMD_MODIFY_S)
1754 #define FW_EQ_OFLD_CMD_MODIFY_F         FW_EQ_OFLD_CMD_MODIFY_V(1U)
1755
1756 #define FW_EQ_OFLD_CMD_EQSTART_S        28
1757 #define FW_EQ_OFLD_CMD_EQSTART_V(x)     ((x) << FW_EQ_OFLD_CMD_EQSTART_S)
1758 #define FW_EQ_OFLD_CMD_EQSTART_F        FW_EQ_OFLD_CMD_EQSTART_V(1U)
1759
1760 #define FW_EQ_OFLD_CMD_EQSTOP_S         27
1761 #define FW_EQ_OFLD_CMD_EQSTOP_V(x)      ((x) << FW_EQ_OFLD_CMD_EQSTOP_S)
1762 #define FW_EQ_OFLD_CMD_EQSTOP_F         FW_EQ_OFLD_CMD_EQSTOP_V(1U)
1763
1764 #define FW_EQ_OFLD_CMD_EQID_S           0
1765 #define FW_EQ_OFLD_CMD_EQID_M           0xfffff
1766 #define FW_EQ_OFLD_CMD_EQID_V(x)        ((x) << FW_EQ_OFLD_CMD_EQID_S)
1767 #define FW_EQ_OFLD_CMD_EQID_G(x)        \
1768         (((x) >> FW_EQ_OFLD_CMD_EQID_S) & FW_EQ_OFLD_CMD_EQID_M)
1769
1770 #define FW_EQ_OFLD_CMD_PHYSEQID_S       0
1771 #define FW_EQ_OFLD_CMD_PHYSEQID_M       0xfffff
1772 #define FW_EQ_OFLD_CMD_PHYSEQID_G(x)    \
1773         (((x) >> FW_EQ_OFLD_CMD_PHYSEQID_S) & FW_EQ_OFLD_CMD_PHYSEQID_M)
1774
1775 #define FW_EQ_OFLD_CMD_FETCHSZM_S       26
1776 #define FW_EQ_OFLD_CMD_FETCHSZM_V(x)    ((x) << FW_EQ_OFLD_CMD_FETCHSZM_S)
1777
1778 #define FW_EQ_OFLD_CMD_STATUSPGNS_S     25
1779 #define FW_EQ_OFLD_CMD_STATUSPGNS_V(x)  ((x) << FW_EQ_OFLD_CMD_STATUSPGNS_S)
1780
1781 #define FW_EQ_OFLD_CMD_STATUSPGRO_S     24
1782 #define FW_EQ_OFLD_CMD_STATUSPGRO_V(x)  ((x) << FW_EQ_OFLD_CMD_STATUSPGRO_S)
1783
1784 #define FW_EQ_OFLD_CMD_FETCHNS_S        23
1785 #define FW_EQ_OFLD_CMD_FETCHNS_V(x)     ((x) << FW_EQ_OFLD_CMD_FETCHNS_S)
1786
1787 #define FW_EQ_OFLD_CMD_FETCHRO_S        22
1788 #define FW_EQ_OFLD_CMD_FETCHRO_V(x)     ((x) << FW_EQ_OFLD_CMD_FETCHRO_S)
1789 #define FW_EQ_OFLD_CMD_FETCHRO_F        FW_EQ_OFLD_CMD_FETCHRO_V(1U)
1790
1791 #define FW_EQ_OFLD_CMD_HOSTFCMODE_S     20
1792 #define FW_EQ_OFLD_CMD_HOSTFCMODE_V(x)  ((x) << FW_EQ_OFLD_CMD_HOSTFCMODE_S)
1793
1794 #define FW_EQ_OFLD_CMD_CPRIO_S          19
1795 #define FW_EQ_OFLD_CMD_CPRIO_V(x)       ((x) << FW_EQ_OFLD_CMD_CPRIO_S)
1796
1797 #define FW_EQ_OFLD_CMD_ONCHIP_S         18
1798 #define FW_EQ_OFLD_CMD_ONCHIP_V(x)      ((x) << FW_EQ_OFLD_CMD_ONCHIP_S)
1799
1800 #define FW_EQ_OFLD_CMD_PCIECHN_S        16
1801 #define FW_EQ_OFLD_CMD_PCIECHN_V(x)     ((x) << FW_EQ_OFLD_CMD_PCIECHN_S)
1802
1803 #define FW_EQ_OFLD_CMD_IQID_S           0
1804 #define FW_EQ_OFLD_CMD_IQID_V(x)        ((x) << FW_EQ_OFLD_CMD_IQID_S)
1805
1806 #define FW_EQ_OFLD_CMD_DCAEN_S          31
1807 #define FW_EQ_OFLD_CMD_DCAEN_V(x)       ((x) << FW_EQ_OFLD_CMD_DCAEN_S)
1808
1809 #define FW_EQ_OFLD_CMD_DCACPU_S         26
1810 #define FW_EQ_OFLD_CMD_DCACPU_V(x)      ((x) << FW_EQ_OFLD_CMD_DCACPU_S)
1811
1812 #define FW_EQ_OFLD_CMD_FBMIN_S          23
1813 #define FW_EQ_OFLD_CMD_FBMIN_V(x)       ((x) << FW_EQ_OFLD_CMD_FBMIN_S)
1814
1815 #define FW_EQ_OFLD_CMD_FBMAX_S          20
1816 #define FW_EQ_OFLD_CMD_FBMAX_V(x)       ((x) << FW_EQ_OFLD_CMD_FBMAX_S)
1817
1818 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_S           19
1819 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_V(x)        \
1820         ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESHO_S)
1821
1822 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_S    16
1823 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESH_S)
1824
1825 #define FW_EQ_OFLD_CMD_EQSIZE_S         0
1826 #define FW_EQ_OFLD_CMD_EQSIZE_V(x)      ((x) << FW_EQ_OFLD_CMD_EQSIZE_S)
1827
1828 /*
1829  * Macros for VIID parsing:
1830  * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
1831  */
1832
1833 #define FW_VIID_PFN_S           8
1834 #define FW_VIID_PFN_M           0x7
1835 #define FW_VIID_PFN_G(x)        (((x) >> FW_VIID_PFN_S) & FW_VIID_PFN_M)
1836
1837 #define FW_VIID_VIVLD_S         7
1838 #define FW_VIID_VIVLD_M         0x1
1839 #define FW_VIID_VIVLD_G(x)      (((x) >> FW_VIID_VIVLD_S) & FW_VIID_VIVLD_M)
1840
1841 #define FW_VIID_VIN_S           0
1842 #define FW_VIID_VIN_M           0x7F
1843 #define FW_VIID_VIN_G(x)        (((x) >> FW_VIID_VIN_S) & FW_VIID_VIN_M)
1844
1845 struct fw_vi_cmd {
1846         __be32 op_to_vfn;
1847         __be32 alloc_to_len16;
1848         __be16 type_viid;
1849         u8 mac[6];
1850         u8 portid_pkd;
1851         u8 nmac;
1852         u8 nmac0[6];
1853         __be16 rsssize_pkd;
1854         u8 nmac1[6];
1855         __be16 idsiiq_pkd;
1856         u8 nmac2[6];
1857         __be16 idseiq_pkd;
1858         u8 nmac3[6];
1859         __be64 r9;
1860         __be64 r10;
1861 };
1862
1863 #define FW_VI_CMD_PFN_S         8
1864 #define FW_VI_CMD_PFN_V(x)      ((x) << FW_VI_CMD_PFN_S)
1865
1866 #define FW_VI_CMD_VFN_S         0
1867 #define FW_VI_CMD_VFN_V(x)      ((x) << FW_VI_CMD_VFN_S)
1868
1869 #define FW_VI_CMD_ALLOC_S       31
1870 #define FW_VI_CMD_ALLOC_V(x)    ((x) << FW_VI_CMD_ALLOC_S)
1871 #define FW_VI_CMD_ALLOC_F       FW_VI_CMD_ALLOC_V(1U)
1872
1873 #define FW_VI_CMD_FREE_S        30
1874 #define FW_VI_CMD_FREE_V(x)     ((x) << FW_VI_CMD_FREE_S)
1875 #define FW_VI_CMD_FREE_F        FW_VI_CMD_FREE_V(1U)
1876
1877 #define FW_VI_CMD_VIID_S        0
1878 #define FW_VI_CMD_VIID_M        0xfff
1879 #define FW_VI_CMD_VIID_V(x)     ((x) << FW_VI_CMD_VIID_S)
1880 #define FW_VI_CMD_VIID_G(x)     (((x) >> FW_VI_CMD_VIID_S) & FW_VI_CMD_VIID_M)
1881
1882 #define FW_VI_CMD_PORTID_S      4
1883 #define FW_VI_CMD_PORTID_M      0xf
1884 #define FW_VI_CMD_PORTID_V(x)   ((x) << FW_VI_CMD_PORTID_S)
1885 #define FW_VI_CMD_PORTID_G(x)   \
1886         (((x) >> FW_VI_CMD_PORTID_S) & FW_VI_CMD_PORTID_M)
1887
1888 #define FW_VI_CMD_RSSSIZE_S     0
1889 #define FW_VI_CMD_RSSSIZE_M     0x7ff
1890 #define FW_VI_CMD_RSSSIZE_G(x)  \
1891         (((x) >> FW_VI_CMD_RSSSIZE_S) & FW_VI_CMD_RSSSIZE_M)
1892
1893 /* Special VI_MAC command index ids */
1894 #define FW_VI_MAC_ADD_MAC               0x3FF
1895 #define FW_VI_MAC_ADD_PERSIST_MAC       0x3FE
1896 #define FW_VI_MAC_MAC_BASED_FREE        0x3FD
1897 #define FW_CLS_TCAM_NUM_ENTRIES         336
1898
1899 enum fw_vi_mac_smac {
1900         FW_VI_MAC_MPS_TCAM_ENTRY,
1901         FW_VI_MAC_MPS_TCAM_ONLY,
1902         FW_VI_MAC_SMT_ONLY,
1903         FW_VI_MAC_SMT_AND_MPSTCAM
1904 };
1905
1906 enum fw_vi_mac_result {
1907         FW_VI_MAC_R_SUCCESS,
1908         FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
1909         FW_VI_MAC_R_SMAC_FAIL,
1910         FW_VI_MAC_R_F_ACL_CHECK
1911 };
1912
1913 struct fw_vi_mac_cmd {
1914         __be32 op_to_viid;
1915         __be32 freemacs_to_len16;
1916         union fw_vi_mac {
1917                 struct fw_vi_mac_exact {
1918                         __be16 valid_to_idx;
1919                         u8 macaddr[6];
1920                 } exact[7];
1921                 struct fw_vi_mac_hash {
1922                         __be64 hashvec;
1923                 } hash;
1924         } u;
1925 };
1926
1927 #define FW_VI_MAC_CMD_VIID_S    0
1928 #define FW_VI_MAC_CMD_VIID_V(x) ((x) << FW_VI_MAC_CMD_VIID_S)
1929
1930 #define FW_VI_MAC_CMD_FREEMACS_S        31
1931 #define FW_VI_MAC_CMD_FREEMACS_V(x)     ((x) << FW_VI_MAC_CMD_FREEMACS_S)
1932
1933 #define FW_VI_MAC_CMD_HASHVECEN_S       23
1934 #define FW_VI_MAC_CMD_HASHVECEN_V(x)    ((x) << FW_VI_MAC_CMD_HASHVECEN_S)
1935 #define FW_VI_MAC_CMD_HASHVECEN_F       FW_VI_MAC_CMD_HASHVECEN_V(1U)
1936
1937 #define FW_VI_MAC_CMD_HASHUNIEN_S       22
1938 #define FW_VI_MAC_CMD_HASHUNIEN_V(x)    ((x) << FW_VI_MAC_CMD_HASHUNIEN_S)
1939
1940 #define FW_VI_MAC_CMD_VALID_S           15
1941 #define FW_VI_MAC_CMD_VALID_V(x)        ((x) << FW_VI_MAC_CMD_VALID_S)
1942 #define FW_VI_MAC_CMD_VALID_F   FW_VI_MAC_CMD_VALID_V(1U)
1943
1944 #define FW_VI_MAC_CMD_PRIO_S    12
1945 #define FW_VI_MAC_CMD_PRIO_V(x) ((x) << FW_VI_MAC_CMD_PRIO_S)
1946
1947 #define FW_VI_MAC_CMD_SMAC_RESULT_S     10
1948 #define FW_VI_MAC_CMD_SMAC_RESULT_M     0x3
1949 #define FW_VI_MAC_CMD_SMAC_RESULT_V(x)  ((x) << FW_VI_MAC_CMD_SMAC_RESULT_S)
1950 #define FW_VI_MAC_CMD_SMAC_RESULT_G(x)  \
1951         (((x) >> FW_VI_MAC_CMD_SMAC_RESULT_S) & FW_VI_MAC_CMD_SMAC_RESULT_M)
1952
1953 #define FW_VI_MAC_CMD_IDX_S     0
1954 #define FW_VI_MAC_CMD_IDX_M     0x3ff
1955 #define FW_VI_MAC_CMD_IDX_V(x)  ((x) << FW_VI_MAC_CMD_IDX_S)
1956 #define FW_VI_MAC_CMD_IDX_G(x)  \
1957         (((x) >> FW_VI_MAC_CMD_IDX_S) & FW_VI_MAC_CMD_IDX_M)
1958
1959 #define FW_RXMODE_MTU_NO_CHG    65535
1960
1961 struct fw_vi_rxmode_cmd {
1962         __be32 op_to_viid;
1963         __be32 retval_len16;
1964         __be32 mtu_to_vlanexen;
1965         __be32 r4_lo;
1966 };
1967
1968 #define FW_VI_RXMODE_CMD_VIID_S         0
1969 #define FW_VI_RXMODE_CMD_VIID_V(x)      ((x) << FW_VI_RXMODE_CMD_VIID_S)
1970
1971 #define FW_VI_RXMODE_CMD_MTU_S          16
1972 #define FW_VI_RXMODE_CMD_MTU_M          0xffff
1973 #define FW_VI_RXMODE_CMD_MTU_V(x)       ((x) << FW_VI_RXMODE_CMD_MTU_S)
1974
1975 #define FW_VI_RXMODE_CMD_PROMISCEN_S    14
1976 #define FW_VI_RXMODE_CMD_PROMISCEN_M    0x3
1977 #define FW_VI_RXMODE_CMD_PROMISCEN_V(x) ((x) << FW_VI_RXMODE_CMD_PROMISCEN_S)
1978
1979 #define FW_VI_RXMODE_CMD_ALLMULTIEN_S           12
1980 #define FW_VI_RXMODE_CMD_ALLMULTIEN_M           0x3
1981 #define FW_VI_RXMODE_CMD_ALLMULTIEN_V(x)        \
1982         ((x) << FW_VI_RXMODE_CMD_ALLMULTIEN_S)
1983
1984 #define FW_VI_RXMODE_CMD_BROADCASTEN_S          10
1985 #define FW_VI_RXMODE_CMD_BROADCASTEN_M          0x3
1986 #define FW_VI_RXMODE_CMD_BROADCASTEN_V(x)       \
1987         ((x) << FW_VI_RXMODE_CMD_BROADCASTEN_S)
1988
1989 #define FW_VI_RXMODE_CMD_VLANEXEN_S     8
1990 #define FW_VI_RXMODE_CMD_VLANEXEN_M     0x3
1991 #define FW_VI_RXMODE_CMD_VLANEXEN_V(x)  ((x) << FW_VI_RXMODE_CMD_VLANEXEN_S)
1992
1993 struct fw_vi_enable_cmd {
1994         __be32 op_to_viid;
1995         __be32 ien_to_len16;
1996         __be16 blinkdur;
1997         __be16 r3;
1998         __be32 r4;
1999 };
2000
2001 #define FW_VI_ENABLE_CMD_VIID_S         0
2002 #define FW_VI_ENABLE_CMD_VIID_V(x)      ((x) << FW_VI_ENABLE_CMD_VIID_S)
2003
2004 #define FW_VI_ENABLE_CMD_IEN_S          31
2005 #define FW_VI_ENABLE_CMD_IEN_V(x)       ((x) << FW_VI_ENABLE_CMD_IEN_S)
2006
2007 #define FW_VI_ENABLE_CMD_EEN_S          30
2008 #define FW_VI_ENABLE_CMD_EEN_V(x)       ((x) << FW_VI_ENABLE_CMD_EEN_S)
2009
2010 #define FW_VI_ENABLE_CMD_LED_S          29
2011 #define FW_VI_ENABLE_CMD_LED_V(x)       ((x) << FW_VI_ENABLE_CMD_LED_S)
2012 #define FW_VI_ENABLE_CMD_LED_F  FW_VI_ENABLE_CMD_LED_V(1U)
2013
2014 #define FW_VI_ENABLE_CMD_DCB_INFO_S     28
2015 #define FW_VI_ENABLE_CMD_DCB_INFO_V(x)  ((x) << FW_VI_ENABLE_CMD_DCB_INFO_S)
2016
2017 /* VI VF stats offset definitions */
2018 #define VI_VF_NUM_STATS 16
2019 enum fw_vi_stats_vf_index {
2020         FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
2021         FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
2022         FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
2023         FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
2024         FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
2025         FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
2026         FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
2027         FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
2028         FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
2029         FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
2030         FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
2031         FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
2032         FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
2033         FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
2034         FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
2035         FW_VI_VF_STAT_RX_ERR_FRAMES_IX
2036 };
2037
2038 /* VI PF stats offset definitions */
2039 #define VI_PF_NUM_STATS 17
2040 enum fw_vi_stats_pf_index {
2041         FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
2042         FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
2043         FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
2044         FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
2045         FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
2046         FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
2047         FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
2048         FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
2049         FW_VI_PF_STAT_RX_BYTES_IX,
2050         FW_VI_PF_STAT_RX_FRAMES_IX,
2051         FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
2052         FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
2053         FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
2054         FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
2055         FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
2056         FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
2057         FW_VI_PF_STAT_RX_ERR_FRAMES_IX
2058 };
2059
2060 struct fw_vi_stats_cmd {
2061         __be32 op_to_viid;
2062         __be32 retval_len16;
2063         union fw_vi_stats {
2064                 struct fw_vi_stats_ctl {
2065                         __be16 nstats_ix;
2066                         __be16 r6;
2067                         __be32 r7;
2068                         __be64 stat0;
2069                         __be64 stat1;
2070                         __be64 stat2;
2071                         __be64 stat3;
2072                         __be64 stat4;
2073                         __be64 stat5;
2074                 } ctl;
2075                 struct fw_vi_stats_pf {
2076                         __be64 tx_bcast_bytes;
2077                         __be64 tx_bcast_frames;
2078                         __be64 tx_mcast_bytes;
2079                         __be64 tx_mcast_frames;
2080                         __be64 tx_ucast_bytes;
2081                         __be64 tx_ucast_frames;
2082                         __be64 tx_offload_bytes;
2083                         __be64 tx_offload_frames;
2084                         __be64 rx_pf_bytes;
2085                         __be64 rx_pf_frames;
2086                         __be64 rx_bcast_bytes;
2087                         __be64 rx_bcast_frames;
2088                         __be64 rx_mcast_bytes;
2089                         __be64 rx_mcast_frames;
2090                         __be64 rx_ucast_bytes;
2091                         __be64 rx_ucast_frames;
2092                         __be64 rx_err_frames;
2093                 } pf;
2094                 struct fw_vi_stats_vf {
2095                         __be64 tx_bcast_bytes;
2096                         __be64 tx_bcast_frames;
2097                         __be64 tx_mcast_bytes;
2098                         __be64 tx_mcast_frames;
2099                         __be64 tx_ucast_bytes;
2100                         __be64 tx_ucast_frames;
2101                         __be64 tx_drop_frames;
2102                         __be64 tx_offload_bytes;
2103                         __be64 tx_offload_frames;
2104                         __be64 rx_bcast_bytes;
2105                         __be64 rx_bcast_frames;
2106                         __be64 rx_mcast_bytes;
2107                         __be64 rx_mcast_frames;
2108                         __be64 rx_ucast_bytes;
2109                         __be64 rx_ucast_frames;
2110                         __be64 rx_err_frames;
2111                 } vf;
2112         } u;
2113 };
2114
2115 #define FW_VI_STATS_CMD_VIID_S          0
2116 #define FW_VI_STATS_CMD_VIID_V(x)       ((x) << FW_VI_STATS_CMD_VIID_S)
2117
2118 #define FW_VI_STATS_CMD_NSTATS_S        12
2119 #define FW_VI_STATS_CMD_NSTATS_V(x)     ((x) << FW_VI_STATS_CMD_NSTATS_S)
2120
2121 #define FW_VI_STATS_CMD_IX_S    0
2122 #define FW_VI_STATS_CMD_IX_V(x) ((x) << FW_VI_STATS_CMD_IX_S)
2123
2124 struct fw_acl_mac_cmd {
2125         __be32 op_to_vfn;
2126         __be32 en_to_len16;
2127         u8 nmac;
2128         u8 r3[7];
2129         __be16 r4;
2130         u8 macaddr0[6];
2131         __be16 r5;
2132         u8 macaddr1[6];
2133         __be16 r6;
2134         u8 macaddr2[6];
2135         __be16 r7;
2136         u8 macaddr3[6];
2137 };
2138
2139 #define FW_ACL_MAC_CMD_PFN_S    8
2140 #define FW_ACL_MAC_CMD_PFN_V(x) ((x) << FW_ACL_MAC_CMD_PFN_S)
2141
2142 #define FW_ACL_MAC_CMD_VFN_S    0
2143 #define FW_ACL_MAC_CMD_VFN_V(x) ((x) << FW_ACL_MAC_CMD_VFN_S)
2144
2145 #define FW_ACL_MAC_CMD_EN_S     31
2146 #define FW_ACL_MAC_CMD_EN_V(x)  ((x) << FW_ACL_MAC_CMD_EN_S)
2147
2148 struct fw_acl_vlan_cmd {
2149         __be32 op_to_vfn;
2150         __be32 en_to_len16;
2151         u8 nvlan;
2152         u8 dropnovlan_fm;
2153         u8 r3_lo[6];
2154         __be16 vlanid[16];
2155 };
2156
2157 #define FW_ACL_VLAN_CMD_PFN_S           8
2158 #define FW_ACL_VLAN_CMD_PFN_V(x)        ((x) << FW_ACL_VLAN_CMD_PFN_S)
2159
2160 #define FW_ACL_VLAN_CMD_VFN_S           0
2161 #define FW_ACL_VLAN_CMD_VFN_V(x)        ((x) << FW_ACL_VLAN_CMD_VFN_S)
2162
2163 #define FW_ACL_VLAN_CMD_EN_S    31
2164 #define FW_ACL_VLAN_CMD_EN_V(x) ((x) << FW_ACL_VLAN_CMD_EN_S)
2165
2166 #define FW_ACL_VLAN_CMD_DROPNOVLAN_S    7
2167 #define FW_ACL_VLAN_CMD_DROPNOVLAN_V(x) ((x) << FW_ACL_VLAN_CMD_DROPNOVLAN_S)
2168
2169 #define FW_ACL_VLAN_CMD_FM_S    6
2170 #define FW_ACL_VLAN_CMD_FM_V(x) ((x) << FW_ACL_VLAN_CMD_FM_S)
2171
2172 enum fw_port_cap {
2173         FW_PORT_CAP_SPEED_100M          = 0x0001,
2174         FW_PORT_CAP_SPEED_1G            = 0x0002,
2175         FW_PORT_CAP_SPEED_2_5G          = 0x0004,
2176         FW_PORT_CAP_SPEED_10G           = 0x0008,
2177         FW_PORT_CAP_SPEED_40G           = 0x0010,
2178         FW_PORT_CAP_SPEED_100G          = 0x0020,
2179         FW_PORT_CAP_FC_RX               = 0x0040,
2180         FW_PORT_CAP_FC_TX               = 0x0080,
2181         FW_PORT_CAP_ANEG                = 0x0100,
2182         FW_PORT_CAP_MDI_0               = 0x0200,
2183         FW_PORT_CAP_MDI_1               = 0x0400,
2184         FW_PORT_CAP_BEAN                = 0x0800,
2185         FW_PORT_CAP_PMA_LPBK            = 0x1000,
2186         FW_PORT_CAP_PCS_LPBK            = 0x2000,
2187         FW_PORT_CAP_PHYXS_LPBK          = 0x4000,
2188         FW_PORT_CAP_FAR_END_LPBK        = 0x8000,
2189 };
2190
2191 enum fw_port_mdi {
2192         FW_PORT_CAP_MDI_UNCHANGED,
2193         FW_PORT_CAP_MDI_AUTO,
2194         FW_PORT_CAP_MDI_F_STRAIGHT,
2195         FW_PORT_CAP_MDI_F_CROSSOVER
2196 };
2197
2198 #define FW_PORT_CAP_MDI_S 9
2199 #define FW_PORT_CAP_MDI_V(x) ((x) << FW_PORT_CAP_MDI_S)
2200
2201 enum fw_port_action {
2202         FW_PORT_ACTION_L1_CFG           = 0x0001,
2203         FW_PORT_ACTION_L2_CFG           = 0x0002,
2204         FW_PORT_ACTION_GET_PORT_INFO    = 0x0003,
2205         FW_PORT_ACTION_L2_PPP_CFG       = 0x0004,
2206         FW_PORT_ACTION_L2_DCB_CFG       = 0x0005,
2207         FW_PORT_ACTION_DCB_READ_TRANS   = 0x0006,
2208         FW_PORT_ACTION_DCB_READ_RECV    = 0x0007,
2209         FW_PORT_ACTION_DCB_READ_DET     = 0x0008,
2210         FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
2211         FW_PORT_ACTION_L1_LOW_PWR_EN    = 0x0011,
2212         FW_PORT_ACTION_L2_WOL_MODE_EN   = 0x0012,
2213         FW_PORT_ACTION_LPBK_TO_NORMAL   = 0x0020,
2214         FW_PORT_ACTION_L1_LPBK          = 0x0021,
2215         FW_PORT_ACTION_L1_PMA_LPBK      = 0x0022,
2216         FW_PORT_ACTION_L1_PCS_LPBK      = 0x0023,
2217         FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024,
2218         FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025,
2219         FW_PORT_ACTION_PHY_RESET        = 0x0040,
2220         FW_PORT_ACTION_PMA_RESET        = 0x0041,
2221         FW_PORT_ACTION_PCS_RESET        = 0x0042,
2222         FW_PORT_ACTION_PHYXS_RESET      = 0x0043,
2223         FW_PORT_ACTION_DTEXS_REEST      = 0x0044,
2224         FW_PORT_ACTION_AN_RESET         = 0x0045
2225 };
2226
2227 enum fw_port_l2cfg_ctlbf {
2228         FW_PORT_L2_CTLBF_OVLAN0 = 0x01,
2229         FW_PORT_L2_CTLBF_OVLAN1 = 0x02,
2230         FW_PORT_L2_CTLBF_OVLAN2 = 0x04,
2231         FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
2232         FW_PORT_L2_CTLBF_IVLAN  = 0x10,
2233         FW_PORT_L2_CTLBF_TXIPG  = 0x20
2234 };
2235
2236 enum fw_port_dcb_versions {
2237         FW_PORT_DCB_VER_UNKNOWN,
2238         FW_PORT_DCB_VER_CEE1D0,
2239         FW_PORT_DCB_VER_CEE1D01,
2240         FW_PORT_DCB_VER_IEEE,
2241         FW_PORT_DCB_VER_AUTO = 7
2242 };
2243
2244 enum fw_port_dcb_cfg {
2245         FW_PORT_DCB_CFG_PG      = 0x01,
2246         FW_PORT_DCB_CFG_PFC     = 0x02,
2247         FW_PORT_DCB_CFG_APPL    = 0x04
2248 };
2249
2250 enum fw_port_dcb_cfg_rc {
2251         FW_PORT_DCB_CFG_SUCCESS = 0x0,
2252         FW_PORT_DCB_CFG_ERROR   = 0x1
2253 };
2254
2255 enum fw_port_dcb_type {
2256         FW_PORT_DCB_TYPE_PGID           = 0x00,
2257         FW_PORT_DCB_TYPE_PGRATE         = 0x01,
2258         FW_PORT_DCB_TYPE_PRIORATE       = 0x02,
2259         FW_PORT_DCB_TYPE_PFC            = 0x03,
2260         FW_PORT_DCB_TYPE_APP_ID         = 0x04,
2261         FW_PORT_DCB_TYPE_CONTROL        = 0x05,
2262 };
2263
2264 enum fw_port_dcb_feature_state {
2265         FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0,
2266         FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1,
2267         FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2,
2268         FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3,
2269 };
2270
2271 struct fw_port_cmd {
2272         __be32 op_to_portid;
2273         __be32 action_to_len16;
2274         union fw_port {
2275                 struct fw_port_l1cfg {
2276                         __be32 rcap;
2277                         __be32 r;
2278                 } l1cfg;
2279                 struct fw_port_l2cfg {
2280                         __u8   ctlbf;
2281                         __u8   ovlan3_to_ivlan0;
2282                         __be16 ivlantype;
2283                         __be16 txipg_force_pinfo;
2284                         __be16 mtu;
2285                         __be16 ovlan0mask;
2286                         __be16 ovlan0type;
2287                         __be16 ovlan1mask;
2288                         __be16 ovlan1type;
2289                         __be16 ovlan2mask;
2290                         __be16 ovlan2type;
2291                         __be16 ovlan3mask;
2292                         __be16 ovlan3type;
2293                 } l2cfg;
2294                 struct fw_port_info {
2295                         __be32 lstatus_to_modtype;
2296                         __be16 pcap;
2297                         __be16 acap;
2298                         __be16 mtu;
2299                         __u8   cbllen;
2300                         __u8   auxlinfo;
2301                         __u8   dcbxdis_pkd;
2302                         __u8   r8_lo[3];
2303                         __be64 r9;
2304                 } info;
2305                 struct fw_port_diags {
2306                         __u8   diagop;
2307                         __u8   r[3];
2308                         __be32 diagval;
2309                 } diags;
2310                 union fw_port_dcb {
2311                         struct fw_port_dcb_pgid {
2312                                 __u8   type;
2313                                 __u8   apply_pkd;
2314                                 __u8   r10_lo[2];
2315                                 __be32 pgid;
2316                                 __be64 r11;
2317                         } pgid;
2318                         struct fw_port_dcb_pgrate {
2319                                 __u8   type;
2320                                 __u8   apply_pkd;
2321                                 __u8   r10_lo[5];
2322                                 __u8   num_tcs_supported;
2323                                 __u8   pgrate[8];
2324                                 __u8   tsa[8];
2325                         } pgrate;
2326                         struct fw_port_dcb_priorate {
2327                                 __u8   type;
2328                                 __u8   apply_pkd;
2329                                 __u8   r10_lo[6];
2330                                 __u8   strict_priorate[8];
2331                         } priorate;
2332                         struct fw_port_dcb_pfc {
2333                                 __u8   type;
2334                                 __u8   pfcen;
2335                                 __u8   r10[5];
2336                                 __u8   max_pfc_tcs;
2337                                 __be64 r11;
2338                         } pfc;
2339                         struct fw_port_app_priority {
2340                                 __u8   type;
2341                                 __u8   r10[2];
2342                                 __u8   idx;
2343                                 __u8   user_prio_map;
2344                                 __u8   sel_field;
2345                                 __be16 protocolid;
2346                                 __be64 r12;
2347                         } app_priority;
2348                         struct fw_port_dcb_control {
2349                                 __u8   type;
2350                                 __u8   all_syncd_pkd;
2351                                 __be16 dcb_version_to_app_state;
2352                                 __be32 r11;
2353                                 __be64 r12;
2354                         } control;
2355                 } dcb;
2356         } u;
2357 };
2358
2359 #define FW_PORT_CMD_READ_S      22
2360 #define FW_PORT_CMD_READ_V(x)   ((x) << FW_PORT_CMD_READ_S)
2361 #define FW_PORT_CMD_READ_F      FW_PORT_CMD_READ_V(1U)
2362
2363 #define FW_PORT_CMD_PORTID_S    0
2364 #define FW_PORT_CMD_PORTID_M    0xf
2365 #define FW_PORT_CMD_PORTID_V(x) ((x) << FW_PORT_CMD_PORTID_S)
2366 #define FW_PORT_CMD_PORTID_G(x) \
2367         (((x) >> FW_PORT_CMD_PORTID_S) & FW_PORT_CMD_PORTID_M)
2368
2369 #define FW_PORT_CMD_ACTION_S    16
2370 #define FW_PORT_CMD_ACTION_M    0xffff
2371 #define FW_PORT_CMD_ACTION_V(x) ((x) << FW_PORT_CMD_ACTION_S)
2372 #define FW_PORT_CMD_ACTION_G(x) \
2373         (((x) >> FW_PORT_CMD_ACTION_S) & FW_PORT_CMD_ACTION_M)
2374
2375 #define FW_PORT_CMD_OVLAN3_S    7
2376 #define FW_PORT_CMD_OVLAN3_V(x) ((x) << FW_PORT_CMD_OVLAN3_S)
2377
2378 #define FW_PORT_CMD_OVLAN2_S    6
2379 #define FW_PORT_CMD_OVLAN2_V(x) ((x) << FW_PORT_CMD_OVLAN2_S)
2380
2381 #define FW_PORT_CMD_OVLAN1_S    5
2382 #define FW_PORT_CMD_OVLAN1_V(x) ((x) << FW_PORT_CMD_OVLAN1_S)
2383
2384 #define FW_PORT_CMD_OVLAN0_S    4
2385 #define FW_PORT_CMD_OVLAN0_V(x) ((x) << FW_PORT_CMD_OVLAN0_S)
2386
2387 #define FW_PORT_CMD_IVLAN0_S    3
2388 #define FW_PORT_CMD_IVLAN0_V(x) ((x) << FW_PORT_CMD_IVLAN0_S)
2389
2390 #define FW_PORT_CMD_TXIPG_S     3
2391 #define FW_PORT_CMD_TXIPG_V(x)  ((x) << FW_PORT_CMD_TXIPG_S)
2392
2393 #define FW_PORT_CMD_LSTATUS_S           31
2394 #define FW_PORT_CMD_LSTATUS_M           0x1
2395 #define FW_PORT_CMD_LSTATUS_V(x)        ((x) << FW_PORT_CMD_LSTATUS_S)
2396 #define FW_PORT_CMD_LSTATUS_G(x)        \
2397         (((x) >> FW_PORT_CMD_LSTATUS_S) & FW_PORT_CMD_LSTATUS_M)
2398 #define FW_PORT_CMD_LSTATUS_F   FW_PORT_CMD_LSTATUS_V(1U)
2399
2400 #define FW_PORT_CMD_LSPEED_S    24
2401 #define FW_PORT_CMD_LSPEED_M    0x3f
2402 #define FW_PORT_CMD_LSPEED_V(x) ((x) << FW_PORT_CMD_LSPEED_S)
2403 #define FW_PORT_CMD_LSPEED_G(x) \
2404         (((x) >> FW_PORT_CMD_LSPEED_S) & FW_PORT_CMD_LSPEED_M)
2405
2406 #define FW_PORT_CMD_TXPAUSE_S           23
2407 #define FW_PORT_CMD_TXPAUSE_V(x)        ((x) << FW_PORT_CMD_TXPAUSE_S)
2408 #define FW_PORT_CMD_TXPAUSE_F   FW_PORT_CMD_TXPAUSE_V(1U)
2409
2410 #define FW_PORT_CMD_RXPAUSE_S           22
2411 #define FW_PORT_CMD_RXPAUSE_V(x)        ((x) << FW_PORT_CMD_RXPAUSE_S)
2412 #define FW_PORT_CMD_RXPAUSE_F   FW_PORT_CMD_RXPAUSE_V(1U)
2413
2414 #define FW_PORT_CMD_MDIOCAP_S           21
2415 #define FW_PORT_CMD_MDIOCAP_V(x)        ((x) << FW_PORT_CMD_MDIOCAP_S)
2416 #define FW_PORT_CMD_MDIOCAP_F   FW_PORT_CMD_MDIOCAP_V(1U)
2417
2418 #define FW_PORT_CMD_MDIOADDR_S          16
2419 #define FW_PORT_CMD_MDIOADDR_M          0x1f
2420 #define FW_PORT_CMD_MDIOADDR_G(x)       \
2421         (((x) >> FW_PORT_CMD_MDIOADDR_S) & FW_PORT_CMD_MDIOADDR_M)
2422
2423 #define FW_PORT_CMD_LPTXPAUSE_S         15
2424 #define FW_PORT_CMD_LPTXPAUSE_V(x)      ((x) << FW_PORT_CMD_LPTXPAUSE_S)
2425 #define FW_PORT_CMD_LPTXPAUSE_F FW_PORT_CMD_LPTXPAUSE_V(1U)
2426
2427 #define FW_PORT_CMD_LPRXPAUSE_S         14
2428 #define FW_PORT_CMD_LPRXPAUSE_V(x)      ((x) << FW_PORT_CMD_LPRXPAUSE_S)
2429 #define FW_PORT_CMD_LPRXPAUSE_F FW_PORT_CMD_LPRXPAUSE_V(1U)
2430
2431 #define FW_PORT_CMD_PTYPE_S     8
2432 #define FW_PORT_CMD_PTYPE_M     0x1f
2433 #define FW_PORT_CMD_PTYPE_G(x)  \
2434         (((x) >> FW_PORT_CMD_PTYPE_S) & FW_PORT_CMD_PTYPE_M)
2435
2436 #define FW_PORT_CMD_MODTYPE_S           0
2437 #define FW_PORT_CMD_MODTYPE_M           0x1f
2438 #define FW_PORT_CMD_MODTYPE_V(x)        ((x) << FW_PORT_CMD_MODTYPE_S)
2439 #define FW_PORT_CMD_MODTYPE_G(x)        \
2440         (((x) >> FW_PORT_CMD_MODTYPE_S) & FW_PORT_CMD_MODTYPE_M)
2441
2442 #define FW_PORT_CMD_DCBXDIS_S           7
2443 #define FW_PORT_CMD_DCBXDIS_V(x)        ((x) << FW_PORT_CMD_DCBXDIS_S)
2444 #define FW_PORT_CMD_DCBXDIS_F   FW_PORT_CMD_DCBXDIS_V(1U)
2445
2446 #define FW_PORT_CMD_APPLY_S     7
2447 #define FW_PORT_CMD_APPLY_V(x)  ((x) << FW_PORT_CMD_APPLY_S)
2448 #define FW_PORT_CMD_APPLY_F     FW_PORT_CMD_APPLY_V(1U)
2449
2450 #define FW_PORT_CMD_ALL_SYNCD_S         7
2451 #define FW_PORT_CMD_ALL_SYNCD_V(x)      ((x) << FW_PORT_CMD_ALL_SYNCD_S)
2452 #define FW_PORT_CMD_ALL_SYNCD_F FW_PORT_CMD_ALL_SYNCD_V(1U)
2453
2454 #define FW_PORT_CMD_DCB_VERSION_S       12
2455 #define FW_PORT_CMD_DCB_VERSION_M       0x7
2456 #define FW_PORT_CMD_DCB_VERSION_G(x)    \
2457         (((x) >> FW_PORT_CMD_DCB_VERSION_S) & FW_PORT_CMD_DCB_VERSION_M)
2458
2459 enum fw_port_type {
2460         FW_PORT_TYPE_FIBER_XFI,
2461         FW_PORT_TYPE_FIBER_XAUI,
2462         FW_PORT_TYPE_BT_SGMII,
2463         FW_PORT_TYPE_BT_XFI,
2464         FW_PORT_TYPE_BT_XAUI,
2465         FW_PORT_TYPE_KX4,
2466         FW_PORT_TYPE_CX4,
2467         FW_PORT_TYPE_KX,
2468         FW_PORT_TYPE_KR,
2469         FW_PORT_TYPE_SFP,
2470         FW_PORT_TYPE_BP_AP,
2471         FW_PORT_TYPE_BP4_AP,
2472         FW_PORT_TYPE_QSFP_10G,
2473         FW_PORT_TYPE_QSA,
2474         FW_PORT_TYPE_QSFP,
2475         FW_PORT_TYPE_BP40_BA,
2476
2477         FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_M
2478 };
2479
2480 enum fw_port_module_type {
2481         FW_PORT_MOD_TYPE_NA,
2482         FW_PORT_MOD_TYPE_LR,
2483         FW_PORT_MOD_TYPE_SR,
2484         FW_PORT_MOD_TYPE_ER,
2485         FW_PORT_MOD_TYPE_TWINAX_PASSIVE,
2486         FW_PORT_MOD_TYPE_TWINAX_ACTIVE,
2487         FW_PORT_MOD_TYPE_LRM,
2488         FW_PORT_MOD_TYPE_ERROR          = FW_PORT_CMD_MODTYPE_M - 3,
2489         FW_PORT_MOD_TYPE_UNKNOWN        = FW_PORT_CMD_MODTYPE_M - 2,
2490         FW_PORT_MOD_TYPE_NOTSUPPORTED   = FW_PORT_CMD_MODTYPE_M - 1,
2491
2492         FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_M
2493 };
2494
2495 enum fw_port_mod_sub_type {
2496         FW_PORT_MOD_SUB_TYPE_NA,
2497         FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
2498         FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
2499         FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
2500         FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
2501         FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
2502         FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
2503
2504         /* The following will never been in the VPD.  They are TWINAX cable
2505          * lengths decoded from SFP+ module i2c PROMs.  These should
2506          * almost certainly go somewhere else ...
2507          */
2508         FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
2509         FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
2510         FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
2511         FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
2512 };
2513
2514 /* port stats */
2515 #define FW_NUM_PORT_STATS 50
2516 #define FW_NUM_PORT_TX_STATS 23
2517 #define FW_NUM_PORT_RX_STATS 27
2518
2519 enum fw_port_stats_tx_index {
2520         FW_STAT_TX_PORT_BYTES_IX,
2521         FW_STAT_TX_PORT_FRAMES_IX,
2522         FW_STAT_TX_PORT_BCAST_IX,
2523         FW_STAT_TX_PORT_MCAST_IX,
2524         FW_STAT_TX_PORT_UCAST_IX,
2525         FW_STAT_TX_PORT_ERROR_IX,
2526         FW_STAT_TX_PORT_64B_IX,
2527         FW_STAT_TX_PORT_65B_127B_IX,
2528         FW_STAT_TX_PORT_128B_255B_IX,
2529         FW_STAT_TX_PORT_256B_511B_IX,
2530         FW_STAT_TX_PORT_512B_1023B_IX,
2531         FW_STAT_TX_PORT_1024B_1518B_IX,
2532         FW_STAT_TX_PORT_1519B_MAX_IX,
2533         FW_STAT_TX_PORT_DROP_IX,
2534         FW_STAT_TX_PORT_PAUSE_IX,
2535         FW_STAT_TX_PORT_PPP0_IX,
2536         FW_STAT_TX_PORT_PPP1_IX,
2537         FW_STAT_TX_PORT_PPP2_IX,
2538         FW_STAT_TX_PORT_PPP3_IX,
2539         FW_STAT_TX_PORT_PPP4_IX,
2540         FW_STAT_TX_PORT_PPP5_IX,
2541         FW_STAT_TX_PORT_PPP6_IX,
2542         FW_STAT_TX_PORT_PPP7_IX
2543 };
2544
2545 enum fw_port_stat_rx_index {
2546         FW_STAT_RX_PORT_BYTES_IX,
2547         FW_STAT_RX_PORT_FRAMES_IX,
2548         FW_STAT_RX_PORT_BCAST_IX,
2549         FW_STAT_RX_PORT_MCAST_IX,
2550         FW_STAT_RX_PORT_UCAST_IX,
2551         FW_STAT_RX_PORT_MTU_ERROR_IX,
2552         FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
2553         FW_STAT_RX_PORT_CRC_ERROR_IX,
2554         FW_STAT_RX_PORT_LEN_ERROR_IX,
2555         FW_STAT_RX_PORT_SYM_ERROR_IX,
2556         FW_STAT_RX_PORT_64B_IX,
2557         FW_STAT_RX_PORT_65B_127B_IX,
2558         FW_STAT_RX_PORT_128B_255B_IX,
2559         FW_STAT_RX_PORT_256B_511B_IX,
2560         FW_STAT_RX_PORT_512B_1023B_IX,
2561         FW_STAT_RX_PORT_1024B_1518B_IX,
2562         FW_STAT_RX_PORT_1519B_MAX_IX,
2563         FW_STAT_RX_PORT_PAUSE_IX,
2564         FW_STAT_RX_PORT_PPP0_IX,
2565         FW_STAT_RX_PORT_PPP1_IX,
2566         FW_STAT_RX_PORT_PPP2_IX,
2567         FW_STAT_RX_PORT_PPP3_IX,
2568         FW_STAT_RX_PORT_PPP4_IX,
2569         FW_STAT_RX_PORT_PPP5_IX,
2570         FW_STAT_RX_PORT_PPP6_IX,
2571         FW_STAT_RX_PORT_PPP7_IX,
2572         FW_STAT_RX_PORT_LESS_64B_IX
2573 };
2574
2575 struct fw_port_stats_cmd {
2576         __be32 op_to_portid;
2577         __be32 retval_len16;
2578         union fw_port_stats {
2579                 struct fw_port_stats_ctl {
2580                         u8 nstats_bg_bm;
2581                         u8 tx_ix;
2582                         __be16 r6;
2583                         __be32 r7;
2584                         __be64 stat0;
2585                         __be64 stat1;
2586                         __be64 stat2;
2587                         __be64 stat3;
2588                         __be64 stat4;
2589                         __be64 stat5;
2590                 } ctl;
2591                 struct fw_port_stats_all {
2592                         __be64 tx_bytes;
2593                         __be64 tx_frames;
2594                         __be64 tx_bcast;
2595                         __be64 tx_mcast;
2596                         __be64 tx_ucast;
2597                         __be64 tx_error;
2598                         __be64 tx_64b;
2599                         __be64 tx_65b_127b;
2600                         __be64 tx_128b_255b;
2601                         __be64 tx_256b_511b;
2602                         __be64 tx_512b_1023b;
2603                         __be64 tx_1024b_1518b;
2604                         __be64 tx_1519b_max;
2605                         __be64 tx_drop;
2606                         __be64 tx_pause;
2607                         __be64 tx_ppp0;
2608                         __be64 tx_ppp1;
2609                         __be64 tx_ppp2;
2610                         __be64 tx_ppp3;
2611                         __be64 tx_ppp4;
2612                         __be64 tx_ppp5;
2613                         __be64 tx_ppp6;
2614                         __be64 tx_ppp7;
2615                         __be64 rx_bytes;
2616                         __be64 rx_frames;
2617                         __be64 rx_bcast;
2618                         __be64 rx_mcast;
2619                         __be64 rx_ucast;
2620                         __be64 rx_mtu_error;
2621                         __be64 rx_mtu_crc_error;
2622                         __be64 rx_crc_error;
2623                         __be64 rx_len_error;
2624                         __be64 rx_sym_error;
2625                         __be64 rx_64b;
2626                         __be64 rx_65b_127b;
2627                         __be64 rx_128b_255b;
2628                         __be64 rx_256b_511b;
2629                         __be64 rx_512b_1023b;
2630                         __be64 rx_1024b_1518b;
2631                         __be64 rx_1519b_max;
2632                         __be64 rx_pause;
2633                         __be64 rx_ppp0;
2634                         __be64 rx_ppp1;
2635                         __be64 rx_ppp2;
2636                         __be64 rx_ppp3;
2637                         __be64 rx_ppp4;
2638                         __be64 rx_ppp5;
2639                         __be64 rx_ppp6;
2640                         __be64 rx_ppp7;
2641                         __be64 rx_less_64b;
2642                         __be64 rx_bg_drop;
2643                         __be64 rx_bg_trunc;
2644                 } all;
2645         } u;
2646 };
2647
2648 /* port loopback stats */
2649 #define FW_NUM_LB_STATS 16
2650 enum fw_port_lb_stats_index {
2651         FW_STAT_LB_PORT_BYTES_IX,
2652         FW_STAT_LB_PORT_FRAMES_IX,
2653         FW_STAT_LB_PORT_BCAST_IX,
2654         FW_STAT_LB_PORT_MCAST_IX,
2655         FW_STAT_LB_PORT_UCAST_IX,
2656         FW_STAT_LB_PORT_ERROR_IX,
2657         FW_STAT_LB_PORT_64B_IX,
2658         FW_STAT_LB_PORT_65B_127B_IX,
2659         FW_STAT_LB_PORT_128B_255B_IX,
2660         FW_STAT_LB_PORT_256B_511B_IX,
2661         FW_STAT_LB_PORT_512B_1023B_IX,
2662         FW_STAT_LB_PORT_1024B_1518B_IX,
2663         FW_STAT_LB_PORT_1519B_MAX_IX,
2664         FW_STAT_LB_PORT_DROP_FRAMES_IX
2665 };
2666
2667 struct fw_port_lb_stats_cmd {
2668         __be32 op_to_lbport;
2669         __be32 retval_len16;
2670         union fw_port_lb_stats {
2671                 struct fw_port_lb_stats_ctl {
2672                         u8 nstats_bg_bm;
2673                         u8 ix_pkd;
2674                         __be16 r6;
2675                         __be32 r7;
2676                         __be64 stat0;
2677                         __be64 stat1;
2678                         __be64 stat2;
2679                         __be64 stat3;
2680                         __be64 stat4;
2681                         __be64 stat5;
2682                 } ctl;
2683                 struct fw_port_lb_stats_all {
2684                         __be64 tx_bytes;
2685                         __be64 tx_frames;
2686                         __be64 tx_bcast;
2687                         __be64 tx_mcast;
2688                         __be64 tx_ucast;
2689                         __be64 tx_error;
2690                         __be64 tx_64b;
2691                         __be64 tx_65b_127b;
2692                         __be64 tx_128b_255b;
2693                         __be64 tx_256b_511b;
2694                         __be64 tx_512b_1023b;
2695                         __be64 tx_1024b_1518b;
2696                         __be64 tx_1519b_max;
2697                         __be64 rx_lb_drop;
2698                         __be64 rx_lb_trunc;
2699                 } all;
2700         } u;
2701 };
2702
2703 struct fw_rss_ind_tbl_cmd {
2704         __be32 op_to_viid;
2705         __be32 retval_len16;
2706         __be16 niqid;
2707         __be16 startidx;
2708         __be32 r3;
2709         __be32 iq0_to_iq2;
2710         __be32 iq3_to_iq5;
2711         __be32 iq6_to_iq8;
2712         __be32 iq9_to_iq11;
2713         __be32 iq12_to_iq14;
2714         __be32 iq15_to_iq17;
2715         __be32 iq18_to_iq20;
2716         __be32 iq21_to_iq23;
2717         __be32 iq24_to_iq26;
2718         __be32 iq27_to_iq29;
2719         __be32 iq30_iq31;
2720         __be32 r15_lo;
2721 };
2722
2723 #define FW_RSS_IND_TBL_CMD_VIID_S       0
2724 #define FW_RSS_IND_TBL_CMD_VIID_V(x)    ((x) << FW_RSS_IND_TBL_CMD_VIID_S)
2725
2726 #define FW_RSS_IND_TBL_CMD_IQ0_S        20
2727 #define FW_RSS_IND_TBL_CMD_IQ0_V(x)     ((x) << FW_RSS_IND_TBL_CMD_IQ0_S)
2728
2729 #define FW_RSS_IND_TBL_CMD_IQ1_S        10
2730 #define FW_RSS_IND_TBL_CMD_IQ1_V(x)     ((x) << FW_RSS_IND_TBL_CMD_IQ1_S)
2731
2732 #define FW_RSS_IND_TBL_CMD_IQ2_S        0
2733 #define FW_RSS_IND_TBL_CMD_IQ2_V(x)     ((x) << FW_RSS_IND_TBL_CMD_IQ2_S)
2734
2735 struct fw_rss_glb_config_cmd {
2736         __be32 op_to_write;
2737         __be32 retval_len16;
2738         union fw_rss_glb_config {
2739                 struct fw_rss_glb_config_manual {
2740                         __be32 mode_pkd;
2741                         __be32 r3;
2742                         __be64 r4;
2743                         __be64 r5;
2744                 } manual;
2745                 struct fw_rss_glb_config_basicvirtual {
2746                         __be32 mode_pkd;
2747                         __be32 synmapen_to_hashtoeplitz;
2748                         __be64 r8;
2749                         __be64 r9;
2750                 } basicvirtual;
2751         } u;
2752 };
2753
2754 #define FW_RSS_GLB_CONFIG_CMD_MODE_S    28
2755 #define FW_RSS_GLB_CONFIG_CMD_MODE_M    0xf
2756 #define FW_RSS_GLB_CONFIG_CMD_MODE_V(x) ((x) << FW_RSS_GLB_CONFIG_CMD_MODE_S)
2757 #define FW_RSS_GLB_CONFIG_CMD_MODE_G(x) \
2758         (((x) >> FW_RSS_GLB_CONFIG_CMD_MODE_S) & FW_RSS_GLB_CONFIG_CMD_MODE_M)
2759
2760 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL       0
2761 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
2762
2763 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S        8
2764 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(x)     \
2765         ((x) << FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S)
2766 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F        \
2767         FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(1U)
2768
2769 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S           7
2770 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(x)        \
2771         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S)
2772 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F   \
2773         FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(1U)
2774
2775 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S           6
2776 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(x)        \
2777         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S)
2778 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F   \
2779         FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(1U)
2780
2781 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S           5
2782 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(x)        \
2783         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S)
2784 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F   \
2785         FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(1U)
2786
2787 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S           4
2788 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(x)        \
2789         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S)
2790 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F   \
2791         FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(1U)
2792
2793 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S        3
2794 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(x)     \
2795         ((x) << FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S)
2796 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F        \
2797         FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(1U)
2798
2799 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S        2
2800 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(x)     \
2801         ((x) << FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S)
2802 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F        \
2803         FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(1U)
2804
2805 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S       1
2806 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(x)    \
2807         ((x) << FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S)
2808 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F       \
2809         FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(1U)
2810
2811 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S    0
2812 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(x) \
2813         ((x) << FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S)
2814 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F    \
2815         FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(1U)
2816
2817 struct fw_rss_vi_config_cmd {
2818         __be32 op_to_viid;
2819 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0)
2820         __be32 retval_len16;
2821         union fw_rss_vi_config {
2822                 struct fw_rss_vi_config_manual {
2823                         __be64 r3;
2824                         __be64 r4;
2825                         __be64 r5;
2826                 } manual;
2827                 struct fw_rss_vi_config_basicvirtual {
2828                         __be32 r6;
2829                         __be32 defaultq_to_udpen;
2830                         __be64 r9;
2831                         __be64 r10;
2832                 } basicvirtual;
2833         } u;
2834 };
2835
2836 #define FW_RSS_VI_CONFIG_CMD_VIID_S     0
2837 #define FW_RSS_VI_CONFIG_CMD_VIID_V(x)  ((x) << FW_RSS_VI_CONFIG_CMD_VIID_S)
2838
2839 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S         16
2840 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M         0x3ff
2841 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(x)      \
2842         ((x) << FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S)
2843 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(x)      \
2844         (((x) >> FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) & \
2845          FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M)
2846
2847 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S     4
2848 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(x)  \
2849         ((x) << FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S)
2850 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F     \
2851         FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(1U)
2852
2853 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S      3
2854 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(x)   \
2855         ((x) << FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S)
2856 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F      \
2857         FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(1U)
2858
2859 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S     2
2860 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(x)  \
2861         ((x) << FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S)
2862 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F     \
2863         FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(1U)
2864
2865 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S      1
2866 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(x)   \
2867         ((x) << FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S)
2868 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F      \
2869         FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(1U)
2870
2871 #define FW_RSS_VI_CONFIG_CMD_UDPEN_S    0
2872 #define FW_RSS_VI_CONFIG_CMD_UDPEN_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_UDPEN_S)
2873 #define FW_RSS_VI_CONFIG_CMD_UDPEN_F    FW_RSS_VI_CONFIG_CMD_UDPEN_V(1U)
2874
2875 struct fw_clip_cmd {
2876         __be32 op_to_write;
2877         __be32 alloc_to_len16;
2878         __be64 ip_hi;
2879         __be64 ip_lo;
2880         __be32 r4[2];
2881 };
2882
2883 #define FW_CLIP_CMD_ALLOC_S     31
2884 #define FW_CLIP_CMD_ALLOC_V(x)  ((x) << FW_CLIP_CMD_ALLOC_S)
2885 #define FW_CLIP_CMD_ALLOC_F     FW_CLIP_CMD_ALLOC_V(1U)
2886
2887 #define FW_CLIP_CMD_FREE_S      30
2888 #define FW_CLIP_CMD_FREE_V(x)   ((x) << FW_CLIP_CMD_FREE_S)
2889 #define FW_CLIP_CMD_FREE_F      FW_CLIP_CMD_FREE_V(1U)
2890
2891 enum fw_error_type {
2892         FW_ERROR_TYPE_EXCEPTION         = 0x0,
2893         FW_ERROR_TYPE_HWMODULE          = 0x1,
2894         FW_ERROR_TYPE_WR                = 0x2,
2895         FW_ERROR_TYPE_ACL               = 0x3,
2896 };
2897
2898 struct fw_error_cmd {
2899         __be32 op_to_type;
2900         __be32 len16_pkd;
2901         union fw_error {
2902                 struct fw_error_exception {
2903                         __be32 info[6];
2904                 } exception;
2905                 struct fw_error_hwmodule {
2906                         __be32 regaddr;
2907                         __be32 regval;
2908                 } hwmodule;
2909                 struct fw_error_wr {
2910                         __be16 cidx;
2911                         __be16 pfn_vfn;
2912                         __be32 eqid;
2913                         u8 wrhdr[16];
2914                 } wr;
2915                 struct fw_error_acl {
2916                         __be16 cidx;
2917                         __be16 pfn_vfn;
2918                         __be32 eqid;
2919                         __be16 mv_pkd;
2920                         u8 val[6];
2921                         __be64 r4;
2922                 } acl;
2923         } u;
2924 };
2925
2926 struct fw_debug_cmd {
2927         __be32 op_type;
2928         __be32 len16_pkd;
2929         union fw_debug {
2930                 struct fw_debug_assert {
2931                         __be32 fcid;
2932                         __be32 line;
2933                         __be32 x;
2934                         __be32 y;
2935                         u8 filename_0_7[8];
2936                         u8 filename_8_15[8];
2937                         __be64 r3;
2938                 } assert;
2939                 struct fw_debug_prt {
2940                         __be16 dprtstridx;
2941                         __be16 r3[3];
2942                         __be32 dprtstrparam0;
2943                         __be32 dprtstrparam1;
2944                         __be32 dprtstrparam2;
2945                         __be32 dprtstrparam3;
2946                 } prt;
2947         } u;
2948 };
2949
2950 #define FW_DEBUG_CMD_TYPE_S     0
2951 #define FW_DEBUG_CMD_TYPE_M     0xff
2952 #define FW_DEBUG_CMD_TYPE_G(x)  \
2953         (((x) >> FW_DEBUG_CMD_TYPE_S) & FW_DEBUG_CMD_TYPE_M)
2954
2955 #define PCIE_FW_ERR_S           31
2956 #define PCIE_FW_ERR_V(x)        ((x) << PCIE_FW_ERR_S)
2957 #define PCIE_FW_ERR_F           PCIE_FW_ERR_V(1U)
2958
2959 #define PCIE_FW_INIT_S          30
2960 #define PCIE_FW_INIT_V(x)       ((x) << PCIE_FW_INIT_S)
2961 #define PCIE_FW_INIT_F          PCIE_FW_INIT_V(1U)
2962
2963 #define PCIE_FW_HALT_S          29
2964 #define PCIE_FW_HALT_V(x)       ((x) << PCIE_FW_HALT_S)
2965 #define PCIE_FW_HALT_F          PCIE_FW_HALT_V(1U)
2966
2967 #define PCIE_FW_EVAL_S          24
2968 #define PCIE_FW_EVAL_M          0x7
2969 #define PCIE_FW_EVAL_G(x)       (((x) >> PCIE_FW_EVAL_S) & PCIE_FW_EVAL_M)
2970
2971 #define PCIE_FW_MASTER_VLD_S    15
2972 #define PCIE_FW_MASTER_VLD_V(x) ((x) << PCIE_FW_MASTER_VLD_S)
2973 #define PCIE_FW_MASTER_VLD_F    PCIE_FW_MASTER_VLD_V(1U)
2974
2975 #define PCIE_FW_MASTER_S        12
2976 #define PCIE_FW_MASTER_M        0x7
2977 #define PCIE_FW_MASTER_V(x)     ((x) << PCIE_FW_MASTER_S)
2978 #define PCIE_FW_MASTER_G(x)     (((x) >> PCIE_FW_MASTER_S) & PCIE_FW_MASTER_M)
2979
2980 struct fw_hdr {
2981         u8 ver;
2982         u8 chip;                        /* terminator chip type */
2983         __be16  len512;                 /* bin length in units of 512-bytes */
2984         __be32  fw_ver;                 /* firmware version */
2985         __be32  tp_microcode_ver;
2986         u8 intfver_nic;
2987         u8 intfver_vnic;
2988         u8 intfver_ofld;
2989         u8 intfver_ri;
2990         u8 intfver_iscsipdu;
2991         u8 intfver_iscsi;
2992         u8 intfver_fcoepdu;
2993         u8 intfver_fcoe;
2994         __u32   reserved2;
2995         __u32   reserved3;
2996         __u32   reserved4;
2997         __be32  flags;
2998         __be32  reserved6[23];
2999 };
3000
3001 enum fw_hdr_chip {
3002         FW_HDR_CHIP_T4,
3003         FW_HDR_CHIP_T5
3004 };
3005
3006 #define FW_HDR_FW_VER_MAJOR_S   24
3007 #define FW_HDR_FW_VER_MAJOR_M   0xff
3008 #define FW_HDR_FW_VER_MAJOR_G(x) \
3009         (((x) >> FW_HDR_FW_VER_MAJOR_S) & FW_HDR_FW_VER_MAJOR_M)
3010
3011 #define FW_HDR_FW_VER_MINOR_S   16
3012 #define FW_HDR_FW_VER_MINOR_M   0xff
3013 #define FW_HDR_FW_VER_MINOR_G(x) \
3014         (((x) >> FW_HDR_FW_VER_MINOR_S) & FW_HDR_FW_VER_MINOR_M)
3015
3016 #define FW_HDR_FW_VER_MICRO_S   8
3017 #define FW_HDR_FW_VER_MICRO_M   0xff
3018 #define FW_HDR_FW_VER_MICRO_G(x) \
3019         (((x) >> FW_HDR_FW_VER_MICRO_S) & FW_HDR_FW_VER_MICRO_M)
3020
3021 #define FW_HDR_FW_VER_BUILD_S   0
3022 #define FW_HDR_FW_VER_BUILD_M   0xff
3023 #define FW_HDR_FW_VER_BUILD_G(x) \
3024         (((x) >> FW_HDR_FW_VER_BUILD_S) & FW_HDR_FW_VER_BUILD_M)
3025
3026 enum fw_hdr_intfver {
3027         FW_HDR_INTFVER_NIC      = 0x00,
3028         FW_HDR_INTFVER_VNIC     = 0x00,
3029         FW_HDR_INTFVER_OFLD     = 0x00,
3030         FW_HDR_INTFVER_RI       = 0x00,
3031         FW_HDR_INTFVER_ISCSIPDU = 0x00,
3032         FW_HDR_INTFVER_ISCSI    = 0x00,
3033         FW_HDR_INTFVER_FCOEPDU  = 0x00,
3034         FW_HDR_INTFVER_FCOE     = 0x00,
3035 };
3036
3037 enum fw_hdr_flags {
3038         FW_HDR_FLAGS_RESET_HALT = 0x00000001,
3039 };
3040
3041 #endif /* _T4FW_INTERFACE_H_ */