drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2009-2014 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #ifndef _T4FW_INTERFACE_H_
  36 #define _T4FW_INTERFACE_H_
  37
  38 enum fw_retval {
  39         FW_SUCCESS              = 0,    /* completed successfully */
  40         FW_EPERM                = 1,    /* operation not permitted */
  41         FW_ENOENT               = 2,    /* no such file or directory */
  42         FW_EIO                  = 5,    /* input/output error; hw bad */
  43         FW_ENOEXEC              = 8,    /* exec format error; inv microcode */
  44         FW_EAGAIN               = 11,   /* try again */
  45         FW_ENOMEM               = 12,   /* out of memory */
  46         FW_EFAULT               = 14,   /* bad address; fw bad */
  47         FW_EBUSY                = 16,   /* resource busy */
  48         FW_EEXIST               = 17,   /* file exists */
  49         FW_ENODEV               = 19,   /* no such device */
  50         FW_EINVAL               = 22,   /* invalid argument */
  51         FW_ENOSPC               = 28,   /* no space left on device */
  52         FW_ENOSYS               = 38,   /* functionality not implemented */
  53         FW_ENODATA              = 61,   /* no data available */
  54         FW_EPROTO               = 71,   /* protocol error */
  55         FW_EADDRINUSE           = 98,   /* address already in use */
  56         FW_EADDRNOTAVAIL        = 99,   /* cannot assigned requested address */
  57         FW_ENETDOWN             = 100,  /* network is down */
  58         FW_ENETUNREACH          = 101,  /* network is unreachable */
  59         FW_ENOBUFS              = 105,  /* no buffer space available */
  60         FW_ETIMEDOUT            = 110,  /* timeout */
  61         FW_EINPROGRESS          = 115,  /* fw internal */
  62         FW_SCSI_ABORT_REQUESTED = 128,  /* */
  63         FW_SCSI_ABORT_TIMEDOUT  = 129,  /* */
  64         FW_SCSI_ABORTED         = 130,  /* */
  65         FW_SCSI_CLOSE_REQUESTED = 131,  /* */
  66         FW_ERR_LINK_DOWN        = 132,  /* */
  67         FW_RDEV_NOT_READY       = 133,  /* */
  68         FW_ERR_RDEV_LOST        = 134,  /* */
  69         FW_ERR_RDEV_LOGO        = 135,  /* */
  70         FW_FCOE_NO_XCHG         = 136,  /* */
  71         FW_SCSI_RSP_ERR         = 137,  /* */
  72         FW_ERR_RDEV_IMPL_LOGO   = 138,  /* */
  73         FW_SCSI_UNDER_FLOW_ERR  = 139,  /* */
  74         FW_SCSI_OVER_FLOW_ERR   = 140,  /* */
  75         FW_SCSI_DDP_ERR         = 141,  /* DDP error*/
  76         FW_SCSI_TASK_ERR        = 142,  /* No SCSI tasks available */
  77 };
  78
  79 #define FW_T4VF_SGE_BASE_ADDR      0x0000
  80 #define FW_T4VF_MPS_BASE_ADDR      0x0100
  81 #define FW_T4VF_PL_BASE_ADDR       0x0200
  82 #define FW_T4VF_MBDATA_BASE_ADDR   0x0240
  83 #define FW_T4VF_CIM_BASE_ADDR      0x0300
  84
  85 enum fw_wr_opcodes {
  86         FW_FILTER_WR                   = 0x02,
  87         FW_ULPTX_WR                    = 0x04,
  88         FW_TP_WR                       = 0x05,
  89         FW_ETH_TX_PKT_WR               = 0x08,
  90         FW_OFLD_CONNECTION_WR          = 0x2f,
  91         FW_FLOWC_WR                    = 0x0a,
  92         FW_OFLD_TX_DATA_WR             = 0x0b,
  93         FW_CMD_WR                      = 0x10,
  94         FW_ETH_TX_PKT_VM_WR            = 0x11,
  95         FW_RI_RES_WR                   = 0x0c,
  96         FW_RI_INIT_WR                  = 0x0d,
  97         FW_RI_RDMA_WRITE_WR            = 0x14,
  98         FW_RI_SEND_WR                  = 0x15,
  99         FW_RI_RDMA_READ_WR             = 0x16,
 100         FW_RI_RECV_WR                  = 0x17,
 101         FW_RI_BIND_MW_WR               = 0x18,
 102         FW_RI_FR_NSMR_WR               = 0x19,
 103         FW_RI_FR_NSMR_TPTE_WR          = 0x20,
 104         FW_RI_INV_LSTAG_WR             = 0x1a,
 105         FW_ISCSI_TX_DATA_WR            = 0x45,
 106         FW_CRYPTO_LOOKASIDE_WR         = 0X6d,
 107         FW_LASTC2E_WR                  = 0x70
 108 };
 109
 110 struct fw_wr_hdr {
 111         __be32 hi;
 112         __be32 lo;
 113 };
 114
 115 /* work request opcode (hi) */
 116 #define FW_WR_OP_S      24
 117 #define FW_WR_OP_M      0xff
 118 #define FW_WR_OP_V(x)   ((x) << FW_WR_OP_S)
 119 #define FW_WR_OP_G(x)   (((x) >> FW_WR_OP_S) & FW_WR_OP_M)
 120
 121 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */
 122 #define FW_WR_ATOMIC_S          23
 123 #define FW_WR_ATOMIC_V(x)       ((x) << FW_WR_ATOMIC_S)
 124
 125 /* flush flag (hi) - firmware flushes flushable work request buffered
 126  * in the flow context.
 127  */
 128 #define FW_WR_FLUSH_S     22
 129 #define FW_WR_FLUSH_V(x)  ((x) << FW_WR_FLUSH_S)
 130
 131 /* completion flag (hi) - firmware generates a cpl_fw6_ack */
 132 #define FW_WR_COMPL_S     21
 133 #define FW_WR_COMPL_V(x)  ((x) << FW_WR_COMPL_S)
 134 #define FW_WR_COMPL_F     FW_WR_COMPL_V(1U)
 135
 136 /* work request immediate data length (hi) */
 137 #define FW_WR_IMMDLEN_S 0
 138 #define FW_WR_IMMDLEN_M 0xff
 139 #define FW_WR_IMMDLEN_V(x)      ((x) << FW_WR_IMMDLEN_S)
 140
 141 /* egress queue status update to associated ingress queue entry (lo) */
 142 #define FW_WR_EQUIQ_S           31
 143 #define FW_WR_EQUIQ_V(x)        ((x) << FW_WR_EQUIQ_S)
 144 #define FW_WR_EQUIQ_F           FW_WR_EQUIQ_V(1U)
 145
 146 /* egress queue status update to egress queue status entry (lo) */
 147 #define FW_WR_EQUEQ_S           30
 148 #define FW_WR_EQUEQ_V(x)        ((x) << FW_WR_EQUEQ_S)
 149 #define FW_WR_EQUEQ_F           FW_WR_EQUEQ_V(1U)
 150
 151 /* flow context identifier (lo) */
 152 #define FW_WR_FLOWID_S          8
 153 #define FW_WR_FLOWID_V(x)       ((x) << FW_WR_FLOWID_S)
 154
 155 /* length in units of 16-bytes (lo) */
 156 #define FW_WR_LEN16_S           0
 157 #define FW_WR_LEN16_V(x)        ((x) << FW_WR_LEN16_S)
 158
 159 #define HW_TPL_FR_MT_PR_IV_P_FC         0X32B
 160 #define HW_TPL_FR_MT_PR_OV_P_FC         0X327
 161
 162 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
 163 enum fw_filter_wr_cookie {
 164         FW_FILTER_WR_SUCCESS,
 165         FW_FILTER_WR_FLT_ADDED,
 166         FW_FILTER_WR_FLT_DELETED,
 167         FW_FILTER_WR_SMT_TBL_FULL,
 168         FW_FILTER_WR_EINVAL,
 169 };
 170
 171 struct fw_filter_wr {
 172         __be32 op_pkd;
 173         __be32 len16_pkd;
 174         __be64 r3;
 175         __be32 tid_to_iq;
 176         __be32 del_filter_to_l2tix;
 177         __be16 ethtype;
 178         __be16 ethtypem;
 179         __u8   frag_to_ovlan_vldm;
 180         __u8   smac_sel;
 181         __be16 rx_chan_rx_rpl_iq;
 182         __be32 maci_to_matchtypem;
 183         __u8   ptcl;
 184         __u8   ptclm;
 185         __u8   ttyp;
 186         __u8   ttypm;
 187         __be16 ivlan;
 188         __be16 ivlanm;
 189         __be16 ovlan;
 190         __be16 ovlanm;
 191         __u8   lip[16];
 192         __u8   lipm[16];
 193         __u8   fip[16];
 194         __u8   fipm[16];
 195         __be16 lp;
 196         __be16 lpm;
 197         __be16 fp;
 198         __be16 fpm;
 199         __be16 r7;
 200         __u8   sma[6];
 201 };
 202
 203 #define FW_FILTER_WR_TID_S      12
 204 #define FW_FILTER_WR_TID_M      0xfffff
 205 #define FW_FILTER_WR_TID_V(x)   ((x) << FW_FILTER_WR_TID_S)
 206 #define FW_FILTER_WR_TID_G(x)   \
 207         (((x) >> FW_FILTER_WR_TID_S) & FW_FILTER_WR_TID_M)
 208
 209 #define FW_FILTER_WR_RQTYPE_S           11
 210 #define FW_FILTER_WR_RQTYPE_M           0x1
 211 #define FW_FILTER_WR_RQTYPE_V(x)        ((x) << FW_FILTER_WR_RQTYPE_S)
 212 #define FW_FILTER_WR_RQTYPE_G(x)        \
 213         (((x) >> FW_FILTER_WR_RQTYPE_S) & FW_FILTER_WR_RQTYPE_M)
 214 #define FW_FILTER_WR_RQTYPE_F   FW_FILTER_WR_RQTYPE_V(1U)
 215
 216 #define FW_FILTER_WR_NOREPLY_S          10
 217 #define FW_FILTER_WR_NOREPLY_M          0x1
 218 #define FW_FILTER_WR_NOREPLY_V(x)       ((x) << FW_FILTER_WR_NOREPLY_S)
 219 #define FW_FILTER_WR_NOREPLY_G(x)       \
 220         (((x) >> FW_FILTER_WR_NOREPLY_S) & FW_FILTER_WR_NOREPLY_M)
 221 #define FW_FILTER_WR_NOREPLY_F  FW_FILTER_WR_NOREPLY_V(1U)
 222
 223 #define FW_FILTER_WR_IQ_S       0
 224 #define FW_FILTER_WR_IQ_M       0x3ff
 225 #define FW_FILTER_WR_IQ_V(x)    ((x) << FW_FILTER_WR_IQ_S)
 226 #define FW_FILTER_WR_IQ_G(x)    \
 227         (((x) >> FW_FILTER_WR_IQ_S) & FW_FILTER_WR_IQ_M)
 228
 229 #define FW_FILTER_WR_DEL_FILTER_S       31
 230 #define FW_FILTER_WR_DEL_FILTER_M       0x1
 231 #define FW_FILTER_WR_DEL_FILTER_V(x)    ((x) << FW_FILTER_WR_DEL_FILTER_S)
 232 #define FW_FILTER_WR_DEL_FILTER_G(x)    \
 233         (((x) >> FW_FILTER_WR_DEL_FILTER_S) & FW_FILTER_WR_DEL_FILTER_M)
 234 #define FW_FILTER_WR_DEL_FILTER_F       FW_FILTER_WR_DEL_FILTER_V(1U)
 235
 236 #define FW_FILTER_WR_RPTTID_S           25
 237 #define FW_FILTER_WR_RPTTID_M           0x1
 238 #define FW_FILTER_WR_RPTTID_V(x)        ((x) << FW_FILTER_WR_RPTTID_S)
 239 #define FW_FILTER_WR_RPTTID_G(x)        \
 240         (((x) >> FW_FILTER_WR_RPTTID_S) & FW_FILTER_WR_RPTTID_M)
 241 #define FW_FILTER_WR_RPTTID_F   FW_FILTER_WR_RPTTID_V(1U)
 242
 243 #define FW_FILTER_WR_DROP_S     24
 244 #define FW_FILTER_WR_DROP_M     0x1
 245 #define FW_FILTER_WR_DROP_V(x)  ((x) << FW_FILTER_WR_DROP_S)
 246 #define FW_FILTER_WR_DROP_G(x)  \
 247         (((x) >> FW_FILTER_WR_DROP_S) & FW_FILTER_WR_DROP_M)
 248 #define FW_FILTER_WR_DROP_F     FW_FILTER_WR_DROP_V(1U)
 249
 250 #define FW_FILTER_WR_DIRSTEER_S         23
 251 #define FW_FILTER_WR_DIRSTEER_M         0x1
 252 #define FW_FILTER_WR_DIRSTEER_V(x)      ((x) << FW_FILTER_WR_DIRSTEER_S)
 253 #define FW_FILTER_WR_DIRSTEER_G(x)      \
 254         (((x) >> FW_FILTER_WR_DIRSTEER_S) & FW_FILTER_WR_DIRSTEER_M)
 255 #define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1U)
 256
 257 #define FW_FILTER_WR_MASKHASH_S         22
 258 #define FW_FILTER_WR_MASKHASH_M         0x1
 259 #define FW_FILTER_WR_MASKHASH_V(x)      ((x) << FW_FILTER_WR_MASKHASH_S)
 260 #define FW_FILTER_WR_MASKHASH_G(x)      \
 261         (((x) >> FW_FILTER_WR_MASKHASH_S) & FW_FILTER_WR_MASKHASH_M)
 262 #define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1U)
 263
 264 #define FW_FILTER_WR_DIRSTEERHASH_S     21
 265 #define FW_FILTER_WR_DIRSTEERHASH_M     0x1
 266 #define FW_FILTER_WR_DIRSTEERHASH_V(x)  ((x) << FW_FILTER_WR_DIRSTEERHASH_S)
 267 #define FW_FILTER_WR_DIRSTEERHASH_G(x)  \
 268         (((x) >> FW_FILTER_WR_DIRSTEERHASH_S) & FW_FILTER_WR_DIRSTEERHASH_M)
 269 #define FW_FILTER_WR_DIRSTEERHASH_F     FW_FILTER_WR_DIRSTEERHASH_V(1U)
 270
 271 #define FW_FILTER_WR_LPBK_S     20
 272 #define FW_FILTER_WR_LPBK_M     0x1
 273 #define FW_FILTER_WR_LPBK_V(x)  ((x) << FW_FILTER_WR_LPBK_S)
 274 #define FW_FILTER_WR_LPBK_G(x)  \
 275         (((x) >> FW_FILTER_WR_LPBK_S) & FW_FILTER_WR_LPBK_M)
 276 #define FW_FILTER_WR_LPBK_F     FW_FILTER_WR_LPBK_V(1U)
 277
 278 #define FW_FILTER_WR_DMAC_S     19
 279 #define FW_FILTER_WR_DMAC_M     0x1
 280 #define FW_FILTER_WR_DMAC_V(x)  ((x) << FW_FILTER_WR_DMAC_S)
 281 #define FW_FILTER_WR_DMAC_G(x)  \
 282         (((x) >> FW_FILTER_WR_DMAC_S) & FW_FILTER_WR_DMAC_M)
 283 #define FW_FILTER_WR_DMAC_F     FW_FILTER_WR_DMAC_V(1U)
 284
 285 #define FW_FILTER_WR_SMAC_S     18
 286 #define FW_FILTER_WR_SMAC_M     0x1
 287 #define FW_FILTER_WR_SMAC_V(x)  ((x) << FW_FILTER_WR_SMAC_S)
 288 #define FW_FILTER_WR_SMAC_G(x)  \
 289         (((x) >> FW_FILTER_WR_SMAC_S) & FW_FILTER_WR_SMAC_M)
 290 #define FW_FILTER_WR_SMAC_F     FW_FILTER_WR_SMAC_V(1U)
 291
 292 #define FW_FILTER_WR_INSVLAN_S          17
 293 #define FW_FILTER_WR_INSVLAN_M          0x1
 294 #define FW_FILTER_WR_INSVLAN_V(x)       ((x) << FW_FILTER_WR_INSVLAN_S)
 295 #define FW_FILTER_WR_INSVLAN_G(x)       \
 296         (((x) >> FW_FILTER_WR_INSVLAN_S) & FW_FILTER_WR_INSVLAN_M)
 297 #define FW_FILTER_WR_INSVLAN_F  FW_FILTER_WR_INSVLAN_V(1U)
 298
 299 #define FW_FILTER_WR_RMVLAN_S           16
 300 #define FW_FILTER_WR_RMVLAN_M           0x1
 301 #define FW_FILTER_WR_RMVLAN_V(x)        ((x) << FW_FILTER_WR_RMVLAN_S)
 302 #define FW_FILTER_WR_RMVLAN_G(x)        \
 303         (((x) >> FW_FILTER_WR_RMVLAN_S) & FW_FILTER_WR_RMVLAN_M)
 304 #define FW_FILTER_WR_RMVLAN_F   FW_FILTER_WR_RMVLAN_V(1U)
 305
 306 #define FW_FILTER_WR_HITCNTS_S          15
 307 #define FW_FILTER_WR_HITCNTS_M          0x1
 308 #define FW_FILTER_WR_HITCNTS_V(x)       ((x) << FW_FILTER_WR_HITCNTS_S)
 309 #define FW_FILTER_WR_HITCNTS_G(x)       \
 310         (((x) >> FW_FILTER_WR_HITCNTS_S) & FW_FILTER_WR_HITCNTS_M)
 311 #define FW_FILTER_WR_HITCNTS_F  FW_FILTER_WR_HITCNTS_V(1U)
 312
 313 #define FW_FILTER_WR_TXCHAN_S           13
 314 #define FW_FILTER_WR_TXCHAN_M           0x3
 315 #define FW_FILTER_WR_TXCHAN_V(x)        ((x) << FW_FILTER_WR_TXCHAN_S)
 316 #define FW_FILTER_WR_TXCHAN_G(x)        \
 317         (((x) >> FW_FILTER_WR_TXCHAN_S) & FW_FILTER_WR_TXCHAN_M)
 318
 319 #define FW_FILTER_WR_PRIO_S     12
 320 #define FW_FILTER_WR_PRIO_M     0x1
 321 #define FW_FILTER_WR_PRIO_V(x)  ((x) << FW_FILTER_WR_PRIO_S)
 322 #define FW_FILTER_WR_PRIO_G(x)  \
 323         (((x) >> FW_FILTER_WR_PRIO_S) & FW_FILTER_WR_PRIO_M)
 324 #define FW_FILTER_WR_PRIO_F     FW_FILTER_WR_PRIO_V(1U)
 325
 326 #define FW_FILTER_WR_L2TIX_S    0
 327 #define FW_FILTER_WR_L2TIX_M    0xfff
 328 #define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S)
 329 #define FW_FILTER_WR_L2TIX_G(x) \
 330         (((x) >> FW_FILTER_WR_L2TIX_S) & FW_FILTER_WR_L2TIX_M)
 331
 332 #define FW_FILTER_WR_FRAG_S     7
 333 #define FW_FILTER_WR_FRAG_M     0x1
 334 #define FW_FILTER_WR_FRAG_V(x)  ((x) << FW_FILTER_WR_FRAG_S)
 335 #define FW_FILTER_WR_FRAG_G(x)  \
 336         (((x) >> FW_FILTER_WR_FRAG_S) & FW_FILTER_WR_FRAG_M)
 337 #define FW_FILTER_WR_FRAG_F     FW_FILTER_WR_FRAG_V(1U)
 338
 339 #define FW_FILTER_WR_FRAGM_S    6
 340 #define FW_FILTER_WR_FRAGM_M    0x1
 341 #define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S)
 342 #define FW_FILTER_WR_FRAGM_G(x) \
 343         (((x) >> FW_FILTER_WR_FRAGM_S) & FW_FILTER_WR_FRAGM_M)
 344 #define FW_FILTER_WR_FRAGM_F    FW_FILTER_WR_FRAGM_V(1U)
 345
 346 #define FW_FILTER_WR_IVLAN_VLD_S        5
 347 #define FW_FILTER_WR_IVLAN_VLD_M        0x1
 348 #define FW_FILTER_WR_IVLAN_VLD_V(x)     ((x) << FW_FILTER_WR_IVLAN_VLD_S)
 349 #define FW_FILTER_WR_IVLAN_VLD_G(x)     \
 350         (((x) >> FW_FILTER_WR_IVLAN_VLD_S) & FW_FILTER_WR_IVLAN_VLD_M)
 351 #define FW_FILTER_WR_IVLAN_VLD_F        FW_FILTER_WR_IVLAN_VLD_V(1U)
 352
 353 #define FW_FILTER_WR_OVLAN_VLD_S        4
 354 #define FW_FILTER_WR_OVLAN_VLD_M        0x1
 355 #define FW_FILTER_WR_OVLAN_VLD_V(x)     ((x) << FW_FILTER_WR_OVLAN_VLD_S)
 356 #define FW_FILTER_WR_OVLAN_VLD_G(x)     \
 357         (((x) >> FW_FILTER_WR_OVLAN_VLD_S) & FW_FILTER_WR_OVLAN_VLD_M)
 358 #define FW_FILTER_WR_OVLAN_VLD_F        FW_FILTER_WR_OVLAN_VLD_V(1U)
 359
 360 #define FW_FILTER_WR_IVLAN_VLDM_S       3
 361 #define FW_FILTER_WR_IVLAN_VLDM_M       0x1
 362 #define FW_FILTER_WR_IVLAN_VLDM_V(x)    ((x) << FW_FILTER_WR_IVLAN_VLDM_S)
 363 #define FW_FILTER_WR_IVLAN_VLDM_G(x)    \
 364         (((x) >> FW_FILTER_WR_IVLAN_VLDM_S) & FW_FILTER_WR_IVLAN_VLDM_M)
 365 #define FW_FILTER_WR_IVLAN_VLDM_F       FW_FILTER_WR_IVLAN_VLDM_V(1U)
 366
 367 #define FW_FILTER_WR_OVLAN_VLDM_S       2
 368 #define FW_FILTER_WR_OVLAN_VLDM_M       0x1
 369 #define FW_FILTER_WR_OVLAN_VLDM_V(x)    ((x) << FW_FILTER_WR_OVLAN_VLDM_S)
 370 #define FW_FILTER_WR_OVLAN_VLDM_G(x)    \
 371         (((x) >> FW_FILTER_WR_OVLAN_VLDM_S) & FW_FILTER_WR_OVLAN_VLDM_M)
 372 #define FW_FILTER_WR_OVLAN_VLDM_F       FW_FILTER_WR_OVLAN_VLDM_V(1U)
 373
 374 #define FW_FILTER_WR_RX_CHAN_S          15
 375 #define FW_FILTER_WR_RX_CHAN_M          0x1
 376 #define FW_FILTER_WR_RX_CHAN_V(x)       ((x) << FW_FILTER_WR_RX_CHAN_S)
 377 #define FW_FILTER_WR_RX_CHAN_G(x)       \
 378         (((x) >> FW_FILTER_WR_RX_CHAN_S) & FW_FILTER_WR_RX_CHAN_M)
 379 #define FW_FILTER_WR_RX_CHAN_F  FW_FILTER_WR_RX_CHAN_V(1U)
 380
 381 #define FW_FILTER_WR_RX_RPL_IQ_S        0
 382 #define FW_FILTER_WR_RX_RPL_IQ_M        0x3ff
 383 #define FW_FILTER_WR_RX_RPL_IQ_V(x)     ((x) << FW_FILTER_WR_RX_RPL_IQ_S)
 384 #define FW_FILTER_WR_RX_RPL_IQ_G(x)     \
 385         (((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M)
 386
 387 #define FW_FILTER_WR_MACI_S     23
 388 #define FW_FILTER_WR_MACI_M     0x1ff
 389 #define FW_FILTER_WR_MACI_V(x)  ((x) << FW_FILTER_WR_MACI_S)
 390 #define FW_FILTER_WR_MACI_G(x)  \
 391         (((x) >> FW_FILTER_WR_MACI_S) & FW_FILTER_WR_MACI_M)
 392
 393 #define FW_FILTER_WR_MACIM_S    14
 394 #define FW_FILTER_WR_MACIM_M    0x1ff
 395 #define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S)
 396 #define FW_FILTER_WR_MACIM_G(x) \
 397         (((x) >> FW_FILTER_WR_MACIM_S) & FW_FILTER_WR_MACIM_M)
 398
 399 #define FW_FILTER_WR_FCOE_S     13
 400 #define FW_FILTER_WR_FCOE_M     0x1
 401 #define FW_FILTER_WR_FCOE_V(x)  ((x) << FW_FILTER_WR_FCOE_S)
 402 #define FW_FILTER_WR_FCOE_G(x)  \
 403         (((x) >> FW_FILTER_WR_FCOE_S) & FW_FILTER_WR_FCOE_M)
 404 #define FW_FILTER_WR_FCOE_F     FW_FILTER_WR_FCOE_V(1U)
 405
 406 #define FW_FILTER_WR_FCOEM_S    12
 407 #define FW_FILTER_WR_FCOEM_M    0x1
 408 #define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S)
 409 #define FW_FILTER_WR_FCOEM_G(x) \
 410         (((x) >> FW_FILTER_WR_FCOEM_S) & FW_FILTER_WR_FCOEM_M)
 411 #define FW_FILTER_WR_FCOEM_F    FW_FILTER_WR_FCOEM_V(1U)
 412
 413 #define FW_FILTER_WR_PORT_S     9
 414 #define FW_FILTER_WR_PORT_M     0x7
 415 #define FW_FILTER_WR_PORT_V(x)  ((x) << FW_FILTER_WR_PORT_S)
 416 #define FW_FILTER_WR_PORT_G(x)  \
 417         (((x) >> FW_FILTER_WR_PORT_S) & FW_FILTER_WR_PORT_M)
 418
 419 #define FW_FILTER_WR_PORTM_S    6
 420 #define FW_FILTER_WR_PORTM_M    0x7
 421 #define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S)
 422 #define FW_FILTER_WR_PORTM_G(x) \
 423         (((x) >> FW_FILTER_WR_PORTM_S) & FW_FILTER_WR_PORTM_M)
 424
 425 #define FW_FILTER_WR_MATCHTYPE_S        3
 426 #define FW_FILTER_WR_MATCHTYPE_M        0x7
 427 #define FW_FILTER_WR_MATCHTYPE_V(x)     ((x) << FW_FILTER_WR_MATCHTYPE_S)
 428 #define FW_FILTER_WR_MATCHTYPE_G(x)     \
 429         (((x) >> FW_FILTER_WR_MATCHTYPE_S) & FW_FILTER_WR_MATCHTYPE_M)
 430
 431 #define FW_FILTER_WR_MATCHTYPEM_S       0
 432 #define FW_FILTER_WR_MATCHTYPEM_M       0x7
 433 #define FW_FILTER_WR_MATCHTYPEM_V(x)    ((x) << FW_FILTER_WR_MATCHTYPEM_S)
 434 #define FW_FILTER_WR_MATCHTYPEM_G(x)    \
 435         (((x) >> FW_FILTER_WR_MATCHTYPEM_S) & FW_FILTER_WR_MATCHTYPEM_M)
 436
 437 struct fw_ulptx_wr {
 438         __be32 op_to_compl;
 439         __be32 flowid_len16;
 440         u64 cookie;
 441 };
 442
 443 struct fw_tp_wr {
 444         __be32 op_to_immdlen;
 445         __be32 flowid_len16;
 446         u64 cookie;
 447 };
 448
 449 struct fw_eth_tx_pkt_wr {
 450         __be32 op_immdlen;
 451         __be32 equiq_to_len16;
 452         __be64 r3;
 453 };
 454
 455 struct fw_ofld_connection_wr {
 456         __be32 op_compl;
 457         __be32 len16_pkd;
 458         __u64  cookie;
 459         __be64 r2;
 460         __be64 r3;
 461         struct fw_ofld_connection_le {
 462                 __be32 version_cpl;
 463                 __be32 filter;
 464                 __be32 r1;
 465                 __be16 lport;
 466                 __be16 pport;
 467                 union fw_ofld_connection_leip {
 468                         struct fw_ofld_connection_le_ipv4 {
 469                                 __be32 pip;
 470                                 __be32 lip;
 471                                 __be64 r0;
 472                                 __be64 r1;
 473                                 __be64 r2;
 474                         } ipv4;
 475                         struct fw_ofld_connection_le_ipv6 {
 476                                 __be64 pip_hi;
 477                                 __be64 pip_lo;
 478                                 __be64 lip_hi;
 479                                 __be64 lip_lo;
 480                         } ipv6;
 481                 } u;
 482         } le;
 483         struct fw_ofld_connection_tcb {
 484                 __be32 t_state_to_astid;
 485                 __be16 cplrxdataack_cplpassacceptrpl;
 486                 __be16 rcv_adv;
 487                 __be32 rcv_nxt;
 488                 __be32 tx_max;
 489                 __be64 opt0;
 490                 __be32 opt2;
 491                 __be32 r1;
 492                 __be64 r2;
 493                 __be64 r3;
 494         } tcb;
 495 };
 496
 497 #define FW_OFLD_CONNECTION_WR_VERSION_S                31
 498 #define FW_OFLD_CONNECTION_WR_VERSION_M                0x1
 499 #define FW_OFLD_CONNECTION_WR_VERSION_V(x)     \
 500         ((x) << FW_OFLD_CONNECTION_WR_VERSION_S)
 501 #define FW_OFLD_CONNECTION_WR_VERSION_G(x)     \
 502         (((x) >> FW_OFLD_CONNECTION_WR_VERSION_S) & \
 503         FW_OFLD_CONNECTION_WR_VERSION_M)
 504 #define FW_OFLD_CONNECTION_WR_VERSION_F        \
 505         FW_OFLD_CONNECTION_WR_VERSION_V(1U)
 506
 507 #define FW_OFLD_CONNECTION_WR_CPL_S    30
 508 #define FW_OFLD_CONNECTION_WR_CPL_M    0x1
 509 #define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S)
 510 #define FW_OFLD_CONNECTION_WR_CPL_G(x) \
 511         (((x) >> FW_OFLD_CONNECTION_WR_CPL_S) & FW_OFLD_CONNECTION_WR_CPL_M)
 512 #define FW_OFLD_CONNECTION_WR_CPL_F    FW_OFLD_CONNECTION_WR_CPL_V(1U)
 513
 514 #define FW_OFLD_CONNECTION_WR_T_STATE_S                28
 515 #define FW_OFLD_CONNECTION_WR_T_STATE_M                0xf
 516 #define FW_OFLD_CONNECTION_WR_T_STATE_V(x)     \
 517         ((x) << FW_OFLD_CONNECTION_WR_T_STATE_S)
 518 #define FW_OFLD_CONNECTION_WR_T_STATE_G(x)     \
 519         (((x) >> FW_OFLD_CONNECTION_WR_T_STATE_S) & \
 520         FW_OFLD_CONNECTION_WR_T_STATE_M)
 521
 522 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_S      24
 523 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_M      0xf
 524 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x)   \
 525         ((x) << FW_OFLD_CONNECTION_WR_RCV_SCALE_S)
 526 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x)   \
 527         (((x) >> FW_OFLD_CONNECTION_WR_RCV_SCALE_S) & \
 528         FW_OFLD_CONNECTION_WR_RCV_SCALE_M)
 529
 530 #define FW_OFLD_CONNECTION_WR_ASTID_S          0
 531 #define FW_OFLD_CONNECTION_WR_ASTID_M          0xffffff
 532 #define FW_OFLD_CONNECTION_WR_ASTID_V(x)       \
 533         ((x) << FW_OFLD_CONNECTION_WR_ASTID_S)
 534 #define FW_OFLD_CONNECTION_WR_ASTID_G(x)       \
 535         (((x) >> FW_OFLD_CONNECTION_WR_ASTID_S) & FW_OFLD_CONNECTION_WR_ASTID_M)
 536
 537 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S   15
 538 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M   0x1
 539 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x)        \
 540         ((x) << FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S)
 541 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x)        \
 542         (((x) >> FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) & \
 543         FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M)
 544 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F   \
 545         FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(1U)
 546
 547 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S       14
 548 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M       0x1
 549 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x)    \
 550         ((x) << FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S)
 551 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x)    \
 552         (((x) >> FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) & \
 553         FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M)
 554 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F       \
 555         FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(1U)
 556
 557 enum fw_flowc_mnem {
 558         FW_FLOWC_MNEM_PFNVFN,           /* PFN [15:8] VFN [7:0] */
 559         FW_FLOWC_MNEM_CH,
 560         FW_FLOWC_MNEM_PORT,
 561         FW_FLOWC_MNEM_IQID,
 562         FW_FLOWC_MNEM_SNDNXT,
 563         FW_FLOWC_MNEM_RCVNXT,
 564         FW_FLOWC_MNEM_SNDBUF,
 565         FW_FLOWC_MNEM_MSS,
 566         FW_FLOWC_MNEM_TXDATAPLEN_MAX,
 567         FW_FLOWC_MNEM_TCPSTATE,
 568         FW_FLOWC_MNEM_EOSTATE,
 569         FW_FLOWC_MNEM_SCHEDCLASS,
 570         FW_FLOWC_MNEM_DCBPRIO,
 571         FW_FLOWC_MNEM_SND_SCALE,
 572         FW_FLOWC_MNEM_RCV_SCALE,
 573 };
 574
 575 struct fw_flowc_mnemval {
 576         u8 mnemonic;
 577         u8 r4[3];
 578         __be32 val;
 579 };
 580
 581 struct fw_flowc_wr {
 582         __be32 op_to_nparams;
 583         __be32 flowid_len16;
 584         struct fw_flowc_mnemval mnemval[0];
 585 };
 586
 587 #define FW_FLOWC_WR_NPARAMS_S           0
 588 #define FW_FLOWC_WR_NPARAMS_V(x)        ((x) << FW_FLOWC_WR_NPARAMS_S)
 589
 590 struct fw_ofld_tx_data_wr {
 591         __be32 op_to_immdlen;
 592         __be32 flowid_len16;
 593         __be32 plen;
 594         __be32 tunnel_to_proxy;
 595 };
 596
 597 #define FW_OFLD_TX_DATA_WR_TUNNEL_S     19
 598 #define FW_OFLD_TX_DATA_WR_TUNNEL_V(x)  ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S)
 599
 600 #define FW_OFLD_TX_DATA_WR_SAVE_S       18
 601 #define FW_OFLD_TX_DATA_WR_SAVE_V(x)    ((x) << FW_OFLD_TX_DATA_WR_SAVE_S)
 602
 603 #define FW_OFLD_TX_DATA_WR_FLUSH_S      17
 604 #define FW_OFLD_TX_DATA_WR_FLUSH_V(x)   ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S)
 605 #define FW_OFLD_TX_DATA_WR_FLUSH_F      FW_OFLD_TX_DATA_WR_FLUSH_V(1U)
 606
 607 #define FW_OFLD_TX_DATA_WR_URGENT_S     16
 608 #define FW_OFLD_TX_DATA_WR_URGENT_V(x)  ((x) << FW_OFLD_TX_DATA_WR_URGENT_S)
 609
 610 #define FW_OFLD_TX_DATA_WR_MORE_S       15
 611 #define FW_OFLD_TX_DATA_WR_MORE_V(x)    ((x) << FW_OFLD_TX_DATA_WR_MORE_S)
 612
 613 #define FW_OFLD_TX_DATA_WR_SHOVE_S      14
 614 #define FW_OFLD_TX_DATA_WR_SHOVE_V(x)   ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S)
 615 #define FW_OFLD_TX_DATA_WR_SHOVE_F      FW_OFLD_TX_DATA_WR_SHOVE_V(1U)
 616
 617 #define FW_OFLD_TX_DATA_WR_ULPMODE_S    10
 618 #define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S)
 619
 620 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S         6
 621 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x)      \
 622         ((x) << FW_OFLD_TX_DATA_WR_ULPSUBMODE_S)
 623
 624 struct fw_cmd_wr {
 625         __be32 op_dma;
 626         __be32 len16_pkd;
 627         __be64 cookie_daddr;
 628 };
 629
 630 #define FW_CMD_WR_DMA_S         17
 631 #define FW_CMD_WR_DMA_V(x)      ((x) << FW_CMD_WR_DMA_S)
 632
 633 struct fw_eth_tx_pkt_vm_wr {
 634         __be32 op_immdlen;
 635         __be32 equiq_to_len16;
 636         __be32 r3[2];
 637         u8 ethmacdst[6];
 638         u8 ethmacsrc[6];
 639         __be16 ethtype;
 640         __be16 vlantci;
 641 };
 642
 643 #define FW_CMD_MAX_TIMEOUT 10000
 644
 645 /*
 646  * If a host driver does a HELLO and discovers that there's already a MASTER
 647  * selected, we may have to wait for that MASTER to finish issuing RESET,
 648  * configuration and INITIALIZE commands.  Also, there's a possibility that
 649  * our own HELLO may get lost if it happens right as the MASTER is issuign a
 650  * RESET command, so we need to be willing to make a few retries of our HELLO.
 651  */
 652 #define FW_CMD_HELLO_TIMEOUT    (3 * FW_CMD_MAX_TIMEOUT)
 653 #define FW_CMD_HELLO_RETRIES    3
 654
 655
 656 enum fw_cmd_opcodes {
 657         FW_LDST_CMD                    = 0x01,
 658         FW_RESET_CMD                   = 0x03,
 659         FW_HELLO_CMD                   = 0x04,
 660         FW_BYE_CMD                     = 0x05,
 661         FW_INITIALIZE_CMD              = 0x06,
 662         FW_CAPS_CONFIG_CMD             = 0x07,
 663         FW_PARAMS_CMD                  = 0x08,
 664         FW_PFVF_CMD                    = 0x09,
 665         FW_IQ_CMD                      = 0x10,
 666         FW_EQ_MNGT_CMD                 = 0x11,
 667         FW_EQ_ETH_CMD                  = 0x12,
 668         FW_EQ_CTRL_CMD                 = 0x13,
 669         FW_EQ_OFLD_CMD                 = 0x21,
 670         FW_VI_CMD                      = 0x14,
 671         FW_VI_MAC_CMD                  = 0x15,
 672         FW_VI_RXMODE_CMD               = 0x16,
 673         FW_VI_ENABLE_CMD               = 0x17,
 674         FW_ACL_MAC_CMD                 = 0x18,
 675         FW_ACL_VLAN_CMD                = 0x19,
 676         FW_VI_STATS_CMD                = 0x1a,
 677         FW_PORT_CMD                    = 0x1b,
 678         FW_PORT_STATS_CMD              = 0x1c,
 679         FW_PORT_LB_STATS_CMD           = 0x1d,
 680         FW_PORT_TRACE_CMD              = 0x1e,
 681         FW_PORT_TRACE_MMAP_CMD         = 0x1f,
 682         FW_RSS_IND_TBL_CMD             = 0x20,
 683         FW_RSS_GLB_CONFIG_CMD          = 0x22,
 684         FW_RSS_VI_CONFIG_CMD           = 0x23,
 685         FW_DEVLOG_CMD                  = 0x25,
 686         FW_CLIP_CMD                    = 0x28,
 687         FW_LASTC2E_CMD                 = 0x40,
 688         FW_ERROR_CMD                   = 0x80,
 689         FW_DEBUG_CMD                   = 0x81,
 690 };
 691
 692 enum fw_cmd_cap {
 693         FW_CMD_CAP_PF                  = 0x01,
 694         FW_CMD_CAP_DMAQ                = 0x02,
 695         FW_CMD_CAP_PORT                = 0x04,
 696         FW_CMD_CAP_PORTPROMISC         = 0x08,
 697         FW_CMD_CAP_PORTSTATS           = 0x10,
 698         FW_CMD_CAP_VF                  = 0x80,
 699 };
 700
 701 /*
 702  * Generic command header flit0
 703  */
 704 struct fw_cmd_hdr {
 705         __be32 hi;
 706         __be32 lo;
 707 };
 708
 709 #define FW_CMD_OP_S             24
 710 #define FW_CMD_OP_M             0xff
 711 #define FW_CMD_OP_V(x)          ((x) << FW_CMD_OP_S)
 712 #define FW_CMD_OP_G(x)          (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M)
 713
 714 #define FW_CMD_REQUEST_S        23
 715 #define FW_CMD_REQUEST_V(x)     ((x) << FW_CMD_REQUEST_S)
 716 #define FW_CMD_REQUEST_F        FW_CMD_REQUEST_V(1U)
 717
 718 #define FW_CMD_READ_S           22
 719 #define FW_CMD_READ_V(x)        ((x) << FW_CMD_READ_S)
 720 #define FW_CMD_READ_F           FW_CMD_READ_V(1U)
 721
 722 #define FW_CMD_WRITE_S          21
 723 #define FW_CMD_WRITE_V(x)       ((x) << FW_CMD_WRITE_S)
 724 #define FW_CMD_WRITE_F          FW_CMD_WRITE_V(1U)
 725
 726 #define FW_CMD_EXEC_S           20
 727 #define FW_CMD_EXEC_V(x)        ((x) << FW_CMD_EXEC_S)
 728 #define FW_CMD_EXEC_F           FW_CMD_EXEC_V(1U)
 729
 730 #define FW_CMD_RAMASK_S         20
 731 #define FW_CMD_RAMASK_V(x)      ((x) << FW_CMD_RAMASK_S)
 732
 733 #define FW_CMD_RETVAL_S         8
 734 #define FW_CMD_RETVAL_M         0xff
 735 #define FW_CMD_RETVAL_V(x)      ((x) << FW_CMD_RETVAL_S)
 736 #define FW_CMD_RETVAL_G(x)      (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M)
 737
 738 #define FW_CMD_LEN16_S          0
 739 #define FW_CMD_LEN16_V(x)       ((x) << FW_CMD_LEN16_S)
 740
 741 #define FW_LEN16(fw_struct)     FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
 742
 743 enum fw_ldst_addrspc {
 744         FW_LDST_ADDRSPC_FIRMWARE  = 0x0001,
 745         FW_LDST_ADDRSPC_SGE_EGRC  = 0x0008,
 746         FW_LDST_ADDRSPC_SGE_INGC  = 0x0009,
 747         FW_LDST_ADDRSPC_SGE_FLMC  = 0x000a,
 748         FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
 749         FW_LDST_ADDRSPC_TP_PIO    = 0x0010,
 750         FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
 751         FW_LDST_ADDRSPC_TP_MIB    = 0x0012,
 752         FW_LDST_ADDRSPC_MDIO      = 0x0018,
 753         FW_LDST_ADDRSPC_MPS       = 0x0020,
 754         FW_LDST_ADDRSPC_FUNC      = 0x0028,
 755         FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
 756 };
 757
 758 enum fw_ldst_mps_fid {
 759         FW_LDST_MPS_ATRB,
 760         FW_LDST_MPS_RPLC
 761 };
 762
 763 enum fw_ldst_func_access_ctl {
 764         FW_LDST_FUNC_ACC_CTL_VIID,
 765         FW_LDST_FUNC_ACC_CTL_FID
 766 };
 767
 768 enum fw_ldst_func_mod_index {
 769         FW_LDST_FUNC_MPS
 770 };
 771
 772 struct fw_ldst_cmd {
 773         __be32 op_to_addrspace;
 774         __be32 cycles_to_len16;
 775         union fw_ldst {
 776                 struct fw_ldst_addrval {
 777                         __be32 addr;
 778                         __be32 val;
 779                 } addrval;
 780                 struct fw_ldst_idctxt {
 781                         __be32 physid;
 782                         __be32 msg_ctxtflush;
 783                         __be32 ctxt_data7;
 784                         __be32 ctxt_data6;
 785                         __be32 ctxt_data5;
 786                         __be32 ctxt_data4;
 787                         __be32 ctxt_data3;
 788                         __be32 ctxt_data2;
 789                         __be32 ctxt_data1;
 790                         __be32 ctxt_data0;
 791                 } idctxt;
 792                 struct fw_ldst_mdio {
 793                         __be16 paddr_mmd;
 794                         __be16 raddr;
 795                         __be16 vctl;
 796                         __be16 rval;
 797                 } mdio;
 798                 struct fw_ldst_cim_rq {
 799                         u8 req_first64[8];
 800                         u8 req_second64[8];
 801                         u8 resp_first64[8];
 802                         u8 resp_second64[8];
 803                         __be32 r3[2];
 804                 } cim_rq;
 805                 union fw_ldst_mps {
 806                         struct fw_ldst_mps_rplc {
 807                                 __be16 fid_idx;
 808                                 __be16 rplcpf_pkd;
 809                                 __be32 rplc255_224;
 810                                 __be32 rplc223_192;
 811                                 __be32 rplc191_160;
 812                                 __be32 rplc159_128;
 813                                 __be32 rplc127_96;
 814                                 __be32 rplc95_64;
 815                                 __be32 rplc63_32;
 816                                 __be32 rplc31_0;
 817                         } rplc;
 818                         struct fw_ldst_mps_atrb {
 819                                 __be16 fid_mpsid;
 820                                 __be16 r2[3];
 821                                 __be32 r3[2];
 822                                 __be32 r4;
 823                                 __be32 atrb;
 824                                 __be16 vlan[16];
 825                         } atrb;
 826                 } mps;
 827                 struct fw_ldst_func {
 828                         u8 access_ctl;
 829                         u8 mod_index;
 830                         __be16 ctl_id;
 831                         __be32 offset;
 832                         __be64 data0;
 833                         __be64 data1;
 834                 } func;
 835                 struct fw_ldst_pcie {
 836                         u8 ctrl_to_fn;
 837                         u8 bnum;
 838                         u8 r;
 839                         u8 ext_r;
 840                         u8 select_naccess;
 841                         u8 pcie_fn;
 842                         __be16 nset_pkd;
 843                         __be32 data[12];
 844                 } pcie;
 845                 struct fw_ldst_i2c_deprecated {
 846                         u8 pid_pkd;
 847                         u8 base;
 848                         u8 boffset;
 849                         u8 data;
 850                         __be32 r9;
 851                 } i2c_deprecated;
 852                 struct fw_ldst_i2c {
 853                         u8 pid;
 854                         u8 did;
 855                         u8 boffset;
 856                         u8 blen;
 857                         __be32 r9;
 858                         __u8   data[48];
 859                 } i2c;
 860                 struct fw_ldst_le {
 861                         __be32 index;
 862                         __be32 r9;
 863                         u8 val[33];
 864                         u8 r11[7];
 865                 } le;
 866         } u;
 867 };
 868
 869 #define FW_LDST_CMD_ADDRSPACE_S         0
 870 #define FW_LDST_CMD_ADDRSPACE_V(x)      ((x) << FW_LDST_CMD_ADDRSPACE_S)
 871
 872 #define FW_LDST_CMD_MSG_S       31
 873 #define FW_LDST_CMD_MSG_V(x)    ((x) << FW_LDST_CMD_MSG_S)
 874
 875 #define FW_LDST_CMD_CTXTFLUSH_S         30
 876 #define FW_LDST_CMD_CTXTFLUSH_V(x)      ((x) << FW_LDST_CMD_CTXTFLUSH_S)
 877 #define FW_LDST_CMD_CTXTFLUSH_F         FW_LDST_CMD_CTXTFLUSH_V(1U)
 878
 879 #define FW_LDST_CMD_PADDR_S     8
 880 #define FW_LDST_CMD_PADDR_V(x)  ((x) << FW_LDST_CMD_PADDR_S)
 881
 882 #define FW_LDST_CMD_MMD_S       0
 883 #define FW_LDST_CMD_MMD_V(x)    ((x) << FW_LDST_CMD_MMD_S)
 884
 885 #define FW_LDST_CMD_FID_S       15
 886 #define FW_LDST_CMD_FID_V(x)    ((x) << FW_LDST_CMD_FID_S)
 887
 888 #define FW_LDST_CMD_IDX_S       0
 889 #define FW_LDST_CMD_IDX_V(x)    ((x) << FW_LDST_CMD_IDX_S)
 890
 891 #define FW_LDST_CMD_RPLCPF_S    0
 892 #define FW_LDST_CMD_RPLCPF_V(x) ((x) << FW_LDST_CMD_RPLCPF_S)
 893
 894 #define FW_LDST_CMD_LC_S        4
 895 #define FW_LDST_CMD_LC_V(x)     ((x) << FW_LDST_CMD_LC_S)
 896 #define FW_LDST_CMD_LC_F        FW_LDST_CMD_LC_V(1U)
 897
 898 #define FW_LDST_CMD_FN_S        0
 899 #define FW_LDST_CMD_FN_V(x)     ((x) << FW_LDST_CMD_FN_S)
 900
 901 #define FW_LDST_CMD_NACCESS_S           0
 902 #define FW_LDST_CMD_NACCESS_V(x)        ((x) << FW_LDST_CMD_NACCESS_S)
 903
 904 struct fw_reset_cmd {
 905         __be32 op_to_write;
 906         __be32 retval_len16;
 907         __be32 val;
 908         __be32 halt_pkd;
 909 };
 910
 911 #define FW_RESET_CMD_HALT_S     31
 912 #define FW_RESET_CMD_HALT_M     0x1
 913 #define FW_RESET_CMD_HALT_V(x)  ((x) << FW_RESET_CMD_HALT_S)
 914 #define FW_RESET_CMD_HALT_G(x)  \
 915         (((x) >> FW_RESET_CMD_HALT_S) & FW_RESET_CMD_HALT_M)
 916 #define FW_RESET_CMD_HALT_F     FW_RESET_CMD_HALT_V(1U)
 917
 918 enum fw_hellow_cmd {
 919         fw_hello_cmd_stage_os           = 0x0
 920 };
 921
 922 struct fw_hello_cmd {
 923         __be32 op_to_write;
 924         __be32 retval_len16;
 925         __be32 err_to_clearinit;
 926         __be32 fwrev;
 927 };
 928
 929 #define FW_HELLO_CMD_ERR_S      31
 930 #define FW_HELLO_CMD_ERR_V(x)   ((x) << FW_HELLO_CMD_ERR_S)
 931 #define FW_HELLO_CMD_ERR_F      FW_HELLO_CMD_ERR_V(1U)
 932
 933 #define FW_HELLO_CMD_INIT_S     30
 934 #define FW_HELLO_CMD_INIT_V(x)  ((x) << FW_HELLO_CMD_INIT_S)
 935 #define FW_HELLO_CMD_INIT_F     FW_HELLO_CMD_INIT_V(1U)
 936
 937 #define FW_HELLO_CMD_MASTERDIS_S        29
 938 #define FW_HELLO_CMD_MASTERDIS_V(x)     ((x) << FW_HELLO_CMD_MASTERDIS_S)
 939
 940 #define FW_HELLO_CMD_MASTERFORCE_S      28
 941 #define FW_HELLO_CMD_MASTERFORCE_V(x)   ((x) << FW_HELLO_CMD_MASTERFORCE_S)
 942
 943 #define FW_HELLO_CMD_MBMASTER_S         24
 944 #define FW_HELLO_CMD_MBMASTER_M         0xfU
 945 #define FW_HELLO_CMD_MBMASTER_V(x)      ((x) << FW_HELLO_CMD_MBMASTER_S)
 946 #define FW_HELLO_CMD_MBMASTER_G(x)      \
 947         (((x) >> FW_HELLO_CMD_MBMASTER_S) & FW_HELLO_CMD_MBMASTER_M)
 948
 949 #define FW_HELLO_CMD_MBASYNCNOTINT_S    23
 950 #define FW_HELLO_CMD_MBASYNCNOTINT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOTINT_S)
 951
 952 #define FW_HELLO_CMD_MBASYNCNOT_S       20
 953 #define FW_HELLO_CMD_MBASYNCNOT_V(x)    ((x) << FW_HELLO_CMD_MBASYNCNOT_S)
 954
 955 #define FW_HELLO_CMD_STAGE_S            17
 956 #define FW_HELLO_CMD_STAGE_V(x)         ((x) << FW_HELLO_CMD_STAGE_S)
 957
 958 #define FW_HELLO_CMD_CLEARINIT_S        16
 959 #define FW_HELLO_CMD_CLEARINIT_V(x)     ((x) << FW_HELLO_CMD_CLEARINIT_S)
 960 #define FW_HELLO_CMD_CLEARINIT_F        FW_HELLO_CMD_CLEARINIT_V(1U)
 961
 962 struct fw_bye_cmd {
 963         __be32 op_to_write;
 964         __be32 retval_len16;
 965         __be64 r3;
 966 };
 967
 968 struct fw_initialize_cmd {
 969         __be32 op_to_write;
 970         __be32 retval_len16;
 971         __be64 r3;
 972 };
 973
 974 enum fw_caps_config_hm {
 975         FW_CAPS_CONFIG_HM_PCIE          = 0x00000001,
 976         FW_CAPS_CONFIG_HM_PL            = 0x00000002,
 977         FW_CAPS_CONFIG_HM_SGE           = 0x00000004,
 978         FW_CAPS_CONFIG_HM_CIM           = 0x00000008,
 979         FW_CAPS_CONFIG_HM_ULPTX         = 0x00000010,
 980         FW_CAPS_CONFIG_HM_TP            = 0x00000020,
 981         FW_CAPS_CONFIG_HM_ULPRX         = 0x00000040,
 982         FW_CAPS_CONFIG_HM_PMRX          = 0x00000080,
 983         FW_CAPS_CONFIG_HM_PMTX          = 0x00000100,
 984         FW_CAPS_CONFIG_HM_MC            = 0x00000200,
 985         FW_CAPS_CONFIG_HM_LE            = 0x00000400,
 986         FW_CAPS_CONFIG_HM_MPS           = 0x00000800,
 987         FW_CAPS_CONFIG_HM_XGMAC         = 0x00001000,
 988         FW_CAPS_CONFIG_HM_CPLSWITCH     = 0x00002000,
 989         FW_CAPS_CONFIG_HM_T4DBG         = 0x00004000,
 990         FW_CAPS_CONFIG_HM_MI            = 0x00008000,
 991         FW_CAPS_CONFIG_HM_I2CM          = 0x00010000,
 992         FW_CAPS_CONFIG_HM_NCSI          = 0x00020000,
 993         FW_CAPS_CONFIG_HM_SMB           = 0x00040000,
 994         FW_CAPS_CONFIG_HM_MA            = 0x00080000,
 995         FW_CAPS_CONFIG_HM_EDRAM         = 0x00100000,
 996         FW_CAPS_CONFIG_HM_PMU           = 0x00200000,
 997         FW_CAPS_CONFIG_HM_UART          = 0x00400000,
 998         FW_CAPS_CONFIG_HM_SF            = 0x00800000,
 999 };
1000
1001 enum fw_caps_config_nbm {
1002         FW_CAPS_CONFIG_NBM_IPMI         = 0x00000001,
1003         FW_CAPS_CONFIG_NBM_NCSI         = 0x00000002,
1004 };
1005
1006 enum fw_caps_config_link {
1007         FW_CAPS_CONFIG_LINK_PPP         = 0x00000001,
1008         FW_CAPS_CONFIG_LINK_QFC         = 0x00000002,
1009         FW_CAPS_CONFIG_LINK_DCBX        = 0x00000004,
1010 };
1011
1012 enum fw_caps_config_switch {
1013         FW_CAPS_CONFIG_SWITCH_INGRESS   = 0x00000001,
1014         FW_CAPS_CONFIG_SWITCH_EGRESS    = 0x00000002,
1015 };
1016
1017 enum fw_caps_config_nic {
1018         FW_CAPS_CONFIG_NIC              = 0x00000001,
1019         FW_CAPS_CONFIG_NIC_VM           = 0x00000002,
1020 };
1021
1022 enum fw_caps_config_ofld {
1023         FW_CAPS_CONFIG_OFLD             = 0x00000001,
1024 };
1025
1026 enum fw_caps_config_rdma {
1027         FW_CAPS_CONFIG_RDMA_RDDP        = 0x00000001,
1028         FW_CAPS_CONFIG_RDMA_RDMAC       = 0x00000002,
1029 };
1030
1031 enum fw_caps_config_iscsi {
1032         FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
1033         FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
1034         FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
1035         FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
1036 };
1037
1038 enum fw_caps_config_fcoe {
1039         FW_CAPS_CONFIG_FCOE_INITIATOR   = 0x00000001,
1040         FW_CAPS_CONFIG_FCOE_TARGET      = 0x00000002,
1041         FW_CAPS_CONFIG_FCOE_CTRL_OFLD   = 0x00000004,
1042 };
1043
1044 enum fw_memtype_cf {
1045         FW_MEMTYPE_CF_EDC0              = 0x0,
1046         FW_MEMTYPE_CF_EDC1              = 0x1,
1047         FW_MEMTYPE_CF_EXTMEM            = 0x2,
1048         FW_MEMTYPE_CF_FLASH             = 0x4,
1049         FW_MEMTYPE_CF_INTERNAL          = 0x5,
1050         FW_MEMTYPE_CF_EXTMEM1           = 0x6,
1051 };
1052
1053 struct fw_caps_config_cmd {
1054         __be32 op_to_write;
1055         __be32 cfvalid_to_len16;
1056         __be32 r2;
1057         __be32 hwmbitmap;
1058         __be16 nbmcaps;
1059         __be16 linkcaps;
1060         __be16 switchcaps;
1061         __be16 r3;
1062         __be16 niccaps;
1063         __be16 ofldcaps;
1064         __be16 rdmacaps;
1065         __be16 cryptocaps;
1066         __be16 iscsicaps;
1067         __be16 fcoecaps;
1068         __be32 cfcsum;
1069         __be32 finiver;
1070         __be32 finicsum;
1071 };
1072
1073 #define FW_CAPS_CONFIG_CMD_CFVALID_S    27
1074 #define FW_CAPS_CONFIG_CMD_CFVALID_V(x) ((x) << FW_CAPS_CONFIG_CMD_CFVALID_S)
1075 #define FW_CAPS_CONFIG_CMD_CFVALID_F    FW_CAPS_CONFIG_CMD_CFVALID_V(1U)
1076
1077 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S         24
1078 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(x)      \
1079         ((x) << FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S)
1080
1081 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S      16
1082 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(x)   \
1083         ((x) << FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S)
1084
1085 /*
1086  * params command mnemonics
1087  */
1088 enum fw_params_mnem {
1089         FW_PARAMS_MNEM_DEV              = 1,    /* device params */
1090         FW_PARAMS_MNEM_PFVF             = 2,    /* function params */
1091         FW_PARAMS_MNEM_REG              = 3,    /* limited register access */
1092         FW_PARAMS_MNEM_DMAQ             = 4,    /* dma queue params */
1093         FW_PARAMS_MNEM_CHNET            = 5,    /* chnet params */
1094         FW_PARAMS_MNEM_LAST
1095 };
1096
1097 /*
1098  * device parameters
1099  */
1100 enum fw_params_param_dev {
1101         FW_PARAMS_PARAM_DEV_CCLK        = 0x00, /* chip core clock in khz */
1102         FW_PARAMS_PARAM_DEV_PORTVEC     = 0x01, /* the port vector */
1103         FW_PARAMS_PARAM_DEV_NTID        = 0x02, /* reads the number of TIDs
1104                                                  * allocated by the device's
1105                                                  * Lookup Engine
1106                                                  */
1107         FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
1108         FW_PARAMS_PARAM_DEV_INTVER_NIC  = 0x04,
1109         FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05,
1110         FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06,
1111         FW_PARAMS_PARAM_DEV_INTVER_RI   = 0x07,
1112         FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08,
1113         FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09,
1114         FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A,
1115         FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
1116         FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
1117         FW_PARAMS_PARAM_DEV_CF = 0x0D,
1118         FW_PARAMS_PARAM_DEV_PHYFW = 0x0F,
1119         FW_PARAMS_PARAM_DEV_DIAG = 0x11,
1120         FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD */
1121         FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER = 0x14, /* max supported adap IRD */
1122         FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
1123         FW_PARAMS_PARAM_DEV_FWCACHE = 0x18,
1124         FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR  = 0x1C,
1125 };
1126
1127 /*
1128  * physical and virtual function parameters
1129  */
1130 enum fw_params_param_pfvf {
1131         FW_PARAMS_PARAM_PFVF_RWXCAPS    = 0x00,
1132         FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
1133         FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
1134         FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
1135         FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
1136         FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
1137         FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
1138         FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
1139         FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
1140         FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
1141         FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
1142         FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
1143         FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
1144         FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
1145         FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
1146         FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
1147         FW_PARAMS_PARAM_PFVF_RQ_END     = 0x10,
1148         FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
1149         FW_PARAMS_PARAM_PFVF_PBL_END    = 0x12,
1150         FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
1151         FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
1152         FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
1153         FW_PARAMS_PARAM_PFVF_SQRQ_END   = 0x16,
1154         FW_PARAMS_PARAM_PFVF_CQ_START   = 0x17,
1155         FW_PARAMS_PARAM_PFVF_CQ_END     = 0x18,
1156         FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
1157         FW_PARAMS_PARAM_PFVF_VIID       = 0x24,
1158         FW_PARAMS_PARAM_PFVF_CPMASK     = 0x25,
1159         FW_PARAMS_PARAM_PFVF_OCQ_START  = 0x26,
1160         FW_PARAMS_PARAM_PFVF_OCQ_END    = 0x27,
1161         FW_PARAMS_PARAM_PFVF_CONM_MAP   = 0x28,
1162         FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
1163         FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
1164         FW_PARAMS_PARAM_PFVF_EQ_START   = 0x2B,
1165         FW_PARAMS_PARAM_PFVF_EQ_END     = 0x2C,
1166         FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
1167         FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
1168         FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
1169         FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31
1170 };
1171
1172 /*
1173  * dma queue parameters
1174  */
1175 enum fw_params_param_dmaq {
1176         FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
1177         FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
1178         FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
1179         FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
1180         FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
1181         FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
1182         FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
1183 };
1184
1185 enum fw_params_param_dev_phyfw {
1186         FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00,
1187         FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01,
1188 };
1189
1190 enum fw_params_param_dev_diag {
1191         FW_PARAM_DEV_DIAG_TMP           = 0x00,
1192         FW_PARAM_DEV_DIAG_VDD           = 0x01,
1193 };
1194
1195 enum fw_params_param_dev_fwcache {
1196         FW_PARAM_DEV_FWCACHE_FLUSH      = 0x00,
1197         FW_PARAM_DEV_FWCACHE_FLUSHINV   = 0x01,
1198 };
1199
1200 #define FW_PARAMS_MNEM_S        24
1201 #define FW_PARAMS_MNEM_V(x)     ((x) << FW_PARAMS_MNEM_S)
1202
1203 #define FW_PARAMS_PARAM_X_S     16
1204 #define FW_PARAMS_PARAM_X_V(x)  ((x) << FW_PARAMS_PARAM_X_S)
1205
1206 #define FW_PARAMS_PARAM_Y_S     8
1207 #define FW_PARAMS_PARAM_Y_M     0xffU
1208 #define FW_PARAMS_PARAM_Y_V(x)  ((x) << FW_PARAMS_PARAM_Y_S)
1209 #define FW_PARAMS_PARAM_Y_G(x)  (((x) >> FW_PARAMS_PARAM_Y_S) &\
1210                 FW_PARAMS_PARAM_Y_M)
1211
1212 #define FW_PARAMS_PARAM_Z_S     0
1213 #define FW_PARAMS_PARAM_Z_M     0xffu
1214 #define FW_PARAMS_PARAM_Z_V(x)  ((x) << FW_PARAMS_PARAM_Z_S)
1215 #define FW_PARAMS_PARAM_Z_G(x)  (((x) >> FW_PARAMS_PARAM_Z_S) &\
1216                 FW_PARAMS_PARAM_Z_M)
1217
1218 #define FW_PARAMS_PARAM_XYZ_S           0
1219 #define FW_PARAMS_PARAM_XYZ_V(x)        ((x) << FW_PARAMS_PARAM_XYZ_S)
1220
1221 #define FW_PARAMS_PARAM_YZ_S            0
1222 #define FW_PARAMS_PARAM_YZ_V(x)         ((x) << FW_PARAMS_PARAM_YZ_S)
1223
1224 struct fw_params_cmd {
1225         __be32 op_to_vfn;
1226         __be32 retval_len16;
1227         struct fw_params_param {
1228                 __be32 mnem;
1229                 __be32 val;
1230         } param[7];
1231 };
1232
1233 #define FW_PARAMS_CMD_PFN_S     8
1234 #define FW_PARAMS_CMD_PFN_V(x)  ((x) << FW_PARAMS_CMD_PFN_S)
1235
1236 #define FW_PARAMS_CMD_VFN_S     0
1237 #define FW_PARAMS_CMD_VFN_V(x)  ((x) << FW_PARAMS_CMD_VFN_S)
1238
1239 struct fw_pfvf_cmd {
1240         __be32 op_to_vfn;
1241         __be32 retval_len16;
1242         __be32 niqflint_niq;
1243         __be32 type_to_neq;
1244         __be32 tc_to_nexactf;
1245         __be32 r_caps_to_nethctrl;
1246         __be16 nricq;
1247         __be16 nriqp;
1248         __be32 r4;
1249 };
1250
1251 #define FW_PFVF_CMD_PFN_S       8
1252 #define FW_PFVF_CMD_PFN_V(x)    ((x) << FW_PFVF_CMD_PFN_S)
1253
1254 #define FW_PFVF_CMD_VFN_S       0
1255 #define FW_PFVF_CMD_VFN_V(x)    ((x) << FW_PFVF_CMD_VFN_S)
1256
1257 #define FW_PFVF_CMD_NIQFLINT_S          20
1258 #define FW_PFVF_CMD_NIQFLINT_M          0xfff
1259 #define FW_PFVF_CMD_NIQFLINT_V(x)       ((x) << FW_PFVF_CMD_NIQFLINT_S)
1260 #define FW_PFVF_CMD_NIQFLINT_G(x)       \
1261         (((x) >> FW_PFVF_CMD_NIQFLINT_S) & FW_PFVF_CMD_NIQFLINT_M)
1262
1263 #define FW_PFVF_CMD_NIQ_S       0
1264 #define FW_PFVF_CMD_NIQ_M       0xfffff
1265 #define FW_PFVF_CMD_NIQ_V(x)    ((x) << FW_PFVF_CMD_NIQ_S)
1266 #define FW_PFVF_CMD_NIQ_G(x)    \
1267         (((x) >> FW_PFVF_CMD_NIQ_S) & FW_PFVF_CMD_NIQ_M)
1268
1269 #define FW_PFVF_CMD_TYPE_S      31
1270 #define FW_PFVF_CMD_TYPE_M      0x1
1271 #define FW_PFVF_CMD_TYPE_V(x)   ((x) << FW_PFVF_CMD_TYPE_S)
1272 #define FW_PFVF_CMD_TYPE_G(x)   \
1273         (((x) >> FW_PFVF_CMD_TYPE_S) & FW_PFVF_CMD_TYPE_M)
1274 #define FW_PFVF_CMD_TYPE_F      FW_PFVF_CMD_TYPE_V(1U)
1275
1276 #define FW_PFVF_CMD_CMASK_S     24
1277 #define FW_PFVF_CMD_CMASK_M     0xf
1278 #define FW_PFVF_CMD_CMASK_V(x)  ((x) << FW_PFVF_CMD_CMASK_S)
1279 #define FW_PFVF_CMD_CMASK_G(x)  \
1280         (((x) >> FW_PFVF_CMD_CMASK_S) & FW_PFVF_CMD_CMASK_M)
1281
1282 #define FW_PFVF_CMD_PMASK_S     20
1283 #define FW_PFVF_CMD_PMASK_M     0xf
1284 #define FW_PFVF_CMD_PMASK_V(x)  ((x) << FW_PFVF_CMD_PMASK_S)
1285 #define FW_PFVF_CMD_PMASK_G(x) \
1286         (((x) >> FW_PFVF_CMD_PMASK_S) & FW_PFVF_CMD_PMASK_M)
1287
1288 #define FW_PFVF_CMD_NEQ_S       0
1289 #define FW_PFVF_CMD_NEQ_M       0xfffff
1290 #define FW_PFVF_CMD_NEQ_V(x)    ((x) << FW_PFVF_CMD_NEQ_S)
1291 #define FW_PFVF_CMD_NEQ_G(x)    \
1292         (((x) >> FW_PFVF_CMD_NEQ_S) & FW_PFVF_CMD_NEQ_M)
1293
1294 #define FW_PFVF_CMD_TC_S        24
1295 #define FW_PFVF_CMD_TC_M        0xff
1296 #define FW_PFVF_CMD_TC_V(x)     ((x) << FW_PFVF_CMD_TC_S)
1297 #define FW_PFVF_CMD_TC_G(x)     (((x) >> FW_PFVF_CMD_TC_S) & FW_PFVF_CMD_TC_M)
1298
1299 #define FW_PFVF_CMD_NVI_S       16
1300 #define FW_PFVF_CMD_NVI_M       0xff
1301 #define FW_PFVF_CMD_NVI_V(x)    ((x) << FW_PFVF_CMD_NVI_S)
1302 #define FW_PFVF_CMD_NVI_G(x)    (((x) >> FW_PFVF_CMD_NVI_S) & FW_PFVF_CMD_NVI_M)
1303
1304 #define FW_PFVF_CMD_NEXACTF_S           0
1305 #define FW_PFVF_CMD_NEXACTF_M           0xffff
1306 #define FW_PFVF_CMD_NEXACTF_V(x)        ((x) << FW_PFVF_CMD_NEXACTF_S)
1307 #define FW_PFVF_CMD_NEXACTF_G(x)        \
1308         (((x) >> FW_PFVF_CMD_NEXACTF_S) & FW_PFVF_CMD_NEXACTF_M)
1309
1310 #define FW_PFVF_CMD_R_CAPS_S    24
1311 #define FW_PFVF_CMD_R_CAPS_M    0xff
1312 #define FW_PFVF_CMD_R_CAPS_V(x) ((x) << FW_PFVF_CMD_R_CAPS_S)
1313 #define FW_PFVF_CMD_R_CAPS_G(x) \
1314         (((x) >> FW_PFVF_CMD_R_CAPS_S) & FW_PFVF_CMD_R_CAPS_M)
1315
1316 #define FW_PFVF_CMD_WX_CAPS_S           16
1317 #define FW_PFVF_CMD_WX_CAPS_M           0xff
1318 #define FW_PFVF_CMD_WX_CAPS_V(x)        ((x) << FW_PFVF_CMD_WX_CAPS_S)
1319 #define FW_PFVF_CMD_WX_CAPS_G(x)        \
1320         (((x) >> FW_PFVF_CMD_WX_CAPS_S) & FW_PFVF_CMD_WX_CAPS_M)
1321
1322 #define FW_PFVF_CMD_NETHCTRL_S          0
1323 #define FW_PFVF_CMD_NETHCTRL_M          0xffff
1324 #define FW_PFVF_CMD_NETHCTRL_V(x)       ((x) << FW_PFVF_CMD_NETHCTRL_S)
1325 #define FW_PFVF_CMD_NETHCTRL_G(x)       \
1326         (((x) >> FW_PFVF_CMD_NETHCTRL_S) & FW_PFVF_CMD_NETHCTRL_M)
1327
1328 enum fw_iq_type {
1329         FW_IQ_TYPE_FL_INT_CAP,
1330         FW_IQ_TYPE_NO_FL_INT_CAP
1331 };
1332
1333 struct fw_iq_cmd {
1334         __be32 op_to_vfn;
1335         __be32 alloc_to_len16;
1336         __be16 physiqid;
1337         __be16 iqid;
1338         __be16 fl0id;
1339         __be16 fl1id;
1340         __be32 type_to_iqandstindex;
1341         __be16 iqdroprss_to_iqesize;
1342         __be16 iqsize;
1343         __be64 iqaddr;
1344         __be32 iqns_to_fl0congen;
1345         __be16 fl0dcaen_to_fl0cidxfthresh;
1346         __be16 fl0size;
1347         __be64 fl0addr;
1348         __be32 fl1cngchmap_to_fl1congen;
1349         __be16 fl1dcaen_to_fl1cidxfthresh;
1350         __be16 fl1size;
1351         __be64 fl1addr;
1352 };
1353
1354 #define FW_IQ_CMD_PFN_S         8
1355 #define FW_IQ_CMD_PFN_V(x)      ((x) << FW_IQ_CMD_PFN_S)
1356
1357 #define FW_IQ_CMD_VFN_S         0
1358 #define FW_IQ_CMD_VFN_V(x)      ((x) << FW_IQ_CMD_VFN_S)
1359
1360 #define FW_IQ_CMD_ALLOC_S       31
1361 #define FW_IQ_CMD_ALLOC_V(x)    ((x) << FW_IQ_CMD_ALLOC_S)
1362 #define FW_IQ_CMD_ALLOC_F       FW_IQ_CMD_ALLOC_V(1U)
1363
1364 #define FW_IQ_CMD_FREE_S        30
1365 #define FW_IQ_CMD_FREE_V(x)     ((x) << FW_IQ_CMD_FREE_S)
1366 #define FW_IQ_CMD_FREE_F        FW_IQ_CMD_FREE_V(1U)
1367
1368 #define FW_IQ_CMD_MODIFY_S      29
1369 #define FW_IQ_CMD_MODIFY_V(x)   ((x) << FW_IQ_CMD_MODIFY_S)
1370 #define FW_IQ_CMD_MODIFY_F      FW_IQ_CMD_MODIFY_V(1U)
1371
1372 #define FW_IQ_CMD_IQSTART_S     28
1373 #define FW_IQ_CMD_IQSTART_V(x)  ((x) << FW_IQ_CMD_IQSTART_S)
1374 #define FW_IQ_CMD_IQSTART_F     FW_IQ_CMD_IQSTART_V(1U)
1375
1376 #define FW_IQ_CMD_IQSTOP_S      27
1377 #define FW_IQ_CMD_IQSTOP_V(x)   ((x) << FW_IQ_CMD_IQSTOP_S)
1378 #define FW_IQ_CMD_IQSTOP_F      FW_IQ_CMD_IQSTOP_V(1U)
1379
1380 #define FW_IQ_CMD_TYPE_S        29
1381 #define FW_IQ_CMD_TYPE_V(x)     ((x) << FW_IQ_CMD_TYPE_S)
1382
1383 #define FW_IQ_CMD_IQASYNCH_S    28
1384 #define FW_IQ_CMD_IQASYNCH_V(x) ((x) << FW_IQ_CMD_IQASYNCH_S)
1385
1386 #define FW_IQ_CMD_VIID_S        16
1387 #define FW_IQ_CMD_VIID_V(x)     ((x) << FW_IQ_CMD_VIID_S)
1388
1389 #define FW_IQ_CMD_IQANDST_S     15
1390 #define FW_IQ_CMD_IQANDST_V(x)  ((x) << FW_IQ_CMD_IQANDST_S)
1391
1392 #define FW_IQ_CMD_IQANUS_S      14
1393 #define FW_IQ_CMD_IQANUS_V(x)   ((x) << FW_IQ_CMD_IQANUS_S)
1394
1395 #define FW_IQ_CMD_IQANUD_S      12
1396 #define FW_IQ_CMD_IQANUD_V(x)   ((x) << FW_IQ_CMD_IQANUD_S)
1397
1398 #define FW_IQ_CMD_IQANDSTINDEX_S        0
1399 #define FW_IQ_CMD_IQANDSTINDEX_V(x)     ((x) << FW_IQ_CMD_IQANDSTINDEX_S)
1400
1401 #define FW_IQ_CMD_IQDROPRSS_S           15
1402 #define FW_IQ_CMD_IQDROPRSS_V(x)        ((x) << FW_IQ_CMD_IQDROPRSS_S)
1403 #define FW_IQ_CMD_IQDROPRSS_F   FW_IQ_CMD_IQDROPRSS_V(1U)
1404
1405 #define FW_IQ_CMD_IQGTSMODE_S           14
1406 #define FW_IQ_CMD_IQGTSMODE_V(x)        ((x) << FW_IQ_CMD_IQGTSMODE_S)
1407 #define FW_IQ_CMD_IQGTSMODE_F           FW_IQ_CMD_IQGTSMODE_V(1U)
1408
1409 #define FW_IQ_CMD_IQPCIECH_S    12
1410 #define FW_IQ_CMD_IQPCIECH_V(x) ((x) << FW_IQ_CMD_IQPCIECH_S)
1411
1412 #define FW_IQ_CMD_IQDCAEN_S     11
1413 #define FW_IQ_CMD_IQDCAEN_V(x)  ((x) << FW_IQ_CMD_IQDCAEN_S)
1414
1415 #define FW_IQ_CMD_IQDCACPU_S    6
1416 #define FW_IQ_CMD_IQDCACPU_V(x) ((x) << FW_IQ_CMD_IQDCACPU_S)
1417
1418 #define FW_IQ_CMD_IQINTCNTTHRESH_S      4
1419 #define FW_IQ_CMD_IQINTCNTTHRESH_V(x)   ((x) << FW_IQ_CMD_IQINTCNTTHRESH_S)
1420
1421 #define FW_IQ_CMD_IQO_S         3
1422 #define FW_IQ_CMD_IQO_V(x)      ((x) << FW_IQ_CMD_IQO_S)
1423 #define FW_IQ_CMD_IQO_F         FW_IQ_CMD_IQO_V(1U)
1424
1425 #define FW_IQ_CMD_IQCPRIO_S     2
1426 #define FW_IQ_CMD_IQCPRIO_V(x)  ((x) << FW_IQ_CMD_IQCPRIO_S)
1427
1428 #define FW_IQ_CMD_IQESIZE_S     0
1429 #define FW_IQ_CMD_IQESIZE_V(x)  ((x) << FW_IQ_CMD_IQESIZE_S)
1430
1431 #define FW_IQ_CMD_IQNS_S        31
1432 #define FW_IQ_CMD_IQNS_V(x)     ((x) << FW_IQ_CMD_IQNS_S)
1433
1434 #define FW_IQ_CMD_IQRO_S        30
1435 #define FW_IQ_CMD_IQRO_V(x)     ((x) << FW_IQ_CMD_IQRO_S)
1436
1437 #define FW_IQ_CMD_IQFLINTIQHSEN_S       28
1438 #define FW_IQ_CMD_IQFLINTIQHSEN_V(x)    ((x) << FW_IQ_CMD_IQFLINTIQHSEN_S)
1439
1440 #define FW_IQ_CMD_IQFLINTCONGEN_S       27
1441 #define FW_IQ_CMD_IQFLINTCONGEN_V(x)    ((x) << FW_IQ_CMD_IQFLINTCONGEN_S)
1442 #define FW_IQ_CMD_IQFLINTCONGEN_F       FW_IQ_CMD_IQFLINTCONGEN_V(1U)
1443
1444 #define FW_IQ_CMD_IQFLINTISCSIC_S       26
1445 #define FW_IQ_CMD_IQFLINTISCSIC_V(x)    ((x) << FW_IQ_CMD_IQFLINTISCSIC_S)
1446
1447 #define FW_IQ_CMD_FL0CNGCHMAP_S         20
1448 #define FW_IQ_CMD_FL0CNGCHMAP_V(x)      ((x) << FW_IQ_CMD_FL0CNGCHMAP_S)
1449
1450 #define FW_IQ_CMD_FL0CACHELOCK_S        15
1451 #define FW_IQ_CMD_FL0CACHELOCK_V(x)     ((x) << FW_IQ_CMD_FL0CACHELOCK_S)
1452
1453 #define FW_IQ_CMD_FL0DBP_S      14
1454 #define FW_IQ_CMD_FL0DBP_V(x)   ((x) << FW_IQ_CMD_FL0DBP_S)
1455
1456 #define FW_IQ_CMD_FL0DATANS_S           13
1457 #define FW_IQ_CMD_FL0DATANS_V(x)        ((x) << FW_IQ_CMD_FL0DATANS_S)
1458
1459 #define FW_IQ_CMD_FL0DATARO_S           12
1460 #define FW_IQ_CMD_FL0DATARO_V(x)        ((x) << FW_IQ_CMD_FL0DATARO_S)
1461 #define FW_IQ_CMD_FL0DATARO_F           FW_IQ_CMD_FL0DATARO_V(1U)
1462
1463 #define FW_IQ_CMD_FL0CONGCIF_S          11
1464 #define FW_IQ_CMD_FL0CONGCIF_V(x)       ((x) << FW_IQ_CMD_FL0CONGCIF_S)
1465 #define FW_IQ_CMD_FL0CONGCIF_F          FW_IQ_CMD_FL0CONGCIF_V(1U)
1466
1467 #define FW_IQ_CMD_FL0ONCHIP_S           10
1468 #define FW_IQ_CMD_FL0ONCHIP_V(x)        ((x) << FW_IQ_CMD_FL0ONCHIP_S)
1469
1470 #define FW_IQ_CMD_FL0STATUSPGNS_S       9
1471 #define FW_IQ_CMD_FL0STATUSPGNS_V(x)    ((x) << FW_IQ_CMD_FL0STATUSPGNS_S)
1472
1473 #define FW_IQ_CMD_FL0STATUSPGRO_S       8
1474 #define FW_IQ_CMD_FL0STATUSPGRO_V(x)    ((x) << FW_IQ_CMD_FL0STATUSPGRO_S)
1475
1476 #define FW_IQ_CMD_FL0FETCHNS_S          7
1477 #define FW_IQ_CMD_FL0FETCHNS_V(x)       ((x) << FW_IQ_CMD_FL0FETCHNS_S)
1478
1479 #define FW_IQ_CMD_FL0FETCHRO_S          6
1480 #define FW_IQ_CMD_FL0FETCHRO_V(x)       ((x) << FW_IQ_CMD_FL0FETCHRO_S)
1481 #define FW_IQ_CMD_FL0FETCHRO_F          FW_IQ_CMD_FL0FETCHRO_V(1U)
1482
1483 #define FW_IQ_CMD_FL0HOSTFCMODE_S       4
1484 #define FW_IQ_CMD_FL0HOSTFCMODE_V(x)    ((x) << FW_IQ_CMD_FL0HOSTFCMODE_S)
1485
1486 #define FW_IQ_CMD_FL0CPRIO_S    3
1487 #define FW_IQ_CMD_FL0CPRIO_V(x) ((x) << FW_IQ_CMD_FL0CPRIO_S)
1488
1489 #define FW_IQ_CMD_FL0PADEN_S    2
1490 #define FW_IQ_CMD_FL0PADEN_V(x) ((x) << FW_IQ_CMD_FL0PADEN_S)
1491 #define FW_IQ_CMD_FL0PADEN_F    FW_IQ_CMD_FL0PADEN_V(1U)
1492
1493 #define FW_IQ_CMD_FL0PACKEN_S           1
1494 #define FW_IQ_CMD_FL0PACKEN_V(x)        ((x) << FW_IQ_CMD_FL0PACKEN_S)
1495 #define FW_IQ_CMD_FL0PACKEN_F           FW_IQ_CMD_FL0PACKEN_V(1U)
1496
1497 #define FW_IQ_CMD_FL0CONGEN_S           0
1498 #define FW_IQ_CMD_FL0CONGEN_V(x)        ((x) << FW_IQ_CMD_FL0CONGEN_S)
1499 #define FW_IQ_CMD_FL0CONGEN_F           FW_IQ_CMD_FL0CONGEN_V(1U)
1500
1501 #define FW_IQ_CMD_FL0DCAEN_S    15
1502 #define FW_IQ_CMD_FL0DCAEN_V(x) ((x) << FW_IQ_CMD_FL0DCAEN_S)
1503
1504 #define FW_IQ_CMD_FL0DCACPU_S           10
1505 #define FW_IQ_CMD_FL0DCACPU_V(x)        ((x) << FW_IQ_CMD_FL0DCACPU_S)
1506
1507 #define FW_IQ_CMD_FL0FBMIN_S    7
1508 #define FW_IQ_CMD_FL0FBMIN_V(x) ((x) << FW_IQ_CMD_FL0FBMIN_S)
1509
1510 #define FW_IQ_CMD_FL0FBMAX_S    4
1511 #define FW_IQ_CMD_FL0FBMAX_V(x) ((x) << FW_IQ_CMD_FL0FBMAX_S)
1512
1513 #define FW_IQ_CMD_FL0CIDXFTHRESHO_S     3
1514 #define FW_IQ_CMD_FL0CIDXFTHRESHO_V(x)  ((x) << FW_IQ_CMD_FL0CIDXFTHRESHO_S)
1515 #define FW_IQ_CMD_FL0CIDXFTHRESHO_F     FW_IQ_CMD_FL0CIDXFTHRESHO_V(1U)
1516
1517 #define FW_IQ_CMD_FL0CIDXFTHRESH_S      0
1518 #define FW_IQ_CMD_FL0CIDXFTHRESH_V(x)   ((x) << FW_IQ_CMD_FL0CIDXFTHRESH_S)
1519
1520 #define FW_IQ_CMD_FL1CNGCHMAP_S         20
1521 #define FW_IQ_CMD_FL1CNGCHMAP_V(x)      ((x) << FW_IQ_CMD_FL1CNGCHMAP_S)
1522
1523 #define FW_IQ_CMD_FL1CACHELOCK_S        15
1524 #define FW_IQ_CMD_FL1CACHELOCK_V(x)     ((x) << FW_IQ_CMD_FL1CACHELOCK_S)
1525
1526 #define FW_IQ_CMD_FL1DBP_S      14
1527 #define FW_IQ_CMD_FL1DBP_V(x)   ((x) << FW_IQ_CMD_FL1DBP_S)
1528
1529 #define FW_IQ_CMD_FL1DATANS_S           13
1530 #define FW_IQ_CMD_FL1DATANS_V(x)        ((x) << FW_IQ_CMD_FL1DATANS_S)
1531
1532 #define FW_IQ_CMD_FL1DATARO_S           12
1533 #define FW_IQ_CMD_FL1DATARO_V(x)        ((x) << FW_IQ_CMD_FL1DATARO_S)
1534
1535 #define FW_IQ_CMD_FL1CONGCIF_S          11
1536 #define FW_IQ_CMD_FL1CONGCIF_V(x)       ((x) << FW_IQ_CMD_FL1CONGCIF_S)
1537
1538 #define FW_IQ_CMD_FL1ONCHIP_S           10
1539 #define FW_IQ_CMD_FL1ONCHIP_V(x)        ((x) << FW_IQ_CMD_FL1ONCHIP_S)
1540
1541 #define FW_IQ_CMD_FL1STATUSPGNS_S       9
1542 #define FW_IQ_CMD_FL1STATUSPGNS_V(x)    ((x) << FW_IQ_CMD_FL1STATUSPGNS_S)
1543
1544 #define FW_IQ_CMD_FL1STATUSPGRO_S       8
1545 #define FW_IQ_CMD_FL1STATUSPGRO_V(x)    ((x) << FW_IQ_CMD_FL1STATUSPGRO_S)
1546
1547 #define FW_IQ_CMD_FL1FETCHNS_S          7
1548 #define FW_IQ_CMD_FL1FETCHNS_V(x)       ((x) << FW_IQ_CMD_FL1FETCHNS_S)
1549
1550 #define FW_IQ_CMD_FL1FETCHRO_S          6
1551 #define FW_IQ_CMD_FL1FETCHRO_V(x)       ((x) << FW_IQ_CMD_FL1FETCHRO_S)
1552
1553 #define FW_IQ_CMD_FL1HOSTFCMODE_S       4
1554 #define FW_IQ_CMD_FL1HOSTFCMODE_V(x)    ((x) << FW_IQ_CMD_FL1HOSTFCMODE_S)
1555
1556 #define FW_IQ_CMD_FL1CPRIO_S    3
1557 #define FW_IQ_CMD_FL1CPRIO_V(x) ((x) << FW_IQ_CMD_FL1CPRIO_S)
1558
1559 #define FW_IQ_CMD_FL1PADEN_S    2
1560 #define FW_IQ_CMD_FL1PADEN_V(x) ((x) << FW_IQ_CMD_FL1PADEN_S)
1561 #define FW_IQ_CMD_FL1PADEN_F    FW_IQ_CMD_FL1PADEN_V(1U)
1562
1563 #define FW_IQ_CMD_FL1PACKEN_S           1
1564 #define FW_IQ_CMD_FL1PACKEN_V(x)        ((x) << FW_IQ_CMD_FL1PACKEN_S)
1565 #define FW_IQ_CMD_FL1PACKEN_F   FW_IQ_CMD_FL1PACKEN_V(1U)
1566
1567 #define FW_IQ_CMD_FL1CONGEN_S           0
1568 #define FW_IQ_CMD_FL1CONGEN_V(x)        ((x) << FW_IQ_CMD_FL1CONGEN_S)
1569 #define FW_IQ_CMD_FL1CONGEN_F   FW_IQ_CMD_FL1CONGEN_V(1U)
1570
1571 #define FW_IQ_CMD_FL1DCAEN_S    15
1572 #define FW_IQ_CMD_FL1DCAEN_V(x) ((x) << FW_IQ_CMD_FL1DCAEN_S)
1573
1574 #define FW_IQ_CMD_FL1DCACPU_S           10
1575 #define FW_IQ_CMD_FL1DCACPU_V(x)        ((x) << FW_IQ_CMD_FL1DCACPU_S)
1576
1577 #define FW_IQ_CMD_FL1FBMIN_S    7
1578 #define FW_IQ_CMD_FL1FBMIN_V(x) ((x) << FW_IQ_CMD_FL1FBMIN_S)
1579
1580 #define FW_IQ_CMD_FL1FBMAX_S    4
1581 #define FW_IQ_CMD_FL1FBMAX_V(x) ((x) << FW_IQ_CMD_FL1FBMAX_S)
1582
1583 #define FW_IQ_CMD_FL1CIDXFTHRESHO_S     3
1584 #define FW_IQ_CMD_FL1CIDXFTHRESHO_V(x)  ((x) << FW_IQ_CMD_FL1CIDXFTHRESHO_S)
1585 #define FW_IQ_CMD_FL1CIDXFTHRESHO_F     FW_IQ_CMD_FL1CIDXFTHRESHO_V(1U)
1586
1587 #define FW_IQ_CMD_FL1CIDXFTHRESH_S      0
1588 #define FW_IQ_CMD_FL1CIDXFTHRESH_V(x)   ((x) << FW_IQ_CMD_FL1CIDXFTHRESH_S)
1589
1590 struct fw_eq_eth_cmd {
1591         __be32 op_to_vfn;
1592         __be32 alloc_to_len16;
1593         __be32 eqid_pkd;
1594         __be32 physeqid_pkd;
1595         __be32 fetchszm_to_iqid;
1596         __be32 dcaen_to_eqsize;
1597         __be64 eqaddr;
1598         __be32 viid_pkd;
1599         __be32 r8_lo;
1600         __be64 r9;
1601 };
1602
1603 #define FW_EQ_ETH_CMD_PFN_S     8
1604 #define FW_EQ_ETH_CMD_PFN_V(x)  ((x) << FW_EQ_ETH_CMD_PFN_S)
1605
1606 #define FW_EQ_ETH_CMD_VFN_S     0
1607 #define FW_EQ_ETH_CMD_VFN_V(x)  ((x) << FW_EQ_ETH_CMD_VFN_S)
1608
1609 #define FW_EQ_ETH_CMD_ALLOC_S           31
1610 #define FW_EQ_ETH_CMD_ALLOC_V(x)        ((x) << FW_EQ_ETH_CMD_ALLOC_S)
1611 #define FW_EQ_ETH_CMD_ALLOC_F   FW_EQ_ETH_CMD_ALLOC_V(1U)
1612
1613 #define FW_EQ_ETH_CMD_FREE_S    30
1614 #define FW_EQ_ETH_CMD_FREE_V(x) ((x) << FW_EQ_ETH_CMD_FREE_S)
1615 #define FW_EQ_ETH_CMD_FREE_F    FW_EQ_ETH_CMD_FREE_V(1U)
1616
1617 #define FW_EQ_ETH_CMD_MODIFY_S          29
1618 #define FW_EQ_ETH_CMD_MODIFY_V(x)       ((x) << FW_EQ_ETH_CMD_MODIFY_S)
1619 #define FW_EQ_ETH_CMD_MODIFY_F  FW_EQ_ETH_CMD_MODIFY_V(1U)
1620
1621 #define FW_EQ_ETH_CMD_EQSTART_S         28
1622 #define FW_EQ_ETH_CMD_EQSTART_V(x)      ((x) << FW_EQ_ETH_CMD_EQSTART_S)
1623 #define FW_EQ_ETH_CMD_EQSTART_F FW_EQ_ETH_CMD_EQSTART_V(1U)
1624
1625 #define FW_EQ_ETH_CMD_EQSTOP_S          27
1626 #define FW_EQ_ETH_CMD_EQSTOP_V(x)       ((x) << FW_EQ_ETH_CMD_EQSTOP_S)
1627 #define FW_EQ_ETH_CMD_EQSTOP_F  FW_EQ_ETH_CMD_EQSTOP_V(1U)
1628
1629 #define FW_EQ_ETH_CMD_EQID_S    0
1630 #define FW_EQ_ETH_CMD_EQID_M    0xfffff
1631 #define FW_EQ_ETH_CMD_EQID_V(x) ((x) << FW_EQ_ETH_CMD_EQID_S)
1632 #define FW_EQ_ETH_CMD_EQID_G(x) \
1633         (((x) >> FW_EQ_ETH_CMD_EQID_S) & FW_EQ_ETH_CMD_EQID_M)
1634
1635 #define FW_EQ_ETH_CMD_PHYSEQID_S        0
1636 #define FW_EQ_ETH_CMD_PHYSEQID_M        0xfffff
1637 #define FW_EQ_ETH_CMD_PHYSEQID_V(x)     ((x) << FW_EQ_ETH_CMD_PHYSEQID_S)
1638 #define FW_EQ_ETH_CMD_PHYSEQID_G(x)     \
1639         (((x) >> FW_EQ_ETH_CMD_PHYSEQID_S) & FW_EQ_ETH_CMD_PHYSEQID_M)
1640
1641 #define FW_EQ_ETH_CMD_FETCHSZM_S        26
1642 #define FW_EQ_ETH_CMD_FETCHSZM_V(x)     ((x) << FW_EQ_ETH_CMD_FETCHSZM_S)
1643 #define FW_EQ_ETH_CMD_FETCHSZM_F        FW_EQ_ETH_CMD_FETCHSZM_V(1U)
1644
1645 #define FW_EQ_ETH_CMD_STATUSPGNS_S      25
1646 #define FW_EQ_ETH_CMD_STATUSPGNS_V(x)   ((x) << FW_EQ_ETH_CMD_STATUSPGNS_S)
1647
1648 #define FW_EQ_ETH_CMD_STATUSPGRO_S      24
1649 #define FW_EQ_ETH_CMD_STATUSPGRO_V(x)   ((x) << FW_EQ_ETH_CMD_STATUSPGRO_S)
1650
1651 #define FW_EQ_ETH_CMD_FETCHNS_S         23
1652 #define FW_EQ_ETH_CMD_FETCHNS_V(x)      ((x) << FW_EQ_ETH_CMD_FETCHNS_S)
1653
1654 #define FW_EQ_ETH_CMD_FETCHRO_S         22
1655 #define FW_EQ_ETH_CMD_FETCHRO_V(x)      ((x) << FW_EQ_ETH_CMD_FETCHRO_S)
1656 #define FW_EQ_ETH_CMD_FETCHRO_F         FW_EQ_ETH_CMD_FETCHRO_V(1U)
1657
1658 #define FW_EQ_ETH_CMD_HOSTFCMODE_S      20
1659 #define FW_EQ_ETH_CMD_HOSTFCMODE_V(x)   ((x) << FW_EQ_ETH_CMD_HOSTFCMODE_S)
1660
1661 #define FW_EQ_ETH_CMD_CPRIO_S           19
1662 #define FW_EQ_ETH_CMD_CPRIO_V(x)        ((x) << FW_EQ_ETH_CMD_CPRIO_S)
1663
1664 #define FW_EQ_ETH_CMD_ONCHIP_S          18
1665 #define FW_EQ_ETH_CMD_ONCHIP_V(x)       ((x) << FW_EQ_ETH_CMD_ONCHIP_S)
1666
1667 #define FW_EQ_ETH_CMD_PCIECHN_S         16
1668 #define FW_EQ_ETH_CMD_PCIECHN_V(x)      ((x) << FW_EQ_ETH_CMD_PCIECHN_S)
1669
1670 #define FW_EQ_ETH_CMD_IQID_S    0
1671 #define FW_EQ_ETH_CMD_IQID_V(x) ((x) << FW_EQ_ETH_CMD_IQID_S)
1672
1673 #define FW_EQ_ETH_CMD_DCAEN_S           31
1674 #define FW_EQ_ETH_CMD_DCAEN_V(x)        ((x) << FW_EQ_ETH_CMD_DCAEN_S)
1675
1676 #define FW_EQ_ETH_CMD_DCACPU_S          26
1677 #define FW_EQ_ETH_CMD_DCACPU_V(x)       ((x) << FW_EQ_ETH_CMD_DCACPU_S)
1678
1679 #define FW_EQ_ETH_CMD_FBMIN_S           23
1680 #define FW_EQ_ETH_CMD_FBMIN_V(x)        ((x) << FW_EQ_ETH_CMD_FBMIN_S)
1681
1682 #define FW_EQ_ETH_CMD_FBMAX_S           20
1683 #define FW_EQ_ETH_CMD_FBMAX_V(x)        ((x) << FW_EQ_ETH_CMD_FBMAX_S)
1684
1685 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_S    19
1686 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESHO_S)
1687
1688 #define FW_EQ_ETH_CMD_CIDXFTHRESH_S     16
1689 #define FW_EQ_ETH_CMD_CIDXFTHRESH_V(x)  ((x) << FW_EQ_ETH_CMD_CIDXFTHRESH_S)
1690
1691 #define FW_EQ_ETH_CMD_EQSIZE_S          0
1692 #define FW_EQ_ETH_CMD_EQSIZE_V(x)       ((x) << FW_EQ_ETH_CMD_EQSIZE_S)
1693
1694 #define FW_EQ_ETH_CMD_AUTOEQUEQE_S      30
1695 #define FW_EQ_ETH_CMD_AUTOEQUEQE_V(x)   ((x) << FW_EQ_ETH_CMD_AUTOEQUEQE_S)
1696 #define FW_EQ_ETH_CMD_AUTOEQUEQE_F      FW_EQ_ETH_CMD_AUTOEQUEQE_V(1U)
1697
1698 #define FW_EQ_ETH_CMD_VIID_S    16
1699 #define FW_EQ_ETH_CMD_VIID_V(x) ((x) << FW_EQ_ETH_CMD_VIID_S)
1700
1701 struct fw_eq_ctrl_cmd {
1702         __be32 op_to_vfn;
1703         __be32 alloc_to_len16;
1704         __be32 cmpliqid_eqid;
1705         __be32 physeqid_pkd;
1706         __be32 fetchszm_to_iqid;
1707         __be32 dcaen_to_eqsize;
1708         __be64 eqaddr;
1709 };
1710
1711 #define FW_EQ_CTRL_CMD_PFN_S    8
1712 #define FW_EQ_CTRL_CMD_PFN_V(x) ((x) << FW_EQ_CTRL_CMD_PFN_S)
1713
1714 #define FW_EQ_CTRL_CMD_VFN_S    0
1715 #define FW_EQ_CTRL_CMD_VFN_V(x) ((x) << FW_EQ_CTRL_CMD_VFN_S)
1716
1717 #define FW_EQ_CTRL_CMD_ALLOC_S          31
1718 #define FW_EQ_CTRL_CMD_ALLOC_V(x)       ((x) << FW_EQ_CTRL_CMD_ALLOC_S)
1719 #define FW_EQ_CTRL_CMD_ALLOC_F          FW_EQ_CTRL_CMD_ALLOC_V(1U)
1720
1721 #define FW_EQ_CTRL_CMD_FREE_S           30
1722 #define FW_EQ_CTRL_CMD_FREE_V(x)        ((x) << FW_EQ_CTRL_CMD_FREE_S)
1723 #define FW_EQ_CTRL_CMD_FREE_F           FW_EQ_CTRL_CMD_FREE_V(1U)
1724
1725 #define FW_EQ_CTRL_CMD_MODIFY_S         29
1726 #define FW_EQ_CTRL_CMD_MODIFY_V(x)      ((x) << FW_EQ_CTRL_CMD_MODIFY_S)
1727 #define FW_EQ_CTRL_CMD_MODIFY_F         FW_EQ_CTRL_CMD_MODIFY_V(1U)
1728
1729 #define FW_EQ_CTRL_CMD_EQSTART_S        28
1730 #define FW_EQ_CTRL_CMD_EQSTART_V(x)     ((x) << FW_EQ_CTRL_CMD_EQSTART_S)
1731 #define FW_EQ_CTRL_CMD_EQSTART_F        FW_EQ_CTRL_CMD_EQSTART_V(1U)
1732
1733 #define FW_EQ_CTRL_CMD_EQSTOP_S         27
1734 #define FW_EQ_CTRL_CMD_EQSTOP_V(x)      ((x) << FW_EQ_CTRL_CMD_EQSTOP_S)
1735 #define FW_EQ_CTRL_CMD_EQSTOP_F         FW_EQ_CTRL_CMD_EQSTOP_V(1U)
1736
1737 #define FW_EQ_CTRL_CMD_CMPLIQID_S       20
1738 #define FW_EQ_CTRL_CMD_CMPLIQID_V(x)    ((x) << FW_EQ_CTRL_CMD_CMPLIQID_S)
1739
1740 #define FW_EQ_CTRL_CMD_EQID_S           0
1741 #define FW_EQ_CTRL_CMD_EQID_M           0xfffff
1742 #define FW_EQ_CTRL_CMD_EQID_V(x)        ((x) << FW_EQ_CTRL_CMD_EQID_S)
1743 #define FW_EQ_CTRL_CMD_EQID_G(x)        \
1744         (((x) >> FW_EQ_CTRL_CMD_EQID_S) & FW_EQ_CTRL_CMD_EQID_M)
1745
1746 #define FW_EQ_CTRL_CMD_PHYSEQID_S       0
1747 #define FW_EQ_CTRL_CMD_PHYSEQID_M       0xfffff
1748 #define FW_EQ_CTRL_CMD_PHYSEQID_G(x)    \
1749         (((x) >> FW_EQ_CTRL_CMD_PHYSEQID_S) & FW_EQ_CTRL_CMD_PHYSEQID_M)
1750
1751 #define FW_EQ_CTRL_CMD_FETCHSZM_S       26
1752 #define FW_EQ_CTRL_CMD_FETCHSZM_V(x)    ((x) << FW_EQ_CTRL_CMD_FETCHSZM_S)
1753 #define FW_EQ_CTRL_CMD_FETCHSZM_F       FW_EQ_CTRL_CMD_FETCHSZM_V(1U)
1754
1755 #define FW_EQ_CTRL_CMD_STATUSPGNS_S     25
1756 #define FW_EQ_CTRL_CMD_STATUSPGNS_V(x)  ((x) << FW_EQ_CTRL_CMD_STATUSPGNS_S)
1757 #define FW_EQ_CTRL_CMD_STATUSPGNS_F     FW_EQ_CTRL_CMD_STATUSPGNS_V(1U)
1758
1759 #define FW_EQ_CTRL_CMD_STATUSPGRO_S     24
1760 #define FW_EQ_CTRL_CMD_STATUSPGRO_V(x)  ((x) << FW_EQ_CTRL_CMD_STATUSPGRO_S)
1761 #define FW_EQ_CTRL_CMD_STATUSPGRO_F     FW_EQ_CTRL_CMD_STATUSPGRO_V(1U)
1762
1763 #define FW_EQ_CTRL_CMD_FETCHNS_S        23
1764 #define FW_EQ_CTRL_CMD_FETCHNS_V(x)     ((x) << FW_EQ_CTRL_CMD_FETCHNS_S)
1765 #define FW_EQ_CTRL_CMD_FETCHNS_F        FW_EQ_CTRL_CMD_FETCHNS_V(1U)
1766
1767 #define FW_EQ_CTRL_CMD_FETCHRO_S        22
1768 #define FW_EQ_CTRL_CMD_FETCHRO_V(x)     ((x) << FW_EQ_CTRL_CMD_FETCHRO_S)
1769 #define FW_EQ_CTRL_CMD_FETCHRO_F        FW_EQ_CTRL_CMD_FETCHRO_V(1U)
1770
1771 #define FW_EQ_CTRL_CMD_HOSTFCMODE_S     20
1772 #define FW_EQ_CTRL_CMD_HOSTFCMODE_V(x)  ((x) << FW_EQ_CTRL_CMD_HOSTFCMODE_S)
1773
1774 #define FW_EQ_CTRL_CMD_CPRIO_S          19
1775 #define FW_EQ_CTRL_CMD_CPRIO_V(x)       ((x) << FW_EQ_CTRL_CMD_CPRIO_S)
1776
1777 #define FW_EQ_CTRL_CMD_ONCHIP_S         18
1778 #define FW_EQ_CTRL_CMD_ONCHIP_V(x)      ((x) << FW_EQ_CTRL_CMD_ONCHIP_S)
1779
1780 #define FW_EQ_CTRL_CMD_PCIECHN_S        16
1781 #define FW_EQ_CTRL_CMD_PCIECHN_V(x)     ((x) << FW_EQ_CTRL_CMD_PCIECHN_S)
1782
1783 #define FW_EQ_CTRL_CMD_IQID_S           0
1784 #define FW_EQ_CTRL_CMD_IQID_V(x)        ((x) << FW_EQ_CTRL_CMD_IQID_S)
1785
1786 #define FW_EQ_CTRL_CMD_DCAEN_S          31
1787 #define FW_EQ_CTRL_CMD_DCAEN_V(x)       ((x) << FW_EQ_CTRL_CMD_DCAEN_S)
1788
1789 #define FW_EQ_CTRL_CMD_DCACPU_S         26
1790 #define FW_EQ_CTRL_CMD_DCACPU_V(x)      ((x) << FW_EQ_CTRL_CMD_DCACPU_S)
1791
1792 #define FW_EQ_CTRL_CMD_FBMIN_S          23
1793 #define FW_EQ_CTRL_CMD_FBMIN_V(x)       ((x) << FW_EQ_CTRL_CMD_FBMIN_S)
1794
1795 #define FW_EQ_CTRL_CMD_FBMAX_S          20
1796 #define FW_EQ_CTRL_CMD_FBMAX_V(x)       ((x) << FW_EQ_CTRL_CMD_FBMAX_S)
1797
1798 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_S           19
1799 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_V(x)        \
1800         ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESHO_S)
1801
1802 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_S    16
1803 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESH_S)
1804
1805 #define FW_EQ_CTRL_CMD_EQSIZE_S         0
1806 #define FW_EQ_CTRL_CMD_EQSIZE_V(x)      ((x) << FW_EQ_CTRL_CMD_EQSIZE_S)
1807
1808 struct fw_eq_ofld_cmd {
1809         __be32 op_to_vfn;
1810         __be32 alloc_to_len16;
1811         __be32 eqid_pkd;
1812         __be32 physeqid_pkd;
1813         __be32 fetchszm_to_iqid;
1814         __be32 dcaen_to_eqsize;
1815         __be64 eqaddr;
1816 };
1817
1818 #define FW_EQ_OFLD_CMD_PFN_S    8
1819 #define FW_EQ_OFLD_CMD_PFN_V(x) ((x) << FW_EQ_OFLD_CMD_PFN_S)
1820
1821 #define FW_EQ_OFLD_CMD_VFN_S    0
1822 #define FW_EQ_OFLD_CMD_VFN_V(x) ((x) << FW_EQ_OFLD_CMD_VFN_S)
1823
1824 #define FW_EQ_OFLD_CMD_ALLOC_S          31
1825 #define FW_EQ_OFLD_CMD_ALLOC_V(x)       ((x) << FW_EQ_OFLD_CMD_ALLOC_S)
1826 #define FW_EQ_OFLD_CMD_ALLOC_F          FW_EQ_OFLD_CMD_ALLOC_V(1U)
1827
1828 #define FW_EQ_OFLD_CMD_FREE_S           30
1829 #define FW_EQ_OFLD_CMD_FREE_V(x)        ((x) << FW_EQ_OFLD_CMD_FREE_S)
1830 #define FW_EQ_OFLD_CMD_FREE_F           FW_EQ_OFLD_CMD_FREE_V(1U)
1831
1832 #define FW_EQ_OFLD_CMD_MODIFY_S         29
1833 #define FW_EQ_OFLD_CMD_MODIFY_V(x)      ((x) << FW_EQ_OFLD_CMD_MODIFY_S)
1834 #define FW_EQ_OFLD_CMD_MODIFY_F         FW_EQ_OFLD_CMD_MODIFY_V(1U)
1835
1836 #define FW_EQ_OFLD_CMD_EQSTART_S        28
1837 #define FW_EQ_OFLD_CMD_EQSTART_V(x)     ((x) << FW_EQ_OFLD_CMD_EQSTART_S)
1838 #define FW_EQ_OFLD_CMD_EQSTART_F        FW_EQ_OFLD_CMD_EQSTART_V(1U)
1839
1840 #define FW_EQ_OFLD_CMD_EQSTOP_S         27
1841 #define FW_EQ_OFLD_CMD_EQSTOP_V(x)      ((x) << FW_EQ_OFLD_CMD_EQSTOP_S)
1842 #define FW_EQ_OFLD_CMD_EQSTOP_F         FW_EQ_OFLD_CMD_EQSTOP_V(1U)
1843
1844 #define FW_EQ_OFLD_CMD_EQID_S           0
1845 #define FW_EQ_OFLD_CMD_EQID_M           0xfffff
1846 #define FW_EQ_OFLD_CMD_EQID_V(x)        ((x) << FW_EQ_OFLD_CMD_EQID_S)
1847 #define FW_EQ_OFLD_CMD_EQID_G(x)        \
1848         (((x) >> FW_EQ_OFLD_CMD_EQID_S) & FW_EQ_OFLD_CMD_EQID_M)
1849
1850 #define FW_EQ_OFLD_CMD_PHYSEQID_S       0
1851 #define FW_EQ_OFLD_CMD_PHYSEQID_M       0xfffff
1852 #define FW_EQ_OFLD_CMD_PHYSEQID_G(x)    \
1853         (((x) >> FW_EQ_OFLD_CMD_PHYSEQID_S) & FW_EQ_OFLD_CMD_PHYSEQID_M)
1854
1855 #define FW_EQ_OFLD_CMD_FETCHSZM_S       26
1856 #define FW_EQ_OFLD_CMD_FETCHSZM_V(x)    ((x) << FW_EQ_OFLD_CMD_FETCHSZM_S)
1857
1858 #define FW_EQ_OFLD_CMD_STATUSPGNS_S     25
1859 #define FW_EQ_OFLD_CMD_STATUSPGNS_V(x)  ((x) << FW_EQ_OFLD_CMD_STATUSPGNS_S)
1860
1861 #define FW_EQ_OFLD_CMD_STATUSPGRO_S     24
1862 #define FW_EQ_OFLD_CMD_STATUSPGRO_V(x)  ((x) << FW_EQ_OFLD_CMD_STATUSPGRO_S)
1863
1864 #define FW_EQ_OFLD_CMD_FETCHNS_S        23
1865 #define FW_EQ_OFLD_CMD_FETCHNS_V(x)     ((x) << FW_EQ_OFLD_CMD_FETCHNS_S)
1866
1867 #define FW_EQ_OFLD_CMD_FETCHRO_S        22
1868 #define FW_EQ_OFLD_CMD_FETCHRO_V(x)     ((x) << FW_EQ_OFLD_CMD_FETCHRO_S)
1869 #define FW_EQ_OFLD_CMD_FETCHRO_F        FW_EQ_OFLD_CMD_FETCHRO_V(1U)
1870
1871 #define FW_EQ_OFLD_CMD_HOSTFCMODE_S     20
1872 #define FW_EQ_OFLD_CMD_HOSTFCMODE_V(x)  ((x) << FW_EQ_OFLD_CMD_HOSTFCMODE_S)
1873
1874 #define FW_EQ_OFLD_CMD_CPRIO_S          19
1875 #define FW_EQ_OFLD_CMD_CPRIO_V(x)       ((x) << FW_EQ_OFLD_CMD_CPRIO_S)
1876
1877 #define FW_EQ_OFLD_CMD_ONCHIP_S         18
1878 #define FW_EQ_OFLD_CMD_ONCHIP_V(x)      ((x) << FW_EQ_OFLD_CMD_ONCHIP_S)
1879
1880 #define FW_EQ_OFLD_CMD_PCIECHN_S        16
1881 #define FW_EQ_OFLD_CMD_PCIECHN_V(x)     ((x) << FW_EQ_OFLD_CMD_PCIECHN_S)
1882
1883 #define FW_EQ_OFLD_CMD_IQID_S           0
1884 #define FW_EQ_OFLD_CMD_IQID_V(x)        ((x) << FW_EQ_OFLD_CMD_IQID_S)
1885
1886 #define FW_EQ_OFLD_CMD_DCAEN_S          31
1887 #define FW_EQ_OFLD_CMD_DCAEN_V(x)       ((x) << FW_EQ_OFLD_CMD_DCAEN_S)
1888
1889 #define FW_EQ_OFLD_CMD_DCACPU_S         26
1890 #define FW_EQ_OFLD_CMD_DCACPU_V(x)      ((x) << FW_EQ_OFLD_CMD_DCACPU_S)
1891
1892 #define FW_EQ_OFLD_CMD_FBMIN_S          23
1893 #define FW_EQ_OFLD_CMD_FBMIN_V(x)       ((x) << FW_EQ_OFLD_CMD_FBMIN_S)
1894
1895 #define FW_EQ_OFLD_CMD_FBMAX_S          20
1896 #define FW_EQ_OFLD_CMD_FBMAX_V(x)       ((x) << FW_EQ_OFLD_CMD_FBMAX_S)
1897
1898 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_S           19
1899 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_V(x)        \
1900         ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESHO_S)
1901
1902 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_S    16
1903 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESH_S)
1904
1905 #define FW_EQ_OFLD_CMD_EQSIZE_S         0
1906 #define FW_EQ_OFLD_CMD_EQSIZE_V(x)      ((x) << FW_EQ_OFLD_CMD_EQSIZE_S)
1907
1908 /*
1909  * Macros for VIID parsing:
1910  * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
1911  */
1912
1913 #define FW_VIID_PFN_S           8
1914 #define FW_VIID_PFN_M           0x7
1915 #define FW_VIID_PFN_G(x)        (((x) >> FW_VIID_PFN_S) & FW_VIID_PFN_M)
1916
1917 #define FW_VIID_VIVLD_S         7
1918 #define FW_VIID_VIVLD_M         0x1
1919 #define FW_VIID_VIVLD_G(x)      (((x) >> FW_VIID_VIVLD_S) & FW_VIID_VIVLD_M)
1920
1921 #define FW_VIID_VIN_S           0
1922 #define FW_VIID_VIN_M           0x7F
1923 #define FW_VIID_VIN_G(x)        (((x) >> FW_VIID_VIN_S) & FW_VIID_VIN_M)
1924
1925 struct fw_vi_cmd {
1926         __be32 op_to_vfn;
1927         __be32 alloc_to_len16;
1928         __be16 type_viid;
1929         u8 mac[6];
1930         u8 portid_pkd;
1931         u8 nmac;
1932         u8 nmac0[6];
1933         __be16 rsssize_pkd;
1934         u8 nmac1[6];
1935         __be16 idsiiq_pkd;
1936         u8 nmac2[6];
1937         __be16 idseiq_pkd;
1938         u8 nmac3[6];
1939         __be64 r9;
1940         __be64 r10;
1941 };
1942
1943 #define FW_VI_CMD_PFN_S         8
1944 #define FW_VI_CMD_PFN_V(x)      ((x) << FW_VI_CMD_PFN_S)
1945
1946 #define FW_VI_CMD_VFN_S         0
1947 #define FW_VI_CMD_VFN_V(x)      ((x) << FW_VI_CMD_VFN_S)
1948
1949 #define FW_VI_CMD_ALLOC_S       31
1950 #define FW_VI_CMD_ALLOC_V(x)    ((x) << FW_VI_CMD_ALLOC_S)
1951 #define FW_VI_CMD_ALLOC_F       FW_VI_CMD_ALLOC_V(1U)
1952
1953 #define FW_VI_CMD_FREE_S        30
1954 #define FW_VI_CMD_FREE_V(x)     ((x) << FW_VI_CMD_FREE_S)
1955 #define FW_VI_CMD_FREE_F        FW_VI_CMD_FREE_V(1U)
1956
1957 #define FW_VI_CMD_VIID_S        0
1958 #define FW_VI_CMD_VIID_M        0xfff
1959 #define FW_VI_CMD_VIID_V(x)     ((x) << FW_VI_CMD_VIID_S)
1960 #define FW_VI_CMD_VIID_G(x)     (((x) >> FW_VI_CMD_VIID_S) & FW_VI_CMD_VIID_M)
1961
1962 #define FW_VI_CMD_PORTID_S      4
1963 #define FW_VI_CMD_PORTID_M      0xf
1964 #define FW_VI_CMD_PORTID_V(x)   ((x) << FW_VI_CMD_PORTID_S)
1965 #define FW_VI_CMD_PORTID_G(x)   \
1966         (((x) >> FW_VI_CMD_PORTID_S) & FW_VI_CMD_PORTID_M)
1967
1968 #define FW_VI_CMD_RSSSIZE_S     0
1969 #define FW_VI_CMD_RSSSIZE_M     0x7ff
1970 #define FW_VI_CMD_RSSSIZE_G(x)  \
1971         (((x) >> FW_VI_CMD_RSSSIZE_S) & FW_VI_CMD_RSSSIZE_M)
1972
1973 /* Special VI_MAC command index ids */
1974 #define FW_VI_MAC_ADD_MAC               0x3FF
1975 #define FW_VI_MAC_ADD_PERSIST_MAC       0x3FE
1976 #define FW_VI_MAC_MAC_BASED_FREE        0x3FD
1977 #define FW_CLS_TCAM_NUM_ENTRIES         336
1978
1979 enum fw_vi_mac_smac {
1980         FW_VI_MAC_MPS_TCAM_ENTRY,
1981         FW_VI_MAC_MPS_TCAM_ONLY,
1982         FW_VI_MAC_SMT_ONLY,
1983         FW_VI_MAC_SMT_AND_MPSTCAM
1984 };
1985
1986 enum fw_vi_mac_result {
1987         FW_VI_MAC_R_SUCCESS,
1988         FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
1989         FW_VI_MAC_R_SMAC_FAIL,
1990         FW_VI_MAC_R_F_ACL_CHECK
1991 };
1992
1993 struct fw_vi_mac_cmd {
1994         __be32 op_to_viid;
1995         __be32 freemacs_to_len16;
1996         union fw_vi_mac {
1997                 struct fw_vi_mac_exact {
1998                         __be16 valid_to_idx;
1999                         u8 macaddr[6];
2000                 } exact[7];
2001                 struct fw_vi_mac_hash {
2002                         __be64 hashvec;
2003                 } hash;
2004         } u;
2005 };
2006
2007 #define FW_VI_MAC_CMD_VIID_S    0
2008 #define FW_VI_MAC_CMD_VIID_V(x) ((x) << FW_VI_MAC_CMD_VIID_S)
2009
2010 #define FW_VI_MAC_CMD_FREEMACS_S        31
2011 #define FW_VI_MAC_CMD_FREEMACS_V(x)     ((x) << FW_VI_MAC_CMD_FREEMACS_S)
2012
2013 #define FW_VI_MAC_CMD_HASHVECEN_S       23
2014 #define FW_VI_MAC_CMD_HASHVECEN_V(x)    ((x) << FW_VI_MAC_CMD_HASHVECEN_S)
2015 #define FW_VI_MAC_CMD_HASHVECEN_F       FW_VI_MAC_CMD_HASHVECEN_V(1U)
2016
2017 #define FW_VI_MAC_CMD_HASHUNIEN_S       22
2018 #define FW_VI_MAC_CMD_HASHUNIEN_V(x)    ((x) << FW_VI_MAC_CMD_HASHUNIEN_S)
2019
2020 #define FW_VI_MAC_CMD_VALID_S           15
2021 #define FW_VI_MAC_CMD_VALID_V(x)        ((x) << FW_VI_MAC_CMD_VALID_S)
2022 #define FW_VI_MAC_CMD_VALID_F   FW_VI_MAC_CMD_VALID_V(1U)
2023
2024 #define FW_VI_MAC_CMD_PRIO_S    12
2025 #define FW_VI_MAC_CMD_PRIO_V(x) ((x) << FW_VI_MAC_CMD_PRIO_S)
2026
2027 #define FW_VI_MAC_CMD_SMAC_RESULT_S     10
2028 #define FW_VI_MAC_CMD_SMAC_RESULT_M     0x3
2029 #define FW_VI_MAC_CMD_SMAC_RESULT_V(x)  ((x) << FW_VI_MAC_CMD_SMAC_RESULT_S)
2030 #define FW_VI_MAC_CMD_SMAC_RESULT_G(x)  \
2031         (((x) >> FW_VI_MAC_CMD_SMAC_RESULT_S) & FW_VI_MAC_CMD_SMAC_RESULT_M)
2032
2033 #define FW_VI_MAC_CMD_IDX_S     0
2034 #define FW_VI_MAC_CMD_IDX_M     0x3ff
2035 #define FW_VI_MAC_CMD_IDX_V(x)  ((x) << FW_VI_MAC_CMD_IDX_S)
2036 #define FW_VI_MAC_CMD_IDX_G(x)  \
2037         (((x) >> FW_VI_MAC_CMD_IDX_S) & FW_VI_MAC_CMD_IDX_M)
2038
2039 #define FW_RXMODE_MTU_NO_CHG    65535
2040
2041 struct fw_vi_rxmode_cmd {
2042         __be32 op_to_viid;
2043         __be32 retval_len16;
2044         __be32 mtu_to_vlanexen;
2045         __be32 r4_lo;
2046 };
2047
2048 #define FW_VI_RXMODE_CMD_VIID_S         0
2049 #define FW_VI_RXMODE_CMD_VIID_V(x)      ((x) << FW_VI_RXMODE_CMD_VIID_S)
2050
2051 #define FW_VI_RXMODE_CMD_MTU_S          16
2052 #define FW_VI_RXMODE_CMD_MTU_M          0xffff
2053 #define FW_VI_RXMODE_CMD_MTU_V(x)       ((x) << FW_VI_RXMODE_CMD_MTU_S)
2054
2055 #define FW_VI_RXMODE_CMD_PROMISCEN_S    14
2056 #define FW_VI_RXMODE_CMD_PROMISCEN_M    0x3
2057 #define FW_VI_RXMODE_CMD_PROMISCEN_V(x) ((x) << FW_VI_RXMODE_CMD_PROMISCEN_S)
2058
2059 #define FW_VI_RXMODE_CMD_ALLMULTIEN_S           12
2060 #define FW_VI_RXMODE_CMD_ALLMULTIEN_M           0x3
2061 #define FW_VI_RXMODE_CMD_ALLMULTIEN_V(x)        \
2062         ((x) << FW_VI_RXMODE_CMD_ALLMULTIEN_S)
2063
2064 #define FW_VI_RXMODE_CMD_BROADCASTEN_S          10
2065 #define FW_VI_RXMODE_CMD_BROADCASTEN_M          0x3
2066 #define FW_VI_RXMODE_CMD_BROADCASTEN_V(x)       \
2067         ((x) << FW_VI_RXMODE_CMD_BROADCASTEN_S)
2068
2069 #define FW_VI_RXMODE_CMD_VLANEXEN_S     8
2070 #define FW_VI_RXMODE_CMD_VLANEXEN_M     0x3
2071 #define FW_VI_RXMODE_CMD_VLANEXEN_V(x)  ((x) << FW_VI_RXMODE_CMD_VLANEXEN_S)
2072
2073 struct fw_vi_enable_cmd {
2074         __be32 op_to_viid;
2075         __be32 ien_to_len16;
2076         __be16 blinkdur;
2077         __be16 r3;
2078         __be32 r4;
2079 };
2080
2081 #define FW_VI_ENABLE_CMD_VIID_S         0
2082 #define FW_VI_ENABLE_CMD_VIID_V(x)      ((x) << FW_VI_ENABLE_CMD_VIID_S)
2083
2084 #define FW_VI_ENABLE_CMD_IEN_S          31
2085 #define FW_VI_ENABLE_CMD_IEN_V(x)       ((x) << FW_VI_ENABLE_CMD_IEN_S)
2086
2087 #define FW_VI_ENABLE_CMD_EEN_S          30
2088 #define FW_VI_ENABLE_CMD_EEN_V(x)       ((x) << FW_VI_ENABLE_CMD_EEN_S)
2089
2090 #define FW_VI_ENABLE_CMD_LED_S          29
2091 #define FW_VI_ENABLE_CMD_LED_V(x)       ((x) << FW_VI_ENABLE_CMD_LED_S)
2092 #define FW_VI_ENABLE_CMD_LED_F  FW_VI_ENABLE_CMD_LED_V(1U)
2093
2094 #define FW_VI_ENABLE_CMD_DCB_INFO_S     28
2095 #define FW_VI_ENABLE_CMD_DCB_INFO_V(x)  ((x) << FW_VI_ENABLE_CMD_DCB_INFO_S)
2096
2097 /* VI VF stats offset definitions */
2098 #define VI_VF_NUM_STATS 16
2099 enum fw_vi_stats_vf_index {
2100         FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
2101         FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
2102         FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
2103         FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
2104         FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
2105         FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
2106         FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
2107         FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
2108         FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
2109         FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
2110         FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
2111         FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
2112         FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
2113         FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
2114         FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
2115         FW_VI_VF_STAT_RX_ERR_FRAMES_IX
2116 };
2117
2118 /* VI PF stats offset definitions */
2119 #define VI_PF_NUM_STATS 17
2120 enum fw_vi_stats_pf_index {
2121         FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
2122         FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
2123         FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
2124         FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
2125         FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
2126         FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
2127         FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
2128         FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
2129         FW_VI_PF_STAT_RX_BYTES_IX,
2130         FW_VI_PF_STAT_RX_FRAMES_IX,
2131         FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
2132         FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
2133         FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
2134         FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
2135         FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
2136         FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
2137         FW_VI_PF_STAT_RX_ERR_FRAMES_IX
2138 };
2139
2140 struct fw_vi_stats_cmd {
2141         __be32 op_to_viid;
2142         __be32 retval_len16;
2143         union fw_vi_stats {
2144                 struct fw_vi_stats_ctl {
2145                         __be16 nstats_ix;
2146                         __be16 r6;
2147                         __be32 r7;
2148                         __be64 stat0;
2149                         __be64 stat1;
2150                         __be64 stat2;
2151                         __be64 stat3;
2152                         __be64 stat4;
2153                         __be64 stat5;
2154                 } ctl;
2155                 struct fw_vi_stats_pf {
2156                         __be64 tx_bcast_bytes;
2157                         __be64 tx_bcast_frames;
2158                         __be64 tx_mcast_bytes;
2159                         __be64 tx_mcast_frames;
2160                         __be64 tx_ucast_bytes;
2161                         __be64 tx_ucast_frames;
2162                         __be64 tx_offload_bytes;
2163                         __be64 tx_offload_frames;
2164                         __be64 rx_pf_bytes;
2165                         __be64 rx_pf_frames;
2166                         __be64 rx_bcast_bytes;
2167                         __be64 rx_bcast_frames;
2168                         __be64 rx_mcast_bytes;
2169                         __be64 rx_mcast_frames;
2170                         __be64 rx_ucast_bytes;
2171                         __be64 rx_ucast_frames;
2172                         __be64 rx_err_frames;
2173                 } pf;
2174                 struct fw_vi_stats_vf {
2175                         __be64 tx_bcast_bytes;
2176                         __be64 tx_bcast_frames;
2177                         __be64 tx_mcast_bytes;
2178                         __be64 tx_mcast_frames;
2179                         __be64 tx_ucast_bytes;
2180                         __be64 tx_ucast_frames;
2181                         __be64 tx_drop_frames;
2182                         __be64 tx_offload_bytes;
2183                         __be64 tx_offload_frames;
2184                         __be64 rx_bcast_bytes;
2185                         __be64 rx_bcast_frames;
2186                         __be64 rx_mcast_bytes;
2187                         __be64 rx_mcast_frames;
2188                         __be64 rx_ucast_bytes;
2189                         __be64 rx_ucast_frames;
2190                         __be64 rx_err_frames;
2191                 } vf;
2192         } u;
2193 };
2194
2195 #define FW_VI_STATS_CMD_VIID_S          0
2196 #define FW_VI_STATS_CMD_VIID_V(x)       ((x) << FW_VI_STATS_CMD_VIID_S)
2197
2198 #define FW_VI_STATS_CMD_NSTATS_S        12
2199 #define FW_VI_STATS_CMD_NSTATS_V(x)     ((x) << FW_VI_STATS_CMD_NSTATS_S)
2200
2201 #define FW_VI_STATS_CMD_IX_S    0
2202 #define FW_VI_STATS_CMD_IX_V(x) ((x) << FW_VI_STATS_CMD_IX_S)
2203
2204 struct fw_acl_mac_cmd {
2205         __be32 op_to_vfn;
2206         __be32 en_to_len16;
2207         u8 nmac;
2208         u8 r3[7];
2209         __be16 r4;
2210         u8 macaddr0[6];
2211         __be16 r5;
2212         u8 macaddr1[6];
2213         __be16 r6;
2214         u8 macaddr2[6];
2215         __be16 r7;
2216         u8 macaddr3[6];
2217 };
2218
2219 #define FW_ACL_MAC_CMD_PFN_S    8
2220 #define FW_ACL_MAC_CMD_PFN_V(x) ((x) << FW_ACL_MAC_CMD_PFN_S)
2221
2222 #define FW_ACL_MAC_CMD_VFN_S    0
2223 #define FW_ACL_MAC_CMD_VFN_V(x) ((x) << FW_ACL_MAC_CMD_VFN_S)
2224
2225 #define FW_ACL_MAC_CMD_EN_S     31
2226 #define FW_ACL_MAC_CMD_EN_V(x)  ((x) << FW_ACL_MAC_CMD_EN_S)
2227
2228 struct fw_acl_vlan_cmd {
2229         __be32 op_to_vfn;
2230         __be32 en_to_len16;
2231         u8 nvlan;
2232         u8 dropnovlan_fm;
2233         u8 r3_lo[6];
2234         __be16 vlanid[16];
2235 };
2236
2237 #define FW_ACL_VLAN_CMD_PFN_S           8
2238 #define FW_ACL_VLAN_CMD_PFN_V(x)        ((x) << FW_ACL_VLAN_CMD_PFN_S)
2239
2240 #define FW_ACL_VLAN_CMD_VFN_S           0
2241 #define FW_ACL_VLAN_CMD_VFN_V(x)        ((x) << FW_ACL_VLAN_CMD_VFN_S)
2242
2243 #define FW_ACL_VLAN_CMD_EN_S    31
2244 #define FW_ACL_VLAN_CMD_EN_V(x) ((x) << FW_ACL_VLAN_CMD_EN_S)
2245
2246 #define FW_ACL_VLAN_CMD_DROPNOVLAN_S    7
2247 #define FW_ACL_VLAN_CMD_DROPNOVLAN_V(x) ((x) << FW_ACL_VLAN_CMD_DROPNOVLAN_S)
2248
2249 #define FW_ACL_VLAN_CMD_FM_S    6
2250 #define FW_ACL_VLAN_CMD_FM_V(x) ((x) << FW_ACL_VLAN_CMD_FM_S)
2251
2252 enum fw_port_cap {
2253         FW_PORT_CAP_SPEED_100M          = 0x0001,
2254         FW_PORT_CAP_SPEED_1G            = 0x0002,
2255         FW_PORT_CAP_SPEED_25G           = 0x0004,
2256         FW_PORT_CAP_SPEED_10G           = 0x0008,
2257         FW_PORT_CAP_SPEED_40G           = 0x0010,
2258         FW_PORT_CAP_SPEED_100G          = 0x0020,
2259         FW_PORT_CAP_FC_RX               = 0x0040,
2260         FW_PORT_CAP_FC_TX               = 0x0080,
2261         FW_PORT_CAP_ANEG                = 0x0100,
2262         FW_PORT_CAP_MDIX                = 0x0200,
2263         FW_PORT_CAP_MDIAUTO             = 0x0400,
2264         FW_PORT_CAP_FEC                 = 0x0800,
2265         FW_PORT_CAP_TECHKR              = 0x1000,
2266         FW_PORT_CAP_TECHKX4             = 0x2000,
2267         FW_PORT_CAP_802_3_PAUSE         = 0x4000,
2268         FW_PORT_CAP_802_3_ASM_DIR       = 0x8000,
2269 };
2270
2271 enum fw_port_mdi {
2272         FW_PORT_CAP_MDI_UNCHANGED,
2273         FW_PORT_CAP_MDI_AUTO,
2274         FW_PORT_CAP_MDI_F_STRAIGHT,
2275         FW_PORT_CAP_MDI_F_CROSSOVER
2276 };
2277
2278 #define FW_PORT_CAP_MDI_S 9
2279 #define FW_PORT_CAP_MDI_V(x) ((x) << FW_PORT_CAP_MDI_S)
2280
2281 enum fw_port_action {
2282         FW_PORT_ACTION_L1_CFG           = 0x0001,
2283         FW_PORT_ACTION_L2_CFG           = 0x0002,
2284         FW_PORT_ACTION_GET_PORT_INFO    = 0x0003,
2285         FW_PORT_ACTION_L2_PPP_CFG       = 0x0004,
2286         FW_PORT_ACTION_L2_DCB_CFG       = 0x0005,
2287         FW_PORT_ACTION_DCB_READ_TRANS   = 0x0006,
2288         FW_PORT_ACTION_DCB_READ_RECV    = 0x0007,
2289         FW_PORT_ACTION_DCB_READ_DET     = 0x0008,
2290         FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
2291         FW_PORT_ACTION_L1_LOW_PWR_EN    = 0x0011,
2292         FW_PORT_ACTION_L2_WOL_MODE_EN   = 0x0012,
2293         FW_PORT_ACTION_LPBK_TO_NORMAL   = 0x0020,
2294         FW_PORT_ACTION_L1_LPBK          = 0x0021,
2295         FW_PORT_ACTION_L1_PMA_LPBK      = 0x0022,
2296         FW_PORT_ACTION_L1_PCS_LPBK      = 0x0023,
2297         FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024,
2298         FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025,
2299         FW_PORT_ACTION_PHY_RESET        = 0x0040,
2300         FW_PORT_ACTION_PMA_RESET        = 0x0041,
2301         FW_PORT_ACTION_PCS_RESET        = 0x0042,
2302         FW_PORT_ACTION_PHYXS_RESET      = 0x0043,
2303         FW_PORT_ACTION_DTEXS_REEST      = 0x0044,
2304         FW_PORT_ACTION_AN_RESET         = 0x0045
2305 };
2306
2307 enum fw_port_l2cfg_ctlbf {
2308         FW_PORT_L2_CTLBF_OVLAN0 = 0x01,
2309         FW_PORT_L2_CTLBF_OVLAN1 = 0x02,
2310         FW_PORT_L2_CTLBF_OVLAN2 = 0x04,
2311         FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
2312         FW_PORT_L2_CTLBF_IVLAN  = 0x10,
2313         FW_PORT_L2_CTLBF_TXIPG  = 0x20
2314 };
2315
2316 enum fw_port_dcb_versions {
2317         FW_PORT_DCB_VER_UNKNOWN,
2318         FW_PORT_DCB_VER_CEE1D0,
2319         FW_PORT_DCB_VER_CEE1D01,
2320         FW_PORT_DCB_VER_IEEE,
2321         FW_PORT_DCB_VER_AUTO = 7
2322 };
2323
2324 enum fw_port_dcb_cfg {
2325         FW_PORT_DCB_CFG_PG      = 0x01,
2326         FW_PORT_DCB_CFG_PFC     = 0x02,
2327         FW_PORT_DCB_CFG_APPL    = 0x04
2328 };
2329
2330 enum fw_port_dcb_cfg_rc {
2331         FW_PORT_DCB_CFG_SUCCESS = 0x0,
2332         FW_PORT_DCB_CFG_ERROR   = 0x1
2333 };
2334
2335 enum fw_port_dcb_type {
2336         FW_PORT_DCB_TYPE_PGID           = 0x00,
2337         FW_PORT_DCB_TYPE_PGRATE         = 0x01,
2338         FW_PORT_DCB_TYPE_PRIORATE       = 0x02,
2339         FW_PORT_DCB_TYPE_PFC            = 0x03,
2340         FW_PORT_DCB_TYPE_APP_ID         = 0x04,
2341         FW_PORT_DCB_TYPE_CONTROL        = 0x05,
2342 };
2343
2344 enum fw_port_dcb_feature_state {
2345         FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0,
2346         FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1,
2347         FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2,
2348         FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3,
2349 };
2350
2351 struct fw_port_cmd {
2352         __be32 op_to_portid;
2353         __be32 action_to_len16;
2354         union fw_port {
2355                 struct fw_port_l1cfg {
2356                         __be32 rcap;
2357                         __be32 r;
2358                 } l1cfg;
2359                 struct fw_port_l2cfg {
2360                         __u8   ctlbf;
2361                         __u8   ovlan3_to_ivlan0;
2362                         __be16 ivlantype;
2363                         __be16 txipg_force_pinfo;
2364                         __be16 mtu;
2365                         __be16 ovlan0mask;
2366                         __be16 ovlan0type;
2367                         __be16 ovlan1mask;
2368                         __be16 ovlan1type;
2369                         __be16 ovlan2mask;
2370                         __be16 ovlan2type;
2371                         __be16 ovlan3mask;
2372                         __be16 ovlan3type;
2373                 } l2cfg;
2374                 struct fw_port_info {
2375                         __be32 lstatus_to_modtype;
2376                         __be16 pcap;
2377                         __be16 acap;
2378                         __be16 mtu;
2379                         __u8   cbllen;
2380                         __u8   auxlinfo;
2381                         __u8   dcbxdis_pkd;
2382                         __u8   r8_lo;
2383                         __be16 lpacap;
2384                         __be64 r9;
2385                 } info;
2386                 struct fw_port_diags {
2387                         __u8   diagop;
2388                         __u8   r[3];
2389                         __be32 diagval;
2390                 } diags;
2391                 union fw_port_dcb {
2392                         struct fw_port_dcb_pgid {
2393                                 __u8   type;
2394                                 __u8   apply_pkd;
2395                                 __u8   r10_lo[2];
2396                                 __be32 pgid;
2397                                 __be64 r11;
2398                         } pgid;
2399                         struct fw_port_dcb_pgrate {
2400                                 __u8   type;
2401                                 __u8   apply_pkd;
2402                                 __u8   r10_lo[5];
2403                                 __u8   num_tcs_supported;
2404                                 __u8   pgrate[8];
2405                                 __u8   tsa[8];
2406                         } pgrate;
2407                         struct fw_port_dcb_priorate {
2408                                 __u8   type;
2409                                 __u8   apply_pkd;
2410                                 __u8   r10_lo[6];
2411                                 __u8   strict_priorate[8];
2412                         } priorate;
2413                         struct fw_port_dcb_pfc {
2414                                 __u8   type;
2415                                 __u8   pfcen;
2416                                 __u8   r10[5];
2417                                 __u8   max_pfc_tcs;
2418                                 __be64 r11;
2419                         } pfc;
2420                         struct fw_port_app_priority {
2421                                 __u8   type;
2422                                 __u8   r10[2];
2423                                 __u8   idx;
2424                                 __u8   user_prio_map;
2425                                 __u8   sel_field;
2426                                 __be16 protocolid;
2427                                 __be64 r12;
2428                         } app_priority;
2429                         struct fw_port_dcb_control {
2430                                 __u8   type;
2431                                 __u8   all_syncd_pkd;
2432                                 __be16 dcb_version_to_app_state;
2433                                 __be32 r11;
2434                                 __be64 r12;
2435                         } control;
2436                 } dcb;
2437         } u;
2438 };
2439
2440 #define FW_PORT_CMD_READ_S      22
2441 #define FW_PORT_CMD_READ_V(x)   ((x) << FW_PORT_CMD_READ_S)
2442 #define FW_PORT_CMD_READ_F      FW_PORT_CMD_READ_V(1U)
2443
2444 #define FW_PORT_CMD_PORTID_S    0
2445 #define FW_PORT_CMD_PORTID_M    0xf
2446 #define FW_PORT_CMD_PORTID_V(x) ((x) << FW_PORT_CMD_PORTID_S)
2447 #define FW_PORT_CMD_PORTID_G(x) \
2448         (((x) >> FW_PORT_CMD_PORTID_S) & FW_PORT_CMD_PORTID_M)
2449
2450 #define FW_PORT_CMD_ACTION_S    16
2451 #define FW_PORT_CMD_ACTION_M    0xffff
2452 #define FW_PORT_CMD_ACTION_V(x) ((x) << FW_PORT_CMD_ACTION_S)
2453 #define FW_PORT_CMD_ACTION_G(x) \
2454         (((x) >> FW_PORT_CMD_ACTION_S) & FW_PORT_CMD_ACTION_M)
2455
2456 #define FW_PORT_CMD_OVLAN3_S    7
2457 #define FW_PORT_CMD_OVLAN3_V(x) ((x) << FW_PORT_CMD_OVLAN3_S)
2458
2459 #define FW_PORT_CMD_OVLAN2_S    6
2460 #define FW_PORT_CMD_OVLAN2_V(x) ((x) << FW_PORT_CMD_OVLAN2_S)
2461
2462 #define FW_PORT_CMD_OVLAN1_S    5
2463 #define FW_PORT_CMD_OVLAN1_V(x) ((x) << FW_PORT_CMD_OVLAN1_S)
2464
2465 #define FW_PORT_CMD_OVLAN0_S    4
2466 #define FW_PORT_CMD_OVLAN0_V(x) ((x) << FW_PORT_CMD_OVLAN0_S)
2467
2468 #define FW_PORT_CMD_IVLAN0_S    3
2469 #define FW_PORT_CMD_IVLAN0_V(x) ((x) << FW_PORT_CMD_IVLAN0_S)
2470
2471 #define FW_PORT_CMD_TXIPG_S     3
2472 #define FW_PORT_CMD_TXIPG_V(x)  ((x) << FW_PORT_CMD_TXIPG_S)
2473
2474 #define FW_PORT_CMD_LSTATUS_S           31
2475 #define FW_PORT_CMD_LSTATUS_M           0x1
2476 #define FW_PORT_CMD_LSTATUS_V(x)        ((x) << FW_PORT_CMD_LSTATUS_S)
2477 #define FW_PORT_CMD_LSTATUS_G(x)        \
2478         (((x) >> FW_PORT_CMD_LSTATUS_S) & FW_PORT_CMD_LSTATUS_M)
2479 #define FW_PORT_CMD_LSTATUS_F   FW_PORT_CMD_LSTATUS_V(1U)
2480
2481 #define FW_PORT_CMD_LSPEED_S    24
2482 #define FW_PORT_CMD_LSPEED_M    0x3f
2483 #define FW_PORT_CMD_LSPEED_V(x) ((x) << FW_PORT_CMD_LSPEED_S)
2484 #define FW_PORT_CMD_LSPEED_G(x) \
2485         (((x) >> FW_PORT_CMD_LSPEED_S) & FW_PORT_CMD_LSPEED_M)
2486
2487 #define FW_PORT_CMD_TXPAUSE_S           23
2488 #define FW_PORT_CMD_TXPAUSE_V(x)        ((x) << FW_PORT_CMD_TXPAUSE_S)
2489 #define FW_PORT_CMD_TXPAUSE_F   FW_PORT_CMD_TXPAUSE_V(1U)
2490
2491 #define FW_PORT_CMD_RXPAUSE_S           22
2492 #define FW_PORT_CMD_RXPAUSE_V(x)        ((x) << FW_PORT_CMD_RXPAUSE_S)
2493 #define FW_PORT_CMD_RXPAUSE_F   FW_PORT_CMD_RXPAUSE_V(1U)
2494
2495 #define FW_PORT_CMD_MDIOCAP_S           21
2496 #define FW_PORT_CMD_MDIOCAP_V(x)        ((x) << FW_PORT_CMD_MDIOCAP_S)
2497 #define FW_PORT_CMD_MDIOCAP_F   FW_PORT_CMD_MDIOCAP_V(1U)
2498
2499 #define FW_PORT_CMD_MDIOADDR_S          16
2500 #define FW_PORT_CMD_MDIOADDR_M          0x1f
2501 #define FW_PORT_CMD_MDIOADDR_G(x)       \
2502         (((x) >> FW_PORT_CMD_MDIOADDR_S) & FW_PORT_CMD_MDIOADDR_M)
2503
2504 #define FW_PORT_CMD_LPTXPAUSE_S         15
2505 #define FW_PORT_CMD_LPTXPAUSE_V(x)      ((x) << FW_PORT_CMD_LPTXPAUSE_S)
2506 #define FW_PORT_CMD_LPTXPAUSE_F FW_PORT_CMD_LPTXPAUSE_V(1U)
2507
2508 #define FW_PORT_CMD_LPRXPAUSE_S         14
2509 #define FW_PORT_CMD_LPRXPAUSE_V(x)      ((x) << FW_PORT_CMD_LPRXPAUSE_S)
2510 #define FW_PORT_CMD_LPRXPAUSE_F FW_PORT_CMD_LPRXPAUSE_V(1U)
2511
2512 #define FW_PORT_CMD_PTYPE_S     8
2513 #define FW_PORT_CMD_PTYPE_M     0x1f
2514 #define FW_PORT_CMD_PTYPE_G(x)  \
2515         (((x) >> FW_PORT_CMD_PTYPE_S) & FW_PORT_CMD_PTYPE_M)
2516
2517 #define FW_PORT_CMD_LINKDNRC_S          5
2518 #define FW_PORT_CMD_LINKDNRC_M          0x7
2519 #define FW_PORT_CMD_LINKDNRC_G(x)       \
2520         (((x) >> FW_PORT_CMD_LINKDNRC_S) & FW_PORT_CMD_LINKDNRC_M)
2521
2522 #define FW_PORT_CMD_MODTYPE_S           0
2523 #define FW_PORT_CMD_MODTYPE_M           0x1f
2524 #define FW_PORT_CMD_MODTYPE_V(x)        ((x) << FW_PORT_CMD_MODTYPE_S)
2525 #define FW_PORT_CMD_MODTYPE_G(x)        \
2526         (((x) >> FW_PORT_CMD_MODTYPE_S) & FW_PORT_CMD_MODTYPE_M)
2527
2528 #define FW_PORT_CMD_DCBXDIS_S           7
2529 #define FW_PORT_CMD_DCBXDIS_V(x)        ((x) << FW_PORT_CMD_DCBXDIS_S)
2530 #define FW_PORT_CMD_DCBXDIS_F   FW_PORT_CMD_DCBXDIS_V(1U)
2531
2532 #define FW_PORT_CMD_APPLY_S     7
2533 #define FW_PORT_CMD_APPLY_V(x)  ((x) << FW_PORT_CMD_APPLY_S)
2534 #define FW_PORT_CMD_APPLY_F     FW_PORT_CMD_APPLY_V(1U)
2535
2536 #define FW_PORT_CMD_ALL_SYNCD_S         7
2537 #define FW_PORT_CMD_ALL_SYNCD_V(x)      ((x) << FW_PORT_CMD_ALL_SYNCD_S)
2538 #define FW_PORT_CMD_ALL_SYNCD_F FW_PORT_CMD_ALL_SYNCD_V(1U)
2539
2540 #define FW_PORT_CMD_DCB_VERSION_S       12
2541 #define FW_PORT_CMD_DCB_VERSION_M       0x7
2542 #define FW_PORT_CMD_DCB_VERSION_G(x)    \
2543         (((x) >> FW_PORT_CMD_DCB_VERSION_S) & FW_PORT_CMD_DCB_VERSION_M)
2544
2545 enum fw_port_type {
2546         FW_PORT_TYPE_FIBER_XFI,
2547         FW_PORT_TYPE_FIBER_XAUI,
2548         FW_PORT_TYPE_BT_SGMII,
2549         FW_PORT_TYPE_BT_XFI,
2550         FW_PORT_TYPE_BT_XAUI,
2551         FW_PORT_TYPE_KX4,
2552         FW_PORT_TYPE_CX4,
2553         FW_PORT_TYPE_KX,
2554         FW_PORT_TYPE_KR,
2555         FW_PORT_TYPE_SFP,
2556         FW_PORT_TYPE_BP_AP,
2557         FW_PORT_TYPE_BP4_AP,
2558         FW_PORT_TYPE_QSFP_10G,
2559         FW_PORT_TYPE_QSA,
2560         FW_PORT_TYPE_QSFP,
2561         FW_PORT_TYPE_BP40_BA,
2562         FW_PORT_TYPE_KR4_100G,
2563         FW_PORT_TYPE_CR4_QSFP,
2564         FW_PORT_TYPE_CR_QSFP,
2565         FW_PORT_TYPE_CR2_QSFP,
2566         FW_PORT_TYPE_SFP28,
2567
2568         FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_M
2569 };
2570
2571 enum fw_port_module_type {
2572         FW_PORT_MOD_TYPE_NA,
2573         FW_PORT_MOD_TYPE_LR,
2574         FW_PORT_MOD_TYPE_SR,
2575         FW_PORT_MOD_TYPE_ER,
2576         FW_PORT_MOD_TYPE_TWINAX_PASSIVE,
2577         FW_PORT_MOD_TYPE_TWINAX_ACTIVE,
2578         FW_PORT_MOD_TYPE_LRM,
2579         FW_PORT_MOD_TYPE_ERROR          = FW_PORT_CMD_MODTYPE_M - 3,
2580         FW_PORT_MOD_TYPE_UNKNOWN        = FW_PORT_CMD_MODTYPE_M - 2,
2581         FW_PORT_MOD_TYPE_NOTSUPPORTED   = FW_PORT_CMD_MODTYPE_M - 1,
2582
2583         FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_M
2584 };
2585
2586 enum fw_port_mod_sub_type {
2587         FW_PORT_MOD_SUB_TYPE_NA,
2588         FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
2589         FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
2590         FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
2591         FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
2592         FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
2593         FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
2594
2595         /* The following will never been in the VPD.  They are TWINAX cable
2596          * lengths decoded from SFP+ module i2c PROMs.  These should
2597          * almost certainly go somewhere else ...
2598          */
2599         FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
2600         FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
2601         FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
2602         FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
2603 };
2604
2605 enum fw_port_stats_tx_index {
2606         FW_STAT_TX_PORT_BYTES_IX = 0,
2607         FW_STAT_TX_PORT_FRAMES_IX,
2608         FW_STAT_TX_PORT_BCAST_IX,
2609         FW_STAT_TX_PORT_MCAST_IX,
2610         FW_STAT_TX_PORT_UCAST_IX,
2611         FW_STAT_TX_PORT_ERROR_IX,
2612         FW_STAT_TX_PORT_64B_IX,
2613         FW_STAT_TX_PORT_65B_127B_IX,
2614         FW_STAT_TX_PORT_128B_255B_IX,
2615         FW_STAT_TX_PORT_256B_511B_IX,
2616         FW_STAT_TX_PORT_512B_1023B_IX,
2617         FW_STAT_TX_PORT_1024B_1518B_IX,
2618         FW_STAT_TX_PORT_1519B_MAX_IX,
2619         FW_STAT_TX_PORT_DROP_IX,
2620         FW_STAT_TX_PORT_PAUSE_IX,
2621         FW_STAT_TX_PORT_PPP0_IX,
2622         FW_STAT_TX_PORT_PPP1_IX,
2623         FW_STAT_TX_PORT_PPP2_IX,
2624         FW_STAT_TX_PORT_PPP3_IX,
2625         FW_STAT_TX_PORT_PPP4_IX,
2626         FW_STAT_TX_PORT_PPP5_IX,
2627         FW_STAT_TX_PORT_PPP6_IX,
2628         FW_STAT_TX_PORT_PPP7_IX,
2629         FW_NUM_PORT_TX_STATS
2630 };
2631
2632 enum fw_port_stat_rx_index {
2633         FW_STAT_RX_PORT_BYTES_IX = 0,
2634         FW_STAT_RX_PORT_FRAMES_IX,
2635         FW_STAT_RX_PORT_BCAST_IX,
2636         FW_STAT_RX_PORT_MCAST_IX,
2637         FW_STAT_RX_PORT_UCAST_IX,
2638         FW_STAT_RX_PORT_MTU_ERROR_IX,
2639         FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
2640         FW_STAT_RX_PORT_CRC_ERROR_IX,
2641         FW_STAT_RX_PORT_LEN_ERROR_IX,
2642         FW_STAT_RX_PORT_SYM_ERROR_IX,
2643         FW_STAT_RX_PORT_64B_IX,
2644         FW_STAT_RX_PORT_65B_127B_IX,
2645         FW_STAT_RX_PORT_128B_255B_IX,
2646         FW_STAT_RX_PORT_256B_511B_IX,
2647         FW_STAT_RX_PORT_512B_1023B_IX,
2648         FW_STAT_RX_PORT_1024B_1518B_IX,
2649         FW_STAT_RX_PORT_1519B_MAX_IX,
2650         FW_STAT_RX_PORT_PAUSE_IX,
2651         FW_STAT_RX_PORT_PPP0_IX,
2652         FW_STAT_RX_PORT_PPP1_IX,
2653         FW_STAT_RX_PORT_PPP2_IX,
2654         FW_STAT_RX_PORT_PPP3_IX,
2655         FW_STAT_RX_PORT_PPP4_IX,
2656         FW_STAT_RX_PORT_PPP5_IX,
2657         FW_STAT_RX_PORT_PPP6_IX,
2658         FW_STAT_RX_PORT_PPP7_IX,
2659         FW_STAT_RX_PORT_LESS_64B_IX,
2660         FW_STAT_RX_PORT_MAC_ERROR_IX,
2661         FW_NUM_PORT_RX_STATS
2662 };
2663
2664 /* port stats */
2665 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + FW_NUM_PORT_RX_STATS)
2666
2667 struct fw_port_stats_cmd {
2668         __be32 op_to_portid;
2669         __be32 retval_len16;
2670         union fw_port_stats {
2671                 struct fw_port_stats_ctl {
2672                         u8 nstats_bg_bm;
2673                         u8 tx_ix;
2674                         __be16 r6;
2675                         __be32 r7;
2676                         __be64 stat0;
2677                         __be64 stat1;
2678                         __be64 stat2;
2679                         __be64 stat3;
2680                         __be64 stat4;
2681                         __be64 stat5;
2682                 } ctl;
2683                 struct fw_port_stats_all {
2684                         __be64 tx_bytes;
2685                         __be64 tx_frames;
2686                         __be64 tx_bcast;
2687                         __be64 tx_mcast;
2688                         __be64 tx_ucast;
2689                         __be64 tx_error;
2690                         __be64 tx_64b;
2691                         __be64 tx_65b_127b;
2692                         __be64 tx_128b_255b;
2693                         __be64 tx_256b_511b;
2694                         __be64 tx_512b_1023b;
2695                         __be64 tx_1024b_1518b;
2696                         __be64 tx_1519b_max;
2697                         __be64 tx_drop;
2698                         __be64 tx_pause;
2699                         __be64 tx_ppp0;
2700                         __be64 tx_ppp1;
2701                         __be64 tx_ppp2;
2702                         __be64 tx_ppp3;
2703                         __be64 tx_ppp4;
2704                         __be64 tx_ppp5;
2705                         __be64 tx_ppp6;
2706                         __be64 tx_ppp7;
2707                         __be64 rx_bytes;
2708                         __be64 rx_frames;
2709                         __be64 rx_bcast;
2710                         __be64 rx_mcast;
2711                         __be64 rx_ucast;
2712                         __be64 rx_mtu_error;
2713                         __be64 rx_mtu_crc_error;
2714                         __be64 rx_crc_error;
2715                         __be64 rx_len_error;
2716                         __be64 rx_sym_error;
2717                         __be64 rx_64b;
2718                         __be64 rx_65b_127b;
2719                         __be64 rx_128b_255b;
2720                         __be64 rx_256b_511b;
2721                         __be64 rx_512b_1023b;
2722                         __be64 rx_1024b_1518b;
2723                         __be64 rx_1519b_max;
2724                         __be64 rx_pause;
2725                         __be64 rx_ppp0;
2726                         __be64 rx_ppp1;
2727                         __be64 rx_ppp2;
2728                         __be64 rx_ppp3;
2729                         __be64 rx_ppp4;
2730                         __be64 rx_ppp5;
2731                         __be64 rx_ppp6;
2732                         __be64 rx_ppp7;
2733                         __be64 rx_less_64b;
2734                         __be64 rx_bg_drop;
2735                         __be64 rx_bg_trunc;
2736                 } all;
2737         } u;
2738 };
2739
2740 /* port loopback stats */
2741 #define FW_NUM_LB_STATS 16
2742 enum fw_port_lb_stats_index {
2743         FW_STAT_LB_PORT_BYTES_IX,
2744         FW_STAT_LB_PORT_FRAMES_IX,
2745         FW_STAT_LB_PORT_BCAST_IX,
2746         FW_STAT_LB_PORT_MCAST_IX,
2747         FW_STAT_LB_PORT_UCAST_IX,
2748         FW_STAT_LB_PORT_ERROR_IX,
2749         FW_STAT_LB_PORT_64B_IX,
2750         FW_STAT_LB_PORT_65B_127B_IX,
2751         FW_STAT_LB_PORT_128B_255B_IX,
2752         FW_STAT_LB_PORT_256B_511B_IX,
2753         FW_STAT_LB_PORT_512B_1023B_IX,
2754         FW_STAT_LB_PORT_1024B_1518B_IX,
2755         FW_STAT_LB_PORT_1519B_MAX_IX,
2756         FW_STAT_LB_PORT_DROP_FRAMES_IX
2757 };
2758
2759 struct fw_port_lb_stats_cmd {
2760         __be32 op_to_lbport;
2761         __be32 retval_len16;
2762         union fw_port_lb_stats {
2763                 struct fw_port_lb_stats_ctl {
2764                         u8 nstats_bg_bm;
2765                         u8 ix_pkd;
2766                         __be16 r6;
2767                         __be32 r7;
2768                         __be64 stat0;
2769                         __be64 stat1;
2770                         __be64 stat2;
2771                         __be64 stat3;
2772                         __be64 stat4;
2773                         __be64 stat5;
2774                 } ctl;
2775                 struct fw_port_lb_stats_all {
2776                         __be64 tx_bytes;
2777                         __be64 tx_frames;
2778                         __be64 tx_bcast;
2779                         __be64 tx_mcast;
2780                         __be64 tx_ucast;
2781                         __be64 tx_error;
2782                         __be64 tx_64b;
2783                         __be64 tx_65b_127b;
2784                         __be64 tx_128b_255b;
2785                         __be64 tx_256b_511b;
2786                         __be64 tx_512b_1023b;
2787                         __be64 tx_1024b_1518b;
2788                         __be64 tx_1519b_max;
2789                         __be64 rx_lb_drop;
2790                         __be64 rx_lb_trunc;
2791                 } all;
2792         } u;
2793 };
2794
2795 struct fw_rss_ind_tbl_cmd {
2796         __be32 op_to_viid;
2797         __be32 retval_len16;
2798         __be16 niqid;
2799         __be16 startidx;
2800         __be32 r3;
2801         __be32 iq0_to_iq2;
2802         __be32 iq3_to_iq5;
2803         __be32 iq6_to_iq8;
2804         __be32 iq9_to_iq11;
2805         __be32 iq12_to_iq14;
2806         __be32 iq15_to_iq17;
2807         __be32 iq18_to_iq20;
2808         __be32 iq21_to_iq23;
2809         __be32 iq24_to_iq26;
2810         __be32 iq27_to_iq29;
2811         __be32 iq30_iq31;
2812         __be32 r15_lo;
2813 };
2814
2815 #define FW_RSS_IND_TBL_CMD_VIID_S       0
2816 #define FW_RSS_IND_TBL_CMD_VIID_V(x)    ((x) << FW_RSS_IND_TBL_CMD_VIID_S)
2817
2818 #define FW_RSS_IND_TBL_CMD_IQ0_S        20
2819 #define FW_RSS_IND_TBL_CMD_IQ0_V(x)     ((x) << FW_RSS_IND_TBL_CMD_IQ0_S)
2820
2821 #define FW_RSS_IND_TBL_CMD_IQ1_S        10
2822 #define FW_RSS_IND_TBL_CMD_IQ1_V(x)     ((x) << FW_RSS_IND_TBL_CMD_IQ1_S)
2823
2824 #define FW_RSS_IND_TBL_CMD_IQ2_S        0
2825 #define FW_RSS_IND_TBL_CMD_IQ2_V(x)     ((x) << FW_RSS_IND_TBL_CMD_IQ2_S)
2826
2827 struct fw_rss_glb_config_cmd {
2828         __be32 op_to_write;
2829         __be32 retval_len16;
2830         union fw_rss_glb_config {
2831                 struct fw_rss_glb_config_manual {
2832                         __be32 mode_pkd;
2833                         __be32 r3;
2834                         __be64 r4;
2835                         __be64 r5;
2836                 } manual;
2837                 struct fw_rss_glb_config_basicvirtual {
2838                         __be32 mode_pkd;
2839                         __be32 synmapen_to_hashtoeplitz;
2840                         __be64 r8;
2841                         __be64 r9;
2842                 } basicvirtual;
2843         } u;
2844 };
2845
2846 #define FW_RSS_GLB_CONFIG_CMD_MODE_S    28
2847 #define FW_RSS_GLB_CONFIG_CMD_MODE_M    0xf
2848 #define FW_RSS_GLB_CONFIG_CMD_MODE_V(x) ((x) << FW_RSS_GLB_CONFIG_CMD_MODE_S)
2849 #define FW_RSS_GLB_CONFIG_CMD_MODE_G(x) \
2850         (((x) >> FW_RSS_GLB_CONFIG_CMD_MODE_S) & FW_RSS_GLB_CONFIG_CMD_MODE_M)
2851
2852 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL       0
2853 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
2854
2855 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S        8
2856 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(x)     \
2857         ((x) << FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S)
2858 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F        \
2859         FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(1U)
2860
2861 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S           7
2862 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(x)        \
2863         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S)
2864 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F   \
2865         FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(1U)
2866
2867 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S           6
2868 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(x)        \
2869         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S)
2870 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F   \
2871         FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(1U)
2872
2873 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S           5
2874 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(x)        \
2875         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S)
2876 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F   \
2877         FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(1U)
2878
2879 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S           4
2880 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(x)        \
2881         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S)
2882 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F   \
2883         FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(1U)
2884
2885 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S        3
2886 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(x)     \
2887         ((x) << FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S)
2888 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F        \
2889         FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(1U)
2890
2891 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S        2
2892 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(x)     \
2893         ((x) << FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S)
2894 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F        \
2895         FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(1U)
2896
2897 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S       1
2898 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(x)    \
2899         ((x) << FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S)
2900 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F       \
2901         FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(1U)
2902
2903 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S    0
2904 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(x) \
2905         ((x) << FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S)
2906 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F    \
2907         FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(1U)
2908
2909 struct fw_rss_vi_config_cmd {
2910         __be32 op_to_viid;
2911 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0)
2912         __be32 retval_len16;
2913         union fw_rss_vi_config {
2914                 struct fw_rss_vi_config_manual {
2915                         __be64 r3;
2916                         __be64 r4;
2917                         __be64 r5;
2918                 } manual;
2919                 struct fw_rss_vi_config_basicvirtual {
2920                         __be32 r6;
2921                         __be32 defaultq_to_udpen;
2922                         __be64 r9;
2923                         __be64 r10;
2924                 } basicvirtual;
2925         } u;
2926 };
2927
2928 #define FW_RSS_VI_CONFIG_CMD_VIID_S     0
2929 #define FW_RSS_VI_CONFIG_CMD_VIID_V(x)  ((x) << FW_RSS_VI_CONFIG_CMD_VIID_S)
2930
2931 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S         16
2932 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M         0x3ff
2933 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(x)      \
2934         ((x) << FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S)
2935 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(x)      \
2936         (((x) >> FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) & \
2937          FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M)
2938
2939 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S     4
2940 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(x)  \
2941         ((x) << FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S)
2942 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F     \
2943         FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(1U)
2944
2945 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S      3
2946 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(x)   \
2947         ((x) << FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S)
2948 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F      \
2949         FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(1U)
2950
2951 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S     2
2952 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(x)  \
2953         ((x) << FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S)
2954 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F     \
2955         FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(1U)
2956
2957 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S      1
2958 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(x)   \
2959         ((x) << FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S)
2960 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F      \
2961         FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(1U)
2962
2963 #define FW_RSS_VI_CONFIG_CMD_UDPEN_S    0
2964 #define FW_RSS_VI_CONFIG_CMD_UDPEN_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_UDPEN_S)
2965 #define FW_RSS_VI_CONFIG_CMD_UDPEN_F    FW_RSS_VI_CONFIG_CMD_UDPEN_V(1U)
2966
2967 struct fw_clip_cmd {
2968         __be32 op_to_write;
2969         __be32 alloc_to_len16;
2970         __be64 ip_hi;
2971         __be64 ip_lo;
2972         __be32 r4[2];
2973 };
2974
2975 #define FW_CLIP_CMD_ALLOC_S     31
2976 #define FW_CLIP_CMD_ALLOC_V(x)  ((x) << FW_CLIP_CMD_ALLOC_S)
2977 #define FW_CLIP_CMD_ALLOC_F     FW_CLIP_CMD_ALLOC_V(1U)
2978
2979 #define FW_CLIP_CMD_FREE_S      30
2980 #define FW_CLIP_CMD_FREE_V(x)   ((x) << FW_CLIP_CMD_FREE_S)
2981 #define FW_CLIP_CMD_FREE_F      FW_CLIP_CMD_FREE_V(1U)
2982
2983 enum fw_error_type {
2984         FW_ERROR_TYPE_EXCEPTION         = 0x0,
2985         FW_ERROR_TYPE_HWMODULE          = 0x1,
2986         FW_ERROR_TYPE_WR                = 0x2,
2987         FW_ERROR_TYPE_ACL               = 0x3,
2988 };
2989
2990 struct fw_error_cmd {
2991         __be32 op_to_type;
2992         __be32 len16_pkd;
2993         union fw_error {
2994                 struct fw_error_exception {
2995                         __be32 info[6];
2996                 } exception;
2997                 struct fw_error_hwmodule {
2998                         __be32 regaddr;
2999                         __be32 regval;
3000                 } hwmodule;
3001                 struct fw_error_wr {
3002                         __be16 cidx;
3003                         __be16 pfn_vfn;
3004                         __be32 eqid;
3005                         u8 wrhdr[16];
3006                 } wr;
3007                 struct fw_error_acl {
3008                         __be16 cidx;
3009                         __be16 pfn_vfn;
3010                         __be32 eqid;
3011                         __be16 mv_pkd;
3012                         u8 val[6];
3013                         __be64 r4;
3014                 } acl;
3015         } u;
3016 };
3017
3018 struct fw_debug_cmd {
3019         __be32 op_type;
3020         __be32 len16_pkd;
3021         union fw_debug {
3022                 struct fw_debug_assert {
3023                         __be32 fcid;
3024                         __be32 line;
3025                         __be32 x;
3026                         __be32 y;
3027                         u8 filename_0_7[8];
3028                         u8 filename_8_15[8];
3029                         __be64 r3;
3030                 } assert;
3031                 struct fw_debug_prt {
3032                         __be16 dprtstridx;
3033                         __be16 r3[3];
3034                         __be32 dprtstrparam0;
3035                         __be32 dprtstrparam1;
3036                         __be32 dprtstrparam2;
3037                         __be32 dprtstrparam3;
3038                 } prt;
3039         } u;
3040 };
3041
3042 #define FW_DEBUG_CMD_TYPE_S     0
3043 #define FW_DEBUG_CMD_TYPE_M     0xff
3044 #define FW_DEBUG_CMD_TYPE_G(x)  \
3045         (((x) >> FW_DEBUG_CMD_TYPE_S) & FW_DEBUG_CMD_TYPE_M)
3046
3047 #define PCIE_FW_ERR_S           31
3048 #define PCIE_FW_ERR_V(x)        ((x) << PCIE_FW_ERR_S)
3049 #define PCIE_FW_ERR_F           PCIE_FW_ERR_V(1U)
3050
3051 #define PCIE_FW_INIT_S          30
3052 #define PCIE_FW_INIT_V(x)       ((x) << PCIE_FW_INIT_S)
3053 #define PCIE_FW_INIT_F          PCIE_FW_INIT_V(1U)
3054
3055 #define PCIE_FW_HALT_S          29
3056 #define PCIE_FW_HALT_V(x)       ((x) << PCIE_FW_HALT_S)
3057 #define PCIE_FW_HALT_F          PCIE_FW_HALT_V(1U)
3058
3059 #define PCIE_FW_EVAL_S          24
3060 #define PCIE_FW_EVAL_M          0x7
3061 #define PCIE_FW_EVAL_G(x)       (((x) >> PCIE_FW_EVAL_S) & PCIE_FW_EVAL_M)
3062
3063 #define PCIE_FW_MASTER_VLD_S    15
3064 #define PCIE_FW_MASTER_VLD_V(x) ((x) << PCIE_FW_MASTER_VLD_S)
3065 #define PCIE_FW_MASTER_VLD_F    PCIE_FW_MASTER_VLD_V(1U)
3066
3067 #define PCIE_FW_MASTER_S        12
3068 #define PCIE_FW_MASTER_M        0x7
3069 #define PCIE_FW_MASTER_V(x)     ((x) << PCIE_FW_MASTER_S)
3070 #define PCIE_FW_MASTER_G(x)     (((x) >> PCIE_FW_MASTER_S) & PCIE_FW_MASTER_M)
3071
3072 struct fw_hdr {
3073         u8 ver;
3074         u8 chip;                        /* terminator chip type */
3075         __be16  len512;                 /* bin length in units of 512-bytes */
3076         __be32  fw_ver;                 /* firmware version */
3077         __be32  tp_microcode_ver;
3078         u8 intfver_nic;
3079         u8 intfver_vnic;
3080         u8 intfver_ofld;
3081         u8 intfver_ri;
3082         u8 intfver_iscsipdu;
3083         u8 intfver_iscsi;
3084         u8 intfver_fcoepdu;
3085         u8 intfver_fcoe;
3086         __u32   reserved2;
3087         __u32   reserved3;
3088         __u32   reserved4;
3089         __be32  flags;
3090         __be32  reserved6[23];
3091 };
3092
3093 enum fw_hdr_chip {
3094         FW_HDR_CHIP_T4,
3095         FW_HDR_CHIP_T5,
3096         FW_HDR_CHIP_T6
3097 };
3098
3099 #define FW_HDR_FW_VER_MAJOR_S   24
3100 #define FW_HDR_FW_VER_MAJOR_M   0xff
3101 #define FW_HDR_FW_VER_MAJOR_V(x) \
3102         ((x) << FW_HDR_FW_VER_MAJOR_S)
3103 #define FW_HDR_FW_VER_MAJOR_G(x) \
3104         (((x) >> FW_HDR_FW_VER_MAJOR_S) & FW_HDR_FW_VER_MAJOR_M)
3105
3106 #define FW_HDR_FW_VER_MINOR_S   16
3107 #define FW_HDR_FW_VER_MINOR_M   0xff
3108 #define FW_HDR_FW_VER_MINOR_V(x) \
3109         ((x) << FW_HDR_FW_VER_MINOR_S)
3110 #define FW_HDR_FW_VER_MINOR_G(x) \
3111         (((x) >> FW_HDR_FW_VER_MINOR_S) & FW_HDR_FW_VER_MINOR_M)
3112
3113 #define FW_HDR_FW_VER_MICRO_S   8
3114 #define FW_HDR_FW_VER_MICRO_M   0xff
3115 #define FW_HDR_FW_VER_MICRO_V(x) \
3116         ((x) << FW_HDR_FW_VER_MICRO_S)
3117 #define FW_HDR_FW_VER_MICRO_G(x) \
3118         (((x) >> FW_HDR_FW_VER_MICRO_S) & FW_HDR_FW_VER_MICRO_M)
3119
3120 #define FW_HDR_FW_VER_BUILD_S   0
3121 #define FW_HDR_FW_VER_BUILD_M   0xff
3122 #define FW_HDR_FW_VER_BUILD_V(x) \
3123         ((x) << FW_HDR_FW_VER_BUILD_S)
3124 #define FW_HDR_FW_VER_BUILD_G(x) \
3125         (((x) >> FW_HDR_FW_VER_BUILD_S) & FW_HDR_FW_VER_BUILD_M)
3126
3127 enum fw_hdr_intfver {
3128         FW_HDR_INTFVER_NIC      = 0x00,
3129         FW_HDR_INTFVER_VNIC     = 0x00,
3130         FW_HDR_INTFVER_OFLD     = 0x00,
3131         FW_HDR_INTFVER_RI       = 0x00,
3132         FW_HDR_INTFVER_ISCSIPDU = 0x00,
3133         FW_HDR_INTFVER_ISCSI    = 0x00,
3134         FW_HDR_INTFVER_FCOEPDU  = 0x00,
3135         FW_HDR_INTFVER_FCOE     = 0x00,
3136 };
3137
3138 enum fw_hdr_flags {
3139         FW_HDR_FLAGS_RESET_HALT = 0x00000001,
3140 };
3141
3142 /* length of the formatting string  */
3143 #define FW_DEVLOG_FMT_LEN       192
3144
3145 /* maximum number of the formatting string parameters */
3146 #define FW_DEVLOG_FMT_PARAMS_NUM 8
3147
3148 /* priority levels */
3149 enum fw_devlog_level {
3150         FW_DEVLOG_LEVEL_EMERG   = 0x0,
3151         FW_DEVLOG_LEVEL_CRIT    = 0x1,
3152         FW_DEVLOG_LEVEL_ERR     = 0x2,
3153         FW_DEVLOG_LEVEL_NOTICE  = 0x3,
3154         FW_DEVLOG_LEVEL_INFO    = 0x4,
3155         FW_DEVLOG_LEVEL_DEBUG   = 0x5,
3156         FW_DEVLOG_LEVEL_MAX     = 0x5,
3157 };
3158
3159 /* facilities that may send a log message */
3160 enum fw_devlog_facility {
3161         FW_DEVLOG_FACILITY_CORE         = 0x00,
3162         FW_DEVLOG_FACILITY_CF           = 0x01,
3163         FW_DEVLOG_FACILITY_SCHED        = 0x02,
3164         FW_DEVLOG_FACILITY_TIMER        = 0x04,
3165         FW_DEVLOG_FACILITY_RES          = 0x06,
3166         FW_DEVLOG_FACILITY_HW           = 0x08,
3167         FW_DEVLOG_FACILITY_FLR          = 0x10,
3168         FW_DEVLOG_FACILITY_DMAQ         = 0x12,
3169         FW_DEVLOG_FACILITY_PHY          = 0x14,
3170         FW_DEVLOG_FACILITY_MAC          = 0x16,
3171         FW_DEVLOG_FACILITY_PORT         = 0x18,
3172         FW_DEVLOG_FACILITY_VI           = 0x1A,
3173         FW_DEVLOG_FACILITY_FILTER       = 0x1C,
3174         FW_DEVLOG_FACILITY_ACL          = 0x1E,
3175         FW_DEVLOG_FACILITY_TM           = 0x20,
3176         FW_DEVLOG_FACILITY_QFC          = 0x22,
3177         FW_DEVLOG_FACILITY_DCB          = 0x24,
3178         FW_DEVLOG_FACILITY_ETH          = 0x26,
3179         FW_DEVLOG_FACILITY_OFLD         = 0x28,
3180         FW_DEVLOG_FACILITY_RI           = 0x2A,
3181         FW_DEVLOG_FACILITY_ISCSI        = 0x2C,
3182         FW_DEVLOG_FACILITY_FCOE         = 0x2E,
3183         FW_DEVLOG_FACILITY_FOISCSI      = 0x30,
3184         FW_DEVLOG_FACILITY_FOFCOE       = 0x32,
3185         FW_DEVLOG_FACILITY_CHNET        = 0x34,
3186         FW_DEVLOG_FACILITY_MAX          = 0x34,
3187 };
3188
3189 /* log message format */
3190 struct fw_devlog_e {
3191         __be64  timestamp;
3192         __be32  seqno;
3193         __be16  reserved1;
3194         __u8    level;
3195         __u8    facility;
3196         __u8    fmt[FW_DEVLOG_FMT_LEN];
3197         __be32  params[FW_DEVLOG_FMT_PARAMS_NUM];
3198         __be32  reserved3[4];
3199 };
3200
3201 struct fw_devlog_cmd {
3202         __be32 op_to_write;
3203         __be32 retval_len16;
3204         __u8   level;
3205         __u8   r2[7];
3206         __be32 memtype_devlog_memaddr16_devlog;
3207         __be32 memsize_devlog;
3208         __be32 r3[2];
3209 };
3210
3211 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S          28
3212 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M          0xf
3213 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(x)       \
3214         (((x) >> FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S) & \
3215          FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M)
3216
3217 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S        0
3218 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M        0xfffffff
3219 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(x)     \
3220         (((x) >> FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S) & \
3221          FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M)
3222
3223 /* P C I E   F W   P F 7   R E G I S T E R */
3224
3225 /* PF7 stores the Firmware Device Log parameters which allows Host Drivers to
3226  * access the "devlog" which needing to contact firmware.  The encoding is
3227  * mostly the same as that returned by the DEVLOG command except for the size
3228  * which is encoded as the number of entries in multiples-1 of 128 here rather
3229  * than the memory size as is done in the DEVLOG command.  Thus, 0 means 128
3230  * and 15 means 2048.  This of course in turn constrains the allowed values
3231  * for the devlog size ...
3232  */
3233 #define PCIE_FW_PF_DEVLOG               7
3234
3235 #define PCIE_FW_PF_DEVLOG_NENTRIES128_S 28
3236 #define PCIE_FW_PF_DEVLOG_NENTRIES128_M 0xf
3237 #define PCIE_FW_PF_DEVLOG_NENTRIES128_V(x) \
3238         ((x) << PCIE_FW_PF_DEVLOG_NENTRIES128_S)
3239 #define PCIE_FW_PF_DEVLOG_NENTRIES128_G(x) \
3240         (((x) >> PCIE_FW_PF_DEVLOG_NENTRIES128_S) & \
3241          PCIE_FW_PF_DEVLOG_NENTRIES128_M)
3242
3243 #define PCIE_FW_PF_DEVLOG_ADDR16_S      4
3244 #define PCIE_FW_PF_DEVLOG_ADDR16_M      0xffffff
3245 #define PCIE_FW_PF_DEVLOG_ADDR16_V(x)   ((x) << PCIE_FW_PF_DEVLOG_ADDR16_S)
3246 #define PCIE_FW_PF_DEVLOG_ADDR16_G(x) \
3247         (((x) >> PCIE_FW_PF_DEVLOG_ADDR16_S) & PCIE_FW_PF_DEVLOG_ADDR16_M)
3248
3249 #define PCIE_FW_PF_DEVLOG_MEMTYPE_S     0
3250 #define PCIE_FW_PF_DEVLOG_MEMTYPE_M     0xf
3251 #define PCIE_FW_PF_DEVLOG_MEMTYPE_V(x)  ((x) << PCIE_FW_PF_DEVLOG_MEMTYPE_S)
3252 #define PCIE_FW_PF_DEVLOG_MEMTYPE_G(x) \
3253         (((x) >> PCIE_FW_PF_DEVLOG_MEMTYPE_S) & PCIE_FW_PF_DEVLOG_MEMTYPE_M)
3254
3255 #define MAX_IMM_OFLD_TX_DATA_WR_LEN (0xff + sizeof(struct fw_ofld_tx_data_wr))
3256
3257 struct fw_crypto_lookaside_wr {
3258         __be32 op_to_cctx_size;
3259         __be32 len16_pkd;
3260         __be32 session_id;
3261         __be32 rx_chid_to_rx_q_id;
3262         __be32 key_addr;
3263         __be32 pld_size_hash_size;
3264         __be64 cookie;
3265 };
3266
3267 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_S 24
3268 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_M 0xff
3269 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_V(x) \
3270         ((x) << FW_CRYPTO_LOOKASIDE_WR_OPCODE_S)
3271 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_G(x) \
3272         (((x) >> FW_CRYPTO_LOOKASIDE_WR_OPCODE_S) & \
3273          FW_CRYPTO_LOOKASIDE_WR_OPCODE_M)
3274
3275 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_S 23
3276 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_M 0x1
3277 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_V(x) \
3278         ((x) << FW_CRYPTO_LOOKASIDE_WR_COMPL_S)
3279 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_G(x) \
3280         (((x) >> FW_CRYPTO_LOOKASIDE_WR_COMPL_S) & \
3281          FW_CRYPTO_LOOKASIDE_WR_COMPL_M)
3282 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_F FW_CRYPTO_LOOKASIDE_WR_COMPL_V(1U)
3283
3284 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S 15
3285 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M 0xff
3286 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_V(x) \
3287         ((x) << FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S)
3288 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_G(x) \
3289         (((x) >> FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S) & \
3290          FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M)
3291
3292 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S 5
3293 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M 0x3
3294 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_V(x) \
3295         ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S)
3296 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_G(x) \
3297         (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S) & \
3298          FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M)
3299
3300 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S 0
3301 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M 0x1f
3302 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_V(x) \
3303         ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S)
3304 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_G(x) \
3305         (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S) & \
3306          FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M)
3307
3308 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_S 0
3309 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_M 0xff
3310 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_V(x) \
3311         ((x) << FW_CRYPTO_LOOKASIDE_WR_LEN16_S)
3312 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_G(x) \
3313         (((x) >> FW_CRYPTO_LOOKASIDE_WR_LEN16_S) & \
3314          FW_CRYPTO_LOOKASIDE_WR_LEN16_M)
3315
3316 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S 29
3317 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M 0x3
3318 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_V(x) \
3319         ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S)
3320 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_G(x) \
3321         (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S) & \
3322          FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M)
3323
3324 #define FW_CRYPTO_LOOKASIDE_WR_LCB_S  27
3325 #define FW_CRYPTO_LOOKASIDE_WR_LCB_M  0x3
3326 #define FW_CRYPTO_LOOKASIDE_WR_LCB_V(x) \
3327         ((x) << FW_CRYPTO_LOOKASIDE_WR_LCB_S)
3328 #define FW_CRYPTO_LOOKASIDE_WR_LCB_G(x) \
3329         (((x) >> FW_CRYPTO_LOOKASIDE_WR_LCB_S) & FW_CRYPTO_LOOKASIDE_WR_LCB_M)
3330
3331 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_S 25
3332 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_M 0x3
3333 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_V(x) \
3334         ((x) << FW_CRYPTO_LOOKASIDE_WR_PHASH_S)
3335 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_G(x) \
3336         (((x) >> FW_CRYPTO_LOOKASIDE_WR_PHASH_S) & \
3337          FW_CRYPTO_LOOKASIDE_WR_PHASH_M)
3338
3339 #define FW_CRYPTO_LOOKASIDE_WR_IV_S   23
3340 #define FW_CRYPTO_LOOKASIDE_WR_IV_M   0x3
3341 #define FW_CRYPTO_LOOKASIDE_WR_IV_V(x) \
3342         ((x) << FW_CRYPTO_LOOKASIDE_WR_IV_S)
3343 #define FW_CRYPTO_LOOKASIDE_WR_IV_G(x) \
3344         (((x) >> FW_CRYPTO_LOOKASIDE_WR_IV_S) & FW_CRYPTO_LOOKASIDE_WR_IV_M)
3345
3346 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_S 10
3347 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_M 0x3
3348 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_V(x) \
3349         ((x) << FW_CRYPTO_LOOKASIDE_WR_TX_CH_S)
3350 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_G(x) \
3351         (((x) >> FW_CRYPTO_LOOKASIDE_WR_TX_CH_S) & \
3352          FW_CRYPTO_LOOKASIDE_WR_TX_CH_M)
3353
3354 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S 0
3355 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M 0x3ff
3356 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_V(x) \
3357         ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S)
3358 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_G(x) \
3359         (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S) & \
3360          FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M)
3361
3362 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S 24
3363 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M 0xff
3364 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_V(x) \
3365         ((x) << FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S)
3366 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_G(x) \
3367         (((x) >> FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S) & \
3368          FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M)
3369
3370 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S 17
3371 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M 0x7f
3372 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_V(x) \
3373         ((x) << FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S)
3374 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_G(x) \
3375         (((x) >> FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S) & \
3376          FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M)
3377
3378 #endif /* _T4FW_INTERFACE_H_ */