drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2009-2014 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #ifndef _T4FW_INTERFACE_H_
  36 #define _T4FW_INTERFACE_H_
  37
  38 enum fw_retval {
  39         FW_SUCCESS              = 0,    /* completed successfully */
  40         FW_EPERM                = 1,    /* operation not permitted */
  41         FW_ENOENT               = 2,    /* no such file or directory */
  42         FW_EIO                  = 5,    /* input/output error; hw bad */
  43         FW_ENOEXEC              = 8,    /* exec format error; inv microcode */
  44         FW_EAGAIN               = 11,   /* try again */
  45         FW_ENOMEM               = 12,   /* out of memory */
  46         FW_EFAULT               = 14,   /* bad address; fw bad */
  47         FW_EBUSY                = 16,   /* resource busy */
  48         FW_EEXIST               = 17,   /* file exists */
  49         FW_ENODEV               = 19,   /* no such device */
  50         FW_EINVAL               = 22,   /* invalid argument */
  51         FW_ENOSPC               = 28,   /* no space left on device */
  52         FW_ENOSYS               = 38,   /* functionality not implemented */
  53         FW_ENODATA              = 61,   /* no data available */
  54         FW_EPROTO               = 71,   /* protocol error */
  55         FW_EADDRINUSE           = 98,   /* address already in use */
  56         FW_EADDRNOTAVAIL        = 99,   /* cannot assigned requested address */
  57         FW_ENETDOWN             = 100,  /* network is down */
  58         FW_ENETUNREACH          = 101,  /* network is unreachable */
  59         FW_ENOBUFS              = 105,  /* no buffer space available */
  60         FW_ETIMEDOUT            = 110,  /* timeout */
  61         FW_EINPROGRESS          = 115,  /* fw internal */
  62         FW_SCSI_ABORT_REQUESTED = 128,  /* */
  63         FW_SCSI_ABORT_TIMEDOUT  = 129,  /* */
  64         FW_SCSI_ABORTED         = 130,  /* */
  65         FW_SCSI_CLOSE_REQUESTED = 131,  /* */
  66         FW_ERR_LINK_DOWN        = 132,  /* */
  67         FW_RDEV_NOT_READY       = 133,  /* */
  68         FW_ERR_RDEV_LOST        = 134,  /* */
  69         FW_ERR_RDEV_LOGO        = 135,  /* */
  70         FW_FCOE_NO_XCHG         = 136,  /* */
  71         FW_SCSI_RSP_ERR         = 137,  /* */
  72         FW_ERR_RDEV_IMPL_LOGO   = 138,  /* */
  73         FW_SCSI_UNDER_FLOW_ERR  = 139,  /* */
  74         FW_SCSI_OVER_FLOW_ERR   = 140,  /* */
  75         FW_SCSI_DDP_ERR         = 141,  /* DDP error*/
  76         FW_SCSI_TASK_ERR        = 142,  /* No SCSI tasks available */
  77 };
  78
  79 #define FW_T4VF_SGE_BASE_ADDR      0x0000
  80 #define FW_T4VF_MPS_BASE_ADDR      0x0100
  81 #define FW_T4VF_PL_BASE_ADDR       0x0200
  82 #define FW_T4VF_MBDATA_BASE_ADDR   0x0240
  83 #define FW_T4VF_CIM_BASE_ADDR      0x0300
  84
  85 enum fw_wr_opcodes {
  86         FW_FILTER_WR                   = 0x02,
  87         FW_ULPTX_WR                    = 0x04,
  88         FW_TP_WR                       = 0x05,
  89         FW_ETH_TX_PKT_WR               = 0x08,
  90         FW_OFLD_CONNECTION_WR          = 0x2f,
  91         FW_FLOWC_WR                    = 0x0a,
  92         FW_OFLD_TX_DATA_WR             = 0x0b,
  93         FW_CMD_WR                      = 0x10,
  94         FW_ETH_TX_PKT_VM_WR            = 0x11,
  95         FW_RI_RES_WR                   = 0x0c,
  96         FW_RI_INIT_WR                  = 0x0d,
  97         FW_RI_RDMA_WRITE_WR            = 0x14,
  98         FW_RI_SEND_WR                  = 0x15,
  99         FW_RI_RDMA_READ_WR             = 0x16,
 100         FW_RI_RECV_WR                  = 0x17,
 101         FW_RI_BIND_MW_WR               = 0x18,
 102         FW_RI_FR_NSMR_WR               = 0x19,
 103         FW_RI_INV_LSTAG_WR             = 0x1a,
 104         FW_ISCSI_TX_DATA_WR            = 0x45,
 105         FW_CRYPTO_LOOKASIDE_WR         = 0X6d,
 106         FW_LASTC2E_WR                  = 0x70
 107 };
 108
 109 struct fw_wr_hdr {
 110         __be32 hi;
 111         __be32 lo;
 112 };
 113
 114 /* work request opcode (hi) */
 115 #define FW_WR_OP_S      24
 116 #define FW_WR_OP_M      0xff
 117 #define FW_WR_OP_V(x)   ((x) << FW_WR_OP_S)
 118 #define FW_WR_OP_G(x)   (((x) >> FW_WR_OP_S) & FW_WR_OP_M)
 119
 120 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */
 121 #define FW_WR_ATOMIC_S          23
 122 #define FW_WR_ATOMIC_V(x)       ((x) << FW_WR_ATOMIC_S)
 123
 124 /* flush flag (hi) - firmware flushes flushable work request buffered
 125  * in the flow context.
 126  */
 127 #define FW_WR_FLUSH_S     22
 128 #define FW_WR_FLUSH_V(x)  ((x) << FW_WR_FLUSH_S)
 129
 130 /* completion flag (hi) - firmware generates a cpl_fw6_ack */
 131 #define FW_WR_COMPL_S     21
 132 #define FW_WR_COMPL_V(x)  ((x) << FW_WR_COMPL_S)
 133 #define FW_WR_COMPL_F     FW_WR_COMPL_V(1U)
 134
 135 /* work request immediate data length (hi) */
 136 #define FW_WR_IMMDLEN_S 0
 137 #define FW_WR_IMMDLEN_M 0xff
 138 #define FW_WR_IMMDLEN_V(x)      ((x) << FW_WR_IMMDLEN_S)
 139
 140 /* egress queue status update to associated ingress queue entry (lo) */
 141 #define FW_WR_EQUIQ_S           31
 142 #define FW_WR_EQUIQ_V(x)        ((x) << FW_WR_EQUIQ_S)
 143 #define FW_WR_EQUIQ_F           FW_WR_EQUIQ_V(1U)
 144
 145 /* egress queue status update to egress queue status entry (lo) */
 146 #define FW_WR_EQUEQ_S           30
 147 #define FW_WR_EQUEQ_V(x)        ((x) << FW_WR_EQUEQ_S)
 148 #define FW_WR_EQUEQ_F           FW_WR_EQUEQ_V(1U)
 149
 150 /* flow context identifier (lo) */
 151 #define FW_WR_FLOWID_S          8
 152 #define FW_WR_FLOWID_V(x)       ((x) << FW_WR_FLOWID_S)
 153
 154 /* length in units of 16-bytes (lo) */
 155 #define FW_WR_LEN16_S           0
 156 #define FW_WR_LEN16_V(x)        ((x) << FW_WR_LEN16_S)
 157
 158 #define HW_TPL_FR_MT_PR_IV_P_FC         0X32B
 159 #define HW_TPL_FR_MT_PR_OV_P_FC         0X327
 160
 161 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
 162 enum fw_filter_wr_cookie {
 163         FW_FILTER_WR_SUCCESS,
 164         FW_FILTER_WR_FLT_ADDED,
 165         FW_FILTER_WR_FLT_DELETED,
 166         FW_FILTER_WR_SMT_TBL_FULL,
 167         FW_FILTER_WR_EINVAL,
 168 };
 169
 170 struct fw_filter_wr {
 171         __be32 op_pkd;
 172         __be32 len16_pkd;
 173         __be64 r3;
 174         __be32 tid_to_iq;
 175         __be32 del_filter_to_l2tix;
 176         __be16 ethtype;
 177         __be16 ethtypem;
 178         __u8   frag_to_ovlan_vldm;
 179         __u8   smac_sel;
 180         __be16 rx_chan_rx_rpl_iq;
 181         __be32 maci_to_matchtypem;
 182         __u8   ptcl;
 183         __u8   ptclm;
 184         __u8   ttyp;
 185         __u8   ttypm;
 186         __be16 ivlan;
 187         __be16 ivlanm;
 188         __be16 ovlan;
 189         __be16 ovlanm;
 190         __u8   lip[16];
 191         __u8   lipm[16];
 192         __u8   fip[16];
 193         __u8   fipm[16];
 194         __be16 lp;
 195         __be16 lpm;
 196         __be16 fp;
 197         __be16 fpm;
 198         __be16 r7;
 199         __u8   sma[6];
 200 };
 201
 202 #define FW_FILTER_WR_TID_S      12
 203 #define FW_FILTER_WR_TID_M      0xfffff
 204 #define FW_FILTER_WR_TID_V(x)   ((x) << FW_FILTER_WR_TID_S)
 205 #define FW_FILTER_WR_TID_G(x)   \
 206         (((x) >> FW_FILTER_WR_TID_S) & FW_FILTER_WR_TID_M)
 207
 208 #define FW_FILTER_WR_RQTYPE_S           11
 209 #define FW_FILTER_WR_RQTYPE_M           0x1
 210 #define FW_FILTER_WR_RQTYPE_V(x)        ((x) << FW_FILTER_WR_RQTYPE_S)
 211 #define FW_FILTER_WR_RQTYPE_G(x)        \
 212         (((x) >> FW_FILTER_WR_RQTYPE_S) & FW_FILTER_WR_RQTYPE_M)
 213 #define FW_FILTER_WR_RQTYPE_F   FW_FILTER_WR_RQTYPE_V(1U)
 214
 215 #define FW_FILTER_WR_NOREPLY_S          10
 216 #define FW_FILTER_WR_NOREPLY_M          0x1
 217 #define FW_FILTER_WR_NOREPLY_V(x)       ((x) << FW_FILTER_WR_NOREPLY_S)
 218 #define FW_FILTER_WR_NOREPLY_G(x)       \
 219         (((x) >> FW_FILTER_WR_NOREPLY_S) & FW_FILTER_WR_NOREPLY_M)
 220 #define FW_FILTER_WR_NOREPLY_F  FW_FILTER_WR_NOREPLY_V(1U)
 221
 222 #define FW_FILTER_WR_IQ_S       0
 223 #define FW_FILTER_WR_IQ_M       0x3ff
 224 #define FW_FILTER_WR_IQ_V(x)    ((x) << FW_FILTER_WR_IQ_S)
 225 #define FW_FILTER_WR_IQ_G(x)    \
 226         (((x) >> FW_FILTER_WR_IQ_S) & FW_FILTER_WR_IQ_M)
 227
 228 #define FW_FILTER_WR_DEL_FILTER_S       31
 229 #define FW_FILTER_WR_DEL_FILTER_M       0x1
 230 #define FW_FILTER_WR_DEL_FILTER_V(x)    ((x) << FW_FILTER_WR_DEL_FILTER_S)
 231 #define FW_FILTER_WR_DEL_FILTER_G(x)    \
 232         (((x) >> FW_FILTER_WR_DEL_FILTER_S) & FW_FILTER_WR_DEL_FILTER_M)
 233 #define FW_FILTER_WR_DEL_FILTER_F       FW_FILTER_WR_DEL_FILTER_V(1U)
 234
 235 #define FW_FILTER_WR_RPTTID_S           25
 236 #define FW_FILTER_WR_RPTTID_M           0x1
 237 #define FW_FILTER_WR_RPTTID_V(x)        ((x) << FW_FILTER_WR_RPTTID_S)
 238 #define FW_FILTER_WR_RPTTID_G(x)        \
 239         (((x) >> FW_FILTER_WR_RPTTID_S) & FW_FILTER_WR_RPTTID_M)
 240 #define FW_FILTER_WR_RPTTID_F   FW_FILTER_WR_RPTTID_V(1U)
 241
 242 #define FW_FILTER_WR_DROP_S     24
 243 #define FW_FILTER_WR_DROP_M     0x1
 244 #define FW_FILTER_WR_DROP_V(x)  ((x) << FW_FILTER_WR_DROP_S)
 245 #define FW_FILTER_WR_DROP_G(x)  \
 246         (((x) >> FW_FILTER_WR_DROP_S) & FW_FILTER_WR_DROP_M)
 247 #define FW_FILTER_WR_DROP_F     FW_FILTER_WR_DROP_V(1U)
 248
 249 #define FW_FILTER_WR_DIRSTEER_S         23
 250 #define FW_FILTER_WR_DIRSTEER_M         0x1
 251 #define FW_FILTER_WR_DIRSTEER_V(x)      ((x) << FW_FILTER_WR_DIRSTEER_S)
 252 #define FW_FILTER_WR_DIRSTEER_G(x)      \
 253         (((x) >> FW_FILTER_WR_DIRSTEER_S) & FW_FILTER_WR_DIRSTEER_M)
 254 #define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1U)
 255
 256 #define FW_FILTER_WR_MASKHASH_S         22
 257 #define FW_FILTER_WR_MASKHASH_M         0x1
 258 #define FW_FILTER_WR_MASKHASH_V(x)      ((x) << FW_FILTER_WR_MASKHASH_S)
 259 #define FW_FILTER_WR_MASKHASH_G(x)      \
 260         (((x) >> FW_FILTER_WR_MASKHASH_S) & FW_FILTER_WR_MASKHASH_M)
 261 #define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1U)
 262
 263 #define FW_FILTER_WR_DIRSTEERHASH_S     21
 264 #define FW_FILTER_WR_DIRSTEERHASH_M     0x1
 265 #define FW_FILTER_WR_DIRSTEERHASH_V(x)  ((x) << FW_FILTER_WR_DIRSTEERHASH_S)
 266 #define FW_FILTER_WR_DIRSTEERHASH_G(x)  \
 267         (((x) >> FW_FILTER_WR_DIRSTEERHASH_S) & FW_FILTER_WR_DIRSTEERHASH_M)
 268 #define FW_FILTER_WR_DIRSTEERHASH_F     FW_FILTER_WR_DIRSTEERHASH_V(1U)
 269
 270 #define FW_FILTER_WR_LPBK_S     20
 271 #define FW_FILTER_WR_LPBK_M     0x1
 272 #define FW_FILTER_WR_LPBK_V(x)  ((x) << FW_FILTER_WR_LPBK_S)
 273 #define FW_FILTER_WR_LPBK_G(x)  \
 274         (((x) >> FW_FILTER_WR_LPBK_S) & FW_FILTER_WR_LPBK_M)
 275 #define FW_FILTER_WR_LPBK_F     FW_FILTER_WR_LPBK_V(1U)
 276
 277 #define FW_FILTER_WR_DMAC_S     19
 278 #define FW_FILTER_WR_DMAC_M     0x1
 279 #define FW_FILTER_WR_DMAC_V(x)  ((x) << FW_FILTER_WR_DMAC_S)
 280 #define FW_FILTER_WR_DMAC_G(x)  \
 281         (((x) >> FW_FILTER_WR_DMAC_S) & FW_FILTER_WR_DMAC_M)
 282 #define FW_FILTER_WR_DMAC_F     FW_FILTER_WR_DMAC_V(1U)
 283
 284 #define FW_FILTER_WR_SMAC_S     18
 285 #define FW_FILTER_WR_SMAC_M     0x1
 286 #define FW_FILTER_WR_SMAC_V(x)  ((x) << FW_FILTER_WR_SMAC_S)
 287 #define FW_FILTER_WR_SMAC_G(x)  \
 288         (((x) >> FW_FILTER_WR_SMAC_S) & FW_FILTER_WR_SMAC_M)
 289 #define FW_FILTER_WR_SMAC_F     FW_FILTER_WR_SMAC_V(1U)
 290
 291 #define FW_FILTER_WR_INSVLAN_S          17
 292 #define FW_FILTER_WR_INSVLAN_M          0x1
 293 #define FW_FILTER_WR_INSVLAN_V(x)       ((x) << FW_FILTER_WR_INSVLAN_S)
 294 #define FW_FILTER_WR_INSVLAN_G(x)       \
 295         (((x) >> FW_FILTER_WR_INSVLAN_S) & FW_FILTER_WR_INSVLAN_M)
 296 #define FW_FILTER_WR_INSVLAN_F  FW_FILTER_WR_INSVLAN_V(1U)
 297
 298 #define FW_FILTER_WR_RMVLAN_S           16
 299 #define FW_FILTER_WR_RMVLAN_M           0x1
 300 #define FW_FILTER_WR_RMVLAN_V(x)        ((x) << FW_FILTER_WR_RMVLAN_S)
 301 #define FW_FILTER_WR_RMVLAN_G(x)        \
 302         (((x) >> FW_FILTER_WR_RMVLAN_S) & FW_FILTER_WR_RMVLAN_M)
 303 #define FW_FILTER_WR_RMVLAN_F   FW_FILTER_WR_RMVLAN_V(1U)
 304
 305 #define FW_FILTER_WR_HITCNTS_S          15
 306 #define FW_FILTER_WR_HITCNTS_M          0x1
 307 #define FW_FILTER_WR_HITCNTS_V(x)       ((x) << FW_FILTER_WR_HITCNTS_S)
 308 #define FW_FILTER_WR_HITCNTS_G(x)       \
 309         (((x) >> FW_FILTER_WR_HITCNTS_S) & FW_FILTER_WR_HITCNTS_M)
 310 #define FW_FILTER_WR_HITCNTS_F  FW_FILTER_WR_HITCNTS_V(1U)
 311
 312 #define FW_FILTER_WR_TXCHAN_S           13
 313 #define FW_FILTER_WR_TXCHAN_M           0x3
 314 #define FW_FILTER_WR_TXCHAN_V(x)        ((x) << FW_FILTER_WR_TXCHAN_S)
 315 #define FW_FILTER_WR_TXCHAN_G(x)        \
 316         (((x) >> FW_FILTER_WR_TXCHAN_S) & FW_FILTER_WR_TXCHAN_M)
 317
 318 #define FW_FILTER_WR_PRIO_S     12
 319 #define FW_FILTER_WR_PRIO_M     0x1
 320 #define FW_FILTER_WR_PRIO_V(x)  ((x) << FW_FILTER_WR_PRIO_S)
 321 #define FW_FILTER_WR_PRIO_G(x)  \
 322         (((x) >> FW_FILTER_WR_PRIO_S) & FW_FILTER_WR_PRIO_M)
 323 #define FW_FILTER_WR_PRIO_F     FW_FILTER_WR_PRIO_V(1U)
 324
 325 #define FW_FILTER_WR_L2TIX_S    0
 326 #define FW_FILTER_WR_L2TIX_M    0xfff
 327 #define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S)
 328 #define FW_FILTER_WR_L2TIX_G(x) \
 329         (((x) >> FW_FILTER_WR_L2TIX_S) & FW_FILTER_WR_L2TIX_M)
 330
 331 #define FW_FILTER_WR_FRAG_S     7
 332 #define FW_FILTER_WR_FRAG_M     0x1
 333 #define FW_FILTER_WR_FRAG_V(x)  ((x) << FW_FILTER_WR_FRAG_S)
 334 #define FW_FILTER_WR_FRAG_G(x)  \
 335         (((x) >> FW_FILTER_WR_FRAG_S) & FW_FILTER_WR_FRAG_M)
 336 #define FW_FILTER_WR_FRAG_F     FW_FILTER_WR_FRAG_V(1U)
 337
 338 #define FW_FILTER_WR_FRAGM_S    6
 339 #define FW_FILTER_WR_FRAGM_M    0x1
 340 #define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S)
 341 #define FW_FILTER_WR_FRAGM_G(x) \
 342         (((x) >> FW_FILTER_WR_FRAGM_S) & FW_FILTER_WR_FRAGM_M)
 343 #define FW_FILTER_WR_FRAGM_F    FW_FILTER_WR_FRAGM_V(1U)
 344
 345 #define FW_FILTER_WR_IVLAN_VLD_S        5
 346 #define FW_FILTER_WR_IVLAN_VLD_M        0x1
 347 #define FW_FILTER_WR_IVLAN_VLD_V(x)     ((x) << FW_FILTER_WR_IVLAN_VLD_S)
 348 #define FW_FILTER_WR_IVLAN_VLD_G(x)     \
 349         (((x) >> FW_FILTER_WR_IVLAN_VLD_S) & FW_FILTER_WR_IVLAN_VLD_M)
 350 #define FW_FILTER_WR_IVLAN_VLD_F        FW_FILTER_WR_IVLAN_VLD_V(1U)
 351
 352 #define FW_FILTER_WR_OVLAN_VLD_S        4
 353 #define FW_FILTER_WR_OVLAN_VLD_M        0x1
 354 #define FW_FILTER_WR_OVLAN_VLD_V(x)     ((x) << FW_FILTER_WR_OVLAN_VLD_S)
 355 #define FW_FILTER_WR_OVLAN_VLD_G(x)     \
 356         (((x) >> FW_FILTER_WR_OVLAN_VLD_S) & FW_FILTER_WR_OVLAN_VLD_M)
 357 #define FW_FILTER_WR_OVLAN_VLD_F        FW_FILTER_WR_OVLAN_VLD_V(1U)
 358
 359 #define FW_FILTER_WR_IVLAN_VLDM_S       3
 360 #define FW_FILTER_WR_IVLAN_VLDM_M       0x1
 361 #define FW_FILTER_WR_IVLAN_VLDM_V(x)    ((x) << FW_FILTER_WR_IVLAN_VLDM_S)
 362 #define FW_FILTER_WR_IVLAN_VLDM_G(x)    \
 363         (((x) >> FW_FILTER_WR_IVLAN_VLDM_S) & FW_FILTER_WR_IVLAN_VLDM_M)
 364 #define FW_FILTER_WR_IVLAN_VLDM_F       FW_FILTER_WR_IVLAN_VLDM_V(1U)
 365
 366 #define FW_FILTER_WR_OVLAN_VLDM_S       2
 367 #define FW_FILTER_WR_OVLAN_VLDM_M       0x1
 368 #define FW_FILTER_WR_OVLAN_VLDM_V(x)    ((x) << FW_FILTER_WR_OVLAN_VLDM_S)
 369 #define FW_FILTER_WR_OVLAN_VLDM_G(x)    \
 370         (((x) >> FW_FILTER_WR_OVLAN_VLDM_S) & FW_FILTER_WR_OVLAN_VLDM_M)
 371 #define FW_FILTER_WR_OVLAN_VLDM_F       FW_FILTER_WR_OVLAN_VLDM_V(1U)
 372
 373 #define FW_FILTER_WR_RX_CHAN_S          15
 374 #define FW_FILTER_WR_RX_CHAN_M          0x1
 375 #define FW_FILTER_WR_RX_CHAN_V(x)       ((x) << FW_FILTER_WR_RX_CHAN_S)
 376 #define FW_FILTER_WR_RX_CHAN_G(x)       \
 377         (((x) >> FW_FILTER_WR_RX_CHAN_S) & FW_FILTER_WR_RX_CHAN_M)
 378 #define FW_FILTER_WR_RX_CHAN_F  FW_FILTER_WR_RX_CHAN_V(1U)
 379
 380 #define FW_FILTER_WR_RX_RPL_IQ_S        0
 381 #define FW_FILTER_WR_RX_RPL_IQ_M        0x3ff
 382 #define FW_FILTER_WR_RX_RPL_IQ_V(x)     ((x) << FW_FILTER_WR_RX_RPL_IQ_S)
 383 #define FW_FILTER_WR_RX_RPL_IQ_G(x)     \
 384         (((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M)
 385
 386 #define FW_FILTER_WR_MACI_S     23
 387 #define FW_FILTER_WR_MACI_M     0x1ff
 388 #define FW_FILTER_WR_MACI_V(x)  ((x) << FW_FILTER_WR_MACI_S)
 389 #define FW_FILTER_WR_MACI_G(x)  \
 390         (((x) >> FW_FILTER_WR_MACI_S) & FW_FILTER_WR_MACI_M)
 391
 392 #define FW_FILTER_WR_MACIM_S    14
 393 #define FW_FILTER_WR_MACIM_M    0x1ff
 394 #define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S)
 395 #define FW_FILTER_WR_MACIM_G(x) \
 396         (((x) >> FW_FILTER_WR_MACIM_S) & FW_FILTER_WR_MACIM_M)
 397
 398 #define FW_FILTER_WR_FCOE_S     13
 399 #define FW_FILTER_WR_FCOE_M     0x1
 400 #define FW_FILTER_WR_FCOE_V(x)  ((x) << FW_FILTER_WR_FCOE_S)
 401 #define FW_FILTER_WR_FCOE_G(x)  \
 402         (((x) >> FW_FILTER_WR_FCOE_S) & FW_FILTER_WR_FCOE_M)
 403 #define FW_FILTER_WR_FCOE_F     FW_FILTER_WR_FCOE_V(1U)
 404
 405 #define FW_FILTER_WR_FCOEM_S    12
 406 #define FW_FILTER_WR_FCOEM_M    0x1
 407 #define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S)
 408 #define FW_FILTER_WR_FCOEM_G(x) \
 409         (((x) >> FW_FILTER_WR_FCOEM_S) & FW_FILTER_WR_FCOEM_M)
 410 #define FW_FILTER_WR_FCOEM_F    FW_FILTER_WR_FCOEM_V(1U)
 411
 412 #define FW_FILTER_WR_PORT_S     9
 413 #define FW_FILTER_WR_PORT_M     0x7
 414 #define FW_FILTER_WR_PORT_V(x)  ((x) << FW_FILTER_WR_PORT_S)
 415 #define FW_FILTER_WR_PORT_G(x)  \
 416         (((x) >> FW_FILTER_WR_PORT_S) & FW_FILTER_WR_PORT_M)
 417
 418 #define FW_FILTER_WR_PORTM_S    6
 419 #define FW_FILTER_WR_PORTM_M    0x7
 420 #define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S)
 421 #define FW_FILTER_WR_PORTM_G(x) \
 422         (((x) >> FW_FILTER_WR_PORTM_S) & FW_FILTER_WR_PORTM_M)
 423
 424 #define FW_FILTER_WR_MATCHTYPE_S        3
 425 #define FW_FILTER_WR_MATCHTYPE_M        0x7
 426 #define FW_FILTER_WR_MATCHTYPE_V(x)     ((x) << FW_FILTER_WR_MATCHTYPE_S)
 427 #define FW_FILTER_WR_MATCHTYPE_G(x)     \
 428         (((x) >> FW_FILTER_WR_MATCHTYPE_S) & FW_FILTER_WR_MATCHTYPE_M)
 429
 430 #define FW_FILTER_WR_MATCHTYPEM_S       0
 431 #define FW_FILTER_WR_MATCHTYPEM_M       0x7
 432 #define FW_FILTER_WR_MATCHTYPEM_V(x)    ((x) << FW_FILTER_WR_MATCHTYPEM_S)
 433 #define FW_FILTER_WR_MATCHTYPEM_G(x)    \
 434         (((x) >> FW_FILTER_WR_MATCHTYPEM_S) & FW_FILTER_WR_MATCHTYPEM_M)
 435
 436 struct fw_ulptx_wr {
 437         __be32 op_to_compl;
 438         __be32 flowid_len16;
 439         u64 cookie;
 440 };
 441
 442 struct fw_tp_wr {
 443         __be32 op_to_immdlen;
 444         __be32 flowid_len16;
 445         u64 cookie;
 446 };
 447
 448 struct fw_eth_tx_pkt_wr {
 449         __be32 op_immdlen;
 450         __be32 equiq_to_len16;
 451         __be64 r3;
 452 };
 453
 454 struct fw_ofld_connection_wr {
 455         __be32 op_compl;
 456         __be32 len16_pkd;
 457         __u64  cookie;
 458         __be64 r2;
 459         __be64 r3;
 460         struct fw_ofld_connection_le {
 461                 __be32 version_cpl;
 462                 __be32 filter;
 463                 __be32 r1;
 464                 __be16 lport;
 465                 __be16 pport;
 466                 union fw_ofld_connection_leip {
 467                         struct fw_ofld_connection_le_ipv4 {
 468                                 __be32 pip;
 469                                 __be32 lip;
 470                                 __be64 r0;
 471                                 __be64 r1;
 472                                 __be64 r2;
 473                         } ipv4;
 474                         struct fw_ofld_connection_le_ipv6 {
 475                                 __be64 pip_hi;
 476                                 __be64 pip_lo;
 477                                 __be64 lip_hi;
 478                                 __be64 lip_lo;
 479                         } ipv6;
 480                 } u;
 481         } le;
 482         struct fw_ofld_connection_tcb {
 483                 __be32 t_state_to_astid;
 484                 __be16 cplrxdataack_cplpassacceptrpl;
 485                 __be16 rcv_adv;
 486                 __be32 rcv_nxt;
 487                 __be32 tx_max;
 488                 __be64 opt0;
 489                 __be32 opt2;
 490                 __be32 r1;
 491                 __be64 r2;
 492                 __be64 r3;
 493         } tcb;
 494 };
 495
 496 #define FW_OFLD_CONNECTION_WR_VERSION_S                31
 497 #define FW_OFLD_CONNECTION_WR_VERSION_M                0x1
 498 #define FW_OFLD_CONNECTION_WR_VERSION_V(x)     \
 499         ((x) << FW_OFLD_CONNECTION_WR_VERSION_S)
 500 #define FW_OFLD_CONNECTION_WR_VERSION_G(x)     \
 501         (((x) >> FW_OFLD_CONNECTION_WR_VERSION_S) & \
 502         FW_OFLD_CONNECTION_WR_VERSION_M)
 503 #define FW_OFLD_CONNECTION_WR_VERSION_F        \
 504         FW_OFLD_CONNECTION_WR_VERSION_V(1U)
 505
 506 #define FW_OFLD_CONNECTION_WR_CPL_S    30
 507 #define FW_OFLD_CONNECTION_WR_CPL_M    0x1
 508 #define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S)
 509 #define FW_OFLD_CONNECTION_WR_CPL_G(x) \
 510         (((x) >> FW_OFLD_CONNECTION_WR_CPL_S) & FW_OFLD_CONNECTION_WR_CPL_M)
 511 #define FW_OFLD_CONNECTION_WR_CPL_F    FW_OFLD_CONNECTION_WR_CPL_V(1U)
 512
 513 #define FW_OFLD_CONNECTION_WR_T_STATE_S                28
 514 #define FW_OFLD_CONNECTION_WR_T_STATE_M                0xf
 515 #define FW_OFLD_CONNECTION_WR_T_STATE_V(x)     \
 516         ((x) << FW_OFLD_CONNECTION_WR_T_STATE_S)
 517 #define FW_OFLD_CONNECTION_WR_T_STATE_G(x)     \
 518         (((x) >> FW_OFLD_CONNECTION_WR_T_STATE_S) & \
 519         FW_OFLD_CONNECTION_WR_T_STATE_M)
 520
 521 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_S      24
 522 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_M      0xf
 523 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x)   \
 524         ((x) << FW_OFLD_CONNECTION_WR_RCV_SCALE_S)
 525 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x)   \
 526         (((x) >> FW_OFLD_CONNECTION_WR_RCV_SCALE_S) & \
 527         FW_OFLD_CONNECTION_WR_RCV_SCALE_M)
 528
 529 #define FW_OFLD_CONNECTION_WR_ASTID_S          0
 530 #define FW_OFLD_CONNECTION_WR_ASTID_M          0xffffff
 531 #define FW_OFLD_CONNECTION_WR_ASTID_V(x)       \
 532         ((x) << FW_OFLD_CONNECTION_WR_ASTID_S)
 533 #define FW_OFLD_CONNECTION_WR_ASTID_G(x)       \
 534         (((x) >> FW_OFLD_CONNECTION_WR_ASTID_S) & FW_OFLD_CONNECTION_WR_ASTID_M)
 535
 536 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S   15
 537 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M   0x1
 538 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x)        \
 539         ((x) << FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S)
 540 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x)        \
 541         (((x) >> FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) & \
 542         FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M)
 543 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F   \
 544         FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(1U)
 545
 546 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S       14
 547 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M       0x1
 548 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x)    \
 549         ((x) << FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S)
 550 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x)    \
 551         (((x) >> FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) & \
 552         FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M)
 553 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F       \
 554         FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(1U)
 555
 556 enum fw_flowc_mnem {
 557         FW_FLOWC_MNEM_PFNVFN,           /* PFN [15:8] VFN [7:0] */
 558         FW_FLOWC_MNEM_CH,
 559         FW_FLOWC_MNEM_PORT,
 560         FW_FLOWC_MNEM_IQID,
 561         FW_FLOWC_MNEM_SNDNXT,
 562         FW_FLOWC_MNEM_RCVNXT,
 563         FW_FLOWC_MNEM_SNDBUF,
 564         FW_FLOWC_MNEM_MSS,
 565         FW_FLOWC_MNEM_TXDATAPLEN_MAX,
 566         FW_FLOWC_MNEM_TCPSTATE,
 567         FW_FLOWC_MNEM_EOSTATE,
 568         FW_FLOWC_MNEM_SCHEDCLASS,
 569         FW_FLOWC_MNEM_DCBPRIO,
 570         FW_FLOWC_MNEM_SND_SCALE,
 571         FW_FLOWC_MNEM_RCV_SCALE,
 572 };
 573
 574 struct fw_flowc_mnemval {
 575         u8 mnemonic;
 576         u8 r4[3];
 577         __be32 val;
 578 };
 579
 580 struct fw_flowc_wr {
 581         __be32 op_to_nparams;
 582         __be32 flowid_len16;
 583         struct fw_flowc_mnemval mnemval[0];
 584 };
 585
 586 #define FW_FLOWC_WR_NPARAMS_S           0
 587 #define FW_FLOWC_WR_NPARAMS_V(x)        ((x) << FW_FLOWC_WR_NPARAMS_S)
 588
 589 struct fw_ofld_tx_data_wr {
 590         __be32 op_to_immdlen;
 591         __be32 flowid_len16;
 592         __be32 plen;
 593         __be32 tunnel_to_proxy;
 594 };
 595
 596 #define FW_OFLD_TX_DATA_WR_TUNNEL_S     19
 597 #define FW_OFLD_TX_DATA_WR_TUNNEL_V(x)  ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S)
 598
 599 #define FW_OFLD_TX_DATA_WR_SAVE_S       18
 600 #define FW_OFLD_TX_DATA_WR_SAVE_V(x)    ((x) << FW_OFLD_TX_DATA_WR_SAVE_S)
 601
 602 #define FW_OFLD_TX_DATA_WR_FLUSH_S      17
 603 #define FW_OFLD_TX_DATA_WR_FLUSH_V(x)   ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S)
 604 #define FW_OFLD_TX_DATA_WR_FLUSH_F      FW_OFLD_TX_DATA_WR_FLUSH_V(1U)
 605
 606 #define FW_OFLD_TX_DATA_WR_URGENT_S     16
 607 #define FW_OFLD_TX_DATA_WR_URGENT_V(x)  ((x) << FW_OFLD_TX_DATA_WR_URGENT_S)
 608
 609 #define FW_OFLD_TX_DATA_WR_MORE_S       15
 610 #define FW_OFLD_TX_DATA_WR_MORE_V(x)    ((x) << FW_OFLD_TX_DATA_WR_MORE_S)
 611
 612 #define FW_OFLD_TX_DATA_WR_SHOVE_S      14
 613 #define FW_OFLD_TX_DATA_WR_SHOVE_V(x)   ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S)
 614 #define FW_OFLD_TX_DATA_WR_SHOVE_F      FW_OFLD_TX_DATA_WR_SHOVE_V(1U)
 615
 616 #define FW_OFLD_TX_DATA_WR_ULPMODE_S    10
 617 #define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S)
 618
 619 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S         6
 620 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x)      \
 621         ((x) << FW_OFLD_TX_DATA_WR_ULPSUBMODE_S)
 622
 623 struct fw_cmd_wr {
 624         __be32 op_dma;
 625         __be32 len16_pkd;
 626         __be64 cookie_daddr;
 627 };
 628
 629 #define FW_CMD_WR_DMA_S         17
 630 #define FW_CMD_WR_DMA_V(x)      ((x) << FW_CMD_WR_DMA_S)
 631
 632 struct fw_eth_tx_pkt_vm_wr {
 633         __be32 op_immdlen;
 634         __be32 equiq_to_len16;
 635         __be32 r3[2];
 636         u8 ethmacdst[6];
 637         u8 ethmacsrc[6];
 638         __be16 ethtype;
 639         __be16 vlantci;
 640 };
 641
 642 #define FW_CMD_MAX_TIMEOUT 10000
 643
 644 /*
 645  * If a host driver does a HELLO and discovers that there's already a MASTER
 646  * selected, we may have to wait for that MASTER to finish issuing RESET,
 647  * configuration and INITIALIZE commands.  Also, there's a possibility that
 648  * our own HELLO may get lost if it happens right as the MASTER is issuign a
 649  * RESET command, so we need to be willing to make a few retries of our HELLO.
 650  */
 651 #define FW_CMD_HELLO_TIMEOUT    (3 * FW_CMD_MAX_TIMEOUT)
 652 #define FW_CMD_HELLO_RETRIES    3
 653
 654
 655 enum fw_cmd_opcodes {
 656         FW_LDST_CMD                    = 0x01,
 657         FW_RESET_CMD                   = 0x03,
 658         FW_HELLO_CMD                   = 0x04,
 659         FW_BYE_CMD                     = 0x05,
 660         FW_INITIALIZE_CMD              = 0x06,
 661         FW_CAPS_CONFIG_CMD             = 0x07,
 662         FW_PARAMS_CMD                  = 0x08,
 663         FW_PFVF_CMD                    = 0x09,
 664         FW_IQ_CMD                      = 0x10,
 665         FW_EQ_MNGT_CMD                 = 0x11,
 666         FW_EQ_ETH_CMD                  = 0x12,
 667         FW_EQ_CTRL_CMD                 = 0x13,
 668         FW_EQ_OFLD_CMD                 = 0x21,
 669         FW_VI_CMD                      = 0x14,
 670         FW_VI_MAC_CMD                  = 0x15,
 671         FW_VI_RXMODE_CMD               = 0x16,
 672         FW_VI_ENABLE_CMD               = 0x17,
 673         FW_ACL_MAC_CMD                 = 0x18,
 674         FW_ACL_VLAN_CMD                = 0x19,
 675         FW_VI_STATS_CMD                = 0x1a,
 676         FW_PORT_CMD                    = 0x1b,
 677         FW_PORT_STATS_CMD              = 0x1c,
 678         FW_PORT_LB_STATS_CMD           = 0x1d,
 679         FW_PORT_TRACE_CMD              = 0x1e,
 680         FW_PORT_TRACE_MMAP_CMD         = 0x1f,
 681         FW_RSS_IND_TBL_CMD             = 0x20,
 682         FW_RSS_GLB_CONFIG_CMD          = 0x22,
 683         FW_RSS_VI_CONFIG_CMD           = 0x23,
 684         FW_DEVLOG_CMD                  = 0x25,
 685         FW_CLIP_CMD                    = 0x28,
 686         FW_LASTC2E_CMD                 = 0x40,
 687         FW_ERROR_CMD                   = 0x80,
 688         FW_DEBUG_CMD                   = 0x81,
 689 };
 690
 691 enum fw_cmd_cap {
 692         FW_CMD_CAP_PF                  = 0x01,
 693         FW_CMD_CAP_DMAQ                = 0x02,
 694         FW_CMD_CAP_PORT                = 0x04,
 695         FW_CMD_CAP_PORTPROMISC         = 0x08,
 696         FW_CMD_CAP_PORTSTATS           = 0x10,
 697         FW_CMD_CAP_VF                  = 0x80,
 698 };
 699
 700 /*
 701  * Generic command header flit0
 702  */
 703 struct fw_cmd_hdr {
 704         __be32 hi;
 705         __be32 lo;
 706 };
 707
 708 #define FW_CMD_OP_S             24
 709 #define FW_CMD_OP_M             0xff
 710 #define FW_CMD_OP_V(x)          ((x) << FW_CMD_OP_S)
 711 #define FW_CMD_OP_G(x)          (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M)
 712
 713 #define FW_CMD_REQUEST_S        23
 714 #define FW_CMD_REQUEST_V(x)     ((x) << FW_CMD_REQUEST_S)
 715 #define FW_CMD_REQUEST_F        FW_CMD_REQUEST_V(1U)
 716
 717 #define FW_CMD_READ_S           22
 718 #define FW_CMD_READ_V(x)        ((x) << FW_CMD_READ_S)
 719 #define FW_CMD_READ_F           FW_CMD_READ_V(1U)
 720
 721 #define FW_CMD_WRITE_S          21
 722 #define FW_CMD_WRITE_V(x)       ((x) << FW_CMD_WRITE_S)
 723 #define FW_CMD_WRITE_F          FW_CMD_WRITE_V(1U)
 724
 725 #define FW_CMD_EXEC_S           20
 726 #define FW_CMD_EXEC_V(x)        ((x) << FW_CMD_EXEC_S)
 727 #define FW_CMD_EXEC_F           FW_CMD_EXEC_V(1U)
 728
 729 #define FW_CMD_RAMASK_S         20
 730 #define FW_CMD_RAMASK_V(x)      ((x) << FW_CMD_RAMASK_S)
 731
 732 #define FW_CMD_RETVAL_S         8
 733 #define FW_CMD_RETVAL_M         0xff
 734 #define FW_CMD_RETVAL_V(x)      ((x) << FW_CMD_RETVAL_S)
 735 #define FW_CMD_RETVAL_G(x)      (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M)
 736
 737 #define FW_CMD_LEN16_S          0
 738 #define FW_CMD_LEN16_V(x)       ((x) << FW_CMD_LEN16_S)
 739
 740 #define FW_LEN16(fw_struct)     FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
 741
 742 enum fw_ldst_addrspc {
 743         FW_LDST_ADDRSPC_FIRMWARE  = 0x0001,
 744         FW_LDST_ADDRSPC_SGE_EGRC  = 0x0008,
 745         FW_LDST_ADDRSPC_SGE_INGC  = 0x0009,
 746         FW_LDST_ADDRSPC_SGE_FLMC  = 0x000a,
 747         FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
 748         FW_LDST_ADDRSPC_TP_PIO    = 0x0010,
 749         FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
 750         FW_LDST_ADDRSPC_TP_MIB    = 0x0012,
 751         FW_LDST_ADDRSPC_MDIO      = 0x0018,
 752         FW_LDST_ADDRSPC_MPS       = 0x0020,
 753         FW_LDST_ADDRSPC_FUNC      = 0x0028,
 754         FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
 755 };
 756
 757 enum fw_ldst_mps_fid {
 758         FW_LDST_MPS_ATRB,
 759         FW_LDST_MPS_RPLC
 760 };
 761
 762 enum fw_ldst_func_access_ctl {
 763         FW_LDST_FUNC_ACC_CTL_VIID,
 764         FW_LDST_FUNC_ACC_CTL_FID
 765 };
 766
 767 enum fw_ldst_func_mod_index {
 768         FW_LDST_FUNC_MPS
 769 };
 770
 771 struct fw_ldst_cmd {
 772         __be32 op_to_addrspace;
 773         __be32 cycles_to_len16;
 774         union fw_ldst {
 775                 struct fw_ldst_addrval {
 776                         __be32 addr;
 777                         __be32 val;
 778                 } addrval;
 779                 struct fw_ldst_idctxt {
 780                         __be32 physid;
 781                         __be32 msg_ctxtflush;
 782                         __be32 ctxt_data7;
 783                         __be32 ctxt_data6;
 784                         __be32 ctxt_data5;
 785                         __be32 ctxt_data4;
 786                         __be32 ctxt_data3;
 787                         __be32 ctxt_data2;
 788                         __be32 ctxt_data1;
 789                         __be32 ctxt_data0;
 790                 } idctxt;
 791                 struct fw_ldst_mdio {
 792                         __be16 paddr_mmd;
 793                         __be16 raddr;
 794                         __be16 vctl;
 795                         __be16 rval;
 796                 } mdio;
 797                 struct fw_ldst_cim_rq {
 798                         u8 req_first64[8];
 799                         u8 req_second64[8];
 800                         u8 resp_first64[8];
 801                         u8 resp_second64[8];
 802                         __be32 r3[2];
 803                 } cim_rq;
 804                 union fw_ldst_mps {
 805                         struct fw_ldst_mps_rplc {
 806                                 __be16 fid_idx;
 807                                 __be16 rplcpf_pkd;
 808                                 __be32 rplc255_224;
 809                                 __be32 rplc223_192;
 810                                 __be32 rplc191_160;
 811                                 __be32 rplc159_128;
 812                                 __be32 rplc127_96;
 813                                 __be32 rplc95_64;
 814                                 __be32 rplc63_32;
 815                                 __be32 rplc31_0;
 816                         } rplc;
 817                         struct fw_ldst_mps_atrb {
 818                                 __be16 fid_mpsid;
 819                                 __be16 r2[3];
 820                                 __be32 r3[2];
 821                                 __be32 r4;
 822                                 __be32 atrb;
 823                                 __be16 vlan[16];
 824                         } atrb;
 825                 } mps;
 826                 struct fw_ldst_func {
 827                         u8 access_ctl;
 828                         u8 mod_index;
 829                         __be16 ctl_id;
 830                         __be32 offset;
 831                         __be64 data0;
 832                         __be64 data1;
 833                 } func;
 834                 struct fw_ldst_pcie {
 835                         u8 ctrl_to_fn;
 836                         u8 bnum;
 837                         u8 r;
 838                         u8 ext_r;
 839                         u8 select_naccess;
 840                         u8 pcie_fn;
 841                         __be16 nset_pkd;
 842                         __be32 data[12];
 843                 } pcie;
 844                 struct fw_ldst_i2c_deprecated {
 845                         u8 pid_pkd;
 846                         u8 base;
 847                         u8 boffset;
 848                         u8 data;
 849                         __be32 r9;
 850                 } i2c_deprecated;
 851                 struct fw_ldst_i2c {
 852                         u8 pid;
 853                         u8 did;
 854                         u8 boffset;
 855                         u8 blen;
 856                         __be32 r9;
 857                         __u8   data[48];
 858                 } i2c;
 859                 struct fw_ldst_le {
 860                         __be32 index;
 861                         __be32 r9;
 862                         u8 val[33];
 863                         u8 r11[7];
 864                 } le;
 865         } u;
 866 };
 867
 868 #define FW_LDST_CMD_ADDRSPACE_S         0
 869 #define FW_LDST_CMD_ADDRSPACE_V(x)      ((x) << FW_LDST_CMD_ADDRSPACE_S)
 870
 871 #define FW_LDST_CMD_MSG_S       31
 872 #define FW_LDST_CMD_MSG_V(x)    ((x) << FW_LDST_CMD_MSG_S)
 873
 874 #define FW_LDST_CMD_CTXTFLUSH_S         30
 875 #define FW_LDST_CMD_CTXTFLUSH_V(x)      ((x) << FW_LDST_CMD_CTXTFLUSH_S)
 876 #define FW_LDST_CMD_CTXTFLUSH_F         FW_LDST_CMD_CTXTFLUSH_V(1U)
 877
 878 #define FW_LDST_CMD_PADDR_S     8
 879 #define FW_LDST_CMD_PADDR_V(x)  ((x) << FW_LDST_CMD_PADDR_S)
 880
 881 #define FW_LDST_CMD_MMD_S       0
 882 #define FW_LDST_CMD_MMD_V(x)    ((x) << FW_LDST_CMD_MMD_S)
 883
 884 #define FW_LDST_CMD_FID_S       15
 885 #define FW_LDST_CMD_FID_V(x)    ((x) << FW_LDST_CMD_FID_S)
 886
 887 #define FW_LDST_CMD_IDX_S       0
 888 #define FW_LDST_CMD_IDX_V(x)    ((x) << FW_LDST_CMD_IDX_S)
 889
 890 #define FW_LDST_CMD_RPLCPF_S    0
 891 #define FW_LDST_CMD_RPLCPF_V(x) ((x) << FW_LDST_CMD_RPLCPF_S)
 892
 893 #define FW_LDST_CMD_LC_S        4
 894 #define FW_LDST_CMD_LC_V(x)     ((x) << FW_LDST_CMD_LC_S)
 895 #define FW_LDST_CMD_LC_F        FW_LDST_CMD_LC_V(1U)
 896
 897 #define FW_LDST_CMD_FN_S        0
 898 #define FW_LDST_CMD_FN_V(x)     ((x) << FW_LDST_CMD_FN_S)
 899
 900 #define FW_LDST_CMD_NACCESS_S           0
 901 #define FW_LDST_CMD_NACCESS_V(x)        ((x) << FW_LDST_CMD_NACCESS_S)
 902
 903 struct fw_reset_cmd {
 904         __be32 op_to_write;
 905         __be32 retval_len16;
 906         __be32 val;
 907         __be32 halt_pkd;
 908 };
 909
 910 #define FW_RESET_CMD_HALT_S     31
 911 #define FW_RESET_CMD_HALT_M     0x1
 912 #define FW_RESET_CMD_HALT_V(x)  ((x) << FW_RESET_CMD_HALT_S)
 913 #define FW_RESET_CMD_HALT_G(x)  \
 914         (((x) >> FW_RESET_CMD_HALT_S) & FW_RESET_CMD_HALT_M)
 915 #define FW_RESET_CMD_HALT_F     FW_RESET_CMD_HALT_V(1U)
 916
 917 enum fw_hellow_cmd {
 918         fw_hello_cmd_stage_os           = 0x0
 919 };
 920
 921 struct fw_hello_cmd {
 922         __be32 op_to_write;
 923         __be32 retval_len16;
 924         __be32 err_to_clearinit;
 925         __be32 fwrev;
 926 };
 927
 928 #define FW_HELLO_CMD_ERR_S      31
 929 #define FW_HELLO_CMD_ERR_V(x)   ((x) << FW_HELLO_CMD_ERR_S)
 930 #define FW_HELLO_CMD_ERR_F      FW_HELLO_CMD_ERR_V(1U)
 931
 932 #define FW_HELLO_CMD_INIT_S     30
 933 #define FW_HELLO_CMD_INIT_V(x)  ((x) << FW_HELLO_CMD_INIT_S)
 934 #define FW_HELLO_CMD_INIT_F     FW_HELLO_CMD_INIT_V(1U)
 935
 936 #define FW_HELLO_CMD_MASTERDIS_S        29
 937 #define FW_HELLO_CMD_MASTERDIS_V(x)     ((x) << FW_HELLO_CMD_MASTERDIS_S)
 938
 939 #define FW_HELLO_CMD_MASTERFORCE_S      28
 940 #define FW_HELLO_CMD_MASTERFORCE_V(x)   ((x) << FW_HELLO_CMD_MASTERFORCE_S)
 941
 942 #define FW_HELLO_CMD_MBMASTER_S         24
 943 #define FW_HELLO_CMD_MBMASTER_M         0xfU
 944 #define FW_HELLO_CMD_MBMASTER_V(x)      ((x) << FW_HELLO_CMD_MBMASTER_S)
 945 #define FW_HELLO_CMD_MBMASTER_G(x)      \
 946         (((x) >> FW_HELLO_CMD_MBMASTER_S) & FW_HELLO_CMD_MBMASTER_M)
 947
 948 #define FW_HELLO_CMD_MBASYNCNOTINT_S    23
 949 #define FW_HELLO_CMD_MBASYNCNOTINT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOTINT_S)
 950
 951 #define FW_HELLO_CMD_MBASYNCNOT_S       20
 952 #define FW_HELLO_CMD_MBASYNCNOT_V(x)    ((x) << FW_HELLO_CMD_MBASYNCNOT_S)
 953
 954 #define FW_HELLO_CMD_STAGE_S            17
 955 #define FW_HELLO_CMD_STAGE_V(x)         ((x) << FW_HELLO_CMD_STAGE_S)
 956
 957 #define FW_HELLO_CMD_CLEARINIT_S        16
 958 #define FW_HELLO_CMD_CLEARINIT_V(x)     ((x) << FW_HELLO_CMD_CLEARINIT_S)
 959 #define FW_HELLO_CMD_CLEARINIT_F        FW_HELLO_CMD_CLEARINIT_V(1U)
 960
 961 struct fw_bye_cmd {
 962         __be32 op_to_write;
 963         __be32 retval_len16;
 964         __be64 r3;
 965 };
 966
 967 struct fw_initialize_cmd {
 968         __be32 op_to_write;
 969         __be32 retval_len16;
 970         __be64 r3;
 971 };
 972
 973 enum fw_caps_config_hm {
 974         FW_CAPS_CONFIG_HM_PCIE          = 0x00000001,
 975         FW_CAPS_CONFIG_HM_PL            = 0x00000002,
 976         FW_CAPS_CONFIG_HM_SGE           = 0x00000004,
 977         FW_CAPS_CONFIG_HM_CIM           = 0x00000008,
 978         FW_CAPS_CONFIG_HM_ULPTX         = 0x00000010,
 979         FW_CAPS_CONFIG_HM_TP            = 0x00000020,
 980         FW_CAPS_CONFIG_HM_ULPRX         = 0x00000040,
 981         FW_CAPS_CONFIG_HM_PMRX          = 0x00000080,
 982         FW_CAPS_CONFIG_HM_PMTX          = 0x00000100,
 983         FW_CAPS_CONFIG_HM_MC            = 0x00000200,
 984         FW_CAPS_CONFIG_HM_LE            = 0x00000400,
 985         FW_CAPS_CONFIG_HM_MPS           = 0x00000800,
 986         FW_CAPS_CONFIG_HM_XGMAC         = 0x00001000,
 987         FW_CAPS_CONFIG_HM_CPLSWITCH     = 0x00002000,
 988         FW_CAPS_CONFIG_HM_T4DBG         = 0x00004000,
 989         FW_CAPS_CONFIG_HM_MI            = 0x00008000,
 990         FW_CAPS_CONFIG_HM_I2CM          = 0x00010000,
 991         FW_CAPS_CONFIG_HM_NCSI          = 0x00020000,
 992         FW_CAPS_CONFIG_HM_SMB           = 0x00040000,
 993         FW_CAPS_CONFIG_HM_MA            = 0x00080000,
 994         FW_CAPS_CONFIG_HM_EDRAM         = 0x00100000,
 995         FW_CAPS_CONFIG_HM_PMU           = 0x00200000,
 996         FW_CAPS_CONFIG_HM_UART          = 0x00400000,
 997         FW_CAPS_CONFIG_HM_SF            = 0x00800000,
 998 };
 999
1000 enum fw_caps_config_nbm {
1001         FW_CAPS_CONFIG_NBM_IPMI         = 0x00000001,
1002         FW_CAPS_CONFIG_NBM_NCSI         = 0x00000002,
1003 };
1004
1005 enum fw_caps_config_link {
1006         FW_CAPS_CONFIG_LINK_PPP         = 0x00000001,
1007         FW_CAPS_CONFIG_LINK_QFC         = 0x00000002,
1008         FW_CAPS_CONFIG_LINK_DCBX        = 0x00000004,
1009 };
1010
1011 enum fw_caps_config_switch {
1012         FW_CAPS_CONFIG_SWITCH_INGRESS   = 0x00000001,
1013         FW_CAPS_CONFIG_SWITCH_EGRESS    = 0x00000002,
1014 };
1015
1016 enum fw_caps_config_nic {
1017         FW_CAPS_CONFIG_NIC              = 0x00000001,
1018         FW_CAPS_CONFIG_NIC_VM           = 0x00000002,
1019 };
1020
1021 enum fw_caps_config_ofld {
1022         FW_CAPS_CONFIG_OFLD             = 0x00000001,
1023 };
1024
1025 enum fw_caps_config_rdma {
1026         FW_CAPS_CONFIG_RDMA_RDDP        = 0x00000001,
1027         FW_CAPS_CONFIG_RDMA_RDMAC       = 0x00000002,
1028 };
1029
1030 enum fw_caps_config_iscsi {
1031         FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
1032         FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
1033         FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
1034         FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
1035 };
1036
1037 enum fw_caps_config_fcoe {
1038         FW_CAPS_CONFIG_FCOE_INITIATOR   = 0x00000001,
1039         FW_CAPS_CONFIG_FCOE_TARGET      = 0x00000002,
1040         FW_CAPS_CONFIG_FCOE_CTRL_OFLD   = 0x00000004,
1041 };
1042
1043 enum fw_memtype_cf {
1044         FW_MEMTYPE_CF_EDC0              = 0x0,
1045         FW_MEMTYPE_CF_EDC1              = 0x1,
1046         FW_MEMTYPE_CF_EXTMEM            = 0x2,
1047         FW_MEMTYPE_CF_FLASH             = 0x4,
1048         FW_MEMTYPE_CF_INTERNAL          = 0x5,
1049         FW_MEMTYPE_CF_EXTMEM1           = 0x6,
1050 };
1051
1052 struct fw_caps_config_cmd {
1053         __be32 op_to_write;
1054         __be32 cfvalid_to_len16;
1055         __be32 r2;
1056         __be32 hwmbitmap;
1057         __be16 nbmcaps;
1058         __be16 linkcaps;
1059         __be16 switchcaps;
1060         __be16 r3;
1061         __be16 niccaps;
1062         __be16 ofldcaps;
1063         __be16 rdmacaps;
1064         __be16 cryptocaps;
1065         __be16 iscsicaps;
1066         __be16 fcoecaps;
1067         __be32 cfcsum;
1068         __be32 finiver;
1069         __be32 finicsum;
1070 };
1071
1072 #define FW_CAPS_CONFIG_CMD_CFVALID_S    27
1073 #define FW_CAPS_CONFIG_CMD_CFVALID_V(x) ((x) << FW_CAPS_CONFIG_CMD_CFVALID_S)
1074 #define FW_CAPS_CONFIG_CMD_CFVALID_F    FW_CAPS_CONFIG_CMD_CFVALID_V(1U)
1075
1076 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S         24
1077 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(x)      \
1078         ((x) << FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S)
1079
1080 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S      16
1081 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(x)   \
1082         ((x) << FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S)
1083
1084 /*
1085  * params command mnemonics
1086  */
1087 enum fw_params_mnem {
1088         FW_PARAMS_MNEM_DEV              = 1,    /* device params */
1089         FW_PARAMS_MNEM_PFVF             = 2,    /* function params */
1090         FW_PARAMS_MNEM_REG              = 3,    /* limited register access */
1091         FW_PARAMS_MNEM_DMAQ             = 4,    /* dma queue params */
1092         FW_PARAMS_MNEM_CHNET            = 5,    /* chnet params */
1093         FW_PARAMS_MNEM_LAST
1094 };
1095
1096 /*
1097  * device parameters
1098  */
1099 enum fw_params_param_dev {
1100         FW_PARAMS_PARAM_DEV_CCLK        = 0x00, /* chip core clock in khz */
1101         FW_PARAMS_PARAM_DEV_PORTVEC     = 0x01, /* the port vector */
1102         FW_PARAMS_PARAM_DEV_NTID        = 0x02, /* reads the number of TIDs
1103                                                  * allocated by the device's
1104                                                  * Lookup Engine
1105                                                  */
1106         FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
1107         FW_PARAMS_PARAM_DEV_INTVER_NIC  = 0x04,
1108         FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05,
1109         FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06,
1110         FW_PARAMS_PARAM_DEV_INTVER_RI   = 0x07,
1111         FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08,
1112         FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09,
1113         FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A,
1114         FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
1115         FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
1116         FW_PARAMS_PARAM_DEV_CF = 0x0D,
1117         FW_PARAMS_PARAM_DEV_PHYFW = 0x0F,
1118         FW_PARAMS_PARAM_DEV_DIAG = 0x11,
1119         FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD */
1120         FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER = 0x14, /* max supported adap IRD */
1121         FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
1122         FW_PARAMS_PARAM_DEV_FWCACHE = 0x18,
1123 };
1124
1125 /*
1126  * physical and virtual function parameters
1127  */
1128 enum fw_params_param_pfvf {
1129         FW_PARAMS_PARAM_PFVF_RWXCAPS    = 0x00,
1130         FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
1131         FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
1132         FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
1133         FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
1134         FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
1135         FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
1136         FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
1137         FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
1138         FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
1139         FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
1140         FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
1141         FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
1142         FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
1143         FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
1144         FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
1145         FW_PARAMS_PARAM_PFVF_RQ_END     = 0x10,
1146         FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
1147         FW_PARAMS_PARAM_PFVF_PBL_END    = 0x12,
1148         FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
1149         FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
1150         FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
1151         FW_PARAMS_PARAM_PFVF_SQRQ_END   = 0x16,
1152         FW_PARAMS_PARAM_PFVF_CQ_START   = 0x17,
1153         FW_PARAMS_PARAM_PFVF_CQ_END     = 0x18,
1154         FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
1155         FW_PARAMS_PARAM_PFVF_VIID       = 0x24,
1156         FW_PARAMS_PARAM_PFVF_CPMASK     = 0x25,
1157         FW_PARAMS_PARAM_PFVF_OCQ_START  = 0x26,
1158         FW_PARAMS_PARAM_PFVF_OCQ_END    = 0x27,
1159         FW_PARAMS_PARAM_PFVF_CONM_MAP   = 0x28,
1160         FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
1161         FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
1162         FW_PARAMS_PARAM_PFVF_EQ_START   = 0x2B,
1163         FW_PARAMS_PARAM_PFVF_EQ_END     = 0x2C,
1164         FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
1165         FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
1166         FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
1167         FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31
1168 };
1169
1170 /*
1171  * dma queue parameters
1172  */
1173 enum fw_params_param_dmaq {
1174         FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
1175         FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
1176         FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
1177         FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
1178         FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
1179         FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
1180         FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
1181 };
1182
1183 enum fw_params_param_dev_phyfw {
1184         FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00,
1185         FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01,
1186 };
1187
1188 enum fw_params_param_dev_diag {
1189         FW_PARAM_DEV_DIAG_TMP           = 0x00,
1190         FW_PARAM_DEV_DIAG_VDD           = 0x01,
1191 };
1192
1193 enum fw_params_param_dev_fwcache {
1194         FW_PARAM_DEV_FWCACHE_FLUSH      = 0x00,
1195         FW_PARAM_DEV_FWCACHE_FLUSHINV   = 0x01,
1196 };
1197
1198 #define FW_PARAMS_MNEM_S        24
1199 #define FW_PARAMS_MNEM_V(x)     ((x) << FW_PARAMS_MNEM_S)
1200
1201 #define FW_PARAMS_PARAM_X_S     16
1202 #define FW_PARAMS_PARAM_X_V(x)  ((x) << FW_PARAMS_PARAM_X_S)
1203
1204 #define FW_PARAMS_PARAM_Y_S     8
1205 #define FW_PARAMS_PARAM_Y_M     0xffU
1206 #define FW_PARAMS_PARAM_Y_V(x)  ((x) << FW_PARAMS_PARAM_Y_S)
1207 #define FW_PARAMS_PARAM_Y_G(x)  (((x) >> FW_PARAMS_PARAM_Y_S) &\
1208                 FW_PARAMS_PARAM_Y_M)
1209
1210 #define FW_PARAMS_PARAM_Z_S     0
1211 #define FW_PARAMS_PARAM_Z_M     0xffu
1212 #define FW_PARAMS_PARAM_Z_V(x)  ((x) << FW_PARAMS_PARAM_Z_S)
1213 #define FW_PARAMS_PARAM_Z_G(x)  (((x) >> FW_PARAMS_PARAM_Z_S) &\
1214                 FW_PARAMS_PARAM_Z_M)
1215
1216 #define FW_PARAMS_PARAM_XYZ_S           0
1217 #define FW_PARAMS_PARAM_XYZ_V(x)        ((x) << FW_PARAMS_PARAM_XYZ_S)
1218
1219 #define FW_PARAMS_PARAM_YZ_S            0
1220 #define FW_PARAMS_PARAM_YZ_V(x)         ((x) << FW_PARAMS_PARAM_YZ_S)
1221
1222 struct fw_params_cmd {
1223         __be32 op_to_vfn;
1224         __be32 retval_len16;
1225         struct fw_params_param {
1226                 __be32 mnem;
1227                 __be32 val;
1228         } param[7];
1229 };
1230
1231 #define FW_PARAMS_CMD_PFN_S     8
1232 #define FW_PARAMS_CMD_PFN_V(x)  ((x) << FW_PARAMS_CMD_PFN_S)
1233
1234 #define FW_PARAMS_CMD_VFN_S     0
1235 #define FW_PARAMS_CMD_VFN_V(x)  ((x) << FW_PARAMS_CMD_VFN_S)
1236
1237 struct fw_pfvf_cmd {
1238         __be32 op_to_vfn;
1239         __be32 retval_len16;
1240         __be32 niqflint_niq;
1241         __be32 type_to_neq;
1242         __be32 tc_to_nexactf;
1243         __be32 r_caps_to_nethctrl;
1244         __be16 nricq;
1245         __be16 nriqp;
1246         __be32 r4;
1247 };
1248
1249 #define FW_PFVF_CMD_PFN_S       8
1250 #define FW_PFVF_CMD_PFN_V(x)    ((x) << FW_PFVF_CMD_PFN_S)
1251
1252 #define FW_PFVF_CMD_VFN_S       0
1253 #define FW_PFVF_CMD_VFN_V(x)    ((x) << FW_PFVF_CMD_VFN_S)
1254
1255 #define FW_PFVF_CMD_NIQFLINT_S          20
1256 #define FW_PFVF_CMD_NIQFLINT_M          0xfff
1257 #define FW_PFVF_CMD_NIQFLINT_V(x)       ((x) << FW_PFVF_CMD_NIQFLINT_S)
1258 #define FW_PFVF_CMD_NIQFLINT_G(x)       \
1259         (((x) >> FW_PFVF_CMD_NIQFLINT_S) & FW_PFVF_CMD_NIQFLINT_M)
1260
1261 #define FW_PFVF_CMD_NIQ_S       0
1262 #define FW_PFVF_CMD_NIQ_M       0xfffff
1263 #define FW_PFVF_CMD_NIQ_V(x)    ((x) << FW_PFVF_CMD_NIQ_S)
1264 #define FW_PFVF_CMD_NIQ_G(x)    \
1265         (((x) >> FW_PFVF_CMD_NIQ_S) & FW_PFVF_CMD_NIQ_M)
1266
1267 #define FW_PFVF_CMD_TYPE_S      31
1268 #define FW_PFVF_CMD_TYPE_M      0x1
1269 #define FW_PFVF_CMD_TYPE_V(x)   ((x) << FW_PFVF_CMD_TYPE_S)
1270 #define FW_PFVF_CMD_TYPE_G(x)   \
1271         (((x) >> FW_PFVF_CMD_TYPE_S) & FW_PFVF_CMD_TYPE_M)
1272 #define FW_PFVF_CMD_TYPE_F      FW_PFVF_CMD_TYPE_V(1U)
1273
1274 #define FW_PFVF_CMD_CMASK_S     24
1275 #define FW_PFVF_CMD_CMASK_M     0xf
1276 #define FW_PFVF_CMD_CMASK_V(x)  ((x) << FW_PFVF_CMD_CMASK_S)
1277 #define FW_PFVF_CMD_CMASK_G(x)  \
1278         (((x) >> FW_PFVF_CMD_CMASK_S) & FW_PFVF_CMD_CMASK_M)
1279
1280 #define FW_PFVF_CMD_PMASK_S     20
1281 #define FW_PFVF_CMD_PMASK_M     0xf
1282 #define FW_PFVF_CMD_PMASK_V(x)  ((x) << FW_PFVF_CMD_PMASK_S)
1283 #define FW_PFVF_CMD_PMASK_G(x) \
1284         (((x) >> FW_PFVF_CMD_PMASK_S) & FW_PFVF_CMD_PMASK_M)
1285
1286 #define FW_PFVF_CMD_NEQ_S       0
1287 #define FW_PFVF_CMD_NEQ_M       0xfffff
1288 #define FW_PFVF_CMD_NEQ_V(x)    ((x) << FW_PFVF_CMD_NEQ_S)
1289 #define FW_PFVF_CMD_NEQ_G(x)    \
1290         (((x) >> FW_PFVF_CMD_NEQ_S) & FW_PFVF_CMD_NEQ_M)
1291
1292 #define FW_PFVF_CMD_TC_S        24
1293 #define FW_PFVF_CMD_TC_M        0xff
1294 #define FW_PFVF_CMD_TC_V(x)     ((x) << FW_PFVF_CMD_TC_S)
1295 #define FW_PFVF_CMD_TC_G(x)     (((x) >> FW_PFVF_CMD_TC_S) & FW_PFVF_CMD_TC_M)
1296
1297 #define FW_PFVF_CMD_NVI_S       16
1298 #define FW_PFVF_CMD_NVI_M       0xff
1299 #define FW_PFVF_CMD_NVI_V(x)    ((x) << FW_PFVF_CMD_NVI_S)
1300 #define FW_PFVF_CMD_NVI_G(x)    (((x) >> FW_PFVF_CMD_NVI_S) & FW_PFVF_CMD_NVI_M)
1301
1302 #define FW_PFVF_CMD_NEXACTF_S           0
1303 #define FW_PFVF_CMD_NEXACTF_M           0xffff
1304 #define FW_PFVF_CMD_NEXACTF_V(x)        ((x) << FW_PFVF_CMD_NEXACTF_S)
1305 #define FW_PFVF_CMD_NEXACTF_G(x)        \
1306         (((x) >> FW_PFVF_CMD_NEXACTF_S) & FW_PFVF_CMD_NEXACTF_M)
1307
1308 #define FW_PFVF_CMD_R_CAPS_S    24
1309 #define FW_PFVF_CMD_R_CAPS_M    0xff
1310 #define FW_PFVF_CMD_R_CAPS_V(x) ((x) << FW_PFVF_CMD_R_CAPS_S)
1311 #define FW_PFVF_CMD_R_CAPS_G(x) \
1312         (((x) >> FW_PFVF_CMD_R_CAPS_S) & FW_PFVF_CMD_R_CAPS_M)
1313
1314 #define FW_PFVF_CMD_WX_CAPS_S           16
1315 #define FW_PFVF_CMD_WX_CAPS_M           0xff
1316 #define FW_PFVF_CMD_WX_CAPS_V(x)        ((x) << FW_PFVF_CMD_WX_CAPS_S)
1317 #define FW_PFVF_CMD_WX_CAPS_G(x)        \
1318         (((x) >> FW_PFVF_CMD_WX_CAPS_S) & FW_PFVF_CMD_WX_CAPS_M)
1319
1320 #define FW_PFVF_CMD_NETHCTRL_S          0
1321 #define FW_PFVF_CMD_NETHCTRL_M          0xffff
1322 #define FW_PFVF_CMD_NETHCTRL_V(x)       ((x) << FW_PFVF_CMD_NETHCTRL_S)
1323 #define FW_PFVF_CMD_NETHCTRL_G(x)       \
1324         (((x) >> FW_PFVF_CMD_NETHCTRL_S) & FW_PFVF_CMD_NETHCTRL_M)
1325
1326 enum fw_iq_type {
1327         FW_IQ_TYPE_FL_INT_CAP,
1328         FW_IQ_TYPE_NO_FL_INT_CAP
1329 };
1330
1331 struct fw_iq_cmd {
1332         __be32 op_to_vfn;
1333         __be32 alloc_to_len16;
1334         __be16 physiqid;
1335         __be16 iqid;
1336         __be16 fl0id;
1337         __be16 fl1id;
1338         __be32 type_to_iqandstindex;
1339         __be16 iqdroprss_to_iqesize;
1340         __be16 iqsize;
1341         __be64 iqaddr;
1342         __be32 iqns_to_fl0congen;
1343         __be16 fl0dcaen_to_fl0cidxfthresh;
1344         __be16 fl0size;
1345         __be64 fl0addr;
1346         __be32 fl1cngchmap_to_fl1congen;
1347         __be16 fl1dcaen_to_fl1cidxfthresh;
1348         __be16 fl1size;
1349         __be64 fl1addr;
1350 };
1351
1352 #define FW_IQ_CMD_PFN_S         8
1353 #define FW_IQ_CMD_PFN_V(x)      ((x) << FW_IQ_CMD_PFN_S)
1354
1355 #define FW_IQ_CMD_VFN_S         0
1356 #define FW_IQ_CMD_VFN_V(x)      ((x) << FW_IQ_CMD_VFN_S)
1357
1358 #define FW_IQ_CMD_ALLOC_S       31
1359 #define FW_IQ_CMD_ALLOC_V(x)    ((x) << FW_IQ_CMD_ALLOC_S)
1360 #define FW_IQ_CMD_ALLOC_F       FW_IQ_CMD_ALLOC_V(1U)
1361
1362 #define FW_IQ_CMD_FREE_S        30
1363 #define FW_IQ_CMD_FREE_V(x)     ((x) << FW_IQ_CMD_FREE_S)
1364 #define FW_IQ_CMD_FREE_F        FW_IQ_CMD_FREE_V(1U)
1365
1366 #define FW_IQ_CMD_MODIFY_S      29
1367 #define FW_IQ_CMD_MODIFY_V(x)   ((x) << FW_IQ_CMD_MODIFY_S)
1368 #define FW_IQ_CMD_MODIFY_F      FW_IQ_CMD_MODIFY_V(1U)
1369
1370 #define FW_IQ_CMD_IQSTART_S     28
1371 #define FW_IQ_CMD_IQSTART_V(x)  ((x) << FW_IQ_CMD_IQSTART_S)
1372 #define FW_IQ_CMD_IQSTART_F     FW_IQ_CMD_IQSTART_V(1U)
1373
1374 #define FW_IQ_CMD_IQSTOP_S      27
1375 #define FW_IQ_CMD_IQSTOP_V(x)   ((x) << FW_IQ_CMD_IQSTOP_S)
1376 #define FW_IQ_CMD_IQSTOP_F      FW_IQ_CMD_IQSTOP_V(1U)
1377
1378 #define FW_IQ_CMD_TYPE_S        29
1379 #define FW_IQ_CMD_TYPE_V(x)     ((x) << FW_IQ_CMD_TYPE_S)
1380
1381 #define FW_IQ_CMD_IQASYNCH_S    28
1382 #define FW_IQ_CMD_IQASYNCH_V(x) ((x) << FW_IQ_CMD_IQASYNCH_S)
1383
1384 #define FW_IQ_CMD_VIID_S        16
1385 #define FW_IQ_CMD_VIID_V(x)     ((x) << FW_IQ_CMD_VIID_S)
1386
1387 #define FW_IQ_CMD_IQANDST_S     15
1388 #define FW_IQ_CMD_IQANDST_V(x)  ((x) << FW_IQ_CMD_IQANDST_S)
1389
1390 #define FW_IQ_CMD_IQANUS_S      14
1391 #define FW_IQ_CMD_IQANUS_V(x)   ((x) << FW_IQ_CMD_IQANUS_S)
1392
1393 #define FW_IQ_CMD_IQANUD_S      12
1394 #define FW_IQ_CMD_IQANUD_V(x)   ((x) << FW_IQ_CMD_IQANUD_S)
1395
1396 #define FW_IQ_CMD_IQANDSTINDEX_S        0
1397 #define FW_IQ_CMD_IQANDSTINDEX_V(x)     ((x) << FW_IQ_CMD_IQANDSTINDEX_S)
1398
1399 #define FW_IQ_CMD_IQDROPRSS_S           15
1400 #define FW_IQ_CMD_IQDROPRSS_V(x)        ((x) << FW_IQ_CMD_IQDROPRSS_S)
1401 #define FW_IQ_CMD_IQDROPRSS_F   FW_IQ_CMD_IQDROPRSS_V(1U)
1402
1403 #define FW_IQ_CMD_IQGTSMODE_S           14
1404 #define FW_IQ_CMD_IQGTSMODE_V(x)        ((x) << FW_IQ_CMD_IQGTSMODE_S)
1405 #define FW_IQ_CMD_IQGTSMODE_F           FW_IQ_CMD_IQGTSMODE_V(1U)
1406
1407 #define FW_IQ_CMD_IQPCIECH_S    12
1408 #define FW_IQ_CMD_IQPCIECH_V(x) ((x) << FW_IQ_CMD_IQPCIECH_S)
1409
1410 #define FW_IQ_CMD_IQDCAEN_S     11
1411 #define FW_IQ_CMD_IQDCAEN_V(x)  ((x) << FW_IQ_CMD_IQDCAEN_S)
1412
1413 #define FW_IQ_CMD_IQDCACPU_S    6
1414 #define FW_IQ_CMD_IQDCACPU_V(x) ((x) << FW_IQ_CMD_IQDCACPU_S)
1415
1416 #define FW_IQ_CMD_IQINTCNTTHRESH_S      4
1417 #define FW_IQ_CMD_IQINTCNTTHRESH_V(x)   ((x) << FW_IQ_CMD_IQINTCNTTHRESH_S)
1418
1419 #define FW_IQ_CMD_IQO_S         3
1420 #define FW_IQ_CMD_IQO_V(x)      ((x) << FW_IQ_CMD_IQO_S)
1421 #define FW_IQ_CMD_IQO_F         FW_IQ_CMD_IQO_V(1U)
1422
1423 #define FW_IQ_CMD_IQCPRIO_S     2
1424 #define FW_IQ_CMD_IQCPRIO_V(x)  ((x) << FW_IQ_CMD_IQCPRIO_S)
1425
1426 #define FW_IQ_CMD_IQESIZE_S     0
1427 #define FW_IQ_CMD_IQESIZE_V(x)  ((x) << FW_IQ_CMD_IQESIZE_S)
1428
1429 #define FW_IQ_CMD_IQNS_S        31
1430 #define FW_IQ_CMD_IQNS_V(x)     ((x) << FW_IQ_CMD_IQNS_S)
1431
1432 #define FW_IQ_CMD_IQRO_S        30
1433 #define FW_IQ_CMD_IQRO_V(x)     ((x) << FW_IQ_CMD_IQRO_S)
1434
1435 #define FW_IQ_CMD_IQFLINTIQHSEN_S       28
1436 #define FW_IQ_CMD_IQFLINTIQHSEN_V(x)    ((x) << FW_IQ_CMD_IQFLINTIQHSEN_S)
1437
1438 #define FW_IQ_CMD_IQFLINTCONGEN_S       27
1439 #define FW_IQ_CMD_IQFLINTCONGEN_V(x)    ((x) << FW_IQ_CMD_IQFLINTCONGEN_S)
1440 #define FW_IQ_CMD_IQFLINTCONGEN_F       FW_IQ_CMD_IQFLINTCONGEN_V(1U)
1441
1442 #define FW_IQ_CMD_IQFLINTISCSIC_S       26
1443 #define FW_IQ_CMD_IQFLINTISCSIC_V(x)    ((x) << FW_IQ_CMD_IQFLINTISCSIC_S)
1444
1445 #define FW_IQ_CMD_FL0CNGCHMAP_S         20
1446 #define FW_IQ_CMD_FL0CNGCHMAP_V(x)      ((x) << FW_IQ_CMD_FL0CNGCHMAP_S)
1447
1448 #define FW_IQ_CMD_FL0CACHELOCK_S        15
1449 #define FW_IQ_CMD_FL0CACHELOCK_V(x)     ((x) << FW_IQ_CMD_FL0CACHELOCK_S)
1450
1451 #define FW_IQ_CMD_FL0DBP_S      14
1452 #define FW_IQ_CMD_FL0DBP_V(x)   ((x) << FW_IQ_CMD_FL0DBP_S)
1453
1454 #define FW_IQ_CMD_FL0DATANS_S           13
1455 #define FW_IQ_CMD_FL0DATANS_V(x)        ((x) << FW_IQ_CMD_FL0DATANS_S)
1456
1457 #define FW_IQ_CMD_FL0DATARO_S           12
1458 #define FW_IQ_CMD_FL0DATARO_V(x)        ((x) << FW_IQ_CMD_FL0DATARO_S)
1459 #define FW_IQ_CMD_FL0DATARO_F           FW_IQ_CMD_FL0DATARO_V(1U)
1460
1461 #define FW_IQ_CMD_FL0CONGCIF_S          11
1462 #define FW_IQ_CMD_FL0CONGCIF_V(x)       ((x) << FW_IQ_CMD_FL0CONGCIF_S)
1463 #define FW_IQ_CMD_FL0CONGCIF_F          FW_IQ_CMD_FL0CONGCIF_V(1U)
1464
1465 #define FW_IQ_CMD_FL0ONCHIP_S           10
1466 #define FW_IQ_CMD_FL0ONCHIP_V(x)        ((x) << FW_IQ_CMD_FL0ONCHIP_S)
1467
1468 #define FW_IQ_CMD_FL0STATUSPGNS_S       9
1469 #define FW_IQ_CMD_FL0STATUSPGNS_V(x)    ((x) << FW_IQ_CMD_FL0STATUSPGNS_S)
1470
1471 #define FW_IQ_CMD_FL0STATUSPGRO_S       8
1472 #define FW_IQ_CMD_FL0STATUSPGRO_V(x)    ((x) << FW_IQ_CMD_FL0STATUSPGRO_S)
1473
1474 #define FW_IQ_CMD_FL0FETCHNS_S          7
1475 #define FW_IQ_CMD_FL0FETCHNS_V(x)       ((x) << FW_IQ_CMD_FL0FETCHNS_S)
1476
1477 #define FW_IQ_CMD_FL0FETCHRO_S          6
1478 #define FW_IQ_CMD_FL0FETCHRO_V(x)       ((x) << FW_IQ_CMD_FL0FETCHRO_S)
1479 #define FW_IQ_CMD_FL0FETCHRO_F          FW_IQ_CMD_FL0FETCHRO_V(1U)
1480
1481 #define FW_IQ_CMD_FL0HOSTFCMODE_S       4
1482 #define FW_IQ_CMD_FL0HOSTFCMODE_V(x)    ((x) << FW_IQ_CMD_FL0HOSTFCMODE_S)
1483
1484 #define FW_IQ_CMD_FL0CPRIO_S    3
1485 #define FW_IQ_CMD_FL0CPRIO_V(x) ((x) << FW_IQ_CMD_FL0CPRIO_S)
1486
1487 #define FW_IQ_CMD_FL0PADEN_S    2
1488 #define FW_IQ_CMD_FL0PADEN_V(x) ((x) << FW_IQ_CMD_FL0PADEN_S)
1489 #define FW_IQ_CMD_FL0PADEN_F    FW_IQ_CMD_FL0PADEN_V(1U)
1490
1491 #define FW_IQ_CMD_FL0PACKEN_S           1
1492 #define FW_IQ_CMD_FL0PACKEN_V(x)        ((x) << FW_IQ_CMD_FL0PACKEN_S)
1493 #define FW_IQ_CMD_FL0PACKEN_F           FW_IQ_CMD_FL0PACKEN_V(1U)
1494
1495 #define FW_IQ_CMD_FL0CONGEN_S           0
1496 #define FW_IQ_CMD_FL0CONGEN_V(x)        ((x) << FW_IQ_CMD_FL0CONGEN_S)
1497 #define FW_IQ_CMD_FL0CONGEN_F           FW_IQ_CMD_FL0CONGEN_V(1U)
1498
1499 #define FW_IQ_CMD_FL0DCAEN_S    15
1500 #define FW_IQ_CMD_FL0DCAEN_V(x) ((x) << FW_IQ_CMD_FL0DCAEN_S)
1501
1502 #define FW_IQ_CMD_FL0DCACPU_S           10
1503 #define FW_IQ_CMD_FL0DCACPU_V(x)        ((x) << FW_IQ_CMD_FL0DCACPU_S)
1504
1505 #define FW_IQ_CMD_FL0FBMIN_S    7
1506 #define FW_IQ_CMD_FL0FBMIN_V(x) ((x) << FW_IQ_CMD_FL0FBMIN_S)
1507
1508 #define FW_IQ_CMD_FL0FBMAX_S    4
1509 #define FW_IQ_CMD_FL0FBMAX_V(x) ((x) << FW_IQ_CMD_FL0FBMAX_S)
1510
1511 #define FW_IQ_CMD_FL0CIDXFTHRESHO_S     3
1512 #define FW_IQ_CMD_FL0CIDXFTHRESHO_V(x)  ((x) << FW_IQ_CMD_FL0CIDXFTHRESHO_S)
1513 #define FW_IQ_CMD_FL0CIDXFTHRESHO_F     FW_IQ_CMD_FL0CIDXFTHRESHO_V(1U)
1514
1515 #define FW_IQ_CMD_FL0CIDXFTHRESH_S      0
1516 #define FW_IQ_CMD_FL0CIDXFTHRESH_V(x)   ((x) << FW_IQ_CMD_FL0CIDXFTHRESH_S)
1517
1518 #define FW_IQ_CMD_FL1CNGCHMAP_S         20
1519 #define FW_IQ_CMD_FL1CNGCHMAP_V(x)      ((x) << FW_IQ_CMD_FL1CNGCHMAP_S)
1520
1521 #define FW_IQ_CMD_FL1CACHELOCK_S        15
1522 #define FW_IQ_CMD_FL1CACHELOCK_V(x)     ((x) << FW_IQ_CMD_FL1CACHELOCK_S)
1523
1524 #define FW_IQ_CMD_FL1DBP_S      14
1525 #define FW_IQ_CMD_FL1DBP_V(x)   ((x) << FW_IQ_CMD_FL1DBP_S)
1526
1527 #define FW_IQ_CMD_FL1DATANS_S           13
1528 #define FW_IQ_CMD_FL1DATANS_V(x)        ((x) << FW_IQ_CMD_FL1DATANS_S)
1529
1530 #define FW_IQ_CMD_FL1DATARO_S           12
1531 #define FW_IQ_CMD_FL1DATARO_V(x)        ((x) << FW_IQ_CMD_FL1DATARO_S)
1532
1533 #define FW_IQ_CMD_FL1CONGCIF_S          11
1534 #define FW_IQ_CMD_FL1CONGCIF_V(x)       ((x) << FW_IQ_CMD_FL1CONGCIF_S)
1535
1536 #define FW_IQ_CMD_FL1ONCHIP_S           10
1537 #define FW_IQ_CMD_FL1ONCHIP_V(x)        ((x) << FW_IQ_CMD_FL1ONCHIP_S)
1538
1539 #define FW_IQ_CMD_FL1STATUSPGNS_S       9
1540 #define FW_IQ_CMD_FL1STATUSPGNS_V(x)    ((x) << FW_IQ_CMD_FL1STATUSPGNS_S)
1541
1542 #define FW_IQ_CMD_FL1STATUSPGRO_S       8
1543 #define FW_IQ_CMD_FL1STATUSPGRO_V(x)    ((x) << FW_IQ_CMD_FL1STATUSPGRO_S)
1544
1545 #define FW_IQ_CMD_FL1FETCHNS_S          7
1546 #define FW_IQ_CMD_FL1FETCHNS_V(x)       ((x) << FW_IQ_CMD_FL1FETCHNS_S)
1547
1548 #define FW_IQ_CMD_FL1FETCHRO_S          6
1549 #define FW_IQ_CMD_FL1FETCHRO_V(x)       ((x) << FW_IQ_CMD_FL1FETCHRO_S)
1550
1551 #define FW_IQ_CMD_FL1HOSTFCMODE_S       4
1552 #define FW_IQ_CMD_FL1HOSTFCMODE_V(x)    ((x) << FW_IQ_CMD_FL1HOSTFCMODE_S)
1553
1554 #define FW_IQ_CMD_FL1CPRIO_S    3
1555 #define FW_IQ_CMD_FL1CPRIO_V(x) ((x) << FW_IQ_CMD_FL1CPRIO_S)
1556
1557 #define FW_IQ_CMD_FL1PADEN_S    2
1558 #define FW_IQ_CMD_FL1PADEN_V(x) ((x) << FW_IQ_CMD_FL1PADEN_S)
1559 #define FW_IQ_CMD_FL1PADEN_F    FW_IQ_CMD_FL1PADEN_V(1U)
1560
1561 #define FW_IQ_CMD_FL1PACKEN_S           1
1562 #define FW_IQ_CMD_FL1PACKEN_V(x)        ((x) << FW_IQ_CMD_FL1PACKEN_S)
1563 #define FW_IQ_CMD_FL1PACKEN_F   FW_IQ_CMD_FL1PACKEN_V(1U)
1564
1565 #define FW_IQ_CMD_FL1CONGEN_S           0
1566 #define FW_IQ_CMD_FL1CONGEN_V(x)        ((x) << FW_IQ_CMD_FL1CONGEN_S)
1567 #define FW_IQ_CMD_FL1CONGEN_F   FW_IQ_CMD_FL1CONGEN_V(1U)
1568
1569 #define FW_IQ_CMD_FL1DCAEN_S    15
1570 #define FW_IQ_CMD_FL1DCAEN_V(x) ((x) << FW_IQ_CMD_FL1DCAEN_S)
1571
1572 #define FW_IQ_CMD_FL1DCACPU_S           10
1573 #define FW_IQ_CMD_FL1DCACPU_V(x)        ((x) << FW_IQ_CMD_FL1DCACPU_S)
1574
1575 #define FW_IQ_CMD_FL1FBMIN_S    7
1576 #define FW_IQ_CMD_FL1FBMIN_V(x) ((x) << FW_IQ_CMD_FL1FBMIN_S)
1577
1578 #define FW_IQ_CMD_FL1FBMAX_S    4
1579 #define FW_IQ_CMD_FL1FBMAX_V(x) ((x) << FW_IQ_CMD_FL1FBMAX_S)
1580
1581 #define FW_IQ_CMD_FL1CIDXFTHRESHO_S     3
1582 #define FW_IQ_CMD_FL1CIDXFTHRESHO_V(x)  ((x) << FW_IQ_CMD_FL1CIDXFTHRESHO_S)
1583 #define FW_IQ_CMD_FL1CIDXFTHRESHO_F     FW_IQ_CMD_FL1CIDXFTHRESHO_V(1U)
1584
1585 #define FW_IQ_CMD_FL1CIDXFTHRESH_S      0
1586 #define FW_IQ_CMD_FL1CIDXFTHRESH_V(x)   ((x) << FW_IQ_CMD_FL1CIDXFTHRESH_S)
1587
1588 struct fw_eq_eth_cmd {
1589         __be32 op_to_vfn;
1590         __be32 alloc_to_len16;
1591         __be32 eqid_pkd;
1592         __be32 physeqid_pkd;
1593         __be32 fetchszm_to_iqid;
1594         __be32 dcaen_to_eqsize;
1595         __be64 eqaddr;
1596         __be32 viid_pkd;
1597         __be32 r8_lo;
1598         __be64 r9;
1599 };
1600
1601 #define FW_EQ_ETH_CMD_PFN_S     8
1602 #define FW_EQ_ETH_CMD_PFN_V(x)  ((x) << FW_EQ_ETH_CMD_PFN_S)
1603
1604 #define FW_EQ_ETH_CMD_VFN_S     0
1605 #define FW_EQ_ETH_CMD_VFN_V(x)  ((x) << FW_EQ_ETH_CMD_VFN_S)
1606
1607 #define FW_EQ_ETH_CMD_ALLOC_S           31
1608 #define FW_EQ_ETH_CMD_ALLOC_V(x)        ((x) << FW_EQ_ETH_CMD_ALLOC_S)
1609 #define FW_EQ_ETH_CMD_ALLOC_F   FW_EQ_ETH_CMD_ALLOC_V(1U)
1610
1611 #define FW_EQ_ETH_CMD_FREE_S    30
1612 #define FW_EQ_ETH_CMD_FREE_V(x) ((x) << FW_EQ_ETH_CMD_FREE_S)
1613 #define FW_EQ_ETH_CMD_FREE_F    FW_EQ_ETH_CMD_FREE_V(1U)
1614
1615 #define FW_EQ_ETH_CMD_MODIFY_S          29
1616 #define FW_EQ_ETH_CMD_MODIFY_V(x)       ((x) << FW_EQ_ETH_CMD_MODIFY_S)
1617 #define FW_EQ_ETH_CMD_MODIFY_F  FW_EQ_ETH_CMD_MODIFY_V(1U)
1618
1619 #define FW_EQ_ETH_CMD_EQSTART_S         28
1620 #define FW_EQ_ETH_CMD_EQSTART_V(x)      ((x) << FW_EQ_ETH_CMD_EQSTART_S)
1621 #define FW_EQ_ETH_CMD_EQSTART_F FW_EQ_ETH_CMD_EQSTART_V(1U)
1622
1623 #define FW_EQ_ETH_CMD_EQSTOP_S          27
1624 #define FW_EQ_ETH_CMD_EQSTOP_V(x)       ((x) << FW_EQ_ETH_CMD_EQSTOP_S)
1625 #define FW_EQ_ETH_CMD_EQSTOP_F  FW_EQ_ETH_CMD_EQSTOP_V(1U)
1626
1627 #define FW_EQ_ETH_CMD_EQID_S    0
1628 #define FW_EQ_ETH_CMD_EQID_M    0xfffff
1629 #define FW_EQ_ETH_CMD_EQID_V(x) ((x) << FW_EQ_ETH_CMD_EQID_S)
1630 #define FW_EQ_ETH_CMD_EQID_G(x) \
1631         (((x) >> FW_EQ_ETH_CMD_EQID_S) & FW_EQ_ETH_CMD_EQID_M)
1632
1633 #define FW_EQ_ETH_CMD_PHYSEQID_S        0
1634 #define FW_EQ_ETH_CMD_PHYSEQID_M        0xfffff
1635 #define FW_EQ_ETH_CMD_PHYSEQID_V(x)     ((x) << FW_EQ_ETH_CMD_PHYSEQID_S)
1636 #define FW_EQ_ETH_CMD_PHYSEQID_G(x)     \
1637         (((x) >> FW_EQ_ETH_CMD_PHYSEQID_S) & FW_EQ_ETH_CMD_PHYSEQID_M)
1638
1639 #define FW_EQ_ETH_CMD_FETCHSZM_S        26
1640 #define FW_EQ_ETH_CMD_FETCHSZM_V(x)     ((x) << FW_EQ_ETH_CMD_FETCHSZM_S)
1641 #define FW_EQ_ETH_CMD_FETCHSZM_F        FW_EQ_ETH_CMD_FETCHSZM_V(1U)
1642
1643 #define FW_EQ_ETH_CMD_STATUSPGNS_S      25
1644 #define FW_EQ_ETH_CMD_STATUSPGNS_V(x)   ((x) << FW_EQ_ETH_CMD_STATUSPGNS_S)
1645
1646 #define FW_EQ_ETH_CMD_STATUSPGRO_S      24
1647 #define FW_EQ_ETH_CMD_STATUSPGRO_V(x)   ((x) << FW_EQ_ETH_CMD_STATUSPGRO_S)
1648
1649 #define FW_EQ_ETH_CMD_FETCHNS_S         23
1650 #define FW_EQ_ETH_CMD_FETCHNS_V(x)      ((x) << FW_EQ_ETH_CMD_FETCHNS_S)
1651
1652 #define FW_EQ_ETH_CMD_FETCHRO_S         22
1653 #define FW_EQ_ETH_CMD_FETCHRO_V(x)      ((x) << FW_EQ_ETH_CMD_FETCHRO_S)
1654 #define FW_EQ_ETH_CMD_FETCHRO_F         FW_EQ_ETH_CMD_FETCHRO_V(1U)
1655
1656 #define FW_EQ_ETH_CMD_HOSTFCMODE_S      20
1657 #define FW_EQ_ETH_CMD_HOSTFCMODE_V(x)   ((x) << FW_EQ_ETH_CMD_HOSTFCMODE_S)
1658
1659 #define FW_EQ_ETH_CMD_CPRIO_S           19
1660 #define FW_EQ_ETH_CMD_CPRIO_V(x)        ((x) << FW_EQ_ETH_CMD_CPRIO_S)
1661
1662 #define FW_EQ_ETH_CMD_ONCHIP_S          18
1663 #define FW_EQ_ETH_CMD_ONCHIP_V(x)       ((x) << FW_EQ_ETH_CMD_ONCHIP_S)
1664
1665 #define FW_EQ_ETH_CMD_PCIECHN_S         16
1666 #define FW_EQ_ETH_CMD_PCIECHN_V(x)      ((x) << FW_EQ_ETH_CMD_PCIECHN_S)
1667
1668 #define FW_EQ_ETH_CMD_IQID_S    0
1669 #define FW_EQ_ETH_CMD_IQID_V(x) ((x) << FW_EQ_ETH_CMD_IQID_S)
1670
1671 #define FW_EQ_ETH_CMD_DCAEN_S           31
1672 #define FW_EQ_ETH_CMD_DCAEN_V(x)        ((x) << FW_EQ_ETH_CMD_DCAEN_S)
1673
1674 #define FW_EQ_ETH_CMD_DCACPU_S          26
1675 #define FW_EQ_ETH_CMD_DCACPU_V(x)       ((x) << FW_EQ_ETH_CMD_DCACPU_S)
1676
1677 #define FW_EQ_ETH_CMD_FBMIN_S           23
1678 #define FW_EQ_ETH_CMD_FBMIN_V(x)        ((x) << FW_EQ_ETH_CMD_FBMIN_S)
1679
1680 #define FW_EQ_ETH_CMD_FBMAX_S           20
1681 #define FW_EQ_ETH_CMD_FBMAX_V(x)        ((x) << FW_EQ_ETH_CMD_FBMAX_S)
1682
1683 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_S    19
1684 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESHO_S)
1685
1686 #define FW_EQ_ETH_CMD_CIDXFTHRESH_S     16
1687 #define FW_EQ_ETH_CMD_CIDXFTHRESH_V(x)  ((x) << FW_EQ_ETH_CMD_CIDXFTHRESH_S)
1688
1689 #define FW_EQ_ETH_CMD_EQSIZE_S          0
1690 #define FW_EQ_ETH_CMD_EQSIZE_V(x)       ((x) << FW_EQ_ETH_CMD_EQSIZE_S)
1691
1692 #define FW_EQ_ETH_CMD_AUTOEQUEQE_S      30
1693 #define FW_EQ_ETH_CMD_AUTOEQUEQE_V(x)   ((x) << FW_EQ_ETH_CMD_AUTOEQUEQE_S)
1694 #define FW_EQ_ETH_CMD_AUTOEQUEQE_F      FW_EQ_ETH_CMD_AUTOEQUEQE_V(1U)
1695
1696 #define FW_EQ_ETH_CMD_VIID_S    16
1697 #define FW_EQ_ETH_CMD_VIID_V(x) ((x) << FW_EQ_ETH_CMD_VIID_S)
1698
1699 struct fw_eq_ctrl_cmd {
1700         __be32 op_to_vfn;
1701         __be32 alloc_to_len16;
1702         __be32 cmpliqid_eqid;
1703         __be32 physeqid_pkd;
1704         __be32 fetchszm_to_iqid;
1705         __be32 dcaen_to_eqsize;
1706         __be64 eqaddr;
1707 };
1708
1709 #define FW_EQ_CTRL_CMD_PFN_S    8
1710 #define FW_EQ_CTRL_CMD_PFN_V(x) ((x) << FW_EQ_CTRL_CMD_PFN_S)
1711
1712 #define FW_EQ_CTRL_CMD_VFN_S    0
1713 #define FW_EQ_CTRL_CMD_VFN_V(x) ((x) << FW_EQ_CTRL_CMD_VFN_S)
1714
1715 #define FW_EQ_CTRL_CMD_ALLOC_S          31
1716 #define FW_EQ_CTRL_CMD_ALLOC_V(x)       ((x) << FW_EQ_CTRL_CMD_ALLOC_S)
1717 #define FW_EQ_CTRL_CMD_ALLOC_F          FW_EQ_CTRL_CMD_ALLOC_V(1U)
1718
1719 #define FW_EQ_CTRL_CMD_FREE_S           30
1720 #define FW_EQ_CTRL_CMD_FREE_V(x)        ((x) << FW_EQ_CTRL_CMD_FREE_S)
1721 #define FW_EQ_CTRL_CMD_FREE_F           FW_EQ_CTRL_CMD_FREE_V(1U)
1722
1723 #define FW_EQ_CTRL_CMD_MODIFY_S         29
1724 #define FW_EQ_CTRL_CMD_MODIFY_V(x)      ((x) << FW_EQ_CTRL_CMD_MODIFY_S)
1725 #define FW_EQ_CTRL_CMD_MODIFY_F         FW_EQ_CTRL_CMD_MODIFY_V(1U)
1726
1727 #define FW_EQ_CTRL_CMD_EQSTART_S        28
1728 #define FW_EQ_CTRL_CMD_EQSTART_V(x)     ((x) << FW_EQ_CTRL_CMD_EQSTART_S)
1729 #define FW_EQ_CTRL_CMD_EQSTART_F        FW_EQ_CTRL_CMD_EQSTART_V(1U)
1730
1731 #define FW_EQ_CTRL_CMD_EQSTOP_S         27
1732 #define FW_EQ_CTRL_CMD_EQSTOP_V(x)      ((x) << FW_EQ_CTRL_CMD_EQSTOP_S)
1733 #define FW_EQ_CTRL_CMD_EQSTOP_F         FW_EQ_CTRL_CMD_EQSTOP_V(1U)
1734
1735 #define FW_EQ_CTRL_CMD_CMPLIQID_S       20
1736 #define FW_EQ_CTRL_CMD_CMPLIQID_V(x)    ((x) << FW_EQ_CTRL_CMD_CMPLIQID_S)
1737
1738 #define FW_EQ_CTRL_CMD_EQID_S           0
1739 #define FW_EQ_CTRL_CMD_EQID_M           0xfffff
1740 #define FW_EQ_CTRL_CMD_EQID_V(x)        ((x) << FW_EQ_CTRL_CMD_EQID_S)
1741 #define FW_EQ_CTRL_CMD_EQID_G(x)        \
1742         (((x) >> FW_EQ_CTRL_CMD_EQID_S) & FW_EQ_CTRL_CMD_EQID_M)
1743
1744 #define FW_EQ_CTRL_CMD_PHYSEQID_S       0
1745 #define FW_EQ_CTRL_CMD_PHYSEQID_M       0xfffff
1746 #define FW_EQ_CTRL_CMD_PHYSEQID_G(x)    \
1747         (((x) >> FW_EQ_CTRL_CMD_PHYSEQID_S) & FW_EQ_CTRL_CMD_PHYSEQID_M)
1748
1749 #define FW_EQ_CTRL_CMD_FETCHSZM_S       26
1750 #define FW_EQ_CTRL_CMD_FETCHSZM_V(x)    ((x) << FW_EQ_CTRL_CMD_FETCHSZM_S)
1751 #define FW_EQ_CTRL_CMD_FETCHSZM_F       FW_EQ_CTRL_CMD_FETCHSZM_V(1U)
1752
1753 #define FW_EQ_CTRL_CMD_STATUSPGNS_S     25
1754 #define FW_EQ_CTRL_CMD_STATUSPGNS_V(x)  ((x) << FW_EQ_CTRL_CMD_STATUSPGNS_S)
1755 #define FW_EQ_CTRL_CMD_STATUSPGNS_F     FW_EQ_CTRL_CMD_STATUSPGNS_V(1U)
1756
1757 #define FW_EQ_CTRL_CMD_STATUSPGRO_S     24
1758 #define FW_EQ_CTRL_CMD_STATUSPGRO_V(x)  ((x) << FW_EQ_CTRL_CMD_STATUSPGRO_S)
1759 #define FW_EQ_CTRL_CMD_STATUSPGRO_F     FW_EQ_CTRL_CMD_STATUSPGRO_V(1U)
1760
1761 #define FW_EQ_CTRL_CMD_FETCHNS_S        23
1762 #define FW_EQ_CTRL_CMD_FETCHNS_V(x)     ((x) << FW_EQ_CTRL_CMD_FETCHNS_S)
1763 #define FW_EQ_CTRL_CMD_FETCHNS_F        FW_EQ_CTRL_CMD_FETCHNS_V(1U)
1764
1765 #define FW_EQ_CTRL_CMD_FETCHRO_S        22
1766 #define FW_EQ_CTRL_CMD_FETCHRO_V(x)     ((x) << FW_EQ_CTRL_CMD_FETCHRO_S)
1767 #define FW_EQ_CTRL_CMD_FETCHRO_F        FW_EQ_CTRL_CMD_FETCHRO_V(1U)
1768
1769 #define FW_EQ_CTRL_CMD_HOSTFCMODE_S     20
1770 #define FW_EQ_CTRL_CMD_HOSTFCMODE_V(x)  ((x) << FW_EQ_CTRL_CMD_HOSTFCMODE_S)
1771
1772 #define FW_EQ_CTRL_CMD_CPRIO_S          19
1773 #define FW_EQ_CTRL_CMD_CPRIO_V(x)       ((x) << FW_EQ_CTRL_CMD_CPRIO_S)
1774
1775 #define FW_EQ_CTRL_CMD_ONCHIP_S         18
1776 #define FW_EQ_CTRL_CMD_ONCHIP_V(x)      ((x) << FW_EQ_CTRL_CMD_ONCHIP_S)
1777
1778 #define FW_EQ_CTRL_CMD_PCIECHN_S        16
1779 #define FW_EQ_CTRL_CMD_PCIECHN_V(x)     ((x) << FW_EQ_CTRL_CMD_PCIECHN_S)
1780
1781 #define FW_EQ_CTRL_CMD_IQID_S           0
1782 #define FW_EQ_CTRL_CMD_IQID_V(x)        ((x) << FW_EQ_CTRL_CMD_IQID_S)
1783
1784 #define FW_EQ_CTRL_CMD_DCAEN_S          31
1785 #define FW_EQ_CTRL_CMD_DCAEN_V(x)       ((x) << FW_EQ_CTRL_CMD_DCAEN_S)
1786
1787 #define FW_EQ_CTRL_CMD_DCACPU_S         26
1788 #define FW_EQ_CTRL_CMD_DCACPU_V(x)      ((x) << FW_EQ_CTRL_CMD_DCACPU_S)
1789
1790 #define FW_EQ_CTRL_CMD_FBMIN_S          23
1791 #define FW_EQ_CTRL_CMD_FBMIN_V(x)       ((x) << FW_EQ_CTRL_CMD_FBMIN_S)
1792
1793 #define FW_EQ_CTRL_CMD_FBMAX_S          20
1794 #define FW_EQ_CTRL_CMD_FBMAX_V(x)       ((x) << FW_EQ_CTRL_CMD_FBMAX_S)
1795
1796 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_S           19
1797 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_V(x)        \
1798         ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESHO_S)
1799
1800 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_S    16
1801 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESH_S)
1802
1803 #define FW_EQ_CTRL_CMD_EQSIZE_S         0
1804 #define FW_EQ_CTRL_CMD_EQSIZE_V(x)      ((x) << FW_EQ_CTRL_CMD_EQSIZE_S)
1805
1806 struct fw_eq_ofld_cmd {
1807         __be32 op_to_vfn;
1808         __be32 alloc_to_len16;
1809         __be32 eqid_pkd;
1810         __be32 physeqid_pkd;
1811         __be32 fetchszm_to_iqid;
1812         __be32 dcaen_to_eqsize;
1813         __be64 eqaddr;
1814 };
1815
1816 #define FW_EQ_OFLD_CMD_PFN_S    8
1817 #define FW_EQ_OFLD_CMD_PFN_V(x) ((x) << FW_EQ_OFLD_CMD_PFN_S)
1818
1819 #define FW_EQ_OFLD_CMD_VFN_S    0
1820 #define FW_EQ_OFLD_CMD_VFN_V(x) ((x) << FW_EQ_OFLD_CMD_VFN_S)
1821
1822 #define FW_EQ_OFLD_CMD_ALLOC_S          31
1823 #define FW_EQ_OFLD_CMD_ALLOC_V(x)       ((x) << FW_EQ_OFLD_CMD_ALLOC_S)
1824 #define FW_EQ_OFLD_CMD_ALLOC_F          FW_EQ_OFLD_CMD_ALLOC_V(1U)
1825
1826 #define FW_EQ_OFLD_CMD_FREE_S           30
1827 #define FW_EQ_OFLD_CMD_FREE_V(x)        ((x) << FW_EQ_OFLD_CMD_FREE_S)
1828 #define FW_EQ_OFLD_CMD_FREE_F           FW_EQ_OFLD_CMD_FREE_V(1U)
1829
1830 #define FW_EQ_OFLD_CMD_MODIFY_S         29
1831 #define FW_EQ_OFLD_CMD_MODIFY_V(x)      ((x) << FW_EQ_OFLD_CMD_MODIFY_S)
1832 #define FW_EQ_OFLD_CMD_MODIFY_F         FW_EQ_OFLD_CMD_MODIFY_V(1U)
1833
1834 #define FW_EQ_OFLD_CMD_EQSTART_S        28
1835 #define FW_EQ_OFLD_CMD_EQSTART_V(x)     ((x) << FW_EQ_OFLD_CMD_EQSTART_S)
1836 #define FW_EQ_OFLD_CMD_EQSTART_F        FW_EQ_OFLD_CMD_EQSTART_V(1U)
1837
1838 #define FW_EQ_OFLD_CMD_EQSTOP_S         27
1839 #define FW_EQ_OFLD_CMD_EQSTOP_V(x)      ((x) << FW_EQ_OFLD_CMD_EQSTOP_S)
1840 #define FW_EQ_OFLD_CMD_EQSTOP_F         FW_EQ_OFLD_CMD_EQSTOP_V(1U)
1841
1842 #define FW_EQ_OFLD_CMD_EQID_S           0
1843 #define FW_EQ_OFLD_CMD_EQID_M           0xfffff
1844 #define FW_EQ_OFLD_CMD_EQID_V(x)        ((x) << FW_EQ_OFLD_CMD_EQID_S)
1845 #define FW_EQ_OFLD_CMD_EQID_G(x)        \
1846         (((x) >> FW_EQ_OFLD_CMD_EQID_S) & FW_EQ_OFLD_CMD_EQID_M)
1847
1848 #define FW_EQ_OFLD_CMD_PHYSEQID_S       0
1849 #define FW_EQ_OFLD_CMD_PHYSEQID_M       0xfffff
1850 #define FW_EQ_OFLD_CMD_PHYSEQID_G(x)    \
1851         (((x) >> FW_EQ_OFLD_CMD_PHYSEQID_S) & FW_EQ_OFLD_CMD_PHYSEQID_M)
1852
1853 #define FW_EQ_OFLD_CMD_FETCHSZM_S       26
1854 #define FW_EQ_OFLD_CMD_FETCHSZM_V(x)    ((x) << FW_EQ_OFLD_CMD_FETCHSZM_S)
1855
1856 #define FW_EQ_OFLD_CMD_STATUSPGNS_S     25
1857 #define FW_EQ_OFLD_CMD_STATUSPGNS_V(x)  ((x) << FW_EQ_OFLD_CMD_STATUSPGNS_S)
1858
1859 #define FW_EQ_OFLD_CMD_STATUSPGRO_S     24
1860 #define FW_EQ_OFLD_CMD_STATUSPGRO_V(x)  ((x) << FW_EQ_OFLD_CMD_STATUSPGRO_S)
1861
1862 #define FW_EQ_OFLD_CMD_FETCHNS_S        23
1863 #define FW_EQ_OFLD_CMD_FETCHNS_V(x)     ((x) << FW_EQ_OFLD_CMD_FETCHNS_S)
1864
1865 #define FW_EQ_OFLD_CMD_FETCHRO_S        22
1866 #define FW_EQ_OFLD_CMD_FETCHRO_V(x)     ((x) << FW_EQ_OFLD_CMD_FETCHRO_S)
1867 #define FW_EQ_OFLD_CMD_FETCHRO_F        FW_EQ_OFLD_CMD_FETCHRO_V(1U)
1868
1869 #define FW_EQ_OFLD_CMD_HOSTFCMODE_S     20
1870 #define FW_EQ_OFLD_CMD_HOSTFCMODE_V(x)  ((x) << FW_EQ_OFLD_CMD_HOSTFCMODE_S)
1871
1872 #define FW_EQ_OFLD_CMD_CPRIO_S          19
1873 #define FW_EQ_OFLD_CMD_CPRIO_V(x)       ((x) << FW_EQ_OFLD_CMD_CPRIO_S)
1874
1875 #define FW_EQ_OFLD_CMD_ONCHIP_S         18
1876 #define FW_EQ_OFLD_CMD_ONCHIP_V(x)      ((x) << FW_EQ_OFLD_CMD_ONCHIP_S)
1877
1878 #define FW_EQ_OFLD_CMD_PCIECHN_S        16
1879 #define FW_EQ_OFLD_CMD_PCIECHN_V(x)     ((x) << FW_EQ_OFLD_CMD_PCIECHN_S)
1880
1881 #define FW_EQ_OFLD_CMD_IQID_S           0
1882 #define FW_EQ_OFLD_CMD_IQID_V(x)        ((x) << FW_EQ_OFLD_CMD_IQID_S)
1883
1884 #define FW_EQ_OFLD_CMD_DCAEN_S          31
1885 #define FW_EQ_OFLD_CMD_DCAEN_V(x)       ((x) << FW_EQ_OFLD_CMD_DCAEN_S)
1886
1887 #define FW_EQ_OFLD_CMD_DCACPU_S         26
1888 #define FW_EQ_OFLD_CMD_DCACPU_V(x)      ((x) << FW_EQ_OFLD_CMD_DCACPU_S)
1889
1890 #define FW_EQ_OFLD_CMD_FBMIN_S          23
1891 #define FW_EQ_OFLD_CMD_FBMIN_V(x)       ((x) << FW_EQ_OFLD_CMD_FBMIN_S)
1892
1893 #define FW_EQ_OFLD_CMD_FBMAX_S          20
1894 #define FW_EQ_OFLD_CMD_FBMAX_V(x)       ((x) << FW_EQ_OFLD_CMD_FBMAX_S)
1895
1896 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_S           19
1897 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_V(x)        \
1898         ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESHO_S)
1899
1900 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_S    16
1901 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESH_S)
1902
1903 #define FW_EQ_OFLD_CMD_EQSIZE_S         0
1904 #define FW_EQ_OFLD_CMD_EQSIZE_V(x)      ((x) << FW_EQ_OFLD_CMD_EQSIZE_S)
1905
1906 /*
1907  * Macros for VIID parsing:
1908  * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
1909  */
1910
1911 #define FW_VIID_PFN_S           8
1912 #define FW_VIID_PFN_M           0x7
1913 #define FW_VIID_PFN_G(x)        (((x) >> FW_VIID_PFN_S) & FW_VIID_PFN_M)
1914
1915 #define FW_VIID_VIVLD_S         7
1916 #define FW_VIID_VIVLD_M         0x1
1917 #define FW_VIID_VIVLD_G(x)      (((x) >> FW_VIID_VIVLD_S) & FW_VIID_VIVLD_M)
1918
1919 #define FW_VIID_VIN_S           0
1920 #define FW_VIID_VIN_M           0x7F
1921 #define FW_VIID_VIN_G(x)        (((x) >> FW_VIID_VIN_S) & FW_VIID_VIN_M)
1922
1923 struct fw_vi_cmd {
1924         __be32 op_to_vfn;
1925         __be32 alloc_to_len16;
1926         __be16 type_viid;
1927         u8 mac[6];
1928         u8 portid_pkd;
1929         u8 nmac;
1930         u8 nmac0[6];
1931         __be16 rsssize_pkd;
1932         u8 nmac1[6];
1933         __be16 idsiiq_pkd;
1934         u8 nmac2[6];
1935         __be16 idseiq_pkd;
1936         u8 nmac3[6];
1937         __be64 r9;
1938         __be64 r10;
1939 };
1940
1941 #define FW_VI_CMD_PFN_S         8
1942 #define FW_VI_CMD_PFN_V(x)      ((x) << FW_VI_CMD_PFN_S)
1943
1944 #define FW_VI_CMD_VFN_S         0
1945 #define FW_VI_CMD_VFN_V(x)      ((x) << FW_VI_CMD_VFN_S)
1946
1947 #define FW_VI_CMD_ALLOC_S       31
1948 #define FW_VI_CMD_ALLOC_V(x)    ((x) << FW_VI_CMD_ALLOC_S)
1949 #define FW_VI_CMD_ALLOC_F       FW_VI_CMD_ALLOC_V(1U)
1950
1951 #define FW_VI_CMD_FREE_S        30
1952 #define FW_VI_CMD_FREE_V(x)     ((x) << FW_VI_CMD_FREE_S)
1953 #define FW_VI_CMD_FREE_F        FW_VI_CMD_FREE_V(1U)
1954
1955 #define FW_VI_CMD_VIID_S        0
1956 #define FW_VI_CMD_VIID_M        0xfff
1957 #define FW_VI_CMD_VIID_V(x)     ((x) << FW_VI_CMD_VIID_S)
1958 #define FW_VI_CMD_VIID_G(x)     (((x) >> FW_VI_CMD_VIID_S) & FW_VI_CMD_VIID_M)
1959
1960 #define FW_VI_CMD_PORTID_S      4
1961 #define FW_VI_CMD_PORTID_M      0xf
1962 #define FW_VI_CMD_PORTID_V(x)   ((x) << FW_VI_CMD_PORTID_S)
1963 #define FW_VI_CMD_PORTID_G(x)   \
1964         (((x) >> FW_VI_CMD_PORTID_S) & FW_VI_CMD_PORTID_M)
1965
1966 #define FW_VI_CMD_RSSSIZE_S     0
1967 #define FW_VI_CMD_RSSSIZE_M     0x7ff
1968 #define FW_VI_CMD_RSSSIZE_G(x)  \
1969         (((x) >> FW_VI_CMD_RSSSIZE_S) & FW_VI_CMD_RSSSIZE_M)
1970
1971 /* Special VI_MAC command index ids */
1972 #define FW_VI_MAC_ADD_MAC               0x3FF
1973 #define FW_VI_MAC_ADD_PERSIST_MAC       0x3FE
1974 #define FW_VI_MAC_MAC_BASED_FREE        0x3FD
1975 #define FW_CLS_TCAM_NUM_ENTRIES         336
1976
1977 enum fw_vi_mac_smac {
1978         FW_VI_MAC_MPS_TCAM_ENTRY,
1979         FW_VI_MAC_MPS_TCAM_ONLY,
1980         FW_VI_MAC_SMT_ONLY,
1981         FW_VI_MAC_SMT_AND_MPSTCAM
1982 };
1983
1984 enum fw_vi_mac_result {
1985         FW_VI_MAC_R_SUCCESS,
1986         FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
1987         FW_VI_MAC_R_SMAC_FAIL,
1988         FW_VI_MAC_R_F_ACL_CHECK
1989 };
1990
1991 struct fw_vi_mac_cmd {
1992         __be32 op_to_viid;
1993         __be32 freemacs_to_len16;
1994         union fw_vi_mac {
1995                 struct fw_vi_mac_exact {
1996                         __be16 valid_to_idx;
1997                         u8 macaddr[6];
1998                 } exact[7];
1999                 struct fw_vi_mac_hash {
2000                         __be64 hashvec;
2001                 } hash;
2002         } u;
2003 };
2004
2005 #define FW_VI_MAC_CMD_VIID_S    0
2006 #define FW_VI_MAC_CMD_VIID_V(x) ((x) << FW_VI_MAC_CMD_VIID_S)
2007
2008 #define FW_VI_MAC_CMD_FREEMACS_S        31
2009 #define FW_VI_MAC_CMD_FREEMACS_V(x)     ((x) << FW_VI_MAC_CMD_FREEMACS_S)
2010
2011 #define FW_VI_MAC_CMD_HASHVECEN_S       23
2012 #define FW_VI_MAC_CMD_HASHVECEN_V(x)    ((x) << FW_VI_MAC_CMD_HASHVECEN_S)
2013 #define FW_VI_MAC_CMD_HASHVECEN_F       FW_VI_MAC_CMD_HASHVECEN_V(1U)
2014
2015 #define FW_VI_MAC_CMD_HASHUNIEN_S       22
2016 #define FW_VI_MAC_CMD_HASHUNIEN_V(x)    ((x) << FW_VI_MAC_CMD_HASHUNIEN_S)
2017
2018 #define FW_VI_MAC_CMD_VALID_S           15
2019 #define FW_VI_MAC_CMD_VALID_V(x)        ((x) << FW_VI_MAC_CMD_VALID_S)
2020 #define FW_VI_MAC_CMD_VALID_F   FW_VI_MAC_CMD_VALID_V(1U)
2021
2022 #define FW_VI_MAC_CMD_PRIO_S    12
2023 #define FW_VI_MAC_CMD_PRIO_V(x) ((x) << FW_VI_MAC_CMD_PRIO_S)
2024
2025 #define FW_VI_MAC_CMD_SMAC_RESULT_S     10
2026 #define FW_VI_MAC_CMD_SMAC_RESULT_M     0x3
2027 #define FW_VI_MAC_CMD_SMAC_RESULT_V(x)  ((x) << FW_VI_MAC_CMD_SMAC_RESULT_S)
2028 #define FW_VI_MAC_CMD_SMAC_RESULT_G(x)  \
2029         (((x) >> FW_VI_MAC_CMD_SMAC_RESULT_S) & FW_VI_MAC_CMD_SMAC_RESULT_M)
2030
2031 #define FW_VI_MAC_CMD_IDX_S     0
2032 #define FW_VI_MAC_CMD_IDX_M     0x3ff
2033 #define FW_VI_MAC_CMD_IDX_V(x)  ((x) << FW_VI_MAC_CMD_IDX_S)
2034 #define FW_VI_MAC_CMD_IDX_G(x)  \
2035         (((x) >> FW_VI_MAC_CMD_IDX_S) & FW_VI_MAC_CMD_IDX_M)
2036
2037 #define FW_RXMODE_MTU_NO_CHG    65535
2038
2039 struct fw_vi_rxmode_cmd {
2040         __be32 op_to_viid;
2041         __be32 retval_len16;
2042         __be32 mtu_to_vlanexen;
2043         __be32 r4_lo;
2044 };
2045
2046 #define FW_VI_RXMODE_CMD_VIID_S         0
2047 #define FW_VI_RXMODE_CMD_VIID_V(x)      ((x) << FW_VI_RXMODE_CMD_VIID_S)
2048
2049 #define FW_VI_RXMODE_CMD_MTU_S          16
2050 #define FW_VI_RXMODE_CMD_MTU_M          0xffff
2051 #define FW_VI_RXMODE_CMD_MTU_V(x)       ((x) << FW_VI_RXMODE_CMD_MTU_S)
2052
2053 #define FW_VI_RXMODE_CMD_PROMISCEN_S    14
2054 #define FW_VI_RXMODE_CMD_PROMISCEN_M    0x3
2055 #define FW_VI_RXMODE_CMD_PROMISCEN_V(x) ((x) << FW_VI_RXMODE_CMD_PROMISCEN_S)
2056
2057 #define FW_VI_RXMODE_CMD_ALLMULTIEN_S           12
2058 #define FW_VI_RXMODE_CMD_ALLMULTIEN_M           0x3
2059 #define FW_VI_RXMODE_CMD_ALLMULTIEN_V(x)        \
2060         ((x) << FW_VI_RXMODE_CMD_ALLMULTIEN_S)
2061
2062 #define FW_VI_RXMODE_CMD_BROADCASTEN_S          10
2063 #define FW_VI_RXMODE_CMD_BROADCASTEN_M          0x3
2064 #define FW_VI_RXMODE_CMD_BROADCASTEN_V(x)       \
2065         ((x) << FW_VI_RXMODE_CMD_BROADCASTEN_S)
2066
2067 #define FW_VI_RXMODE_CMD_VLANEXEN_S     8
2068 #define FW_VI_RXMODE_CMD_VLANEXEN_M     0x3
2069 #define FW_VI_RXMODE_CMD_VLANEXEN_V(x)  ((x) << FW_VI_RXMODE_CMD_VLANEXEN_S)
2070
2071 struct fw_vi_enable_cmd {
2072         __be32 op_to_viid;
2073         __be32 ien_to_len16;
2074         __be16 blinkdur;
2075         __be16 r3;
2076         __be32 r4;
2077 };
2078
2079 #define FW_VI_ENABLE_CMD_VIID_S         0
2080 #define FW_VI_ENABLE_CMD_VIID_V(x)      ((x) << FW_VI_ENABLE_CMD_VIID_S)
2081
2082 #define FW_VI_ENABLE_CMD_IEN_S          31
2083 #define FW_VI_ENABLE_CMD_IEN_V(x)       ((x) << FW_VI_ENABLE_CMD_IEN_S)
2084
2085 #define FW_VI_ENABLE_CMD_EEN_S          30
2086 #define FW_VI_ENABLE_CMD_EEN_V(x)       ((x) << FW_VI_ENABLE_CMD_EEN_S)
2087
2088 #define FW_VI_ENABLE_CMD_LED_S          29
2089 #define FW_VI_ENABLE_CMD_LED_V(x)       ((x) << FW_VI_ENABLE_CMD_LED_S)
2090 #define FW_VI_ENABLE_CMD_LED_F  FW_VI_ENABLE_CMD_LED_V(1U)
2091
2092 #define FW_VI_ENABLE_CMD_DCB_INFO_S     28
2093 #define FW_VI_ENABLE_CMD_DCB_INFO_V(x)  ((x) << FW_VI_ENABLE_CMD_DCB_INFO_S)
2094
2095 /* VI VF stats offset definitions */
2096 #define VI_VF_NUM_STATS 16
2097 enum fw_vi_stats_vf_index {
2098         FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
2099         FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
2100         FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
2101         FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
2102         FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
2103         FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
2104         FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
2105         FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
2106         FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
2107         FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
2108         FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
2109         FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
2110         FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
2111         FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
2112         FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
2113         FW_VI_VF_STAT_RX_ERR_FRAMES_IX
2114 };
2115
2116 /* VI PF stats offset definitions */
2117 #define VI_PF_NUM_STATS 17
2118 enum fw_vi_stats_pf_index {
2119         FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
2120         FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
2121         FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
2122         FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
2123         FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
2124         FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
2125         FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
2126         FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
2127         FW_VI_PF_STAT_RX_BYTES_IX,
2128         FW_VI_PF_STAT_RX_FRAMES_IX,
2129         FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
2130         FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
2131         FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
2132         FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
2133         FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
2134         FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
2135         FW_VI_PF_STAT_RX_ERR_FRAMES_IX
2136 };
2137
2138 struct fw_vi_stats_cmd {
2139         __be32 op_to_viid;
2140         __be32 retval_len16;
2141         union fw_vi_stats {
2142                 struct fw_vi_stats_ctl {
2143                         __be16 nstats_ix;
2144                         __be16 r6;
2145                         __be32 r7;
2146                         __be64 stat0;
2147                         __be64 stat1;
2148                         __be64 stat2;
2149                         __be64 stat3;
2150                         __be64 stat4;
2151                         __be64 stat5;
2152                 } ctl;
2153                 struct fw_vi_stats_pf {
2154                         __be64 tx_bcast_bytes;
2155                         __be64 tx_bcast_frames;
2156                         __be64 tx_mcast_bytes;
2157                         __be64 tx_mcast_frames;
2158                         __be64 tx_ucast_bytes;
2159                         __be64 tx_ucast_frames;
2160                         __be64 tx_offload_bytes;
2161                         __be64 tx_offload_frames;
2162                         __be64 rx_pf_bytes;
2163                         __be64 rx_pf_frames;
2164                         __be64 rx_bcast_bytes;
2165                         __be64 rx_bcast_frames;
2166                         __be64 rx_mcast_bytes;
2167                         __be64 rx_mcast_frames;
2168                         __be64 rx_ucast_bytes;
2169                         __be64 rx_ucast_frames;
2170                         __be64 rx_err_frames;
2171                 } pf;
2172                 struct fw_vi_stats_vf {
2173                         __be64 tx_bcast_bytes;
2174                         __be64 tx_bcast_frames;
2175                         __be64 tx_mcast_bytes;
2176                         __be64 tx_mcast_frames;
2177                         __be64 tx_ucast_bytes;
2178                         __be64 tx_ucast_frames;
2179                         __be64 tx_drop_frames;
2180                         __be64 tx_offload_bytes;
2181                         __be64 tx_offload_frames;
2182                         __be64 rx_bcast_bytes;
2183                         __be64 rx_bcast_frames;
2184                         __be64 rx_mcast_bytes;
2185                         __be64 rx_mcast_frames;
2186                         __be64 rx_ucast_bytes;
2187                         __be64 rx_ucast_frames;
2188                         __be64 rx_err_frames;
2189                 } vf;
2190         } u;
2191 };
2192
2193 #define FW_VI_STATS_CMD_VIID_S          0
2194 #define FW_VI_STATS_CMD_VIID_V(x)       ((x) << FW_VI_STATS_CMD_VIID_S)
2195
2196 #define FW_VI_STATS_CMD_NSTATS_S        12
2197 #define FW_VI_STATS_CMD_NSTATS_V(x)     ((x) << FW_VI_STATS_CMD_NSTATS_S)
2198
2199 #define FW_VI_STATS_CMD_IX_S    0
2200 #define FW_VI_STATS_CMD_IX_V(x) ((x) << FW_VI_STATS_CMD_IX_S)
2201
2202 struct fw_acl_mac_cmd {
2203         __be32 op_to_vfn;
2204         __be32 en_to_len16;
2205         u8 nmac;
2206         u8 r3[7];
2207         __be16 r4;
2208         u8 macaddr0[6];
2209         __be16 r5;
2210         u8 macaddr1[6];
2211         __be16 r6;
2212         u8 macaddr2[6];
2213         __be16 r7;
2214         u8 macaddr3[6];
2215 };
2216
2217 #define FW_ACL_MAC_CMD_PFN_S    8
2218 #define FW_ACL_MAC_CMD_PFN_V(x) ((x) << FW_ACL_MAC_CMD_PFN_S)
2219
2220 #define FW_ACL_MAC_CMD_VFN_S    0
2221 #define FW_ACL_MAC_CMD_VFN_V(x) ((x) << FW_ACL_MAC_CMD_VFN_S)
2222
2223 #define FW_ACL_MAC_CMD_EN_S     31
2224 #define FW_ACL_MAC_CMD_EN_V(x)  ((x) << FW_ACL_MAC_CMD_EN_S)
2225
2226 struct fw_acl_vlan_cmd {
2227         __be32 op_to_vfn;
2228         __be32 en_to_len16;
2229         u8 nvlan;
2230         u8 dropnovlan_fm;
2231         u8 r3_lo[6];
2232         __be16 vlanid[16];
2233 };
2234
2235 #define FW_ACL_VLAN_CMD_PFN_S           8
2236 #define FW_ACL_VLAN_CMD_PFN_V(x)        ((x) << FW_ACL_VLAN_CMD_PFN_S)
2237
2238 #define FW_ACL_VLAN_CMD_VFN_S           0
2239 #define FW_ACL_VLAN_CMD_VFN_V(x)        ((x) << FW_ACL_VLAN_CMD_VFN_S)
2240
2241 #define FW_ACL_VLAN_CMD_EN_S    31
2242 #define FW_ACL_VLAN_CMD_EN_V(x) ((x) << FW_ACL_VLAN_CMD_EN_S)
2243
2244 #define FW_ACL_VLAN_CMD_DROPNOVLAN_S    7
2245 #define FW_ACL_VLAN_CMD_DROPNOVLAN_V(x) ((x) << FW_ACL_VLAN_CMD_DROPNOVLAN_S)
2246
2247 #define FW_ACL_VLAN_CMD_FM_S    6
2248 #define FW_ACL_VLAN_CMD_FM_V(x) ((x) << FW_ACL_VLAN_CMD_FM_S)
2249
2250 enum fw_port_cap {
2251         FW_PORT_CAP_SPEED_100M          = 0x0001,
2252         FW_PORT_CAP_SPEED_1G            = 0x0002,
2253         FW_PORT_CAP_SPEED_25G           = 0x0004,
2254         FW_PORT_CAP_SPEED_10G           = 0x0008,
2255         FW_PORT_CAP_SPEED_40G           = 0x0010,
2256         FW_PORT_CAP_SPEED_100G          = 0x0020,
2257         FW_PORT_CAP_FC_RX               = 0x0040,
2258         FW_PORT_CAP_FC_TX               = 0x0080,
2259         FW_PORT_CAP_ANEG                = 0x0100,
2260         FW_PORT_CAP_MDIX                = 0x0200,
2261         FW_PORT_CAP_MDIAUTO             = 0x0400,
2262         FW_PORT_CAP_FEC                 = 0x0800,
2263         FW_PORT_CAP_TECHKR              = 0x1000,
2264         FW_PORT_CAP_TECHKX4             = 0x2000,
2265         FW_PORT_CAP_802_3_PAUSE         = 0x4000,
2266         FW_PORT_CAP_802_3_ASM_DIR       = 0x8000,
2267 };
2268
2269 enum fw_port_mdi {
2270         FW_PORT_CAP_MDI_UNCHANGED,
2271         FW_PORT_CAP_MDI_AUTO,
2272         FW_PORT_CAP_MDI_F_STRAIGHT,
2273         FW_PORT_CAP_MDI_F_CROSSOVER
2274 };
2275
2276 #define FW_PORT_CAP_MDI_S 9
2277 #define FW_PORT_CAP_MDI_V(x) ((x) << FW_PORT_CAP_MDI_S)
2278
2279 enum fw_port_action {
2280         FW_PORT_ACTION_L1_CFG           = 0x0001,
2281         FW_PORT_ACTION_L2_CFG           = 0x0002,
2282         FW_PORT_ACTION_GET_PORT_INFO    = 0x0003,
2283         FW_PORT_ACTION_L2_PPP_CFG       = 0x0004,
2284         FW_PORT_ACTION_L2_DCB_CFG       = 0x0005,
2285         FW_PORT_ACTION_DCB_READ_TRANS   = 0x0006,
2286         FW_PORT_ACTION_DCB_READ_RECV    = 0x0007,
2287         FW_PORT_ACTION_DCB_READ_DET     = 0x0008,
2288         FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
2289         FW_PORT_ACTION_L1_LOW_PWR_EN    = 0x0011,
2290         FW_PORT_ACTION_L2_WOL_MODE_EN   = 0x0012,
2291         FW_PORT_ACTION_LPBK_TO_NORMAL   = 0x0020,
2292         FW_PORT_ACTION_L1_LPBK          = 0x0021,
2293         FW_PORT_ACTION_L1_PMA_LPBK      = 0x0022,
2294         FW_PORT_ACTION_L1_PCS_LPBK      = 0x0023,
2295         FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024,
2296         FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025,
2297         FW_PORT_ACTION_PHY_RESET        = 0x0040,
2298         FW_PORT_ACTION_PMA_RESET        = 0x0041,
2299         FW_PORT_ACTION_PCS_RESET        = 0x0042,
2300         FW_PORT_ACTION_PHYXS_RESET      = 0x0043,
2301         FW_PORT_ACTION_DTEXS_REEST      = 0x0044,
2302         FW_PORT_ACTION_AN_RESET         = 0x0045
2303 };
2304
2305 enum fw_port_l2cfg_ctlbf {
2306         FW_PORT_L2_CTLBF_OVLAN0 = 0x01,
2307         FW_PORT_L2_CTLBF_OVLAN1 = 0x02,
2308         FW_PORT_L2_CTLBF_OVLAN2 = 0x04,
2309         FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
2310         FW_PORT_L2_CTLBF_IVLAN  = 0x10,
2311         FW_PORT_L2_CTLBF_TXIPG  = 0x20
2312 };
2313
2314 enum fw_port_dcb_versions {
2315         FW_PORT_DCB_VER_UNKNOWN,
2316         FW_PORT_DCB_VER_CEE1D0,
2317         FW_PORT_DCB_VER_CEE1D01,
2318         FW_PORT_DCB_VER_IEEE,
2319         FW_PORT_DCB_VER_AUTO = 7
2320 };
2321
2322 enum fw_port_dcb_cfg {
2323         FW_PORT_DCB_CFG_PG      = 0x01,
2324         FW_PORT_DCB_CFG_PFC     = 0x02,
2325         FW_PORT_DCB_CFG_APPL    = 0x04
2326 };
2327
2328 enum fw_port_dcb_cfg_rc {
2329         FW_PORT_DCB_CFG_SUCCESS = 0x0,
2330         FW_PORT_DCB_CFG_ERROR   = 0x1
2331 };
2332
2333 enum fw_port_dcb_type {
2334         FW_PORT_DCB_TYPE_PGID           = 0x00,
2335         FW_PORT_DCB_TYPE_PGRATE         = 0x01,
2336         FW_PORT_DCB_TYPE_PRIORATE       = 0x02,
2337         FW_PORT_DCB_TYPE_PFC            = 0x03,
2338         FW_PORT_DCB_TYPE_APP_ID         = 0x04,
2339         FW_PORT_DCB_TYPE_CONTROL        = 0x05,
2340 };
2341
2342 enum fw_port_dcb_feature_state {
2343         FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0,
2344         FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1,
2345         FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2,
2346         FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3,
2347 };
2348
2349 struct fw_port_cmd {
2350         __be32 op_to_portid;
2351         __be32 action_to_len16;
2352         union fw_port {
2353                 struct fw_port_l1cfg {
2354                         __be32 rcap;
2355                         __be32 r;
2356                 } l1cfg;
2357                 struct fw_port_l2cfg {
2358                         __u8   ctlbf;
2359                         __u8   ovlan3_to_ivlan0;
2360                         __be16 ivlantype;
2361                         __be16 txipg_force_pinfo;
2362                         __be16 mtu;
2363                         __be16 ovlan0mask;
2364                         __be16 ovlan0type;
2365                         __be16 ovlan1mask;
2366                         __be16 ovlan1type;
2367                         __be16 ovlan2mask;
2368                         __be16 ovlan2type;
2369                         __be16 ovlan3mask;
2370                         __be16 ovlan3type;
2371                 } l2cfg;
2372                 struct fw_port_info {
2373                         __be32 lstatus_to_modtype;
2374                         __be16 pcap;
2375                         __be16 acap;
2376                         __be16 mtu;
2377                         __u8   cbllen;
2378                         __u8   auxlinfo;
2379                         __u8   dcbxdis_pkd;
2380                         __u8   r8_lo;
2381                         __be16 lpacap;
2382                         __be64 r9;
2383                 } info;
2384                 struct fw_port_diags {
2385                         __u8   diagop;
2386                         __u8   r[3];
2387                         __be32 diagval;
2388                 } diags;
2389                 union fw_port_dcb {
2390                         struct fw_port_dcb_pgid {
2391                                 __u8   type;
2392                                 __u8   apply_pkd;
2393                                 __u8   r10_lo[2];
2394                                 __be32 pgid;
2395                                 __be64 r11;
2396                         } pgid;
2397                         struct fw_port_dcb_pgrate {
2398                                 __u8   type;
2399                                 __u8   apply_pkd;
2400                                 __u8   r10_lo[5];
2401                                 __u8   num_tcs_supported;
2402                                 __u8   pgrate[8];
2403                                 __u8   tsa[8];
2404                         } pgrate;
2405                         struct fw_port_dcb_priorate {
2406                                 __u8   type;
2407                                 __u8   apply_pkd;
2408                                 __u8   r10_lo[6];
2409                                 __u8   strict_priorate[8];
2410                         } priorate;
2411                         struct fw_port_dcb_pfc {
2412                                 __u8   type;
2413                                 __u8   pfcen;
2414                                 __u8   r10[5];
2415                                 __u8   max_pfc_tcs;
2416                                 __be64 r11;
2417                         } pfc;
2418                         struct fw_port_app_priority {
2419                                 __u8   type;
2420                                 __u8   r10[2];
2421                                 __u8   idx;
2422                                 __u8   user_prio_map;
2423                                 __u8   sel_field;
2424                                 __be16 protocolid;
2425                                 __be64 r12;
2426                         } app_priority;
2427                         struct fw_port_dcb_control {
2428                                 __u8   type;
2429                                 __u8   all_syncd_pkd;
2430                                 __be16 dcb_version_to_app_state;
2431                                 __be32 r11;
2432                                 __be64 r12;
2433                         } control;
2434                 } dcb;
2435         } u;
2436 };
2437
2438 #define FW_PORT_CMD_READ_S      22
2439 #define FW_PORT_CMD_READ_V(x)   ((x) << FW_PORT_CMD_READ_S)
2440 #define FW_PORT_CMD_READ_F      FW_PORT_CMD_READ_V(1U)
2441
2442 #define FW_PORT_CMD_PORTID_S    0
2443 #define FW_PORT_CMD_PORTID_M    0xf
2444 #define FW_PORT_CMD_PORTID_V(x) ((x) << FW_PORT_CMD_PORTID_S)
2445 #define FW_PORT_CMD_PORTID_G(x) \
2446         (((x) >> FW_PORT_CMD_PORTID_S) & FW_PORT_CMD_PORTID_M)
2447
2448 #define FW_PORT_CMD_ACTION_S    16
2449 #define FW_PORT_CMD_ACTION_M    0xffff
2450 #define FW_PORT_CMD_ACTION_V(x) ((x) << FW_PORT_CMD_ACTION_S)
2451 #define FW_PORT_CMD_ACTION_G(x) \
2452         (((x) >> FW_PORT_CMD_ACTION_S) & FW_PORT_CMD_ACTION_M)
2453
2454 #define FW_PORT_CMD_OVLAN3_S    7
2455 #define FW_PORT_CMD_OVLAN3_V(x) ((x) << FW_PORT_CMD_OVLAN3_S)
2456
2457 #define FW_PORT_CMD_OVLAN2_S    6
2458 #define FW_PORT_CMD_OVLAN2_V(x) ((x) << FW_PORT_CMD_OVLAN2_S)
2459
2460 #define FW_PORT_CMD_OVLAN1_S    5
2461 #define FW_PORT_CMD_OVLAN1_V(x) ((x) << FW_PORT_CMD_OVLAN1_S)
2462
2463 #define FW_PORT_CMD_OVLAN0_S    4
2464 #define FW_PORT_CMD_OVLAN0_V(x) ((x) << FW_PORT_CMD_OVLAN0_S)
2465
2466 #define FW_PORT_CMD_IVLAN0_S    3
2467 #define FW_PORT_CMD_IVLAN0_V(x) ((x) << FW_PORT_CMD_IVLAN0_S)
2468
2469 #define FW_PORT_CMD_TXIPG_S     3
2470 #define FW_PORT_CMD_TXIPG_V(x)  ((x) << FW_PORT_CMD_TXIPG_S)
2471
2472 #define FW_PORT_CMD_LSTATUS_S           31
2473 #define FW_PORT_CMD_LSTATUS_M           0x1
2474 #define FW_PORT_CMD_LSTATUS_V(x)        ((x) << FW_PORT_CMD_LSTATUS_S)
2475 #define FW_PORT_CMD_LSTATUS_G(x)        \
2476         (((x) >> FW_PORT_CMD_LSTATUS_S) & FW_PORT_CMD_LSTATUS_M)
2477 #define FW_PORT_CMD_LSTATUS_F   FW_PORT_CMD_LSTATUS_V(1U)
2478
2479 #define FW_PORT_CMD_LSPEED_S    24
2480 #define FW_PORT_CMD_LSPEED_M    0x3f
2481 #define FW_PORT_CMD_LSPEED_V(x) ((x) << FW_PORT_CMD_LSPEED_S)
2482 #define FW_PORT_CMD_LSPEED_G(x) \
2483         (((x) >> FW_PORT_CMD_LSPEED_S) & FW_PORT_CMD_LSPEED_M)
2484
2485 #define FW_PORT_CMD_TXPAUSE_S           23
2486 #define FW_PORT_CMD_TXPAUSE_V(x)        ((x) << FW_PORT_CMD_TXPAUSE_S)
2487 #define FW_PORT_CMD_TXPAUSE_F   FW_PORT_CMD_TXPAUSE_V(1U)
2488
2489 #define FW_PORT_CMD_RXPAUSE_S           22
2490 #define FW_PORT_CMD_RXPAUSE_V(x)        ((x) << FW_PORT_CMD_RXPAUSE_S)
2491 #define FW_PORT_CMD_RXPAUSE_F   FW_PORT_CMD_RXPAUSE_V(1U)
2492
2493 #define FW_PORT_CMD_MDIOCAP_S           21
2494 #define FW_PORT_CMD_MDIOCAP_V(x)        ((x) << FW_PORT_CMD_MDIOCAP_S)
2495 #define FW_PORT_CMD_MDIOCAP_F   FW_PORT_CMD_MDIOCAP_V(1U)
2496
2497 #define FW_PORT_CMD_MDIOADDR_S          16
2498 #define FW_PORT_CMD_MDIOADDR_M          0x1f
2499 #define FW_PORT_CMD_MDIOADDR_G(x)       \
2500         (((x) >> FW_PORT_CMD_MDIOADDR_S) & FW_PORT_CMD_MDIOADDR_M)
2501
2502 #define FW_PORT_CMD_LPTXPAUSE_S         15
2503 #define FW_PORT_CMD_LPTXPAUSE_V(x)      ((x) << FW_PORT_CMD_LPTXPAUSE_S)
2504 #define FW_PORT_CMD_LPTXPAUSE_F FW_PORT_CMD_LPTXPAUSE_V(1U)
2505
2506 #define FW_PORT_CMD_LPRXPAUSE_S         14
2507 #define FW_PORT_CMD_LPRXPAUSE_V(x)      ((x) << FW_PORT_CMD_LPRXPAUSE_S)
2508 #define FW_PORT_CMD_LPRXPAUSE_F FW_PORT_CMD_LPRXPAUSE_V(1U)
2509
2510 #define FW_PORT_CMD_PTYPE_S     8
2511 #define FW_PORT_CMD_PTYPE_M     0x1f
2512 #define FW_PORT_CMD_PTYPE_G(x)  \
2513         (((x) >> FW_PORT_CMD_PTYPE_S) & FW_PORT_CMD_PTYPE_M)
2514
2515 #define FW_PORT_CMD_LINKDNRC_S          5
2516 #define FW_PORT_CMD_LINKDNRC_M          0x7
2517 #define FW_PORT_CMD_LINKDNRC_G(x)       \
2518         (((x) >> FW_PORT_CMD_LINKDNRC_S) & FW_PORT_CMD_LINKDNRC_M)
2519
2520 #define FW_PORT_CMD_MODTYPE_S           0
2521 #define FW_PORT_CMD_MODTYPE_M           0x1f
2522 #define FW_PORT_CMD_MODTYPE_V(x)        ((x) << FW_PORT_CMD_MODTYPE_S)
2523 #define FW_PORT_CMD_MODTYPE_G(x)        \
2524         (((x) >> FW_PORT_CMD_MODTYPE_S) & FW_PORT_CMD_MODTYPE_M)
2525
2526 #define FW_PORT_CMD_DCBXDIS_S           7
2527 #define FW_PORT_CMD_DCBXDIS_V(x)        ((x) << FW_PORT_CMD_DCBXDIS_S)
2528 #define FW_PORT_CMD_DCBXDIS_F   FW_PORT_CMD_DCBXDIS_V(1U)
2529
2530 #define FW_PORT_CMD_APPLY_S     7
2531 #define FW_PORT_CMD_APPLY_V(x)  ((x) << FW_PORT_CMD_APPLY_S)
2532 #define FW_PORT_CMD_APPLY_F     FW_PORT_CMD_APPLY_V(1U)
2533
2534 #define FW_PORT_CMD_ALL_SYNCD_S         7
2535 #define FW_PORT_CMD_ALL_SYNCD_V(x)      ((x) << FW_PORT_CMD_ALL_SYNCD_S)
2536 #define FW_PORT_CMD_ALL_SYNCD_F FW_PORT_CMD_ALL_SYNCD_V(1U)
2537
2538 #define FW_PORT_CMD_DCB_VERSION_S       12
2539 #define FW_PORT_CMD_DCB_VERSION_M       0x7
2540 #define FW_PORT_CMD_DCB_VERSION_G(x)    \
2541         (((x) >> FW_PORT_CMD_DCB_VERSION_S) & FW_PORT_CMD_DCB_VERSION_M)
2542
2543 enum fw_port_type {
2544         FW_PORT_TYPE_FIBER_XFI,
2545         FW_PORT_TYPE_FIBER_XAUI,
2546         FW_PORT_TYPE_BT_SGMII,
2547         FW_PORT_TYPE_BT_XFI,
2548         FW_PORT_TYPE_BT_XAUI,
2549         FW_PORT_TYPE_KX4,
2550         FW_PORT_TYPE_CX4,
2551         FW_PORT_TYPE_KX,
2552         FW_PORT_TYPE_KR,
2553         FW_PORT_TYPE_SFP,
2554         FW_PORT_TYPE_BP_AP,
2555         FW_PORT_TYPE_BP4_AP,
2556         FW_PORT_TYPE_QSFP_10G,
2557         FW_PORT_TYPE_QSA,
2558         FW_PORT_TYPE_QSFP,
2559         FW_PORT_TYPE_BP40_BA,
2560         FW_PORT_TYPE_KR4_100G,
2561         FW_PORT_TYPE_CR4_QSFP,
2562         FW_PORT_TYPE_CR_QSFP,
2563         FW_PORT_TYPE_CR2_QSFP,
2564         FW_PORT_TYPE_SFP28,
2565
2566         FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_M
2567 };
2568
2569 enum fw_port_module_type {
2570         FW_PORT_MOD_TYPE_NA,
2571         FW_PORT_MOD_TYPE_LR,
2572         FW_PORT_MOD_TYPE_SR,
2573         FW_PORT_MOD_TYPE_ER,
2574         FW_PORT_MOD_TYPE_TWINAX_PASSIVE,
2575         FW_PORT_MOD_TYPE_TWINAX_ACTIVE,
2576         FW_PORT_MOD_TYPE_LRM,
2577         FW_PORT_MOD_TYPE_ERROR          = FW_PORT_CMD_MODTYPE_M - 3,
2578         FW_PORT_MOD_TYPE_UNKNOWN        = FW_PORT_CMD_MODTYPE_M - 2,
2579         FW_PORT_MOD_TYPE_NOTSUPPORTED   = FW_PORT_CMD_MODTYPE_M - 1,
2580
2581         FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_M
2582 };
2583
2584 enum fw_port_mod_sub_type {
2585         FW_PORT_MOD_SUB_TYPE_NA,
2586         FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
2587         FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
2588         FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
2589         FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
2590         FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
2591         FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
2592
2593         /* The following will never been in the VPD.  They are TWINAX cable
2594          * lengths decoded from SFP+ module i2c PROMs.  These should
2595          * almost certainly go somewhere else ...
2596          */
2597         FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
2598         FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
2599         FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
2600         FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
2601 };
2602
2603 enum fw_port_stats_tx_index {
2604         FW_STAT_TX_PORT_BYTES_IX = 0,
2605         FW_STAT_TX_PORT_FRAMES_IX,
2606         FW_STAT_TX_PORT_BCAST_IX,
2607         FW_STAT_TX_PORT_MCAST_IX,
2608         FW_STAT_TX_PORT_UCAST_IX,
2609         FW_STAT_TX_PORT_ERROR_IX,
2610         FW_STAT_TX_PORT_64B_IX,
2611         FW_STAT_TX_PORT_65B_127B_IX,
2612         FW_STAT_TX_PORT_128B_255B_IX,
2613         FW_STAT_TX_PORT_256B_511B_IX,
2614         FW_STAT_TX_PORT_512B_1023B_IX,
2615         FW_STAT_TX_PORT_1024B_1518B_IX,
2616         FW_STAT_TX_PORT_1519B_MAX_IX,
2617         FW_STAT_TX_PORT_DROP_IX,
2618         FW_STAT_TX_PORT_PAUSE_IX,
2619         FW_STAT_TX_PORT_PPP0_IX,
2620         FW_STAT_TX_PORT_PPP1_IX,
2621         FW_STAT_TX_PORT_PPP2_IX,
2622         FW_STAT_TX_PORT_PPP3_IX,
2623         FW_STAT_TX_PORT_PPP4_IX,
2624         FW_STAT_TX_PORT_PPP5_IX,
2625         FW_STAT_TX_PORT_PPP6_IX,
2626         FW_STAT_TX_PORT_PPP7_IX,
2627         FW_NUM_PORT_TX_STATS
2628 };
2629
2630 enum fw_port_stat_rx_index {
2631         FW_STAT_RX_PORT_BYTES_IX = 0,
2632         FW_STAT_RX_PORT_FRAMES_IX,
2633         FW_STAT_RX_PORT_BCAST_IX,
2634         FW_STAT_RX_PORT_MCAST_IX,
2635         FW_STAT_RX_PORT_UCAST_IX,
2636         FW_STAT_RX_PORT_MTU_ERROR_IX,
2637         FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
2638         FW_STAT_RX_PORT_CRC_ERROR_IX,
2639         FW_STAT_RX_PORT_LEN_ERROR_IX,
2640         FW_STAT_RX_PORT_SYM_ERROR_IX,
2641         FW_STAT_RX_PORT_64B_IX,
2642         FW_STAT_RX_PORT_65B_127B_IX,
2643         FW_STAT_RX_PORT_128B_255B_IX,
2644         FW_STAT_RX_PORT_256B_511B_IX,
2645         FW_STAT_RX_PORT_512B_1023B_IX,
2646         FW_STAT_RX_PORT_1024B_1518B_IX,
2647         FW_STAT_RX_PORT_1519B_MAX_IX,
2648         FW_STAT_RX_PORT_PAUSE_IX,
2649         FW_STAT_RX_PORT_PPP0_IX,
2650         FW_STAT_RX_PORT_PPP1_IX,
2651         FW_STAT_RX_PORT_PPP2_IX,
2652         FW_STAT_RX_PORT_PPP3_IX,
2653         FW_STAT_RX_PORT_PPP4_IX,
2654         FW_STAT_RX_PORT_PPP5_IX,
2655         FW_STAT_RX_PORT_PPP6_IX,
2656         FW_STAT_RX_PORT_PPP7_IX,
2657         FW_STAT_RX_PORT_LESS_64B_IX,
2658         FW_STAT_RX_PORT_MAC_ERROR_IX,
2659         FW_NUM_PORT_RX_STATS
2660 };
2661
2662 /* port stats */
2663 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + FW_NUM_PORT_RX_STATS)
2664
2665 struct fw_port_stats_cmd {
2666         __be32 op_to_portid;
2667         __be32 retval_len16;
2668         union fw_port_stats {
2669                 struct fw_port_stats_ctl {
2670                         u8 nstats_bg_bm;
2671                         u8 tx_ix;
2672                         __be16 r6;
2673                         __be32 r7;
2674                         __be64 stat0;
2675                         __be64 stat1;
2676                         __be64 stat2;
2677                         __be64 stat3;
2678                         __be64 stat4;
2679                         __be64 stat5;
2680                 } ctl;
2681                 struct fw_port_stats_all {
2682                         __be64 tx_bytes;
2683                         __be64 tx_frames;
2684                         __be64 tx_bcast;
2685                         __be64 tx_mcast;
2686                         __be64 tx_ucast;
2687                         __be64 tx_error;
2688                         __be64 tx_64b;
2689                         __be64 tx_65b_127b;
2690                         __be64 tx_128b_255b;
2691                         __be64 tx_256b_511b;
2692                         __be64 tx_512b_1023b;
2693                         __be64 tx_1024b_1518b;
2694                         __be64 tx_1519b_max;
2695                         __be64 tx_drop;
2696                         __be64 tx_pause;
2697                         __be64 tx_ppp0;
2698                         __be64 tx_ppp1;
2699                         __be64 tx_ppp2;
2700                         __be64 tx_ppp3;
2701                         __be64 tx_ppp4;
2702                         __be64 tx_ppp5;
2703                         __be64 tx_ppp6;
2704                         __be64 tx_ppp7;
2705                         __be64 rx_bytes;
2706                         __be64 rx_frames;
2707                         __be64 rx_bcast;
2708                         __be64 rx_mcast;
2709                         __be64 rx_ucast;
2710                         __be64 rx_mtu_error;
2711                         __be64 rx_mtu_crc_error;
2712                         __be64 rx_crc_error;
2713                         __be64 rx_len_error;
2714                         __be64 rx_sym_error;
2715                         __be64 rx_64b;
2716                         __be64 rx_65b_127b;
2717                         __be64 rx_128b_255b;
2718                         __be64 rx_256b_511b;
2719                         __be64 rx_512b_1023b;
2720                         __be64 rx_1024b_1518b;
2721                         __be64 rx_1519b_max;
2722                         __be64 rx_pause;
2723                         __be64 rx_ppp0;
2724                         __be64 rx_ppp1;
2725                         __be64 rx_ppp2;
2726                         __be64 rx_ppp3;
2727                         __be64 rx_ppp4;
2728                         __be64 rx_ppp5;
2729                         __be64 rx_ppp6;
2730                         __be64 rx_ppp7;
2731                         __be64 rx_less_64b;
2732                         __be64 rx_bg_drop;
2733                         __be64 rx_bg_trunc;
2734                 } all;
2735         } u;
2736 };
2737
2738 /* port loopback stats */
2739 #define FW_NUM_LB_STATS 16
2740 enum fw_port_lb_stats_index {
2741         FW_STAT_LB_PORT_BYTES_IX,
2742         FW_STAT_LB_PORT_FRAMES_IX,
2743         FW_STAT_LB_PORT_BCAST_IX,
2744         FW_STAT_LB_PORT_MCAST_IX,
2745         FW_STAT_LB_PORT_UCAST_IX,
2746         FW_STAT_LB_PORT_ERROR_IX,
2747         FW_STAT_LB_PORT_64B_IX,
2748         FW_STAT_LB_PORT_65B_127B_IX,
2749         FW_STAT_LB_PORT_128B_255B_IX,
2750         FW_STAT_LB_PORT_256B_511B_IX,
2751         FW_STAT_LB_PORT_512B_1023B_IX,
2752         FW_STAT_LB_PORT_1024B_1518B_IX,
2753         FW_STAT_LB_PORT_1519B_MAX_IX,
2754         FW_STAT_LB_PORT_DROP_FRAMES_IX
2755 };
2756
2757 struct fw_port_lb_stats_cmd {
2758         __be32 op_to_lbport;
2759         __be32 retval_len16;
2760         union fw_port_lb_stats {
2761                 struct fw_port_lb_stats_ctl {
2762                         u8 nstats_bg_bm;
2763                         u8 ix_pkd;
2764                         __be16 r6;
2765                         __be32 r7;
2766                         __be64 stat0;
2767                         __be64 stat1;
2768                         __be64 stat2;
2769                         __be64 stat3;
2770                         __be64 stat4;
2771                         __be64 stat5;
2772                 } ctl;
2773                 struct fw_port_lb_stats_all {
2774                         __be64 tx_bytes;
2775                         __be64 tx_frames;
2776                         __be64 tx_bcast;
2777                         __be64 tx_mcast;
2778                         __be64 tx_ucast;
2779                         __be64 tx_error;
2780                         __be64 tx_64b;
2781                         __be64 tx_65b_127b;
2782                         __be64 tx_128b_255b;
2783                         __be64 tx_256b_511b;
2784                         __be64 tx_512b_1023b;
2785                         __be64 tx_1024b_1518b;
2786                         __be64 tx_1519b_max;
2787                         __be64 rx_lb_drop;
2788                         __be64 rx_lb_trunc;
2789                 } all;
2790         } u;
2791 };
2792
2793 struct fw_rss_ind_tbl_cmd {
2794         __be32 op_to_viid;
2795         __be32 retval_len16;
2796         __be16 niqid;
2797         __be16 startidx;
2798         __be32 r3;
2799         __be32 iq0_to_iq2;
2800         __be32 iq3_to_iq5;
2801         __be32 iq6_to_iq8;
2802         __be32 iq9_to_iq11;
2803         __be32 iq12_to_iq14;
2804         __be32 iq15_to_iq17;
2805         __be32 iq18_to_iq20;
2806         __be32 iq21_to_iq23;
2807         __be32 iq24_to_iq26;
2808         __be32 iq27_to_iq29;
2809         __be32 iq30_iq31;
2810         __be32 r15_lo;
2811 };
2812
2813 #define FW_RSS_IND_TBL_CMD_VIID_S       0
2814 #define FW_RSS_IND_TBL_CMD_VIID_V(x)    ((x) << FW_RSS_IND_TBL_CMD_VIID_S)
2815
2816 #define FW_RSS_IND_TBL_CMD_IQ0_S        20
2817 #define FW_RSS_IND_TBL_CMD_IQ0_V(x)     ((x) << FW_RSS_IND_TBL_CMD_IQ0_S)
2818
2819 #define FW_RSS_IND_TBL_CMD_IQ1_S        10
2820 #define FW_RSS_IND_TBL_CMD_IQ1_V(x)     ((x) << FW_RSS_IND_TBL_CMD_IQ1_S)
2821
2822 #define FW_RSS_IND_TBL_CMD_IQ2_S        0
2823 #define FW_RSS_IND_TBL_CMD_IQ2_V(x)     ((x) << FW_RSS_IND_TBL_CMD_IQ2_S)
2824
2825 struct fw_rss_glb_config_cmd {
2826         __be32 op_to_write;
2827         __be32 retval_len16;
2828         union fw_rss_glb_config {
2829                 struct fw_rss_glb_config_manual {
2830                         __be32 mode_pkd;
2831                         __be32 r3;
2832                         __be64 r4;
2833                         __be64 r5;
2834                 } manual;
2835                 struct fw_rss_glb_config_basicvirtual {
2836                         __be32 mode_pkd;
2837                         __be32 synmapen_to_hashtoeplitz;
2838                         __be64 r8;
2839                         __be64 r9;
2840                 } basicvirtual;
2841         } u;
2842 };
2843
2844 #define FW_RSS_GLB_CONFIG_CMD_MODE_S    28
2845 #define FW_RSS_GLB_CONFIG_CMD_MODE_M    0xf
2846 #define FW_RSS_GLB_CONFIG_CMD_MODE_V(x) ((x) << FW_RSS_GLB_CONFIG_CMD_MODE_S)
2847 #define FW_RSS_GLB_CONFIG_CMD_MODE_G(x) \
2848         (((x) >> FW_RSS_GLB_CONFIG_CMD_MODE_S) & FW_RSS_GLB_CONFIG_CMD_MODE_M)
2849
2850 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL       0
2851 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
2852
2853 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S        8
2854 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(x)     \
2855         ((x) << FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S)
2856 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F        \
2857         FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(1U)
2858
2859 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S           7
2860 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(x)        \
2861         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S)
2862 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F   \
2863         FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(1U)
2864
2865 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S           6
2866 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(x)        \
2867         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S)
2868 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F   \
2869         FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(1U)
2870
2871 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S           5
2872 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(x)        \
2873         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S)
2874 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F   \
2875         FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(1U)
2876
2877 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S           4
2878 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(x)        \
2879         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S)
2880 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F   \
2881         FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(1U)
2882
2883 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S        3
2884 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(x)     \
2885         ((x) << FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S)
2886 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F        \
2887         FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(1U)
2888
2889 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S        2
2890 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(x)     \
2891         ((x) << FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S)
2892 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F        \
2893         FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(1U)
2894
2895 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S       1
2896 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(x)    \
2897         ((x) << FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S)
2898 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F       \
2899         FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(1U)
2900
2901 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S    0
2902 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(x) \
2903         ((x) << FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S)
2904 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F    \
2905         FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(1U)
2906
2907 struct fw_rss_vi_config_cmd {
2908         __be32 op_to_viid;
2909 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0)
2910         __be32 retval_len16;
2911         union fw_rss_vi_config {
2912                 struct fw_rss_vi_config_manual {
2913                         __be64 r3;
2914                         __be64 r4;
2915                         __be64 r5;
2916                 } manual;
2917                 struct fw_rss_vi_config_basicvirtual {
2918                         __be32 r6;
2919                         __be32 defaultq_to_udpen;
2920                         __be64 r9;
2921                         __be64 r10;
2922                 } basicvirtual;
2923         } u;
2924 };
2925
2926 #define FW_RSS_VI_CONFIG_CMD_VIID_S     0
2927 #define FW_RSS_VI_CONFIG_CMD_VIID_V(x)  ((x) << FW_RSS_VI_CONFIG_CMD_VIID_S)
2928
2929 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S         16
2930 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M         0x3ff
2931 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(x)      \
2932         ((x) << FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S)
2933 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(x)      \
2934         (((x) >> FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) & \
2935          FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M)
2936
2937 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S     4
2938 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(x)  \
2939         ((x) << FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S)
2940 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F     \
2941         FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(1U)
2942
2943 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S      3
2944 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(x)   \
2945         ((x) << FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S)
2946 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F      \
2947         FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(1U)
2948
2949 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S     2
2950 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(x)  \
2951         ((x) << FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S)
2952 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F     \
2953         FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(1U)
2954
2955 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S      1
2956 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(x)   \
2957         ((x) << FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S)
2958 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F      \
2959         FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(1U)
2960
2961 #define FW_RSS_VI_CONFIG_CMD_UDPEN_S    0
2962 #define FW_RSS_VI_CONFIG_CMD_UDPEN_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_UDPEN_S)
2963 #define FW_RSS_VI_CONFIG_CMD_UDPEN_F    FW_RSS_VI_CONFIG_CMD_UDPEN_V(1U)
2964
2965 struct fw_clip_cmd {
2966         __be32 op_to_write;
2967         __be32 alloc_to_len16;
2968         __be64 ip_hi;
2969         __be64 ip_lo;
2970         __be32 r4[2];
2971 };
2972
2973 #define FW_CLIP_CMD_ALLOC_S     31
2974 #define FW_CLIP_CMD_ALLOC_V(x)  ((x) << FW_CLIP_CMD_ALLOC_S)
2975 #define FW_CLIP_CMD_ALLOC_F     FW_CLIP_CMD_ALLOC_V(1U)
2976
2977 #define FW_CLIP_CMD_FREE_S      30
2978 #define FW_CLIP_CMD_FREE_V(x)   ((x) << FW_CLIP_CMD_FREE_S)
2979 #define FW_CLIP_CMD_FREE_F      FW_CLIP_CMD_FREE_V(1U)
2980
2981 enum fw_error_type {
2982         FW_ERROR_TYPE_EXCEPTION         = 0x0,
2983         FW_ERROR_TYPE_HWMODULE          = 0x1,
2984         FW_ERROR_TYPE_WR                = 0x2,
2985         FW_ERROR_TYPE_ACL               = 0x3,
2986 };
2987
2988 struct fw_error_cmd {
2989         __be32 op_to_type;
2990         __be32 len16_pkd;
2991         union fw_error {
2992                 struct fw_error_exception {
2993                         __be32 info[6];
2994                 } exception;
2995                 struct fw_error_hwmodule {
2996                         __be32 regaddr;
2997                         __be32 regval;
2998                 } hwmodule;
2999                 struct fw_error_wr {
3000                         __be16 cidx;
3001                         __be16 pfn_vfn;
3002                         __be32 eqid;
3003                         u8 wrhdr[16];
3004                 } wr;
3005                 struct fw_error_acl {
3006                         __be16 cidx;
3007                         __be16 pfn_vfn;
3008                         __be32 eqid;
3009                         __be16 mv_pkd;
3010                         u8 val[6];
3011                         __be64 r4;
3012                 } acl;
3013         } u;
3014 };
3015
3016 struct fw_debug_cmd {
3017         __be32 op_type;
3018         __be32 len16_pkd;
3019         union fw_debug {
3020                 struct fw_debug_assert {
3021                         __be32 fcid;
3022                         __be32 line;
3023                         __be32 x;
3024                         __be32 y;
3025                         u8 filename_0_7[8];
3026                         u8 filename_8_15[8];
3027                         __be64 r3;
3028                 } assert;
3029                 struct fw_debug_prt {
3030                         __be16 dprtstridx;
3031                         __be16 r3[3];
3032                         __be32 dprtstrparam0;
3033                         __be32 dprtstrparam1;
3034                         __be32 dprtstrparam2;
3035                         __be32 dprtstrparam3;
3036                 } prt;
3037         } u;
3038 };
3039
3040 #define FW_DEBUG_CMD_TYPE_S     0
3041 #define FW_DEBUG_CMD_TYPE_M     0xff
3042 #define FW_DEBUG_CMD_TYPE_G(x)  \
3043         (((x) >> FW_DEBUG_CMD_TYPE_S) & FW_DEBUG_CMD_TYPE_M)
3044
3045 #define PCIE_FW_ERR_S           31
3046 #define PCIE_FW_ERR_V(x)        ((x) << PCIE_FW_ERR_S)
3047 #define PCIE_FW_ERR_F           PCIE_FW_ERR_V(1U)
3048
3049 #define PCIE_FW_INIT_S          30
3050 #define PCIE_FW_INIT_V(x)       ((x) << PCIE_FW_INIT_S)
3051 #define PCIE_FW_INIT_F          PCIE_FW_INIT_V(1U)
3052
3053 #define PCIE_FW_HALT_S          29
3054 #define PCIE_FW_HALT_V(x)       ((x) << PCIE_FW_HALT_S)
3055 #define PCIE_FW_HALT_F          PCIE_FW_HALT_V(1U)
3056
3057 #define PCIE_FW_EVAL_S          24
3058 #define PCIE_FW_EVAL_M          0x7
3059 #define PCIE_FW_EVAL_G(x)       (((x) >> PCIE_FW_EVAL_S) & PCIE_FW_EVAL_M)
3060
3061 #define PCIE_FW_MASTER_VLD_S    15
3062 #define PCIE_FW_MASTER_VLD_V(x) ((x) << PCIE_FW_MASTER_VLD_S)
3063 #define PCIE_FW_MASTER_VLD_F    PCIE_FW_MASTER_VLD_V(1U)
3064
3065 #define PCIE_FW_MASTER_S        12
3066 #define PCIE_FW_MASTER_M        0x7
3067 #define PCIE_FW_MASTER_V(x)     ((x) << PCIE_FW_MASTER_S)
3068 #define PCIE_FW_MASTER_G(x)     (((x) >> PCIE_FW_MASTER_S) & PCIE_FW_MASTER_M)
3069
3070 struct fw_hdr {
3071         u8 ver;
3072         u8 chip;                        /* terminator chip type */
3073         __be16  len512;                 /* bin length in units of 512-bytes */
3074         __be32  fw_ver;                 /* firmware version */
3075         __be32  tp_microcode_ver;
3076         u8 intfver_nic;
3077         u8 intfver_vnic;
3078         u8 intfver_ofld;
3079         u8 intfver_ri;
3080         u8 intfver_iscsipdu;
3081         u8 intfver_iscsi;
3082         u8 intfver_fcoepdu;
3083         u8 intfver_fcoe;
3084         __u32   reserved2;
3085         __u32   reserved3;
3086         __u32   reserved4;
3087         __be32  flags;
3088         __be32  reserved6[23];
3089 };
3090
3091 enum fw_hdr_chip {
3092         FW_HDR_CHIP_T4,
3093         FW_HDR_CHIP_T5,
3094         FW_HDR_CHIP_T6
3095 };
3096
3097 #define FW_HDR_FW_VER_MAJOR_S   24
3098 #define FW_HDR_FW_VER_MAJOR_M   0xff
3099 #define FW_HDR_FW_VER_MAJOR_V(x) \
3100         ((x) << FW_HDR_FW_VER_MAJOR_S)
3101 #define FW_HDR_FW_VER_MAJOR_G(x) \
3102         (((x) >> FW_HDR_FW_VER_MAJOR_S) & FW_HDR_FW_VER_MAJOR_M)
3103
3104 #define FW_HDR_FW_VER_MINOR_S   16
3105 #define FW_HDR_FW_VER_MINOR_M   0xff
3106 #define FW_HDR_FW_VER_MINOR_V(x) \
3107         ((x) << FW_HDR_FW_VER_MINOR_S)
3108 #define FW_HDR_FW_VER_MINOR_G(x) \
3109         (((x) >> FW_HDR_FW_VER_MINOR_S) & FW_HDR_FW_VER_MINOR_M)
3110
3111 #define FW_HDR_FW_VER_MICRO_S   8
3112 #define FW_HDR_FW_VER_MICRO_M   0xff
3113 #define FW_HDR_FW_VER_MICRO_V(x) \
3114         ((x) << FW_HDR_FW_VER_MICRO_S)
3115 #define FW_HDR_FW_VER_MICRO_G(x) \
3116         (((x) >> FW_HDR_FW_VER_MICRO_S) & FW_HDR_FW_VER_MICRO_M)
3117
3118 #define FW_HDR_FW_VER_BUILD_S   0
3119 #define FW_HDR_FW_VER_BUILD_M   0xff
3120 #define FW_HDR_FW_VER_BUILD_V(x) \
3121         ((x) << FW_HDR_FW_VER_BUILD_S)
3122 #define FW_HDR_FW_VER_BUILD_G(x) \
3123         (((x) >> FW_HDR_FW_VER_BUILD_S) & FW_HDR_FW_VER_BUILD_M)
3124
3125 enum fw_hdr_intfver {
3126         FW_HDR_INTFVER_NIC      = 0x00,
3127         FW_HDR_INTFVER_VNIC     = 0x00,
3128         FW_HDR_INTFVER_OFLD     = 0x00,
3129         FW_HDR_INTFVER_RI       = 0x00,
3130         FW_HDR_INTFVER_ISCSIPDU = 0x00,
3131         FW_HDR_INTFVER_ISCSI    = 0x00,
3132         FW_HDR_INTFVER_FCOEPDU  = 0x00,
3133         FW_HDR_INTFVER_FCOE     = 0x00,
3134 };
3135
3136 enum fw_hdr_flags {
3137         FW_HDR_FLAGS_RESET_HALT = 0x00000001,
3138 };
3139
3140 /* length of the formatting string  */
3141 #define FW_DEVLOG_FMT_LEN       192
3142
3143 /* maximum number of the formatting string parameters */
3144 #define FW_DEVLOG_FMT_PARAMS_NUM 8
3145
3146 /* priority levels */
3147 enum fw_devlog_level {
3148         FW_DEVLOG_LEVEL_EMERG   = 0x0,
3149         FW_DEVLOG_LEVEL_CRIT    = 0x1,
3150         FW_DEVLOG_LEVEL_ERR     = 0x2,
3151         FW_DEVLOG_LEVEL_NOTICE  = 0x3,
3152         FW_DEVLOG_LEVEL_INFO    = 0x4,
3153         FW_DEVLOG_LEVEL_DEBUG   = 0x5,
3154         FW_DEVLOG_LEVEL_MAX     = 0x5,
3155 };
3156
3157 /* facilities that may send a log message */
3158 enum fw_devlog_facility {
3159         FW_DEVLOG_FACILITY_CORE         = 0x00,
3160         FW_DEVLOG_FACILITY_CF           = 0x01,
3161         FW_DEVLOG_FACILITY_SCHED        = 0x02,
3162         FW_DEVLOG_FACILITY_TIMER        = 0x04,
3163         FW_DEVLOG_FACILITY_RES          = 0x06,
3164         FW_DEVLOG_FACILITY_HW           = 0x08,
3165         FW_DEVLOG_FACILITY_FLR          = 0x10,
3166         FW_DEVLOG_FACILITY_DMAQ         = 0x12,
3167         FW_DEVLOG_FACILITY_PHY          = 0x14,
3168         FW_DEVLOG_FACILITY_MAC          = 0x16,
3169         FW_DEVLOG_FACILITY_PORT         = 0x18,
3170         FW_DEVLOG_FACILITY_VI           = 0x1A,
3171         FW_DEVLOG_FACILITY_FILTER       = 0x1C,
3172         FW_DEVLOG_FACILITY_ACL          = 0x1E,
3173         FW_DEVLOG_FACILITY_TM           = 0x20,
3174         FW_DEVLOG_FACILITY_QFC          = 0x22,
3175         FW_DEVLOG_FACILITY_DCB          = 0x24,
3176         FW_DEVLOG_FACILITY_ETH          = 0x26,
3177         FW_DEVLOG_FACILITY_OFLD         = 0x28,
3178         FW_DEVLOG_FACILITY_RI           = 0x2A,
3179         FW_DEVLOG_FACILITY_ISCSI        = 0x2C,
3180         FW_DEVLOG_FACILITY_FCOE         = 0x2E,
3181         FW_DEVLOG_FACILITY_FOISCSI      = 0x30,
3182         FW_DEVLOG_FACILITY_FOFCOE       = 0x32,
3183         FW_DEVLOG_FACILITY_CHNET        = 0x34,
3184         FW_DEVLOG_FACILITY_MAX          = 0x34,
3185 };
3186
3187 /* log message format */
3188 struct fw_devlog_e {
3189         __be64  timestamp;
3190         __be32  seqno;
3191         __be16  reserved1;
3192         __u8    level;
3193         __u8    facility;
3194         __u8    fmt[FW_DEVLOG_FMT_LEN];
3195         __be32  params[FW_DEVLOG_FMT_PARAMS_NUM];
3196         __be32  reserved3[4];
3197 };
3198
3199 struct fw_devlog_cmd {
3200         __be32 op_to_write;
3201         __be32 retval_len16;
3202         __u8   level;
3203         __u8   r2[7];
3204         __be32 memtype_devlog_memaddr16_devlog;
3205         __be32 memsize_devlog;
3206         __be32 r3[2];
3207 };
3208
3209 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S          28
3210 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M          0xf
3211 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(x)       \
3212         (((x) >> FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S) & \
3213          FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M)
3214
3215 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S        0
3216 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M        0xfffffff
3217 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(x)     \
3218         (((x) >> FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S) & \
3219          FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M)
3220
3221 /* P C I E   F W   P F 7   R E G I S T E R */
3222
3223 /* PF7 stores the Firmware Device Log parameters which allows Host Drivers to
3224  * access the "devlog" which needing to contact firmware.  The encoding is
3225  * mostly the same as that returned by the DEVLOG command except for the size
3226  * which is encoded as the number of entries in multiples-1 of 128 here rather
3227  * than the memory size as is done in the DEVLOG command.  Thus, 0 means 128
3228  * and 15 means 2048.  This of course in turn constrains the allowed values
3229  * for the devlog size ...
3230  */
3231 #define PCIE_FW_PF_DEVLOG               7
3232
3233 #define PCIE_FW_PF_DEVLOG_NENTRIES128_S 28
3234 #define PCIE_FW_PF_DEVLOG_NENTRIES128_M 0xf
3235 #define PCIE_FW_PF_DEVLOG_NENTRIES128_V(x) \
3236         ((x) << PCIE_FW_PF_DEVLOG_NENTRIES128_S)
3237 #define PCIE_FW_PF_DEVLOG_NENTRIES128_G(x) \
3238         (((x) >> PCIE_FW_PF_DEVLOG_NENTRIES128_S) & \
3239          PCIE_FW_PF_DEVLOG_NENTRIES128_M)
3240
3241 #define PCIE_FW_PF_DEVLOG_ADDR16_S      4
3242 #define PCIE_FW_PF_DEVLOG_ADDR16_M      0xffffff
3243 #define PCIE_FW_PF_DEVLOG_ADDR16_V(x)   ((x) << PCIE_FW_PF_DEVLOG_ADDR16_S)
3244 #define PCIE_FW_PF_DEVLOG_ADDR16_G(x) \
3245         (((x) >> PCIE_FW_PF_DEVLOG_ADDR16_S) & PCIE_FW_PF_DEVLOG_ADDR16_M)
3246
3247 #define PCIE_FW_PF_DEVLOG_MEMTYPE_S     0
3248 #define PCIE_FW_PF_DEVLOG_MEMTYPE_M     0xf
3249 #define PCIE_FW_PF_DEVLOG_MEMTYPE_V(x)  ((x) << PCIE_FW_PF_DEVLOG_MEMTYPE_S)
3250 #define PCIE_FW_PF_DEVLOG_MEMTYPE_G(x) \
3251         (((x) >> PCIE_FW_PF_DEVLOG_MEMTYPE_S) & PCIE_FW_PF_DEVLOG_MEMTYPE_M)
3252
3253 #define MAX_IMM_OFLD_TX_DATA_WR_LEN (0xff + sizeof(struct fw_ofld_tx_data_wr))
3254
3255 struct fw_crypto_lookaside_wr {
3256         __be32 op_to_cctx_size;
3257         __be32 len16_pkd;
3258         __be32 session_id;
3259         __be32 rx_chid_to_rx_q_id;
3260         __be32 key_addr;
3261         __be32 pld_size_hash_size;
3262         __be64 cookie;
3263 };
3264
3265 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_S 24
3266 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_M 0xff
3267 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_V(x) \
3268         ((x) << FW_CRYPTO_LOOKASIDE_WR_OPCODE_S)
3269 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_G(x) \
3270         (((x) >> FW_CRYPTO_LOOKASIDE_WR_OPCODE_S) & \
3271          FW_CRYPTO_LOOKASIDE_WR_OPCODE_M)
3272
3273 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_S 23
3274 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_M 0x1
3275 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_V(x) \
3276         ((x) << FW_CRYPTO_LOOKASIDE_WR_COMPL_S)
3277 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_G(x) \
3278         (((x) >> FW_CRYPTO_LOOKASIDE_WR_COMPL_S) & \
3279          FW_CRYPTO_LOOKASIDE_WR_COMPL_M)
3280 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_F FW_CRYPTO_LOOKASIDE_WR_COMPL_V(1U)
3281
3282 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S 15
3283 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M 0xff
3284 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_V(x) \
3285         ((x) << FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S)
3286 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_G(x) \
3287         (((x) >> FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S) & \
3288          FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M)
3289
3290 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S 5
3291 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M 0x3
3292 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_V(x) \
3293         ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S)
3294 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_G(x) \
3295         (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S) & \
3296          FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M)
3297
3298 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S 0
3299 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M 0x1f
3300 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_V(x) \
3301         ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S)
3302 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_G(x) \
3303         (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S) & \
3304          FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M)
3305
3306 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_S 0
3307 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_M 0xff
3308 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_V(x) \
3309         ((x) << FW_CRYPTO_LOOKASIDE_WR_LEN16_S)
3310 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_G(x) \
3311         (((x) >> FW_CRYPTO_LOOKASIDE_WR_LEN16_S) & \
3312          FW_CRYPTO_LOOKASIDE_WR_LEN16_M)
3313
3314 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S 29
3315 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M 0x3
3316 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_V(x) \
3317         ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S)
3318 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_G(x) \
3319         (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S) & \
3320          FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M)
3321
3322 #define FW_CRYPTO_LOOKASIDE_WR_LCB_S  27
3323 #define FW_CRYPTO_LOOKASIDE_WR_LCB_M  0x3
3324 #define FW_CRYPTO_LOOKASIDE_WR_LCB_V(x) \
3325         ((x) << FW_CRYPTO_LOOKASIDE_WR_LCB_S)
3326 #define FW_CRYPTO_LOOKASIDE_WR_LCB_G(x) \
3327         (((x) >> FW_CRYPTO_LOOKASIDE_WR_LCB_S) & FW_CRYPTO_LOOKASIDE_WR_LCB_M)
3328
3329 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_S 25
3330 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_M 0x3
3331 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_V(x) \
3332         ((x) << FW_CRYPTO_LOOKASIDE_WR_PHASH_S)
3333 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_G(x) \
3334         (((x) >> FW_CRYPTO_LOOKASIDE_WR_PHASH_S) & \
3335          FW_CRYPTO_LOOKASIDE_WR_PHASH_M)
3336
3337 #define FW_CRYPTO_LOOKASIDE_WR_IV_S   23
3338 #define FW_CRYPTO_LOOKASIDE_WR_IV_M   0x3
3339 #define FW_CRYPTO_LOOKASIDE_WR_IV_V(x) \
3340         ((x) << FW_CRYPTO_LOOKASIDE_WR_IV_S)
3341 #define FW_CRYPTO_LOOKASIDE_WR_IV_G(x) \
3342         (((x) >> FW_CRYPTO_LOOKASIDE_WR_IV_S) & FW_CRYPTO_LOOKASIDE_WR_IV_M)
3343
3344 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_S 10
3345 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_M 0x3
3346 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_V(x) \
3347         ((x) << FW_CRYPTO_LOOKASIDE_WR_TX_CH_S)
3348 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_G(x) \
3349         (((x) >> FW_CRYPTO_LOOKASIDE_WR_TX_CH_S) & \
3350          FW_CRYPTO_LOOKASIDE_WR_TX_CH_M)
3351
3352 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S 0
3353 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M 0x3ff
3354 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_V(x) \
3355         ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S)
3356 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_G(x) \
3357         (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S) & \
3358          FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M)
3359
3360 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S 24
3361 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M 0xff
3362 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_V(x) \
3363         ((x) << FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S)
3364 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_G(x) \
3365         (((x) >> FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S) & \
3366          FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M)
3367
3368 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S 17
3369 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M 0x7f
3370 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_V(x) \
3371         ((x) << FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S)
3372 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_G(x) \
3373         (((x) >> FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S) & \
3374          FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M)
3375
3376 #endif /* _T4FW_INTERFACE_H_ */