drivers/net/ethernet/emulex/benet/be_cmds.c

   1 /*
   2  * Copyright (C) 2005 - 2011 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 #include <linux/module.h>
  19 #include "be.h"
  20 #include "be_cmds.h"
  21
  22 static struct be_cmd_priv_map cmd_priv_map[] = {
  23         {
  24                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
  25                 CMD_SUBSYSTEM_ETH,
  26                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  27                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  28         },
  29         {
  30                 OPCODE_COMMON_GET_FLOW_CONTROL,
  31                 CMD_SUBSYSTEM_COMMON,
  32                 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
  33                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  34         },
  35         {
  36                 OPCODE_COMMON_SET_FLOW_CONTROL,
  37                 CMD_SUBSYSTEM_COMMON,
  38                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  39                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  40         },
  41         {
  42                 OPCODE_ETH_GET_PPORT_STATS,
  43                 CMD_SUBSYSTEM_ETH,
  44                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  45                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  46         },
  47         {
  48                 OPCODE_COMMON_GET_PHY_DETAILS,
  49                 CMD_SUBSYSTEM_COMMON,
  50                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  51                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  52         }
  53 };
  54
  55 static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode,
  56                            u8 subsystem)
  57 {
  58         int i;
  59         int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
  60         u32 cmd_privileges = adapter->cmd_privileges;
  61
  62         for (i = 0; i < num_entries; i++)
  63                 if (opcode == cmd_priv_map[i].opcode &&
  64                     subsystem == cmd_priv_map[i].subsystem)
  65                         if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
  66                                 return false;
  67
  68         return true;
  69 }
  70
  71 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
  72 {
  73         return wrb->payload.embedded_payload;
  74 }
  75
  76 static void be_mcc_notify(struct be_adapter *adapter)
  77 {
  78         struct be_queue_info *mccq = &adapter->mcc_obj.q;
  79         u32 val = 0;
  80
  81         if (be_error(adapter))
  82                 return;
  83
  84         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
  85         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
  86
  87         wmb();
  88         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
  89 }
  90
  91 /* To check if valid bit is set, check the entire word as we don't know
  92  * the endianness of the data (old entry is host endian while a new entry is
  93  * little endian) */
  94 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
  95 {
  96         u32 flags;
  97
  98         if (compl->flags != 0) {
  99                 flags = le32_to_cpu(compl->flags);
 100                 if (flags & CQE_FLAGS_VALID_MASK) {
 101                         compl->flags = flags;
 102                         return true;
 103                 }
 104         }
 105         return false;
 106 }
 107
 108 /* Need to reset the entire word that houses the valid bit */
 109 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
 110 {
 111         compl->flags = 0;
 112 }
 113
 114 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
 115 {
 116         unsigned long addr;
 117
 118         addr = tag1;
 119         addr = ((addr << 16) << 16) | tag0;
 120         return (void *)addr;
 121 }
 122
 123 static int be_mcc_compl_process(struct be_adapter *adapter,
 124                                 struct be_mcc_compl *compl)
 125 {
 126         u16 compl_status, extd_status;
 127         struct be_cmd_resp_hdr *resp_hdr;
 128         u8 opcode = 0, subsystem = 0;
 129
 130         /* Just swap the status to host endian; mcc tag is opaquely copied
 131          * from mcc_wrb */
 132         be_dws_le_to_cpu(compl, 4);
 133
 134         compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
 135                                 CQE_STATUS_COMPL_MASK;
 136
 137         resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
 138
 139         if (resp_hdr) {
 140                 opcode = resp_hdr->opcode;
 141                 subsystem = resp_hdr->subsystem;
 142         }
 143
 144         if (((opcode == OPCODE_COMMON_WRITE_FLASHROM) ||
 145              (opcode == OPCODE_COMMON_WRITE_OBJECT)) &&
 146             (subsystem == CMD_SUBSYSTEM_COMMON)) {
 147                 adapter->flash_status = compl_status;
 148                 complete(&adapter->flash_compl);
 149         }
 150
 151         if (compl_status == MCC_STATUS_SUCCESS) {
 152                 if (((opcode == OPCODE_ETH_GET_STATISTICS) ||
 153                      (opcode == OPCODE_ETH_GET_PPORT_STATS)) &&
 154                     (subsystem == CMD_SUBSYSTEM_ETH)) {
 155                         be_parse_stats(adapter);
 156                         adapter->stats_cmd_sent = false;
 157                 }
 158                 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
 159                     subsystem == CMD_SUBSYSTEM_COMMON) {
 160                         struct be_cmd_resp_get_cntl_addnl_attribs *resp =
 161                                 (void *)resp_hdr;
 162                         adapter->drv_stats.be_on_die_temperature =
 163                                 resp->on_die_temperature;
 164                 }
 165         } else {
 166                 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES)
 167                         adapter->be_get_temp_freq = 0;
 168
 169                 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
 170                         compl_status == MCC_STATUS_ILLEGAL_REQUEST)
 171                         goto done;
 172
 173                 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
 174                         dev_warn(&adapter->pdev->dev,
 175                                  "VF is not privileged to issue opcode %d-%d\n",
 176                                  opcode, subsystem);
 177                 } else {
 178                         extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
 179                                         CQE_STATUS_EXTD_MASK;
 180                         dev_err(&adapter->pdev->dev,
 181                                 "opcode %d-%d failed:status %d-%d\n",
 182                                 opcode, subsystem, compl_status, extd_status);
 183                 }
 184         }
 185 done:
 186         return compl_status;
 187 }
 188
 189 /* Link state evt is a string of bytes; no need for endian swapping */
 190 static void be_async_link_state_process(struct be_adapter *adapter,
 191                 struct be_async_event_link_state *evt)
 192 {
 193         /* When link status changes, link speed must be re-queried from FW */
 194         adapter->phy.link_speed = -1;
 195
 196         /* Ignore physical link event */
 197         if (lancer_chip(adapter) &&
 198             !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
 199                 return;
 200
 201         /* For the initial link status do not rely on the ASYNC event as
 202          * it may not be received in some cases.
 203          */
 204         if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
 205                 be_link_status_update(adapter, evt->port_link_status);
 206 }
 207
 208 /* Grp5 CoS Priority evt */
 209 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
 210                 struct be_async_event_grp5_cos_priority *evt)
 211 {
 212         if (evt->valid) {
 213                 adapter->vlan_prio_bmap = evt->available_priority_bmap;
 214                 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
 215                 adapter->recommended_prio =
 216                         evt->reco_default_priority << VLAN_PRIO_SHIFT;
 217         }
 218 }
 219
 220 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
 221 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
 222                 struct be_async_event_grp5_qos_link_speed *evt)
 223 {
 224         if (adapter->phy.link_speed >= 0 &&
 225             evt->physical_port == adapter->port_num)
 226                 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
 227 }
 228
 229 /*Grp5 PVID evt*/
 230 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
 231                 struct be_async_event_grp5_pvid_state *evt)
 232 {
 233         if (evt->enabled)
 234                 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
 235         else
 236                 adapter->pvid = 0;
 237 }
 238
 239 static void be_async_grp5_evt_process(struct be_adapter *adapter,
 240                 u32 trailer, struct be_mcc_compl *evt)
 241 {
 242         u8 event_type = 0;
 243
 244         event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
 245                 ASYNC_TRAILER_EVENT_TYPE_MASK;
 246
 247         switch (event_type) {
 248         case ASYNC_EVENT_COS_PRIORITY:
 249                 be_async_grp5_cos_priority_process(adapter,
 250                 (struct be_async_event_grp5_cos_priority *)evt);
 251         break;
 252         case ASYNC_EVENT_QOS_SPEED:
 253                 be_async_grp5_qos_speed_process(adapter,
 254                 (struct be_async_event_grp5_qos_link_speed *)evt);
 255         break;
 256         case ASYNC_EVENT_PVID_STATE:
 257                 be_async_grp5_pvid_state_process(adapter,
 258                 (struct be_async_event_grp5_pvid_state *)evt);
 259         break;
 260         default:
 261                 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
 262                 break;
 263         }
 264 }
 265
 266 static void be_async_dbg_evt_process(struct be_adapter *adapter,
 267                 u32 trailer, struct be_mcc_compl *cmp)
 268 {
 269         u8 event_type = 0;
 270         struct be_async_event_qnq *evt = (struct be_async_event_qnq *) cmp;
 271
 272         event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
 273                 ASYNC_TRAILER_EVENT_TYPE_MASK;
 274
 275         switch (event_type) {
 276         case ASYNC_DEBUG_EVENT_TYPE_QNQ:
 277                 if (evt->valid)
 278                         adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
 279                 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
 280         break;
 281         default:
 282                 dev_warn(&adapter->pdev->dev, "Unknown debug event\n");
 283         break;
 284         }
 285 }
 286
 287 static inline bool is_link_state_evt(u32 trailer)
 288 {
 289         return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 290                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 291                                 ASYNC_EVENT_CODE_LINK_STATE;
 292 }
 293
 294 static inline bool is_grp5_evt(u32 trailer)
 295 {
 296         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 297                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 298                                 ASYNC_EVENT_CODE_GRP_5);
 299 }
 300
 301 static inline bool is_dbg_evt(u32 trailer)
 302 {
 303         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 304                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 305                                 ASYNC_EVENT_CODE_QNQ);
 306 }
 307
 308 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
 309 {
 310         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
 311         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
 312
 313         if (be_mcc_compl_is_new(compl)) {
 314                 queue_tail_inc(mcc_cq);
 315                 return compl;
 316         }
 317         return NULL;
 318 }
 319
 320 void be_async_mcc_enable(struct be_adapter *adapter)
 321 {
 322         spin_lock_bh(&adapter->mcc_cq_lock);
 323
 324         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
 325         adapter->mcc_obj.rearm_cq = true;
 326
 327         spin_unlock_bh(&adapter->mcc_cq_lock);
 328 }
 329
 330 void be_async_mcc_disable(struct be_adapter *adapter)
 331 {
 332         spin_lock_bh(&adapter->mcc_cq_lock);
 333
 334         adapter->mcc_obj.rearm_cq = false;
 335         be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
 336
 337         spin_unlock_bh(&adapter->mcc_cq_lock);
 338 }
 339
 340 int be_process_mcc(struct be_adapter *adapter)
 341 {
 342         struct be_mcc_compl *compl;
 343         int num = 0, status = 0;
 344         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 345
 346         spin_lock(&adapter->mcc_cq_lock);
 347         while ((compl = be_mcc_compl_get(adapter))) {
 348                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 349                         /* Interpret flags as an async trailer */
 350                         if (is_link_state_evt(compl->flags))
 351                                 be_async_link_state_process(adapter,
 352                                 (struct be_async_event_link_state *) compl);
 353                         else if (is_grp5_evt(compl->flags))
 354                                 be_async_grp5_evt_process(adapter,
 355                                 compl->flags, compl);
 356                         else if (is_dbg_evt(compl->flags))
 357                                 be_async_dbg_evt_process(adapter,
 358                                 compl->flags, compl);
 359                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
 360                                 status = be_mcc_compl_process(adapter, compl);
 361                                 atomic_dec(&mcc_obj->q.used);
 362                 }
 363                 be_mcc_compl_use(compl);
 364                 num++;
 365         }
 366
 367         if (num)
 368                 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
 369
 370         spin_unlock(&adapter->mcc_cq_lock);
 371         return status;
 372 }
 373
 374 /* Wait till no more pending mcc requests are present */
 375 static int be_mcc_wait_compl(struct be_adapter *adapter)
 376 {
 377 #define mcc_timeout             120000 /* 12s timeout */
 378         int i, status = 0;
 379         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 380
 381         for (i = 0; i < mcc_timeout; i++) {
 382                 if (be_error(adapter))
 383                         return -EIO;
 384
 385                 local_bh_disable();
 386                 status = be_process_mcc(adapter);
 387                 local_bh_enable();
 388
 389                 if (atomic_read(&mcc_obj->q.used) == 0)
 390                         break;
 391                 udelay(100);
 392         }
 393         if (i == mcc_timeout) {
 394                 dev_err(&adapter->pdev->dev, "FW not responding\n");
 395                 adapter->fw_timeout = true;
 396                 return -EIO;
 397         }
 398         return status;
 399 }
 400
 401 /* Notify MCC requests and wait for completion */
 402 static int be_mcc_notify_wait(struct be_adapter *adapter)
 403 {
 404         int status;
 405         struct be_mcc_wrb *wrb;
 406         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 407         u16 index = mcc_obj->q.head;
 408         struct be_cmd_resp_hdr *resp;
 409
 410         index_dec(&index, mcc_obj->q.len);
 411         wrb = queue_index_node(&mcc_obj->q, index);
 412
 413         resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
 414
 415         be_mcc_notify(adapter);
 416
 417         status = be_mcc_wait_compl(adapter);
 418         if (status == -EIO)
 419                 goto out;
 420
 421         status = resp->status;
 422 out:
 423         return status;
 424 }
 425
 426 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 427 {
 428         int msecs = 0;
 429         u32 ready;
 430
 431         do {
 432                 if (be_error(adapter))
 433                         return -EIO;
 434
 435                 ready = ioread32(db);
 436                 if (ready == 0xffffffff)
 437                         return -1;
 438
 439                 ready &= MPU_MAILBOX_DB_RDY_MASK;
 440                 if (ready)
 441                         break;
 442
 443                 if (msecs > 4000) {
 444                         dev_err(&adapter->pdev->dev, "FW not responding\n");
 445                         adapter->fw_timeout = true;
 446                         be_detect_error(adapter);
 447                         return -1;
 448                 }
 449
 450                 msleep(1);
 451                 msecs++;
 452         } while (true);
 453
 454         return 0;
 455 }
 456
 457 /*
 458  * Insert the mailbox address into the doorbell in two steps
 459  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 460  */
 461 static int be_mbox_notify_wait(struct be_adapter *adapter)
 462 {
 463         int status;
 464         u32 val = 0;
 465         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 466         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 467         struct be_mcc_mailbox *mbox = mbox_mem->va;
 468         struct be_mcc_compl *compl = &mbox->compl;
 469
 470         /* wait for ready to be set */
 471         status = be_mbox_db_ready_wait(adapter, db);
 472         if (status != 0)
 473                 return status;
 474
 475         val |= MPU_MAILBOX_DB_HI_MASK;
 476         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 477         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 478         iowrite32(val, db);
 479
 480         /* wait for ready to be set */
 481         status = be_mbox_db_ready_wait(adapter, db);
 482         if (status != 0)
 483                 return status;
 484
 485         val = 0;
 486         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 487         val |= (u32)(mbox_mem->dma >> 4) << 2;
 488         iowrite32(val, db);
 489
 490         status = be_mbox_db_ready_wait(adapter, db);
 491         if (status != 0)
 492                 return status;
 493
 494         /* A cq entry has been made now */
 495         if (be_mcc_compl_is_new(compl)) {
 496                 status = be_mcc_compl_process(adapter, &mbox->compl);
 497                 be_mcc_compl_use(compl);
 498                 if (status)
 499                         return status;
 500         } else {
 501                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 502                 return -1;
 503         }
 504         return 0;
 505 }
 506
 507 static u16 be_POST_stage_get(struct be_adapter *adapter)
 508 {
 509         u32 sem;
 510
 511         if (BEx_chip(adapter))
 512                 sem  = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
 513         else
 514                 pci_read_config_dword(adapter->pdev,
 515                                       SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
 516
 517         return sem & POST_STAGE_MASK;
 518 }
 519
 520 int lancer_wait_ready(struct be_adapter *adapter)
 521 {
 522 #define SLIPORT_READY_TIMEOUT 30
 523         u32 sliport_status;
 524         int status = 0, i;
 525
 526         for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
 527                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 528                 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
 529                         break;
 530
 531                 msleep(1000);
 532         }
 533
 534         if (i == SLIPORT_READY_TIMEOUT)
 535                 status = -1;
 536
 537         return status;
 538 }
 539
 540 static bool lancer_provisioning_error(struct be_adapter *adapter)
 541 {
 542         u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0;
 543         sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 544         if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
 545                 sliport_err1 = ioread32(adapter->db +
 546                                         SLIPORT_ERROR1_OFFSET);
 547                 sliport_err2 = ioread32(adapter->db +
 548                                         SLIPORT_ERROR2_OFFSET);
 549
 550                 if (sliport_err1 == SLIPORT_ERROR_NO_RESOURCE1 &&
 551                     sliport_err2 == SLIPORT_ERROR_NO_RESOURCE2)
 552                         return true;
 553         }
 554         return false;
 555 }
 556
 557 int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
 558 {
 559         int status;
 560         u32 sliport_status, err, reset_needed;
 561         bool resource_error;
 562
 563         resource_error = lancer_provisioning_error(adapter);
 564         if (resource_error)
 565                 return -1;
 566
 567         status = lancer_wait_ready(adapter);
 568         if (!status) {
 569                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 570                 err = sliport_status & SLIPORT_STATUS_ERR_MASK;
 571                 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK;
 572                 if (err && reset_needed) {
 573                         iowrite32(SLI_PORT_CONTROL_IP_MASK,
 574                                   adapter->db + SLIPORT_CONTROL_OFFSET);
 575
 576                         /* check adapter has corrected the error */
 577                         status = lancer_wait_ready(adapter);
 578                         sliport_status = ioread32(adapter->db +
 579                                                   SLIPORT_STATUS_OFFSET);
 580                         sliport_status &= (SLIPORT_STATUS_ERR_MASK |
 581                                                 SLIPORT_STATUS_RN_MASK);
 582                         if (status || sliport_status)
 583                                 status = -1;
 584                 } else if (err || reset_needed) {
 585                         status = -1;
 586                 }
 587         }
 588         /* Stop error recovery if error is not recoverable.
 589          * No resource error is temporary errors and will go away
 590          * when PF provisions resources.
 591          */
 592         resource_error = lancer_provisioning_error(adapter);
 593         if (status == -1 && !resource_error)
 594                 adapter->eeh_error = true;
 595
 596         return status;
 597 }
 598
 599 int be_fw_wait_ready(struct be_adapter *adapter)
 600 {
 601         u16 stage;
 602         int status, timeout = 0;
 603         struct device *dev = &adapter->pdev->dev;
 604
 605         if (lancer_chip(adapter)) {
 606                 status = lancer_wait_ready(adapter);
 607                 return status;
 608         }
 609
 610         do {
 611                 stage = be_POST_stage_get(adapter);
 612                 if (stage == POST_STAGE_ARMFW_RDY)
 613                         return 0;
 614
 615                 dev_info(dev, "Waiting for POST, %ds elapsed\n",
 616                          timeout);
 617                 if (msleep_interruptible(2000)) {
 618                         dev_err(dev, "Waiting for POST aborted\n");
 619                         return -EINTR;
 620                 }
 621                 timeout += 2;
 622         } while (timeout < 60);
 623
 624         dev_err(dev, "POST timeout; stage=0x%x\n", stage);
 625         return -1;
 626 }
 627
 628
 629 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 630 {
 631         return &wrb->payload.sgl[0];
 632 }
 633
 634
 635 /* Don't touch the hdr after it's prepared */
 636 /* mem will be NULL for embedded commands */
 637 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 638                                 u8 subsystem, u8 opcode, int cmd_len,
 639                                 struct be_mcc_wrb *wrb, struct be_dma_mem *mem)
 640 {
 641         struct be_sge *sge;
 642         unsigned long addr = (unsigned long)req_hdr;
 643         u64 req_addr = addr;
 644
 645         req_hdr->opcode = opcode;
 646         req_hdr->subsystem = subsystem;
 647         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 648         req_hdr->version = 0;
 649
 650         wrb->tag0 = req_addr & 0xFFFFFFFF;
 651         wrb->tag1 = upper_32_bits(req_addr);
 652
 653         wrb->payload_length = cmd_len;
 654         if (mem) {
 655                 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
 656                         MCC_WRB_SGE_CNT_SHIFT;
 657                 sge = nonembedded_sgl(wrb);
 658                 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
 659                 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
 660                 sge->len = cpu_to_le32(mem->size);
 661         } else
 662                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 663         be_dws_cpu_to_le(wrb, 8);
 664 }
 665
 666 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 667                         struct be_dma_mem *mem)
 668 {
 669         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 670         u64 dma = (u64)mem->dma;
 671
 672         for (i = 0; i < buf_pages; i++) {
 673                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 674                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 675                 dma += PAGE_SIZE_4K;
 676         }
 677 }
 678
 679 /* Converts interrupt delay in microseconds to multiplier value */
 680 static u32 eq_delay_to_mult(u32 usec_delay)
 681 {
 682 #define MAX_INTR_RATE                   651042
 683         const u32 round = 10;
 684         u32 multiplier;
 685
 686         if (usec_delay == 0)
 687                 multiplier = 0;
 688         else {
 689                 u32 interrupt_rate = 1000000 / usec_delay;
 690                 /* Max delay, corresponding to the lowest interrupt rate */
 691                 if (interrupt_rate == 0)
 692                         multiplier = 1023;
 693                 else {
 694                         multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
 695                         multiplier /= interrupt_rate;
 696                         /* Round the multiplier to the closest value.*/
 697                         multiplier = (multiplier + round/2) / round;
 698                         multiplier = min(multiplier, (u32)1023);
 699                 }
 700         }
 701         return multiplier;
 702 }
 703
 704 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
 705 {
 706         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 707         struct be_mcc_wrb *wrb
 708                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 709         memset(wrb, 0, sizeof(*wrb));
 710         return wrb;
 711 }
 712
 713 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
 714 {
 715         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 716         struct be_mcc_wrb *wrb;
 717
 718         if (!mccq->created)
 719                 return NULL;
 720
 721         if (atomic_read(&mccq->used) >= mccq->len) {
 722                 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
 723                 return NULL;
 724         }
 725
 726         wrb = queue_head_node(mccq);
 727         queue_head_inc(mccq);
 728         atomic_inc(&mccq->used);
 729         memset(wrb, 0, sizeof(*wrb));
 730         return wrb;
 731 }
 732
 733 /* Tell fw we're about to start firing cmds by writing a
 734  * special pattern across the wrb hdr; uses mbox
 735  */
 736 int be_cmd_fw_init(struct be_adapter *adapter)
 737 {
 738         u8 *wrb;
 739         int status;
 740
 741         if (lancer_chip(adapter))
 742                 return 0;
 743
 744         if (mutex_lock_interruptible(&adapter->mbox_lock))
 745                 return -1;
 746
 747         wrb = (u8 *)wrb_from_mbox(adapter);
 748         *wrb++ = 0xFF;
 749         *wrb++ = 0x12;
 750         *wrb++ = 0x34;
 751         *wrb++ = 0xFF;
 752         *wrb++ = 0xFF;
 753         *wrb++ = 0x56;
 754         *wrb++ = 0x78;
 755         *wrb = 0xFF;
 756
 757         status = be_mbox_notify_wait(adapter);
 758
 759         mutex_unlock(&adapter->mbox_lock);
 760         return status;
 761 }
 762
 763 /* Tell fw we're done with firing cmds by writing a
 764  * special pattern across the wrb hdr; uses mbox
 765  */
 766 int be_cmd_fw_clean(struct be_adapter *adapter)
 767 {
 768         u8 *wrb;
 769         int status;
 770
 771         if (lancer_chip(adapter))
 772                 return 0;
 773
 774         if (mutex_lock_interruptible(&adapter->mbox_lock))
 775                 return -1;
 776
 777         wrb = (u8 *)wrb_from_mbox(adapter);
 778         *wrb++ = 0xFF;
 779         *wrb++ = 0xAA;
 780         *wrb++ = 0xBB;
 781         *wrb++ = 0xFF;
 782         *wrb++ = 0xFF;
 783         *wrb++ = 0xCC;
 784         *wrb++ = 0xDD;
 785         *wrb = 0xFF;
 786
 787         status = be_mbox_notify_wait(adapter);
 788
 789         mutex_unlock(&adapter->mbox_lock);
 790         return status;
 791 }
 792
 793 int be_cmd_eq_create(struct be_adapter *adapter,
 794                 struct be_queue_info *eq, int eq_delay)
 795 {
 796         struct be_mcc_wrb *wrb;
 797         struct be_cmd_req_eq_create *req;
 798         struct be_dma_mem *q_mem = &eq->dma_mem;
 799         int status;
 800
 801         if (mutex_lock_interruptible(&adapter->mbox_lock))
 802                 return -1;
 803
 804         wrb = wrb_from_mbox(adapter);
 805         req = embedded_payload(wrb);
 806
 807         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 808                 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL);
 809
 810         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 811
 812         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
 813         /* 4byte eqe*/
 814         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
 815         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
 816                         __ilog2_u32(eq->len/256));
 817         AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
 818                         eq_delay_to_mult(eq_delay));
 819         be_dws_cpu_to_le(req->context, sizeof(req->context));
 820
 821         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 822
 823         status = be_mbox_notify_wait(adapter);
 824         if (!status) {
 825                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
 826                 eq->id = le16_to_cpu(resp->eq_id);
 827                 eq->created = true;
 828         }
 829
 830         mutex_unlock(&adapter->mbox_lock);
 831         return status;
 832 }
 833
 834 /* Use MCC */
 835 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 836                           bool permanent, u32 if_handle, u32 pmac_id)
 837 {
 838         struct be_mcc_wrb *wrb;
 839         struct be_cmd_req_mac_query *req;
 840         int status;
 841
 842         spin_lock_bh(&adapter->mcc_lock);
 843
 844         wrb = wrb_from_mccq(adapter);
 845         if (!wrb) {
 846                 status = -EBUSY;
 847                 goto err;
 848         }
 849         req = embedded_payload(wrb);
 850
 851         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 852                 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL);
 853         req->type = MAC_ADDRESS_TYPE_NETWORK;
 854         if (permanent) {
 855                 req->permanent = 1;
 856         } else {
 857                 req->if_id = cpu_to_le16((u16) if_handle);
 858                 req->pmac_id = cpu_to_le32(pmac_id);
 859                 req->permanent = 0;
 860         }
 861
 862         status = be_mcc_notify_wait(adapter);
 863         if (!status) {
 864                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
 865                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
 866         }
 867
 868 err:
 869         spin_unlock_bh(&adapter->mcc_lock);
 870         return status;
 871 }
 872
 873 /* Uses synchronous MCCQ */
 874 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
 875                 u32 if_id, u32 *pmac_id, u32 domain)
 876 {
 877         struct be_mcc_wrb *wrb;
 878         struct be_cmd_req_pmac_add *req;
 879         int status;
 880
 881         spin_lock_bh(&adapter->mcc_lock);
 882
 883         wrb = wrb_from_mccq(adapter);
 884         if (!wrb) {
 885                 status = -EBUSY;
 886                 goto err;
 887         }
 888         req = embedded_payload(wrb);
 889
 890         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 891                 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL);
 892
 893         req->hdr.domain = domain;
 894         req->if_id = cpu_to_le32(if_id);
 895         memcpy(req->mac_address, mac_addr, ETH_ALEN);
 896
 897         status = be_mcc_notify_wait(adapter);
 898         if (!status) {
 899                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
 900                 *pmac_id = le32_to_cpu(resp->pmac_id);
 901         }
 902
 903 err:
 904         spin_unlock_bh(&adapter->mcc_lock);
 905
 906          if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
 907                 status = -EPERM;
 908
 909         return status;
 910 }
 911
 912 /* Uses synchronous MCCQ */
 913 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
 914 {
 915         struct be_mcc_wrb *wrb;
 916         struct be_cmd_req_pmac_del *req;
 917         int status;
 918
 919         if (pmac_id == -1)
 920                 return 0;
 921
 922         spin_lock_bh(&adapter->mcc_lock);
 923
 924         wrb = wrb_from_mccq(adapter);
 925         if (!wrb) {
 926                 status = -EBUSY;
 927                 goto err;
 928         }
 929         req = embedded_payload(wrb);
 930
 931         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 932                 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
 933
 934         req->hdr.domain = dom;
 935         req->if_id = cpu_to_le32(if_id);
 936         req->pmac_id = cpu_to_le32(pmac_id);
 937
 938         status = be_mcc_notify_wait(adapter);
 939
 940 err:
 941         spin_unlock_bh(&adapter->mcc_lock);
 942         return status;
 943 }
 944
 945 /* Uses Mbox */
 946 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
 947                 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
 948 {
 949         struct be_mcc_wrb *wrb;
 950         struct be_cmd_req_cq_create *req;
 951         struct be_dma_mem *q_mem = &cq->dma_mem;
 952         void *ctxt;
 953         int status;
 954
 955         if (mutex_lock_interruptible(&adapter->mbox_lock))
 956                 return -1;
 957
 958         wrb = wrb_from_mbox(adapter);
 959         req = embedded_payload(wrb);
 960         ctxt = &req->context;
 961
 962         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 963                 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL);
 964
 965         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 966         if (lancer_chip(adapter)) {
 967                 req->hdr.version = 2;
 968                 req->page_size = 1; /* 1 for 4K */
 969                 AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt,
 970                                                                 no_delay);
 971                 AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt,
 972                                                 __ilog2_u32(cq->len/256));
 973                 AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1);
 974                 AMAP_SET_BITS(struct amap_cq_context_lancer, eventable,
 975                                                                 ctxt, 1);
 976                 AMAP_SET_BITS(struct amap_cq_context_lancer, eqid,
 977                                                                 ctxt, eq->id);
 978         } else {
 979                 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
 980                                                                 coalesce_wm);
 981                 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
 982                                                                 ctxt, no_delay);
 983                 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
 984                                                 __ilog2_u32(cq->len/256));
 985                 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
 986                 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
 987                 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
 988         }
 989
 990         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 991
 992         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 993
 994         status = be_mbox_notify_wait(adapter);
 995         if (!status) {
 996                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
 997                 cq->id = le16_to_cpu(resp->cq_id);
 998                 cq->created = true;
 999         }
1000
1001         mutex_unlock(&adapter->mbox_lock);
1002
1003         return status;
1004 }
1005
1006 static u32 be_encoded_q_len(int q_len)
1007 {
1008         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
1009         if (len_encoded == 16)
1010                 len_encoded = 0;
1011         return len_encoded;
1012 }
1013
1014 int be_cmd_mccq_ext_create(struct be_adapter *adapter,
1015                         struct be_queue_info *mccq,
1016                         struct be_queue_info *cq)
1017 {
1018         struct be_mcc_wrb *wrb;
1019         struct be_cmd_req_mcc_ext_create *req;
1020         struct be_dma_mem *q_mem = &mccq->dma_mem;
1021         void *ctxt;
1022         int status;
1023
1024         if (mutex_lock_interruptible(&adapter->mbox_lock))
1025                 return -1;
1026
1027         wrb = wrb_from_mbox(adapter);
1028         req = embedded_payload(wrb);
1029         ctxt = &req->context;
1030
1031         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1032                         OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL);
1033
1034         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1035         if (lancer_chip(adapter)) {
1036                 req->hdr.version = 1;
1037                 req->cq_id = cpu_to_le16(cq->id);
1038
1039                 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
1040                                                 be_encoded_q_len(mccq->len));
1041                 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
1042                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
1043                                                                 ctxt, cq->id);
1044                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
1045                                                                  ctxt, 1);
1046
1047         } else {
1048                 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1049                 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1050                                                 be_encoded_q_len(mccq->len));
1051                 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1052         }
1053
1054         /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
1055         req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
1056         req->async_event_bitmap[0] |= cpu_to_le32(1 << ASYNC_EVENT_CODE_QNQ);
1057         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1058
1059         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1060
1061         status = be_mbox_notify_wait(adapter);
1062         if (!status) {
1063                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1064                 mccq->id = le16_to_cpu(resp->id);
1065                 mccq->created = true;
1066         }
1067         mutex_unlock(&adapter->mbox_lock);
1068
1069         return status;
1070 }
1071
1072 int be_cmd_mccq_org_create(struct be_adapter *adapter,
1073                         struct be_queue_info *mccq,
1074                         struct be_queue_info *cq)
1075 {
1076         struct be_mcc_wrb *wrb;
1077         struct be_cmd_req_mcc_create *req;
1078         struct be_dma_mem *q_mem = &mccq->dma_mem;
1079         void *ctxt;
1080         int status;
1081
1082         if (mutex_lock_interruptible(&adapter->mbox_lock))
1083                 return -1;
1084
1085         wrb = wrb_from_mbox(adapter);
1086         req = embedded_payload(wrb);
1087         ctxt = &req->context;
1088
1089         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1090                         OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL);
1091
1092         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1093
1094         AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1095         AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1096                         be_encoded_q_len(mccq->len));
1097         AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1098
1099         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1100
1101         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1102
1103         status = be_mbox_notify_wait(adapter);
1104         if (!status) {
1105                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1106                 mccq->id = le16_to_cpu(resp->id);
1107                 mccq->created = true;
1108         }
1109
1110         mutex_unlock(&adapter->mbox_lock);
1111         return status;
1112 }
1113
1114 int be_cmd_mccq_create(struct be_adapter *adapter,
1115                         struct be_queue_info *mccq,
1116                         struct be_queue_info *cq)
1117 {
1118         int status;
1119
1120         status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1121         if (status && !lancer_chip(adapter)) {
1122                 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1123                         "or newer to avoid conflicting priorities between NIC "
1124                         "and FCoE traffic");
1125                 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1126         }
1127         return status;
1128 }
1129
1130 int be_cmd_txq_create(struct be_adapter *adapter,
1131                         struct be_queue_info *txq,
1132                         struct be_queue_info *cq)
1133 {
1134         struct be_mcc_wrb *wrb;
1135         struct be_cmd_req_eth_tx_create *req;
1136         struct be_dma_mem *q_mem = &txq->dma_mem;
1137         void *ctxt;
1138         int status;
1139
1140         spin_lock_bh(&adapter->mcc_lock);
1141
1142         wrb = wrb_from_mccq(adapter);
1143         if (!wrb) {
1144                 status = -EBUSY;
1145                 goto err;
1146         }
1147
1148         req = embedded_payload(wrb);
1149         ctxt = &req->context;
1150
1151         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1152                 OPCODE_ETH_TX_CREATE, sizeof(*req), wrb, NULL);
1153
1154         if (lancer_chip(adapter)) {
1155                 req->hdr.version = 1;
1156                 AMAP_SET_BITS(struct amap_tx_context, if_id, ctxt,
1157                                         adapter->if_handle);
1158         }
1159
1160         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1161         req->ulp_num = BE_ULP1_NUM;
1162         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1163
1164         AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
1165                 be_encoded_q_len(txq->len));
1166         AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
1167         AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
1168
1169         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1170
1171         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1172
1173         status = be_mcc_notify_wait(adapter);
1174         if (!status) {
1175                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
1176                 txq->id = le16_to_cpu(resp->cid);
1177                 txq->created = true;
1178         }
1179
1180 err:
1181         spin_unlock_bh(&adapter->mcc_lock);
1182
1183         return status;
1184 }
1185
1186 /* Uses MCC */
1187 int be_cmd_rxq_create(struct be_adapter *adapter,
1188                 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1189                 u32 if_id, u32 rss, u8 *rss_id)
1190 {
1191         struct be_mcc_wrb *wrb;
1192         struct be_cmd_req_eth_rx_create *req;
1193         struct be_dma_mem *q_mem = &rxq->dma_mem;
1194         int status;
1195
1196         spin_lock_bh(&adapter->mcc_lock);
1197
1198         wrb = wrb_from_mccq(adapter);
1199         if (!wrb) {
1200                 status = -EBUSY;
1201                 goto err;
1202         }
1203         req = embedded_payload(wrb);
1204
1205         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1206                                 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1207
1208         req->cq_id = cpu_to_le16(cq_id);
1209         req->frag_size = fls(frag_size) - 1;
1210         req->num_pages = 2;
1211         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1212         req->interface_id = cpu_to_le32(if_id);
1213         req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
1214         req->rss_queue = cpu_to_le32(rss);
1215
1216         status = be_mcc_notify_wait(adapter);
1217         if (!status) {
1218                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1219                 rxq->id = le16_to_cpu(resp->id);
1220                 rxq->created = true;
1221                 *rss_id = resp->rss_id;
1222         }
1223
1224 err:
1225         spin_unlock_bh(&adapter->mcc_lock);
1226         return status;
1227 }
1228
1229 /* Generic destroyer function for all types of queues
1230  * Uses Mbox
1231  */
1232 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1233                 int queue_type)
1234 {
1235         struct be_mcc_wrb *wrb;
1236         struct be_cmd_req_q_destroy *req;
1237         u8 subsys = 0, opcode = 0;
1238         int status;
1239
1240         if (mutex_lock_interruptible(&adapter->mbox_lock))
1241                 return -1;
1242
1243         wrb = wrb_from_mbox(adapter);
1244         req = embedded_payload(wrb);
1245
1246         switch (queue_type) {
1247         case QTYPE_EQ:
1248                 subsys = CMD_SUBSYSTEM_COMMON;
1249                 opcode = OPCODE_COMMON_EQ_DESTROY;
1250                 break;
1251         case QTYPE_CQ:
1252                 subsys = CMD_SUBSYSTEM_COMMON;
1253                 opcode = OPCODE_COMMON_CQ_DESTROY;
1254                 break;
1255         case QTYPE_TXQ:
1256                 subsys = CMD_SUBSYSTEM_ETH;
1257                 opcode = OPCODE_ETH_TX_DESTROY;
1258                 break;
1259         case QTYPE_RXQ:
1260                 subsys = CMD_SUBSYSTEM_ETH;
1261                 opcode = OPCODE_ETH_RX_DESTROY;
1262                 break;
1263         case QTYPE_MCCQ:
1264                 subsys = CMD_SUBSYSTEM_COMMON;
1265                 opcode = OPCODE_COMMON_MCC_DESTROY;
1266                 break;
1267         default:
1268                 BUG();
1269         }
1270
1271         be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1272                                 NULL);
1273         req->id = cpu_to_le16(q->id);
1274
1275         status = be_mbox_notify_wait(adapter);
1276         q->created = false;
1277
1278         mutex_unlock(&adapter->mbox_lock);
1279         return status;
1280 }
1281
1282 /* Uses MCC */
1283 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1284 {
1285         struct be_mcc_wrb *wrb;
1286         struct be_cmd_req_q_destroy *req;
1287         int status;
1288
1289         spin_lock_bh(&adapter->mcc_lock);
1290
1291         wrb = wrb_from_mccq(adapter);
1292         if (!wrb) {
1293                 status = -EBUSY;
1294                 goto err;
1295         }
1296         req = embedded_payload(wrb);
1297
1298         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1299                         OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1300         req->id = cpu_to_le16(q->id);
1301
1302         status = be_mcc_notify_wait(adapter);
1303         q->created = false;
1304
1305 err:
1306         spin_unlock_bh(&adapter->mcc_lock);
1307         return status;
1308 }
1309
1310 /* Create an rx filtering policy configuration on an i/f
1311  * Uses MCCQ
1312  */
1313 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1314                      u32 *if_handle, u32 domain)
1315 {
1316         struct be_mcc_wrb *wrb;
1317         struct be_cmd_req_if_create *req;
1318         int status;
1319
1320         spin_lock_bh(&adapter->mcc_lock);
1321
1322         wrb = wrb_from_mccq(adapter);
1323         if (!wrb) {
1324                 status = -EBUSY;
1325                 goto err;
1326         }
1327         req = embedded_payload(wrb);
1328
1329         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1330                 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), wrb, NULL);
1331         req->hdr.domain = domain;
1332         req->capability_flags = cpu_to_le32(cap_flags);
1333         req->enable_flags = cpu_to_le32(en_flags);
1334
1335         req->pmac_invalid = true;
1336
1337         status = be_mcc_notify_wait(adapter);
1338         if (!status) {
1339                 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
1340                 *if_handle = le32_to_cpu(resp->interface_id);
1341         }
1342
1343 err:
1344         spin_unlock_bh(&adapter->mcc_lock);
1345         return status;
1346 }
1347
1348 /* Uses MCCQ */
1349 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1350 {
1351         struct be_mcc_wrb *wrb;
1352         struct be_cmd_req_if_destroy *req;
1353         int status;
1354
1355         if (interface_id == -1)
1356                 return 0;
1357
1358         spin_lock_bh(&adapter->mcc_lock);
1359
1360         wrb = wrb_from_mccq(adapter);
1361         if (!wrb) {
1362                 status = -EBUSY;
1363                 goto err;
1364         }
1365         req = embedded_payload(wrb);
1366
1367         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1368                 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL);
1369         req->hdr.domain = domain;
1370         req->interface_id = cpu_to_le32(interface_id);
1371
1372         status = be_mcc_notify_wait(adapter);
1373 err:
1374         spin_unlock_bh(&adapter->mcc_lock);
1375         return status;
1376 }
1377
1378 /* Get stats is a non embedded command: the request is not embedded inside
1379  * WRB but is a separate dma memory block
1380  * Uses asynchronous MCC
1381  */
1382 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1383 {
1384         struct be_mcc_wrb *wrb;
1385         struct be_cmd_req_hdr *hdr;
1386         int status = 0;
1387
1388         spin_lock_bh(&adapter->mcc_lock);
1389
1390         wrb = wrb_from_mccq(adapter);
1391         if (!wrb) {
1392                 status = -EBUSY;
1393                 goto err;
1394         }
1395         hdr = nonemb_cmd->va;
1396
1397         be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1398                 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd);
1399
1400         /* version 1 of the cmd is not supported only by BE2 */
1401         if (!BE2_chip(adapter))
1402                 hdr->version = 1;
1403
1404         be_mcc_notify(adapter);
1405         adapter->stats_cmd_sent = true;
1406
1407 err:
1408         spin_unlock_bh(&adapter->mcc_lock);
1409         return status;
1410 }
1411
1412 /* Lancer Stats */
1413 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1414                                 struct be_dma_mem *nonemb_cmd)
1415 {
1416
1417         struct be_mcc_wrb *wrb;
1418         struct lancer_cmd_req_pport_stats *req;
1419         int status = 0;
1420
1421         if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1422                             CMD_SUBSYSTEM_ETH))
1423                 return -EPERM;
1424
1425         spin_lock_bh(&adapter->mcc_lock);
1426
1427         wrb = wrb_from_mccq(adapter);
1428         if (!wrb) {
1429                 status = -EBUSY;
1430                 goto err;
1431         }
1432         req = nonemb_cmd->va;
1433
1434         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1435                         OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb,
1436                         nonemb_cmd);
1437
1438         req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1439         req->cmd_params.params.reset_stats = 0;
1440
1441         be_mcc_notify(adapter);
1442         adapter->stats_cmd_sent = true;
1443
1444 err:
1445         spin_unlock_bh(&adapter->mcc_lock);
1446         return status;
1447 }
1448
1449 static int be_mac_to_link_speed(int mac_speed)
1450 {
1451         switch (mac_speed) {
1452         case PHY_LINK_SPEED_ZERO:
1453                 return 0;
1454         case PHY_LINK_SPEED_10MBPS:
1455                 return 10;
1456         case PHY_LINK_SPEED_100MBPS:
1457                 return 100;
1458         case PHY_LINK_SPEED_1GBPS:
1459                 return 1000;
1460         case PHY_LINK_SPEED_10GBPS:
1461                 return 10000;
1462         }
1463         return 0;
1464 }
1465
1466 /* Uses synchronous mcc
1467  * Returns link_speed in Mbps
1468  */
1469 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1470                              u8 *link_status, u32 dom)
1471 {
1472         struct be_mcc_wrb *wrb;
1473         struct be_cmd_req_link_status *req;
1474         int status;
1475
1476         spin_lock_bh(&adapter->mcc_lock);
1477
1478         if (link_status)
1479                 *link_status = LINK_DOWN;
1480
1481         wrb = wrb_from_mccq(adapter);
1482         if (!wrb) {
1483                 status = -EBUSY;
1484                 goto err;
1485         }
1486         req = embedded_payload(wrb);
1487
1488         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1489                 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL);
1490
1491         /* version 1 of the cmd is not supported only by BE2 */
1492         if (!BE2_chip(adapter))
1493                 req->hdr.version = 1;
1494
1495         req->hdr.domain = dom;
1496
1497         status = be_mcc_notify_wait(adapter);
1498         if (!status) {
1499                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1500                 if (link_speed) {
1501                         *link_speed = resp->link_speed ?
1502                                       le16_to_cpu(resp->link_speed) * 10 :
1503                                       be_mac_to_link_speed(resp->mac_speed);
1504
1505                         if (!resp->logical_link_status)
1506                                 *link_speed = 0;
1507                 }
1508                 if (link_status)
1509                         *link_status = resp->logical_link_status;
1510         }
1511
1512 err:
1513         spin_unlock_bh(&adapter->mcc_lock);
1514         return status;
1515 }
1516
1517 /* Uses synchronous mcc */
1518 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1519 {
1520         struct be_mcc_wrb *wrb;
1521         struct be_cmd_req_get_cntl_addnl_attribs *req;
1522         int status;
1523
1524         spin_lock_bh(&adapter->mcc_lock);
1525
1526         wrb = wrb_from_mccq(adapter);
1527         if (!wrb) {
1528                 status = -EBUSY;
1529                 goto err;
1530         }
1531         req = embedded_payload(wrb);
1532
1533         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1534                 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req),
1535                 wrb, NULL);
1536
1537         be_mcc_notify(adapter);
1538
1539 err:
1540         spin_unlock_bh(&adapter->mcc_lock);
1541         return status;
1542 }
1543
1544 /* Uses synchronous mcc */
1545 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1546 {
1547         struct be_mcc_wrb *wrb;
1548         struct be_cmd_req_get_fat *req;
1549         int status;
1550
1551         spin_lock_bh(&adapter->mcc_lock);
1552
1553         wrb = wrb_from_mccq(adapter);
1554         if (!wrb) {
1555                 status = -EBUSY;
1556                 goto err;
1557         }
1558         req = embedded_payload(wrb);
1559
1560         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1561                 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL);
1562         req->fat_operation = cpu_to_le32(QUERY_FAT);
1563         status = be_mcc_notify_wait(adapter);
1564         if (!status) {
1565                 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1566                 if (log_size && resp->log_size)
1567                         *log_size = le32_to_cpu(resp->log_size) -
1568                                         sizeof(u32);
1569         }
1570 err:
1571         spin_unlock_bh(&adapter->mcc_lock);
1572         return status;
1573 }
1574
1575 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1576 {
1577         struct be_dma_mem get_fat_cmd;
1578         struct be_mcc_wrb *wrb;
1579         struct be_cmd_req_get_fat *req;
1580         u32 offset = 0, total_size, buf_size,
1581                                 log_offset = sizeof(u32), payload_len;
1582         int status;
1583
1584         if (buf_len == 0)
1585                 return;
1586
1587         total_size = buf_len;
1588
1589         get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1590         get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1591                         get_fat_cmd.size,
1592                         &get_fat_cmd.dma);
1593         if (!get_fat_cmd.va) {
1594                 status = -ENOMEM;
1595                 dev_err(&adapter->pdev->dev,
1596                 "Memory allocation failure while retrieving FAT data\n");
1597                 return;
1598         }
1599
1600         spin_lock_bh(&adapter->mcc_lock);
1601
1602         while (total_size) {
1603                 buf_size = min(total_size, (u32)60*1024);
1604                 total_size -= buf_size;
1605
1606                 wrb = wrb_from_mccq(adapter);
1607                 if (!wrb) {
1608                         status = -EBUSY;
1609                         goto err;
1610                 }
1611                 req = get_fat_cmd.va;
1612
1613                 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1614                 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1615                                 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb,
1616                                 &get_fat_cmd);
1617
1618                 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1619                 req->read_log_offset = cpu_to_le32(log_offset);
1620                 req->read_log_length = cpu_to_le32(buf_size);
1621                 req->data_buffer_size = cpu_to_le32(buf_size);
1622
1623                 status = be_mcc_notify_wait(adapter);
1624                 if (!status) {
1625                         struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1626                         memcpy(buf + offset,
1627                                 resp->data_buffer,
1628                                 le32_to_cpu(resp->read_log_length));
1629                 } else {
1630                         dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1631                         goto err;
1632                 }
1633                 offset += buf_size;
1634                 log_offset += buf_size;
1635         }
1636 err:
1637         pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1638                         get_fat_cmd.va,
1639                         get_fat_cmd.dma);
1640         spin_unlock_bh(&adapter->mcc_lock);
1641 }
1642
1643 /* Uses synchronous mcc */
1644 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1645                         char *fw_on_flash)
1646 {
1647         struct be_mcc_wrb *wrb;
1648         struct be_cmd_req_get_fw_version *req;
1649         int status;
1650
1651         spin_lock_bh(&adapter->mcc_lock);
1652
1653         wrb = wrb_from_mccq(adapter);
1654         if (!wrb) {
1655                 status = -EBUSY;
1656                 goto err;
1657         }
1658
1659         req = embedded_payload(wrb);
1660
1661         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1662                 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL);
1663         status = be_mcc_notify_wait(adapter);
1664         if (!status) {
1665                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1666                 strcpy(fw_ver, resp->firmware_version_string);
1667                 if (fw_on_flash)
1668                         strcpy(fw_on_flash, resp->fw_on_flash_version_string);
1669         }
1670 err:
1671         spin_unlock_bh(&adapter->mcc_lock);
1672         return status;
1673 }
1674
1675 /* set the EQ delay interval of an EQ to specified value
1676  * Uses async mcc
1677  */
1678 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1679 {
1680         struct be_mcc_wrb *wrb;
1681         struct be_cmd_req_modify_eq_delay *req;
1682         int status = 0;
1683
1684         spin_lock_bh(&adapter->mcc_lock);
1685
1686         wrb = wrb_from_mccq(adapter);
1687         if (!wrb) {
1688                 status = -EBUSY;
1689                 goto err;
1690         }
1691         req = embedded_payload(wrb);
1692
1693         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1694                 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL);
1695
1696         req->num_eq = cpu_to_le32(1);
1697         req->delay[0].eq_id = cpu_to_le32(eq_id);
1698         req->delay[0].phase = 0;
1699         req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1700
1701         be_mcc_notify(adapter);
1702
1703 err:
1704         spin_unlock_bh(&adapter->mcc_lock);
1705         return status;
1706 }
1707
1708 /* Uses sycnhronous mcc */
1709 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1710                         u32 num, bool untagged, bool promiscuous)
1711 {
1712         struct be_mcc_wrb *wrb;
1713         struct be_cmd_req_vlan_config *req;
1714         int status;
1715
1716         spin_lock_bh(&adapter->mcc_lock);
1717
1718         wrb = wrb_from_mccq(adapter);
1719         if (!wrb) {
1720                 status = -EBUSY;
1721                 goto err;
1722         }
1723         req = embedded_payload(wrb);
1724
1725         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1726                 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL);
1727
1728         req->interface_id = if_id;
1729         req->promiscuous = promiscuous;
1730         req->untagged = untagged;
1731         req->num_vlan = num;
1732         if (!promiscuous) {
1733                 memcpy(req->normal_vlan, vtag_array,
1734                         req->num_vlan * sizeof(vtag_array[0]));
1735         }
1736
1737         status = be_mcc_notify_wait(adapter);
1738
1739 err:
1740         spin_unlock_bh(&adapter->mcc_lock);
1741         return status;
1742 }
1743
1744 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1745 {
1746         struct be_mcc_wrb *wrb;
1747         struct be_dma_mem *mem = &adapter->rx_filter;
1748         struct be_cmd_req_rx_filter *req = mem->va;
1749         int status;
1750
1751         spin_lock_bh(&adapter->mcc_lock);
1752
1753         wrb = wrb_from_mccq(adapter);
1754         if (!wrb) {
1755                 status = -EBUSY;
1756                 goto err;
1757         }
1758         memset(req, 0, sizeof(*req));
1759         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1760                                 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1761                                 wrb, mem);
1762
1763         req->if_id = cpu_to_le32(adapter->if_handle);
1764         if (flags & IFF_PROMISC) {
1765                 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1766                                         BE_IF_FLAGS_VLAN_PROMISCUOUS);
1767                 if (value == ON)
1768                         req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1769                                                 BE_IF_FLAGS_VLAN_PROMISCUOUS);
1770         } else if (flags & IFF_ALLMULTI) {
1771                 req->if_flags_mask = req->if_flags =
1772                                 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1773         } else {
1774                 struct netdev_hw_addr *ha;
1775                 int i = 0;
1776
1777                 req->if_flags_mask = req->if_flags =
1778                                 cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1779
1780                 /* Reset mcast promisc mode if already set by setting mask
1781                  * and not setting flags field
1782                  */
1783                 req->if_flags_mask |=
1784                         cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
1785                                     adapter->if_cap_flags);
1786
1787                 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
1788                 netdev_for_each_mc_addr(ha, adapter->netdev)
1789                         memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
1790         }
1791
1792         status = be_mcc_notify_wait(adapter);
1793 err:
1794         spin_unlock_bh(&adapter->mcc_lock);
1795         return status;
1796 }
1797
1798 /* Uses synchrounous mcc */
1799 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1800 {
1801         struct be_mcc_wrb *wrb;
1802         struct be_cmd_req_set_flow_control *req;
1803         int status;
1804
1805         if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
1806                             CMD_SUBSYSTEM_COMMON))
1807                 return -EPERM;
1808
1809         spin_lock_bh(&adapter->mcc_lock);
1810
1811         wrb = wrb_from_mccq(adapter);
1812         if (!wrb) {
1813                 status = -EBUSY;
1814                 goto err;
1815         }
1816         req = embedded_payload(wrb);
1817
1818         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1819                 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1820
1821         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1822         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1823
1824         status = be_mcc_notify_wait(adapter);
1825
1826 err:
1827         spin_unlock_bh(&adapter->mcc_lock);
1828         return status;
1829 }
1830
1831 /* Uses sycn mcc */
1832 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1833 {
1834         struct be_mcc_wrb *wrb;
1835         struct be_cmd_req_get_flow_control *req;
1836         int status;
1837
1838         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
1839                             CMD_SUBSYSTEM_COMMON))
1840                 return -EPERM;
1841
1842         spin_lock_bh(&adapter->mcc_lock);
1843
1844         wrb = wrb_from_mccq(adapter);
1845         if (!wrb) {
1846                 status = -EBUSY;
1847                 goto err;
1848         }
1849         req = embedded_payload(wrb);
1850
1851         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1852                 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1853
1854         status = be_mcc_notify_wait(adapter);
1855         if (!status) {
1856                 struct be_cmd_resp_get_flow_control *resp =
1857                                                 embedded_payload(wrb);
1858                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1859                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1860         }
1861
1862 err:
1863         spin_unlock_bh(&adapter->mcc_lock);
1864         return status;
1865 }
1866
1867 /* Uses mbox */
1868 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1869                 u32 *mode, u32 *caps)
1870 {
1871         struct be_mcc_wrb *wrb;
1872         struct be_cmd_req_query_fw_cfg *req;
1873         int status;
1874
1875         if (mutex_lock_interruptible(&adapter->mbox_lock))
1876                 return -1;
1877
1878         wrb = wrb_from_mbox(adapter);
1879         req = embedded_payload(wrb);
1880
1881         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1882                 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL);
1883
1884         status = be_mbox_notify_wait(adapter);
1885         if (!status) {
1886                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1887                 *port_num = le32_to_cpu(resp->phys_port);
1888                 *mode = le32_to_cpu(resp->function_mode);
1889                 *caps = le32_to_cpu(resp->function_caps);
1890         }
1891
1892         mutex_unlock(&adapter->mbox_lock);
1893         return status;
1894 }
1895
1896 /* Uses mbox */
1897 int be_cmd_reset_function(struct be_adapter *adapter)
1898 {
1899         struct be_mcc_wrb *wrb;
1900         struct be_cmd_req_hdr *req;
1901         int status;
1902
1903         if (lancer_chip(adapter)) {
1904                 status = lancer_wait_ready(adapter);
1905                 if (!status) {
1906                         iowrite32(SLI_PORT_CONTROL_IP_MASK,
1907                                   adapter->db + SLIPORT_CONTROL_OFFSET);
1908                         status = lancer_test_and_set_rdy_state(adapter);
1909                 }
1910                 if (status) {
1911                         dev_err(&adapter->pdev->dev,
1912                                 "Adapter in non recoverable error\n");
1913                 }
1914                 return status;
1915         }
1916
1917         if (mutex_lock_interruptible(&adapter->mbox_lock))
1918                 return -1;
1919
1920         wrb = wrb_from_mbox(adapter);
1921         req = embedded_payload(wrb);
1922
1923         be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1924                 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL);
1925
1926         status = be_mbox_notify_wait(adapter);
1927
1928         mutex_unlock(&adapter->mbox_lock);
1929         return status;
1930 }
1931
1932 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
1933 {
1934         struct be_mcc_wrb *wrb;
1935         struct be_cmd_req_rss_config *req;
1936         u32 myhash[10] = {0x15d43fa5, 0x2534685a, 0x5f87693a, 0x5668494e,
1937                         0x33cf6a53, 0x383334c6, 0x76ac4257, 0x59b242b2,
1938                         0x3ea83c02, 0x4a110304};
1939         int status;
1940
1941         if (mutex_lock_interruptible(&adapter->mbox_lock))
1942                 return -1;
1943
1944         wrb = wrb_from_mbox(adapter);
1945         req = embedded_payload(wrb);
1946
1947         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1948                 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
1949
1950         req->if_id = cpu_to_le32(adapter->if_handle);
1951         req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4 |
1952                                       RSS_ENABLE_TCP_IPV6 | RSS_ENABLE_IPV6);
1953
1954         if (lancer_chip(adapter) || skyhawk_chip(adapter)) {
1955                 req->hdr.version = 1;
1956                 req->enable_rss |= cpu_to_le16(RSS_ENABLE_UDP_IPV4 |
1957                                                RSS_ENABLE_UDP_IPV6);
1958         }
1959
1960         req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1961         memcpy(req->cpu_table, rsstable, table_size);
1962         memcpy(req->hash, myhash, sizeof(myhash));
1963         be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1964
1965         status = be_mbox_notify_wait(adapter);
1966
1967         mutex_unlock(&adapter->mbox_lock);
1968         return status;
1969 }
1970
1971 /* Uses sync mcc */
1972 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1973                         u8 bcn, u8 sts, u8 state)
1974 {
1975         struct be_mcc_wrb *wrb;
1976         struct be_cmd_req_enable_disable_beacon *req;
1977         int status;
1978
1979         spin_lock_bh(&adapter->mcc_lock);
1980
1981         wrb = wrb_from_mccq(adapter);
1982         if (!wrb) {
1983                 status = -EBUSY;
1984                 goto err;
1985         }
1986         req = embedded_payload(wrb);
1987
1988         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1989                 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL);
1990
1991         req->port_num = port_num;
1992         req->beacon_state = state;
1993         req->beacon_duration = bcn;
1994         req->status_duration = sts;
1995
1996         status = be_mcc_notify_wait(adapter);
1997
1998 err:
1999         spin_unlock_bh(&adapter->mcc_lock);
2000         return status;
2001 }
2002
2003 /* Uses sync mcc */
2004 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2005 {
2006         struct be_mcc_wrb *wrb;
2007         struct be_cmd_req_get_beacon_state *req;
2008         int status;
2009
2010         spin_lock_bh(&adapter->mcc_lock);
2011
2012         wrb = wrb_from_mccq(adapter);
2013         if (!wrb) {
2014                 status = -EBUSY;
2015                 goto err;
2016         }
2017         req = embedded_payload(wrb);
2018
2019         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2020                 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL);
2021
2022         req->port_num = port_num;
2023
2024         status = be_mcc_notify_wait(adapter);
2025         if (!status) {
2026                 struct be_cmd_resp_get_beacon_state *resp =
2027                                                 embedded_payload(wrb);
2028                 *state = resp->beacon_state;
2029         }
2030
2031 err:
2032         spin_unlock_bh(&adapter->mcc_lock);
2033         return status;
2034 }
2035
2036 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2037                             u32 data_size, u32 data_offset,
2038                             const char *obj_name, u32 *data_written,
2039                             u8 *change_status, u8 *addn_status)
2040 {
2041         struct be_mcc_wrb *wrb;
2042         struct lancer_cmd_req_write_object *req;
2043         struct lancer_cmd_resp_write_object *resp;
2044         void *ctxt = NULL;
2045         int status;
2046
2047         spin_lock_bh(&adapter->mcc_lock);
2048         adapter->flash_status = 0;
2049
2050         wrb = wrb_from_mccq(adapter);
2051         if (!wrb) {
2052                 status = -EBUSY;
2053                 goto err_unlock;
2054         }
2055
2056         req = embedded_payload(wrb);
2057
2058         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2059                                 OPCODE_COMMON_WRITE_OBJECT,
2060                                 sizeof(struct lancer_cmd_req_write_object), wrb,
2061                                 NULL);
2062
2063         ctxt = &req->context;
2064         AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2065                         write_length, ctxt, data_size);
2066
2067         if (data_size == 0)
2068                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2069                                 eof, ctxt, 1);
2070         else
2071                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2072                                 eof, ctxt, 0);
2073
2074         be_dws_cpu_to_le(ctxt, sizeof(req->context));
2075         req->write_offset = cpu_to_le32(data_offset);
2076         strcpy(req->object_name, obj_name);
2077         req->descriptor_count = cpu_to_le32(1);
2078         req->buf_len = cpu_to_le32(data_size);
2079         req->addr_low = cpu_to_le32((cmd->dma +
2080                                 sizeof(struct lancer_cmd_req_write_object))
2081                                 & 0xFFFFFFFF);
2082         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2083                                 sizeof(struct lancer_cmd_req_write_object)));
2084
2085         be_mcc_notify(adapter);
2086         spin_unlock_bh(&adapter->mcc_lock);
2087
2088         if (!wait_for_completion_timeout(&adapter->flash_compl,
2089                                          msecs_to_jiffies(30000)))
2090                 status = -1;
2091         else
2092                 status = adapter->flash_status;
2093
2094         resp = embedded_payload(wrb);
2095         if (!status) {
2096                 *data_written = le32_to_cpu(resp->actual_write_len);
2097                 *change_status = resp->change_status;
2098         } else {
2099                 *addn_status = resp->additional_status;
2100         }
2101
2102         return status;
2103
2104 err_unlock:
2105         spin_unlock_bh(&adapter->mcc_lock);
2106         return status;
2107 }
2108
2109 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2110                 u32 data_size, u32 data_offset, const char *obj_name,
2111                 u32 *data_read, u32 *eof, u8 *addn_status)
2112 {
2113         struct be_mcc_wrb *wrb;
2114         struct lancer_cmd_req_read_object *req;
2115         struct lancer_cmd_resp_read_object *resp;
2116         int status;
2117
2118         spin_lock_bh(&adapter->mcc_lock);
2119
2120         wrb = wrb_from_mccq(adapter);
2121         if (!wrb) {
2122                 status = -EBUSY;
2123                 goto err_unlock;
2124         }
2125
2126         req = embedded_payload(wrb);
2127
2128         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2129                         OPCODE_COMMON_READ_OBJECT,
2130                         sizeof(struct lancer_cmd_req_read_object), wrb,
2131                         NULL);
2132
2133         req->desired_read_len = cpu_to_le32(data_size);
2134         req->read_offset = cpu_to_le32(data_offset);
2135         strcpy(req->object_name, obj_name);
2136         req->descriptor_count = cpu_to_le32(1);
2137         req->buf_len = cpu_to_le32(data_size);
2138         req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2139         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2140
2141         status = be_mcc_notify_wait(adapter);
2142
2143         resp = embedded_payload(wrb);
2144         if (!status) {
2145                 *data_read = le32_to_cpu(resp->actual_read_len);
2146                 *eof = le32_to_cpu(resp->eof);
2147         } else {
2148                 *addn_status = resp->additional_status;
2149         }
2150
2151 err_unlock:
2152         spin_unlock_bh(&adapter->mcc_lock);
2153         return status;
2154 }
2155
2156 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
2157                         u32 flash_type, u32 flash_opcode, u32 buf_size)
2158 {
2159         struct be_mcc_wrb *wrb;
2160         struct be_cmd_write_flashrom *req;
2161         int status;
2162
2163         spin_lock_bh(&adapter->mcc_lock);
2164         adapter->flash_status = 0;
2165
2166         wrb = wrb_from_mccq(adapter);
2167         if (!wrb) {
2168                 status = -EBUSY;
2169                 goto err_unlock;
2170         }
2171         req = cmd->va;
2172
2173         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2174                 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd);
2175
2176         req->params.op_type = cpu_to_le32(flash_type);
2177         req->params.op_code = cpu_to_le32(flash_opcode);
2178         req->params.data_buf_size = cpu_to_le32(buf_size);
2179
2180         be_mcc_notify(adapter);
2181         spin_unlock_bh(&adapter->mcc_lock);
2182
2183         if (!wait_for_completion_timeout(&adapter->flash_compl,
2184                         msecs_to_jiffies(40000)))
2185                 status = -1;
2186         else
2187                 status = adapter->flash_status;
2188
2189         return status;
2190
2191 err_unlock:
2192         spin_unlock_bh(&adapter->mcc_lock);
2193         return status;
2194 }
2195
2196 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2197                          int offset)
2198 {
2199         struct be_mcc_wrb *wrb;
2200         struct be_cmd_read_flash_crc *req;
2201         int status;
2202
2203         spin_lock_bh(&adapter->mcc_lock);
2204
2205         wrb = wrb_from_mccq(adapter);
2206         if (!wrb) {
2207                 status = -EBUSY;
2208                 goto err;
2209         }
2210         req = embedded_payload(wrb);
2211
2212         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2213                                OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2214                                wrb, NULL);
2215
2216         req->params.op_type = cpu_to_le32(OPTYPE_REDBOOT);
2217         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2218         req->params.offset = cpu_to_le32(offset);
2219         req->params.data_buf_size = cpu_to_le32(0x4);
2220
2221         status = be_mcc_notify_wait(adapter);
2222         if (!status)
2223                 memcpy(flashed_crc, req->crc, 4);
2224
2225 err:
2226         spin_unlock_bh(&adapter->mcc_lock);
2227         return status;
2228 }
2229
2230 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2231                                 struct be_dma_mem *nonemb_cmd)
2232 {
2233         struct be_mcc_wrb *wrb;
2234         struct be_cmd_req_acpi_wol_magic_config *req;
2235         int status;
2236
2237         spin_lock_bh(&adapter->mcc_lock);
2238
2239         wrb = wrb_from_mccq(adapter);
2240         if (!wrb) {
2241                 status = -EBUSY;
2242                 goto err;
2243         }
2244         req = nonemb_cmd->va;
2245
2246         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2247                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb,
2248                 nonemb_cmd);
2249         memcpy(req->magic_mac, mac, ETH_ALEN);
2250
2251         status = be_mcc_notify_wait(adapter);
2252
2253 err:
2254         spin_unlock_bh(&adapter->mcc_lock);
2255         return status;
2256 }
2257
2258 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2259                         u8 loopback_type, u8 enable)
2260 {
2261         struct be_mcc_wrb *wrb;
2262         struct be_cmd_req_set_lmode *req;
2263         int status;
2264
2265         spin_lock_bh(&adapter->mcc_lock);
2266
2267         wrb = wrb_from_mccq(adapter);
2268         if (!wrb) {
2269                 status = -EBUSY;
2270                 goto err;
2271         }
2272
2273         req = embedded_payload(wrb);
2274
2275         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2276                         OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb,
2277                         NULL);
2278
2279         req->src_port = port_num;
2280         req->dest_port = port_num;
2281         req->loopback_type = loopback_type;
2282         req->loopback_state = enable;
2283
2284         status = be_mcc_notify_wait(adapter);
2285 err:
2286         spin_unlock_bh(&adapter->mcc_lock);
2287         return status;
2288 }
2289
2290 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2291                 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
2292 {
2293         struct be_mcc_wrb *wrb;
2294         struct be_cmd_req_loopback_test *req;
2295         int status;
2296
2297         spin_lock_bh(&adapter->mcc_lock);
2298
2299         wrb = wrb_from_mccq(adapter);
2300         if (!wrb) {
2301                 status = -EBUSY;
2302                 goto err;
2303         }
2304
2305         req = embedded_payload(wrb);
2306
2307         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2308                         OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL);
2309         req->hdr.timeout = cpu_to_le32(4);
2310
2311         req->pattern = cpu_to_le64(pattern);
2312         req->src_port = cpu_to_le32(port_num);
2313         req->dest_port = cpu_to_le32(port_num);
2314         req->pkt_size = cpu_to_le32(pkt_size);
2315         req->num_pkts = cpu_to_le32(num_pkts);
2316         req->loopback_type = cpu_to_le32(loopback_type);
2317
2318         status = be_mcc_notify_wait(adapter);
2319         if (!status) {
2320                 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
2321                 status = le32_to_cpu(resp->status);
2322         }
2323
2324 err:
2325         spin_unlock_bh(&adapter->mcc_lock);
2326         return status;
2327 }
2328
2329 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2330                                 u32 byte_cnt, struct be_dma_mem *cmd)
2331 {
2332         struct be_mcc_wrb *wrb;
2333         struct be_cmd_req_ddrdma_test *req;
2334         int status;
2335         int i, j = 0;
2336
2337         spin_lock_bh(&adapter->mcc_lock);
2338
2339         wrb = wrb_from_mccq(adapter);
2340         if (!wrb) {
2341                 status = -EBUSY;
2342                 goto err;
2343         }
2344         req = cmd->va;
2345         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2346                         OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd);
2347
2348         req->pattern = cpu_to_le64(pattern);
2349         req->byte_count = cpu_to_le32(byte_cnt);
2350         for (i = 0; i < byte_cnt; i++) {
2351                 req->snd_buff[i] = (u8)(pattern >> (j*8));
2352                 j++;
2353                 if (j > 7)
2354                         j = 0;
2355         }
2356
2357         status = be_mcc_notify_wait(adapter);
2358
2359         if (!status) {
2360                 struct be_cmd_resp_ddrdma_test *resp;
2361                 resp = cmd->va;
2362                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2363                                 resp->snd_err) {
2364                         status = -1;
2365                 }
2366         }
2367
2368 err:
2369         spin_unlock_bh(&adapter->mcc_lock);
2370         return status;
2371 }
2372
2373 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2374                                 struct be_dma_mem *nonemb_cmd)
2375 {
2376         struct be_mcc_wrb *wrb;
2377         struct be_cmd_req_seeprom_read *req;
2378         struct be_sge *sge;
2379         int status;
2380
2381         spin_lock_bh(&adapter->mcc_lock);
2382
2383         wrb = wrb_from_mccq(adapter);
2384         if (!wrb) {
2385                 status = -EBUSY;
2386                 goto err;
2387         }
2388         req = nonemb_cmd->va;
2389         sge = nonembedded_sgl(wrb);
2390
2391         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2392                         OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2393                         nonemb_cmd);
2394
2395         status = be_mcc_notify_wait(adapter);
2396
2397 err:
2398         spin_unlock_bh(&adapter->mcc_lock);
2399         return status;
2400 }
2401
2402 int be_cmd_get_phy_info(struct be_adapter *adapter)
2403 {
2404         struct be_mcc_wrb *wrb;
2405         struct be_cmd_req_get_phy_info *req;
2406         struct be_dma_mem cmd;
2407         int status;
2408
2409         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
2410                             CMD_SUBSYSTEM_COMMON))
2411                 return -EPERM;
2412
2413         spin_lock_bh(&adapter->mcc_lock);
2414
2415         wrb = wrb_from_mccq(adapter);
2416         if (!wrb) {
2417                 status = -EBUSY;
2418                 goto err;
2419         }
2420         cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2421         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2422                                         &cmd.dma);
2423         if (!cmd.va) {
2424                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2425                 status = -ENOMEM;
2426                 goto err;
2427         }
2428
2429         req = cmd.va;
2430
2431         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2432                         OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2433                         wrb, &cmd);
2434
2435         status = be_mcc_notify_wait(adapter);
2436         if (!status) {
2437                 struct be_phy_info *resp_phy_info =
2438                                 cmd.va + sizeof(struct be_cmd_req_hdr);
2439                 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2440                 adapter->phy.interface_type =
2441                         le16_to_cpu(resp_phy_info->interface_type);
2442                 adapter->phy.auto_speeds_supported =
2443                         le16_to_cpu(resp_phy_info->auto_speeds_supported);
2444                 adapter->phy.fixed_speeds_supported =
2445                         le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2446                 adapter->phy.misc_params =
2447                         le32_to_cpu(resp_phy_info->misc_params);
2448         }
2449         pci_free_consistent(adapter->pdev, cmd.size,
2450                                 cmd.va, cmd.dma);
2451 err:
2452         spin_unlock_bh(&adapter->mcc_lock);
2453         return status;
2454 }
2455
2456 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2457 {
2458         struct be_mcc_wrb *wrb;
2459         struct be_cmd_req_set_qos *req;
2460         int status;
2461
2462         spin_lock_bh(&adapter->mcc_lock);
2463
2464         wrb = wrb_from_mccq(adapter);
2465         if (!wrb) {
2466                 status = -EBUSY;
2467                 goto err;
2468         }
2469
2470         req = embedded_payload(wrb);
2471
2472         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2473                         OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
2474
2475         req->hdr.domain = domain;
2476         req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2477         req->max_bps_nic = cpu_to_le32(bps);
2478
2479         status = be_mcc_notify_wait(adapter);
2480
2481 err:
2482         spin_unlock_bh(&adapter->mcc_lock);
2483         return status;
2484 }
2485
2486 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2487 {
2488         struct be_mcc_wrb *wrb;
2489         struct be_cmd_req_cntl_attribs *req;
2490         struct be_cmd_resp_cntl_attribs *resp;
2491         int status;
2492         int payload_len = max(sizeof(*req), sizeof(*resp));
2493         struct mgmt_controller_attrib *attribs;
2494         struct be_dma_mem attribs_cmd;
2495
2496         if (mutex_lock_interruptible(&adapter->mbox_lock))
2497                 return -1;
2498
2499         memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2500         attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2501         attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2502                                                 &attribs_cmd.dma);
2503         if (!attribs_cmd.va) {
2504                 dev_err(&adapter->pdev->dev,
2505                                 "Memory allocation failure\n");
2506                 status = -ENOMEM;
2507                 goto err;
2508         }
2509
2510         wrb = wrb_from_mbox(adapter);
2511         if (!wrb) {
2512                 status = -EBUSY;
2513                 goto err;
2514         }
2515         req = attribs_cmd.va;
2516
2517         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2518                          OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb,
2519                         &attribs_cmd);
2520
2521         status = be_mbox_notify_wait(adapter);
2522         if (!status) {
2523                 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
2524                 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2525         }
2526
2527 err:
2528         mutex_unlock(&adapter->mbox_lock);
2529         if (attribs_cmd.va)
2530                 pci_free_consistent(adapter->pdev, attribs_cmd.size,
2531                                     attribs_cmd.va, attribs_cmd.dma);
2532         return status;
2533 }
2534
2535 /* Uses mbox */
2536 int be_cmd_req_native_mode(struct be_adapter *adapter)
2537 {
2538         struct be_mcc_wrb *wrb;
2539         struct be_cmd_req_set_func_cap *req;
2540         int status;
2541
2542         if (mutex_lock_interruptible(&adapter->mbox_lock))
2543                 return -1;
2544
2545         wrb = wrb_from_mbox(adapter);
2546         if (!wrb) {
2547                 status = -EBUSY;
2548                 goto err;
2549         }
2550
2551         req = embedded_payload(wrb);
2552
2553         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2554                 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL);
2555
2556         req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2557                                 CAPABILITY_BE3_NATIVE_ERX_API);
2558         req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2559
2560         status = be_mbox_notify_wait(adapter);
2561         if (!status) {
2562                 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2563                 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2564                                         CAPABILITY_BE3_NATIVE_ERX_API;
2565                 if (!adapter->be3_native)
2566                         dev_warn(&adapter->pdev->dev,
2567                                  "adapter not in advanced mode\n");
2568         }
2569 err:
2570         mutex_unlock(&adapter->mbox_lock);
2571         return status;
2572 }
2573
2574 /* Get privilege(s) for a function */
2575 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2576                              u32 domain)
2577 {
2578         struct be_mcc_wrb *wrb;
2579         struct be_cmd_req_get_fn_privileges *req;
2580         int status;
2581
2582         spin_lock_bh(&adapter->mcc_lock);
2583
2584         wrb = wrb_from_mccq(adapter);
2585         if (!wrb) {
2586                 status = -EBUSY;
2587                 goto err;
2588         }
2589
2590         req = embedded_payload(wrb);
2591
2592         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2593                                OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
2594                                wrb, NULL);
2595
2596         req->hdr.domain = domain;
2597
2598         status = be_mcc_notify_wait(adapter);
2599         if (!status) {
2600                 struct be_cmd_resp_get_fn_privileges *resp =
2601                                                 embedded_payload(wrb);
2602                 *privilege = le32_to_cpu(resp->privilege_mask);
2603         }
2604
2605 err:
2606         spin_unlock_bh(&adapter->mcc_lock);
2607         return status;
2608 }
2609
2610 /* Uses synchronous MCCQ */
2611 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
2612                              bool *pmac_id_active, u32 *pmac_id, u8 domain)
2613 {
2614         struct be_mcc_wrb *wrb;
2615         struct be_cmd_req_get_mac_list *req;
2616         int status;
2617         int mac_count;
2618         struct be_dma_mem get_mac_list_cmd;
2619         int i;
2620
2621         memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
2622         get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
2623         get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev,
2624                         get_mac_list_cmd.size,
2625                         &get_mac_list_cmd.dma);
2626
2627         if (!get_mac_list_cmd.va) {
2628                 dev_err(&adapter->pdev->dev,
2629                                 "Memory allocation failure during GET_MAC_LIST\n");
2630                 return -ENOMEM;
2631         }
2632
2633         spin_lock_bh(&adapter->mcc_lock);
2634
2635         wrb = wrb_from_mccq(adapter);
2636         if (!wrb) {
2637                 status = -EBUSY;
2638                 goto out;
2639         }
2640
2641         req = get_mac_list_cmd.va;
2642
2643         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2644                                 OPCODE_COMMON_GET_MAC_LIST, sizeof(*req),
2645                                 wrb, &get_mac_list_cmd);
2646
2647         req->hdr.domain = domain;
2648         req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
2649         req->perm_override = 1;
2650
2651         status = be_mcc_notify_wait(adapter);
2652         if (!status) {
2653                 struct be_cmd_resp_get_mac_list *resp =
2654                                                 get_mac_list_cmd.va;
2655                 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
2656                 /* Mac list returned could contain one or more active mac_ids
2657                  * or one or more true or pseudo permanant mac addresses.
2658                  * If an active mac_id is present, return first active mac_id
2659                  * found.
2660                  */
2661                 for (i = 0; i < mac_count; i++) {
2662                         struct get_list_macaddr *mac_entry;
2663                         u16 mac_addr_size;
2664                         u32 mac_id;
2665
2666                         mac_entry = &resp->macaddr_list[i];
2667                         mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
2668                         /* mac_id is a 32 bit value and mac_addr size
2669                          * is 6 bytes
2670                          */
2671                         if (mac_addr_size == sizeof(u32)) {
2672                                 *pmac_id_active = true;
2673                                 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
2674                                 *pmac_id = le32_to_cpu(mac_id);
2675                                 goto out;
2676                         }
2677                 }
2678                 /* If no active mac_id found, return first mac addr */
2679                 *pmac_id_active = false;
2680                 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
2681                                                                 ETH_ALEN);
2682         }
2683
2684 out:
2685         spin_unlock_bh(&adapter->mcc_lock);
2686         pci_free_consistent(adapter->pdev, get_mac_list_cmd.size,
2687                         get_mac_list_cmd.va, get_mac_list_cmd.dma);
2688         return status;
2689 }
2690
2691 /* Uses synchronous MCCQ */
2692 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
2693                         u8 mac_count, u32 domain)
2694 {
2695         struct be_mcc_wrb *wrb;
2696         struct be_cmd_req_set_mac_list *req;
2697         int status;
2698         struct be_dma_mem cmd;
2699
2700         memset(&cmd, 0, sizeof(struct be_dma_mem));
2701         cmd.size = sizeof(struct be_cmd_req_set_mac_list);
2702         cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
2703                         &cmd.dma, GFP_KERNEL);
2704         if (!cmd.va) {
2705                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2706                 return -ENOMEM;
2707         }
2708
2709         spin_lock_bh(&adapter->mcc_lock);
2710
2711         wrb = wrb_from_mccq(adapter);
2712         if (!wrb) {
2713                 status = -EBUSY;
2714                 goto err;
2715         }
2716
2717         req = cmd.va;
2718         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2719                                 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
2720                                 wrb, &cmd);
2721
2722         req->hdr.domain = domain;
2723         req->mac_count = mac_count;
2724         if (mac_count)
2725                 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
2726
2727         status = be_mcc_notify_wait(adapter);
2728
2729 err:
2730         dma_free_coherent(&adapter->pdev->dev, cmd.size,
2731                                 cmd.va, cmd.dma);
2732         spin_unlock_bh(&adapter->mcc_lock);
2733         return status;
2734 }
2735
2736 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
2737                         u32 domain, u16 intf_id)
2738 {
2739         struct be_mcc_wrb *wrb;
2740         struct be_cmd_req_set_hsw_config *req;
2741         void *ctxt;
2742         int status;
2743
2744         spin_lock_bh(&adapter->mcc_lock);
2745
2746         wrb = wrb_from_mccq(adapter);
2747         if (!wrb) {
2748                 status = -EBUSY;
2749                 goto err;
2750         }
2751
2752         req = embedded_payload(wrb);
2753         ctxt = &req->context;
2754
2755         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2756                         OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2757
2758         req->hdr.domain = domain;
2759         AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
2760         if (pvid) {
2761                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
2762                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
2763         }
2764
2765         be_dws_cpu_to_le(req->context, sizeof(req->context));
2766         status = be_mcc_notify_wait(adapter);
2767
2768 err:
2769         spin_unlock_bh(&adapter->mcc_lock);
2770         return status;
2771 }
2772
2773 /* Get Hyper switch config */
2774 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
2775                         u32 domain, u16 intf_id)
2776 {
2777         struct be_mcc_wrb *wrb;
2778         struct be_cmd_req_get_hsw_config *req;
2779         void *ctxt;
2780         int status;
2781         u16 vid;
2782
2783         spin_lock_bh(&adapter->mcc_lock);
2784
2785         wrb = wrb_from_mccq(adapter);
2786         if (!wrb) {
2787                 status = -EBUSY;
2788                 goto err;
2789         }
2790
2791         req = embedded_payload(wrb);
2792         ctxt = &req->context;
2793
2794         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2795                         OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2796
2797         req->hdr.domain = domain;
2798         AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id, ctxt,
2799                                                                 intf_id);
2800         AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
2801         be_dws_cpu_to_le(req->context, sizeof(req->context));
2802
2803         status = be_mcc_notify_wait(adapter);
2804         if (!status) {
2805                 struct be_cmd_resp_get_hsw_config *resp =
2806                                                 embedded_payload(wrb);
2807                 be_dws_le_to_cpu(&resp->context,
2808                                                 sizeof(resp->context));
2809                 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
2810                                                         pvid, &resp->context);
2811                 *pvid = le16_to_cpu(vid);
2812         }
2813
2814 err:
2815         spin_unlock_bh(&adapter->mcc_lock);
2816         return status;
2817 }
2818
2819 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
2820 {
2821         struct be_mcc_wrb *wrb;
2822         struct be_cmd_req_acpi_wol_magic_config_v1 *req;
2823         int status;
2824         int payload_len = sizeof(*req);
2825         struct be_dma_mem cmd;
2826
2827         if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
2828                             CMD_SUBSYSTEM_ETH))
2829                 return -EPERM;
2830
2831         if (mutex_lock_interruptible(&adapter->mbox_lock))
2832                 return -1;
2833
2834         memset(&cmd, 0, sizeof(struct be_dma_mem));
2835         cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
2836         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2837                                                &cmd.dma);
2838         if (!cmd.va) {
2839                 dev_err(&adapter->pdev->dev,
2840                                 "Memory allocation failure\n");
2841                 status = -ENOMEM;
2842                 goto err;
2843         }
2844
2845         wrb = wrb_from_mbox(adapter);
2846         if (!wrb) {
2847                 status = -EBUSY;
2848                 goto err;
2849         }
2850
2851         req = cmd.va;
2852
2853         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2854                                OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
2855                                payload_len, wrb, &cmd);
2856
2857         req->hdr.version = 1;
2858         req->query_options = BE_GET_WOL_CAP;
2859
2860         status = be_mbox_notify_wait(adapter);
2861         if (!status) {
2862                 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
2863                 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *) cmd.va;
2864
2865                 /* the command could succeed misleadingly on old f/w
2866                  * which is not aware of the V1 version. fake an error. */
2867                 if (resp->hdr.response_length < payload_len) {
2868                         status = -1;
2869                         goto err;
2870                 }
2871                 adapter->wol_cap = resp->wol_settings;
2872         }
2873 err:
2874         mutex_unlock(&adapter->mbox_lock);
2875         if (cmd.va)
2876                 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
2877         return status;
2878
2879 }
2880 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
2881                                    struct be_dma_mem *cmd)
2882 {
2883         struct be_mcc_wrb *wrb;
2884         struct be_cmd_req_get_ext_fat_caps *req;
2885         int status;
2886
2887         if (mutex_lock_interruptible(&adapter->mbox_lock))
2888                 return -1;
2889
2890         wrb = wrb_from_mbox(adapter);
2891         if (!wrb) {
2892                 status = -EBUSY;
2893                 goto err;
2894         }
2895
2896         req = cmd->va;
2897         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2898                                OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
2899                                cmd->size, wrb, cmd);
2900         req->parameter_type = cpu_to_le32(1);
2901
2902         status = be_mbox_notify_wait(adapter);
2903 err:
2904         mutex_unlock(&adapter->mbox_lock);
2905         return status;
2906 }
2907
2908 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
2909                                    struct be_dma_mem *cmd,
2910                                    struct be_fat_conf_params *configs)
2911 {
2912         struct be_mcc_wrb *wrb;
2913         struct be_cmd_req_set_ext_fat_caps *req;
2914         int status;
2915
2916         spin_lock_bh(&adapter->mcc_lock);
2917
2918         wrb = wrb_from_mccq(adapter);
2919         if (!wrb) {
2920                 status = -EBUSY;
2921                 goto err;
2922         }
2923
2924         req = cmd->va;
2925         memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
2926         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2927                                OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
2928                                cmd->size, wrb, cmd);
2929
2930         status = be_mcc_notify_wait(adapter);
2931 err:
2932         spin_unlock_bh(&adapter->mcc_lock);
2933         return status;
2934 }
2935
2936 int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name)
2937 {
2938         struct be_mcc_wrb *wrb;
2939         struct be_cmd_req_get_port_name *req;
2940         int status;
2941
2942         if (!lancer_chip(adapter)) {
2943                 *port_name = adapter->hba_port_num + '0';
2944                 return 0;
2945         }
2946
2947         spin_lock_bh(&adapter->mcc_lock);
2948
2949         wrb = wrb_from_mccq(adapter);
2950         if (!wrb) {
2951                 status = -EBUSY;
2952                 goto err;
2953         }
2954
2955         req = embedded_payload(wrb);
2956
2957         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2958                                OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
2959                                NULL);
2960         req->hdr.version = 1;
2961
2962         status = be_mcc_notify_wait(adapter);
2963         if (!status) {
2964                 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
2965                 *port_name = resp->port_name[adapter->hba_port_num];
2966         } else {
2967                 *port_name = adapter->hba_port_num + '0';
2968         }
2969 err:
2970         spin_unlock_bh(&adapter->mcc_lock);
2971         return status;
2972 }
2973
2974 static struct be_nic_resource_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
2975                                                     u32 max_buf_size)
2976 {
2977         struct be_nic_resource_desc *desc = (struct be_nic_resource_desc *)buf;
2978         int i;
2979
2980         for (i = 0; i < desc_count; i++) {
2981                 desc->desc_len = RESOURCE_DESC_SIZE;
2982                 if (((void *)desc + desc->desc_len) >
2983                     (void *)(buf + max_buf_size)) {
2984                         desc = NULL;
2985                         break;
2986                 }
2987
2988                 if (desc->desc_type == NIC_RESOURCE_DESC_TYPE_ID)
2989                         break;
2990
2991                 desc = (void *)desc + desc->desc_len;
2992         }
2993
2994         if (!desc || i == MAX_RESOURCE_DESC)
2995                 return NULL;
2996
2997         return desc;
2998 }
2999
3000 /* Uses Mbox */
3001 int be_cmd_get_func_config(struct be_adapter *adapter)
3002 {
3003         struct be_mcc_wrb *wrb;
3004         struct be_cmd_req_get_func_config *req;
3005         int status;
3006         struct be_dma_mem cmd;
3007
3008         if (mutex_lock_interruptible(&adapter->mbox_lock))
3009                 return -1;
3010
3011         memset(&cmd, 0, sizeof(struct be_dma_mem));
3012         cmd.size = sizeof(struct be_cmd_resp_get_func_config);
3013         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
3014                                       &cmd.dma);
3015         if (!cmd.va) {
3016                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3017                 status = -ENOMEM;
3018                 goto err;
3019         }
3020
3021         wrb = wrb_from_mbox(adapter);
3022         if (!wrb) {
3023                 status = -EBUSY;
3024                 goto err;
3025         }
3026
3027         req = cmd.va;
3028
3029         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3030                                OPCODE_COMMON_GET_FUNC_CONFIG,
3031                                cmd.size, wrb, &cmd);
3032
3033         status = be_mbox_notify_wait(adapter);
3034         if (!status) {
3035                 struct be_cmd_resp_get_func_config *resp = cmd.va;
3036                 u32 desc_count = le32_to_cpu(resp->desc_count);
3037                 struct be_nic_resource_desc *desc;
3038
3039                 desc = be_get_nic_desc(resp->func_param, desc_count,
3040                                        sizeof(resp->func_param));
3041                 if (!desc) {
3042                         status = -EINVAL;
3043                         goto err;
3044                 }
3045
3046                 adapter->pf_number = desc->pf_num;
3047                 adapter->max_pmac_cnt = le16_to_cpu(desc->unicast_mac_count);
3048                 adapter->max_vlans = le16_to_cpu(desc->vlan_count);
3049                 adapter->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
3050                 adapter->max_tx_queues = le16_to_cpu(desc->txq_count);
3051                 adapter->max_rss_queues = le16_to_cpu(desc->rssq_count);
3052                 adapter->max_rx_queues = le16_to_cpu(desc->rq_count);
3053
3054                 adapter->max_event_queues = le16_to_cpu(desc->eq_count);
3055                 adapter->if_cap_flags = le32_to_cpu(desc->cap_flags);
3056         }
3057 err:
3058         mutex_unlock(&adapter->mbox_lock);
3059         if (cmd.va)
3060                 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
3061         return status;
3062 }
3063
3064  /* Uses sync mcc */
3065 int be_cmd_get_profile_config(struct be_adapter *adapter, u32 *cap_flags,
3066                               u8 domain)
3067 {
3068         struct be_mcc_wrb *wrb;
3069         struct be_cmd_req_get_profile_config *req;
3070         int status;
3071         struct be_dma_mem cmd;
3072
3073         memset(&cmd, 0, sizeof(struct be_dma_mem));
3074         cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
3075         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
3076                                       &cmd.dma);
3077         if (!cmd.va) {
3078                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3079                 return -ENOMEM;
3080         }
3081
3082         spin_lock_bh(&adapter->mcc_lock);
3083
3084         wrb = wrb_from_mccq(adapter);
3085         if (!wrb) {
3086                 status = -EBUSY;
3087                 goto err;
3088         }
3089
3090         req = cmd.va;
3091
3092         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3093                                OPCODE_COMMON_GET_PROFILE_CONFIG,
3094                                cmd.size, wrb, &cmd);
3095
3096         req->type = ACTIVE_PROFILE_TYPE;
3097         req->hdr.domain = domain;
3098
3099         status = be_mcc_notify_wait(adapter);
3100         if (!status) {
3101                 struct be_cmd_resp_get_profile_config *resp = cmd.va;
3102                 u32 desc_count = le32_to_cpu(resp->desc_count);
3103                 struct be_nic_resource_desc *desc;
3104
3105                 desc = be_get_nic_desc(resp->func_param, desc_count,
3106                                        sizeof(resp->func_param));
3107
3108                 if (!desc) {
3109                         status = -EINVAL;
3110                         goto err;
3111                 }
3112                 *cap_flags = le32_to_cpu(desc->cap_flags);
3113         }
3114 err:
3115         spin_unlock_bh(&adapter->mcc_lock);
3116         pci_free_consistent(adapter->pdev, cmd.size,
3117                             cmd.va, cmd.dma);
3118         return status;
3119 }
3120
3121 /* Uses sync mcc */
3122 int be_cmd_set_profile_config(struct be_adapter *adapter, u32 bps,
3123                               u8 domain)
3124 {
3125         struct be_mcc_wrb *wrb;
3126         struct be_cmd_req_set_profile_config *req;
3127         int status;
3128
3129         spin_lock_bh(&adapter->mcc_lock);
3130
3131         wrb = wrb_from_mccq(adapter);
3132         if (!wrb) {
3133                 status = -EBUSY;
3134                 goto err;
3135         }
3136
3137         req = embedded_payload(wrb);
3138
3139         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3140                                OPCODE_COMMON_SET_PROFILE_CONFIG, sizeof(*req),
3141                                wrb, NULL);
3142
3143         req->hdr.domain = domain;
3144         req->desc_count = cpu_to_le32(1);
3145
3146         req->nic_desc.desc_type = NIC_RESOURCE_DESC_TYPE_ID;
3147         req->nic_desc.desc_len = RESOURCE_DESC_SIZE;
3148         req->nic_desc.flags = (1 << QUN) | (1 << IMM) | (1 << NOSV);
3149         req->nic_desc.pf_num = adapter->pf_number;
3150         req->nic_desc.vf_num = domain;
3151
3152         /* Mark fields invalid */
3153         req->nic_desc.unicast_mac_count = 0xFFFF;
3154         req->nic_desc.mcc_count = 0xFFFF;
3155         req->nic_desc.vlan_count = 0xFFFF;
3156         req->nic_desc.mcast_mac_count = 0xFFFF;
3157         req->nic_desc.txq_count = 0xFFFF;
3158         req->nic_desc.rq_count = 0xFFFF;
3159         req->nic_desc.rssq_count = 0xFFFF;
3160         req->nic_desc.lro_count = 0xFFFF;
3161         req->nic_desc.cq_count = 0xFFFF;
3162         req->nic_desc.toe_conn_count = 0xFFFF;
3163         req->nic_desc.eq_count = 0xFFFF;
3164         req->nic_desc.link_param = 0xFF;
3165         req->nic_desc.bw_min = 0xFFFFFFFF;
3166         req->nic_desc.acpi_params = 0xFF;
3167         req->nic_desc.wol_param = 0x0F;
3168
3169         /* Change BW */
3170         req->nic_desc.bw_min = cpu_to_le32(bps);
3171         req->nic_desc.bw_max = cpu_to_le32(bps);
3172         status = be_mcc_notify_wait(adapter);
3173 err:
3174         spin_unlock_bh(&adapter->mcc_lock);
3175         return status;
3176 }
3177
3178 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
3179                      int vf_num)
3180 {
3181         struct be_mcc_wrb *wrb;
3182         struct be_cmd_req_get_iface_list *req;
3183         struct be_cmd_resp_get_iface_list *resp;
3184         int status;
3185
3186         spin_lock_bh(&adapter->mcc_lock);
3187
3188         wrb = wrb_from_mccq(adapter);
3189         if (!wrb) {
3190                 status = -EBUSY;
3191                 goto err;
3192         }
3193         req = embedded_payload(wrb);
3194
3195         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3196                                OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
3197                                wrb, NULL);
3198         req->hdr.domain = vf_num + 1;
3199
3200         status = be_mcc_notify_wait(adapter);
3201         if (!status) {
3202                 resp = (struct be_cmd_resp_get_iface_list *)req;
3203                 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
3204         }
3205
3206 err:
3207         spin_unlock_bh(&adapter->mcc_lock);
3208         return status;
3209 }
3210
3211 /* Uses sync mcc */
3212 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
3213 {
3214         struct be_mcc_wrb *wrb;
3215         struct be_cmd_enable_disable_vf *req;
3216         int status;
3217
3218         if (!lancer_chip(adapter))
3219                 return 0;
3220
3221         spin_lock_bh(&adapter->mcc_lock);
3222
3223         wrb = wrb_from_mccq(adapter);
3224         if (!wrb) {
3225                 status = -EBUSY;
3226                 goto err;
3227         }
3228
3229         req = embedded_payload(wrb);
3230
3231         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3232                                OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
3233                                wrb, NULL);
3234
3235         req->hdr.domain = domain;
3236         req->enable = 1;
3237         status = be_mcc_notify_wait(adapter);
3238 err:
3239         spin_unlock_bh(&adapter->mcc_lock);
3240         return status;
3241 }
3242
3243 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
3244                         int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
3245 {
3246         struct be_adapter *adapter = netdev_priv(netdev_handle);
3247         struct be_mcc_wrb *wrb;
3248         struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *) wrb_payload;
3249         struct be_cmd_req_hdr *req;
3250         struct be_cmd_resp_hdr *resp;
3251         int status;
3252
3253         spin_lock_bh(&adapter->mcc_lock);
3254
3255         wrb = wrb_from_mccq(adapter);
3256         if (!wrb) {
3257                 status = -EBUSY;
3258                 goto err;
3259         }
3260         req = embedded_payload(wrb);
3261         resp = embedded_payload(wrb);
3262
3263         be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
3264                                hdr->opcode, wrb_payload_size, wrb, NULL);
3265         memcpy(req, wrb_payload, wrb_payload_size);
3266         be_dws_cpu_to_le(req, wrb_payload_size);
3267
3268         status = be_mcc_notify_wait(adapter);
3269         if (cmd_status)
3270                 *cmd_status = (status & 0xffff);
3271         if (ext_status)
3272                 *ext_status = 0;
3273         memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
3274         be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
3275 err:
3276         spin_unlock_bh(&adapter->mcc_lock);
3277         return status;
3278 }
3279 EXPORT_SYMBOL(be_roce_mcc_cmd);