drivers/net/ethernet/emulex/benet/be_cmds.c

   1 /*
   2  * Copyright (C) 2005 - 2016 Broadcom
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 #include <linux/module.h>
  19 #include "be.h"
  20 #include "be_cmds.h"
  21
  22 char *be_misconfig_evt_port_state[] = {
  23         "Physical Link is functional",
  24         "Optics faulted/incorrectly installed/not installed - Reseat optics. If issue not resolved, replace.",
  25         "Optics of two types installed – Remove one optic or install matching pair of optics.",
  26         "Incompatible optics – Replace with compatible optics for card to function.",
  27         "Unqualified optics – Replace with Avago optics for Warranty and Technical Support.",
  28         "Uncertified optics – Replace with Avago-certified optics to enable link operation."
  29 };
  30
  31 static char *be_port_misconfig_evt_severity[] = {
  32         "KERN_WARN",
  33         "KERN_INFO",
  34         "KERN_ERR",
  35         "KERN_WARN"
  36 };
  37
  38 static char *phy_state_oper_desc[] = {
  39         "Link is non-operational",
  40         "Link is operational",
  41         ""
  42 };
  43
  44 static struct be_cmd_priv_map cmd_priv_map[] = {
  45         {
  46                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
  47                 CMD_SUBSYSTEM_ETH,
  48                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  49                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  50         },
  51         {
  52                 OPCODE_COMMON_GET_FLOW_CONTROL,
  53                 CMD_SUBSYSTEM_COMMON,
  54                 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
  55                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  56         },
  57         {
  58                 OPCODE_COMMON_SET_FLOW_CONTROL,
  59                 CMD_SUBSYSTEM_COMMON,
  60                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  61                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  62         },
  63         {
  64                 OPCODE_ETH_GET_PPORT_STATS,
  65                 CMD_SUBSYSTEM_ETH,
  66                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  67                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  68         },
  69         {
  70                 OPCODE_COMMON_GET_PHY_DETAILS,
  71                 CMD_SUBSYSTEM_COMMON,
  72                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  73                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  74         },
  75         {
  76                 OPCODE_LOWLEVEL_HOST_DDR_DMA,
  77                 CMD_SUBSYSTEM_LOWLEVEL,
  78                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  79         },
  80         {
  81                 OPCODE_LOWLEVEL_LOOPBACK_TEST,
  82                 CMD_SUBSYSTEM_LOWLEVEL,
  83                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  84         },
  85         {
  86                 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
  87                 CMD_SUBSYSTEM_LOWLEVEL,
  88                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  89         },
  90         {
  91                 OPCODE_COMMON_SET_HSW_CONFIG,
  92                 CMD_SUBSYSTEM_COMMON,
  93                 BE_PRIV_DEVCFG | BE_PRIV_VHADM
  94         },
  95         {
  96                 OPCODE_COMMON_GET_EXT_FAT_CAPABILITIES,
  97                 CMD_SUBSYSTEM_COMMON,
  98                 BE_PRIV_DEVCFG
  99         }
 100 };
 101
 102 static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, u8 subsystem)
 103 {
 104         int i;
 105         int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
 106         u32 cmd_privileges = adapter->cmd_privileges;
 107
 108         for (i = 0; i < num_entries; i++)
 109                 if (opcode == cmd_priv_map[i].opcode &&
 110                     subsystem == cmd_priv_map[i].subsystem)
 111                         if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
 112                                 return false;
 113
 114         return true;
 115 }
 116
 117 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
 118 {
 119         return wrb->payload.embedded_payload;
 120 }
 121
 122 static int be_mcc_notify(struct be_adapter *adapter)
 123 {
 124         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 125         u32 val = 0;
 126
 127         if (be_check_error(adapter, BE_ERROR_ANY))
 128                 return -EIO;
 129
 130         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
 131         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
 132
 133         wmb();
 134         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
 135
 136         return 0;
 137 }
 138
 139 /* To check if valid bit is set, check the entire word as we don't know
 140  * the endianness of the data (old entry is host endian while a new entry is
 141  * little endian) */
 142 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
 143 {
 144         u32 flags;
 145
 146         if (compl->flags != 0) {
 147                 flags = le32_to_cpu(compl->flags);
 148                 if (flags & CQE_FLAGS_VALID_MASK) {
 149                         compl->flags = flags;
 150                         return true;
 151                 }
 152         }
 153         return false;
 154 }
 155
 156 /* Need to reset the entire word that houses the valid bit */
 157 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
 158 {
 159         compl->flags = 0;
 160 }
 161
 162 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
 163 {
 164         unsigned long addr;
 165
 166         addr = tag1;
 167         addr = ((addr << 16) << 16) | tag0;
 168         return (void *)addr;
 169 }
 170
 171 static bool be_skip_err_log(u8 opcode, u16 base_status, u16 addl_status)
 172 {
 173         if (base_status == MCC_STATUS_NOT_SUPPORTED ||
 174             base_status == MCC_STATUS_ILLEGAL_REQUEST ||
 175             addl_status == MCC_ADDL_STATUS_TOO_MANY_INTERFACES ||
 176             addl_status == MCC_ADDL_STATUS_INSUFFICIENT_VLANS ||
 177             (opcode == OPCODE_COMMON_WRITE_FLASHROM &&
 178             (base_status == MCC_STATUS_ILLEGAL_FIELD ||
 179              addl_status == MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH)))
 180                 return true;
 181         else
 182                 return false;
 183 }
 184
 185 /* Place holder for all the async MCC cmds wherein the caller is not in a busy
 186  * loop (has not issued be_mcc_notify_wait())
 187  */
 188 static void be_async_cmd_process(struct be_adapter *adapter,
 189                                  struct be_mcc_compl *compl,
 190                                  struct be_cmd_resp_hdr *resp_hdr)
 191 {
 192         enum mcc_base_status base_status = base_status(compl->status);
 193         u8 opcode = 0, subsystem = 0;
 194
 195         if (resp_hdr) {
 196                 opcode = resp_hdr->opcode;
 197                 subsystem = resp_hdr->subsystem;
 198         }
 199
 200         if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST &&
 201             subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
 202                 complete(&adapter->et_cmd_compl);
 203                 return;
 204         }
 205
 206         if (opcode == OPCODE_LOWLEVEL_SET_LOOPBACK_MODE &&
 207             subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
 208                 complete(&adapter->et_cmd_compl);
 209                 return;
 210         }
 211
 212         if ((opcode == OPCODE_COMMON_WRITE_FLASHROM ||
 213              opcode == OPCODE_COMMON_WRITE_OBJECT) &&
 214             subsystem == CMD_SUBSYSTEM_COMMON) {
 215                 adapter->flash_status = compl->status;
 216                 complete(&adapter->et_cmd_compl);
 217                 return;
 218         }
 219
 220         if ((opcode == OPCODE_ETH_GET_STATISTICS ||
 221              opcode == OPCODE_ETH_GET_PPORT_STATS) &&
 222             subsystem == CMD_SUBSYSTEM_ETH &&
 223             base_status == MCC_STATUS_SUCCESS) {
 224                 be_parse_stats(adapter);
 225                 adapter->stats_cmd_sent = false;
 226                 return;
 227         }
 228
 229         if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
 230             subsystem == CMD_SUBSYSTEM_COMMON) {
 231                 if (base_status == MCC_STATUS_SUCCESS) {
 232                         struct be_cmd_resp_get_cntl_addnl_attribs *resp =
 233                                                         (void *)resp_hdr;
 234                         adapter->hwmon_info.be_on_die_temp =
 235                                                 resp->on_die_temperature;
 236                 } else {
 237                         adapter->be_get_temp_freq = 0;
 238                         adapter->hwmon_info.be_on_die_temp =
 239                                                 BE_INVALID_DIE_TEMP;
 240                 }
 241                 return;
 242         }
 243 }
 244
 245 static int be_mcc_compl_process(struct be_adapter *adapter,
 246                                 struct be_mcc_compl *compl)
 247 {
 248         enum mcc_base_status base_status;
 249         enum mcc_addl_status addl_status;
 250         struct be_cmd_resp_hdr *resp_hdr;
 251         u8 opcode = 0, subsystem = 0;
 252
 253         /* Just swap the status to host endian; mcc tag is opaquely copied
 254          * from mcc_wrb */
 255         be_dws_le_to_cpu(compl, 4);
 256
 257         base_status = base_status(compl->status);
 258         addl_status = addl_status(compl->status);
 259
 260         resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
 261         if (resp_hdr) {
 262                 opcode = resp_hdr->opcode;
 263                 subsystem = resp_hdr->subsystem;
 264         }
 265
 266         be_async_cmd_process(adapter, compl, resp_hdr);
 267
 268         if (base_status != MCC_STATUS_SUCCESS &&
 269             !be_skip_err_log(opcode, base_status, addl_status)) {
 270                 if (base_status == MCC_STATUS_UNAUTHORIZED_REQUEST ||
 271                     addl_status == MCC_ADDL_STATUS_INSUFFICIENT_PRIVILEGES) {
 272                         dev_warn(&adapter->pdev->dev,
 273                                  "VF is not privileged to issue opcode %d-%d\n",
 274                                  opcode, subsystem);
 275                 } else {
 276                         dev_err(&adapter->pdev->dev,
 277                                 "opcode %d-%d failed:status %d-%d\n",
 278                                 opcode, subsystem, base_status, addl_status);
 279                 }
 280         }
 281         return compl->status;
 282 }
 283
 284 /* Link state evt is a string of bytes; no need for endian swapping */
 285 static void be_async_link_state_process(struct be_adapter *adapter,
 286                                         struct be_mcc_compl *compl)
 287 {
 288         struct be_async_event_link_state *evt =
 289                         (struct be_async_event_link_state *)compl;
 290
 291         /* When link status changes, link speed must be re-queried from FW */
 292         adapter->phy.link_speed = -1;
 293
 294         /* On BEx the FW does not send a separate link status
 295          * notification for physical and logical link.
 296          * On other chips just process the logical link
 297          * status notification
 298          */
 299         if (!BEx_chip(adapter) &&
 300             !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
 301                 return;
 302
 303         /* For the initial link status do not rely on the ASYNC event as
 304          * it may not be received in some cases.
 305          */
 306         if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
 307                 be_link_status_update(adapter,
 308                                       evt->port_link_status & LINK_STATUS_MASK);
 309 }
 310
 311 static void be_async_port_misconfig_event_process(struct be_adapter *adapter,
 312                                                   struct be_mcc_compl *compl)
 313 {
 314         struct be_async_event_misconfig_port *evt =
 315                         (struct be_async_event_misconfig_port *)compl;
 316         u32 sfp_misconfig_evt_word1 = le32_to_cpu(evt->event_data_word1);
 317         u32 sfp_misconfig_evt_word2 = le32_to_cpu(evt->event_data_word2);
 318         u8 phy_oper_state = PHY_STATE_OPER_MSG_NONE;
 319         struct device *dev = &adapter->pdev->dev;
 320         u8 msg_severity = DEFAULT_MSG_SEVERITY;
 321         u8 phy_state_info;
 322         u8 new_phy_state;
 323
 324         new_phy_state =
 325                 (sfp_misconfig_evt_word1 >> (adapter->hba_port_num * 8)) & 0xff;
 326
 327         if (new_phy_state == adapter->phy_state)
 328                 return;
 329
 330         adapter->phy_state = new_phy_state;
 331
 332         /* for older fw that doesn't populate link effect data */
 333         if (!sfp_misconfig_evt_word2)
 334                 goto log_message;
 335
 336         phy_state_info =
 337                 (sfp_misconfig_evt_word2 >> (adapter->hba_port_num * 8)) & 0xff;
 338
 339         if (phy_state_info & PHY_STATE_INFO_VALID) {
 340                 msg_severity = (phy_state_info & PHY_STATE_MSG_SEVERITY) >> 1;
 341
 342                 if (be_phy_unqualified(new_phy_state))
 343                         phy_oper_state = (phy_state_info & PHY_STATE_OPER);
 344         }
 345
 346 log_message:
 347         /* Log an error message that would allow a user to determine
 348          * whether the SFPs have an issue
 349          */
 350         if (be_phy_state_unknown(new_phy_state))
 351                 dev_printk(be_port_misconfig_evt_severity[msg_severity], dev,
 352                            "Port %c: Unrecognized Optics state: 0x%x. %s",
 353                            adapter->port_name,
 354                            new_phy_state,
 355                            phy_state_oper_desc[phy_oper_state]);
 356         else
 357                 dev_printk(be_port_misconfig_evt_severity[msg_severity], dev,
 358                            "Port %c: %s %s",
 359                            adapter->port_name,
 360                            be_misconfig_evt_port_state[new_phy_state],
 361                            phy_state_oper_desc[phy_oper_state]);
 362
 363         /* Log Vendor name and part no. if a misconfigured SFP is detected */
 364         if (be_phy_misconfigured(new_phy_state))
 365                 adapter->flags |= BE_FLAGS_PHY_MISCONFIGURED;
 366 }
 367
 368 /* Grp5 CoS Priority evt */
 369 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
 370                                                struct be_mcc_compl *compl)
 371 {
 372         struct be_async_event_grp5_cos_priority *evt =
 373                         (struct be_async_event_grp5_cos_priority *)compl;
 374
 375         if (evt->valid) {
 376                 adapter->vlan_prio_bmap = evt->available_priority_bmap;
 377                 adapter->recommended_prio_bits =
 378                         evt->reco_default_priority << VLAN_PRIO_SHIFT;
 379         }
 380 }
 381
 382 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
 383 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
 384                                             struct be_mcc_compl *compl)
 385 {
 386         struct be_async_event_grp5_qos_link_speed *evt =
 387                         (struct be_async_event_grp5_qos_link_speed *)compl;
 388
 389         if (adapter->phy.link_speed >= 0 &&
 390             evt->physical_port == adapter->port_num)
 391                 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
 392 }
 393
 394 /*Grp5 PVID evt*/
 395 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
 396                                              struct be_mcc_compl *compl)
 397 {
 398         struct be_async_event_grp5_pvid_state *evt =
 399                         (struct be_async_event_grp5_pvid_state *)compl;
 400
 401         if (evt->enabled) {
 402                 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
 403                 dev_info(&adapter->pdev->dev, "LPVID: %d\n", adapter->pvid);
 404         } else {
 405                 adapter->pvid = 0;
 406         }
 407 }
 408
 409 #define MGMT_ENABLE_MASK        0x4
 410 static void be_async_grp5_fw_control_process(struct be_adapter *adapter,
 411                                              struct be_mcc_compl *compl)
 412 {
 413         struct be_async_fw_control *evt = (struct be_async_fw_control *)compl;
 414         u32 evt_dw1 = le32_to_cpu(evt->event_data_word1);
 415
 416         if (evt_dw1 & MGMT_ENABLE_MASK) {
 417                 adapter->flags |= BE_FLAGS_OS2BMC;
 418                 adapter->bmc_filt_mask = le32_to_cpu(evt->event_data_word2);
 419         } else {
 420                 adapter->flags &= ~BE_FLAGS_OS2BMC;
 421         }
 422 }
 423
 424 static void be_async_grp5_evt_process(struct be_adapter *adapter,
 425                                       struct be_mcc_compl *compl)
 426 {
 427         u8 event_type = (compl->flags >> ASYNC_EVENT_TYPE_SHIFT) &
 428                                 ASYNC_EVENT_TYPE_MASK;
 429
 430         switch (event_type) {
 431         case ASYNC_EVENT_COS_PRIORITY:
 432                 be_async_grp5_cos_priority_process(adapter, compl);
 433                 break;
 434         case ASYNC_EVENT_QOS_SPEED:
 435                 be_async_grp5_qos_speed_process(adapter, compl);
 436                 break;
 437         case ASYNC_EVENT_PVID_STATE:
 438                 be_async_grp5_pvid_state_process(adapter, compl);
 439                 break;
 440         /* Async event to disable/enable os2bmc and/or mac-learning */
 441         case ASYNC_EVENT_FW_CONTROL:
 442                 be_async_grp5_fw_control_process(adapter, compl);
 443                 break;
 444         default:
 445                 break;
 446         }
 447 }
 448
 449 static void be_async_dbg_evt_process(struct be_adapter *adapter,
 450                                      struct be_mcc_compl *cmp)
 451 {
 452         u8 event_type = 0;
 453         struct be_async_event_qnq *evt = (struct be_async_event_qnq *)cmp;
 454
 455         event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
 456                         ASYNC_EVENT_TYPE_MASK;
 457
 458         switch (event_type) {
 459         case ASYNC_DEBUG_EVENT_TYPE_QNQ:
 460                 if (evt->valid)
 461                         adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
 462                 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
 463         break;
 464         default:
 465                 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
 466                          event_type);
 467         break;
 468         }
 469 }
 470
 471 static void be_async_sliport_evt_process(struct be_adapter *adapter,
 472                                          struct be_mcc_compl *cmp)
 473 {
 474         u8 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
 475                         ASYNC_EVENT_TYPE_MASK;
 476
 477         if (event_type == ASYNC_EVENT_PORT_MISCONFIG)
 478                 be_async_port_misconfig_event_process(adapter, cmp);
 479 }
 480
 481 static inline bool is_link_state_evt(u32 flags)
 482 {
 483         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 484                         ASYNC_EVENT_CODE_LINK_STATE;
 485 }
 486
 487 static inline bool is_grp5_evt(u32 flags)
 488 {
 489         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 490                         ASYNC_EVENT_CODE_GRP_5;
 491 }
 492
 493 static inline bool is_dbg_evt(u32 flags)
 494 {
 495         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 496                         ASYNC_EVENT_CODE_QNQ;
 497 }
 498
 499 static inline bool is_sliport_evt(u32 flags)
 500 {
 501         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 502                 ASYNC_EVENT_CODE_SLIPORT;
 503 }
 504
 505 static void be_mcc_event_process(struct be_adapter *adapter,
 506                                  struct be_mcc_compl *compl)
 507 {
 508         if (is_link_state_evt(compl->flags))
 509                 be_async_link_state_process(adapter, compl);
 510         else if (is_grp5_evt(compl->flags))
 511                 be_async_grp5_evt_process(adapter, compl);
 512         else if (is_dbg_evt(compl->flags))
 513                 be_async_dbg_evt_process(adapter, compl);
 514         else if (is_sliport_evt(compl->flags))
 515                 be_async_sliport_evt_process(adapter, compl);
 516 }
 517
 518 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
 519 {
 520         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
 521         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
 522
 523         if (be_mcc_compl_is_new(compl)) {
 524                 queue_tail_inc(mcc_cq);
 525                 return compl;
 526         }
 527         return NULL;
 528 }
 529
 530 void be_async_mcc_enable(struct be_adapter *adapter)
 531 {
 532         spin_lock_bh(&adapter->mcc_cq_lock);
 533
 534         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
 535         adapter->mcc_obj.rearm_cq = true;
 536
 537         spin_unlock_bh(&adapter->mcc_cq_lock);
 538 }
 539
 540 void be_async_mcc_disable(struct be_adapter *adapter)
 541 {
 542         spin_lock_bh(&adapter->mcc_cq_lock);
 543
 544         adapter->mcc_obj.rearm_cq = false;
 545         be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
 546
 547         spin_unlock_bh(&adapter->mcc_cq_lock);
 548 }
 549
 550 int be_process_mcc(struct be_adapter *adapter)
 551 {
 552         struct be_mcc_compl *compl;
 553         int num = 0, status = 0;
 554         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 555
 556         spin_lock(&adapter->mcc_cq_lock);
 557
 558         while ((compl = be_mcc_compl_get(adapter))) {
 559                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 560                         be_mcc_event_process(adapter, compl);
 561                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
 562                         status = be_mcc_compl_process(adapter, compl);
 563                         atomic_dec(&mcc_obj->q.used);
 564                 }
 565                 be_mcc_compl_use(compl);
 566                 num++;
 567         }
 568
 569         if (num)
 570                 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
 571
 572         spin_unlock(&adapter->mcc_cq_lock);
 573         return status;
 574 }
 575
 576 /* Wait till no more pending mcc requests are present */
 577 static int be_mcc_wait_compl(struct be_adapter *adapter)
 578 {
 579 #define mcc_timeout             12000 /* 12s timeout */
 580         int i, status = 0;
 581         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 582
 583         for (i = 0; i < mcc_timeout; i++) {
 584                 if (be_check_error(adapter, BE_ERROR_ANY))
 585                         return -EIO;
 586
 587                 local_bh_disable();
 588                 status = be_process_mcc(adapter);
 589                 local_bh_enable();
 590
 591                 if (atomic_read(&mcc_obj->q.used) == 0)
 592                         break;
 593                 usleep_range(500, 1000);
 594         }
 595         if (i == mcc_timeout) {
 596                 dev_err(&adapter->pdev->dev, "FW not responding\n");
 597                 be_set_error(adapter, BE_ERROR_FW);
 598                 return -EIO;
 599         }
 600         return status;
 601 }
 602
 603 /* Notify MCC requests and wait for completion */
 604 static int be_mcc_notify_wait(struct be_adapter *adapter)
 605 {
 606         int status;
 607         struct be_mcc_wrb *wrb;
 608         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 609         u32 index = mcc_obj->q.head;
 610         struct be_cmd_resp_hdr *resp;
 611
 612         index_dec(&index, mcc_obj->q.len);
 613         wrb = queue_index_node(&mcc_obj->q, index);
 614
 615         resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
 616
 617         status = be_mcc_notify(adapter);
 618         if (status)
 619                 goto out;
 620
 621         status = be_mcc_wait_compl(adapter);
 622         if (status == -EIO)
 623                 goto out;
 624
 625         status = (resp->base_status |
 626                   ((resp->addl_status & CQE_ADDL_STATUS_MASK) <<
 627                    CQE_ADDL_STATUS_SHIFT));
 628 out:
 629         return status;
 630 }
 631
 632 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 633 {
 634         int msecs = 0;
 635         u32 ready;
 636
 637         do {
 638                 if (be_check_error(adapter, BE_ERROR_ANY))
 639                         return -EIO;
 640
 641                 ready = ioread32(db);
 642                 if (ready == 0xffffffff)
 643                         return -1;
 644
 645                 ready &= MPU_MAILBOX_DB_RDY_MASK;
 646                 if (ready)
 647                         break;
 648
 649                 if (msecs > 4000) {
 650                         dev_err(&adapter->pdev->dev, "FW not responding\n");
 651                         be_set_error(adapter, BE_ERROR_FW);
 652                         be_detect_error(adapter);
 653                         return -1;
 654                 }
 655
 656                 msleep(1);
 657                 msecs++;
 658         } while (true);
 659
 660         return 0;
 661 }
 662
 663 /*
 664  * Insert the mailbox address into the doorbell in two steps
 665  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 666  */
 667 static int be_mbox_notify_wait(struct be_adapter *adapter)
 668 {
 669         int status;
 670         u32 val = 0;
 671         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 672         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 673         struct be_mcc_mailbox *mbox = mbox_mem->va;
 674         struct be_mcc_compl *compl = &mbox->compl;
 675
 676         /* wait for ready to be set */
 677         status = be_mbox_db_ready_wait(adapter, db);
 678         if (status != 0)
 679                 return status;
 680
 681         val |= MPU_MAILBOX_DB_HI_MASK;
 682         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 683         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 684         iowrite32(val, db);
 685
 686         /* wait for ready to be set */
 687         status = be_mbox_db_ready_wait(adapter, db);
 688         if (status != 0)
 689                 return status;
 690
 691         val = 0;
 692         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 693         val |= (u32)(mbox_mem->dma >> 4) << 2;
 694         iowrite32(val, db);
 695
 696         status = be_mbox_db_ready_wait(adapter, db);
 697         if (status != 0)
 698                 return status;
 699
 700         /* A cq entry has been made now */
 701         if (be_mcc_compl_is_new(compl)) {
 702                 status = be_mcc_compl_process(adapter, &mbox->compl);
 703                 be_mcc_compl_use(compl);
 704                 if (status)
 705                         return status;
 706         } else {
 707                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 708                 return -1;
 709         }
 710         return 0;
 711 }
 712
 713 u16 be_POST_stage_get(struct be_adapter *adapter)
 714 {
 715         u32 sem;
 716
 717         if (BEx_chip(adapter))
 718                 sem  = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
 719         else
 720                 pci_read_config_dword(adapter->pdev,
 721                                       SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
 722
 723         return sem & POST_STAGE_MASK;
 724 }
 725
 726 static int lancer_wait_ready(struct be_adapter *adapter)
 727 {
 728 #define SLIPORT_READY_TIMEOUT 30
 729         u32 sliport_status;
 730         int i;
 731
 732         for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
 733                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 734                 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
 735                         return 0;
 736
 737                 if (sliport_status & SLIPORT_STATUS_ERR_MASK &&
 738                     !(sliport_status & SLIPORT_STATUS_RN_MASK))
 739                         return -EIO;
 740
 741                 msleep(1000);
 742         }
 743
 744         return sliport_status ? : -1;
 745 }
 746
 747 int be_fw_wait_ready(struct be_adapter *adapter)
 748 {
 749         u16 stage;
 750         int status, timeout = 0;
 751         struct device *dev = &adapter->pdev->dev;
 752
 753         if (lancer_chip(adapter)) {
 754                 status = lancer_wait_ready(adapter);
 755                 if (status) {
 756                         stage = status;
 757                         goto err;
 758                 }
 759                 return 0;
 760         }
 761
 762         do {
 763                 /* There's no means to poll POST state on BE2/3 VFs */
 764                 if (BEx_chip(adapter) && be_virtfn(adapter))
 765                         return 0;
 766
 767                 stage = be_POST_stage_get(adapter);
 768                 if (stage == POST_STAGE_ARMFW_RDY)
 769                         return 0;
 770
 771                 dev_info(dev, "Waiting for POST, %ds elapsed\n", timeout);
 772                 if (msleep_interruptible(2000)) {
 773                         dev_err(dev, "Waiting for POST aborted\n");
 774                         return -EINTR;
 775                 }
 776                 timeout += 2;
 777         } while (timeout < 60);
 778
 779 err:
 780         dev_err(dev, "POST timeout; stage=%#x\n", stage);
 781         return -ETIMEDOUT;
 782 }
 783
 784 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 785 {
 786         return &wrb->payload.sgl[0];
 787 }
 788
 789 static inline void fill_wrb_tags(struct be_mcc_wrb *wrb, unsigned long addr)
 790 {
 791         wrb->tag0 = addr & 0xFFFFFFFF;
 792         wrb->tag1 = upper_32_bits(addr);
 793 }
 794
 795 /* Don't touch the hdr after it's prepared */
 796 /* mem will be NULL for embedded commands */
 797 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 798                                    u8 subsystem, u8 opcode, int cmd_len,
 799                                    struct be_mcc_wrb *wrb,
 800                                    struct be_dma_mem *mem)
 801 {
 802         struct be_sge *sge;
 803
 804         req_hdr->opcode = opcode;
 805         req_hdr->subsystem = subsystem;
 806         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 807         req_hdr->version = 0;
 808         fill_wrb_tags(wrb, (ulong) req_hdr);
 809         wrb->payload_length = cmd_len;
 810         if (mem) {
 811                 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
 812                         MCC_WRB_SGE_CNT_SHIFT;
 813                 sge = nonembedded_sgl(wrb);
 814                 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
 815                 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
 816                 sge->len = cpu_to_le32(mem->size);
 817         } else
 818                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 819         be_dws_cpu_to_le(wrb, 8);
 820 }
 821
 822 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 823                                       struct be_dma_mem *mem)
 824 {
 825         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 826         u64 dma = (u64)mem->dma;
 827
 828         for (i = 0; i < buf_pages; i++) {
 829                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 830                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 831                 dma += PAGE_SIZE_4K;
 832         }
 833 }
 834
 835 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
 836 {
 837         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 838         struct be_mcc_wrb *wrb
 839                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 840         memset(wrb, 0, sizeof(*wrb));
 841         return wrb;
 842 }
 843
 844 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
 845 {
 846         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 847         struct be_mcc_wrb *wrb;
 848
 849         if (!mccq->created)
 850                 return NULL;
 851
 852         if (atomic_read(&mccq->used) >= mccq->len)
 853                 return NULL;
 854
 855         wrb = queue_head_node(mccq);
 856         queue_head_inc(mccq);
 857         atomic_inc(&mccq->used);
 858         memset(wrb, 0, sizeof(*wrb));
 859         return wrb;
 860 }
 861
 862 static bool use_mcc(struct be_adapter *adapter)
 863 {
 864         return adapter->mcc_obj.q.created;
 865 }
 866
 867 /* Must be used only in process context */
 868 static int be_cmd_lock(struct be_adapter *adapter)
 869 {
 870         if (use_mcc(adapter)) {
 871                 mutex_lock(&adapter->mcc_lock);
 872                 return 0;
 873         } else {
 874                 return mutex_lock_interruptible(&adapter->mbox_lock);
 875         }
 876 }
 877
 878 /* Must be used only in process context */
 879 static void be_cmd_unlock(struct be_adapter *adapter)
 880 {
 881         if (use_mcc(adapter))
 882                 return mutex_unlock(&adapter->mcc_lock);
 883         else
 884                 return mutex_unlock(&adapter->mbox_lock);
 885 }
 886
 887 static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter,
 888                                       struct be_mcc_wrb *wrb)
 889 {
 890         struct be_mcc_wrb *dest_wrb;
 891
 892         if (use_mcc(adapter)) {
 893                 dest_wrb = wrb_from_mccq(adapter);
 894                 if (!dest_wrb)
 895                         return NULL;
 896         } else {
 897                 dest_wrb = wrb_from_mbox(adapter);
 898         }
 899
 900         memcpy(dest_wrb, wrb, sizeof(*wrb));
 901         if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK))
 902                 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb));
 903
 904         return dest_wrb;
 905 }
 906
 907 /* Must be used only in process context */
 908 static int be_cmd_notify_wait(struct be_adapter *adapter,
 909                               struct be_mcc_wrb *wrb)
 910 {
 911         struct be_mcc_wrb *dest_wrb;
 912         int status;
 913
 914         status = be_cmd_lock(adapter);
 915         if (status)
 916                 return status;
 917
 918         dest_wrb = be_cmd_copy(adapter, wrb);
 919         if (!dest_wrb) {
 920                 status = -EBUSY;
 921                 goto unlock;
 922         }
 923
 924         if (use_mcc(adapter))
 925                 status = be_mcc_notify_wait(adapter);
 926         else
 927                 status = be_mbox_notify_wait(adapter);
 928
 929         if (!status)
 930                 memcpy(wrb, dest_wrb, sizeof(*wrb));
 931
 932 unlock:
 933         be_cmd_unlock(adapter);
 934         return status;
 935 }
 936
 937 /* Tell fw we're about to start firing cmds by writing a
 938  * special pattern across the wrb hdr; uses mbox
 939  */
 940 int be_cmd_fw_init(struct be_adapter *adapter)
 941 {
 942         u8 *wrb;
 943         int status;
 944
 945         if (lancer_chip(adapter))
 946                 return 0;
 947
 948         if (mutex_lock_interruptible(&adapter->mbox_lock))
 949                 return -1;
 950
 951         wrb = (u8 *)wrb_from_mbox(adapter);
 952         *wrb++ = 0xFF;
 953         *wrb++ = 0x12;
 954         *wrb++ = 0x34;
 955         *wrb++ = 0xFF;
 956         *wrb++ = 0xFF;
 957         *wrb++ = 0x56;
 958         *wrb++ = 0x78;
 959         *wrb = 0xFF;
 960
 961         status = be_mbox_notify_wait(adapter);
 962
 963         mutex_unlock(&adapter->mbox_lock);
 964         return status;
 965 }
 966
 967 /* Tell fw we're done with firing cmds by writing a
 968  * special pattern across the wrb hdr; uses mbox
 969  */
 970 int be_cmd_fw_clean(struct be_adapter *adapter)
 971 {
 972         u8 *wrb;
 973         int status;
 974
 975         if (lancer_chip(adapter))
 976                 return 0;
 977
 978         if (mutex_lock_interruptible(&adapter->mbox_lock))
 979                 return -1;
 980
 981         wrb = (u8 *)wrb_from_mbox(adapter);
 982         *wrb++ = 0xFF;
 983         *wrb++ = 0xAA;
 984         *wrb++ = 0xBB;
 985         *wrb++ = 0xFF;
 986         *wrb++ = 0xFF;
 987         *wrb++ = 0xCC;
 988         *wrb++ = 0xDD;
 989         *wrb = 0xFF;
 990
 991         status = be_mbox_notify_wait(adapter);
 992
 993         mutex_unlock(&adapter->mbox_lock);
 994         return status;
 995 }
 996
 997 int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
 998 {
 999         struct be_mcc_wrb *wrb;
1000         struct be_cmd_req_eq_create *req;
1001         struct be_dma_mem *q_mem = &eqo->q.dma_mem;
1002         int status, ver = 0;
1003
1004         if (mutex_lock_interruptible(&adapter->mbox_lock))
1005                 return -1;
1006
1007         wrb = wrb_from_mbox(adapter);
1008         req = embedded_payload(wrb);
1009
1010         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1011                                OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb,
1012                                NULL);
1013
1014         /* Support for EQ_CREATEv2 available only SH-R onwards */
1015         if (!(BEx_chip(adapter) || lancer_chip(adapter)))
1016                 ver = 2;
1017
1018         req->hdr.version = ver;
1019         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1020
1021         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
1022         /* 4byte eqe*/
1023         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
1024         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
1025                       __ilog2_u32(eqo->q.len / 256));
1026         be_dws_cpu_to_le(req->context, sizeof(req->context));
1027
1028         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1029
1030         status = be_mbox_notify_wait(adapter);
1031         if (!status) {
1032                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
1033
1034                 eqo->q.id = le16_to_cpu(resp->eq_id);
1035                 eqo->msix_idx =
1036                         (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx;
1037                 eqo->q.created = true;
1038         }
1039
1040         mutex_unlock(&adapter->mbox_lock);
1041         return status;
1042 }
1043
1044 /* Use MCC */
1045 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
1046                           bool permanent, u32 if_handle, u32 pmac_id)
1047 {
1048         struct be_mcc_wrb *wrb;
1049         struct be_cmd_req_mac_query *req;
1050         int status;
1051
1052         mutex_lock(&adapter->mcc_lock);
1053
1054         wrb = wrb_from_mccq(adapter);
1055         if (!wrb) {
1056                 status = -EBUSY;
1057                 goto err;
1058         }
1059         req = embedded_payload(wrb);
1060
1061         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1062                                OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb,
1063                                NULL);
1064         req->type = MAC_ADDRESS_TYPE_NETWORK;
1065         if (permanent) {
1066                 req->permanent = 1;
1067         } else {
1068                 req->if_id = cpu_to_le16((u16)if_handle);
1069                 req->pmac_id = cpu_to_le32(pmac_id);
1070                 req->permanent = 0;
1071         }
1072
1073         status = be_mcc_notify_wait(adapter);
1074         if (!status) {
1075                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
1076
1077                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
1078         }
1079
1080 err:
1081         mutex_unlock(&adapter->mcc_lock);
1082         return status;
1083 }
1084
1085 /* Uses synchronous MCCQ */
1086 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
1087                     u32 if_id, u32 *pmac_id, u32 domain)
1088 {
1089         struct be_mcc_wrb *wrb;
1090         struct be_cmd_req_pmac_add *req;
1091         int status;
1092
1093         mutex_lock(&adapter->mcc_lock);
1094
1095         wrb = wrb_from_mccq(adapter);
1096         if (!wrb) {
1097                 status = -EBUSY;
1098                 goto err;
1099         }
1100         req = embedded_payload(wrb);
1101
1102         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1103                                OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb,
1104                                NULL);
1105
1106         req->hdr.domain = domain;
1107         req->if_id = cpu_to_le32(if_id);
1108         memcpy(req->mac_address, mac_addr, ETH_ALEN);
1109
1110         status = be_mcc_notify_wait(adapter);
1111         if (!status) {
1112                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
1113
1114                 *pmac_id = le32_to_cpu(resp->pmac_id);
1115         }
1116
1117 err:
1118         mutex_unlock(&adapter->mcc_lock);
1119
1120          if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
1121                 status = -EPERM;
1122
1123         return status;
1124 }
1125
1126 /* Uses synchronous MCCQ */
1127 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
1128 {
1129         struct be_mcc_wrb *wrb;
1130         struct be_cmd_req_pmac_del *req;
1131         int status;
1132
1133         if (pmac_id == -1)
1134                 return 0;
1135
1136         mutex_lock(&adapter->mcc_lock);
1137
1138         wrb = wrb_from_mccq(adapter);
1139         if (!wrb) {
1140                 status = -EBUSY;
1141                 goto err;
1142         }
1143         req = embedded_payload(wrb);
1144
1145         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1146                                OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req),
1147                                wrb, NULL);
1148
1149         req->hdr.domain = dom;
1150         req->if_id = cpu_to_le32(if_id);
1151         req->pmac_id = cpu_to_le32(pmac_id);
1152
1153         status = be_mcc_notify_wait(adapter);
1154
1155 err:
1156         mutex_unlock(&adapter->mcc_lock);
1157         return status;
1158 }
1159
1160 /* Uses Mbox */
1161 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
1162                      struct be_queue_info *eq, bool no_delay, int coalesce_wm)
1163 {
1164         struct be_mcc_wrb *wrb;
1165         struct be_cmd_req_cq_create *req;
1166         struct be_dma_mem *q_mem = &cq->dma_mem;
1167         void *ctxt;
1168         int status;
1169
1170         if (mutex_lock_interruptible(&adapter->mbox_lock))
1171                 return -1;
1172
1173         wrb = wrb_from_mbox(adapter);
1174         req = embedded_payload(wrb);
1175         ctxt = &req->context;
1176
1177         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1178                                OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb,
1179                                NULL);
1180
1181         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1182
1183         if (BEx_chip(adapter)) {
1184                 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
1185                               coalesce_wm);
1186                 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
1187                               ctxt, no_delay);
1188                 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
1189                               __ilog2_u32(cq->len / 256));
1190                 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
1191                 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
1192                 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
1193         } else {
1194                 req->hdr.version = 2;
1195                 req->page_size = 1; /* 1 for 4K */
1196
1197                 /* coalesce-wm field in this cmd is not relevant to Lancer.
1198                  * Lancer uses COMMON_MODIFY_CQ to set this field
1199                  */
1200                 if (!lancer_chip(adapter))
1201                         AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
1202                                       ctxt, coalesce_wm);
1203                 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
1204                               no_delay);
1205                 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
1206                               __ilog2_u32(cq->len / 256));
1207                 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
1208                 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
1209                 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
1210         }
1211
1212         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1213
1214         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1215
1216         status = be_mbox_notify_wait(adapter);
1217         if (!status) {
1218                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
1219
1220                 cq->id = le16_to_cpu(resp->cq_id);
1221                 cq->created = true;
1222         }
1223
1224         mutex_unlock(&adapter->mbox_lock);
1225
1226         return status;
1227 }
1228
1229 static u32 be_encoded_q_len(int q_len)
1230 {
1231         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
1232
1233         if (len_encoded == 16)
1234                 len_encoded = 0;
1235         return len_encoded;
1236 }
1237
1238 static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
1239                                   struct be_queue_info *mccq,
1240                                   struct be_queue_info *cq)
1241 {
1242         struct be_mcc_wrb *wrb;
1243         struct be_cmd_req_mcc_ext_create *req;
1244         struct be_dma_mem *q_mem = &mccq->dma_mem;
1245         void *ctxt;
1246         int status;
1247
1248         if (mutex_lock_interruptible(&adapter->mbox_lock))
1249                 return -1;
1250
1251         wrb = wrb_from_mbox(adapter);
1252         req = embedded_payload(wrb);
1253         ctxt = &req->context;
1254
1255         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1256                                OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb,
1257                                NULL);
1258
1259         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1260         if (BEx_chip(adapter)) {
1261                 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1262                 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1263                               be_encoded_q_len(mccq->len));
1264                 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1265         } else {
1266                 req->hdr.version = 1;
1267                 req->cq_id = cpu_to_le16(cq->id);
1268
1269                 AMAP_SET_BITS(struct amap_mcc_context_v1, ring_size, ctxt,
1270                               be_encoded_q_len(mccq->len));
1271                 AMAP_SET_BITS(struct amap_mcc_context_v1, valid, ctxt, 1);
1272                 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_id,
1273                               ctxt, cq->id);
1274                 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_valid,
1275                               ctxt, 1);
1276         }
1277
1278         /* Subscribe to Link State, Sliport Event and Group 5 Events
1279          * (bits 1, 5 and 17 set)
1280          */
1281         req->async_event_bitmap[0] =
1282                         cpu_to_le32(BIT(ASYNC_EVENT_CODE_LINK_STATE) |
1283                                     BIT(ASYNC_EVENT_CODE_GRP_5) |
1284                                     BIT(ASYNC_EVENT_CODE_QNQ) |
1285                                     BIT(ASYNC_EVENT_CODE_SLIPORT));
1286
1287         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1288
1289         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1290
1291         status = be_mbox_notify_wait(adapter);
1292         if (!status) {
1293                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1294
1295                 mccq->id = le16_to_cpu(resp->id);
1296                 mccq->created = true;
1297         }
1298         mutex_unlock(&adapter->mbox_lock);
1299
1300         return status;
1301 }
1302
1303 static int be_cmd_mccq_org_create(struct be_adapter *adapter,
1304                                   struct be_queue_info *mccq,
1305                                   struct be_queue_info *cq)
1306 {
1307         struct be_mcc_wrb *wrb;
1308         struct be_cmd_req_mcc_create *req;
1309         struct be_dma_mem *q_mem = &mccq->dma_mem;
1310         void *ctxt;
1311         int status;
1312
1313         if (mutex_lock_interruptible(&adapter->mbox_lock))
1314                 return -1;
1315
1316         wrb = wrb_from_mbox(adapter);
1317         req = embedded_payload(wrb);
1318         ctxt = &req->context;
1319
1320         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1321                                OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb,
1322                                NULL);
1323
1324         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1325
1326         AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1327         AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1328                       be_encoded_q_len(mccq->len));
1329         AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1330
1331         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1332
1333         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1334
1335         status = be_mbox_notify_wait(adapter);
1336         if (!status) {
1337                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1338
1339                 mccq->id = le16_to_cpu(resp->id);
1340                 mccq->created = true;
1341         }
1342
1343         mutex_unlock(&adapter->mbox_lock);
1344         return status;
1345 }
1346
1347 int be_cmd_mccq_create(struct be_adapter *adapter,
1348                        struct be_queue_info *mccq, struct be_queue_info *cq)
1349 {
1350         int status;
1351
1352         status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1353         if (status && BEx_chip(adapter)) {
1354                 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1355                         "or newer to avoid conflicting priorities between NIC "
1356                         "and FCoE traffic");
1357                 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1358         }
1359         return status;
1360 }
1361
1362 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
1363 {
1364         struct be_mcc_wrb wrb = {0};
1365         struct be_cmd_req_eth_tx_create *req;
1366         struct be_queue_info *txq = &txo->q;
1367         struct be_queue_info *cq = &txo->cq;
1368         struct be_dma_mem *q_mem = &txq->dma_mem;
1369         int status, ver = 0;
1370
1371         req = embedded_payload(&wrb);
1372         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1373                                OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL);
1374
1375         if (lancer_chip(adapter)) {
1376                 req->hdr.version = 1;
1377         } else if (BEx_chip(adapter)) {
1378                 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1379                         req->hdr.version = 2;
1380         } else { /* For SH */
1381                 req->hdr.version = 2;
1382         }
1383
1384         if (req->hdr.version > 0)
1385                 req->if_id = cpu_to_le16(adapter->if_handle);
1386         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1387         req->ulp_num = BE_ULP1_NUM;
1388         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1389         req->cq_id = cpu_to_le16(cq->id);
1390         req->queue_size = be_encoded_q_len(txq->len);
1391         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1392         ver = req->hdr.version;
1393
1394         status = be_cmd_notify_wait(adapter, &wrb);
1395         if (!status) {
1396                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb);
1397
1398                 txq->id = le16_to_cpu(resp->cid);
1399                 if (ver == 2)
1400                         txo->db_offset = le32_to_cpu(resp->db_offset);
1401                 else
1402                         txo->db_offset = DB_TXULP1_OFFSET;
1403                 txq->created = true;
1404         }
1405
1406         return status;
1407 }
1408
1409 /* Uses MCC */
1410 int be_cmd_rxq_create(struct be_adapter *adapter,
1411                       struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1412                       u32 if_id, u32 rss, u8 *rss_id)
1413 {
1414         struct be_mcc_wrb *wrb;
1415         struct be_cmd_req_eth_rx_create *req;
1416         struct be_dma_mem *q_mem = &rxq->dma_mem;
1417         int status;
1418
1419         mutex_lock(&adapter->mcc_lock);
1420
1421         wrb = wrb_from_mccq(adapter);
1422         if (!wrb) {
1423                 status = -EBUSY;
1424                 goto err;
1425         }
1426         req = embedded_payload(wrb);
1427
1428         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1429                                OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1430
1431         req->cq_id = cpu_to_le16(cq_id);
1432         req->frag_size = fls(frag_size) - 1;
1433         req->num_pages = 2;
1434         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1435         req->interface_id = cpu_to_le32(if_id);
1436         req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
1437         req->rss_queue = cpu_to_le32(rss);
1438
1439         status = be_mcc_notify_wait(adapter);
1440         if (!status) {
1441                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1442
1443                 rxq->id = le16_to_cpu(resp->id);
1444                 rxq->created = true;
1445                 *rss_id = resp->rss_id;
1446         }
1447
1448 err:
1449         mutex_unlock(&adapter->mcc_lock);
1450         return status;
1451 }
1452
1453 /* Generic destroyer function for all types of queues
1454  * Uses Mbox
1455  */
1456 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1457                      int queue_type)
1458 {
1459         struct be_mcc_wrb *wrb;
1460         struct be_cmd_req_q_destroy *req;
1461         u8 subsys = 0, opcode = 0;
1462         int status;
1463
1464         if (mutex_lock_interruptible(&adapter->mbox_lock))
1465                 return -1;
1466
1467         wrb = wrb_from_mbox(adapter);
1468         req = embedded_payload(wrb);
1469
1470         switch (queue_type) {
1471         case QTYPE_EQ:
1472                 subsys = CMD_SUBSYSTEM_COMMON;
1473                 opcode = OPCODE_COMMON_EQ_DESTROY;
1474                 break;
1475         case QTYPE_CQ:
1476                 subsys = CMD_SUBSYSTEM_COMMON;
1477                 opcode = OPCODE_COMMON_CQ_DESTROY;
1478                 break;
1479         case QTYPE_TXQ:
1480                 subsys = CMD_SUBSYSTEM_ETH;
1481                 opcode = OPCODE_ETH_TX_DESTROY;
1482                 break;
1483         case QTYPE_RXQ:
1484                 subsys = CMD_SUBSYSTEM_ETH;
1485                 opcode = OPCODE_ETH_RX_DESTROY;
1486                 break;
1487         case QTYPE_MCCQ:
1488                 subsys = CMD_SUBSYSTEM_COMMON;
1489                 opcode = OPCODE_COMMON_MCC_DESTROY;
1490                 break;
1491         default:
1492                 BUG();
1493         }
1494
1495         be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1496                                NULL);
1497         req->id = cpu_to_le16(q->id);
1498
1499         status = be_mbox_notify_wait(adapter);
1500         q->created = false;
1501
1502         mutex_unlock(&adapter->mbox_lock);
1503         return status;
1504 }
1505
1506 /* Uses MCC */
1507 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1508 {
1509         struct be_mcc_wrb *wrb;
1510         struct be_cmd_req_q_destroy *req;
1511         int status;
1512
1513         mutex_lock(&adapter->mcc_lock);
1514
1515         wrb = wrb_from_mccq(adapter);
1516         if (!wrb) {
1517                 status = -EBUSY;
1518                 goto err;
1519         }
1520         req = embedded_payload(wrb);
1521
1522         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1523                                OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1524         req->id = cpu_to_le16(q->id);
1525
1526         status = be_mcc_notify_wait(adapter);
1527         q->created = false;
1528
1529 err:
1530         mutex_unlock(&adapter->mcc_lock);
1531         return status;
1532 }
1533
1534 /* Create an rx filtering policy configuration on an i/f
1535  * Will use MBOX only if MCCQ has not been created.
1536  */
1537 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1538                      u32 *if_handle, u32 domain)
1539 {
1540         struct be_mcc_wrb wrb = {0};
1541         struct be_cmd_req_if_create *req;
1542         int status;
1543
1544         req = embedded_payload(&wrb);
1545         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1546                                OPCODE_COMMON_NTWK_INTERFACE_CREATE,
1547                                sizeof(*req), &wrb, NULL);
1548         req->hdr.domain = domain;
1549         req->capability_flags = cpu_to_le32(cap_flags);
1550         req->enable_flags = cpu_to_le32(en_flags);
1551         req->pmac_invalid = true;
1552
1553         status = be_cmd_notify_wait(adapter, &wrb);
1554         if (!status) {
1555                 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb);
1556
1557                 *if_handle = le32_to_cpu(resp->interface_id);
1558
1559                 /* Hack to retrieve VF's pmac-id on BE3 */
1560                 if (BE3_chip(adapter) && be_virtfn(adapter))
1561                         adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
1562         }
1563         return status;
1564 }
1565
1566 /* Uses MCCQ if available else MBOX */
1567 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1568 {
1569         struct be_mcc_wrb wrb = {0};
1570         struct be_cmd_req_if_destroy *req;
1571         int status;
1572
1573         if (interface_id == -1)
1574                 return 0;
1575
1576         req = embedded_payload(&wrb);
1577
1578         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1579                                OPCODE_COMMON_NTWK_INTERFACE_DESTROY,
1580                                sizeof(*req), &wrb, NULL);
1581         req->hdr.domain = domain;
1582         req->interface_id = cpu_to_le32(interface_id);
1583
1584         status = be_cmd_notify_wait(adapter, &wrb);
1585         return status;
1586 }
1587
1588 /* Get stats is a non embedded command: the request is not embedded inside
1589  * WRB but is a separate dma memory block
1590  * Uses asynchronous MCC
1591  */
1592 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1593 {
1594         struct be_mcc_wrb *wrb;
1595         struct be_cmd_req_hdr *hdr;
1596         int status = 0;
1597
1598         mutex_lock(&adapter->mcc_lock);
1599
1600         wrb = wrb_from_mccq(adapter);
1601         if (!wrb) {
1602                 status = -EBUSY;
1603                 goto err;
1604         }
1605         hdr = nonemb_cmd->va;
1606
1607         be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1608                                OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb,
1609                                nonemb_cmd);
1610
1611         /* version 1 of the cmd is not supported only by BE2 */
1612         if (BE2_chip(adapter))
1613                 hdr->version = 0;
1614         if (BE3_chip(adapter) || lancer_chip(adapter))
1615                 hdr->version = 1;
1616         else
1617                 hdr->version = 2;
1618
1619         status = be_mcc_notify(adapter);
1620         if (status)
1621                 goto err;
1622
1623         adapter->stats_cmd_sent = true;
1624
1625 err:
1626         mutex_unlock(&adapter->mcc_lock);
1627         return status;
1628 }
1629
1630 /* Lancer Stats */
1631 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1632                                struct be_dma_mem *nonemb_cmd)
1633 {
1634         struct be_mcc_wrb *wrb;
1635         struct lancer_cmd_req_pport_stats *req;
1636         int status = 0;
1637
1638         if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1639                             CMD_SUBSYSTEM_ETH))
1640                 return -EPERM;
1641
1642         mutex_lock(&adapter->mcc_lock);
1643
1644         wrb = wrb_from_mccq(adapter);
1645         if (!wrb) {
1646                 status = -EBUSY;
1647                 goto err;
1648         }
1649         req = nonemb_cmd->va;
1650
1651         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1652                                OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size,
1653                                wrb, nonemb_cmd);
1654
1655         req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1656         req->cmd_params.params.reset_stats = 0;
1657
1658         status = be_mcc_notify(adapter);
1659         if (status)
1660                 goto err;
1661
1662         adapter->stats_cmd_sent = true;
1663
1664 err:
1665         mutex_unlock(&adapter->mcc_lock);
1666         return status;
1667 }
1668
1669 static int be_mac_to_link_speed(int mac_speed)
1670 {
1671         switch (mac_speed) {
1672         case PHY_LINK_SPEED_ZERO:
1673                 return 0;
1674         case PHY_LINK_SPEED_10MBPS:
1675                 return 10;
1676         case PHY_LINK_SPEED_100MBPS:
1677                 return 100;
1678         case PHY_LINK_SPEED_1GBPS:
1679                 return 1000;
1680         case PHY_LINK_SPEED_10GBPS:
1681                 return 10000;
1682         case PHY_LINK_SPEED_20GBPS:
1683                 return 20000;
1684         case PHY_LINK_SPEED_25GBPS:
1685                 return 25000;
1686         case PHY_LINK_SPEED_40GBPS:
1687                 return 40000;
1688         }
1689         return 0;
1690 }
1691
1692 /* Uses synchronous mcc
1693  * Returns link_speed in Mbps
1694  */
1695 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1696                              u8 *link_status, u32 dom)
1697 {
1698         struct be_mcc_wrb *wrb;
1699         struct be_cmd_req_link_status *req;
1700         int status;
1701
1702         mutex_lock(&adapter->mcc_lock);
1703
1704         if (link_status)
1705                 *link_status = LINK_DOWN;
1706
1707         wrb = wrb_from_mccq(adapter);
1708         if (!wrb) {
1709                 status = -EBUSY;
1710                 goto err;
1711         }
1712         req = embedded_payload(wrb);
1713
1714         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1715                                OPCODE_COMMON_NTWK_LINK_STATUS_QUERY,
1716                                sizeof(*req), wrb, NULL);
1717
1718         /* version 1 of the cmd is not supported only by BE2 */
1719         if (!BE2_chip(adapter))
1720                 req->hdr.version = 1;
1721
1722         req->hdr.domain = dom;
1723
1724         status = be_mcc_notify_wait(adapter);
1725         if (!status) {
1726                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1727
1728                 if (link_speed) {
1729                         *link_speed = resp->link_speed ?
1730                                       le16_to_cpu(resp->link_speed) * 10 :
1731                                       be_mac_to_link_speed(resp->mac_speed);
1732
1733                         if (!resp->logical_link_status)
1734                                 *link_speed = 0;
1735                 }
1736                 if (link_status)
1737                         *link_status = resp->logical_link_status;
1738         }
1739
1740 err:
1741         mutex_unlock(&adapter->mcc_lock);
1742         return status;
1743 }
1744
1745 /* Uses synchronous mcc */
1746 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1747 {
1748         struct be_mcc_wrb *wrb;
1749         struct be_cmd_req_get_cntl_addnl_attribs *req;
1750         int status = 0;
1751
1752         mutex_lock(&adapter->mcc_lock);
1753
1754         wrb = wrb_from_mccq(adapter);
1755         if (!wrb) {
1756                 status = -EBUSY;
1757                 goto err;
1758         }
1759         req = embedded_payload(wrb);
1760
1761         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1762                                OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES,
1763                                sizeof(*req), wrb, NULL);
1764
1765         status = be_mcc_notify(adapter);
1766 err:
1767         mutex_unlock(&adapter->mcc_lock);
1768         return status;
1769 }
1770
1771 /* Uses synchronous mcc */
1772 int be_cmd_get_fat_dump_len(struct be_adapter *adapter, u32 *dump_size)
1773 {
1774         struct be_mcc_wrb wrb = {0};
1775         struct be_cmd_req_get_fat *req;
1776         int status;
1777
1778         req = embedded_payload(&wrb);
1779
1780         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1781                                OPCODE_COMMON_MANAGE_FAT, sizeof(*req),
1782                                &wrb, NULL);
1783         req->fat_operation = cpu_to_le32(QUERY_FAT);
1784         status = be_cmd_notify_wait(adapter, &wrb);
1785         if (!status) {
1786                 struct be_cmd_resp_get_fat *resp = embedded_payload(&wrb);
1787
1788                 if (dump_size && resp->log_size)
1789                         *dump_size = le32_to_cpu(resp->log_size) -
1790                                         sizeof(u32);
1791         }
1792         return status;
1793 }
1794
1795 int be_cmd_get_fat_dump(struct be_adapter *adapter, u32 buf_len, void *buf)
1796 {
1797         struct be_dma_mem get_fat_cmd;
1798         struct be_mcc_wrb *wrb;
1799         struct be_cmd_req_get_fat *req;
1800         u32 offset = 0, total_size, buf_size,
1801                                 log_offset = sizeof(u32), payload_len;
1802         int status;
1803
1804         if (buf_len == 0)
1805                 return 0;
1806
1807         total_size = buf_len;
1808
1809         get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1810         get_fat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
1811                                              get_fat_cmd.size,
1812                                              &get_fat_cmd.dma, GFP_ATOMIC);
1813         if (!get_fat_cmd.va)
1814                 return -ENOMEM;
1815
1816         mutex_lock(&adapter->mcc_lock);
1817
1818         while (total_size) {
1819                 buf_size = min(total_size, (u32)60*1024);
1820                 total_size -= buf_size;
1821
1822                 wrb = wrb_from_mccq(adapter);
1823                 if (!wrb) {
1824                         status = -EBUSY;
1825                         goto err;
1826                 }
1827                 req = get_fat_cmd.va;
1828
1829                 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1830                 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1831                                        OPCODE_COMMON_MANAGE_FAT, payload_len,
1832                                        wrb, &get_fat_cmd);
1833
1834                 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1835                 req->read_log_offset = cpu_to_le32(log_offset);
1836                 req->read_log_length = cpu_to_le32(buf_size);
1837                 req->data_buffer_size = cpu_to_le32(buf_size);
1838
1839                 status = be_mcc_notify_wait(adapter);
1840                 if (!status) {
1841                         struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1842
1843                         memcpy(buf + offset,
1844                                resp->data_buffer,
1845                                le32_to_cpu(resp->read_log_length));
1846                 } else {
1847                         dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1848                         goto err;
1849                 }
1850                 offset += buf_size;
1851                 log_offset += buf_size;
1852         }
1853 err:
1854         dma_free_coherent(&adapter->pdev->dev, get_fat_cmd.size,
1855                           get_fat_cmd.va, get_fat_cmd.dma);
1856         mutex_unlock(&adapter->mcc_lock);
1857         return status;
1858 }
1859
1860 /* Uses synchronous mcc */
1861 int be_cmd_get_fw_ver(struct be_adapter *adapter)
1862 {
1863         struct be_mcc_wrb *wrb;
1864         struct be_cmd_req_get_fw_version *req;
1865         int status;
1866
1867         mutex_lock(&adapter->mcc_lock);
1868
1869         wrb = wrb_from_mccq(adapter);
1870         if (!wrb) {
1871                 status = -EBUSY;
1872                 goto err;
1873         }
1874
1875         req = embedded_payload(wrb);
1876
1877         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1878                                OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb,
1879                                NULL);
1880         status = be_mcc_notify_wait(adapter);
1881         if (!status) {
1882                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1883
1884                 strlcpy(adapter->fw_ver, resp->firmware_version_string,
1885                         sizeof(adapter->fw_ver));
1886                 strlcpy(adapter->fw_on_flash, resp->fw_on_flash_version_string,
1887                         sizeof(adapter->fw_on_flash));
1888         }
1889 err:
1890         mutex_unlock(&adapter->mcc_lock);
1891         return status;
1892 }
1893
1894 /* set the EQ delay interval of an EQ to specified value
1895  * Uses async mcc
1896  */
1897 static int __be_cmd_modify_eqd(struct be_adapter *adapter,
1898                                struct be_set_eqd *set_eqd, int num)
1899 {
1900         struct be_mcc_wrb *wrb;
1901         struct be_cmd_req_modify_eq_delay *req;
1902         int status = 0, i;
1903
1904         mutex_lock(&adapter->mcc_lock);
1905
1906         wrb = wrb_from_mccq(adapter);
1907         if (!wrb) {
1908                 status = -EBUSY;
1909                 goto err;
1910         }
1911         req = embedded_payload(wrb);
1912
1913         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1914                                OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb,
1915                                NULL);
1916
1917         req->num_eq = cpu_to_le32(num);
1918         for (i = 0; i < num; i++) {
1919                 req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id);
1920                 req->set_eqd[i].phase = 0;
1921                 req->set_eqd[i].delay_multiplier =
1922                                 cpu_to_le32(set_eqd[i].delay_multiplier);
1923         }
1924
1925         status = be_mcc_notify(adapter);
1926 err:
1927         mutex_unlock(&adapter->mcc_lock);
1928         return status;
1929 }
1930
1931 int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd,
1932                       int num)
1933 {
1934         int num_eqs, i = 0;
1935
1936         while (num) {
1937                 num_eqs = min(num, 8);
1938                 __be_cmd_modify_eqd(adapter, &set_eqd[i], num_eqs);
1939                 i += num_eqs;
1940                 num -= num_eqs;
1941         }
1942
1943         return 0;
1944 }
1945
1946 /* Uses sycnhronous mcc */
1947 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1948                        u32 num, u32 domain)
1949 {
1950         struct be_mcc_wrb *wrb;
1951         struct be_cmd_req_vlan_config *req;
1952         int status;
1953
1954         mutex_lock(&adapter->mcc_lock);
1955
1956         wrb = wrb_from_mccq(adapter);
1957         if (!wrb) {
1958                 status = -EBUSY;
1959                 goto err;
1960         }
1961         req = embedded_payload(wrb);
1962
1963         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1964                                OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req),
1965                                wrb, NULL);
1966         req->hdr.domain = domain;
1967
1968         req->interface_id = if_id;
1969         req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0;
1970         req->num_vlan = num;
1971         memcpy(req->normal_vlan, vtag_array,
1972                req->num_vlan * sizeof(vtag_array[0]));
1973
1974         status = be_mcc_notify_wait(adapter);
1975 err:
1976         mutex_unlock(&adapter->mcc_lock);
1977         return status;
1978 }
1979
1980 static int __be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1981 {
1982         struct be_mcc_wrb *wrb;
1983         struct be_dma_mem *mem = &adapter->rx_filter;
1984         struct be_cmd_req_rx_filter *req = mem->va;
1985         int status;
1986
1987         mutex_lock(&adapter->mcc_lock);
1988
1989         wrb = wrb_from_mccq(adapter);
1990         if (!wrb) {
1991                 status = -EBUSY;
1992                 goto err;
1993         }
1994         memset(req, 0, sizeof(*req));
1995         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1996                                OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1997                                wrb, mem);
1998
1999         req->if_id = cpu_to_le32(adapter->if_handle);
2000         req->if_flags_mask = cpu_to_le32(flags);
2001         req->if_flags = (value == ON) ? req->if_flags_mask : 0;
2002
2003         if (flags & BE_IF_FLAGS_MULTICAST) {
2004                 int i;
2005
2006                 /* Reset mcast promisc mode if already set by setting mask
2007                  * and not setting flags field
2008                  */
2009                 req->if_flags_mask |=
2010                         cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
2011                                     be_if_cap_flags(adapter));
2012                 req->mcast_num = cpu_to_le32(adapter->mc_count);
2013                 for (i = 0; i < adapter->mc_count; i++)
2014                         ether_addr_copy(req->mcast_mac[i].byte,
2015                                         adapter->mc_list[i].mac);
2016         }
2017
2018         status = be_mcc_notify_wait(adapter);
2019 err:
2020         mutex_unlock(&adapter->mcc_lock);
2021         return status;
2022 }
2023
2024 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
2025 {
2026         struct device *dev = &adapter->pdev->dev;
2027
2028         if ((flags & be_if_cap_flags(adapter)) != flags) {
2029                 dev_warn(dev, "Cannot set rx filter flags 0x%x\n", flags);
2030                 dev_warn(dev, "Interface is capable of 0x%x flags only\n",
2031                          be_if_cap_flags(adapter));
2032         }
2033         flags &= be_if_cap_flags(adapter);
2034         if (!flags)
2035                 return -ENOTSUPP;
2036
2037         return __be_cmd_rx_filter(adapter, flags, value);
2038 }
2039
2040 /* Uses synchrounous mcc */
2041 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
2042 {
2043         struct be_mcc_wrb *wrb;
2044         struct be_cmd_req_set_flow_control *req;
2045         int status;
2046
2047         if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
2048                             CMD_SUBSYSTEM_COMMON))
2049                 return -EPERM;
2050
2051         mutex_lock(&adapter->mcc_lock);
2052
2053         wrb = wrb_from_mccq(adapter);
2054         if (!wrb) {
2055                 status = -EBUSY;
2056                 goto err;
2057         }
2058         req = embedded_payload(wrb);
2059
2060         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2061                                OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req),
2062                                wrb, NULL);
2063
2064         req->hdr.version = 1;
2065         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
2066         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
2067
2068         status = be_mcc_notify_wait(adapter);
2069
2070 err:
2071         mutex_unlock(&adapter->mcc_lock);
2072
2073         if (base_status(status) == MCC_STATUS_FEATURE_NOT_SUPPORTED)
2074                 return  -EOPNOTSUPP;
2075
2076         return status;
2077 }
2078
2079 /* Uses sycn mcc */
2080 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
2081 {
2082         struct be_mcc_wrb *wrb;
2083         struct be_cmd_req_get_flow_control *req;
2084         int status;
2085
2086         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
2087                             CMD_SUBSYSTEM_COMMON))
2088                 return -EPERM;
2089
2090         mutex_lock(&adapter->mcc_lock);
2091
2092         wrb = wrb_from_mccq(adapter);
2093         if (!wrb) {
2094                 status = -EBUSY;
2095                 goto err;
2096         }
2097         req = embedded_payload(wrb);
2098
2099         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2100                                OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req),
2101                                wrb, NULL);
2102
2103         status = be_mcc_notify_wait(adapter);
2104         if (!status) {
2105                 struct be_cmd_resp_get_flow_control *resp =
2106                                                 embedded_payload(wrb);
2107
2108                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
2109                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
2110         }
2111
2112 err:
2113         mutex_unlock(&adapter->mcc_lock);
2114         return status;
2115 }
2116
2117 /* Uses mbox */
2118 int be_cmd_query_fw_cfg(struct be_adapter *adapter)
2119 {
2120         struct be_mcc_wrb *wrb;
2121         struct be_cmd_req_query_fw_cfg *req;
2122         int status;
2123
2124         if (mutex_lock_interruptible(&adapter->mbox_lock))
2125                 return -1;
2126
2127         wrb = wrb_from_mbox(adapter);
2128         req = embedded_payload(wrb);
2129
2130         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2131                                OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
2132                                sizeof(*req), wrb, NULL);
2133
2134         status = be_mbox_notify_wait(adapter);
2135         if (!status) {
2136                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
2137
2138                 adapter->port_num = le32_to_cpu(resp->phys_port);
2139                 adapter->function_mode = le32_to_cpu(resp->function_mode);
2140                 adapter->function_caps = le32_to_cpu(resp->function_caps);
2141                 adapter->asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
2142                 dev_info(&adapter->pdev->dev,
2143                          "FW config: function_mode=0x%x, function_caps=0x%x\n",
2144                          adapter->function_mode, adapter->function_caps);
2145         }
2146
2147         mutex_unlock(&adapter->mbox_lock);
2148         return status;
2149 }
2150
2151 /* Uses mbox */
2152 int be_cmd_reset_function(struct be_adapter *adapter)
2153 {
2154         struct be_mcc_wrb *wrb;
2155         struct be_cmd_req_hdr *req;
2156         int status;
2157
2158         if (lancer_chip(adapter)) {
2159                 iowrite32(SLI_PORT_CONTROL_IP_MASK,
2160                           adapter->db + SLIPORT_CONTROL_OFFSET);
2161                 status = lancer_wait_ready(adapter);
2162                 if (status)
2163                         dev_err(&adapter->pdev->dev,
2164                                 "Adapter in non recoverable error\n");
2165                 return status;
2166         }
2167
2168         if (mutex_lock_interruptible(&adapter->mbox_lock))
2169                 return -1;
2170
2171         wrb = wrb_from_mbox(adapter);
2172         req = embedded_payload(wrb);
2173
2174         be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
2175                                OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb,
2176                                NULL);
2177
2178         status = be_mbox_notify_wait(adapter);
2179
2180         mutex_unlock(&adapter->mbox_lock);
2181         return status;
2182 }
2183
2184 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
2185                       u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey)
2186 {
2187         struct be_mcc_wrb *wrb;
2188         struct be_cmd_req_rss_config *req;
2189         int status;
2190
2191         if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS))
2192                 return 0;
2193
2194         mutex_lock(&adapter->mcc_lock);
2195
2196         wrb = wrb_from_mccq(adapter);
2197         if (!wrb) {
2198                 status = -EBUSY;
2199                 goto err;
2200         }
2201         req = embedded_payload(wrb);
2202
2203         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2204                                OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
2205
2206         req->if_id = cpu_to_le32(adapter->if_handle);
2207         req->enable_rss = cpu_to_le16(rss_hash_opts);
2208         req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
2209
2210         if (!BEx_chip(adapter))
2211                 req->hdr.version = 1;
2212
2213         memcpy(req->cpu_table, rsstable, table_size);
2214         memcpy(req->hash, rss_hkey, RSS_HASH_KEY_LEN);
2215         be_dws_cpu_to_le(req->hash, sizeof(req->hash));
2216
2217         status = be_mcc_notify_wait(adapter);
2218 err:
2219         mutex_unlock(&adapter->mcc_lock);
2220         return status;
2221 }
2222
2223 /* Uses sync mcc */
2224 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
2225                             u8 bcn, u8 sts, u8 state)
2226 {
2227         struct be_mcc_wrb *wrb;
2228         struct be_cmd_req_enable_disable_beacon *req;
2229         int status;
2230
2231         mutex_lock(&adapter->mcc_lock);
2232
2233         wrb = wrb_from_mccq(adapter);
2234         if (!wrb) {
2235                 status = -EBUSY;
2236                 goto err;
2237         }
2238         req = embedded_payload(wrb);
2239
2240         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2241                                OPCODE_COMMON_ENABLE_DISABLE_BEACON,
2242                                sizeof(*req), wrb, NULL);
2243
2244         req->port_num = port_num;
2245         req->beacon_state = state;
2246         req->beacon_duration = bcn;
2247         req->status_duration = sts;
2248
2249         status = be_mcc_notify_wait(adapter);
2250
2251 err:
2252         mutex_unlock(&adapter->mcc_lock);
2253         return status;
2254 }
2255
2256 /* Uses sync mcc */
2257 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2258 {
2259         struct be_mcc_wrb *wrb;
2260         struct be_cmd_req_get_beacon_state *req;
2261         int status;
2262
2263         mutex_lock(&adapter->mcc_lock);
2264
2265         wrb = wrb_from_mccq(adapter);
2266         if (!wrb) {
2267                 status = -EBUSY;
2268                 goto err;
2269         }
2270         req = embedded_payload(wrb);
2271
2272         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2273                                OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req),
2274                                wrb, NULL);
2275
2276         req->port_num = port_num;
2277
2278         status = be_mcc_notify_wait(adapter);
2279         if (!status) {
2280                 struct be_cmd_resp_get_beacon_state *resp =
2281                                                 embedded_payload(wrb);
2282
2283                 *state = resp->beacon_state;
2284         }
2285
2286 err:
2287         mutex_unlock(&adapter->mcc_lock);
2288         return status;
2289 }
2290
2291 /* Uses sync mcc */
2292 int be_cmd_read_port_transceiver_data(struct be_adapter *adapter,
2293                                       u8 page_num, u8 *data)
2294 {
2295         struct be_dma_mem cmd;
2296         struct be_mcc_wrb *wrb;
2297         struct be_cmd_req_port_type *req;
2298         int status;
2299
2300         if (page_num > TR_PAGE_A2)
2301                 return -EINVAL;
2302
2303         cmd.size = sizeof(struct be_cmd_resp_port_type);
2304         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
2305                                      GFP_ATOMIC);
2306         if (!cmd.va) {
2307                 dev_err(&adapter->pdev->dev, "Memory allocation failed\n");
2308                 return -ENOMEM;
2309         }
2310
2311         mutex_lock(&adapter->mcc_lock);
2312
2313         wrb = wrb_from_mccq(adapter);
2314         if (!wrb) {
2315                 status = -EBUSY;
2316                 goto err;
2317         }
2318         req = cmd.va;
2319
2320         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2321                                OPCODE_COMMON_READ_TRANSRECV_DATA,
2322                                cmd.size, wrb, &cmd);
2323
2324         req->port = cpu_to_le32(adapter->hba_port_num);
2325         req->page_num = cpu_to_le32(page_num);
2326         status = be_mcc_notify_wait(adapter);
2327         if (!status) {
2328                 struct be_cmd_resp_port_type *resp = cmd.va;
2329
2330                 memcpy(data, resp->page_data, PAGE_DATA_LEN);
2331         }
2332 err:
2333         mutex_unlock(&adapter->mcc_lock);
2334         dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
2335         return status;
2336 }
2337
2338 static int lancer_cmd_write_object(struct be_adapter *adapter,
2339                                    struct be_dma_mem *cmd, u32 data_size,
2340                                    u32 data_offset, const char *obj_name,
2341                                    u32 *data_written, u8 *change_status,
2342                                    u8 *addn_status)
2343 {
2344         struct be_mcc_wrb *wrb;
2345         struct lancer_cmd_req_write_object *req;
2346         struct lancer_cmd_resp_write_object *resp;
2347         void *ctxt = NULL;
2348         int status;
2349
2350         mutex_lock(&adapter->mcc_lock);
2351         adapter->flash_status = 0;
2352
2353         wrb = wrb_from_mccq(adapter);
2354         if (!wrb) {
2355                 status = -EBUSY;
2356                 goto err_unlock;
2357         }
2358
2359         req = embedded_payload(wrb);
2360
2361         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2362                                OPCODE_COMMON_WRITE_OBJECT,
2363                                sizeof(struct lancer_cmd_req_write_object), wrb,
2364                                NULL);
2365
2366         ctxt = &req->context;
2367         AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2368                       write_length, ctxt, data_size);
2369
2370         if (data_size == 0)
2371                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2372                               eof, ctxt, 1);
2373         else
2374                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2375                               eof, ctxt, 0);
2376
2377         be_dws_cpu_to_le(ctxt, sizeof(req->context));
2378         req->write_offset = cpu_to_le32(data_offset);
2379         strlcpy(req->object_name, obj_name, sizeof(req->object_name));
2380         req->descriptor_count = cpu_to_le32(1);
2381         req->buf_len = cpu_to_le32(data_size);
2382         req->addr_low = cpu_to_le32((cmd->dma +
2383                                      sizeof(struct lancer_cmd_req_write_object))
2384                                     & 0xFFFFFFFF);
2385         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2386                                 sizeof(struct lancer_cmd_req_write_object)));
2387
2388         status = be_mcc_notify(adapter);
2389         if (status)
2390                 goto err_unlock;
2391
2392         mutex_unlock(&adapter->mcc_lock);
2393
2394         if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2395                                          msecs_to_jiffies(60000)))
2396                 status = -ETIMEDOUT;
2397         else
2398                 status = adapter->flash_status;
2399
2400         resp = embedded_payload(wrb);
2401         if (!status) {
2402                 *data_written = le32_to_cpu(resp->actual_write_len);
2403                 *change_status = resp->change_status;
2404         } else {
2405                 *addn_status = resp->additional_status;
2406         }
2407
2408         return status;
2409
2410 err_unlock:
2411         mutex_unlock(&adapter->mcc_lock);
2412         return status;
2413 }
2414
2415 int be_cmd_query_cable_type(struct be_adapter *adapter)
2416 {
2417         u8 page_data[PAGE_DATA_LEN];
2418         int status;
2419
2420         status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2421                                                    page_data);
2422         if (!status) {
2423                 switch (adapter->phy.interface_type) {
2424                 case PHY_TYPE_QSFP:
2425                         adapter->phy.cable_type =
2426                                 page_data[QSFP_PLUS_CABLE_TYPE_OFFSET];
2427                         break;
2428                 case PHY_TYPE_SFP_PLUS_10GB:
2429                         adapter->phy.cable_type =
2430                                 page_data[SFP_PLUS_CABLE_TYPE_OFFSET];
2431                         break;
2432                 default:
2433                         adapter->phy.cable_type = 0;
2434                         break;
2435                 }
2436         }
2437         return status;
2438 }
2439
2440 int be_cmd_query_sfp_info(struct be_adapter *adapter)
2441 {
2442         u8 page_data[PAGE_DATA_LEN];
2443         int status;
2444
2445         status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2446                                                    page_data);
2447         if (!status) {
2448                 strlcpy(adapter->phy.vendor_name, page_data +
2449                         SFP_VENDOR_NAME_OFFSET, SFP_VENDOR_NAME_LEN - 1);
2450                 strlcpy(adapter->phy.vendor_pn,
2451                         page_data + SFP_VENDOR_PN_OFFSET,
2452                         SFP_VENDOR_NAME_LEN - 1);
2453         }
2454
2455         return status;
2456 }
2457
2458 static int lancer_cmd_delete_object(struct be_adapter *adapter,
2459                                     const char *obj_name)
2460 {
2461         struct lancer_cmd_req_delete_object *req;
2462         struct be_mcc_wrb *wrb;
2463         int status;
2464
2465         mutex_lock(&adapter->mcc_lock);
2466
2467         wrb = wrb_from_mccq(adapter);
2468         if (!wrb) {
2469                 status = -EBUSY;
2470                 goto err;
2471         }
2472
2473         req = embedded_payload(wrb);
2474
2475         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2476                                OPCODE_COMMON_DELETE_OBJECT,
2477                                sizeof(*req), wrb, NULL);
2478
2479         strlcpy(req->object_name, obj_name, sizeof(req->object_name));
2480
2481         status = be_mcc_notify_wait(adapter);
2482 err:
2483         mutex_unlock(&adapter->mcc_lock);
2484         return status;
2485 }
2486
2487 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2488                            u32 data_size, u32 data_offset, const char *obj_name,
2489                            u32 *data_read, u32 *eof, u8 *addn_status)
2490 {
2491         struct be_mcc_wrb *wrb;
2492         struct lancer_cmd_req_read_object *req;
2493         struct lancer_cmd_resp_read_object *resp;
2494         int status;
2495
2496         mutex_lock(&adapter->mcc_lock);
2497
2498         wrb = wrb_from_mccq(adapter);
2499         if (!wrb) {
2500                 status = -EBUSY;
2501                 goto err_unlock;
2502         }
2503
2504         req = embedded_payload(wrb);
2505
2506         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2507                                OPCODE_COMMON_READ_OBJECT,
2508                                sizeof(struct lancer_cmd_req_read_object), wrb,
2509                                NULL);
2510
2511         req->desired_read_len = cpu_to_le32(data_size);
2512         req->read_offset = cpu_to_le32(data_offset);
2513         strcpy(req->object_name, obj_name);
2514         req->descriptor_count = cpu_to_le32(1);
2515         req->buf_len = cpu_to_le32(data_size);
2516         req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2517         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2518
2519         status = be_mcc_notify_wait(adapter);
2520
2521         resp = embedded_payload(wrb);
2522         if (!status) {
2523                 *data_read = le32_to_cpu(resp->actual_read_len);
2524                 *eof = le32_to_cpu(resp->eof);
2525         } else {
2526                 *addn_status = resp->additional_status;
2527         }
2528
2529 err_unlock:
2530         mutex_unlock(&adapter->mcc_lock);
2531         return status;
2532 }
2533
2534 static int be_cmd_write_flashrom(struct be_adapter *adapter,
2535                                  struct be_dma_mem *cmd, u32 flash_type,
2536                                  u32 flash_opcode, u32 img_offset, u32 buf_size)
2537 {
2538         struct be_mcc_wrb *wrb;
2539         struct be_cmd_write_flashrom *req;
2540         int status;
2541
2542         mutex_lock(&adapter->mcc_lock);
2543         adapter->flash_status = 0;
2544
2545         wrb = wrb_from_mccq(adapter);
2546         if (!wrb) {
2547                 status = -EBUSY;
2548                 goto err_unlock;
2549         }
2550         req = cmd->va;
2551
2552         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2553                                OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb,
2554                                cmd);
2555
2556         req->params.op_type = cpu_to_le32(flash_type);
2557         if (flash_type == OPTYPE_OFFSET_SPECIFIED)
2558                 req->params.offset = cpu_to_le32(img_offset);
2559
2560         req->params.op_code = cpu_to_le32(flash_opcode);
2561         req->params.data_buf_size = cpu_to_le32(buf_size);
2562
2563         status = be_mcc_notify(adapter);
2564         if (status)
2565                 goto err_unlock;
2566
2567         mutex_unlock(&adapter->mcc_lock);
2568
2569         if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2570                                          msecs_to_jiffies(40000)))
2571                 status = -ETIMEDOUT;
2572         else
2573                 status = adapter->flash_status;
2574
2575         return status;
2576
2577 err_unlock:
2578         mutex_unlock(&adapter->mcc_lock);
2579         return status;
2580 }
2581
2582 static int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2583                                 u16 img_optype, u32 img_offset, u32 crc_offset)
2584 {
2585         struct be_cmd_read_flash_crc *req;
2586         struct be_mcc_wrb *wrb;
2587         int status;
2588
2589         mutex_lock(&adapter->mcc_lock);
2590
2591         wrb = wrb_from_mccq(adapter);
2592         if (!wrb) {
2593                 status = -EBUSY;
2594                 goto err;
2595         }
2596         req = embedded_payload(wrb);
2597
2598         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2599                                OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2600                                wrb, NULL);
2601
2602         req->params.op_type = cpu_to_le32(img_optype);
2603         if (img_optype == OPTYPE_OFFSET_SPECIFIED)
2604                 req->params.offset = cpu_to_le32(img_offset + crc_offset);
2605         else
2606                 req->params.offset = cpu_to_le32(crc_offset);
2607
2608         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2609         req->params.data_buf_size = cpu_to_le32(0x4);
2610
2611         status = be_mcc_notify_wait(adapter);
2612         if (!status)
2613                 memcpy(flashed_crc, req->crc, 4);
2614
2615 err:
2616         mutex_unlock(&adapter->mcc_lock);
2617         return status;
2618 }
2619
2620 static char flash_cookie[2][16] = {"*** SE FLAS", "H DIRECTORY *** "};
2621
2622 static bool phy_flashing_required(struct be_adapter *adapter)
2623 {
2624         return (adapter->phy.phy_type == PHY_TYPE_TN_8022 &&
2625                 adapter->phy.interface_type == PHY_TYPE_BASET_10GB);
2626 }
2627
2628 static bool is_comp_in_ufi(struct be_adapter *adapter,
2629                            struct flash_section_info *fsec, int type)
2630 {
2631         int i = 0, img_type = 0;
2632         struct flash_section_info_g2 *fsec_g2 = NULL;
2633
2634         if (BE2_chip(adapter))
2635                 fsec_g2 = (struct flash_section_info_g2 *)fsec;
2636
2637         for (i = 0; i < MAX_FLASH_COMP; i++) {
2638                 if (fsec_g2)
2639                         img_type = le32_to_cpu(fsec_g2->fsec_entry[i].type);
2640                 else
2641                         img_type = le32_to_cpu(fsec->fsec_entry[i].type);
2642
2643                 if (img_type == type)
2644                         return true;
2645         }
2646         return false;
2647 }
2648
2649 static struct flash_section_info *get_fsec_info(struct be_adapter *adapter,
2650                                                 int header_size,
2651                                                 const struct firmware *fw)
2652 {
2653         struct flash_section_info *fsec = NULL;
2654         const u8 *p = fw->data;
2655
2656         p += header_size;
2657         while (p < (fw->data + fw->size)) {
2658                 fsec = (struct flash_section_info *)p;
2659                 if (!memcmp(flash_cookie, fsec->cookie, sizeof(flash_cookie)))
2660                         return fsec;
2661                 p += 32;
2662         }
2663         return NULL;
2664 }
2665
2666 static int be_check_flash_crc(struct be_adapter *adapter, const u8 *p,
2667                               u32 img_offset, u32 img_size, int hdr_size,
2668                               u16 img_optype, bool *crc_match)
2669 {
2670         u32 crc_offset;
2671         int status;
2672         u8 crc[4];
2673
2674         status = be_cmd_get_flash_crc(adapter, crc, img_optype, img_offset,
2675                                       img_size - 4);
2676         if (status)
2677                 return status;
2678
2679         crc_offset = hdr_size + img_offset + img_size - 4;
2680
2681         /* Skip flashing, if crc of flashed region matches */
2682         if (!memcmp(crc, p + crc_offset, 4))
2683                 *crc_match = true;
2684         else
2685                 *crc_match = false;
2686
2687         return status;
2688 }
2689
2690 static int be_flash(struct be_adapter *adapter, const u8 *img,
2691                     struct be_dma_mem *flash_cmd, int optype, int img_size,
2692                     u32 img_offset)
2693 {
2694         u32 flash_op, num_bytes, total_bytes = img_size, bytes_sent = 0;
2695         struct be_cmd_write_flashrom *req = flash_cmd->va;
2696         int status;
2697
2698         while (total_bytes) {
2699                 num_bytes = min_t(u32, 32 * 1024, total_bytes);
2700
2701                 total_bytes -= num_bytes;
2702
2703                 if (!total_bytes) {
2704                         if (optype == OPTYPE_PHY_FW)
2705                                 flash_op = FLASHROM_OPER_PHY_FLASH;
2706                         else
2707                                 flash_op = FLASHROM_OPER_FLASH;
2708                 } else {
2709                         if (optype == OPTYPE_PHY_FW)
2710                                 flash_op = FLASHROM_OPER_PHY_SAVE;
2711                         else
2712                                 flash_op = FLASHROM_OPER_SAVE;
2713                 }
2714
2715                 memcpy(req->data_buf, img, num_bytes);
2716                 img += num_bytes;
2717                 status = be_cmd_write_flashrom(adapter, flash_cmd, optype,
2718                                                flash_op, img_offset +
2719                                                bytes_sent, num_bytes);
2720                 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST &&
2721                     optype == OPTYPE_PHY_FW)
2722                         break;
2723                 else if (status)
2724                         return status;
2725
2726                 bytes_sent += num_bytes;
2727         }
2728         return 0;
2729 }
2730
2731 /* For BE2, BE3 and BE3-R */
2732 static int be_flash_BEx(struct be_adapter *adapter,
2733                         const struct firmware *fw,
2734                         struct be_dma_mem *flash_cmd, int num_of_images)
2735 {
2736         int img_hdrs_size = (num_of_images * sizeof(struct image_hdr));
2737         struct device *dev = &adapter->pdev->dev;
2738         struct flash_section_info *fsec = NULL;
2739         int status, i, filehdr_size, num_comp;
2740         const struct flash_comp *pflashcomp;
2741         bool crc_match;
2742         const u8 *p;
2743
2744         struct flash_comp gen3_flash_types[] = {
2745                 { BE3_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE,
2746                         BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI},
2747                 { BE3_REDBOOT_START, OPTYPE_REDBOOT,
2748                         BE3_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE},
2749                 { BE3_ISCSI_BIOS_START, OPTYPE_BIOS,
2750                         BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI},
2751                 { BE3_PXE_BIOS_START, OPTYPE_PXE_BIOS,
2752                         BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE},
2753                 { BE3_FCOE_BIOS_START, OPTYPE_FCOE_BIOS,
2754                         BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE},
2755                 { BE3_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP,
2756                         BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI},
2757                 { BE3_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE,
2758                         BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE},
2759                 { BE3_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP,
2760                         BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE},
2761                 { BE3_NCSI_START, OPTYPE_NCSI_FW,
2762                         BE3_NCSI_COMP_MAX_SIZE, IMAGE_NCSI},
2763                 { BE3_PHY_FW_START, OPTYPE_PHY_FW,
2764                         BE3_PHY_FW_COMP_MAX_SIZE, IMAGE_FIRMWARE_PHY}
2765         };
2766
2767         struct flash_comp gen2_flash_types[] = {
2768                 { BE2_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE,
2769                         BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI},
2770                 { BE2_REDBOOT_START, OPTYPE_REDBOOT,
2771                         BE2_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE},
2772                 { BE2_ISCSI_BIOS_START, OPTYPE_BIOS,
2773                         BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI},
2774                 { BE2_PXE_BIOS_START, OPTYPE_PXE_BIOS,
2775                         BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE},
2776                 { BE2_FCOE_BIOS_START, OPTYPE_FCOE_BIOS,
2777                         BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE},
2778                 { BE2_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP,
2779                         BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI},
2780                 { BE2_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE,
2781                         BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE},
2782                 { BE2_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP,
2783                          BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE}
2784         };
2785
2786         if (BE3_chip(adapter)) {
2787                 pflashcomp = gen3_flash_types;
2788                 filehdr_size = sizeof(struct flash_file_hdr_g3);
2789                 num_comp = ARRAY_SIZE(gen3_flash_types);
2790         } else {
2791                 pflashcomp = gen2_flash_types;
2792                 filehdr_size = sizeof(struct flash_file_hdr_g2);
2793                 num_comp = ARRAY_SIZE(gen2_flash_types);
2794                 img_hdrs_size = 0;
2795         }
2796
2797         /* Get flash section info*/
2798         fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw);
2799         if (!fsec) {
2800                 dev_err(dev, "Invalid Cookie. FW image may be corrupted\n");
2801                 return -1;
2802         }
2803         for (i = 0; i < num_comp; i++) {
2804                 if (!is_comp_in_ufi(adapter, fsec, pflashcomp[i].img_type))
2805                         continue;
2806
2807                 if ((pflashcomp[i].optype == OPTYPE_NCSI_FW) &&
2808                     memcmp(adapter->fw_ver, "3.102.148.0", 11) < 0)
2809                         continue;
2810
2811                 if (pflashcomp[i].optype == OPTYPE_PHY_FW  &&
2812                     !phy_flashing_required(adapter))
2813                         continue;
2814
2815                 if (pflashcomp[i].optype == OPTYPE_REDBOOT) {
2816                         status = be_check_flash_crc(adapter, fw->data,
2817                                                     pflashcomp[i].offset,
2818                                                     pflashcomp[i].size,
2819                                                     filehdr_size +
2820                                                     img_hdrs_size,
2821                                                     OPTYPE_REDBOOT, &crc_match);
2822                         if (status) {
2823                                 dev_err(dev,
2824                                         "Could not get CRC for 0x%x region\n",
2825                                         pflashcomp[i].optype);
2826                                 continue;
2827                         }
2828
2829                         if (crc_match)
2830                                 continue;
2831                 }
2832
2833                 p = fw->data + filehdr_size + pflashcomp[i].offset +
2834                         img_hdrs_size;
2835                 if (p + pflashcomp[i].size > fw->data + fw->size)
2836                         return -1;
2837
2838                 status = be_flash(adapter, p, flash_cmd, pflashcomp[i].optype,
2839                                   pflashcomp[i].size, 0);
2840                 if (status) {
2841                         dev_err(dev, "Flashing section type 0x%x failed\n",
2842                                 pflashcomp[i].img_type);
2843                         return status;
2844                 }
2845         }
2846         return 0;
2847 }
2848
2849 static u16 be_get_img_optype(struct flash_section_entry fsec_entry)
2850 {
2851         u32 img_type = le32_to_cpu(fsec_entry.type);
2852         u16 img_optype = le16_to_cpu(fsec_entry.optype);
2853
2854         if (img_optype != 0xFFFF)
2855                 return img_optype;
2856
2857         switch (img_type) {
2858         case IMAGE_FIRMWARE_ISCSI:
2859                 img_optype = OPTYPE_ISCSI_ACTIVE;
2860                 break;
2861         case IMAGE_BOOT_CODE:
2862                 img_optype = OPTYPE_REDBOOT;
2863                 break;
2864         case IMAGE_OPTION_ROM_ISCSI:
2865                 img_optype = OPTYPE_BIOS;
2866                 break;
2867         case IMAGE_OPTION_ROM_PXE:
2868                 img_optype = OPTYPE_PXE_BIOS;
2869                 break;
2870         case IMAGE_OPTION_ROM_FCOE:
2871                 img_optype = OPTYPE_FCOE_BIOS;
2872                 break;
2873         case IMAGE_FIRMWARE_BACKUP_ISCSI:
2874                 img_optype = OPTYPE_ISCSI_BACKUP;
2875                 break;
2876         case IMAGE_NCSI:
2877                 img_optype = OPTYPE_NCSI_FW;
2878                 break;
2879         case IMAGE_FLASHISM_JUMPVECTOR:
2880                 img_optype = OPTYPE_FLASHISM_JUMPVECTOR;
2881                 break;
2882         case IMAGE_FIRMWARE_PHY:
2883                 img_optype = OPTYPE_SH_PHY_FW;
2884                 break;
2885         case IMAGE_REDBOOT_DIR:
2886                 img_optype = OPTYPE_REDBOOT_DIR;
2887                 break;
2888         case IMAGE_REDBOOT_CONFIG:
2889                 img_optype = OPTYPE_REDBOOT_CONFIG;
2890                 break;
2891         case IMAGE_UFI_DIR:
2892                 img_optype = OPTYPE_UFI_DIR;
2893                 break;
2894         default:
2895                 break;
2896         }
2897
2898         return img_optype;
2899 }
2900
2901 static int be_flash_skyhawk(struct be_adapter *adapter,
2902                             const struct firmware *fw,
2903                             struct be_dma_mem *flash_cmd, int num_of_images)
2904 {
2905         int img_hdrs_size = num_of_images * sizeof(struct image_hdr);
2906         bool crc_match, old_fw_img, flash_offset_support = true;
2907         struct device *dev = &adapter->pdev->dev;
2908         struct flash_section_info *fsec = NULL;
2909         u32 img_offset, img_size, img_type;
2910         u16 img_optype, flash_optype;
2911         int status, i, filehdr_size;
2912         const u8 *p;
2913
2914         filehdr_size = sizeof(struct flash_file_hdr_g3);
2915         fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw);
2916         if (!fsec) {
2917                 dev_err(dev, "Invalid Cookie. FW image may be corrupted\n");
2918                 return -EINVAL;
2919         }
2920
2921 retry_flash:
2922         for (i = 0; i < le32_to_cpu(fsec->fsec_hdr.num_images); i++) {
2923                 img_offset = le32_to_cpu(fsec->fsec_entry[i].offset);
2924                 img_size   = le32_to_cpu(fsec->fsec_entry[i].pad_size);
2925                 img_type   = le32_to_cpu(fsec->fsec_entry[i].type);
2926                 img_optype = be_get_img_optype(fsec->fsec_entry[i]);
2927                 old_fw_img = fsec->fsec_entry[i].optype == 0xFFFF;
2928
2929                 if (img_optype == 0xFFFF)
2930                         continue;
2931
2932                 if (flash_offset_support)
2933                         flash_optype = OPTYPE_OFFSET_SPECIFIED;
2934                 else
2935                         flash_optype = img_optype;
2936
2937                 /* Don't bother verifying CRC if an old FW image is being
2938                  * flashed
2939                  */
2940                 if (old_fw_img)
2941                         goto flash;
2942
2943                 status = be_check_flash_crc(adapter, fw->data, img_offset,
2944                                             img_size, filehdr_size +
2945                                             img_hdrs_size, flash_optype,
2946                                             &crc_match);
2947                 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST ||
2948                     base_status(status) == MCC_STATUS_ILLEGAL_FIELD) {
2949                         /* The current FW image on the card does not support
2950                          * OFFSET based flashing. Retry using older mechanism
2951                          * of OPTYPE based flashing
2952                          */
2953                         if (flash_optype == OPTYPE_OFFSET_SPECIFIED) {
2954                                 flash_offset_support = false;
2955                                 goto retry_flash;
2956                         }
2957
2958                         /* The current FW image on the card does not recognize
2959                          * the new FLASH op_type. The FW download is partially
2960                          * complete. Reboot the server now to enable FW image
2961                          * to recognize the new FLASH op_type. To complete the
2962                          * remaining process, download the same FW again after
2963                          * the reboot.
2964                          */
2965                         dev_err(dev, "Flash incomplete. Reset the server\n");
2966                         dev_err(dev, "Download FW image again after reset\n");
2967                         return -EAGAIN;
2968                 } else if (status) {
2969                         dev_err(dev, "Could not get CRC for 0x%x region\n",
2970                                 img_optype);
2971                         return -EFAULT;
2972                 }
2973
2974                 if (crc_match)
2975                         continue;
2976
2977 flash:
2978                 p = fw->data + filehdr_size + img_offset + img_hdrs_size;
2979                 if (p + img_size > fw->data + fw->size)
2980                         return -1;
2981
2982                 status = be_flash(adapter, p, flash_cmd, flash_optype, img_size,
2983                                   img_offset);
2984
2985                 /* The current FW image on the card does not support OFFSET
2986                  * based flashing. Retry using older mechanism of OPTYPE based
2987                  * flashing
2988                  */
2989                 if (base_status(status) == MCC_STATUS_ILLEGAL_FIELD &&
2990                     flash_optype == OPTYPE_OFFSET_SPECIFIED) {
2991                         flash_offset_support = false;
2992                         goto retry_flash;
2993                 }
2994
2995                 /* For old FW images ignore ILLEGAL_FIELD error or errors on
2996                  * UFI_DIR region
2997                  */
2998                 if (old_fw_img &&
2999                     (base_status(status) == MCC_STATUS_ILLEGAL_FIELD ||
3000                      (img_optype == OPTYPE_UFI_DIR &&
3001                       base_status(status) == MCC_STATUS_FAILED))) {
3002                         continue;
3003                 } else if (status) {
3004                         dev_err(dev, "Flashing section type 0x%x failed\n",
3005                                 img_type);
3006
3007                         switch (addl_status(status)) {
3008                         case MCC_ADDL_STATUS_MISSING_SIGNATURE:
3009                                 dev_err(dev,
3010                                         "Digital signature missing in FW\n");
3011                                 return -EINVAL;
3012                         case MCC_ADDL_STATUS_INVALID_SIGNATURE:
3013                                 dev_err(dev,
3014                                         "Invalid digital signature in FW\n");
3015                                 return -EINVAL;
3016                         default:
3017                                 return -EFAULT;
3018                         }
3019                 }
3020         }
3021         return 0;
3022 }
3023
3024 int lancer_fw_download(struct be_adapter *adapter,
3025                        const struct firmware *fw)
3026 {
3027         struct device *dev = &adapter->pdev->dev;
3028         struct be_dma_mem flash_cmd;
3029         const u8 *data_ptr = NULL;
3030         u8 *dest_image_ptr = NULL;
3031         size_t image_size = 0;
3032         u32 chunk_size = 0;
3033         u32 data_written = 0;
3034         u32 offset = 0;
3035         int status = 0;
3036         u8 add_status = 0;
3037         u8 change_status;
3038
3039         if (!IS_ALIGNED(fw->size, sizeof(u32))) {
3040                 dev_err(dev, "FW image size should be multiple of 4\n");
3041                 return -EINVAL;
3042         }
3043
3044         flash_cmd.size = sizeof(struct lancer_cmd_req_write_object)
3045                                 + LANCER_FW_DOWNLOAD_CHUNK;
3046         flash_cmd.va = dma_zalloc_coherent(dev, flash_cmd.size,
3047                                            &flash_cmd.dma, GFP_KERNEL);
3048         if (!flash_cmd.va)
3049                 return -ENOMEM;
3050
3051         dest_image_ptr = flash_cmd.va +
3052                                 sizeof(struct lancer_cmd_req_write_object);
3053         image_size = fw->size;
3054         data_ptr = fw->data;
3055
3056         while (image_size) {
3057                 chunk_size = min_t(u32, image_size, LANCER_FW_DOWNLOAD_CHUNK);
3058
3059                 /* Copy the image chunk content. */
3060                 memcpy(dest_image_ptr, data_ptr, chunk_size);
3061
3062                 status = lancer_cmd_write_object(adapter, &flash_cmd,
3063                                                  chunk_size, offset,
3064                                                  LANCER_FW_DOWNLOAD_LOCATION,
3065                                                  &data_written, &change_status,
3066                                                  &add_status);
3067                 if (status)
3068                         break;
3069
3070                 offset += data_written;
3071                 data_ptr += data_written;
3072                 image_size -= data_written;
3073         }
3074
3075         if (!status) {
3076                 /* Commit the FW written */
3077                 status = lancer_cmd_write_object(adapter, &flash_cmd,
3078                                                  0, offset,
3079                                                  LANCER_FW_DOWNLOAD_LOCATION,
3080                                                  &data_written, &change_status,
3081                                                  &add_status);
3082         }
3083
3084         dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma);
3085         if (status) {
3086                 dev_err(dev, "Firmware load error\n");
3087                 return be_cmd_status(status);
3088         }
3089
3090         dev_info(dev, "Firmware flashed successfully\n");
3091
3092         if (change_status == LANCER_FW_RESET_NEEDED) {
3093                 dev_info(dev, "Resetting adapter to activate new FW\n");
3094                 status = lancer_physdev_ctrl(adapter,
3095                                              PHYSDEV_CONTROL_FW_RESET_MASK);
3096                 if (status) {
3097                         dev_err(dev, "Adapter busy, could not reset FW\n");
3098                         dev_err(dev, "Reboot server to activate new FW\n");
3099                 }
3100         } else if (change_status != LANCER_NO_RESET_NEEDED) {
3101                 dev_info(dev, "Reboot server to activate new FW\n");
3102         }
3103
3104         return 0;
3105 }
3106
3107 /* Check if the flash image file is compatible with the adapter that
3108  * is being flashed.
3109  */
3110 static bool be_check_ufi_compatibility(struct be_adapter *adapter,
3111                                        struct flash_file_hdr_g3 *fhdr)
3112 {
3113         if (!fhdr) {
3114                 dev_err(&adapter->pdev->dev, "Invalid FW UFI file");
3115                 return false;
3116         }
3117
3118         /* First letter of the build version is used to identify
3119          * which chip this image file is meant for.
3120          */
3121         switch (fhdr->build[0]) {
3122         case BLD_STR_UFI_TYPE_SH:
3123                 if (!skyhawk_chip(adapter))
3124                         return false;
3125                 break;
3126         case BLD_STR_UFI_TYPE_BE3:
3127                 if (!BE3_chip(adapter))
3128                         return false;
3129                 break;
3130         case BLD_STR_UFI_TYPE_BE2:
3131                 if (!BE2_chip(adapter))
3132                         return false;
3133                 break;
3134         default:
3135                 return false;
3136         }
3137
3138         /* In BE3 FW images the "asic_type_rev" field doesn't track the
3139          * asic_rev of the chips it is compatible with.
3140          * When asic_type_rev is 0 the image is compatible only with
3141          * pre-BE3-R chips (asic_rev < 0x10)
3142          */
3143         if (BEx_chip(adapter) && fhdr->asic_type_rev == 0)
3144                 return adapter->asic_rev < 0x10;
3145         else
3146                 return (fhdr->asic_type_rev >= adapter->asic_rev);
3147 }
3148
3149 int be_fw_download(struct be_adapter *adapter, const struct firmware *fw)
3150 {
3151         struct device *dev = &adapter->pdev->dev;
3152         struct flash_file_hdr_g3 *fhdr3;
3153         struct image_hdr *img_hdr_ptr;
3154         int status = 0, i, num_imgs;
3155         struct be_dma_mem flash_cmd;
3156
3157         fhdr3 = (struct flash_file_hdr_g3 *)fw->data;
3158         if (!be_check_ufi_compatibility(adapter, fhdr3)) {
3159                 dev_err(dev, "Flash image is not compatible with adapter\n");
3160                 return -EINVAL;
3161         }
3162
3163         flash_cmd.size = sizeof(struct be_cmd_write_flashrom);
3164         flash_cmd.va = dma_zalloc_coherent(dev, flash_cmd.size, &flash_cmd.dma,
3165                                            GFP_KERNEL);
3166         if (!flash_cmd.va)
3167                 return -ENOMEM;
3168
3169         num_imgs = le32_to_cpu(fhdr3->num_imgs);
3170         for (i = 0; i < num_imgs; i++) {
3171                 img_hdr_ptr = (struct image_hdr *)(fw->data +
3172                                 (sizeof(struct flash_file_hdr_g3) +
3173                                  i * sizeof(struct image_hdr)));
3174                 if (!BE2_chip(adapter) &&
3175                     le32_to_cpu(img_hdr_ptr->imageid) != 1)
3176                         continue;
3177
3178                 if (skyhawk_chip(adapter))
3179                         status = be_flash_skyhawk(adapter, fw, &flash_cmd,
3180                                                   num_imgs);
3181                 else
3182                         status = be_flash_BEx(adapter, fw, &flash_cmd,
3183                                               num_imgs);
3184         }
3185
3186         dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma);
3187         if (!status)
3188                 dev_info(dev, "Firmware flashed successfully\n");
3189
3190         return status;
3191 }
3192
3193 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
3194                             struct be_dma_mem *nonemb_cmd)
3195 {
3196         struct be_mcc_wrb *wrb;
3197         struct be_cmd_req_acpi_wol_magic_config *req;
3198         int status;
3199
3200         mutex_lock(&adapter->mcc_lock);
3201
3202         wrb = wrb_from_mccq(adapter);
3203         if (!wrb) {
3204                 status = -EBUSY;
3205                 goto err;
3206         }
3207         req = nonemb_cmd->va;
3208
3209         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
3210                                OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req),
3211                                wrb, nonemb_cmd);
3212         memcpy(req->magic_mac, mac, ETH_ALEN);
3213
3214         status = be_mcc_notify_wait(adapter);
3215
3216 err:
3217         mutex_unlock(&adapter->mcc_lock);
3218         return status;
3219 }
3220
3221 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
3222                         u8 loopback_type, u8 enable)
3223 {
3224         struct be_mcc_wrb *wrb;
3225         struct be_cmd_req_set_lmode *req;
3226         int status;
3227
3228         if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
3229                             CMD_SUBSYSTEM_LOWLEVEL))
3230                 return -EPERM;
3231
3232         mutex_lock(&adapter->mcc_lock);
3233
3234         wrb = wrb_from_mccq(adapter);
3235         if (!wrb) {
3236                 status = -EBUSY;
3237                 goto err_unlock;
3238         }
3239
3240         req = embedded_payload(wrb);
3241
3242         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
3243                                OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req),
3244                                wrb, NULL);
3245
3246         req->src_port = port_num;
3247         req->dest_port = port_num;
3248         req->loopback_type = loopback_type;
3249         req->loopback_state = enable;
3250
3251         status = be_mcc_notify(adapter);
3252         if (status)
3253                 goto err_unlock;
3254
3255         mutex_unlock(&adapter->mcc_lock);
3256
3257         if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
3258                                          msecs_to_jiffies(SET_LB_MODE_TIMEOUT)))
3259                 status = -ETIMEDOUT;
3260
3261         return status;
3262
3263 err_unlock:
3264         mutex_unlock(&adapter->mcc_lock);
3265         return status;
3266 }
3267
3268 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
3269                          u32 loopback_type, u32 pkt_size, u32 num_pkts,
3270                          u64 pattern)
3271 {
3272         struct be_mcc_wrb *wrb;
3273         struct be_cmd_req_loopback_test *req;
3274         struct be_cmd_resp_loopback_test *resp;
3275         int status;
3276
3277         if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_LOOPBACK_TEST,
3278                             CMD_SUBSYSTEM_LOWLEVEL))
3279                 return -EPERM;
3280
3281         mutex_lock(&adapter->mcc_lock);
3282
3283         wrb = wrb_from_mccq(adapter);
3284         if (!wrb) {
3285                 status = -EBUSY;
3286                 goto err;
3287         }
3288
3289         req = embedded_payload(wrb);
3290
3291         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
3292                                OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb,
3293                                NULL);
3294
3295         req->hdr.timeout = cpu_to_le32(15);
3296         req->pattern = cpu_to_le64(pattern);
3297         req->src_port = cpu_to_le32(port_num);
3298         req->dest_port = cpu_to_le32(port_num);
3299         req->pkt_size = cpu_to_le32(pkt_size);
3300         req->num_pkts = cpu_to_le32(num_pkts);
3301         req->loopback_type = cpu_to_le32(loopback_type);
3302
3303         status = be_mcc_notify(adapter);
3304         if (status)
3305                 goto err;
3306
3307         mutex_unlock(&adapter->mcc_lock);
3308
3309         wait_for_completion(&adapter->et_cmd_compl);
3310         resp = embedded_payload(wrb);
3311         status = le32_to_cpu(resp->status);
3312
3313         return status;
3314 err:
3315         mutex_unlock(&adapter->mcc_lock);
3316         return status;
3317 }
3318
3319 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
3320                         u32 byte_cnt, struct be_dma_mem *cmd)
3321 {
3322         struct be_mcc_wrb *wrb;
3323         struct be_cmd_req_ddrdma_test *req;
3324         int status;
3325         int i, j = 0;
3326
3327         if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_HOST_DDR_DMA,
3328                             CMD_SUBSYSTEM_LOWLEVEL))
3329                 return -EPERM;
3330
3331         mutex_lock(&adapter->mcc_lock);
3332
3333         wrb = wrb_from_mccq(adapter);
3334         if (!wrb) {
3335                 status = -EBUSY;
3336                 goto err;
3337         }
3338         req = cmd->va;
3339         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
3340                                OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb,
3341                                cmd);
3342
3343         req->pattern = cpu_to_le64(pattern);
3344         req->byte_count = cpu_to_le32(byte_cnt);
3345         for (i = 0; i < byte_cnt; i++) {
3346                 req->snd_buff[i] = (u8)(pattern >> (j*8));
3347                 j++;
3348                 if (j > 7)
3349                         j = 0;
3350         }
3351
3352         status = be_mcc_notify_wait(adapter);
3353
3354         if (!status) {
3355                 struct be_cmd_resp_ddrdma_test *resp;
3356
3357                 resp = cmd->va;
3358                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
3359                     resp->snd_err) {
3360                         status = -1;
3361                 }
3362         }
3363
3364 err:
3365         mutex_unlock(&adapter->mcc_lock);
3366         return status;
3367 }
3368
3369 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
3370                             struct be_dma_mem *nonemb_cmd)
3371 {
3372         struct be_mcc_wrb *wrb;
3373         struct be_cmd_req_seeprom_read *req;
3374         int status;
3375
3376         mutex_lock(&adapter->mcc_lock);
3377
3378         wrb = wrb_from_mccq(adapter);
3379         if (!wrb) {
3380                 status = -EBUSY;
3381                 goto err;
3382         }
3383         req = nonemb_cmd->va;
3384
3385         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3386                                OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
3387                                nonemb_cmd);
3388
3389         status = be_mcc_notify_wait(adapter);
3390
3391 err:
3392         mutex_unlock(&adapter->mcc_lock);
3393         return status;
3394 }
3395
3396 int be_cmd_get_phy_info(struct be_adapter *adapter)
3397 {
3398         struct be_mcc_wrb *wrb;
3399         struct be_cmd_req_get_phy_info *req;
3400         struct be_dma_mem cmd;
3401         int status;
3402
3403         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
3404                             CMD_SUBSYSTEM_COMMON))
3405                 return -EPERM;
3406
3407         mutex_lock(&adapter->mcc_lock);
3408
3409         wrb = wrb_from_mccq(adapter);
3410         if (!wrb) {
3411                 status = -EBUSY;
3412                 goto err;
3413         }
3414         cmd.size = sizeof(struct be_cmd_req_get_phy_info);
3415         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3416                                      GFP_ATOMIC);
3417         if (!cmd.va) {
3418                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3419                 status = -ENOMEM;
3420                 goto err;
3421         }
3422
3423         req = cmd.va;
3424
3425         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3426                                OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
3427                                wrb, &cmd);
3428
3429         status = be_mcc_notify_wait(adapter);
3430         if (!status) {
3431                 struct be_phy_info *resp_phy_info =
3432                                 cmd.va + sizeof(struct be_cmd_req_hdr);
3433
3434                 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
3435                 adapter->phy.interface_type =
3436                         le16_to_cpu(resp_phy_info->interface_type);
3437                 adapter->phy.auto_speeds_supported =
3438                         le16_to_cpu(resp_phy_info->auto_speeds_supported);
3439                 adapter->phy.fixed_speeds_supported =
3440                         le16_to_cpu(resp_phy_info->fixed_speeds_supported);
3441                 adapter->phy.misc_params =
3442                         le32_to_cpu(resp_phy_info->misc_params);
3443
3444                 if (BE2_chip(adapter)) {
3445                         adapter->phy.fixed_speeds_supported =
3446                                 BE_SUPPORTED_SPEED_10GBPS |
3447                                 BE_SUPPORTED_SPEED_1GBPS;
3448                 }
3449         }
3450         dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
3451 err:
3452         mutex_unlock(&adapter->mcc_lock);
3453         return status;
3454 }
3455
3456 static int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
3457 {
3458         struct be_mcc_wrb *wrb;
3459         struct be_cmd_req_set_qos *req;
3460         int status;
3461
3462         mutex_lock(&adapter->mcc_lock);
3463
3464         wrb = wrb_from_mccq(adapter);
3465         if (!wrb) {
3466                 status = -EBUSY;
3467                 goto err;
3468         }
3469
3470         req = embedded_payload(wrb);
3471
3472         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3473                                OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
3474
3475         req->hdr.domain = domain;
3476         req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
3477         req->max_bps_nic = cpu_to_le32(bps);
3478
3479         status = be_mcc_notify_wait(adapter);
3480
3481 err:
3482         mutex_unlock(&adapter->mcc_lock);
3483         return status;
3484 }
3485
3486 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
3487 {
3488         struct be_mcc_wrb *wrb;
3489         struct be_cmd_req_cntl_attribs *req;
3490         struct be_cmd_resp_cntl_attribs *resp;
3491         int status, i;
3492         int payload_len = max(sizeof(*req), sizeof(*resp));
3493         struct mgmt_controller_attrib *attribs;
3494         struct be_dma_mem attribs_cmd;
3495         u32 *serial_num;
3496
3497         if (mutex_lock_interruptible(&adapter->mbox_lock))
3498                 return -1;
3499
3500         memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
3501         attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
3502         attribs_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3503                                              attribs_cmd.size,
3504                                              &attribs_cmd.dma, GFP_ATOMIC);
3505         if (!attribs_cmd.va) {
3506                 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
3507                 status = -ENOMEM;
3508                 goto err;
3509         }
3510
3511         wrb = wrb_from_mbox(adapter);
3512         if (!wrb) {
3513                 status = -EBUSY;
3514                 goto err;
3515         }
3516         req = attribs_cmd.va;
3517
3518         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3519                                OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len,
3520                                wrb, &attribs_cmd);
3521
3522         status = be_mbox_notify_wait(adapter);
3523         if (!status) {
3524                 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
3525                 adapter->hba_port_num = attribs->hba_attribs.phy_port;
3526                 serial_num = attribs->hba_attribs.controller_serial_number;
3527                 for (i = 0; i < CNTL_SERIAL_NUM_WORDS; i++)
3528                         adapter->serial_num[i] = le32_to_cpu(serial_num[i]) &
3529                                 (BIT_MASK(16) - 1);
3530                 /* For BEx, since GET_FUNC_CONFIG command is not
3531                  * supported, we read funcnum here as a workaround.
3532                  */
3533                 if (BEx_chip(adapter))
3534                         adapter->pf_num = attribs->hba_attribs.pci_funcnum;
3535         }
3536
3537 err:
3538         mutex_unlock(&adapter->mbox_lock);
3539         if (attribs_cmd.va)
3540                 dma_free_coherent(&adapter->pdev->dev, attribs_cmd.size,
3541                                   attribs_cmd.va, attribs_cmd.dma);
3542         return status;
3543 }
3544
3545 /* Uses mbox */
3546 int be_cmd_req_native_mode(struct be_adapter *adapter)
3547 {
3548         struct be_mcc_wrb *wrb;
3549         struct be_cmd_req_set_func_cap *req;
3550         int status;
3551
3552         if (mutex_lock_interruptible(&adapter->mbox_lock))
3553                 return -1;
3554
3555         wrb = wrb_from_mbox(adapter);
3556         if (!wrb) {
3557                 status = -EBUSY;
3558                 goto err;
3559         }
3560
3561         req = embedded_payload(wrb);
3562
3563         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3564                                OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP,
3565                                sizeof(*req), wrb, NULL);
3566
3567         req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
3568                                 CAPABILITY_BE3_NATIVE_ERX_API);
3569         req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
3570
3571         status = be_mbox_notify_wait(adapter);
3572         if (!status) {
3573                 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
3574
3575                 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
3576                                         CAPABILITY_BE3_NATIVE_ERX_API;
3577                 if (!adapter->be3_native)
3578                         dev_warn(&adapter->pdev->dev,
3579                                  "adapter not in advanced mode\n");
3580         }
3581 err:
3582         mutex_unlock(&adapter->mbox_lock);
3583         return status;
3584 }
3585
3586 /* Get privilege(s) for a function */
3587 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
3588                              u32 domain)
3589 {
3590         struct be_mcc_wrb *wrb;
3591         struct be_cmd_req_get_fn_privileges *req;
3592         int status;
3593
3594         mutex_lock(&adapter->mcc_lock);
3595
3596         wrb = wrb_from_mccq(adapter);
3597         if (!wrb) {
3598                 status = -EBUSY;
3599                 goto err;
3600         }
3601
3602         req = embedded_payload(wrb);
3603
3604         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3605                                OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
3606                                wrb, NULL);
3607
3608         req->hdr.domain = domain;
3609
3610         status = be_mcc_notify_wait(adapter);
3611         if (!status) {
3612                 struct be_cmd_resp_get_fn_privileges *resp =
3613                                                 embedded_payload(wrb);
3614
3615                 *privilege = le32_to_cpu(resp->privilege_mask);
3616
3617                 /* In UMC mode FW does not return right privileges.
3618                  * Override with correct privilege equivalent to PF.
3619                  */
3620                 if (BEx_chip(adapter) && be_is_mc(adapter) &&
3621                     be_physfn(adapter))
3622                         *privilege = MAX_PRIVILEGES;
3623         }
3624
3625 err:
3626         mutex_unlock(&adapter->mcc_lock);
3627         return status;
3628 }
3629
3630 /* Set privilege(s) for a function */
3631 int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
3632                              u32 domain)
3633 {
3634         struct be_mcc_wrb *wrb;
3635         struct be_cmd_req_set_fn_privileges *req;
3636         int status;
3637
3638         mutex_lock(&adapter->mcc_lock);
3639
3640         wrb = wrb_from_mccq(adapter);
3641         if (!wrb) {
3642                 status = -EBUSY;
3643                 goto err;
3644         }
3645
3646         req = embedded_payload(wrb);
3647         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3648                                OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
3649                                wrb, NULL);
3650         req->hdr.domain = domain;
3651         if (lancer_chip(adapter))
3652                 req->privileges_lancer = cpu_to_le32(privileges);
3653         else
3654                 req->privileges = cpu_to_le32(privileges);
3655
3656         status = be_mcc_notify_wait(adapter);
3657 err:
3658         mutex_unlock(&adapter->mcc_lock);
3659         return status;
3660 }
3661
3662 /* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
3663  * pmac_id_valid: false => pmac_id or MAC address is requested.
3664  *                If pmac_id is returned, pmac_id_valid is returned as true
3665  */
3666 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
3667                              bool *pmac_id_valid, u32 *pmac_id, u32 if_handle,
3668                              u8 domain)
3669 {
3670         struct be_mcc_wrb *wrb;
3671         struct be_cmd_req_get_mac_list *req;
3672         int status;
3673         int mac_count;
3674         struct be_dma_mem get_mac_list_cmd;
3675         int i;
3676
3677         memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
3678         get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
3679         get_mac_list_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3680                                                   get_mac_list_cmd.size,
3681                                                   &get_mac_list_cmd.dma,
3682                                                   GFP_ATOMIC);
3683
3684         if (!get_mac_list_cmd.va) {
3685                 dev_err(&adapter->pdev->dev,
3686                         "Memory allocation failure during GET_MAC_LIST\n");
3687                 return -ENOMEM;
3688         }
3689
3690         mutex_lock(&adapter->mcc_lock);
3691
3692         wrb = wrb_from_mccq(adapter);
3693         if (!wrb) {
3694                 status = -EBUSY;
3695                 goto out;
3696         }
3697
3698         req = get_mac_list_cmd.va;
3699
3700         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3701                                OPCODE_COMMON_GET_MAC_LIST,
3702                                get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
3703         req->hdr.domain = domain;
3704         req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
3705         if (*pmac_id_valid) {
3706                 req->mac_id = cpu_to_le32(*pmac_id);
3707                 req->iface_id = cpu_to_le16(if_handle);
3708                 req->perm_override = 0;
3709         } else {
3710                 req->perm_override = 1;
3711         }
3712
3713         status = be_mcc_notify_wait(adapter);
3714         if (!status) {
3715                 struct be_cmd_resp_get_mac_list *resp =
3716                                                 get_mac_list_cmd.va;
3717
3718                 if (*pmac_id_valid) {
3719                         memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
3720                                ETH_ALEN);
3721                         goto out;
3722                 }
3723
3724                 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
3725                 /* Mac list returned could contain one or more active mac_ids
3726                  * or one or more true or pseudo permanent mac addresses.
3727                  * If an active mac_id is present, return first active mac_id
3728                  * found.
3729                  */
3730                 for (i = 0; i < mac_count; i++) {
3731                         struct get_list_macaddr *mac_entry;
3732                         u16 mac_addr_size;
3733                         u32 mac_id;
3734
3735                         mac_entry = &resp->macaddr_list[i];
3736                         mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
3737                         /* mac_id is a 32 bit value and mac_addr size
3738                          * is 6 bytes
3739                          */
3740                         if (mac_addr_size == sizeof(u32)) {
3741                                 *pmac_id_valid = true;
3742                                 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
3743                                 *pmac_id = le32_to_cpu(mac_id);
3744                                 goto out;
3745                         }
3746                 }
3747                 /* If no active mac_id found, return first mac addr */
3748                 *pmac_id_valid = false;
3749                 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
3750                        ETH_ALEN);
3751         }
3752
3753 out:
3754         mutex_unlock(&adapter->mcc_lock);
3755         dma_free_coherent(&adapter->pdev->dev, get_mac_list_cmd.size,
3756                           get_mac_list_cmd.va, get_mac_list_cmd.dma);
3757         return status;
3758 }
3759
3760 int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id,
3761                           u8 *mac, u32 if_handle, bool active, u32 domain)
3762 {
3763         if (!active)
3764                 be_cmd_get_mac_from_list(adapter, mac, &active, &curr_pmac_id,
3765                                          if_handle, domain);
3766         if (BEx_chip(adapter))
3767                 return be_cmd_mac_addr_query(adapter, mac, false,
3768                                              if_handle, curr_pmac_id);
3769         else
3770                 /* Fetch the MAC address using pmac_id */
3771                 return be_cmd_get_mac_from_list(adapter, mac, &active,
3772                                                 &curr_pmac_id,
3773                                                 if_handle, domain);
3774 }
3775
3776 int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
3777 {
3778         int status;
3779         bool pmac_valid = false;
3780
3781         eth_zero_addr(mac);
3782
3783         if (BEx_chip(adapter)) {
3784                 if (be_physfn(adapter))
3785                         status = be_cmd_mac_addr_query(adapter, mac, true, 0,
3786                                                        0);
3787                 else
3788                         status = be_cmd_mac_addr_query(adapter, mac, false,
3789                                                        adapter->if_handle, 0);
3790         } else {
3791                 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
3792                                                   NULL, adapter->if_handle, 0);
3793         }
3794
3795         return status;
3796 }
3797
3798 /* Uses synchronous MCCQ */
3799 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
3800                         u8 mac_count, u32 domain)
3801 {
3802         struct be_mcc_wrb *wrb;
3803         struct be_cmd_req_set_mac_list *req;
3804         int status;
3805         struct be_dma_mem cmd;
3806
3807         memset(&cmd, 0, sizeof(struct be_dma_mem));
3808         cmd.size = sizeof(struct be_cmd_req_set_mac_list);
3809         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3810                                      GFP_KERNEL);
3811         if (!cmd.va)
3812                 return -ENOMEM;
3813
3814         mutex_lock(&adapter->mcc_lock);
3815
3816         wrb = wrb_from_mccq(adapter);
3817         if (!wrb) {
3818                 status = -EBUSY;
3819                 goto err;
3820         }
3821
3822         req = cmd.va;
3823         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3824                                OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
3825                                wrb, &cmd);
3826
3827         req->hdr.domain = domain;
3828         req->mac_count = mac_count;
3829         if (mac_count)
3830                 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
3831
3832         status = be_mcc_notify_wait(adapter);
3833
3834 err:
3835         dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
3836         mutex_unlock(&adapter->mcc_lock);
3837         return status;
3838 }
3839
3840 /* Wrapper to delete any active MACs and provision the new mac.
3841  * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
3842  * current list are active.
3843  */
3844 int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
3845 {
3846         bool active_mac = false;
3847         u8 old_mac[ETH_ALEN];
3848         u32 pmac_id;
3849         int status;
3850
3851         status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
3852                                           &pmac_id, if_id, dom);
3853
3854         if (!status && active_mac)
3855                 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
3856
3857         return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
3858 }
3859
3860 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
3861                           u32 domain, u16 intf_id, u16 hsw_mode, u8 spoofchk)
3862 {
3863         struct be_mcc_wrb *wrb;
3864         struct be_cmd_req_set_hsw_config *req;
3865         void *ctxt;
3866         int status;
3867
3868         if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_HSW_CONFIG,
3869                             CMD_SUBSYSTEM_COMMON))
3870                 return -EPERM;
3871
3872         mutex_lock(&adapter->mcc_lock);
3873
3874         wrb = wrb_from_mccq(adapter);
3875         if (!wrb) {
3876                 status = -EBUSY;
3877                 goto err;
3878         }
3879
3880         req = embedded_payload(wrb);
3881         ctxt = &req->context;
3882
3883         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3884                                OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb,
3885                                NULL);
3886
3887         req->hdr.domain = domain;
3888         AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
3889         if (pvid) {
3890                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
3891                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
3892         }
3893         if (hsw_mode) {
3894                 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id,
3895                               ctxt, adapter->hba_port_num);
3896                 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1);
3897                 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type,
3898                               ctxt, hsw_mode);
3899         }
3900
3901         /* Enable/disable both mac and vlan spoof checking */
3902         if (!BEx_chip(adapter) && spoofchk) {
3903                 AMAP_SET_BITS(struct amap_set_hsw_context, mac_spoofchk,
3904                               ctxt, spoofchk);
3905                 AMAP_SET_BITS(struct amap_set_hsw_context, vlan_spoofchk,
3906                               ctxt, spoofchk);
3907         }
3908
3909         be_dws_cpu_to_le(req->context, sizeof(req->context));
3910         status = be_mcc_notify_wait(adapter);
3911
3912 err:
3913         mutex_unlock(&adapter->mcc_lock);
3914         return status;
3915 }
3916
3917 /* Get Hyper switch config */
3918 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
3919                           u32 domain, u16 intf_id, u8 *mode, bool *spoofchk)
3920 {
3921         struct be_mcc_wrb *wrb;
3922         struct be_cmd_req_get_hsw_config *req;
3923         void *ctxt;
3924         int status;
3925         u16 vid;
3926
3927         mutex_lock(&adapter->mcc_lock);
3928
3929         wrb = wrb_from_mccq(adapter);
3930         if (!wrb) {
3931                 status = -EBUSY;
3932                 goto err;
3933         }
3934
3935         req = embedded_payload(wrb);
3936         ctxt = &req->context;
3937
3938         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3939                                OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb,
3940                                NULL);
3941
3942         req->hdr.domain = domain;
3943         AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3944                       ctxt, intf_id);
3945         AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
3946
3947         if (!BEx_chip(adapter) && mode) {
3948                 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3949                               ctxt, adapter->hba_port_num);
3950                 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1);
3951         }
3952         be_dws_cpu_to_le(req->context, sizeof(req->context));
3953
3954         status = be_mcc_notify_wait(adapter);
3955         if (!status) {
3956                 struct be_cmd_resp_get_hsw_config *resp =
3957                                                 embedded_payload(wrb);
3958
3959                 be_dws_le_to_cpu(&resp->context, sizeof(resp->context));
3960                 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3961                                     pvid, &resp->context);
3962                 if (pvid)
3963                         *pvid = le16_to_cpu(vid);
3964                 if (mode)
3965                         *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3966                                               port_fwd_type, &resp->context);
3967                 if (spoofchk)
3968                         *spoofchk =
3969                                 AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3970                                               spoofchk, &resp->context);
3971         }
3972
3973 err:
3974         mutex_unlock(&adapter->mcc_lock);
3975         return status;
3976 }
3977
3978 static bool be_is_wol_excluded(struct be_adapter *adapter)
3979 {
3980         struct pci_dev *pdev = adapter->pdev;
3981
3982         if (be_virtfn(adapter))
3983                 return true;
3984
3985         switch (pdev->subsystem_device) {
3986         case OC_SUBSYS_DEVICE_ID1:
3987         case OC_SUBSYS_DEVICE_ID2:
3988         case OC_SUBSYS_DEVICE_ID3:
3989         case OC_SUBSYS_DEVICE_ID4:
3990                 return true;
3991         default:
3992                 return false;
3993         }
3994 }
3995
3996 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
3997 {
3998         struct be_mcc_wrb *wrb;
3999         struct be_cmd_req_acpi_wol_magic_config_v1 *req;
4000         int status = 0;
4001         struct be_dma_mem cmd;
4002
4003         if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
4004                             CMD_SUBSYSTEM_ETH))
4005                 return -EPERM;
4006
4007         if (be_is_wol_excluded(adapter))
4008                 return status;
4009
4010         if (mutex_lock_interruptible(&adapter->mbox_lock))
4011                 return -1;
4012
4013         memset(&cmd, 0, sizeof(struct be_dma_mem));
4014         cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
4015         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4016                                      GFP_ATOMIC);
4017         if (!cmd.va) {
4018                 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
4019                 status = -ENOMEM;
4020                 goto err;
4021         }
4022
4023         wrb = wrb_from_mbox(adapter);
4024         if (!wrb) {
4025                 status = -EBUSY;
4026                 goto err;
4027         }
4028
4029         req = cmd.va;
4030
4031         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
4032                                OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
4033                                sizeof(*req), wrb, &cmd);
4034
4035         req->hdr.version = 1;
4036         req->query_options = BE_GET_WOL_CAP;
4037
4038         status = be_mbox_notify_wait(adapter);
4039         if (!status) {
4040                 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
4041
4042                 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *)cmd.va;
4043
4044                 adapter->wol_cap = resp->wol_settings;
4045
4046                 /* Non-zero macaddr indicates WOL is enabled */
4047                 if (adapter->wol_cap & BE_WOL_CAP &&
4048                     !is_zero_ether_addr(resp->magic_mac))
4049                         adapter->wol_en = true;
4050         }
4051 err:
4052         mutex_unlock(&adapter->mbox_lock);
4053         if (cmd.va)
4054                 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4055                                   cmd.dma);
4056         return status;
4057
4058 }
4059
4060 int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level)
4061 {
4062         struct be_dma_mem extfat_cmd;
4063         struct be_fat_conf_params *cfgs;
4064         int status;
4065         int i, j;
4066
4067         memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
4068         extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
4069         extfat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
4070                                             extfat_cmd.size, &extfat_cmd.dma,
4071                                             GFP_ATOMIC);
4072         if (!extfat_cmd.va)
4073                 return -ENOMEM;
4074
4075         status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
4076         if (status)
4077                 goto err;
4078
4079         cfgs = (struct be_fat_conf_params *)
4080                         (extfat_cmd.va + sizeof(struct be_cmd_resp_hdr));
4081         for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) {
4082                 u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes);
4083
4084                 for (j = 0; j < num_modes; j++) {
4085                         if (cfgs->module[i].trace_lvl[j].mode == MODE_UART)
4086                                 cfgs->module[i].trace_lvl[j].dbg_lvl =
4087                                                         cpu_to_le32(level);
4088                 }
4089         }
4090
4091         status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd, cfgs);
4092 err:
4093         dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
4094                           extfat_cmd.dma);
4095         return status;
4096 }
4097
4098 int be_cmd_get_fw_log_level(struct be_adapter *adapter)
4099 {
4100         struct be_dma_mem extfat_cmd;
4101         struct be_fat_conf_params *cfgs;
4102         int status, j;
4103         int level = 0;
4104
4105         memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
4106         extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
4107         extfat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
4108                                             extfat_cmd.size, &extfat_cmd.dma,
4109                                             GFP_ATOMIC);
4110
4111         if (!extfat_cmd.va) {
4112                 dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
4113                         __func__);
4114                 goto err;
4115         }
4116
4117         status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
4118         if (!status) {
4119                 cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
4120                                                 sizeof(struct be_cmd_resp_hdr));
4121
4122                 for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) {
4123                         if (cfgs->module[0].trace_lvl[j].mode == MODE_UART)
4124                                 level = cfgs->module[0].trace_lvl[j].dbg_lvl;
4125                 }
4126         }
4127         dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
4128                           extfat_cmd.dma);
4129 err:
4130         return level;
4131 }
4132
4133 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
4134                                    struct be_dma_mem *cmd)
4135 {
4136         struct be_mcc_wrb *wrb;
4137         struct be_cmd_req_get_ext_fat_caps *req;
4138         int status;
4139
4140         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_EXT_FAT_CAPABILITIES,
4141                             CMD_SUBSYSTEM_COMMON))
4142                 return -EPERM;
4143
4144         if (mutex_lock_interruptible(&adapter->mbox_lock))
4145                 return -1;
4146
4147         wrb = wrb_from_mbox(adapter);
4148         if (!wrb) {
4149                 status = -EBUSY;
4150                 goto err;
4151         }
4152
4153         req = cmd->va;
4154         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4155                                OPCODE_COMMON_GET_EXT_FAT_CAPABILITIES,
4156                                cmd->size, wrb, cmd);
4157         req->parameter_type = cpu_to_le32(1);
4158
4159         status = be_mbox_notify_wait(adapter);
4160 err:
4161         mutex_unlock(&adapter->mbox_lock);
4162         return status;
4163 }
4164
4165 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
4166                                    struct be_dma_mem *cmd,
4167                                    struct be_fat_conf_params *configs)
4168 {
4169         struct be_mcc_wrb *wrb;
4170         struct be_cmd_req_set_ext_fat_caps *req;
4171         int status;
4172
4173         mutex_lock(&adapter->mcc_lock);
4174
4175         wrb = wrb_from_mccq(adapter);
4176         if (!wrb) {
4177                 status = -EBUSY;
4178                 goto err;
4179         }
4180
4181         req = cmd->va;
4182         memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
4183         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4184                                OPCODE_COMMON_SET_EXT_FAT_CAPABILITIES,
4185                                cmd->size, wrb, cmd);
4186
4187         status = be_mcc_notify_wait(adapter);
4188 err:
4189         mutex_unlock(&adapter->mcc_lock);
4190         return status;
4191 }
4192
4193 int be_cmd_query_port_name(struct be_adapter *adapter)
4194 {
4195         struct be_cmd_req_get_port_name *req;
4196         struct be_mcc_wrb *wrb;
4197         int status;
4198
4199         if (mutex_lock_interruptible(&adapter->mbox_lock))
4200                 return -1;
4201
4202         wrb = wrb_from_mbox(adapter);
4203         req = embedded_payload(wrb);
4204
4205         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4206                                OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
4207                                NULL);
4208         if (!BEx_chip(adapter))
4209                 req->hdr.version = 1;
4210
4211         status = be_mbox_notify_wait(adapter);
4212         if (!status) {
4213                 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
4214
4215                 adapter->port_name = resp->port_name[adapter->hba_port_num];
4216         } else {
4217                 adapter->port_name = adapter->hba_port_num + '0';
4218         }
4219
4220         mutex_unlock(&adapter->mbox_lock);
4221         return status;
4222 }
4223
4224 /* When more than 1 NIC descriptor is present in the descriptor list,
4225  * the caller must specify the pf_num to obtain the NIC descriptor
4226  * corresponding to its pci function.
4227  * get_vft must be true when the caller wants the VF-template desc of the
4228  * PF-pool.
4229  * The pf_num should be set to PF_NUM_IGNORE when the caller knows
4230  * that only it's NIC descriptor is present in the descriptor list.
4231  */
4232 static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
4233                                                bool get_vft, u8 pf_num)
4234 {
4235         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4236         struct be_nic_res_desc *nic;
4237         int i;
4238
4239         for (i = 0; i < desc_count; i++) {
4240                 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
4241                     hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1) {
4242                         nic = (struct be_nic_res_desc *)hdr;
4243
4244                         if ((pf_num == PF_NUM_IGNORE ||
4245                              nic->pf_num == pf_num) &&
4246                             (!get_vft || nic->flags & BIT(VFT_SHIFT)))
4247                                 return nic;
4248                 }
4249                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4250                 hdr = (void *)hdr + hdr->desc_len;
4251         }
4252         return NULL;
4253 }
4254
4255 static struct be_nic_res_desc *be_get_vft_desc(u8 *buf, u32 desc_count,
4256                                                u8 pf_num)
4257 {
4258         return be_get_nic_desc(buf, desc_count, true, pf_num);
4259 }
4260
4261 static struct be_nic_res_desc *be_get_func_nic_desc(u8 *buf, u32 desc_count,
4262                                                     u8 pf_num)
4263 {
4264         return be_get_nic_desc(buf, desc_count, false, pf_num);
4265 }
4266
4267 static struct be_pcie_res_desc *be_get_pcie_desc(u8 *buf, u32 desc_count,
4268                                                  u8 pf_num)
4269 {
4270         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4271         struct be_pcie_res_desc *pcie;
4272         int i;
4273
4274         for (i = 0; i < desc_count; i++) {
4275                 if (hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
4276                     hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1) {
4277                         pcie = (struct be_pcie_res_desc *)hdr;
4278                         if (pcie->pf_num == pf_num)
4279                                 return pcie;
4280                 }
4281
4282                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4283                 hdr = (void *)hdr + hdr->desc_len;
4284         }
4285         return NULL;
4286 }
4287
4288 static struct be_port_res_desc *be_get_port_desc(u8 *buf, u32 desc_count)
4289 {
4290         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4291         int i;
4292
4293         for (i = 0; i < desc_count; i++) {
4294                 if (hdr->desc_type == PORT_RESOURCE_DESC_TYPE_V1)
4295                         return (struct be_port_res_desc *)hdr;
4296
4297                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4298                 hdr = (void *)hdr + hdr->desc_len;
4299         }
4300         return NULL;
4301 }
4302
4303 static void be_copy_nic_desc(struct be_resources *res,
4304                              struct be_nic_res_desc *desc)
4305 {
4306         res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count);
4307         res->max_vlans = le16_to_cpu(desc->vlan_count);
4308         res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
4309         res->max_tx_qs = le16_to_cpu(desc->txq_count);
4310         res->max_rss_qs = le16_to_cpu(desc->rssq_count);
4311         res->max_rx_qs = le16_to_cpu(desc->rq_count);
4312         res->max_evt_qs = le16_to_cpu(desc->eq_count);
4313         res->max_cq_count = le16_to_cpu(desc->cq_count);
4314         res->max_iface_count = le16_to_cpu(desc->iface_count);
4315         res->max_mcc_count = le16_to_cpu(desc->mcc_count);
4316         /* Clear flags that driver is not interested in */
4317         res->if_cap_flags = le32_to_cpu(desc->cap_flags) &
4318                                 BE_IF_CAP_FLAGS_WANT;
4319 }
4320
4321 /* Uses Mbox */
4322 int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res)
4323 {
4324         struct be_mcc_wrb *wrb;
4325         struct be_cmd_req_get_func_config *req;
4326         int status;
4327         struct be_dma_mem cmd;
4328
4329         if (mutex_lock_interruptible(&adapter->mbox_lock))
4330                 return -1;
4331
4332         memset(&cmd, 0, sizeof(struct be_dma_mem));
4333         cmd.size = sizeof(struct be_cmd_resp_get_func_config);
4334         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4335                                      GFP_ATOMIC);
4336         if (!cmd.va) {
4337                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
4338                 status = -ENOMEM;
4339                 goto err;
4340         }
4341
4342         wrb = wrb_from_mbox(adapter);
4343         if (!wrb) {
4344                 status = -EBUSY;
4345                 goto err;
4346         }
4347
4348         req = cmd.va;
4349
4350         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4351                                OPCODE_COMMON_GET_FUNC_CONFIG,
4352                                cmd.size, wrb, &cmd);
4353
4354         if (skyhawk_chip(adapter))
4355                 req->hdr.version = 1;
4356
4357         status = be_mbox_notify_wait(adapter);
4358         if (!status) {
4359                 struct be_cmd_resp_get_func_config *resp = cmd.va;
4360                 u32 desc_count = le32_to_cpu(resp->desc_count);
4361                 struct be_nic_res_desc *desc;
4362
4363                 /* GET_FUNC_CONFIG returns resource descriptors of the
4364                  * current function only. So, pf_num should be set to
4365                  * PF_NUM_IGNORE.
4366                  */
4367                 desc = be_get_func_nic_desc(resp->func_param, desc_count,
4368                                             PF_NUM_IGNORE);
4369                 if (!desc) {
4370                         status = -EINVAL;
4371                         goto err;
4372                 }
4373
4374                 /* Store pf_num & vf_num for later use in GET_PROFILE_CONFIG */
4375                 adapter->pf_num = desc->pf_num;
4376                 adapter->vf_num = desc->vf_num;
4377
4378                 if (res)
4379                         be_copy_nic_desc(res, desc);
4380         }
4381 err:
4382         mutex_unlock(&adapter->mbox_lock);
4383         if (cmd.va)
4384                 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4385                                   cmd.dma);
4386         return status;
4387 }
4388
4389 /* This routine returns a list of all the NIC PF_nums in the adapter */
4390 static u16 be_get_nic_pf_num_list(u8 *buf, u32 desc_count, u16 *nic_pf_nums)
4391 {
4392         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4393         struct be_pcie_res_desc *pcie = NULL;
4394         int i;
4395         u16 nic_pf_count = 0;
4396
4397         for (i = 0; i < desc_count; i++) {
4398                 if (hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
4399                     hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1) {
4400                         pcie = (struct be_pcie_res_desc *)hdr;
4401                         if (pcie->pf_state && (pcie->pf_type == MISSION_NIC ||
4402                                                pcie->pf_type == MISSION_RDMA)) {
4403                                 nic_pf_nums[nic_pf_count++] = pcie->pf_num;
4404                         }
4405                 }
4406
4407                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4408                 hdr = (void *)hdr + hdr->desc_len;
4409         }
4410         return nic_pf_count;
4411 }
4412
4413 /* Will use MBOX only if MCCQ has not been created */
4414 int be_cmd_get_profile_config(struct be_adapter *adapter,
4415                               struct be_resources *res,
4416                               struct be_port_resources *port_res,
4417                               u8 profile_type, u8 query, u8 domain)
4418 {
4419         struct be_cmd_resp_get_profile_config *resp;
4420         struct be_cmd_req_get_profile_config *req;
4421         struct be_nic_res_desc *vf_res;
4422         struct be_pcie_res_desc *pcie;
4423         struct be_port_res_desc *port;
4424         struct be_nic_res_desc *nic;
4425         struct be_mcc_wrb wrb = {0};
4426         struct be_dma_mem cmd;
4427         u16 desc_count;
4428         int status;
4429
4430         memset(&cmd, 0, sizeof(struct be_dma_mem));
4431         cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
4432         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4433                                      GFP_ATOMIC);
4434         if (!cmd.va)
4435                 return -ENOMEM;
4436
4437         req = cmd.va;
4438         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4439                                OPCODE_COMMON_GET_PROFILE_CONFIG,
4440                                cmd.size, &wrb, &cmd);
4441
4442         if (!lancer_chip(adapter))
4443                 req->hdr.version = 1;
4444         req->type = profile_type;
4445         req->hdr.domain = domain;
4446
4447         /* When QUERY_MODIFIABLE_FIELDS_TYPE bit is set, cmd returns the
4448          * descriptors with all bits set to "1" for the fields which can be
4449          * modified using SET_PROFILE_CONFIG cmd.
4450          */
4451         if (query == RESOURCE_MODIFIABLE)
4452                 req->type |= QUERY_MODIFIABLE_FIELDS_TYPE;
4453
4454         status = be_cmd_notify_wait(adapter, &wrb);
4455         if (status)
4456                 goto err;
4457
4458         resp = cmd.va;
4459         desc_count = le16_to_cpu(resp->desc_count);
4460
4461         if (port_res) {
4462                 u16 nic_pf_cnt = 0, i;
4463                 u16 nic_pf_num_list[MAX_NIC_FUNCS];
4464
4465                 nic_pf_cnt = be_get_nic_pf_num_list(resp->func_param,
4466                                                     desc_count,
4467                                                     nic_pf_num_list);
4468
4469                 for (i = 0; i < nic_pf_cnt; i++) {
4470                         nic = be_get_func_nic_desc(resp->func_param, desc_count,
4471                                                    nic_pf_num_list[i]);
4472                         if (nic->link_param == adapter->port_num) {
4473                                 port_res->nic_pfs++;
4474                                 pcie = be_get_pcie_desc(resp->func_param,
4475                                                         desc_count,
4476                                                         nic_pf_num_list[i]);
4477                                 port_res->max_vfs += le16_to_cpu(pcie->num_vfs);
4478                         }
4479                 }
4480                 return status;
4481         }
4482
4483         pcie = be_get_pcie_desc(resp->func_param, desc_count,
4484                                 adapter->pf_num);
4485         if (pcie)
4486                 res->max_vfs = le16_to_cpu(pcie->num_vfs);
4487
4488         port = be_get_port_desc(resp->func_param, desc_count);
4489         if (port)
4490                 adapter->mc_type = port->mc_type;
4491
4492         nic = be_get_func_nic_desc(resp->func_param, desc_count,
4493                                    adapter->pf_num);
4494         if (nic)
4495                 be_copy_nic_desc(res, nic);
4496
4497         vf_res = be_get_vft_desc(resp->func_param, desc_count,
4498                                  adapter->pf_num);
4499         if (vf_res)
4500                 res->vf_if_cap_flags = vf_res->cap_flags;
4501 err:
4502         if (cmd.va)
4503                 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4504                                   cmd.dma);
4505         return status;
4506 }
4507
4508 /* Will use MBOX only if MCCQ has not been created */
4509 static int be_cmd_set_profile_config(struct be_adapter *adapter, void *desc,
4510                                      int size, int count, u8 version, u8 domain)
4511 {
4512         struct be_cmd_req_set_profile_config *req;
4513         struct be_mcc_wrb wrb = {0};
4514         struct be_dma_mem cmd;
4515         int status;
4516
4517         memset(&cmd, 0, sizeof(struct be_dma_mem));
4518         cmd.size = sizeof(struct be_cmd_req_set_profile_config);
4519         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4520                                      GFP_ATOMIC);
4521         if (!cmd.va)
4522                 return -ENOMEM;
4523
4524         req = cmd.va;
4525         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4526                                OPCODE_COMMON_SET_PROFILE_CONFIG, cmd.size,
4527                                &wrb, &cmd);
4528         req->hdr.version = version;
4529         req->hdr.domain = domain;
4530         req->desc_count = cpu_to_le32(count);
4531         memcpy(req->desc, desc, size);
4532
4533         status = be_cmd_notify_wait(adapter, &wrb);
4534
4535         if (cmd.va)
4536                 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4537                                   cmd.dma);
4538         return status;
4539 }
4540
4541 /* Mark all fields invalid */
4542 static void be_reset_nic_desc(struct be_nic_res_desc *nic)
4543 {
4544         memset(nic, 0, sizeof(*nic));
4545         nic->unicast_mac_count = 0xFFFF;
4546         nic->mcc_count = 0xFFFF;
4547         nic->vlan_count = 0xFFFF;
4548         nic->mcast_mac_count = 0xFFFF;
4549         nic->txq_count = 0xFFFF;
4550         nic->rq_count = 0xFFFF;
4551         nic->rssq_count = 0xFFFF;
4552         nic->lro_count = 0xFFFF;
4553         nic->cq_count = 0xFFFF;
4554         nic->toe_conn_count = 0xFFFF;
4555         nic->eq_count = 0xFFFF;
4556         nic->iface_count = 0xFFFF;
4557         nic->link_param = 0xFF;
4558         nic->channel_id_param = cpu_to_le16(0xF000);
4559         nic->acpi_params = 0xFF;
4560         nic->wol_param = 0x0F;
4561         nic->tunnel_iface_count = 0xFFFF;
4562         nic->direct_tenant_iface_count = 0xFFFF;
4563         nic->bw_min = 0xFFFFFFFF;
4564         nic->bw_max = 0xFFFFFFFF;
4565 }
4566
4567 /* Mark all fields invalid */
4568 static void be_reset_pcie_desc(struct be_pcie_res_desc *pcie)
4569 {
4570         memset(pcie, 0, sizeof(*pcie));
4571         pcie->sriov_state = 0xFF;
4572         pcie->pf_state = 0xFF;
4573         pcie->pf_type = 0xFF;
4574         pcie->num_vfs = 0xFFFF;
4575 }
4576
4577 int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, u16 link_speed,
4578                       u8 domain)
4579 {
4580         struct be_nic_res_desc nic_desc;
4581         u32 bw_percent;
4582         u16 version = 0;
4583
4584         if (BE3_chip(adapter))
4585                 return be_cmd_set_qos(adapter, max_rate / 10, domain);
4586
4587         be_reset_nic_desc(&nic_desc);
4588         nic_desc.pf_num = adapter->pf_num;
4589         nic_desc.vf_num = domain;
4590         nic_desc.bw_min = 0;
4591         if (lancer_chip(adapter)) {
4592                 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
4593                 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
4594                 nic_desc.flags = (1 << QUN_SHIFT) | (1 << IMM_SHIFT) |
4595                                         (1 << NOSV_SHIFT);
4596                 nic_desc.bw_max = cpu_to_le32(max_rate / 10);
4597         } else {
4598                 version = 1;
4599                 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
4600                 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4601                 nic_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
4602                 bw_percent = max_rate ? (max_rate * 100) / link_speed : 100;
4603                 nic_desc.bw_max = cpu_to_le32(bw_percent);
4604         }
4605
4606         return be_cmd_set_profile_config(adapter, &nic_desc,
4607                                          nic_desc.hdr.desc_len,
4608                                          1, version, domain);
4609 }
4610
4611 int be_cmd_set_sriov_config(struct be_adapter *adapter,
4612                             struct be_resources pool_res, u16 num_vfs,
4613                             struct be_resources *vft_res)
4614 {
4615         struct {
4616                 struct be_pcie_res_desc pcie;
4617                 struct be_nic_res_desc nic_vft;
4618         } __packed desc;
4619
4620         /* PF PCIE descriptor */
4621         be_reset_pcie_desc(&desc.pcie);
4622         desc.pcie.hdr.desc_type = PCIE_RESOURCE_DESC_TYPE_V1;
4623         desc.pcie.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4624         desc.pcie.flags = BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
4625         desc.pcie.pf_num = adapter->pdev->devfn;
4626         desc.pcie.sriov_state = num_vfs ? 1 : 0;
4627         desc.pcie.num_vfs = cpu_to_le16(num_vfs);
4628
4629         /* VF NIC Template descriptor */
4630         be_reset_nic_desc(&desc.nic_vft);
4631         desc.nic_vft.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
4632         desc.nic_vft.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4633         desc.nic_vft.flags = vft_res->flags | BIT(VFT_SHIFT) |
4634                              BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
4635         desc.nic_vft.pf_num = adapter->pdev->devfn;
4636         desc.nic_vft.vf_num = 0;
4637         desc.nic_vft.cap_flags = cpu_to_le32(vft_res->vf_if_cap_flags);
4638         desc.nic_vft.rq_count = cpu_to_le16(vft_res->max_rx_qs);
4639         desc.nic_vft.txq_count = cpu_to_le16(vft_res->max_tx_qs);
4640         desc.nic_vft.rssq_count = cpu_to_le16(vft_res->max_rss_qs);
4641         desc.nic_vft.cq_count = cpu_to_le16(vft_res->max_cq_count);
4642
4643         if (vft_res->max_uc_mac)
4644                 desc.nic_vft.unicast_mac_count =
4645                                         cpu_to_le16(vft_res->max_uc_mac);
4646         if (vft_res->max_vlans)
4647                 desc.nic_vft.vlan_count = cpu_to_le16(vft_res->max_vlans);
4648         if (vft_res->max_iface_count)
4649                 desc.nic_vft.iface_count =
4650                                 cpu_to_le16(vft_res->max_iface_count);
4651         if (vft_res->max_mcc_count)
4652                 desc.nic_vft.mcc_count = cpu_to_le16(vft_res->max_mcc_count);
4653
4654         return be_cmd_set_profile_config(adapter, &desc,
4655                                          2 * RESOURCE_DESC_SIZE_V1, 2, 1, 0);
4656 }
4657
4658 int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op)
4659 {
4660         struct be_mcc_wrb *wrb;
4661         struct be_cmd_req_manage_iface_filters *req;
4662         int status;
4663
4664         if (iface == 0xFFFFFFFF)
4665                 return -1;
4666
4667         mutex_lock(&adapter->mcc_lock);
4668
4669         wrb = wrb_from_mccq(adapter);
4670         if (!wrb) {
4671                 status = -EBUSY;
4672                 goto err;
4673         }
4674         req = embedded_payload(wrb);
4675
4676         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4677                                OPCODE_COMMON_MANAGE_IFACE_FILTERS, sizeof(*req),
4678                                wrb, NULL);
4679         req->op = op;
4680         req->target_iface_id = cpu_to_le32(iface);
4681
4682         status = be_mcc_notify_wait(adapter);
4683 err:
4684         mutex_unlock(&adapter->mcc_lock);
4685         return status;
4686 }
4687
4688 int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port)
4689 {
4690         struct be_port_res_desc port_desc;
4691
4692         memset(&port_desc, 0, sizeof(port_desc));
4693         port_desc.hdr.desc_type = PORT_RESOURCE_DESC_TYPE_V1;
4694         port_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4695         port_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
4696         port_desc.link_num = adapter->hba_port_num;
4697         if (port) {
4698                 port_desc.nv_flags = NV_TYPE_VXLAN | (1 << SOCVID_SHIFT) |
4699                                         (1 << RCVID_SHIFT);
4700                 port_desc.nv_port = swab16(port);
4701         } else {
4702                 port_desc.nv_flags = NV_TYPE_DISABLED;
4703                 port_desc.nv_port = 0;
4704         }
4705
4706         return be_cmd_set_profile_config(adapter, &port_desc,
4707                                          RESOURCE_DESC_SIZE_V1, 1, 1, 0);
4708 }
4709
4710 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
4711                      int vf_num)
4712 {
4713         struct be_mcc_wrb *wrb;
4714         struct be_cmd_req_get_iface_list *req;
4715         struct be_cmd_resp_get_iface_list *resp;
4716         int status;
4717
4718         mutex_lock(&adapter->mcc_lock);
4719
4720         wrb = wrb_from_mccq(adapter);
4721         if (!wrb) {
4722                 status = -EBUSY;
4723                 goto err;
4724         }
4725         req = embedded_payload(wrb);
4726
4727         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4728                                OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
4729                                wrb, NULL);
4730         req->hdr.domain = vf_num + 1;
4731
4732         status = be_mcc_notify_wait(adapter);
4733         if (!status) {
4734                 resp = (struct be_cmd_resp_get_iface_list *)req;
4735                 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
4736         }
4737
4738 err:
4739         mutex_unlock(&adapter->mcc_lock);
4740         return status;
4741 }
4742
4743 static int lancer_wait_idle(struct be_adapter *adapter)
4744 {
4745 #define SLIPORT_IDLE_TIMEOUT 30
4746         u32 reg_val;
4747         int status = 0, i;
4748
4749         for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
4750                 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
4751                 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
4752                         break;
4753
4754                 ssleep(1);
4755         }
4756
4757         if (i == SLIPORT_IDLE_TIMEOUT)
4758                 status = -1;
4759
4760         return status;
4761 }
4762
4763 int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
4764 {
4765         int status = 0;
4766
4767         status = lancer_wait_idle(adapter);
4768         if (status)
4769                 return status;
4770
4771         iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
4772
4773         return status;
4774 }
4775
4776 /* Routine to check whether dump image is present or not */
4777 bool dump_present(struct be_adapter *adapter)
4778 {
4779         u32 sliport_status = 0;
4780
4781         sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
4782         return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
4783 }
4784
4785 int lancer_initiate_dump(struct be_adapter *adapter)
4786 {
4787         struct device *dev = &adapter->pdev->dev;
4788         int status;
4789
4790         if (dump_present(adapter)) {
4791                 dev_info(dev, "Previous dump not cleared, not forcing dump\n");
4792                 return -EEXIST;
4793         }
4794
4795         /* give firmware reset and diagnostic dump */
4796         status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
4797                                      PHYSDEV_CONTROL_DD_MASK);
4798         if (status < 0) {
4799                 dev_err(dev, "FW reset failed\n");
4800                 return status;
4801         }
4802
4803         status = lancer_wait_idle(adapter);
4804         if (status)
4805                 return status;
4806
4807         if (!dump_present(adapter)) {
4808                 dev_err(dev, "FW dump not generated\n");
4809                 return -EIO;
4810         }
4811
4812         return 0;
4813 }
4814
4815 int lancer_delete_dump(struct be_adapter *adapter)
4816 {
4817         int status;
4818
4819         status = lancer_cmd_delete_object(adapter, LANCER_FW_DUMP_FILE);
4820         return be_cmd_status(status);
4821 }
4822
4823 /* Uses sync mcc */
4824 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
4825 {
4826         struct be_mcc_wrb *wrb;
4827         struct be_cmd_enable_disable_vf *req;
4828         int status;
4829
4830         if (BEx_chip(adapter))
4831                 return 0;
4832
4833         mutex_lock(&adapter->mcc_lock);
4834
4835         wrb = wrb_from_mccq(adapter);
4836         if (!wrb) {
4837                 status = -EBUSY;
4838                 goto err;
4839         }
4840
4841         req = embedded_payload(wrb);
4842
4843         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4844                                OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
4845                                wrb, NULL);
4846
4847         req->hdr.domain = domain;
4848         req->enable = 1;
4849         status = be_mcc_notify_wait(adapter);
4850 err:
4851         mutex_unlock(&adapter->mcc_lock);
4852         return status;
4853 }
4854
4855 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
4856 {
4857         struct be_mcc_wrb *wrb;
4858         struct be_cmd_req_intr_set *req;
4859         int status;
4860
4861         if (mutex_lock_interruptible(&adapter->mbox_lock))
4862                 return -1;
4863
4864         wrb = wrb_from_mbox(adapter);
4865
4866         req = embedded_payload(wrb);
4867
4868         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4869                                OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
4870                                wrb, NULL);
4871
4872         req->intr_enabled = intr_enable;
4873
4874         status = be_mbox_notify_wait(adapter);
4875
4876         mutex_unlock(&adapter->mbox_lock);
4877         return status;
4878 }
4879
4880 /* Uses MBOX */
4881 int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile_id)
4882 {
4883         struct be_cmd_req_get_active_profile *req;
4884         struct be_mcc_wrb *wrb;
4885         int status;
4886
4887         if (mutex_lock_interruptible(&adapter->mbox_lock))
4888                 return -1;
4889
4890         wrb = wrb_from_mbox(adapter);
4891         if (!wrb) {
4892                 status = -EBUSY;
4893                 goto err;
4894         }
4895
4896         req = embedded_payload(wrb);
4897
4898         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4899                                OPCODE_COMMON_GET_ACTIVE_PROFILE, sizeof(*req),
4900                                wrb, NULL);
4901
4902         status = be_mbox_notify_wait(adapter);
4903         if (!status) {
4904                 struct be_cmd_resp_get_active_profile *resp =
4905                                                         embedded_payload(wrb);
4906
4907                 *profile_id = le16_to_cpu(resp->active_profile_id);
4908         }
4909
4910 err:
4911         mutex_unlock(&adapter->mbox_lock);
4912         return status;
4913 }
4914
4915 static int
4916 __be_cmd_set_logical_link_config(struct be_adapter *adapter,
4917                                  int link_state, int version, u8 domain)
4918 {
4919         struct be_mcc_wrb *wrb;
4920         struct be_cmd_req_set_ll_link *req;
4921         int status;
4922
4923         mutex_lock(&adapter->mcc_lock);
4924
4925         wrb = wrb_from_mccq(adapter);
4926         if (!wrb) {
4927                 status = -EBUSY;
4928                 goto err;
4929         }
4930
4931         req = embedded_payload(wrb);
4932
4933         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4934                                OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG,
4935                                sizeof(*req), wrb, NULL);
4936
4937         req->hdr.version = version;
4938         req->hdr.domain = domain;
4939
4940         if (link_state == IFLA_VF_LINK_STATE_ENABLE ||
4941             link_state == IFLA_VF_LINK_STATE_AUTO)
4942                 req->link_config |= PLINK_ENABLE;
4943
4944         if (link_state == IFLA_VF_LINK_STATE_AUTO)
4945                 req->link_config |= PLINK_TRACK;
4946
4947         status = be_mcc_notify_wait(adapter);
4948 err:
4949         mutex_unlock(&adapter->mcc_lock);
4950         return status;
4951 }
4952
4953 int be_cmd_set_logical_link_config(struct be_adapter *adapter,
4954                                    int link_state, u8 domain)
4955 {
4956         int status;
4957
4958         if (BEx_chip(adapter))
4959                 return -EOPNOTSUPP;
4960
4961         status = __be_cmd_set_logical_link_config(adapter, link_state,
4962                                                   2, domain);
4963
4964         /* Version 2 of the command will not be recognized by older FW.
4965          * On such a failure issue version 1 of the command.
4966          */
4967         if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST)
4968                 status = __be_cmd_set_logical_link_config(adapter, link_state,
4969                                                           1, domain);
4970         return status;
4971 }
4972
4973 int be_cmd_set_features(struct be_adapter *adapter)
4974 {
4975         struct be_cmd_resp_set_features *resp;
4976         struct be_cmd_req_set_features *req;
4977         struct be_mcc_wrb *wrb;
4978         int status;
4979
4980         if (mutex_lock_interruptible(&adapter->mcc_lock))
4981                 return -1;
4982
4983         wrb = wrb_from_mccq(adapter);
4984         if (!wrb) {
4985                 status = -EBUSY;
4986                 goto err;
4987         }
4988
4989         req = embedded_payload(wrb);
4990
4991         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4992                                OPCODE_COMMON_SET_FEATURES,
4993                                sizeof(*req), wrb, NULL);
4994
4995         req->features = cpu_to_le32(BE_FEATURE_UE_RECOVERY);
4996         req->parameter_len = cpu_to_le32(sizeof(struct be_req_ue_recovery));
4997         req->parameter.req.uer = cpu_to_le32(BE_UE_RECOVERY_UER_MASK);
4998
4999         status = be_mcc_notify_wait(adapter);
5000         if (status)
5001                 goto err;
5002
5003         resp = embedded_payload(wrb);
5004
5005         adapter->error_recovery.ue_to_poll_time =
5006                 le16_to_cpu(resp->parameter.resp.ue2rp);
5007         adapter->error_recovery.ue_to_reset_time =
5008                 le16_to_cpu(resp->parameter.resp.ue2sr);
5009         adapter->error_recovery.recovery_supported = true;
5010 err:
5011         /* Checking "MCC_STATUS_INVALID_LENGTH" for SKH as FW
5012          * returns this error in older firmware versions
5013          */
5014         if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST ||
5015             base_status(status) == MCC_STATUS_INVALID_LENGTH)
5016                 dev_info(&adapter->pdev->dev,
5017                          "Adapter does not support HW error recovery\n");
5018
5019         mutex_unlock(&adapter->mcc_lock);
5020         return status;
5021 }
5022
5023 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
5024                     int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
5025 {
5026         struct be_adapter *adapter = netdev_priv(netdev_handle);
5027         struct be_mcc_wrb *wrb;
5028         struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *)wrb_payload;
5029         struct be_cmd_req_hdr *req;
5030         struct be_cmd_resp_hdr *resp;
5031         int status;
5032
5033         mutex_lock(&adapter->mcc_lock);
5034
5035         wrb = wrb_from_mccq(adapter);
5036         if (!wrb) {
5037                 status = -EBUSY;
5038                 goto err;
5039         }
5040         req = embedded_payload(wrb);
5041         resp = embedded_payload(wrb);
5042
5043         be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
5044                                hdr->opcode, wrb_payload_size, wrb, NULL);
5045         memcpy(req, wrb_payload, wrb_payload_size);
5046         be_dws_cpu_to_le(req, wrb_payload_size);
5047
5048         status = be_mcc_notify_wait(adapter);
5049         if (cmd_status)
5050                 *cmd_status = (status & 0xffff);
5051         if (ext_status)
5052                 *ext_status = 0;
5053         memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
5054         be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
5055 err:
5056         mutex_unlock(&adapter->mcc_lock);
5057         return status;
5058 }
5059 EXPORT_SYMBOL(be_roce_mcc_cmd);