drivers/net/ethernet/emulex/benet/be_cmds.c

   1 /*
   2  * Copyright (C) 2005 - 2015 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 #include <linux/module.h>
  19 #include "be.h"
  20 #include "be_cmds.h"
  21
  22 static char *be_port_misconfig_evt_desc[] = {
  23         "A valid SFP module detected",
  24         "Optics faulted/ incorrectly installed/ not installed.",
  25         "Optics of two types installed.",
  26         "Incompatible optics.",
  27         "Unknown port SFP status"
  28 };
  29
  30 static char *be_port_misconfig_remedy_desc[] = {
  31         "",
  32         "Reseat optics. If issue not resolved, replace",
  33         "Remove one optic or install matching pair of optics",
  34         "Replace with compatible optics for card to function",
  35         ""
  36 };
  37
  38 static struct be_cmd_priv_map cmd_priv_map[] = {
  39         {
  40                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
  41                 CMD_SUBSYSTEM_ETH,
  42                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  43                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  44         },
  45         {
  46                 OPCODE_COMMON_GET_FLOW_CONTROL,
  47                 CMD_SUBSYSTEM_COMMON,
  48                 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
  49                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  50         },
  51         {
  52                 OPCODE_COMMON_SET_FLOW_CONTROL,
  53                 CMD_SUBSYSTEM_COMMON,
  54                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  55                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  56         },
  57         {
  58                 OPCODE_ETH_GET_PPORT_STATS,
  59                 CMD_SUBSYSTEM_ETH,
  60                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  61                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  62         },
  63         {
  64                 OPCODE_COMMON_GET_PHY_DETAILS,
  65                 CMD_SUBSYSTEM_COMMON,
  66                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  67                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  68         }
  69 };
  70
  71 static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, u8 subsystem)
  72 {
  73         int i;
  74         int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
  75         u32 cmd_privileges = adapter->cmd_privileges;
  76
  77         for (i = 0; i < num_entries; i++)
  78                 if (opcode == cmd_priv_map[i].opcode &&
  79                     subsystem == cmd_priv_map[i].subsystem)
  80                         if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
  81                                 return false;
  82
  83         return true;
  84 }
  85
  86 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
  87 {
  88         return wrb->payload.embedded_payload;
  89 }
  90
  91 static int be_mcc_notify(struct be_adapter *adapter)
  92 {
  93         struct be_queue_info *mccq = &adapter->mcc_obj.q;
  94         u32 val = 0;
  95
  96         if (be_check_error(adapter, BE_ERROR_ANY))
  97                 return -EIO;
  98
  99         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
 100         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
 101
 102         wmb();
 103         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
 104
 105         return 0;
 106 }
 107
 108 /* To check if valid bit is set, check the entire word as we don't know
 109  * the endianness of the data (old entry is host endian while a new entry is
 110  * little endian) */
 111 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
 112 {
 113         u32 flags;
 114
 115         if (compl->flags != 0) {
 116                 flags = le32_to_cpu(compl->flags);
 117                 if (flags & CQE_FLAGS_VALID_MASK) {
 118                         compl->flags = flags;
 119                         return true;
 120                 }
 121         }
 122         return false;
 123 }
 124
 125 /* Need to reset the entire word that houses the valid bit */
 126 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
 127 {
 128         compl->flags = 0;
 129 }
 130
 131 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
 132 {
 133         unsigned long addr;
 134
 135         addr = tag1;
 136         addr = ((addr << 16) << 16) | tag0;
 137         return (void *)addr;
 138 }
 139
 140 static bool be_skip_err_log(u8 opcode, u16 base_status, u16 addl_status)
 141 {
 142         if (base_status == MCC_STATUS_NOT_SUPPORTED ||
 143             base_status == MCC_STATUS_ILLEGAL_REQUEST ||
 144             addl_status == MCC_ADDL_STATUS_TOO_MANY_INTERFACES ||
 145             addl_status == MCC_ADDL_STATUS_INSUFFICIENT_VLANS ||
 146             (opcode == OPCODE_COMMON_WRITE_FLASHROM &&
 147             (base_status == MCC_STATUS_ILLEGAL_FIELD ||
 148              addl_status == MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH)))
 149                 return true;
 150         else
 151                 return false;
 152 }
 153
 154 /* Place holder for all the async MCC cmds wherein the caller is not in a busy
 155  * loop (has not issued be_mcc_notify_wait())
 156  */
 157 static void be_async_cmd_process(struct be_adapter *adapter,
 158                                  struct be_mcc_compl *compl,
 159                                  struct be_cmd_resp_hdr *resp_hdr)
 160 {
 161         enum mcc_base_status base_status = base_status(compl->status);
 162         u8 opcode = 0, subsystem = 0;
 163
 164         if (resp_hdr) {
 165                 opcode = resp_hdr->opcode;
 166                 subsystem = resp_hdr->subsystem;
 167         }
 168
 169         if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST &&
 170             subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
 171                 complete(&adapter->et_cmd_compl);
 172                 return;
 173         }
 174
 175         if ((opcode == OPCODE_COMMON_WRITE_FLASHROM ||
 176              opcode == OPCODE_COMMON_WRITE_OBJECT) &&
 177             subsystem == CMD_SUBSYSTEM_COMMON) {
 178                 adapter->flash_status = compl->status;
 179                 complete(&adapter->et_cmd_compl);
 180                 return;
 181         }
 182
 183         if ((opcode == OPCODE_ETH_GET_STATISTICS ||
 184              opcode == OPCODE_ETH_GET_PPORT_STATS) &&
 185             subsystem == CMD_SUBSYSTEM_ETH &&
 186             base_status == MCC_STATUS_SUCCESS) {
 187                 be_parse_stats(adapter);
 188                 adapter->stats_cmd_sent = false;
 189                 return;
 190         }
 191
 192         if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
 193             subsystem == CMD_SUBSYSTEM_COMMON) {
 194                 if (base_status == MCC_STATUS_SUCCESS) {
 195                         struct be_cmd_resp_get_cntl_addnl_attribs *resp =
 196                                                         (void *)resp_hdr;
 197                         adapter->hwmon_info.be_on_die_temp =
 198                                                 resp->on_die_temperature;
 199                 } else {
 200                         adapter->be_get_temp_freq = 0;
 201                         adapter->hwmon_info.be_on_die_temp =
 202                                                 BE_INVALID_DIE_TEMP;
 203                 }
 204                 return;
 205         }
 206 }
 207
 208 static int be_mcc_compl_process(struct be_adapter *adapter,
 209                                 struct be_mcc_compl *compl)
 210 {
 211         enum mcc_base_status base_status;
 212         enum mcc_addl_status addl_status;
 213         struct be_cmd_resp_hdr *resp_hdr;
 214         u8 opcode = 0, subsystem = 0;
 215
 216         /* Just swap the status to host endian; mcc tag is opaquely copied
 217          * from mcc_wrb */
 218         be_dws_le_to_cpu(compl, 4);
 219
 220         base_status = base_status(compl->status);
 221         addl_status = addl_status(compl->status);
 222
 223         resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
 224         if (resp_hdr) {
 225                 opcode = resp_hdr->opcode;
 226                 subsystem = resp_hdr->subsystem;
 227         }
 228
 229         be_async_cmd_process(adapter, compl, resp_hdr);
 230
 231         if (base_status != MCC_STATUS_SUCCESS &&
 232             !be_skip_err_log(opcode, base_status, addl_status)) {
 233                 if (base_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
 234                         dev_warn(&adapter->pdev->dev,
 235                                  "VF is not privileged to issue opcode %d-%d\n",
 236                                  opcode, subsystem);
 237                 } else {
 238                         dev_err(&adapter->pdev->dev,
 239                                 "opcode %d-%d failed:status %d-%d\n",
 240                                 opcode, subsystem, base_status, addl_status);
 241                 }
 242         }
 243         return compl->status;
 244 }
 245
 246 /* Link state evt is a string of bytes; no need for endian swapping */
 247 static void be_async_link_state_process(struct be_adapter *adapter,
 248                                         struct be_mcc_compl *compl)
 249 {
 250         struct be_async_event_link_state *evt =
 251                         (struct be_async_event_link_state *)compl;
 252
 253         /* When link status changes, link speed must be re-queried from FW */
 254         adapter->phy.link_speed = -1;
 255
 256         /* On BEx the FW does not send a separate link status
 257          * notification for physical and logical link.
 258          * On other chips just process the logical link
 259          * status notification
 260          */
 261         if (!BEx_chip(adapter) &&
 262             !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
 263                 return;
 264
 265         /* For the initial link status do not rely on the ASYNC event as
 266          * it may not be received in some cases.
 267          */
 268         if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
 269                 be_link_status_update(adapter,
 270                                       evt->port_link_status & LINK_STATUS_MASK);
 271 }
 272
 273 static void be_async_port_misconfig_event_process(struct be_adapter *adapter,
 274                                                   struct be_mcc_compl *compl)
 275 {
 276         struct be_async_event_misconfig_port *evt =
 277                         (struct be_async_event_misconfig_port *)compl;
 278         u32 sfp_mismatch_evt = le32_to_cpu(evt->event_data_word1);
 279         struct device *dev = &adapter->pdev->dev;
 280         u8 port_misconfig_evt;
 281
 282         port_misconfig_evt =
 283                 ((sfp_mismatch_evt >> (adapter->hba_port_num * 8)) & 0xff);
 284
 285         /* Log an error message that would allow a user to determine
 286          * whether the SFPs have an issue
 287          */
 288         dev_info(dev, "Port %c: %s %s", adapter->port_name,
 289                  be_port_misconfig_evt_desc[port_misconfig_evt],
 290                  be_port_misconfig_remedy_desc[port_misconfig_evt]);
 291
 292         if (port_misconfig_evt == INCOMPATIBLE_SFP)
 293                 adapter->flags |= BE_FLAGS_EVT_INCOMPATIBLE_SFP;
 294 }
 295
 296 /* Grp5 CoS Priority evt */
 297 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
 298                                                struct be_mcc_compl *compl)
 299 {
 300         struct be_async_event_grp5_cos_priority *evt =
 301                         (struct be_async_event_grp5_cos_priority *)compl;
 302
 303         if (evt->valid) {
 304                 adapter->vlan_prio_bmap = evt->available_priority_bmap;
 305                 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
 306                 adapter->recommended_prio =
 307                         evt->reco_default_priority << VLAN_PRIO_SHIFT;
 308         }
 309 }
 310
 311 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
 312 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
 313                                             struct be_mcc_compl *compl)
 314 {
 315         struct be_async_event_grp5_qos_link_speed *evt =
 316                         (struct be_async_event_grp5_qos_link_speed *)compl;
 317
 318         if (adapter->phy.link_speed >= 0 &&
 319             evt->physical_port == adapter->port_num)
 320                 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
 321 }
 322
 323 /*Grp5 PVID evt*/
 324 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
 325                                              struct be_mcc_compl *compl)
 326 {
 327         struct be_async_event_grp5_pvid_state *evt =
 328                         (struct be_async_event_grp5_pvid_state *)compl;
 329
 330         if (evt->enabled) {
 331                 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
 332                 dev_info(&adapter->pdev->dev, "LPVID: %d\n", adapter->pvid);
 333         } else {
 334                 adapter->pvid = 0;
 335         }
 336 }
 337
 338 #define MGMT_ENABLE_MASK        0x4
 339 static void be_async_grp5_fw_control_process(struct be_adapter *adapter,
 340                                              struct be_mcc_compl *compl)
 341 {
 342         struct be_async_fw_control *evt = (struct be_async_fw_control *)compl;
 343         u32 evt_dw1 = le32_to_cpu(evt->event_data_word1);
 344
 345         if (evt_dw1 & MGMT_ENABLE_MASK) {
 346                 adapter->flags |= BE_FLAGS_OS2BMC;
 347                 adapter->bmc_filt_mask = le32_to_cpu(evt->event_data_word2);
 348         } else {
 349                 adapter->flags &= ~BE_FLAGS_OS2BMC;
 350         }
 351 }
 352
 353 static void be_async_grp5_evt_process(struct be_adapter *adapter,
 354                                       struct be_mcc_compl *compl)
 355 {
 356         u8 event_type = (compl->flags >> ASYNC_EVENT_TYPE_SHIFT) &
 357                                 ASYNC_EVENT_TYPE_MASK;
 358
 359         switch (event_type) {
 360         case ASYNC_EVENT_COS_PRIORITY:
 361                 be_async_grp5_cos_priority_process(adapter, compl);
 362                 break;
 363         case ASYNC_EVENT_QOS_SPEED:
 364                 be_async_grp5_qos_speed_process(adapter, compl);
 365                 break;
 366         case ASYNC_EVENT_PVID_STATE:
 367                 be_async_grp5_pvid_state_process(adapter, compl);
 368                 break;
 369         /* Async event to disable/enable os2bmc and/or mac-learning */
 370         case ASYNC_EVENT_FW_CONTROL:
 371                 be_async_grp5_fw_control_process(adapter, compl);
 372                 break;
 373         default:
 374                 break;
 375         }
 376 }
 377
 378 static void be_async_dbg_evt_process(struct be_adapter *adapter,
 379                                      struct be_mcc_compl *cmp)
 380 {
 381         u8 event_type = 0;
 382         struct be_async_event_qnq *evt = (struct be_async_event_qnq *)cmp;
 383
 384         event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
 385                         ASYNC_EVENT_TYPE_MASK;
 386
 387         switch (event_type) {
 388         case ASYNC_DEBUG_EVENT_TYPE_QNQ:
 389                 if (evt->valid)
 390                         adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
 391                 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
 392         break;
 393         default:
 394                 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
 395                          event_type);
 396         break;
 397         }
 398 }
 399
 400 static void be_async_sliport_evt_process(struct be_adapter *adapter,
 401                                          struct be_mcc_compl *cmp)
 402 {
 403         u8 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
 404                         ASYNC_EVENT_TYPE_MASK;
 405
 406         if (event_type == ASYNC_EVENT_PORT_MISCONFIG)
 407                 be_async_port_misconfig_event_process(adapter, cmp);
 408 }
 409
 410 static inline bool is_link_state_evt(u32 flags)
 411 {
 412         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 413                         ASYNC_EVENT_CODE_LINK_STATE;
 414 }
 415
 416 static inline bool is_grp5_evt(u32 flags)
 417 {
 418         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 419                         ASYNC_EVENT_CODE_GRP_5;
 420 }
 421
 422 static inline bool is_dbg_evt(u32 flags)
 423 {
 424         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 425                         ASYNC_EVENT_CODE_QNQ;
 426 }
 427
 428 static inline bool is_sliport_evt(u32 flags)
 429 {
 430         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 431                 ASYNC_EVENT_CODE_SLIPORT;
 432 }
 433
 434 static void be_mcc_event_process(struct be_adapter *adapter,
 435                                  struct be_mcc_compl *compl)
 436 {
 437         if (is_link_state_evt(compl->flags))
 438                 be_async_link_state_process(adapter, compl);
 439         else if (is_grp5_evt(compl->flags))
 440                 be_async_grp5_evt_process(adapter, compl);
 441         else if (is_dbg_evt(compl->flags))
 442                 be_async_dbg_evt_process(adapter, compl);
 443         else if (is_sliport_evt(compl->flags))
 444                 be_async_sliport_evt_process(adapter, compl);
 445 }
 446
 447 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
 448 {
 449         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
 450         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
 451
 452         if (be_mcc_compl_is_new(compl)) {
 453                 queue_tail_inc(mcc_cq);
 454                 return compl;
 455         }
 456         return NULL;
 457 }
 458
 459 void be_async_mcc_enable(struct be_adapter *adapter)
 460 {
 461         spin_lock_bh(&adapter->mcc_cq_lock);
 462
 463         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
 464         adapter->mcc_obj.rearm_cq = true;
 465
 466         spin_unlock_bh(&adapter->mcc_cq_lock);
 467 }
 468
 469 void be_async_mcc_disable(struct be_adapter *adapter)
 470 {
 471         spin_lock_bh(&adapter->mcc_cq_lock);
 472
 473         adapter->mcc_obj.rearm_cq = false;
 474         be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
 475
 476         spin_unlock_bh(&adapter->mcc_cq_lock);
 477 }
 478
 479 int be_process_mcc(struct be_adapter *adapter)
 480 {
 481         struct be_mcc_compl *compl;
 482         int num = 0, status = 0;
 483         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 484
 485         spin_lock(&adapter->mcc_cq_lock);
 486
 487         while ((compl = be_mcc_compl_get(adapter))) {
 488                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 489                         be_mcc_event_process(adapter, compl);
 490                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
 491                         status = be_mcc_compl_process(adapter, compl);
 492                         atomic_dec(&mcc_obj->q.used);
 493                 }
 494                 be_mcc_compl_use(compl);
 495                 num++;
 496         }
 497
 498         if (num)
 499                 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
 500
 501         spin_unlock(&adapter->mcc_cq_lock);
 502         return status;
 503 }
 504
 505 /* Wait till no more pending mcc requests are present */
 506 static int be_mcc_wait_compl(struct be_adapter *adapter)
 507 {
 508 #define mcc_timeout             120000 /* 12s timeout */
 509         int i, status = 0;
 510         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 511
 512         for (i = 0; i < mcc_timeout; i++) {
 513                 if (be_check_error(adapter, BE_ERROR_ANY))
 514                         return -EIO;
 515
 516                 local_bh_disable();
 517                 status = be_process_mcc(adapter);
 518                 local_bh_enable();
 519
 520                 if (atomic_read(&mcc_obj->q.used) == 0)
 521                         break;
 522                 udelay(100);
 523         }
 524         if (i == mcc_timeout) {
 525                 dev_err(&adapter->pdev->dev, "FW not responding\n");
 526                 be_set_error(adapter, BE_ERROR_FW);
 527                 return -EIO;
 528         }
 529         return status;
 530 }
 531
 532 /* Notify MCC requests and wait for completion */
 533 static int be_mcc_notify_wait(struct be_adapter *adapter)
 534 {
 535         int status;
 536         struct be_mcc_wrb *wrb;
 537         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 538         u16 index = mcc_obj->q.head;
 539         struct be_cmd_resp_hdr *resp;
 540
 541         index_dec(&index, mcc_obj->q.len);
 542         wrb = queue_index_node(&mcc_obj->q, index);
 543
 544         resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
 545
 546         status = be_mcc_notify(adapter);
 547         if (status)
 548                 goto out;
 549
 550         status = be_mcc_wait_compl(adapter);
 551         if (status == -EIO)
 552                 goto out;
 553
 554         status = (resp->base_status |
 555                   ((resp->addl_status & CQE_ADDL_STATUS_MASK) <<
 556                    CQE_ADDL_STATUS_SHIFT));
 557 out:
 558         return status;
 559 }
 560
 561 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 562 {
 563         int msecs = 0;
 564         u32 ready;
 565
 566         do {
 567                 if (be_check_error(adapter, BE_ERROR_ANY))
 568                         return -EIO;
 569
 570                 ready = ioread32(db);
 571                 if (ready == 0xffffffff)
 572                         return -1;
 573
 574                 ready &= MPU_MAILBOX_DB_RDY_MASK;
 575                 if (ready)
 576                         break;
 577
 578                 if (msecs > 4000) {
 579                         dev_err(&adapter->pdev->dev, "FW not responding\n");
 580                         be_set_error(adapter, BE_ERROR_FW);
 581                         be_detect_error(adapter);
 582                         return -1;
 583                 }
 584
 585                 msleep(1);
 586                 msecs++;
 587         } while (true);
 588
 589         return 0;
 590 }
 591
 592 /*
 593  * Insert the mailbox address into the doorbell in two steps
 594  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 595  */
 596 static int be_mbox_notify_wait(struct be_adapter *adapter)
 597 {
 598         int status;
 599         u32 val = 0;
 600         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 601         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 602         struct be_mcc_mailbox *mbox = mbox_mem->va;
 603         struct be_mcc_compl *compl = &mbox->compl;
 604
 605         /* wait for ready to be set */
 606         status = be_mbox_db_ready_wait(adapter, db);
 607         if (status != 0)
 608                 return status;
 609
 610         val |= MPU_MAILBOX_DB_HI_MASK;
 611         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 612         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 613         iowrite32(val, db);
 614
 615         /* wait for ready to be set */
 616         status = be_mbox_db_ready_wait(adapter, db);
 617         if (status != 0)
 618                 return status;
 619
 620         val = 0;
 621         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 622         val |= (u32)(mbox_mem->dma >> 4) << 2;
 623         iowrite32(val, db);
 624
 625         status = be_mbox_db_ready_wait(adapter, db);
 626         if (status != 0)
 627                 return status;
 628
 629         /* A cq entry has been made now */
 630         if (be_mcc_compl_is_new(compl)) {
 631                 status = be_mcc_compl_process(adapter, &mbox->compl);
 632                 be_mcc_compl_use(compl);
 633                 if (status)
 634                         return status;
 635         } else {
 636                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 637                 return -1;
 638         }
 639         return 0;
 640 }
 641
 642 static u16 be_POST_stage_get(struct be_adapter *adapter)
 643 {
 644         u32 sem;
 645
 646         if (BEx_chip(adapter))
 647                 sem  = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
 648         else
 649                 pci_read_config_dword(adapter->pdev,
 650                                       SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
 651
 652         return sem & POST_STAGE_MASK;
 653 }
 654
 655 static int lancer_wait_ready(struct be_adapter *adapter)
 656 {
 657 #define SLIPORT_READY_TIMEOUT 30
 658         u32 sliport_status;
 659         int i;
 660
 661         for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
 662                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 663                 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
 664                         return 0;
 665
 666                 if (sliport_status & SLIPORT_STATUS_ERR_MASK &&
 667                     !(sliport_status & SLIPORT_STATUS_RN_MASK))
 668                         return -EIO;
 669
 670                 msleep(1000);
 671         }
 672
 673         return sliport_status ? : -1;
 674 }
 675
 676 int be_fw_wait_ready(struct be_adapter *adapter)
 677 {
 678         u16 stage;
 679         int status, timeout = 0;
 680         struct device *dev = &adapter->pdev->dev;
 681
 682         if (lancer_chip(adapter)) {
 683                 status = lancer_wait_ready(adapter);
 684                 if (status) {
 685                         stage = status;
 686                         goto err;
 687                 }
 688                 return 0;
 689         }
 690
 691         do {
 692                 /* There's no means to poll POST state on BE2/3 VFs */
 693                 if (BEx_chip(adapter) && be_virtfn(adapter))
 694                         return 0;
 695
 696                 stage = be_POST_stage_get(adapter);
 697                 if (stage == POST_STAGE_ARMFW_RDY)
 698                         return 0;
 699
 700                 dev_info(dev, "Waiting for POST, %ds elapsed\n", timeout);
 701                 if (msleep_interruptible(2000)) {
 702                         dev_err(dev, "Waiting for POST aborted\n");
 703                         return -EINTR;
 704                 }
 705                 timeout += 2;
 706         } while (timeout < 60);
 707
 708 err:
 709         dev_err(dev, "POST timeout; stage=%#x\n", stage);
 710         return -ETIMEDOUT;
 711 }
 712
 713 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 714 {
 715         return &wrb->payload.sgl[0];
 716 }
 717
 718 static inline void fill_wrb_tags(struct be_mcc_wrb *wrb, unsigned long addr)
 719 {
 720         wrb->tag0 = addr & 0xFFFFFFFF;
 721         wrb->tag1 = upper_32_bits(addr);
 722 }
 723
 724 /* Don't touch the hdr after it's prepared */
 725 /* mem will be NULL for embedded commands */
 726 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 727                                    u8 subsystem, u8 opcode, int cmd_len,
 728                                    struct be_mcc_wrb *wrb,
 729                                    struct be_dma_mem *mem)
 730 {
 731         struct be_sge *sge;
 732
 733         req_hdr->opcode = opcode;
 734         req_hdr->subsystem = subsystem;
 735         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 736         req_hdr->version = 0;
 737         fill_wrb_tags(wrb, (ulong) req_hdr);
 738         wrb->payload_length = cmd_len;
 739         if (mem) {
 740                 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
 741                         MCC_WRB_SGE_CNT_SHIFT;
 742                 sge = nonembedded_sgl(wrb);
 743                 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
 744                 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
 745                 sge->len = cpu_to_le32(mem->size);
 746         } else
 747                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 748         be_dws_cpu_to_le(wrb, 8);
 749 }
 750
 751 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 752                                       struct be_dma_mem *mem)
 753 {
 754         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 755         u64 dma = (u64)mem->dma;
 756
 757         for (i = 0; i < buf_pages; i++) {
 758                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 759                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 760                 dma += PAGE_SIZE_4K;
 761         }
 762 }
 763
 764 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
 765 {
 766         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 767         struct be_mcc_wrb *wrb
 768                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 769         memset(wrb, 0, sizeof(*wrb));
 770         return wrb;
 771 }
 772
 773 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
 774 {
 775         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 776         struct be_mcc_wrb *wrb;
 777
 778         if (!mccq->created)
 779                 return NULL;
 780
 781         if (atomic_read(&mccq->used) >= mccq->len)
 782                 return NULL;
 783
 784         wrb = queue_head_node(mccq);
 785         queue_head_inc(mccq);
 786         atomic_inc(&mccq->used);
 787         memset(wrb, 0, sizeof(*wrb));
 788         return wrb;
 789 }
 790
 791 static bool use_mcc(struct be_adapter *adapter)
 792 {
 793         return adapter->mcc_obj.q.created;
 794 }
 795
 796 /* Must be used only in process context */
 797 static int be_cmd_lock(struct be_adapter *adapter)
 798 {
 799         if (use_mcc(adapter)) {
 800                 spin_lock_bh(&adapter->mcc_lock);
 801                 return 0;
 802         } else {
 803                 return mutex_lock_interruptible(&adapter->mbox_lock);
 804         }
 805 }
 806
 807 /* Must be used only in process context */
 808 static void be_cmd_unlock(struct be_adapter *adapter)
 809 {
 810         if (use_mcc(adapter))
 811                 spin_unlock_bh(&adapter->mcc_lock);
 812         else
 813                 return mutex_unlock(&adapter->mbox_lock);
 814 }
 815
 816 static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter,
 817                                       struct be_mcc_wrb *wrb)
 818 {
 819         struct be_mcc_wrb *dest_wrb;
 820
 821         if (use_mcc(adapter)) {
 822                 dest_wrb = wrb_from_mccq(adapter);
 823                 if (!dest_wrb)
 824                         return NULL;
 825         } else {
 826                 dest_wrb = wrb_from_mbox(adapter);
 827         }
 828
 829         memcpy(dest_wrb, wrb, sizeof(*wrb));
 830         if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK))
 831                 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb));
 832
 833         return dest_wrb;
 834 }
 835
 836 /* Must be used only in process context */
 837 static int be_cmd_notify_wait(struct be_adapter *adapter,
 838                               struct be_mcc_wrb *wrb)
 839 {
 840         struct be_mcc_wrb *dest_wrb;
 841         int status;
 842
 843         status = be_cmd_lock(adapter);
 844         if (status)
 845                 return status;
 846
 847         dest_wrb = be_cmd_copy(adapter, wrb);
 848         if (!dest_wrb)
 849                 return -EBUSY;
 850
 851         if (use_mcc(adapter))
 852                 status = be_mcc_notify_wait(adapter);
 853         else
 854                 status = be_mbox_notify_wait(adapter);
 855
 856         if (!status)
 857                 memcpy(wrb, dest_wrb, sizeof(*wrb));
 858
 859         be_cmd_unlock(adapter);
 860         return status;
 861 }
 862
 863 /* Tell fw we're about to start firing cmds by writing a
 864  * special pattern across the wrb hdr; uses mbox
 865  */
 866 int be_cmd_fw_init(struct be_adapter *adapter)
 867 {
 868         u8 *wrb;
 869         int status;
 870
 871         if (lancer_chip(adapter))
 872                 return 0;
 873
 874         if (mutex_lock_interruptible(&adapter->mbox_lock))
 875                 return -1;
 876
 877         wrb = (u8 *)wrb_from_mbox(adapter);
 878         *wrb++ = 0xFF;
 879         *wrb++ = 0x12;
 880         *wrb++ = 0x34;
 881         *wrb++ = 0xFF;
 882         *wrb++ = 0xFF;
 883         *wrb++ = 0x56;
 884         *wrb++ = 0x78;
 885         *wrb = 0xFF;
 886
 887         status = be_mbox_notify_wait(adapter);
 888
 889         mutex_unlock(&adapter->mbox_lock);
 890         return status;
 891 }
 892
 893 /* Tell fw we're done with firing cmds by writing a
 894  * special pattern across the wrb hdr; uses mbox
 895  */
 896 int be_cmd_fw_clean(struct be_adapter *adapter)
 897 {
 898         u8 *wrb;
 899         int status;
 900
 901         if (lancer_chip(adapter))
 902                 return 0;
 903
 904         if (mutex_lock_interruptible(&adapter->mbox_lock))
 905                 return -1;
 906
 907         wrb = (u8 *)wrb_from_mbox(adapter);
 908         *wrb++ = 0xFF;
 909         *wrb++ = 0xAA;
 910         *wrb++ = 0xBB;
 911         *wrb++ = 0xFF;
 912         *wrb++ = 0xFF;
 913         *wrb++ = 0xCC;
 914         *wrb++ = 0xDD;
 915         *wrb = 0xFF;
 916
 917         status = be_mbox_notify_wait(adapter);
 918
 919         mutex_unlock(&adapter->mbox_lock);
 920         return status;
 921 }
 922
 923 int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
 924 {
 925         struct be_mcc_wrb *wrb;
 926         struct be_cmd_req_eq_create *req;
 927         struct be_dma_mem *q_mem = &eqo->q.dma_mem;
 928         int status, ver = 0;
 929
 930         if (mutex_lock_interruptible(&adapter->mbox_lock))
 931                 return -1;
 932
 933         wrb = wrb_from_mbox(adapter);
 934         req = embedded_payload(wrb);
 935
 936         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 937                                OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb,
 938                                NULL);
 939
 940         /* Support for EQ_CREATEv2 available only SH-R onwards */
 941         if (!(BEx_chip(adapter) || lancer_chip(adapter)))
 942                 ver = 2;
 943
 944         req->hdr.version = ver;
 945         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 946
 947         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
 948         /* 4byte eqe*/
 949         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
 950         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
 951                       __ilog2_u32(eqo->q.len / 256));
 952         be_dws_cpu_to_le(req->context, sizeof(req->context));
 953
 954         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 955
 956         status = be_mbox_notify_wait(adapter);
 957         if (!status) {
 958                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
 959
 960                 eqo->q.id = le16_to_cpu(resp->eq_id);
 961                 eqo->msix_idx =
 962                         (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx;
 963                 eqo->q.created = true;
 964         }
 965
 966         mutex_unlock(&adapter->mbox_lock);
 967         return status;
 968 }
 969
 970 /* Use MCC */
 971 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 972                           bool permanent, u32 if_handle, u32 pmac_id)
 973 {
 974         struct be_mcc_wrb *wrb;
 975         struct be_cmd_req_mac_query *req;
 976         int status;
 977
 978         spin_lock_bh(&adapter->mcc_lock);
 979
 980         wrb = wrb_from_mccq(adapter);
 981         if (!wrb) {
 982                 status = -EBUSY;
 983                 goto err;
 984         }
 985         req = embedded_payload(wrb);
 986
 987         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 988                                OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb,
 989                                NULL);
 990         req->type = MAC_ADDRESS_TYPE_NETWORK;
 991         if (permanent) {
 992                 req->permanent = 1;
 993         } else {
 994                 req->if_id = cpu_to_le16((u16)if_handle);
 995                 req->pmac_id = cpu_to_le32(pmac_id);
 996                 req->permanent = 0;
 997         }
 998
 999         status = be_mcc_notify_wait(adapter);
1000         if (!status) {
1001                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
1002
1003                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
1004         }
1005
1006 err:
1007         spin_unlock_bh(&adapter->mcc_lock);
1008         return status;
1009 }
1010
1011 /* Uses synchronous MCCQ */
1012 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
1013                     u32 if_id, u32 *pmac_id, u32 domain)
1014 {
1015         struct be_mcc_wrb *wrb;
1016         struct be_cmd_req_pmac_add *req;
1017         int status;
1018
1019         spin_lock_bh(&adapter->mcc_lock);
1020
1021         wrb = wrb_from_mccq(adapter);
1022         if (!wrb) {
1023                 status = -EBUSY;
1024                 goto err;
1025         }
1026         req = embedded_payload(wrb);
1027
1028         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1029                                OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb,
1030                                NULL);
1031
1032         req->hdr.domain = domain;
1033         req->if_id = cpu_to_le32(if_id);
1034         memcpy(req->mac_address, mac_addr, ETH_ALEN);
1035
1036         status = be_mcc_notify_wait(adapter);
1037         if (!status) {
1038                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
1039
1040                 *pmac_id = le32_to_cpu(resp->pmac_id);
1041         }
1042
1043 err:
1044         spin_unlock_bh(&adapter->mcc_lock);
1045
1046          if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
1047                 status = -EPERM;
1048
1049         return status;
1050 }
1051
1052 /* Uses synchronous MCCQ */
1053 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
1054 {
1055         struct be_mcc_wrb *wrb;
1056         struct be_cmd_req_pmac_del *req;
1057         int status;
1058
1059         if (pmac_id == -1)
1060                 return 0;
1061
1062         spin_lock_bh(&adapter->mcc_lock);
1063
1064         wrb = wrb_from_mccq(adapter);
1065         if (!wrb) {
1066                 status = -EBUSY;
1067                 goto err;
1068         }
1069         req = embedded_payload(wrb);
1070
1071         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1072                                OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req),
1073                                wrb, NULL);
1074
1075         req->hdr.domain = dom;
1076         req->if_id = cpu_to_le32(if_id);
1077         req->pmac_id = cpu_to_le32(pmac_id);
1078
1079         status = be_mcc_notify_wait(adapter);
1080
1081 err:
1082         spin_unlock_bh(&adapter->mcc_lock);
1083         return status;
1084 }
1085
1086 /* Uses Mbox */
1087 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
1088                      struct be_queue_info *eq, bool no_delay, int coalesce_wm)
1089 {
1090         struct be_mcc_wrb *wrb;
1091         struct be_cmd_req_cq_create *req;
1092         struct be_dma_mem *q_mem = &cq->dma_mem;
1093         void *ctxt;
1094         int status;
1095
1096         if (mutex_lock_interruptible(&adapter->mbox_lock))
1097                 return -1;
1098
1099         wrb = wrb_from_mbox(adapter);
1100         req = embedded_payload(wrb);
1101         ctxt = &req->context;
1102
1103         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1104                                OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb,
1105                                NULL);
1106
1107         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1108
1109         if (BEx_chip(adapter)) {
1110                 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
1111                               coalesce_wm);
1112                 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
1113                               ctxt, no_delay);
1114                 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
1115                               __ilog2_u32(cq->len / 256));
1116                 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
1117                 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
1118                 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
1119         } else {
1120                 req->hdr.version = 2;
1121                 req->page_size = 1; /* 1 for 4K */
1122
1123                 /* coalesce-wm field in this cmd is not relevant to Lancer.
1124                  * Lancer uses COMMON_MODIFY_CQ to set this field
1125                  */
1126                 if (!lancer_chip(adapter))
1127                         AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
1128                                       ctxt, coalesce_wm);
1129                 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
1130                               no_delay);
1131                 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
1132                               __ilog2_u32(cq->len / 256));
1133                 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
1134                 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
1135                 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
1136         }
1137
1138         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1139
1140         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1141
1142         status = be_mbox_notify_wait(adapter);
1143         if (!status) {
1144                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
1145
1146                 cq->id = le16_to_cpu(resp->cq_id);
1147                 cq->created = true;
1148         }
1149
1150         mutex_unlock(&adapter->mbox_lock);
1151
1152         return status;
1153 }
1154
1155 static u32 be_encoded_q_len(int q_len)
1156 {
1157         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
1158
1159         if (len_encoded == 16)
1160                 len_encoded = 0;
1161         return len_encoded;
1162 }
1163
1164 static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
1165                                   struct be_queue_info *mccq,
1166                                   struct be_queue_info *cq)
1167 {
1168         struct be_mcc_wrb *wrb;
1169         struct be_cmd_req_mcc_ext_create *req;
1170         struct be_dma_mem *q_mem = &mccq->dma_mem;
1171         void *ctxt;
1172         int status;
1173
1174         if (mutex_lock_interruptible(&adapter->mbox_lock))
1175                 return -1;
1176
1177         wrb = wrb_from_mbox(adapter);
1178         req = embedded_payload(wrb);
1179         ctxt = &req->context;
1180
1181         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1182                                OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb,
1183                                NULL);
1184
1185         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1186         if (BEx_chip(adapter)) {
1187                 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1188                 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1189                               be_encoded_q_len(mccq->len));
1190                 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1191         } else {
1192                 req->hdr.version = 1;
1193                 req->cq_id = cpu_to_le16(cq->id);
1194
1195                 AMAP_SET_BITS(struct amap_mcc_context_v1, ring_size, ctxt,
1196                               be_encoded_q_len(mccq->len));
1197                 AMAP_SET_BITS(struct amap_mcc_context_v1, valid, ctxt, 1);
1198                 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_id,
1199                               ctxt, cq->id);
1200                 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_valid,
1201                               ctxt, 1);
1202         }
1203
1204         /* Subscribe to Link State, Sliport Event and Group 5 Events
1205          * (bits 1, 5 and 17 set)
1206          */
1207         req->async_event_bitmap[0] =
1208                         cpu_to_le32(BIT(ASYNC_EVENT_CODE_LINK_STATE) |
1209                                     BIT(ASYNC_EVENT_CODE_GRP_5) |
1210                                     BIT(ASYNC_EVENT_CODE_QNQ) |
1211                                     BIT(ASYNC_EVENT_CODE_SLIPORT));
1212
1213         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1214
1215         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1216
1217         status = be_mbox_notify_wait(adapter);
1218         if (!status) {
1219                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1220
1221                 mccq->id = le16_to_cpu(resp->id);
1222                 mccq->created = true;
1223         }
1224         mutex_unlock(&adapter->mbox_lock);
1225
1226         return status;
1227 }
1228
1229 static int be_cmd_mccq_org_create(struct be_adapter *adapter,
1230                                   struct be_queue_info *mccq,
1231                                   struct be_queue_info *cq)
1232 {
1233         struct be_mcc_wrb *wrb;
1234         struct be_cmd_req_mcc_create *req;
1235         struct be_dma_mem *q_mem = &mccq->dma_mem;
1236         void *ctxt;
1237         int status;
1238
1239         if (mutex_lock_interruptible(&adapter->mbox_lock))
1240                 return -1;
1241
1242         wrb = wrb_from_mbox(adapter);
1243         req = embedded_payload(wrb);
1244         ctxt = &req->context;
1245
1246         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1247                                OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb,
1248                                NULL);
1249
1250         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1251
1252         AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1253         AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1254                       be_encoded_q_len(mccq->len));
1255         AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1256
1257         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1258
1259         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1260
1261         status = be_mbox_notify_wait(adapter);
1262         if (!status) {
1263                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1264
1265                 mccq->id = le16_to_cpu(resp->id);
1266                 mccq->created = true;
1267         }
1268
1269         mutex_unlock(&adapter->mbox_lock);
1270         return status;
1271 }
1272
1273 int be_cmd_mccq_create(struct be_adapter *adapter,
1274                        struct be_queue_info *mccq, struct be_queue_info *cq)
1275 {
1276         int status;
1277
1278         status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1279         if (status && BEx_chip(adapter)) {
1280                 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1281                         "or newer to avoid conflicting priorities between NIC "
1282                         "and FCoE traffic");
1283                 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1284         }
1285         return status;
1286 }
1287
1288 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
1289 {
1290         struct be_mcc_wrb wrb = {0};
1291         struct be_cmd_req_eth_tx_create *req;
1292         struct be_queue_info *txq = &txo->q;
1293         struct be_queue_info *cq = &txo->cq;
1294         struct be_dma_mem *q_mem = &txq->dma_mem;
1295         int status, ver = 0;
1296
1297         req = embedded_payload(&wrb);
1298         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1299                                OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL);
1300
1301         if (lancer_chip(adapter)) {
1302                 req->hdr.version = 1;
1303         } else if (BEx_chip(adapter)) {
1304                 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1305                         req->hdr.version = 2;
1306         } else { /* For SH */
1307                 req->hdr.version = 2;
1308         }
1309
1310         if (req->hdr.version > 0)
1311                 req->if_id = cpu_to_le16(adapter->if_handle);
1312         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1313         req->ulp_num = BE_ULP1_NUM;
1314         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1315         req->cq_id = cpu_to_le16(cq->id);
1316         req->queue_size = be_encoded_q_len(txq->len);
1317         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1318         ver = req->hdr.version;
1319
1320         status = be_cmd_notify_wait(adapter, &wrb);
1321         if (!status) {
1322                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb);
1323
1324                 txq->id = le16_to_cpu(resp->cid);
1325                 if (ver == 2)
1326                         txo->db_offset = le32_to_cpu(resp->db_offset);
1327                 else
1328                         txo->db_offset = DB_TXULP1_OFFSET;
1329                 txq->created = true;
1330         }
1331
1332         return status;
1333 }
1334
1335 /* Uses MCC */
1336 int be_cmd_rxq_create(struct be_adapter *adapter,
1337                       struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1338                       u32 if_id, u32 rss, u8 *rss_id)
1339 {
1340         struct be_mcc_wrb *wrb;
1341         struct be_cmd_req_eth_rx_create *req;
1342         struct be_dma_mem *q_mem = &rxq->dma_mem;
1343         int status;
1344
1345         spin_lock_bh(&adapter->mcc_lock);
1346
1347         wrb = wrb_from_mccq(adapter);
1348         if (!wrb) {
1349                 status = -EBUSY;
1350                 goto err;
1351         }
1352         req = embedded_payload(wrb);
1353
1354         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1355                                OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1356
1357         req->cq_id = cpu_to_le16(cq_id);
1358         req->frag_size = fls(frag_size) - 1;
1359         req->num_pages = 2;
1360         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1361         req->interface_id = cpu_to_le32(if_id);
1362         req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
1363         req->rss_queue = cpu_to_le32(rss);
1364
1365         status = be_mcc_notify_wait(adapter);
1366         if (!status) {
1367                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1368
1369                 rxq->id = le16_to_cpu(resp->id);
1370                 rxq->created = true;
1371                 *rss_id = resp->rss_id;
1372         }
1373
1374 err:
1375         spin_unlock_bh(&adapter->mcc_lock);
1376         return status;
1377 }
1378
1379 /* Generic destroyer function for all types of queues
1380  * Uses Mbox
1381  */
1382 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1383                      int queue_type)
1384 {
1385         struct be_mcc_wrb *wrb;
1386         struct be_cmd_req_q_destroy *req;
1387         u8 subsys = 0, opcode = 0;
1388         int status;
1389
1390         if (mutex_lock_interruptible(&adapter->mbox_lock))
1391                 return -1;
1392
1393         wrb = wrb_from_mbox(adapter);
1394         req = embedded_payload(wrb);
1395
1396         switch (queue_type) {
1397         case QTYPE_EQ:
1398                 subsys = CMD_SUBSYSTEM_COMMON;
1399                 opcode = OPCODE_COMMON_EQ_DESTROY;
1400                 break;
1401         case QTYPE_CQ:
1402                 subsys = CMD_SUBSYSTEM_COMMON;
1403                 opcode = OPCODE_COMMON_CQ_DESTROY;
1404                 break;
1405         case QTYPE_TXQ:
1406                 subsys = CMD_SUBSYSTEM_ETH;
1407                 opcode = OPCODE_ETH_TX_DESTROY;
1408                 break;
1409         case QTYPE_RXQ:
1410                 subsys = CMD_SUBSYSTEM_ETH;
1411                 opcode = OPCODE_ETH_RX_DESTROY;
1412                 break;
1413         case QTYPE_MCCQ:
1414                 subsys = CMD_SUBSYSTEM_COMMON;
1415                 opcode = OPCODE_COMMON_MCC_DESTROY;
1416                 break;
1417         default:
1418                 BUG();
1419         }
1420
1421         be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1422                                NULL);
1423         req->id = cpu_to_le16(q->id);
1424
1425         status = be_mbox_notify_wait(adapter);
1426         q->created = false;
1427
1428         mutex_unlock(&adapter->mbox_lock);
1429         return status;
1430 }
1431
1432 /* Uses MCC */
1433 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1434 {
1435         struct be_mcc_wrb *wrb;
1436         struct be_cmd_req_q_destroy *req;
1437         int status;
1438
1439         spin_lock_bh(&adapter->mcc_lock);
1440
1441         wrb = wrb_from_mccq(adapter);
1442         if (!wrb) {
1443                 status = -EBUSY;
1444                 goto err;
1445         }
1446         req = embedded_payload(wrb);
1447
1448         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1449                                OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1450         req->id = cpu_to_le16(q->id);
1451
1452         status = be_mcc_notify_wait(adapter);
1453         q->created = false;
1454
1455 err:
1456         spin_unlock_bh(&adapter->mcc_lock);
1457         return status;
1458 }
1459
1460 /* Create an rx filtering policy configuration on an i/f
1461  * Will use MBOX only if MCCQ has not been created.
1462  */
1463 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1464                      u32 *if_handle, u32 domain)
1465 {
1466         struct be_mcc_wrb wrb = {0};
1467         struct be_cmd_req_if_create *req;
1468         int status;
1469
1470         req = embedded_payload(&wrb);
1471         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1472                                OPCODE_COMMON_NTWK_INTERFACE_CREATE,
1473                                sizeof(*req), &wrb, NULL);
1474         req->hdr.domain = domain;
1475         req->capability_flags = cpu_to_le32(cap_flags);
1476         req->enable_flags = cpu_to_le32(en_flags);
1477         req->pmac_invalid = true;
1478
1479         status = be_cmd_notify_wait(adapter, &wrb);
1480         if (!status) {
1481                 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb);
1482
1483                 *if_handle = le32_to_cpu(resp->interface_id);
1484
1485                 /* Hack to retrieve VF's pmac-id on BE3 */
1486                 if (BE3_chip(adapter) && be_virtfn(adapter))
1487                         adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
1488         }
1489         return status;
1490 }
1491
1492 /* Uses MCCQ */
1493 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1494 {
1495         struct be_mcc_wrb *wrb;
1496         struct be_cmd_req_if_destroy *req;
1497         int status;
1498
1499         if (interface_id == -1)
1500                 return 0;
1501
1502         spin_lock_bh(&adapter->mcc_lock);
1503
1504         wrb = wrb_from_mccq(adapter);
1505         if (!wrb) {
1506                 status = -EBUSY;
1507                 goto err;
1508         }
1509         req = embedded_payload(wrb);
1510
1511         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1512                                OPCODE_COMMON_NTWK_INTERFACE_DESTROY,
1513                                sizeof(*req), wrb, NULL);
1514         req->hdr.domain = domain;
1515         req->interface_id = cpu_to_le32(interface_id);
1516
1517         status = be_mcc_notify_wait(adapter);
1518 err:
1519         spin_unlock_bh(&adapter->mcc_lock);
1520         return status;
1521 }
1522
1523 /* Get stats is a non embedded command: the request is not embedded inside
1524  * WRB but is a separate dma memory block
1525  * Uses asynchronous MCC
1526  */
1527 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1528 {
1529         struct be_mcc_wrb *wrb;
1530         struct be_cmd_req_hdr *hdr;
1531         int status = 0;
1532
1533         spin_lock_bh(&adapter->mcc_lock);
1534
1535         wrb = wrb_from_mccq(adapter);
1536         if (!wrb) {
1537                 status = -EBUSY;
1538                 goto err;
1539         }
1540         hdr = nonemb_cmd->va;
1541
1542         be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1543                                OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb,
1544                                nonemb_cmd);
1545
1546         /* version 1 of the cmd is not supported only by BE2 */
1547         if (BE2_chip(adapter))
1548                 hdr->version = 0;
1549         if (BE3_chip(adapter) || lancer_chip(adapter))
1550                 hdr->version = 1;
1551         else
1552                 hdr->version = 2;
1553
1554         status = be_mcc_notify(adapter);
1555         if (status)
1556                 goto err;
1557
1558         adapter->stats_cmd_sent = true;
1559
1560 err:
1561         spin_unlock_bh(&adapter->mcc_lock);
1562         return status;
1563 }
1564
1565 /* Lancer Stats */
1566 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1567                                struct be_dma_mem *nonemb_cmd)
1568 {
1569         struct be_mcc_wrb *wrb;
1570         struct lancer_cmd_req_pport_stats *req;
1571         int status = 0;
1572
1573         if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1574                             CMD_SUBSYSTEM_ETH))
1575                 return -EPERM;
1576
1577         spin_lock_bh(&adapter->mcc_lock);
1578
1579         wrb = wrb_from_mccq(adapter);
1580         if (!wrb) {
1581                 status = -EBUSY;
1582                 goto err;
1583         }
1584         req = nonemb_cmd->va;
1585
1586         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1587                                OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size,
1588                                wrb, nonemb_cmd);
1589
1590         req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1591         req->cmd_params.params.reset_stats = 0;
1592
1593         status = be_mcc_notify(adapter);
1594         if (status)
1595                 goto err;
1596
1597         adapter->stats_cmd_sent = true;
1598
1599 err:
1600         spin_unlock_bh(&adapter->mcc_lock);
1601         return status;
1602 }
1603
1604 static int be_mac_to_link_speed(int mac_speed)
1605 {
1606         switch (mac_speed) {
1607         case PHY_LINK_SPEED_ZERO:
1608                 return 0;
1609         case PHY_LINK_SPEED_10MBPS:
1610                 return 10;
1611         case PHY_LINK_SPEED_100MBPS:
1612                 return 100;
1613         case PHY_LINK_SPEED_1GBPS:
1614                 return 1000;
1615         case PHY_LINK_SPEED_10GBPS:
1616                 return 10000;
1617         case PHY_LINK_SPEED_20GBPS:
1618                 return 20000;
1619         case PHY_LINK_SPEED_25GBPS:
1620                 return 25000;
1621         case PHY_LINK_SPEED_40GBPS:
1622                 return 40000;
1623         }
1624         return 0;
1625 }
1626
1627 /* Uses synchronous mcc
1628  * Returns link_speed in Mbps
1629  */
1630 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1631                              u8 *link_status, u32 dom)
1632 {
1633         struct be_mcc_wrb *wrb;
1634         struct be_cmd_req_link_status *req;
1635         int status;
1636
1637         spin_lock_bh(&adapter->mcc_lock);
1638
1639         if (link_status)
1640                 *link_status = LINK_DOWN;
1641
1642         wrb = wrb_from_mccq(adapter);
1643         if (!wrb) {
1644                 status = -EBUSY;
1645                 goto err;
1646         }
1647         req = embedded_payload(wrb);
1648
1649         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1650                                OPCODE_COMMON_NTWK_LINK_STATUS_QUERY,
1651                                sizeof(*req), wrb, NULL);
1652
1653         /* version 1 of the cmd is not supported only by BE2 */
1654         if (!BE2_chip(adapter))
1655                 req->hdr.version = 1;
1656
1657         req->hdr.domain = dom;
1658
1659         status = be_mcc_notify_wait(adapter);
1660         if (!status) {
1661                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1662
1663                 if (link_speed) {
1664                         *link_speed = resp->link_speed ?
1665                                       le16_to_cpu(resp->link_speed) * 10 :
1666                                       be_mac_to_link_speed(resp->mac_speed);
1667
1668                         if (!resp->logical_link_status)
1669                                 *link_speed = 0;
1670                 }
1671                 if (link_status)
1672                         *link_status = resp->logical_link_status;
1673         }
1674
1675 err:
1676         spin_unlock_bh(&adapter->mcc_lock);
1677         return status;
1678 }
1679
1680 /* Uses synchronous mcc */
1681 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1682 {
1683         struct be_mcc_wrb *wrb;
1684         struct be_cmd_req_get_cntl_addnl_attribs *req;
1685         int status = 0;
1686
1687         spin_lock_bh(&adapter->mcc_lock);
1688
1689         wrb = wrb_from_mccq(adapter);
1690         if (!wrb) {
1691                 status = -EBUSY;
1692                 goto err;
1693         }
1694         req = embedded_payload(wrb);
1695
1696         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1697                                OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES,
1698                                sizeof(*req), wrb, NULL);
1699
1700         status = be_mcc_notify(adapter);
1701 err:
1702         spin_unlock_bh(&adapter->mcc_lock);
1703         return status;
1704 }
1705
1706 /* Uses synchronous mcc */
1707 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1708 {
1709         struct be_mcc_wrb *wrb;
1710         struct be_cmd_req_get_fat *req;
1711         int status;
1712
1713         spin_lock_bh(&adapter->mcc_lock);
1714
1715         wrb = wrb_from_mccq(adapter);
1716         if (!wrb) {
1717                 status = -EBUSY;
1718                 goto err;
1719         }
1720         req = embedded_payload(wrb);
1721
1722         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1723                                OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb,
1724                                NULL);
1725         req->fat_operation = cpu_to_le32(QUERY_FAT);
1726         status = be_mcc_notify_wait(adapter);
1727         if (!status) {
1728                 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1729
1730                 if (log_size && resp->log_size)
1731                         *log_size = le32_to_cpu(resp->log_size) -
1732                                         sizeof(u32);
1733         }
1734 err:
1735         spin_unlock_bh(&adapter->mcc_lock);
1736         return status;
1737 }
1738
1739 int be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1740 {
1741         struct be_dma_mem get_fat_cmd;
1742         struct be_mcc_wrb *wrb;
1743         struct be_cmd_req_get_fat *req;
1744         u32 offset = 0, total_size, buf_size,
1745                                 log_offset = sizeof(u32), payload_len;
1746         int status = 0;
1747
1748         if (buf_len == 0)
1749                 return -EIO;
1750
1751         total_size = buf_len;
1752
1753         get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1754         get_fat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
1755                                              get_fat_cmd.size,
1756                                              &get_fat_cmd.dma, GFP_ATOMIC);
1757         if (!get_fat_cmd.va) {
1758                 dev_err(&adapter->pdev->dev,
1759                         "Memory allocation failure while reading FAT data\n");
1760                 return -ENOMEM;
1761         }
1762
1763         spin_lock_bh(&adapter->mcc_lock);
1764
1765         while (total_size) {
1766                 buf_size = min(total_size, (u32)60*1024);
1767                 total_size -= buf_size;
1768
1769                 wrb = wrb_from_mccq(adapter);
1770                 if (!wrb) {
1771                         status = -EBUSY;
1772                         goto err;
1773                 }
1774                 req = get_fat_cmd.va;
1775
1776                 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1777                 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1778                                        OPCODE_COMMON_MANAGE_FAT, payload_len,
1779                                        wrb, &get_fat_cmd);
1780
1781                 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1782                 req->read_log_offset = cpu_to_le32(log_offset);
1783                 req->read_log_length = cpu_to_le32(buf_size);
1784                 req->data_buffer_size = cpu_to_le32(buf_size);
1785
1786                 status = be_mcc_notify_wait(adapter);
1787                 if (!status) {
1788                         struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1789
1790                         memcpy(buf + offset,
1791                                resp->data_buffer,
1792                                le32_to_cpu(resp->read_log_length));
1793                 } else {
1794                         dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1795                         goto err;
1796                 }
1797                 offset += buf_size;
1798                 log_offset += buf_size;
1799         }
1800 err:
1801         dma_free_coherent(&adapter->pdev->dev, get_fat_cmd.size,
1802                           get_fat_cmd.va, get_fat_cmd.dma);
1803         spin_unlock_bh(&adapter->mcc_lock);
1804         return status;
1805 }
1806
1807 /* Uses synchronous mcc */
1808 int be_cmd_get_fw_ver(struct be_adapter *adapter)
1809 {
1810         struct be_mcc_wrb *wrb;
1811         struct be_cmd_req_get_fw_version *req;
1812         int status;
1813
1814         spin_lock_bh(&adapter->mcc_lock);
1815
1816         wrb = wrb_from_mccq(adapter);
1817         if (!wrb) {
1818                 status = -EBUSY;
1819                 goto err;
1820         }
1821
1822         req = embedded_payload(wrb);
1823
1824         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1825                                OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb,
1826                                NULL);
1827         status = be_mcc_notify_wait(adapter);
1828         if (!status) {
1829                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1830
1831                 strlcpy(adapter->fw_ver, resp->firmware_version_string,
1832                         sizeof(adapter->fw_ver));
1833                 strlcpy(adapter->fw_on_flash, resp->fw_on_flash_version_string,
1834                         sizeof(adapter->fw_on_flash));
1835         }
1836 err:
1837         spin_unlock_bh(&adapter->mcc_lock);
1838         return status;
1839 }
1840
1841 /* set the EQ delay interval of an EQ to specified value
1842  * Uses async mcc
1843  */
1844 static int __be_cmd_modify_eqd(struct be_adapter *adapter,
1845                                struct be_set_eqd *set_eqd, int num)
1846 {
1847         struct be_mcc_wrb *wrb;
1848         struct be_cmd_req_modify_eq_delay *req;
1849         int status = 0, i;
1850
1851         spin_lock_bh(&adapter->mcc_lock);
1852
1853         wrb = wrb_from_mccq(adapter);
1854         if (!wrb) {
1855                 status = -EBUSY;
1856                 goto err;
1857         }
1858         req = embedded_payload(wrb);
1859
1860         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1861                                OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb,
1862                                NULL);
1863
1864         req->num_eq = cpu_to_le32(num);
1865         for (i = 0; i < num; i++) {
1866                 req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id);
1867                 req->set_eqd[i].phase = 0;
1868                 req->set_eqd[i].delay_multiplier =
1869                                 cpu_to_le32(set_eqd[i].delay_multiplier);
1870         }
1871
1872         status = be_mcc_notify(adapter);
1873 err:
1874         spin_unlock_bh(&adapter->mcc_lock);
1875         return status;
1876 }
1877
1878 int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd,
1879                       int num)
1880 {
1881         int num_eqs, i = 0;
1882
1883         while (num) {
1884                 num_eqs = min(num, 8);
1885                 __be_cmd_modify_eqd(adapter, &set_eqd[i], num_eqs);
1886                 i += num_eqs;
1887                 num -= num_eqs;
1888         }
1889
1890         return 0;
1891 }
1892
1893 /* Uses sycnhronous mcc */
1894 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1895                        u32 num, u32 domain)
1896 {
1897         struct be_mcc_wrb *wrb;
1898         struct be_cmd_req_vlan_config *req;
1899         int status;
1900
1901         spin_lock_bh(&adapter->mcc_lock);
1902
1903         wrb = wrb_from_mccq(adapter);
1904         if (!wrb) {
1905                 status = -EBUSY;
1906                 goto err;
1907         }
1908         req = embedded_payload(wrb);
1909
1910         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1911                                OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req),
1912                                wrb, NULL);
1913         req->hdr.domain = domain;
1914
1915         req->interface_id = if_id;
1916         req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0;
1917         req->num_vlan = num;
1918         memcpy(req->normal_vlan, vtag_array,
1919                req->num_vlan * sizeof(vtag_array[0]));
1920
1921         status = be_mcc_notify_wait(adapter);
1922 err:
1923         spin_unlock_bh(&adapter->mcc_lock);
1924         return status;
1925 }
1926
1927 static int __be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1928 {
1929         struct be_mcc_wrb *wrb;
1930         struct be_dma_mem *mem = &adapter->rx_filter;
1931         struct be_cmd_req_rx_filter *req = mem->va;
1932         int status;
1933
1934         spin_lock_bh(&adapter->mcc_lock);
1935
1936         wrb = wrb_from_mccq(adapter);
1937         if (!wrb) {
1938                 status = -EBUSY;
1939                 goto err;
1940         }
1941         memset(req, 0, sizeof(*req));
1942         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1943                                OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1944                                wrb, mem);
1945
1946         req->if_id = cpu_to_le32(adapter->if_handle);
1947         req->if_flags_mask = cpu_to_le32(flags);
1948         req->if_flags = (value == ON) ? req->if_flags_mask : 0;
1949
1950         if (flags & BE_IF_FLAGS_MULTICAST) {
1951                 struct netdev_hw_addr *ha;
1952                 int i = 0;
1953
1954                 /* Reset mcast promisc mode if already set by setting mask
1955                  * and not setting flags field
1956                  */
1957                 req->if_flags_mask |=
1958                         cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
1959                                     be_if_cap_flags(adapter));
1960                 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
1961                 netdev_for_each_mc_addr(ha, adapter->netdev)
1962                         memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
1963         }
1964
1965         status = be_mcc_notify(adapter);
1966 err:
1967         spin_unlock_bh(&adapter->mcc_lock);
1968         return status;
1969 }
1970
1971 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1972 {
1973         struct device *dev = &adapter->pdev->dev;
1974
1975         if ((flags & be_if_cap_flags(adapter)) != flags) {
1976                 dev_warn(dev, "Cannot set rx filter flags 0x%x\n", flags);
1977                 dev_warn(dev, "Interface is capable of 0x%x flags only\n",
1978                          be_if_cap_flags(adapter));
1979         }
1980         flags &= be_if_cap_flags(adapter);
1981
1982         return __be_cmd_rx_filter(adapter, flags, value);
1983 }
1984
1985 /* Uses synchrounous mcc */
1986 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1987 {
1988         struct be_mcc_wrb *wrb;
1989         struct be_cmd_req_set_flow_control *req;
1990         int status;
1991
1992         if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
1993                             CMD_SUBSYSTEM_COMMON))
1994                 return -EPERM;
1995
1996         spin_lock_bh(&adapter->mcc_lock);
1997
1998         wrb = wrb_from_mccq(adapter);
1999         if (!wrb) {
2000                 status = -EBUSY;
2001                 goto err;
2002         }
2003         req = embedded_payload(wrb);
2004
2005         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2006                                OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req),
2007                                wrb, NULL);
2008
2009         req->hdr.version = 1;
2010         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
2011         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
2012
2013         status = be_mcc_notify_wait(adapter);
2014
2015 err:
2016         spin_unlock_bh(&adapter->mcc_lock);
2017
2018         if (base_status(status) == MCC_STATUS_FEATURE_NOT_SUPPORTED)
2019                 return  -EOPNOTSUPP;
2020
2021         return status;
2022 }
2023
2024 /* Uses sycn mcc */
2025 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
2026 {
2027         struct be_mcc_wrb *wrb;
2028         struct be_cmd_req_get_flow_control *req;
2029         int status;
2030
2031         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
2032                             CMD_SUBSYSTEM_COMMON))
2033                 return -EPERM;
2034
2035         spin_lock_bh(&adapter->mcc_lock);
2036
2037         wrb = wrb_from_mccq(adapter);
2038         if (!wrb) {
2039                 status = -EBUSY;
2040                 goto err;
2041         }
2042         req = embedded_payload(wrb);
2043
2044         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2045                                OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req),
2046                                wrb, NULL);
2047
2048         status = be_mcc_notify_wait(adapter);
2049         if (!status) {
2050                 struct be_cmd_resp_get_flow_control *resp =
2051                                                 embedded_payload(wrb);
2052
2053                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
2054                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
2055         }
2056
2057 err:
2058         spin_unlock_bh(&adapter->mcc_lock);
2059         return status;
2060 }
2061
2062 /* Uses mbox */
2063 int be_cmd_query_fw_cfg(struct be_adapter *adapter)
2064 {
2065         struct be_mcc_wrb *wrb;
2066         struct be_cmd_req_query_fw_cfg *req;
2067         int status;
2068
2069         if (mutex_lock_interruptible(&adapter->mbox_lock))
2070                 return -1;
2071
2072         wrb = wrb_from_mbox(adapter);
2073         req = embedded_payload(wrb);
2074
2075         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2076                                OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
2077                                sizeof(*req), wrb, NULL);
2078
2079         status = be_mbox_notify_wait(adapter);
2080         if (!status) {
2081                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
2082
2083                 adapter->port_num = le32_to_cpu(resp->phys_port);
2084                 adapter->function_mode = le32_to_cpu(resp->function_mode);
2085                 adapter->function_caps = le32_to_cpu(resp->function_caps);
2086                 adapter->asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
2087                 dev_info(&adapter->pdev->dev,
2088                          "FW config: function_mode=0x%x, function_caps=0x%x\n",
2089                          adapter->function_mode, adapter->function_caps);
2090         }
2091
2092         mutex_unlock(&adapter->mbox_lock);
2093         return status;
2094 }
2095
2096 /* Uses mbox */
2097 int be_cmd_reset_function(struct be_adapter *adapter)
2098 {
2099         struct be_mcc_wrb *wrb;
2100         struct be_cmd_req_hdr *req;
2101         int status;
2102
2103         if (lancer_chip(adapter)) {
2104                 iowrite32(SLI_PORT_CONTROL_IP_MASK,
2105                           adapter->db + SLIPORT_CONTROL_OFFSET);
2106                 status = lancer_wait_ready(adapter);
2107                 if (status)
2108                         dev_err(&adapter->pdev->dev,
2109                                 "Adapter in non recoverable error\n");
2110                 return status;
2111         }
2112
2113         if (mutex_lock_interruptible(&adapter->mbox_lock))
2114                 return -1;
2115
2116         wrb = wrb_from_mbox(adapter);
2117         req = embedded_payload(wrb);
2118
2119         be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
2120                                OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb,
2121                                NULL);
2122
2123         status = be_mbox_notify_wait(adapter);
2124
2125         mutex_unlock(&adapter->mbox_lock);
2126         return status;
2127 }
2128
2129 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
2130                       u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey)
2131 {
2132         struct be_mcc_wrb *wrb;
2133         struct be_cmd_req_rss_config *req;
2134         int status;
2135
2136         if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS))
2137                 return 0;
2138
2139         spin_lock_bh(&adapter->mcc_lock);
2140
2141         wrb = wrb_from_mccq(adapter);
2142         if (!wrb) {
2143                 status = -EBUSY;
2144                 goto err;
2145         }
2146         req = embedded_payload(wrb);
2147
2148         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2149                                OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
2150
2151         req->if_id = cpu_to_le32(adapter->if_handle);
2152         req->enable_rss = cpu_to_le16(rss_hash_opts);
2153         req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
2154
2155         if (!BEx_chip(adapter))
2156                 req->hdr.version = 1;
2157
2158         memcpy(req->cpu_table, rsstable, table_size);
2159         memcpy(req->hash, rss_hkey, RSS_HASH_KEY_LEN);
2160         be_dws_cpu_to_le(req->hash, sizeof(req->hash));
2161
2162         status = be_mcc_notify_wait(adapter);
2163 err:
2164         spin_unlock_bh(&adapter->mcc_lock);
2165         return status;
2166 }
2167
2168 /* Uses sync mcc */
2169 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
2170                             u8 bcn, u8 sts, u8 state)
2171 {
2172         struct be_mcc_wrb *wrb;
2173         struct be_cmd_req_enable_disable_beacon *req;
2174         int status;
2175
2176         spin_lock_bh(&adapter->mcc_lock);
2177
2178         wrb = wrb_from_mccq(adapter);
2179         if (!wrb) {
2180                 status = -EBUSY;
2181                 goto err;
2182         }
2183         req = embedded_payload(wrb);
2184
2185         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2186                                OPCODE_COMMON_ENABLE_DISABLE_BEACON,
2187                                sizeof(*req), wrb, NULL);
2188
2189         req->port_num = port_num;
2190         req->beacon_state = state;
2191         req->beacon_duration = bcn;
2192         req->status_duration = sts;
2193
2194         status = be_mcc_notify_wait(adapter);
2195
2196 err:
2197         spin_unlock_bh(&adapter->mcc_lock);
2198         return status;
2199 }
2200
2201 /* Uses sync mcc */
2202 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2203 {
2204         struct be_mcc_wrb *wrb;
2205         struct be_cmd_req_get_beacon_state *req;
2206         int status;
2207
2208         spin_lock_bh(&adapter->mcc_lock);
2209
2210         wrb = wrb_from_mccq(adapter);
2211         if (!wrb) {
2212                 status = -EBUSY;
2213                 goto err;
2214         }
2215         req = embedded_payload(wrb);
2216
2217         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2218                                OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req),
2219                                wrb, NULL);
2220
2221         req->port_num = port_num;
2222
2223         status = be_mcc_notify_wait(adapter);
2224         if (!status) {
2225                 struct be_cmd_resp_get_beacon_state *resp =
2226                                                 embedded_payload(wrb);
2227
2228                 *state = resp->beacon_state;
2229         }
2230
2231 err:
2232         spin_unlock_bh(&adapter->mcc_lock);
2233         return status;
2234 }
2235
2236 /* Uses sync mcc */
2237 int be_cmd_read_port_transceiver_data(struct be_adapter *adapter,
2238                                       u8 page_num, u8 *data)
2239 {
2240         struct be_dma_mem cmd;
2241         struct be_mcc_wrb *wrb;
2242         struct be_cmd_req_port_type *req;
2243         int status;
2244
2245         if (page_num > TR_PAGE_A2)
2246                 return -EINVAL;
2247
2248         cmd.size = sizeof(struct be_cmd_resp_port_type);
2249         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
2250                                      GFP_ATOMIC);
2251         if (!cmd.va) {
2252                 dev_err(&adapter->pdev->dev, "Memory allocation failed\n");
2253                 return -ENOMEM;
2254         }
2255
2256         spin_lock_bh(&adapter->mcc_lock);
2257
2258         wrb = wrb_from_mccq(adapter);
2259         if (!wrb) {
2260                 status = -EBUSY;
2261                 goto err;
2262         }
2263         req = cmd.va;
2264
2265         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2266                                OPCODE_COMMON_READ_TRANSRECV_DATA,
2267                                cmd.size, wrb, &cmd);
2268
2269         req->port = cpu_to_le32(adapter->hba_port_num);
2270         req->page_num = cpu_to_le32(page_num);
2271         status = be_mcc_notify_wait(adapter);
2272         if (!status) {
2273                 struct be_cmd_resp_port_type *resp = cmd.va;
2274
2275                 memcpy(data, resp->page_data, PAGE_DATA_LEN);
2276         }
2277 err:
2278         spin_unlock_bh(&adapter->mcc_lock);
2279         dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
2280         return status;
2281 }
2282
2283 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2284                             u32 data_size, u32 data_offset,
2285                             const char *obj_name, u32 *data_written,
2286                             u8 *change_status, u8 *addn_status)
2287 {
2288         struct be_mcc_wrb *wrb;
2289         struct lancer_cmd_req_write_object *req;
2290         struct lancer_cmd_resp_write_object *resp;
2291         void *ctxt = NULL;
2292         int status;
2293
2294         spin_lock_bh(&adapter->mcc_lock);
2295         adapter->flash_status = 0;
2296
2297         wrb = wrb_from_mccq(adapter);
2298         if (!wrb) {
2299                 status = -EBUSY;
2300                 goto err_unlock;
2301         }
2302
2303         req = embedded_payload(wrb);
2304
2305         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2306                                OPCODE_COMMON_WRITE_OBJECT,
2307                                sizeof(struct lancer_cmd_req_write_object), wrb,
2308                                NULL);
2309
2310         ctxt = &req->context;
2311         AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2312                       write_length, ctxt, data_size);
2313
2314         if (data_size == 0)
2315                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2316                               eof, ctxt, 1);
2317         else
2318                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2319                               eof, ctxt, 0);
2320
2321         be_dws_cpu_to_le(ctxt, sizeof(req->context));
2322         req->write_offset = cpu_to_le32(data_offset);
2323         strlcpy(req->object_name, obj_name, sizeof(req->object_name));
2324         req->descriptor_count = cpu_to_le32(1);
2325         req->buf_len = cpu_to_le32(data_size);
2326         req->addr_low = cpu_to_le32((cmd->dma +
2327                                      sizeof(struct lancer_cmd_req_write_object))
2328                                     & 0xFFFFFFFF);
2329         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2330                                 sizeof(struct lancer_cmd_req_write_object)));
2331
2332         status = be_mcc_notify(adapter);
2333         if (status)
2334                 goto err_unlock;
2335
2336         spin_unlock_bh(&adapter->mcc_lock);
2337
2338         if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2339                                          msecs_to_jiffies(60000)))
2340                 status = -ETIMEDOUT;
2341         else
2342                 status = adapter->flash_status;
2343
2344         resp = embedded_payload(wrb);
2345         if (!status) {
2346                 *data_written = le32_to_cpu(resp->actual_write_len);
2347                 *change_status = resp->change_status;
2348         } else {
2349                 *addn_status = resp->additional_status;
2350         }
2351
2352         return status;
2353
2354 err_unlock:
2355         spin_unlock_bh(&adapter->mcc_lock);
2356         return status;
2357 }
2358
2359 int be_cmd_query_cable_type(struct be_adapter *adapter)
2360 {
2361         u8 page_data[PAGE_DATA_LEN];
2362         int status;
2363
2364         status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2365                                                    page_data);
2366         if (!status) {
2367                 switch (adapter->phy.interface_type) {
2368                 case PHY_TYPE_QSFP:
2369                         adapter->phy.cable_type =
2370                                 page_data[QSFP_PLUS_CABLE_TYPE_OFFSET];
2371                         break;
2372                 case PHY_TYPE_SFP_PLUS_10GB:
2373                         adapter->phy.cable_type =
2374                                 page_data[SFP_PLUS_CABLE_TYPE_OFFSET];
2375                         break;
2376                 default:
2377                         adapter->phy.cable_type = 0;
2378                         break;
2379                 }
2380         }
2381         return status;
2382 }
2383
2384 int be_cmd_query_sfp_info(struct be_adapter *adapter)
2385 {
2386         u8 page_data[PAGE_DATA_LEN];
2387         int status;
2388
2389         status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2390                                                    page_data);
2391         if (!status) {
2392                 strlcpy(adapter->phy.vendor_name, page_data +
2393                         SFP_VENDOR_NAME_OFFSET, SFP_VENDOR_NAME_LEN - 1);
2394                 strlcpy(adapter->phy.vendor_pn,
2395                         page_data + SFP_VENDOR_PN_OFFSET,
2396                         SFP_VENDOR_NAME_LEN - 1);
2397         }
2398
2399         return status;
2400 }
2401
2402 int lancer_cmd_delete_object(struct be_adapter *adapter, const char *obj_name)
2403 {
2404         struct lancer_cmd_req_delete_object *req;
2405         struct be_mcc_wrb *wrb;
2406         int status;
2407
2408         spin_lock_bh(&adapter->mcc_lock);
2409
2410         wrb = wrb_from_mccq(adapter);
2411         if (!wrb) {
2412                 status = -EBUSY;
2413                 goto err;
2414         }
2415
2416         req = embedded_payload(wrb);
2417
2418         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2419                                OPCODE_COMMON_DELETE_OBJECT,
2420                                sizeof(*req), wrb, NULL);
2421
2422         strlcpy(req->object_name, obj_name, sizeof(req->object_name));
2423
2424         status = be_mcc_notify_wait(adapter);
2425 err:
2426         spin_unlock_bh(&adapter->mcc_lock);
2427         return status;
2428 }
2429
2430 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2431                            u32 data_size, u32 data_offset, const char *obj_name,
2432                            u32 *data_read, u32 *eof, u8 *addn_status)
2433 {
2434         struct be_mcc_wrb *wrb;
2435         struct lancer_cmd_req_read_object *req;
2436         struct lancer_cmd_resp_read_object *resp;
2437         int status;
2438
2439         spin_lock_bh(&adapter->mcc_lock);
2440
2441         wrb = wrb_from_mccq(adapter);
2442         if (!wrb) {
2443                 status = -EBUSY;
2444                 goto err_unlock;
2445         }
2446
2447         req = embedded_payload(wrb);
2448
2449         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2450                                OPCODE_COMMON_READ_OBJECT,
2451                                sizeof(struct lancer_cmd_req_read_object), wrb,
2452                                NULL);
2453
2454         req->desired_read_len = cpu_to_le32(data_size);
2455         req->read_offset = cpu_to_le32(data_offset);
2456         strcpy(req->object_name, obj_name);
2457         req->descriptor_count = cpu_to_le32(1);
2458         req->buf_len = cpu_to_le32(data_size);
2459         req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2460         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2461
2462         status = be_mcc_notify_wait(adapter);
2463
2464         resp = embedded_payload(wrb);
2465         if (!status) {
2466                 *data_read = le32_to_cpu(resp->actual_read_len);
2467                 *eof = le32_to_cpu(resp->eof);
2468         } else {
2469                 *addn_status = resp->additional_status;
2470         }
2471
2472 err_unlock:
2473         spin_unlock_bh(&adapter->mcc_lock);
2474         return status;
2475 }
2476
2477 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
2478                           u32 flash_type, u32 flash_opcode, u32 img_offset,
2479                           u32 buf_size)
2480 {
2481         struct be_mcc_wrb *wrb;
2482         struct be_cmd_write_flashrom *req;
2483         int status;
2484
2485         spin_lock_bh(&adapter->mcc_lock);
2486         adapter->flash_status = 0;
2487
2488         wrb = wrb_from_mccq(adapter);
2489         if (!wrb) {
2490                 status = -EBUSY;
2491                 goto err_unlock;
2492         }
2493         req = cmd->va;
2494
2495         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2496                                OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb,
2497                                cmd);
2498
2499         req->params.op_type = cpu_to_le32(flash_type);
2500         if (flash_type == OPTYPE_OFFSET_SPECIFIED)
2501                 req->params.offset = cpu_to_le32(img_offset);
2502
2503         req->params.op_code = cpu_to_le32(flash_opcode);
2504         req->params.data_buf_size = cpu_to_le32(buf_size);
2505
2506         status = be_mcc_notify(adapter);
2507         if (status)
2508                 goto err_unlock;
2509
2510         spin_unlock_bh(&adapter->mcc_lock);
2511
2512         if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2513                                          msecs_to_jiffies(40000)))
2514                 status = -ETIMEDOUT;
2515         else
2516                 status = adapter->flash_status;
2517
2518         return status;
2519
2520 err_unlock:
2521         spin_unlock_bh(&adapter->mcc_lock);
2522         return status;
2523 }
2524
2525 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2526                          u16 img_optype, u32 img_offset, u32 crc_offset)
2527 {
2528         struct be_cmd_read_flash_crc *req;
2529         struct be_mcc_wrb *wrb;
2530         int status;
2531
2532         spin_lock_bh(&adapter->mcc_lock);
2533
2534         wrb = wrb_from_mccq(adapter);
2535         if (!wrb) {
2536                 status = -EBUSY;
2537                 goto err;
2538         }
2539         req = embedded_payload(wrb);
2540
2541         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2542                                OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2543                                wrb, NULL);
2544
2545         req->params.op_type = cpu_to_le32(img_optype);
2546         if (img_optype == OPTYPE_OFFSET_SPECIFIED)
2547                 req->params.offset = cpu_to_le32(img_offset + crc_offset);
2548         else
2549                 req->params.offset = cpu_to_le32(crc_offset);
2550
2551         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2552         req->params.data_buf_size = cpu_to_le32(0x4);
2553
2554         status = be_mcc_notify_wait(adapter);
2555         if (!status)
2556                 memcpy(flashed_crc, req->crc, 4);
2557
2558 err:
2559         spin_unlock_bh(&adapter->mcc_lock);
2560         return status;
2561 }
2562
2563 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2564                             struct be_dma_mem *nonemb_cmd)
2565 {
2566         struct be_mcc_wrb *wrb;
2567         struct be_cmd_req_acpi_wol_magic_config *req;
2568         int status;
2569
2570         spin_lock_bh(&adapter->mcc_lock);
2571
2572         wrb = wrb_from_mccq(adapter);
2573         if (!wrb) {
2574                 status = -EBUSY;
2575                 goto err;
2576         }
2577         req = nonemb_cmd->va;
2578
2579         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2580                                OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req),
2581                                wrb, nonemb_cmd);
2582         memcpy(req->magic_mac, mac, ETH_ALEN);
2583
2584         status = be_mcc_notify_wait(adapter);
2585
2586 err:
2587         spin_unlock_bh(&adapter->mcc_lock);
2588         return status;
2589 }
2590
2591 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2592                         u8 loopback_type, u8 enable)
2593 {
2594         struct be_mcc_wrb *wrb;
2595         struct be_cmd_req_set_lmode *req;
2596         int status;
2597
2598         spin_lock_bh(&adapter->mcc_lock);
2599
2600         wrb = wrb_from_mccq(adapter);
2601         if (!wrb) {
2602                 status = -EBUSY;
2603                 goto err;
2604         }
2605
2606         req = embedded_payload(wrb);
2607
2608         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2609                                OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req),
2610                                wrb, NULL);
2611
2612         req->src_port = port_num;
2613         req->dest_port = port_num;
2614         req->loopback_type = loopback_type;
2615         req->loopback_state = enable;
2616
2617         status = be_mcc_notify_wait(adapter);
2618 err:
2619         spin_unlock_bh(&adapter->mcc_lock);
2620         return status;
2621 }
2622
2623 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2624                          u32 loopback_type, u32 pkt_size, u32 num_pkts,
2625                          u64 pattern)
2626 {
2627         struct be_mcc_wrb *wrb;
2628         struct be_cmd_req_loopback_test *req;
2629         struct be_cmd_resp_loopback_test *resp;
2630         int status;
2631
2632         spin_lock_bh(&adapter->mcc_lock);
2633
2634         wrb = wrb_from_mccq(adapter);
2635         if (!wrb) {
2636                 status = -EBUSY;
2637                 goto err;
2638         }
2639
2640         req = embedded_payload(wrb);
2641
2642         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2643                                OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb,
2644                                NULL);
2645
2646         req->hdr.timeout = cpu_to_le32(15);
2647         req->pattern = cpu_to_le64(pattern);
2648         req->src_port = cpu_to_le32(port_num);
2649         req->dest_port = cpu_to_le32(port_num);
2650         req->pkt_size = cpu_to_le32(pkt_size);
2651         req->num_pkts = cpu_to_le32(num_pkts);
2652         req->loopback_type = cpu_to_le32(loopback_type);
2653
2654         status = be_mcc_notify(adapter);
2655         if (status)
2656                 goto err;
2657
2658         spin_unlock_bh(&adapter->mcc_lock);
2659
2660         wait_for_completion(&adapter->et_cmd_compl);
2661         resp = embedded_payload(wrb);
2662         status = le32_to_cpu(resp->status);
2663
2664         return status;
2665 err:
2666         spin_unlock_bh(&adapter->mcc_lock);
2667         return status;
2668 }
2669
2670 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2671                         u32 byte_cnt, struct be_dma_mem *cmd)
2672 {
2673         struct be_mcc_wrb *wrb;
2674         struct be_cmd_req_ddrdma_test *req;
2675         int status;
2676         int i, j = 0;
2677
2678         spin_lock_bh(&adapter->mcc_lock);
2679
2680         wrb = wrb_from_mccq(adapter);
2681         if (!wrb) {
2682                 status = -EBUSY;
2683                 goto err;
2684         }
2685         req = cmd->va;
2686         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2687                                OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb,
2688                                cmd);
2689
2690         req->pattern = cpu_to_le64(pattern);
2691         req->byte_count = cpu_to_le32(byte_cnt);
2692         for (i = 0; i < byte_cnt; i++) {
2693                 req->snd_buff[i] = (u8)(pattern >> (j*8));
2694                 j++;
2695                 if (j > 7)
2696                         j = 0;
2697         }
2698
2699         status = be_mcc_notify_wait(adapter);
2700
2701         if (!status) {
2702                 struct be_cmd_resp_ddrdma_test *resp;
2703
2704                 resp = cmd->va;
2705                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2706                     resp->snd_err) {
2707                         status = -1;
2708                 }
2709         }
2710
2711 err:
2712         spin_unlock_bh(&adapter->mcc_lock);
2713         return status;
2714 }
2715
2716 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2717                             struct be_dma_mem *nonemb_cmd)
2718 {
2719         struct be_mcc_wrb *wrb;
2720         struct be_cmd_req_seeprom_read *req;
2721         int status;
2722
2723         spin_lock_bh(&adapter->mcc_lock);
2724
2725         wrb = wrb_from_mccq(adapter);
2726         if (!wrb) {
2727                 status = -EBUSY;
2728                 goto err;
2729         }
2730         req = nonemb_cmd->va;
2731
2732         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2733                                OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2734                                nonemb_cmd);
2735
2736         status = be_mcc_notify_wait(adapter);
2737
2738 err:
2739         spin_unlock_bh(&adapter->mcc_lock);
2740         return status;
2741 }
2742
2743 int be_cmd_get_phy_info(struct be_adapter *adapter)
2744 {
2745         struct be_mcc_wrb *wrb;
2746         struct be_cmd_req_get_phy_info *req;
2747         struct be_dma_mem cmd;
2748         int status;
2749
2750         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
2751                             CMD_SUBSYSTEM_COMMON))
2752                 return -EPERM;
2753
2754         spin_lock_bh(&adapter->mcc_lock);
2755
2756         wrb = wrb_from_mccq(adapter);
2757         if (!wrb) {
2758                 status = -EBUSY;
2759                 goto err;
2760         }
2761         cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2762         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
2763                                      GFP_ATOMIC);
2764         if (!cmd.va) {
2765                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2766                 status = -ENOMEM;
2767                 goto err;
2768         }
2769
2770         req = cmd.va;
2771
2772         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2773                                OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2774                                wrb, &cmd);
2775
2776         status = be_mcc_notify_wait(adapter);
2777         if (!status) {
2778                 struct be_phy_info *resp_phy_info =
2779                                 cmd.va + sizeof(struct be_cmd_req_hdr);
2780
2781                 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2782                 adapter->phy.interface_type =
2783                         le16_to_cpu(resp_phy_info->interface_type);
2784                 adapter->phy.auto_speeds_supported =
2785                         le16_to_cpu(resp_phy_info->auto_speeds_supported);
2786                 adapter->phy.fixed_speeds_supported =
2787                         le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2788                 adapter->phy.misc_params =
2789                         le32_to_cpu(resp_phy_info->misc_params);
2790
2791                 if (BE2_chip(adapter)) {
2792                         adapter->phy.fixed_speeds_supported =
2793                                 BE_SUPPORTED_SPEED_10GBPS |
2794                                 BE_SUPPORTED_SPEED_1GBPS;
2795                 }
2796         }
2797         dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
2798 err:
2799         spin_unlock_bh(&adapter->mcc_lock);
2800         return status;
2801 }
2802
2803 static int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2804 {
2805         struct be_mcc_wrb *wrb;
2806         struct be_cmd_req_set_qos *req;
2807         int status;
2808
2809         spin_lock_bh(&adapter->mcc_lock);
2810
2811         wrb = wrb_from_mccq(adapter);
2812         if (!wrb) {
2813                 status = -EBUSY;
2814                 goto err;
2815         }
2816
2817         req = embedded_payload(wrb);
2818
2819         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2820                                OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
2821
2822         req->hdr.domain = domain;
2823         req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2824         req->max_bps_nic = cpu_to_le32(bps);
2825
2826         status = be_mcc_notify_wait(adapter);
2827
2828 err:
2829         spin_unlock_bh(&adapter->mcc_lock);
2830         return status;
2831 }
2832
2833 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2834 {
2835         struct be_mcc_wrb *wrb;
2836         struct be_cmd_req_cntl_attribs *req;
2837         struct be_cmd_resp_cntl_attribs *resp;
2838         int status;
2839         int payload_len = max(sizeof(*req), sizeof(*resp));
2840         struct mgmt_controller_attrib *attribs;
2841         struct be_dma_mem attribs_cmd;
2842
2843         if (mutex_lock_interruptible(&adapter->mbox_lock))
2844                 return -1;
2845
2846         memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2847         attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2848         attribs_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
2849                                              attribs_cmd.size,
2850                                              &attribs_cmd.dma, GFP_ATOMIC);
2851         if (!attribs_cmd.va) {
2852                 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
2853                 status = -ENOMEM;
2854                 goto err;
2855         }
2856
2857         wrb = wrb_from_mbox(adapter);
2858         if (!wrb) {
2859                 status = -EBUSY;
2860                 goto err;
2861         }
2862         req = attribs_cmd.va;
2863
2864         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2865                                OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len,
2866                                wrb, &attribs_cmd);
2867
2868         status = be_mbox_notify_wait(adapter);
2869         if (!status) {
2870                 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
2871                 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2872         }
2873
2874 err:
2875         mutex_unlock(&adapter->mbox_lock);
2876         if (attribs_cmd.va)
2877                 dma_free_coherent(&adapter->pdev->dev, attribs_cmd.size,
2878                                   attribs_cmd.va, attribs_cmd.dma);
2879         return status;
2880 }
2881
2882 /* Uses mbox */
2883 int be_cmd_req_native_mode(struct be_adapter *adapter)
2884 {
2885         struct be_mcc_wrb *wrb;
2886         struct be_cmd_req_set_func_cap *req;
2887         int status;
2888
2889         if (mutex_lock_interruptible(&adapter->mbox_lock))
2890                 return -1;
2891
2892         wrb = wrb_from_mbox(adapter);
2893         if (!wrb) {
2894                 status = -EBUSY;
2895                 goto err;
2896         }
2897
2898         req = embedded_payload(wrb);
2899
2900         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2901                                OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP,
2902                                sizeof(*req), wrb, NULL);
2903
2904         req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2905                                 CAPABILITY_BE3_NATIVE_ERX_API);
2906         req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2907
2908         status = be_mbox_notify_wait(adapter);
2909         if (!status) {
2910                 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2911
2912                 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2913                                         CAPABILITY_BE3_NATIVE_ERX_API;
2914                 if (!adapter->be3_native)
2915                         dev_warn(&adapter->pdev->dev,
2916                                  "adapter not in advanced mode\n");
2917         }
2918 err:
2919         mutex_unlock(&adapter->mbox_lock);
2920         return status;
2921 }
2922
2923 /* Get privilege(s) for a function */
2924 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2925                              u32 domain)
2926 {
2927         struct be_mcc_wrb *wrb;
2928         struct be_cmd_req_get_fn_privileges *req;
2929         int status;
2930
2931         spin_lock_bh(&adapter->mcc_lock);
2932
2933         wrb = wrb_from_mccq(adapter);
2934         if (!wrb) {
2935                 status = -EBUSY;
2936                 goto err;
2937         }
2938
2939         req = embedded_payload(wrb);
2940
2941         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2942                                OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
2943                                wrb, NULL);
2944
2945         req->hdr.domain = domain;
2946
2947         status = be_mcc_notify_wait(adapter);
2948         if (!status) {
2949                 struct be_cmd_resp_get_fn_privileges *resp =
2950                                                 embedded_payload(wrb);
2951
2952                 *privilege = le32_to_cpu(resp->privilege_mask);
2953
2954                 /* In UMC mode FW does not return right privileges.
2955                  * Override with correct privilege equivalent to PF.
2956                  */
2957                 if (BEx_chip(adapter) && be_is_mc(adapter) &&
2958                     be_physfn(adapter))
2959                         *privilege = MAX_PRIVILEGES;
2960         }
2961
2962 err:
2963         spin_unlock_bh(&adapter->mcc_lock);
2964         return status;
2965 }
2966
2967 /* Set privilege(s) for a function */
2968 int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
2969                              u32 domain)
2970 {
2971         struct be_mcc_wrb *wrb;
2972         struct be_cmd_req_set_fn_privileges *req;
2973         int status;
2974
2975         spin_lock_bh(&adapter->mcc_lock);
2976
2977         wrb = wrb_from_mccq(adapter);
2978         if (!wrb) {
2979                 status = -EBUSY;
2980                 goto err;
2981         }
2982
2983         req = embedded_payload(wrb);
2984         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2985                                OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
2986                                wrb, NULL);
2987         req->hdr.domain = domain;
2988         if (lancer_chip(adapter))
2989                 req->privileges_lancer = cpu_to_le32(privileges);
2990         else
2991                 req->privileges = cpu_to_le32(privileges);
2992
2993         status = be_mcc_notify_wait(adapter);
2994 err:
2995         spin_unlock_bh(&adapter->mcc_lock);
2996         return status;
2997 }
2998
2999 /* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
3000  * pmac_id_valid: false => pmac_id or MAC address is requested.
3001  *                If pmac_id is returned, pmac_id_valid is returned as true
3002  */
3003 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
3004                              bool *pmac_id_valid, u32 *pmac_id, u32 if_handle,
3005                              u8 domain)
3006 {
3007         struct be_mcc_wrb *wrb;
3008         struct be_cmd_req_get_mac_list *req;
3009         int status;
3010         int mac_count;
3011         struct be_dma_mem get_mac_list_cmd;
3012         int i;
3013
3014         memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
3015         get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
3016         get_mac_list_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3017                                                   get_mac_list_cmd.size,
3018                                                   &get_mac_list_cmd.dma,
3019                                                   GFP_ATOMIC);
3020
3021         if (!get_mac_list_cmd.va) {
3022                 dev_err(&adapter->pdev->dev,
3023                         "Memory allocation failure during GET_MAC_LIST\n");
3024                 return -ENOMEM;
3025         }
3026
3027         spin_lock_bh(&adapter->mcc_lock);
3028
3029         wrb = wrb_from_mccq(adapter);
3030         if (!wrb) {
3031                 status = -EBUSY;
3032                 goto out;
3033         }
3034
3035         req = get_mac_list_cmd.va;
3036
3037         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3038                                OPCODE_COMMON_GET_MAC_LIST,
3039                                get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
3040         req->hdr.domain = domain;
3041         req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
3042         if (*pmac_id_valid) {
3043                 req->mac_id = cpu_to_le32(*pmac_id);
3044                 req->iface_id = cpu_to_le16(if_handle);
3045                 req->perm_override = 0;
3046         } else {
3047                 req->perm_override = 1;
3048         }
3049
3050         status = be_mcc_notify_wait(adapter);
3051         if (!status) {
3052                 struct be_cmd_resp_get_mac_list *resp =
3053                                                 get_mac_list_cmd.va;
3054
3055                 if (*pmac_id_valid) {
3056                         memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
3057                                ETH_ALEN);
3058                         goto out;
3059                 }
3060
3061                 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
3062                 /* Mac list returned could contain one or more active mac_ids
3063                  * or one or more true or pseudo permanent mac addresses.
3064                  * If an active mac_id is present, return first active mac_id
3065                  * found.
3066                  */
3067                 for (i = 0; i < mac_count; i++) {
3068                         struct get_list_macaddr *mac_entry;
3069                         u16 mac_addr_size;
3070                         u32 mac_id;
3071
3072                         mac_entry = &resp->macaddr_list[i];
3073                         mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
3074                         /* mac_id is a 32 bit value and mac_addr size
3075                          * is 6 bytes
3076                          */
3077                         if (mac_addr_size == sizeof(u32)) {
3078                                 *pmac_id_valid = true;
3079                                 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
3080                                 *pmac_id = le32_to_cpu(mac_id);
3081                                 goto out;
3082                         }
3083                 }
3084                 /* If no active mac_id found, return first mac addr */
3085                 *pmac_id_valid = false;
3086                 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
3087                        ETH_ALEN);
3088         }
3089
3090 out:
3091         spin_unlock_bh(&adapter->mcc_lock);
3092         dma_free_coherent(&adapter->pdev->dev, get_mac_list_cmd.size,
3093                           get_mac_list_cmd.va, get_mac_list_cmd.dma);
3094         return status;
3095 }
3096
3097 int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id,
3098                           u8 *mac, u32 if_handle, bool active, u32 domain)
3099 {
3100         if (!active)
3101                 be_cmd_get_mac_from_list(adapter, mac, &active, &curr_pmac_id,
3102                                          if_handle, domain);
3103         if (BEx_chip(adapter))
3104                 return be_cmd_mac_addr_query(adapter, mac, false,
3105                                              if_handle, curr_pmac_id);
3106         else
3107                 /* Fetch the MAC address using pmac_id */
3108                 return be_cmd_get_mac_from_list(adapter, mac, &active,
3109                                                 &curr_pmac_id,
3110                                                 if_handle, domain);
3111 }
3112
3113 int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
3114 {
3115         int status;
3116         bool pmac_valid = false;
3117
3118         eth_zero_addr(mac);
3119
3120         if (BEx_chip(adapter)) {
3121                 if (be_physfn(adapter))
3122                         status = be_cmd_mac_addr_query(adapter, mac, true, 0,
3123                                                        0);
3124                 else
3125                         status = be_cmd_mac_addr_query(adapter, mac, false,
3126                                                        adapter->if_handle, 0);
3127         } else {
3128                 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
3129                                                   NULL, adapter->if_handle, 0);
3130         }
3131
3132         return status;
3133 }
3134
3135 /* Uses synchronous MCCQ */
3136 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
3137                         u8 mac_count, u32 domain)
3138 {
3139         struct be_mcc_wrb *wrb;
3140         struct be_cmd_req_set_mac_list *req;
3141         int status;
3142         struct be_dma_mem cmd;
3143
3144         memset(&cmd, 0, sizeof(struct be_dma_mem));
3145         cmd.size = sizeof(struct be_cmd_req_set_mac_list);
3146         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3147                                      GFP_KERNEL);
3148         if (!cmd.va)
3149                 return -ENOMEM;
3150
3151         spin_lock_bh(&adapter->mcc_lock);
3152
3153         wrb = wrb_from_mccq(adapter);
3154         if (!wrb) {
3155                 status = -EBUSY;
3156                 goto err;
3157         }
3158
3159         req = cmd.va;
3160         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3161                                OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
3162                                wrb, &cmd);
3163
3164         req->hdr.domain = domain;
3165         req->mac_count = mac_count;
3166         if (mac_count)
3167                 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
3168
3169         status = be_mcc_notify_wait(adapter);
3170
3171 err:
3172         dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
3173         spin_unlock_bh(&adapter->mcc_lock);
3174         return status;
3175 }
3176
3177 /* Wrapper to delete any active MACs and provision the new mac.
3178  * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
3179  * current list are active.
3180  */
3181 int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
3182 {
3183         bool active_mac = false;
3184         u8 old_mac[ETH_ALEN];
3185         u32 pmac_id;
3186         int status;
3187
3188         status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
3189                                           &pmac_id, if_id, dom);
3190
3191         if (!status && active_mac)
3192                 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
3193
3194         return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
3195 }
3196
3197 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
3198                           u32 domain, u16 intf_id, u16 hsw_mode, u8 spoofchk)
3199 {
3200         struct be_mcc_wrb *wrb;
3201         struct be_cmd_req_set_hsw_config *req;
3202         void *ctxt;
3203         int status;
3204
3205         spin_lock_bh(&adapter->mcc_lock);
3206
3207         wrb = wrb_from_mccq(adapter);
3208         if (!wrb) {
3209                 status = -EBUSY;
3210                 goto err;
3211         }
3212
3213         req = embedded_payload(wrb);
3214         ctxt = &req->context;
3215
3216         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3217                                OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb,
3218                                NULL);
3219
3220         req->hdr.domain = domain;
3221         AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
3222         if (pvid) {
3223                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
3224                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
3225         }
3226         if (!BEx_chip(adapter) && hsw_mode) {
3227                 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id,
3228                               ctxt, adapter->hba_port_num);
3229                 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1);
3230                 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type,
3231                               ctxt, hsw_mode);
3232         }
3233
3234         /* Enable/disable both mac and vlan spoof checking */
3235         if (!BEx_chip(adapter) && spoofchk) {
3236                 AMAP_SET_BITS(struct amap_set_hsw_context, mac_spoofchk,
3237                               ctxt, spoofchk);
3238                 AMAP_SET_BITS(struct amap_set_hsw_context, vlan_spoofchk,
3239                               ctxt, spoofchk);
3240         }
3241
3242         be_dws_cpu_to_le(req->context, sizeof(req->context));
3243         status = be_mcc_notify_wait(adapter);
3244
3245 err:
3246         spin_unlock_bh(&adapter->mcc_lock);
3247         return status;
3248 }
3249
3250 /* Get Hyper switch config */
3251 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
3252                           u32 domain, u16 intf_id, u8 *mode, bool *spoofchk)
3253 {
3254         struct be_mcc_wrb *wrb;
3255         struct be_cmd_req_get_hsw_config *req;
3256         void *ctxt;
3257         int status;
3258         u16 vid;
3259
3260         spin_lock_bh(&adapter->mcc_lock);
3261
3262         wrb = wrb_from_mccq(adapter);
3263         if (!wrb) {
3264                 status = -EBUSY;
3265                 goto err;
3266         }
3267
3268         req = embedded_payload(wrb);
3269         ctxt = &req->context;
3270
3271         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3272                                OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb,
3273                                NULL);
3274
3275         req->hdr.domain = domain;
3276         AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3277                       ctxt, intf_id);
3278         AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
3279
3280         if (!BEx_chip(adapter) && mode) {
3281                 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3282                               ctxt, adapter->hba_port_num);
3283                 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1);
3284         }
3285         be_dws_cpu_to_le(req->context, sizeof(req->context));
3286
3287         status = be_mcc_notify_wait(adapter);
3288         if (!status) {
3289                 struct be_cmd_resp_get_hsw_config *resp =
3290                                                 embedded_payload(wrb);
3291
3292                 be_dws_le_to_cpu(&resp->context, sizeof(resp->context));
3293                 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3294                                     pvid, &resp->context);
3295                 if (pvid)
3296                         *pvid = le16_to_cpu(vid);
3297                 if (mode)
3298                         *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3299                                               port_fwd_type, &resp->context);
3300                 if (spoofchk)
3301                         *spoofchk =
3302                                 AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3303                                               spoofchk, &resp->context);
3304         }
3305
3306 err:
3307         spin_unlock_bh(&adapter->mcc_lock);
3308         return status;
3309 }
3310
3311 static bool be_is_wol_excluded(struct be_adapter *adapter)
3312 {
3313         struct pci_dev *pdev = adapter->pdev;
3314
3315         if (be_virtfn(adapter))
3316                 return true;
3317
3318         switch (pdev->subsystem_device) {
3319         case OC_SUBSYS_DEVICE_ID1:
3320         case OC_SUBSYS_DEVICE_ID2:
3321         case OC_SUBSYS_DEVICE_ID3:
3322         case OC_SUBSYS_DEVICE_ID4:
3323                 return true;
3324         default:
3325                 return false;
3326         }
3327 }
3328
3329 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
3330 {
3331         struct be_mcc_wrb *wrb;
3332         struct be_cmd_req_acpi_wol_magic_config_v1 *req;
3333         int status = 0;
3334         struct be_dma_mem cmd;
3335
3336         if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3337                             CMD_SUBSYSTEM_ETH))
3338                 return -EPERM;
3339
3340         if (be_is_wol_excluded(adapter))
3341                 return status;
3342
3343         if (mutex_lock_interruptible(&adapter->mbox_lock))
3344                 return -1;
3345
3346         memset(&cmd, 0, sizeof(struct be_dma_mem));
3347         cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
3348         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3349                                      GFP_ATOMIC);
3350         if (!cmd.va) {
3351                 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
3352                 status = -ENOMEM;
3353                 goto err;
3354         }
3355
3356         wrb = wrb_from_mbox(adapter);
3357         if (!wrb) {
3358                 status = -EBUSY;
3359                 goto err;
3360         }
3361
3362         req = cmd.va;
3363
3364         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
3365                                OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3366                                sizeof(*req), wrb, &cmd);
3367
3368         req->hdr.version = 1;
3369         req->query_options = BE_GET_WOL_CAP;
3370
3371         status = be_mbox_notify_wait(adapter);
3372         if (!status) {
3373                 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
3374
3375                 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *)cmd.va;
3376
3377                 adapter->wol_cap = resp->wol_settings;
3378                 if (adapter->wol_cap & BE_WOL_CAP)
3379                         adapter->wol_en = true;
3380         }
3381 err:
3382         mutex_unlock(&adapter->mbox_lock);
3383         if (cmd.va)
3384                 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
3385                                   cmd.dma);
3386         return status;
3387
3388 }
3389
3390 int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level)
3391 {
3392         struct be_dma_mem extfat_cmd;
3393         struct be_fat_conf_params *cfgs;
3394         int status;
3395         int i, j;
3396
3397         memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
3398         extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
3399         extfat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3400                                             extfat_cmd.size, &extfat_cmd.dma,
3401                                             GFP_ATOMIC);
3402         if (!extfat_cmd.va)
3403                 return -ENOMEM;
3404
3405         status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
3406         if (status)
3407                 goto err;
3408
3409         cfgs = (struct be_fat_conf_params *)
3410                         (extfat_cmd.va + sizeof(struct be_cmd_resp_hdr));
3411         for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) {
3412                 u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes);
3413
3414                 for (j = 0; j < num_modes; j++) {
3415                         if (cfgs->module[i].trace_lvl[j].mode == MODE_UART)
3416                                 cfgs->module[i].trace_lvl[j].dbg_lvl =
3417                                                         cpu_to_le32(level);
3418                 }
3419         }
3420
3421         status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd, cfgs);
3422 err:
3423         dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
3424                           extfat_cmd.dma);
3425         return status;
3426 }
3427
3428 int be_cmd_get_fw_log_level(struct be_adapter *adapter)
3429 {
3430         struct be_dma_mem extfat_cmd;
3431         struct be_fat_conf_params *cfgs;
3432         int status, j;
3433         int level = 0;
3434
3435         memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
3436         extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
3437         extfat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3438                                             extfat_cmd.size, &extfat_cmd.dma,
3439                                             GFP_ATOMIC);
3440
3441         if (!extfat_cmd.va) {
3442                 dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
3443                         __func__);
3444                 goto err;
3445         }
3446
3447         status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
3448         if (!status) {
3449                 cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
3450                                                 sizeof(struct be_cmd_resp_hdr));
3451
3452                 for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) {
3453                         if (cfgs->module[0].trace_lvl[j].mode == MODE_UART)
3454                                 level = cfgs->module[0].trace_lvl[j].dbg_lvl;
3455                 }
3456         }
3457         dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
3458                           extfat_cmd.dma);
3459 err:
3460         return level;
3461 }
3462
3463 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
3464                                    struct be_dma_mem *cmd)
3465 {
3466         struct be_mcc_wrb *wrb;
3467         struct be_cmd_req_get_ext_fat_caps *req;
3468         int status;
3469
3470         if (mutex_lock_interruptible(&adapter->mbox_lock))
3471                 return -1;
3472
3473         wrb = wrb_from_mbox(adapter);
3474         if (!wrb) {
3475                 status = -EBUSY;
3476                 goto err;
3477         }
3478
3479         req = cmd->va;
3480         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3481                                OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
3482                                cmd->size, wrb, cmd);
3483         req->parameter_type = cpu_to_le32(1);
3484
3485         status = be_mbox_notify_wait(adapter);
3486 err:
3487         mutex_unlock(&adapter->mbox_lock);
3488         return status;
3489 }
3490
3491 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
3492                                    struct be_dma_mem *cmd,
3493                                    struct be_fat_conf_params *configs)
3494 {
3495         struct be_mcc_wrb *wrb;
3496         struct be_cmd_req_set_ext_fat_caps *req;
3497         int status;
3498
3499         spin_lock_bh(&adapter->mcc_lock);
3500
3501         wrb = wrb_from_mccq(adapter);
3502         if (!wrb) {
3503                 status = -EBUSY;
3504                 goto err;
3505         }
3506
3507         req = cmd->va;
3508         memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
3509         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3510                                OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
3511                                cmd->size, wrb, cmd);
3512
3513         status = be_mcc_notify_wait(adapter);
3514 err:
3515         spin_unlock_bh(&adapter->mcc_lock);
3516         return status;
3517 }
3518
3519 int be_cmd_query_port_name(struct be_adapter *adapter)
3520 {
3521         struct be_cmd_req_get_port_name *req;
3522         struct be_mcc_wrb *wrb;
3523         int status;
3524
3525         if (mutex_lock_interruptible(&adapter->mbox_lock))
3526                 return -1;
3527
3528         wrb = wrb_from_mbox(adapter);
3529         req = embedded_payload(wrb);
3530
3531         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3532                                OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
3533                                NULL);
3534         if (!BEx_chip(adapter))
3535                 req->hdr.version = 1;
3536
3537         status = be_mbox_notify_wait(adapter);
3538         if (!status) {
3539                 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
3540
3541                 adapter->port_name = resp->port_name[adapter->hba_port_num];
3542         } else {
3543                 adapter->port_name = adapter->hba_port_num + '0';
3544         }
3545
3546         mutex_unlock(&adapter->mbox_lock);
3547         return status;
3548 }
3549
3550 /* Descriptor type */
3551 enum {
3552         FUNC_DESC = 1,
3553         VFT_DESC = 2
3554 };
3555
3556 static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
3557                                                int desc_type)
3558 {
3559         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3560         struct be_nic_res_desc *nic;
3561         int i;
3562
3563         for (i = 0; i < desc_count; i++) {
3564                 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
3565                     hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1) {
3566                         nic = (struct be_nic_res_desc *)hdr;
3567                         if (desc_type == FUNC_DESC ||
3568                             (desc_type == VFT_DESC &&
3569                              nic->flags & (1 << VFT_SHIFT)))
3570                                 return nic;
3571                 }
3572
3573                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3574                 hdr = (void *)hdr + hdr->desc_len;
3575         }
3576         return NULL;
3577 }
3578
3579 static struct be_nic_res_desc *be_get_vft_desc(u8 *buf, u32 desc_count)
3580 {
3581         return be_get_nic_desc(buf, desc_count, VFT_DESC);
3582 }
3583
3584 static struct be_nic_res_desc *be_get_func_nic_desc(u8 *buf, u32 desc_count)
3585 {
3586         return be_get_nic_desc(buf, desc_count, FUNC_DESC);
3587 }
3588
3589 static struct be_pcie_res_desc *be_get_pcie_desc(u8 devfn, u8 *buf,
3590                                                  u32 desc_count)
3591 {
3592         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3593         struct be_pcie_res_desc *pcie;
3594         int i;
3595
3596         for (i = 0; i < desc_count; i++) {
3597                 if ((hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
3598                      hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1)) {
3599                         pcie = (struct be_pcie_res_desc *)hdr;
3600                         if (pcie->pf_num == devfn)
3601                                 return pcie;
3602                 }
3603
3604                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3605                 hdr = (void *)hdr + hdr->desc_len;
3606         }
3607         return NULL;
3608 }
3609
3610 static struct be_port_res_desc *be_get_port_desc(u8 *buf, u32 desc_count)
3611 {
3612         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3613         int i;
3614
3615         for (i = 0; i < desc_count; i++) {
3616                 if (hdr->desc_type == PORT_RESOURCE_DESC_TYPE_V1)
3617                         return (struct be_port_res_desc *)hdr;
3618
3619                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3620                 hdr = (void *)hdr + hdr->desc_len;
3621         }
3622         return NULL;
3623 }
3624
3625 static void be_copy_nic_desc(struct be_resources *res,
3626                              struct be_nic_res_desc *desc)
3627 {
3628         res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count);
3629         res->max_vlans = le16_to_cpu(desc->vlan_count);
3630         res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
3631         res->max_tx_qs = le16_to_cpu(desc->txq_count);
3632         res->max_rss_qs = le16_to_cpu(desc->rssq_count);
3633         res->max_rx_qs = le16_to_cpu(desc->rq_count);
3634         res->max_evt_qs = le16_to_cpu(desc->eq_count);
3635         res->max_cq_count = le16_to_cpu(desc->cq_count);
3636         res->max_iface_count = le16_to_cpu(desc->iface_count);
3637         res->max_mcc_count = le16_to_cpu(desc->mcc_count);
3638         /* Clear flags that driver is not interested in */
3639         res->if_cap_flags = le32_to_cpu(desc->cap_flags) &
3640                                 BE_IF_CAP_FLAGS_WANT;
3641 }
3642
3643 /* Uses Mbox */
3644 int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res)
3645 {
3646         struct be_mcc_wrb *wrb;
3647         struct be_cmd_req_get_func_config *req;
3648         int status;
3649         struct be_dma_mem cmd;
3650
3651         if (mutex_lock_interruptible(&adapter->mbox_lock))
3652                 return -1;
3653
3654         memset(&cmd, 0, sizeof(struct be_dma_mem));
3655         cmd.size = sizeof(struct be_cmd_resp_get_func_config);
3656         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3657                                      GFP_ATOMIC);
3658         if (!cmd.va) {
3659                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3660                 status = -ENOMEM;
3661                 goto err;
3662         }
3663
3664         wrb = wrb_from_mbox(adapter);
3665         if (!wrb) {
3666                 status = -EBUSY;
3667                 goto err;
3668         }
3669
3670         req = cmd.va;
3671
3672         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3673                                OPCODE_COMMON_GET_FUNC_CONFIG,
3674                                cmd.size, wrb, &cmd);
3675
3676         if (skyhawk_chip(adapter))
3677                 req->hdr.version = 1;
3678
3679         status = be_mbox_notify_wait(adapter);
3680         if (!status) {
3681                 struct be_cmd_resp_get_func_config *resp = cmd.va;
3682                 u32 desc_count = le32_to_cpu(resp->desc_count);
3683                 struct be_nic_res_desc *desc;
3684
3685                 desc = be_get_func_nic_desc(resp->func_param, desc_count);
3686                 if (!desc) {
3687                         status = -EINVAL;
3688                         goto err;
3689                 }
3690
3691                 adapter->pf_number = desc->pf_num;
3692                 be_copy_nic_desc(res, desc);
3693         }
3694 err:
3695         mutex_unlock(&adapter->mbox_lock);
3696         if (cmd.va)
3697                 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
3698                                   cmd.dma);
3699         return status;
3700 }
3701
3702 /* Will use MBOX only if MCCQ has not been created */
3703 int be_cmd_get_profile_config(struct be_adapter *adapter,
3704                               struct be_resources *res, u8 query, u8 domain)
3705 {
3706         struct be_cmd_resp_get_profile_config *resp;
3707         struct be_cmd_req_get_profile_config *req;
3708         struct be_nic_res_desc *vf_res;
3709         struct be_pcie_res_desc *pcie;
3710         struct be_port_res_desc *port;
3711         struct be_nic_res_desc *nic;
3712         struct be_mcc_wrb wrb = {0};
3713         struct be_dma_mem cmd;
3714         u16 desc_count;
3715         int status;
3716
3717         memset(&cmd, 0, sizeof(struct be_dma_mem));
3718         cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
3719         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3720                                      GFP_ATOMIC);
3721         if (!cmd.va)
3722                 return -ENOMEM;
3723
3724         req = cmd.va;
3725         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3726                                OPCODE_COMMON_GET_PROFILE_CONFIG,
3727                                cmd.size, &wrb, &cmd);
3728
3729         req->hdr.domain = domain;
3730         if (!lancer_chip(adapter))
3731                 req->hdr.version = 1;
3732         req->type = ACTIVE_PROFILE_TYPE;
3733
3734         /* When QUERY_MODIFIABLE_FIELDS_TYPE bit is set, cmd returns the
3735          * descriptors with all bits set to "1" for the fields which can be
3736          * modified using SET_PROFILE_CONFIG cmd.
3737          */
3738         if (query == RESOURCE_MODIFIABLE)
3739                 req->type |= QUERY_MODIFIABLE_FIELDS_TYPE;
3740
3741         status = be_cmd_notify_wait(adapter, &wrb);
3742         if (status)
3743                 goto err;
3744
3745         resp = cmd.va;
3746         desc_count = le16_to_cpu(resp->desc_count);
3747
3748         pcie = be_get_pcie_desc(adapter->pdev->devfn, resp->func_param,
3749                                 desc_count);
3750         if (pcie)
3751                 res->max_vfs = le16_to_cpu(pcie->num_vfs);
3752
3753         port = be_get_port_desc(resp->func_param, desc_count);
3754         if (port)
3755                 adapter->mc_type = port->mc_type;
3756
3757         nic = be_get_func_nic_desc(resp->func_param, desc_count);
3758         if (nic)
3759                 be_copy_nic_desc(res, nic);
3760
3761         vf_res = be_get_vft_desc(resp->func_param, desc_count);
3762         if (vf_res)
3763                 res->vf_if_cap_flags = vf_res->cap_flags;
3764 err:
3765         if (cmd.va)
3766                 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
3767                                   cmd.dma);
3768         return status;
3769 }
3770
3771 /* Will use MBOX only if MCCQ has not been created */
3772 static int be_cmd_set_profile_config(struct be_adapter *adapter, void *desc,
3773                                      int size, int count, u8 version, u8 domain)
3774 {
3775         struct be_cmd_req_set_profile_config *req;
3776         struct be_mcc_wrb wrb = {0};
3777         struct be_dma_mem cmd;
3778         int status;
3779
3780         memset(&cmd, 0, sizeof(struct be_dma_mem));
3781         cmd.size = sizeof(struct be_cmd_req_set_profile_config);
3782         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3783                                      GFP_ATOMIC);
3784         if (!cmd.va)
3785                 return -ENOMEM;
3786
3787         req = cmd.va;
3788         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3789                                OPCODE_COMMON_SET_PROFILE_CONFIG, cmd.size,
3790                                &wrb, &cmd);
3791         req->hdr.version = version;
3792         req->hdr.domain = domain;
3793         req->desc_count = cpu_to_le32(count);
3794         memcpy(req->desc, desc, size);
3795
3796         status = be_cmd_notify_wait(adapter, &wrb);
3797
3798         if (cmd.va)
3799                 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
3800                                   cmd.dma);
3801         return status;
3802 }
3803
3804 /* Mark all fields invalid */
3805 static void be_reset_nic_desc(struct be_nic_res_desc *nic)
3806 {
3807         memset(nic, 0, sizeof(*nic));
3808         nic->unicast_mac_count = 0xFFFF;
3809         nic->mcc_count = 0xFFFF;
3810         nic->vlan_count = 0xFFFF;
3811         nic->mcast_mac_count = 0xFFFF;
3812         nic->txq_count = 0xFFFF;
3813         nic->rq_count = 0xFFFF;
3814         nic->rssq_count = 0xFFFF;
3815         nic->lro_count = 0xFFFF;
3816         nic->cq_count = 0xFFFF;
3817         nic->toe_conn_count = 0xFFFF;
3818         nic->eq_count = 0xFFFF;
3819         nic->iface_count = 0xFFFF;
3820         nic->link_param = 0xFF;
3821         nic->channel_id_param = cpu_to_le16(0xF000);
3822         nic->acpi_params = 0xFF;
3823         nic->wol_param = 0x0F;
3824         nic->tunnel_iface_count = 0xFFFF;
3825         nic->direct_tenant_iface_count = 0xFFFF;
3826         nic->bw_min = 0xFFFFFFFF;
3827         nic->bw_max = 0xFFFFFFFF;
3828 }
3829
3830 /* Mark all fields invalid */
3831 static void be_reset_pcie_desc(struct be_pcie_res_desc *pcie)
3832 {
3833         memset(pcie, 0, sizeof(*pcie));
3834         pcie->sriov_state = 0xFF;
3835         pcie->pf_state = 0xFF;
3836         pcie->pf_type = 0xFF;
3837         pcie->num_vfs = 0xFFFF;
3838 }
3839
3840 int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, u16 link_speed,
3841                       u8 domain)
3842 {
3843         struct be_nic_res_desc nic_desc;
3844         u32 bw_percent;
3845         u16 version = 0;
3846
3847         if (BE3_chip(adapter))
3848                 return be_cmd_set_qos(adapter, max_rate / 10, domain);
3849
3850         be_reset_nic_desc(&nic_desc);
3851         nic_desc.pf_num = adapter->pf_number;
3852         nic_desc.vf_num = domain;
3853         nic_desc.bw_min = 0;
3854         if (lancer_chip(adapter)) {
3855                 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
3856                 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
3857                 nic_desc.flags = (1 << QUN_SHIFT) | (1 << IMM_SHIFT) |
3858                                         (1 << NOSV_SHIFT);
3859                 nic_desc.bw_max = cpu_to_le32(max_rate / 10);
3860         } else {
3861                 version = 1;
3862                 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
3863                 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3864                 nic_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
3865                 bw_percent = max_rate ? (max_rate * 100) / link_speed : 100;
3866                 nic_desc.bw_max = cpu_to_le32(bw_percent);
3867         }
3868
3869         return be_cmd_set_profile_config(adapter, &nic_desc,
3870                                          nic_desc.hdr.desc_len,
3871                                          1, version, domain);
3872 }
3873
3874 static void be_fill_vf_res_template(struct be_adapter *adapter,
3875                                     struct be_resources pool_res,
3876                                     u16 num_vfs, u16 num_vf_qs,
3877                                     struct be_nic_res_desc *nic_vft)
3878 {
3879         u32 vf_if_cap_flags = pool_res.vf_if_cap_flags;
3880         struct be_resources res_mod = {0};
3881
3882         /* Resource with fields set to all '1's by GET_PROFILE_CONFIG cmd,
3883          * which are modifiable using SET_PROFILE_CONFIG cmd.
3884          */
3885         be_cmd_get_profile_config(adapter, &res_mod, RESOURCE_MODIFIABLE, 0);
3886
3887         /* If RSS IFACE capability flags are modifiable for a VF, set the
3888          * capability flag as valid and set RSS and DEFQ_RSS IFACE flags if
3889          * more than 1 RSSQ is available for a VF.
3890          * Otherwise, provision only 1 queue pair for VF.
3891          */
3892         if (res_mod.vf_if_cap_flags & BE_IF_FLAGS_RSS) {
3893                 nic_vft->flags |= BIT(IF_CAPS_FLAGS_VALID_SHIFT);
3894                 if (num_vf_qs > 1) {
3895                         vf_if_cap_flags |= BE_IF_FLAGS_RSS;
3896                         if (pool_res.if_cap_flags & BE_IF_FLAGS_DEFQ_RSS)
3897                                 vf_if_cap_flags |= BE_IF_FLAGS_DEFQ_RSS;
3898                 } else {
3899                         vf_if_cap_flags &= ~(BE_IF_FLAGS_RSS |
3900                                              BE_IF_FLAGS_DEFQ_RSS);
3901                 }
3902
3903                 nic_vft->cap_flags = cpu_to_le32(vf_if_cap_flags);
3904         } else {
3905                 num_vf_qs = 1;
3906         }
3907
3908         nic_vft->rq_count = cpu_to_le16(num_vf_qs);
3909         nic_vft->txq_count = cpu_to_le16(num_vf_qs);
3910         nic_vft->rssq_count = cpu_to_le16(num_vf_qs);
3911         nic_vft->cq_count = cpu_to_le16(pool_res.max_cq_count /
3912                                         (num_vfs + 1));
3913
3914         /* Distribute unicast MACs, VLANs, IFACE count and MCCQ count equally
3915          * among the PF and it's VFs, if the fields are changeable
3916          */
3917         if (res_mod.max_uc_mac == FIELD_MODIFIABLE)
3918                 nic_vft->unicast_mac_count = cpu_to_le16(pool_res.max_uc_mac /
3919                                                          (num_vfs + 1));
3920
3921         if (res_mod.max_vlans == FIELD_MODIFIABLE)
3922                 nic_vft->vlan_count = cpu_to_le16(pool_res.max_vlans /
3923                                                   (num_vfs + 1));
3924
3925         if (res_mod.max_iface_count == FIELD_MODIFIABLE)
3926                 nic_vft->iface_count = cpu_to_le16(pool_res.max_iface_count /
3927                                                    (num_vfs + 1));
3928
3929         if (res_mod.max_mcc_count == FIELD_MODIFIABLE)
3930                 nic_vft->mcc_count = cpu_to_le16(pool_res.max_mcc_count /
3931                                                  (num_vfs + 1));
3932 }
3933
3934 int be_cmd_set_sriov_config(struct be_adapter *adapter,
3935                             struct be_resources pool_res, u16 num_vfs,
3936                             u16 num_vf_qs)
3937 {
3938         struct {
3939                 struct be_pcie_res_desc pcie;
3940                 struct be_nic_res_desc nic_vft;
3941         } __packed desc;
3942
3943         /* PF PCIE descriptor */
3944         be_reset_pcie_desc(&desc.pcie);
3945         desc.pcie.hdr.desc_type = PCIE_RESOURCE_DESC_TYPE_V1;
3946         desc.pcie.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3947         desc.pcie.flags = BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
3948         desc.pcie.pf_num = adapter->pdev->devfn;
3949         desc.pcie.sriov_state = num_vfs ? 1 : 0;
3950         desc.pcie.num_vfs = cpu_to_le16(num_vfs);
3951
3952         /* VF NIC Template descriptor */
3953         be_reset_nic_desc(&desc.nic_vft);
3954         desc.nic_vft.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
3955         desc.nic_vft.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3956         desc.nic_vft.flags = BIT(VFT_SHIFT) | BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
3957         desc.nic_vft.pf_num = adapter->pdev->devfn;
3958         desc.nic_vft.vf_num = 0;
3959
3960         be_fill_vf_res_template(adapter, pool_res, num_vfs, num_vf_qs,
3961                                 &desc.nic_vft);
3962
3963         return be_cmd_set_profile_config(adapter, &desc,
3964                                          2 * RESOURCE_DESC_SIZE_V1, 2, 1, 0);
3965 }
3966
3967 int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op)
3968 {
3969         struct be_mcc_wrb *wrb;
3970         struct be_cmd_req_manage_iface_filters *req;
3971         int status;
3972
3973         if (iface == 0xFFFFFFFF)
3974                 return -1;
3975
3976         spin_lock_bh(&adapter->mcc_lock);
3977
3978         wrb = wrb_from_mccq(adapter);
3979         if (!wrb) {
3980                 status = -EBUSY;
3981                 goto err;
3982         }
3983         req = embedded_payload(wrb);
3984
3985         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3986                                OPCODE_COMMON_MANAGE_IFACE_FILTERS, sizeof(*req),
3987                                wrb, NULL);
3988         req->op = op;
3989         req->target_iface_id = cpu_to_le32(iface);
3990
3991         status = be_mcc_notify_wait(adapter);
3992 err:
3993         spin_unlock_bh(&adapter->mcc_lock);
3994         return status;
3995 }
3996
3997 int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port)
3998 {
3999         struct be_port_res_desc port_desc;
4000
4001         memset(&port_desc, 0, sizeof(port_desc));
4002         port_desc.hdr.desc_type = PORT_RESOURCE_DESC_TYPE_V1;
4003         port_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4004         port_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
4005         port_desc.link_num = adapter->hba_port_num;
4006         if (port) {
4007                 port_desc.nv_flags = NV_TYPE_VXLAN | (1 << SOCVID_SHIFT) |
4008                                         (1 << RCVID_SHIFT);
4009                 port_desc.nv_port = swab16(port);
4010         } else {
4011                 port_desc.nv_flags = NV_TYPE_DISABLED;
4012                 port_desc.nv_port = 0;
4013         }
4014
4015         return be_cmd_set_profile_config(adapter, &port_desc,
4016                                          RESOURCE_DESC_SIZE_V1, 1, 1, 0);
4017 }
4018
4019 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
4020                      int vf_num)
4021 {
4022         struct be_mcc_wrb *wrb;
4023         struct be_cmd_req_get_iface_list *req;
4024         struct be_cmd_resp_get_iface_list *resp;
4025         int status;
4026
4027         spin_lock_bh(&adapter->mcc_lock);
4028
4029         wrb = wrb_from_mccq(adapter);
4030         if (!wrb) {
4031                 status = -EBUSY;
4032                 goto err;
4033         }
4034         req = embedded_payload(wrb);
4035
4036         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4037                                OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
4038                                wrb, NULL);
4039         req->hdr.domain = vf_num + 1;
4040
4041         status = be_mcc_notify_wait(adapter);
4042         if (!status) {
4043                 resp = (struct be_cmd_resp_get_iface_list *)req;
4044                 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
4045         }
4046
4047 err:
4048         spin_unlock_bh(&adapter->mcc_lock);
4049         return status;
4050 }
4051
4052 static int lancer_wait_idle(struct be_adapter *adapter)
4053 {
4054 #define SLIPORT_IDLE_TIMEOUT 30
4055         u32 reg_val;
4056         int status = 0, i;
4057
4058         for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
4059                 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
4060                 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
4061                         break;
4062
4063                 ssleep(1);
4064         }
4065
4066         if (i == SLIPORT_IDLE_TIMEOUT)
4067                 status = -1;
4068
4069         return status;
4070 }
4071
4072 int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
4073 {
4074         int status = 0;
4075
4076         status = lancer_wait_idle(adapter);
4077         if (status)
4078                 return status;
4079
4080         iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
4081
4082         return status;
4083 }
4084
4085 /* Routine to check whether dump image is present or not */
4086 bool dump_present(struct be_adapter *adapter)
4087 {
4088         u32 sliport_status = 0;
4089
4090         sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
4091         return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
4092 }
4093
4094 int lancer_initiate_dump(struct be_adapter *adapter)
4095 {
4096         struct device *dev = &adapter->pdev->dev;
4097         int status;
4098
4099         if (dump_present(adapter)) {
4100                 dev_info(dev, "Previous dump not cleared, not forcing dump\n");
4101                 return -EEXIST;
4102         }
4103
4104         /* give firmware reset and diagnostic dump */
4105         status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
4106                                      PHYSDEV_CONTROL_DD_MASK);
4107         if (status < 0) {
4108                 dev_err(dev, "FW reset failed\n");
4109                 return status;
4110         }
4111
4112         status = lancer_wait_idle(adapter);
4113         if (status)
4114                 return status;
4115
4116         if (!dump_present(adapter)) {
4117                 dev_err(dev, "FW dump not generated\n");
4118                 return -EIO;
4119         }
4120
4121         return 0;
4122 }
4123
4124 int lancer_delete_dump(struct be_adapter *adapter)
4125 {
4126         int status;
4127
4128         status = lancer_cmd_delete_object(adapter, LANCER_FW_DUMP_FILE);
4129         return be_cmd_status(status);
4130 }
4131
4132 /* Uses sync mcc */
4133 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
4134 {
4135         struct be_mcc_wrb *wrb;
4136         struct be_cmd_enable_disable_vf *req;
4137         int status;
4138
4139         if (BEx_chip(adapter))
4140                 return 0;
4141
4142         spin_lock_bh(&adapter->mcc_lock);
4143
4144         wrb = wrb_from_mccq(adapter);
4145         if (!wrb) {
4146                 status = -EBUSY;
4147                 goto err;
4148         }
4149
4150         req = embedded_payload(wrb);
4151
4152         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4153                                OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
4154                                wrb, NULL);
4155
4156         req->hdr.domain = domain;
4157         req->enable = 1;
4158         status = be_mcc_notify_wait(adapter);
4159 err:
4160         spin_unlock_bh(&adapter->mcc_lock);
4161         return status;
4162 }
4163
4164 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
4165 {
4166         struct be_mcc_wrb *wrb;
4167         struct be_cmd_req_intr_set *req;
4168         int status;
4169
4170         if (mutex_lock_interruptible(&adapter->mbox_lock))
4171                 return -1;
4172
4173         wrb = wrb_from_mbox(adapter);
4174
4175         req = embedded_payload(wrb);
4176
4177         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4178                                OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
4179                                wrb, NULL);
4180
4181         req->intr_enabled = intr_enable;
4182
4183         status = be_mbox_notify_wait(adapter);
4184
4185         mutex_unlock(&adapter->mbox_lock);
4186         return status;
4187 }
4188
4189 /* Uses MBOX */
4190 int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile_id)
4191 {
4192         struct be_cmd_req_get_active_profile *req;
4193         struct be_mcc_wrb *wrb;
4194         int status;
4195
4196         if (mutex_lock_interruptible(&adapter->mbox_lock))
4197                 return -1;
4198
4199         wrb = wrb_from_mbox(adapter);
4200         if (!wrb) {
4201                 status = -EBUSY;
4202                 goto err;
4203         }
4204
4205         req = embedded_payload(wrb);
4206
4207         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4208                                OPCODE_COMMON_GET_ACTIVE_PROFILE, sizeof(*req),
4209                                wrb, NULL);
4210
4211         status = be_mbox_notify_wait(adapter);
4212         if (!status) {
4213                 struct be_cmd_resp_get_active_profile *resp =
4214                                                         embedded_payload(wrb);
4215
4216                 *profile_id = le16_to_cpu(resp->active_profile_id);
4217         }
4218
4219 err:
4220         mutex_unlock(&adapter->mbox_lock);
4221         return status;
4222 }
4223
4224 int be_cmd_set_logical_link_config(struct be_adapter *adapter,
4225                                    int link_state, u8 domain)
4226 {
4227         struct be_mcc_wrb *wrb;
4228         struct be_cmd_req_set_ll_link *req;
4229         int status;
4230
4231         if (BEx_chip(adapter) || lancer_chip(adapter))
4232                 return -EOPNOTSUPP;
4233
4234         spin_lock_bh(&adapter->mcc_lock);
4235
4236         wrb = wrb_from_mccq(adapter);
4237         if (!wrb) {
4238                 status = -EBUSY;
4239                 goto err;
4240         }
4241
4242         req = embedded_payload(wrb);
4243
4244         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4245                                OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG,
4246                                sizeof(*req), wrb, NULL);
4247
4248         req->hdr.version = 1;
4249         req->hdr.domain = domain;
4250
4251         if (link_state == IFLA_VF_LINK_STATE_ENABLE)
4252                 req->link_config |= 1;
4253
4254         if (link_state == IFLA_VF_LINK_STATE_AUTO)
4255                 req->link_config |= 1 << PLINK_TRACK_SHIFT;
4256
4257         status = be_mcc_notify_wait(adapter);
4258 err:
4259         spin_unlock_bh(&adapter->mcc_lock);
4260         return status;
4261 }
4262
4263 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
4264                     int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
4265 {
4266         struct be_adapter *adapter = netdev_priv(netdev_handle);
4267         struct be_mcc_wrb *wrb;
4268         struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *)wrb_payload;
4269         struct be_cmd_req_hdr *req;
4270         struct be_cmd_resp_hdr *resp;
4271         int status;
4272
4273         spin_lock_bh(&adapter->mcc_lock);
4274
4275         wrb = wrb_from_mccq(adapter);
4276         if (!wrb) {
4277                 status = -EBUSY;
4278                 goto err;
4279         }
4280         req = embedded_payload(wrb);
4281         resp = embedded_payload(wrb);
4282
4283         be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
4284                                hdr->opcode, wrb_payload_size, wrb, NULL);
4285         memcpy(req, wrb_payload, wrb_payload_size);
4286         be_dws_cpu_to_le(req, wrb_payload_size);
4287
4288         status = be_mcc_notify_wait(adapter);
4289         if (cmd_status)
4290                 *cmd_status = (status & 0xffff);
4291         if (ext_status)
4292                 *ext_status = 0;
4293         memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
4294         be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
4295 err:
4296         spin_unlock_bh(&adapter->mcc_lock);
4297         return status;
4298 }
4299 EXPORT_SYMBOL(be_roce_mcc_cmd);