drivers/net/ethernet/emulex/benet/be_cmds.c

   1 /*
   2  * Copyright (C) 2005 - 2013 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 #include <linux/module.h>
  19 #include "be.h"
  20 #include "be_cmds.h"
  21
  22 static struct be_cmd_priv_map cmd_priv_map[] = {
  23         {
  24                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
  25                 CMD_SUBSYSTEM_ETH,
  26                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  27                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  28         },
  29         {
  30                 OPCODE_COMMON_GET_FLOW_CONTROL,
  31                 CMD_SUBSYSTEM_COMMON,
  32                 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
  33                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  34         },
  35         {
  36                 OPCODE_COMMON_SET_FLOW_CONTROL,
  37                 CMD_SUBSYSTEM_COMMON,
  38                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  39                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  40         },
  41         {
  42                 OPCODE_ETH_GET_PPORT_STATS,
  43                 CMD_SUBSYSTEM_ETH,
  44                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  45                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  46         },
  47         {
  48                 OPCODE_COMMON_GET_PHY_DETAILS,
  49                 CMD_SUBSYSTEM_COMMON,
  50                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  51                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  52         }
  53 };
  54
  55 static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode,
  56                            u8 subsystem)
  57 {
  58         int i;
  59         int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
  60         u32 cmd_privileges = adapter->cmd_privileges;
  61
  62         for (i = 0; i < num_entries; i++)
  63                 if (opcode == cmd_priv_map[i].opcode &&
  64                     subsystem == cmd_priv_map[i].subsystem)
  65                         if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
  66                                 return false;
  67
  68         return true;
  69 }
  70
  71 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
  72 {
  73         return wrb->payload.embedded_payload;
  74 }
  75
  76 static void be_mcc_notify(struct be_adapter *adapter)
  77 {
  78         struct be_queue_info *mccq = &adapter->mcc_obj.q;
  79         u32 val = 0;
  80
  81         if (be_error(adapter))
  82                 return;
  83
  84         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
  85         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
  86
  87         wmb();
  88         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
  89 }
  90
  91 /* To check if valid bit is set, check the entire word as we don't know
  92  * the endianness of the data (old entry is host endian while a new entry is
  93  * little endian) */
  94 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
  95 {
  96         u32 flags;
  97
  98         if (compl->flags != 0) {
  99                 flags = le32_to_cpu(compl->flags);
 100                 if (flags & CQE_FLAGS_VALID_MASK) {
 101                         compl->flags = flags;
 102                         return true;
 103                 }
 104         }
 105         return false;
 106 }
 107
 108 /* Need to reset the entire word that houses the valid bit */
 109 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
 110 {
 111         compl->flags = 0;
 112 }
 113
 114 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
 115 {
 116         unsigned long addr;
 117
 118         addr = tag1;
 119         addr = ((addr << 16) << 16) | tag0;
 120         return (void *)addr;
 121 }
 122
 123 static int be_mcc_compl_process(struct be_adapter *adapter,
 124                                 struct be_mcc_compl *compl)
 125 {
 126         u16 compl_status, extd_status;
 127         struct be_cmd_resp_hdr *resp_hdr;
 128         u8 opcode = 0, subsystem = 0;
 129
 130         /* Just swap the status to host endian; mcc tag is opaquely copied
 131          * from mcc_wrb */
 132         be_dws_le_to_cpu(compl, 4);
 133
 134         compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
 135                                 CQE_STATUS_COMPL_MASK;
 136
 137         resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
 138
 139         if (resp_hdr) {
 140                 opcode = resp_hdr->opcode;
 141                 subsystem = resp_hdr->subsystem;
 142         }
 143
 144         if (((opcode == OPCODE_COMMON_WRITE_FLASHROM) ||
 145              (opcode == OPCODE_COMMON_WRITE_OBJECT)) &&
 146             (subsystem == CMD_SUBSYSTEM_COMMON)) {
 147                 adapter->flash_status = compl_status;
 148                 complete(&adapter->flash_compl);
 149         }
 150
 151         if (compl_status == MCC_STATUS_SUCCESS) {
 152                 if (((opcode == OPCODE_ETH_GET_STATISTICS) ||
 153                      (opcode == OPCODE_ETH_GET_PPORT_STATS)) &&
 154                     (subsystem == CMD_SUBSYSTEM_ETH)) {
 155                         be_parse_stats(adapter);
 156                         adapter->stats_cmd_sent = false;
 157                 }
 158                 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
 159                     subsystem == CMD_SUBSYSTEM_COMMON) {
 160                         struct be_cmd_resp_get_cntl_addnl_attribs *resp =
 161                                 (void *)resp_hdr;
 162                         adapter->drv_stats.be_on_die_temperature =
 163                                 resp->on_die_temperature;
 164                 }
 165         } else {
 166                 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES)
 167                         adapter->be_get_temp_freq = 0;
 168
 169                 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
 170                         compl_status == MCC_STATUS_ILLEGAL_REQUEST)
 171                         goto done;
 172
 173                 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
 174                         dev_warn(&adapter->pdev->dev,
 175                                  "VF is not privileged to issue opcode %d-%d\n",
 176                                  opcode, subsystem);
 177                 } else {
 178                         extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
 179                                         CQE_STATUS_EXTD_MASK;
 180                         dev_err(&adapter->pdev->dev,
 181                                 "opcode %d-%d failed:status %d-%d\n",
 182                                 opcode, subsystem, compl_status, extd_status);
 183
 184                         if (extd_status == MCC_ADDL_STS_INSUFFICIENT_RESOURCES)
 185                                 return extd_status;
 186                 }
 187         }
 188 done:
 189         return compl_status;
 190 }
 191
 192 /* Link state evt is a string of bytes; no need for endian swapping */
 193 static void be_async_link_state_process(struct be_adapter *adapter,
 194                 struct be_async_event_link_state *evt)
 195 {
 196         /* When link status changes, link speed must be re-queried from FW */
 197         adapter->phy.link_speed = -1;
 198
 199         /* Ignore physical link event */
 200         if (lancer_chip(adapter) &&
 201             !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
 202                 return;
 203
 204         /* For the initial link status do not rely on the ASYNC event as
 205          * it may not be received in some cases.
 206          */
 207         if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
 208                 be_link_status_update(adapter, evt->port_link_status);
 209 }
 210
 211 /* Grp5 CoS Priority evt */
 212 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
 213                 struct be_async_event_grp5_cos_priority *evt)
 214 {
 215         if (evt->valid) {
 216                 adapter->vlan_prio_bmap = evt->available_priority_bmap;
 217                 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
 218                 adapter->recommended_prio =
 219                         evt->reco_default_priority << VLAN_PRIO_SHIFT;
 220         }
 221 }
 222
 223 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
 224 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
 225                 struct be_async_event_grp5_qos_link_speed *evt)
 226 {
 227         if (adapter->phy.link_speed >= 0 &&
 228             evt->physical_port == adapter->port_num)
 229                 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
 230 }
 231
 232 /*Grp5 PVID evt*/
 233 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
 234                 struct be_async_event_grp5_pvid_state *evt)
 235 {
 236         if (evt->enabled)
 237                 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
 238         else
 239                 adapter->pvid = 0;
 240 }
 241
 242 static void be_async_grp5_evt_process(struct be_adapter *adapter,
 243                 u32 trailer, struct be_mcc_compl *evt)
 244 {
 245         u8 event_type = 0;
 246
 247         event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
 248                 ASYNC_TRAILER_EVENT_TYPE_MASK;
 249
 250         switch (event_type) {
 251         case ASYNC_EVENT_COS_PRIORITY:
 252                 be_async_grp5_cos_priority_process(adapter,
 253                 (struct be_async_event_grp5_cos_priority *)evt);
 254         break;
 255         case ASYNC_EVENT_QOS_SPEED:
 256                 be_async_grp5_qos_speed_process(adapter,
 257                 (struct be_async_event_grp5_qos_link_speed *)evt);
 258         break;
 259         case ASYNC_EVENT_PVID_STATE:
 260                 be_async_grp5_pvid_state_process(adapter,
 261                 (struct be_async_event_grp5_pvid_state *)evt);
 262         break;
 263         default:
 264                 dev_warn(&adapter->pdev->dev, "Unknown grp5 event 0x%x!\n",
 265                          event_type);
 266                 break;
 267         }
 268 }
 269
 270 static void be_async_dbg_evt_process(struct be_adapter *adapter,
 271                 u32 trailer, struct be_mcc_compl *cmp)
 272 {
 273         u8 event_type = 0;
 274         struct be_async_event_qnq *evt = (struct be_async_event_qnq *) cmp;
 275
 276         event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
 277                 ASYNC_TRAILER_EVENT_TYPE_MASK;
 278
 279         switch (event_type) {
 280         case ASYNC_DEBUG_EVENT_TYPE_QNQ:
 281                 if (evt->valid)
 282                         adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
 283                 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
 284         break;
 285         default:
 286                 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
 287                          event_type);
 288         break;
 289         }
 290 }
 291
 292 static inline bool is_link_state_evt(u32 trailer)
 293 {
 294         return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 295                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 296                                 ASYNC_EVENT_CODE_LINK_STATE;
 297 }
 298
 299 static inline bool is_grp5_evt(u32 trailer)
 300 {
 301         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 302                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 303                                 ASYNC_EVENT_CODE_GRP_5);
 304 }
 305
 306 static inline bool is_dbg_evt(u32 trailer)
 307 {
 308         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 309                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 310                                 ASYNC_EVENT_CODE_QNQ);
 311 }
 312
 313 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
 314 {
 315         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
 316         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
 317
 318         if (be_mcc_compl_is_new(compl)) {
 319                 queue_tail_inc(mcc_cq);
 320                 return compl;
 321         }
 322         return NULL;
 323 }
 324
 325 void be_async_mcc_enable(struct be_adapter *adapter)
 326 {
 327         spin_lock_bh(&adapter->mcc_cq_lock);
 328
 329         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
 330         adapter->mcc_obj.rearm_cq = true;
 331
 332         spin_unlock_bh(&adapter->mcc_cq_lock);
 333 }
 334
 335 void be_async_mcc_disable(struct be_adapter *adapter)
 336 {
 337         spin_lock_bh(&adapter->mcc_cq_lock);
 338
 339         adapter->mcc_obj.rearm_cq = false;
 340         be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
 341
 342         spin_unlock_bh(&adapter->mcc_cq_lock);
 343 }
 344
 345 int be_process_mcc(struct be_adapter *adapter)
 346 {
 347         struct be_mcc_compl *compl;
 348         int num = 0, status = 0;
 349         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 350
 351         spin_lock(&adapter->mcc_cq_lock);
 352         while ((compl = be_mcc_compl_get(adapter))) {
 353                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 354                         /* Interpret flags as an async trailer */
 355                         if (is_link_state_evt(compl->flags))
 356                                 be_async_link_state_process(adapter,
 357                                 (struct be_async_event_link_state *) compl);
 358                         else if (is_grp5_evt(compl->flags))
 359                                 be_async_grp5_evt_process(adapter,
 360                                 compl->flags, compl);
 361                         else if (is_dbg_evt(compl->flags))
 362                                 be_async_dbg_evt_process(adapter,
 363                                 compl->flags, compl);
 364                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
 365                                 status = be_mcc_compl_process(adapter, compl);
 366                                 atomic_dec(&mcc_obj->q.used);
 367                 }
 368                 be_mcc_compl_use(compl);
 369                 num++;
 370         }
 371
 372         if (num)
 373                 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
 374
 375         spin_unlock(&adapter->mcc_cq_lock);
 376         return status;
 377 }
 378
 379 /* Wait till no more pending mcc requests are present */
 380 static int be_mcc_wait_compl(struct be_adapter *adapter)
 381 {
 382 #define mcc_timeout             120000 /* 12s timeout */
 383         int i, status = 0;
 384         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 385
 386         for (i = 0; i < mcc_timeout; i++) {
 387                 if (be_error(adapter))
 388                         return -EIO;
 389
 390                 local_bh_disable();
 391                 status = be_process_mcc(adapter);
 392                 local_bh_enable();
 393
 394                 if (atomic_read(&mcc_obj->q.used) == 0)
 395                         break;
 396                 udelay(100);
 397         }
 398         if (i == mcc_timeout) {
 399                 dev_err(&adapter->pdev->dev, "FW not responding\n");
 400                 adapter->fw_timeout = true;
 401                 return -EIO;
 402         }
 403         return status;
 404 }
 405
 406 /* Notify MCC requests and wait for completion */
 407 static int be_mcc_notify_wait(struct be_adapter *adapter)
 408 {
 409         int status;
 410         struct be_mcc_wrb *wrb;
 411         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 412         u16 index = mcc_obj->q.head;
 413         struct be_cmd_resp_hdr *resp;
 414
 415         index_dec(&index, mcc_obj->q.len);
 416         wrb = queue_index_node(&mcc_obj->q, index);
 417
 418         resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
 419
 420         be_mcc_notify(adapter);
 421
 422         status = be_mcc_wait_compl(adapter);
 423         if (status == -EIO)
 424                 goto out;
 425
 426         status = resp->status;
 427 out:
 428         return status;
 429 }
 430
 431 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 432 {
 433         int msecs = 0;
 434         u32 ready;
 435
 436         do {
 437                 if (be_error(adapter))
 438                         return -EIO;
 439
 440                 ready = ioread32(db);
 441                 if (ready == 0xffffffff)
 442                         return -1;
 443
 444                 ready &= MPU_MAILBOX_DB_RDY_MASK;
 445                 if (ready)
 446                         break;
 447
 448                 if (msecs > 4000) {
 449                         dev_err(&adapter->pdev->dev, "FW not responding\n");
 450                         adapter->fw_timeout = true;
 451                         be_detect_error(adapter);
 452                         return -1;
 453                 }
 454
 455                 msleep(1);
 456                 msecs++;
 457         } while (true);
 458
 459         return 0;
 460 }
 461
 462 /*
 463  * Insert the mailbox address into the doorbell in two steps
 464  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 465  */
 466 static int be_mbox_notify_wait(struct be_adapter *adapter)
 467 {
 468         int status;
 469         u32 val = 0;
 470         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 471         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 472         struct be_mcc_mailbox *mbox = mbox_mem->va;
 473         struct be_mcc_compl *compl = &mbox->compl;
 474
 475         /* wait for ready to be set */
 476         status = be_mbox_db_ready_wait(adapter, db);
 477         if (status != 0)
 478                 return status;
 479
 480         val |= MPU_MAILBOX_DB_HI_MASK;
 481         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 482         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 483         iowrite32(val, db);
 484
 485         /* wait for ready to be set */
 486         status = be_mbox_db_ready_wait(adapter, db);
 487         if (status != 0)
 488                 return status;
 489
 490         val = 0;
 491         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 492         val |= (u32)(mbox_mem->dma >> 4) << 2;
 493         iowrite32(val, db);
 494
 495         status = be_mbox_db_ready_wait(adapter, db);
 496         if (status != 0)
 497                 return status;
 498
 499         /* A cq entry has been made now */
 500         if (be_mcc_compl_is_new(compl)) {
 501                 status = be_mcc_compl_process(adapter, &mbox->compl);
 502                 be_mcc_compl_use(compl);
 503                 if (status)
 504                         return status;
 505         } else {
 506                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 507                 return -1;
 508         }
 509         return 0;
 510 }
 511
 512 static u16 be_POST_stage_get(struct be_adapter *adapter)
 513 {
 514         u32 sem;
 515
 516         if (BEx_chip(adapter))
 517                 sem  = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
 518         else
 519                 pci_read_config_dword(adapter->pdev,
 520                                       SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
 521
 522         return sem & POST_STAGE_MASK;
 523 }
 524
 525 int lancer_wait_ready(struct be_adapter *adapter)
 526 {
 527 #define SLIPORT_READY_TIMEOUT 30
 528         u32 sliport_status;
 529         int status = 0, i;
 530
 531         for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
 532                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 533                 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
 534                         break;
 535
 536                 msleep(1000);
 537         }
 538
 539         if (i == SLIPORT_READY_TIMEOUT)
 540                 status = -1;
 541
 542         return status;
 543 }
 544
 545 static bool lancer_provisioning_error(struct be_adapter *adapter)
 546 {
 547         u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0;
 548         sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 549         if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
 550                 sliport_err1 = ioread32(adapter->db +
 551                                         SLIPORT_ERROR1_OFFSET);
 552                 sliport_err2 = ioread32(adapter->db +
 553                                         SLIPORT_ERROR2_OFFSET);
 554
 555                 if (sliport_err1 == SLIPORT_ERROR_NO_RESOURCE1 &&
 556                     sliport_err2 == SLIPORT_ERROR_NO_RESOURCE2)
 557                         return true;
 558         }
 559         return false;
 560 }
 561
 562 int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
 563 {
 564         int status;
 565         u32 sliport_status, err, reset_needed;
 566         bool resource_error;
 567
 568         resource_error = lancer_provisioning_error(adapter);
 569         if (resource_error)
 570                 return -EAGAIN;
 571
 572         status = lancer_wait_ready(adapter);
 573         if (!status) {
 574                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 575                 err = sliport_status & SLIPORT_STATUS_ERR_MASK;
 576                 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK;
 577                 if (err && reset_needed) {
 578                         iowrite32(SLI_PORT_CONTROL_IP_MASK,
 579                                   adapter->db + SLIPORT_CONTROL_OFFSET);
 580
 581                         /* check adapter has corrected the error */
 582                         status = lancer_wait_ready(adapter);
 583                         sliport_status = ioread32(adapter->db +
 584                                                   SLIPORT_STATUS_OFFSET);
 585                         sliport_status &= (SLIPORT_STATUS_ERR_MASK |
 586                                                 SLIPORT_STATUS_RN_MASK);
 587                         if (status || sliport_status)
 588                                 status = -1;
 589                 } else if (err || reset_needed) {
 590                         status = -1;
 591                 }
 592         }
 593         /* Stop error recovery if error is not recoverable.
 594          * No resource error is temporary errors and will go away
 595          * when PF provisions resources.
 596          */
 597         resource_error = lancer_provisioning_error(adapter);
 598         if (resource_error)
 599                 status = -EAGAIN;
 600
 601         return status;
 602 }
 603
 604 int be_fw_wait_ready(struct be_adapter *adapter)
 605 {
 606         u16 stage;
 607         int status, timeout = 0;
 608         struct device *dev = &adapter->pdev->dev;
 609
 610         if (lancer_chip(adapter)) {
 611                 status = lancer_wait_ready(adapter);
 612                 return status;
 613         }
 614
 615         do {
 616                 stage = be_POST_stage_get(adapter);
 617                 if (stage == POST_STAGE_ARMFW_RDY)
 618                         return 0;
 619
 620                 dev_info(dev, "Waiting for POST, %ds elapsed\n",
 621                          timeout);
 622                 if (msleep_interruptible(2000)) {
 623                         dev_err(dev, "Waiting for POST aborted\n");
 624                         return -EINTR;
 625                 }
 626                 timeout += 2;
 627         } while (timeout < 60);
 628
 629         dev_err(dev, "POST timeout; stage=0x%x\n", stage);
 630         return -1;
 631 }
 632
 633
 634 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 635 {
 636         return &wrb->payload.sgl[0];
 637 }
 638
 639 static inline void fill_wrb_tags(struct be_mcc_wrb *wrb,
 640                                  unsigned long addr)
 641 {
 642         wrb->tag0 = addr & 0xFFFFFFFF;
 643         wrb->tag1 = upper_32_bits(addr);
 644 }
 645
 646 /* Don't touch the hdr after it's prepared */
 647 /* mem will be NULL for embedded commands */
 648 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 649                                 u8 subsystem, u8 opcode, int cmd_len,
 650                                 struct be_mcc_wrb *wrb, struct be_dma_mem *mem)
 651 {
 652         struct be_sge *sge;
 653
 654         req_hdr->opcode = opcode;
 655         req_hdr->subsystem = subsystem;
 656         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 657         req_hdr->version = 0;
 658         fill_wrb_tags(wrb, (ulong) req_hdr);
 659         wrb->payload_length = cmd_len;
 660         if (mem) {
 661                 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
 662                         MCC_WRB_SGE_CNT_SHIFT;
 663                 sge = nonembedded_sgl(wrb);
 664                 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
 665                 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
 666                 sge->len = cpu_to_le32(mem->size);
 667         } else
 668                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 669         be_dws_cpu_to_le(wrb, 8);
 670 }
 671
 672 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 673                         struct be_dma_mem *mem)
 674 {
 675         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 676         u64 dma = (u64)mem->dma;
 677
 678         for (i = 0; i < buf_pages; i++) {
 679                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 680                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 681                 dma += PAGE_SIZE_4K;
 682         }
 683 }
 684
 685 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
 686 {
 687         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 688         struct be_mcc_wrb *wrb
 689                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 690         memset(wrb, 0, sizeof(*wrb));
 691         return wrb;
 692 }
 693
 694 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
 695 {
 696         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 697         struct be_mcc_wrb *wrb;
 698
 699         if (!mccq->created)
 700                 return NULL;
 701
 702         if (atomic_read(&mccq->used) >= mccq->len)
 703                 return NULL;
 704
 705         wrb = queue_head_node(mccq);
 706         queue_head_inc(mccq);
 707         atomic_inc(&mccq->used);
 708         memset(wrb, 0, sizeof(*wrb));
 709         return wrb;
 710 }
 711
 712 static bool use_mcc(struct be_adapter *adapter)
 713 {
 714         return adapter->mcc_obj.q.created;
 715 }
 716
 717 /* Must be used only in process context */
 718 static int be_cmd_lock(struct be_adapter *adapter)
 719 {
 720         if (use_mcc(adapter)) {
 721                 spin_lock_bh(&adapter->mcc_lock);
 722                 return 0;
 723         } else {
 724                 return mutex_lock_interruptible(&adapter->mbox_lock);
 725         }
 726 }
 727
 728 /* Must be used only in process context */
 729 static void be_cmd_unlock(struct be_adapter *adapter)
 730 {
 731         if (use_mcc(adapter))
 732                 spin_unlock_bh(&adapter->mcc_lock);
 733         else
 734                 return mutex_unlock(&adapter->mbox_lock);
 735 }
 736
 737 static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter,
 738                                       struct be_mcc_wrb *wrb)
 739 {
 740         struct be_mcc_wrb *dest_wrb;
 741
 742         if (use_mcc(adapter)) {
 743                 dest_wrb = wrb_from_mccq(adapter);
 744                 if (!dest_wrb)
 745                         return NULL;
 746         } else {
 747                 dest_wrb = wrb_from_mbox(adapter);
 748         }
 749
 750         memcpy(dest_wrb, wrb, sizeof(*wrb));
 751         if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK))
 752                 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb));
 753
 754         return dest_wrb;
 755 }
 756
 757 /* Must be used only in process context */
 758 static int be_cmd_notify_wait(struct be_adapter *adapter,
 759                               struct be_mcc_wrb *wrb)
 760 {
 761         struct be_mcc_wrb *dest_wrb;
 762         int status;
 763
 764         status = be_cmd_lock(adapter);
 765         if (status)
 766                 return status;
 767
 768         dest_wrb = be_cmd_copy(adapter, wrb);
 769         if (!dest_wrb)
 770                 return -EBUSY;
 771
 772         if (use_mcc(adapter))
 773                 status = be_mcc_notify_wait(adapter);
 774         else
 775                 status = be_mbox_notify_wait(adapter);
 776
 777         if (!status)
 778                 memcpy(wrb, dest_wrb, sizeof(*wrb));
 779
 780         be_cmd_unlock(adapter);
 781         return status;
 782 }
 783
 784 /* Tell fw we're about to start firing cmds by writing a
 785  * special pattern across the wrb hdr; uses mbox
 786  */
 787 int be_cmd_fw_init(struct be_adapter *adapter)
 788 {
 789         u8 *wrb;
 790         int status;
 791
 792         if (lancer_chip(adapter))
 793                 return 0;
 794
 795         if (mutex_lock_interruptible(&adapter->mbox_lock))
 796                 return -1;
 797
 798         wrb = (u8 *)wrb_from_mbox(adapter);
 799         *wrb++ = 0xFF;
 800         *wrb++ = 0x12;
 801         *wrb++ = 0x34;
 802         *wrb++ = 0xFF;
 803         *wrb++ = 0xFF;
 804         *wrb++ = 0x56;
 805         *wrb++ = 0x78;
 806         *wrb = 0xFF;
 807
 808         status = be_mbox_notify_wait(adapter);
 809
 810         mutex_unlock(&adapter->mbox_lock);
 811         return status;
 812 }
 813
 814 /* Tell fw we're done with firing cmds by writing a
 815  * special pattern across the wrb hdr; uses mbox
 816  */
 817 int be_cmd_fw_clean(struct be_adapter *adapter)
 818 {
 819         u8 *wrb;
 820         int status;
 821
 822         if (lancer_chip(adapter))
 823                 return 0;
 824
 825         if (mutex_lock_interruptible(&adapter->mbox_lock))
 826                 return -1;
 827
 828         wrb = (u8 *)wrb_from_mbox(adapter);
 829         *wrb++ = 0xFF;
 830         *wrb++ = 0xAA;
 831         *wrb++ = 0xBB;
 832         *wrb++ = 0xFF;
 833         *wrb++ = 0xFF;
 834         *wrb++ = 0xCC;
 835         *wrb++ = 0xDD;
 836         *wrb = 0xFF;
 837
 838         status = be_mbox_notify_wait(adapter);
 839
 840         mutex_unlock(&adapter->mbox_lock);
 841         return status;
 842 }
 843
 844 int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
 845 {
 846         struct be_mcc_wrb *wrb;
 847         struct be_cmd_req_eq_create *req;
 848         struct be_dma_mem *q_mem = &eqo->q.dma_mem;
 849         int status, ver = 0;
 850
 851         if (mutex_lock_interruptible(&adapter->mbox_lock))
 852                 return -1;
 853
 854         wrb = wrb_from_mbox(adapter);
 855         req = embedded_payload(wrb);
 856
 857         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 858                 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL);
 859
 860         /* Support for EQ_CREATEv2 available only SH-R onwards */
 861         if (!(BEx_chip(adapter) || lancer_chip(adapter)))
 862                 ver = 2;
 863
 864         req->hdr.version = ver;
 865         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 866
 867         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
 868         /* 4byte eqe*/
 869         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
 870         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
 871                       __ilog2_u32(eqo->q.len / 256));
 872         be_dws_cpu_to_le(req->context, sizeof(req->context));
 873
 874         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 875
 876         status = be_mbox_notify_wait(adapter);
 877         if (!status) {
 878                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
 879                 eqo->q.id = le16_to_cpu(resp->eq_id);
 880                 eqo->msix_idx =
 881                         (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx;
 882                 eqo->q.created = true;
 883         }
 884
 885         mutex_unlock(&adapter->mbox_lock);
 886         return status;
 887 }
 888
 889 /* Use MCC */
 890 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 891                           bool permanent, u32 if_handle, u32 pmac_id)
 892 {
 893         struct be_mcc_wrb *wrb;
 894         struct be_cmd_req_mac_query *req;
 895         int status;
 896
 897         spin_lock_bh(&adapter->mcc_lock);
 898
 899         wrb = wrb_from_mccq(adapter);
 900         if (!wrb) {
 901                 status = -EBUSY;
 902                 goto err;
 903         }
 904         req = embedded_payload(wrb);
 905
 906         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 907                 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL);
 908         req->type = MAC_ADDRESS_TYPE_NETWORK;
 909         if (permanent) {
 910                 req->permanent = 1;
 911         } else {
 912                 req->if_id = cpu_to_le16((u16) if_handle);
 913                 req->pmac_id = cpu_to_le32(pmac_id);
 914                 req->permanent = 0;
 915         }
 916
 917         status = be_mcc_notify_wait(adapter);
 918         if (!status) {
 919                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
 920                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
 921         }
 922
 923 err:
 924         spin_unlock_bh(&adapter->mcc_lock);
 925         return status;
 926 }
 927
 928 /* Uses synchronous MCCQ */
 929 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
 930                 u32 if_id, u32 *pmac_id, u32 domain)
 931 {
 932         struct be_mcc_wrb *wrb;
 933         struct be_cmd_req_pmac_add *req;
 934         int status;
 935
 936         spin_lock_bh(&adapter->mcc_lock);
 937
 938         wrb = wrb_from_mccq(adapter);
 939         if (!wrb) {
 940                 status = -EBUSY;
 941                 goto err;
 942         }
 943         req = embedded_payload(wrb);
 944
 945         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 946                 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL);
 947
 948         req->hdr.domain = domain;
 949         req->if_id = cpu_to_le32(if_id);
 950         memcpy(req->mac_address, mac_addr, ETH_ALEN);
 951
 952         status = be_mcc_notify_wait(adapter);
 953         if (!status) {
 954                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
 955                 *pmac_id = le32_to_cpu(resp->pmac_id);
 956         }
 957
 958 err:
 959         spin_unlock_bh(&adapter->mcc_lock);
 960
 961          if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
 962                 status = -EPERM;
 963
 964         return status;
 965 }
 966
 967 /* Uses synchronous MCCQ */
 968 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
 969 {
 970         struct be_mcc_wrb *wrb;
 971         struct be_cmd_req_pmac_del *req;
 972         int status;
 973
 974         if (pmac_id == -1)
 975                 return 0;
 976
 977         spin_lock_bh(&adapter->mcc_lock);
 978
 979         wrb = wrb_from_mccq(adapter);
 980         if (!wrb) {
 981                 status = -EBUSY;
 982                 goto err;
 983         }
 984         req = embedded_payload(wrb);
 985
 986         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 987                 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
 988
 989         req->hdr.domain = dom;
 990         req->if_id = cpu_to_le32(if_id);
 991         req->pmac_id = cpu_to_le32(pmac_id);
 992
 993         status = be_mcc_notify_wait(adapter);
 994
 995 err:
 996         spin_unlock_bh(&adapter->mcc_lock);
 997         return status;
 998 }
 999
1000 /* Uses Mbox */
1001 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
1002                 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
1003 {
1004         struct be_mcc_wrb *wrb;
1005         struct be_cmd_req_cq_create *req;
1006         struct be_dma_mem *q_mem = &cq->dma_mem;
1007         void *ctxt;
1008         int status;
1009
1010         if (mutex_lock_interruptible(&adapter->mbox_lock))
1011                 return -1;
1012
1013         wrb = wrb_from_mbox(adapter);
1014         req = embedded_payload(wrb);
1015         ctxt = &req->context;
1016
1017         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1018                 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL);
1019
1020         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1021
1022         if (BEx_chip(adapter)) {
1023                 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
1024                                                                 coalesce_wm);
1025                 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
1026                                                                 ctxt, no_delay);
1027                 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
1028                                                 __ilog2_u32(cq->len/256));
1029                 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
1030                 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
1031                 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
1032         } else {
1033                 req->hdr.version = 2;
1034                 req->page_size = 1; /* 1 for 4K */
1035                 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
1036                                                                 no_delay);
1037                 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
1038                                                 __ilog2_u32(cq->len/256));
1039                 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
1040                 AMAP_SET_BITS(struct amap_cq_context_v2, eventable,
1041                                                                 ctxt, 1);
1042                 AMAP_SET_BITS(struct amap_cq_context_v2, eqid,
1043                                                                 ctxt, eq->id);
1044         }
1045
1046         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1047
1048         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1049
1050         status = be_mbox_notify_wait(adapter);
1051         if (!status) {
1052                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
1053                 cq->id = le16_to_cpu(resp->cq_id);
1054                 cq->created = true;
1055         }
1056
1057         mutex_unlock(&adapter->mbox_lock);
1058
1059         return status;
1060 }
1061
1062 static u32 be_encoded_q_len(int q_len)
1063 {
1064         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
1065         if (len_encoded == 16)
1066                 len_encoded = 0;
1067         return len_encoded;
1068 }
1069
1070 static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
1071                                 struct be_queue_info *mccq,
1072                                 struct be_queue_info *cq)
1073 {
1074         struct be_mcc_wrb *wrb;
1075         struct be_cmd_req_mcc_ext_create *req;
1076         struct be_dma_mem *q_mem = &mccq->dma_mem;
1077         void *ctxt;
1078         int status;
1079
1080         if (mutex_lock_interruptible(&adapter->mbox_lock))
1081                 return -1;
1082
1083         wrb = wrb_from_mbox(adapter);
1084         req = embedded_payload(wrb);
1085         ctxt = &req->context;
1086
1087         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1088                         OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL);
1089
1090         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1091         if (lancer_chip(adapter)) {
1092                 req->hdr.version = 1;
1093                 req->cq_id = cpu_to_le16(cq->id);
1094
1095                 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
1096                                                 be_encoded_q_len(mccq->len));
1097                 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
1098                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
1099                                                                 ctxt, cq->id);
1100                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
1101                                                                  ctxt, 1);
1102
1103         } else {
1104                 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1105                 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1106                                                 be_encoded_q_len(mccq->len));
1107                 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1108         }
1109
1110         /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
1111         req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
1112         req->async_event_bitmap[0] |= cpu_to_le32(1 << ASYNC_EVENT_CODE_QNQ);
1113         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1114
1115         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1116
1117         status = be_mbox_notify_wait(adapter);
1118         if (!status) {
1119                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1120                 mccq->id = le16_to_cpu(resp->id);
1121                 mccq->created = true;
1122         }
1123         mutex_unlock(&adapter->mbox_lock);
1124
1125         return status;
1126 }
1127
1128 static int be_cmd_mccq_org_create(struct be_adapter *adapter,
1129                                 struct be_queue_info *mccq,
1130                                 struct be_queue_info *cq)
1131 {
1132         struct be_mcc_wrb *wrb;
1133         struct be_cmd_req_mcc_create *req;
1134         struct be_dma_mem *q_mem = &mccq->dma_mem;
1135         void *ctxt;
1136         int status;
1137
1138         if (mutex_lock_interruptible(&adapter->mbox_lock))
1139                 return -1;
1140
1141         wrb = wrb_from_mbox(adapter);
1142         req = embedded_payload(wrb);
1143         ctxt = &req->context;
1144
1145         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1146                         OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL);
1147
1148         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1149
1150         AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1151         AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1152                         be_encoded_q_len(mccq->len));
1153         AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1154
1155         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1156
1157         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1158
1159         status = be_mbox_notify_wait(adapter);
1160         if (!status) {
1161                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1162                 mccq->id = le16_to_cpu(resp->id);
1163                 mccq->created = true;
1164         }
1165
1166         mutex_unlock(&adapter->mbox_lock);
1167         return status;
1168 }
1169
1170 int be_cmd_mccq_create(struct be_adapter *adapter,
1171                         struct be_queue_info *mccq,
1172                         struct be_queue_info *cq)
1173 {
1174         int status;
1175
1176         status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1177         if (status && !lancer_chip(adapter)) {
1178                 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1179                         "or newer to avoid conflicting priorities between NIC "
1180                         "and FCoE traffic");
1181                 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1182         }
1183         return status;
1184 }
1185
1186 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
1187 {
1188         struct be_mcc_wrb wrb = {0};
1189         struct be_cmd_req_eth_tx_create *req;
1190         struct be_queue_info *txq = &txo->q;
1191         struct be_queue_info *cq = &txo->cq;
1192         struct be_dma_mem *q_mem = &txq->dma_mem;
1193         int status, ver = 0;
1194
1195         req = embedded_payload(&wrb);
1196         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1197                                 OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL);
1198
1199         if (lancer_chip(adapter)) {
1200                 req->hdr.version = 1;
1201         } else if (BEx_chip(adapter)) {
1202                 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1203                         req->hdr.version = 2;
1204         } else { /* For SH */
1205                 req->hdr.version = 2;
1206         }
1207
1208         if (req->hdr.version > 0)
1209                 req->if_id = cpu_to_le16(adapter->if_handle);
1210         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1211         req->ulp_num = BE_ULP1_NUM;
1212         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1213         req->cq_id = cpu_to_le16(cq->id);
1214         req->queue_size = be_encoded_q_len(txq->len);
1215         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1216         ver = req->hdr.version;
1217
1218         status = be_cmd_notify_wait(adapter, &wrb);
1219         if (!status) {
1220                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb);
1221                 txq->id = le16_to_cpu(resp->cid);
1222                 if (ver == 2)
1223                         txo->db_offset = le32_to_cpu(resp->db_offset);
1224                 else
1225                         txo->db_offset = DB_TXULP1_OFFSET;
1226                 txq->created = true;
1227         }
1228
1229         return status;
1230 }
1231
1232 /* Uses MCC */
1233 int be_cmd_rxq_create(struct be_adapter *adapter,
1234                 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1235                 u32 if_id, u32 rss, u8 *rss_id)
1236 {
1237         struct be_mcc_wrb *wrb;
1238         struct be_cmd_req_eth_rx_create *req;
1239         struct be_dma_mem *q_mem = &rxq->dma_mem;
1240         int status;
1241
1242         spin_lock_bh(&adapter->mcc_lock);
1243
1244         wrb = wrb_from_mccq(adapter);
1245         if (!wrb) {
1246                 status = -EBUSY;
1247                 goto err;
1248         }
1249         req = embedded_payload(wrb);
1250
1251         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1252                                 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1253
1254         req->cq_id = cpu_to_le16(cq_id);
1255         req->frag_size = fls(frag_size) - 1;
1256         req->num_pages = 2;
1257         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1258         req->interface_id = cpu_to_le32(if_id);
1259         req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
1260         req->rss_queue = cpu_to_le32(rss);
1261
1262         status = be_mcc_notify_wait(adapter);
1263         if (!status) {
1264                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1265                 rxq->id = le16_to_cpu(resp->id);
1266                 rxq->created = true;
1267                 *rss_id = resp->rss_id;
1268         }
1269
1270 err:
1271         spin_unlock_bh(&adapter->mcc_lock);
1272         return status;
1273 }
1274
1275 /* Generic destroyer function for all types of queues
1276  * Uses Mbox
1277  */
1278 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1279                 int queue_type)
1280 {
1281         struct be_mcc_wrb *wrb;
1282         struct be_cmd_req_q_destroy *req;
1283         u8 subsys = 0, opcode = 0;
1284         int status;
1285
1286         if (mutex_lock_interruptible(&adapter->mbox_lock))
1287                 return -1;
1288
1289         wrb = wrb_from_mbox(adapter);
1290         req = embedded_payload(wrb);
1291
1292         switch (queue_type) {
1293         case QTYPE_EQ:
1294                 subsys = CMD_SUBSYSTEM_COMMON;
1295                 opcode = OPCODE_COMMON_EQ_DESTROY;
1296                 break;
1297         case QTYPE_CQ:
1298                 subsys = CMD_SUBSYSTEM_COMMON;
1299                 opcode = OPCODE_COMMON_CQ_DESTROY;
1300                 break;
1301         case QTYPE_TXQ:
1302                 subsys = CMD_SUBSYSTEM_ETH;
1303                 opcode = OPCODE_ETH_TX_DESTROY;
1304                 break;
1305         case QTYPE_RXQ:
1306                 subsys = CMD_SUBSYSTEM_ETH;
1307                 opcode = OPCODE_ETH_RX_DESTROY;
1308                 break;
1309         case QTYPE_MCCQ:
1310                 subsys = CMD_SUBSYSTEM_COMMON;
1311                 opcode = OPCODE_COMMON_MCC_DESTROY;
1312                 break;
1313         default:
1314                 BUG();
1315         }
1316
1317         be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1318                                 NULL);
1319         req->id = cpu_to_le16(q->id);
1320
1321         status = be_mbox_notify_wait(adapter);
1322         q->created = false;
1323
1324         mutex_unlock(&adapter->mbox_lock);
1325         return status;
1326 }
1327
1328 /* Uses MCC */
1329 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1330 {
1331         struct be_mcc_wrb *wrb;
1332         struct be_cmd_req_q_destroy *req;
1333         int status;
1334
1335         spin_lock_bh(&adapter->mcc_lock);
1336
1337         wrb = wrb_from_mccq(adapter);
1338         if (!wrb) {
1339                 status = -EBUSY;
1340                 goto err;
1341         }
1342         req = embedded_payload(wrb);
1343
1344         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1345                         OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1346         req->id = cpu_to_le16(q->id);
1347
1348         status = be_mcc_notify_wait(adapter);
1349         q->created = false;
1350
1351 err:
1352         spin_unlock_bh(&adapter->mcc_lock);
1353         return status;
1354 }
1355
1356 /* Create an rx filtering policy configuration on an i/f
1357  * Will use MBOX only if MCCQ has not been created.
1358  */
1359 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1360                      u32 *if_handle, u32 domain)
1361 {
1362         struct be_mcc_wrb wrb = {0};
1363         struct be_cmd_req_if_create *req;
1364         int status;
1365
1366         req = embedded_payload(&wrb);
1367         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1368                 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), &wrb, NULL);
1369         req->hdr.domain = domain;
1370         req->capability_flags = cpu_to_le32(cap_flags);
1371         req->enable_flags = cpu_to_le32(en_flags);
1372         req->pmac_invalid = true;
1373
1374         status = be_cmd_notify_wait(adapter, &wrb);
1375         if (!status) {
1376                 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb);
1377                 *if_handle = le32_to_cpu(resp->interface_id);
1378
1379                 /* Hack to retrieve VF's pmac-id on BE3 */
1380                 if (BE3_chip(adapter) && !be_physfn(adapter))
1381                         adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
1382         }
1383         return status;
1384 }
1385
1386 /* Uses MCCQ */
1387 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1388 {
1389         struct be_mcc_wrb *wrb;
1390         struct be_cmd_req_if_destroy *req;
1391         int status;
1392
1393         if (interface_id == -1)
1394                 return 0;
1395
1396         spin_lock_bh(&adapter->mcc_lock);
1397
1398         wrb = wrb_from_mccq(adapter);
1399         if (!wrb) {
1400                 status = -EBUSY;
1401                 goto err;
1402         }
1403         req = embedded_payload(wrb);
1404
1405         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1406                 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL);
1407         req->hdr.domain = domain;
1408         req->interface_id = cpu_to_le32(interface_id);
1409
1410         status = be_mcc_notify_wait(adapter);
1411 err:
1412         spin_unlock_bh(&adapter->mcc_lock);
1413         return status;
1414 }
1415
1416 /* Get stats is a non embedded command: the request is not embedded inside
1417  * WRB but is a separate dma memory block
1418  * Uses asynchronous MCC
1419  */
1420 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1421 {
1422         struct be_mcc_wrb *wrb;
1423         struct be_cmd_req_hdr *hdr;
1424         int status = 0;
1425
1426         spin_lock_bh(&adapter->mcc_lock);
1427
1428         wrb = wrb_from_mccq(adapter);
1429         if (!wrb) {
1430                 status = -EBUSY;
1431                 goto err;
1432         }
1433         hdr = nonemb_cmd->va;
1434
1435         be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1436                 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd);
1437
1438         /* version 1 of the cmd is not supported only by BE2 */
1439         if (!BE2_chip(adapter))
1440                 hdr->version = 1;
1441
1442         be_mcc_notify(adapter);
1443         adapter->stats_cmd_sent = true;
1444
1445 err:
1446         spin_unlock_bh(&adapter->mcc_lock);
1447         return status;
1448 }
1449
1450 /* Lancer Stats */
1451 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1452                                 struct be_dma_mem *nonemb_cmd)
1453 {
1454
1455         struct be_mcc_wrb *wrb;
1456         struct lancer_cmd_req_pport_stats *req;
1457         int status = 0;
1458
1459         if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1460                             CMD_SUBSYSTEM_ETH))
1461                 return -EPERM;
1462
1463         spin_lock_bh(&adapter->mcc_lock);
1464
1465         wrb = wrb_from_mccq(adapter);
1466         if (!wrb) {
1467                 status = -EBUSY;
1468                 goto err;
1469         }
1470         req = nonemb_cmd->va;
1471
1472         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1473                         OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb,
1474                         nonemb_cmd);
1475
1476         req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1477         req->cmd_params.params.reset_stats = 0;
1478
1479         be_mcc_notify(adapter);
1480         adapter->stats_cmd_sent = true;
1481
1482 err:
1483         spin_unlock_bh(&adapter->mcc_lock);
1484         return status;
1485 }
1486
1487 static int be_mac_to_link_speed(int mac_speed)
1488 {
1489         switch (mac_speed) {
1490         case PHY_LINK_SPEED_ZERO:
1491                 return 0;
1492         case PHY_LINK_SPEED_10MBPS:
1493                 return 10;
1494         case PHY_LINK_SPEED_100MBPS:
1495                 return 100;
1496         case PHY_LINK_SPEED_1GBPS:
1497                 return 1000;
1498         case PHY_LINK_SPEED_10GBPS:
1499                 return 10000;
1500         case PHY_LINK_SPEED_20GBPS:
1501                 return 20000;
1502         case PHY_LINK_SPEED_25GBPS:
1503                 return 25000;
1504         case PHY_LINK_SPEED_40GBPS:
1505                 return 40000;
1506         }
1507         return 0;
1508 }
1509
1510 /* Uses synchronous mcc
1511  * Returns link_speed in Mbps
1512  */
1513 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1514                              u8 *link_status, u32 dom)
1515 {
1516         struct be_mcc_wrb *wrb;
1517         struct be_cmd_req_link_status *req;
1518         int status;
1519
1520         spin_lock_bh(&adapter->mcc_lock);
1521
1522         if (link_status)
1523                 *link_status = LINK_DOWN;
1524
1525         wrb = wrb_from_mccq(adapter);
1526         if (!wrb) {
1527                 status = -EBUSY;
1528                 goto err;
1529         }
1530         req = embedded_payload(wrb);
1531
1532         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1533                 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL);
1534
1535         /* version 1 of the cmd is not supported only by BE2 */
1536         if (!BE2_chip(adapter))
1537                 req->hdr.version = 1;
1538
1539         req->hdr.domain = dom;
1540
1541         status = be_mcc_notify_wait(adapter);
1542         if (!status) {
1543                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1544                 if (link_speed) {
1545                         *link_speed = resp->link_speed ?
1546                                       le16_to_cpu(resp->link_speed) * 10 :
1547                                       be_mac_to_link_speed(resp->mac_speed);
1548
1549                         if (!resp->logical_link_status)
1550                                 *link_speed = 0;
1551                 }
1552                 if (link_status)
1553                         *link_status = resp->logical_link_status;
1554         }
1555
1556 err:
1557         spin_unlock_bh(&adapter->mcc_lock);
1558         return status;
1559 }
1560
1561 /* Uses synchronous mcc */
1562 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1563 {
1564         struct be_mcc_wrb *wrb;
1565         struct be_cmd_req_get_cntl_addnl_attribs *req;
1566         int status = 0;
1567
1568         spin_lock_bh(&adapter->mcc_lock);
1569
1570         wrb = wrb_from_mccq(adapter);
1571         if (!wrb) {
1572                 status = -EBUSY;
1573                 goto err;
1574         }
1575         req = embedded_payload(wrb);
1576
1577         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1578                 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req),
1579                 wrb, NULL);
1580
1581         be_mcc_notify(adapter);
1582
1583 err:
1584         spin_unlock_bh(&adapter->mcc_lock);
1585         return status;
1586 }
1587
1588 /* Uses synchronous mcc */
1589 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1590 {
1591         struct be_mcc_wrb *wrb;
1592         struct be_cmd_req_get_fat *req;
1593         int status;
1594
1595         spin_lock_bh(&adapter->mcc_lock);
1596
1597         wrb = wrb_from_mccq(adapter);
1598         if (!wrb) {
1599                 status = -EBUSY;
1600                 goto err;
1601         }
1602         req = embedded_payload(wrb);
1603
1604         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1605                 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL);
1606         req->fat_operation = cpu_to_le32(QUERY_FAT);
1607         status = be_mcc_notify_wait(adapter);
1608         if (!status) {
1609                 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1610                 if (log_size && resp->log_size)
1611                         *log_size = le32_to_cpu(resp->log_size) -
1612                                         sizeof(u32);
1613         }
1614 err:
1615         spin_unlock_bh(&adapter->mcc_lock);
1616         return status;
1617 }
1618
1619 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1620 {
1621         struct be_dma_mem get_fat_cmd;
1622         struct be_mcc_wrb *wrb;
1623         struct be_cmd_req_get_fat *req;
1624         u32 offset = 0, total_size, buf_size,
1625                                 log_offset = sizeof(u32), payload_len;
1626         int status;
1627
1628         if (buf_len == 0)
1629                 return;
1630
1631         total_size = buf_len;
1632
1633         get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1634         get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1635                         get_fat_cmd.size,
1636                         &get_fat_cmd.dma);
1637         if (!get_fat_cmd.va) {
1638                 status = -ENOMEM;
1639                 dev_err(&adapter->pdev->dev,
1640                 "Memory allocation failure while retrieving FAT data\n");
1641                 return;
1642         }
1643
1644         spin_lock_bh(&adapter->mcc_lock);
1645
1646         while (total_size) {
1647                 buf_size = min(total_size, (u32)60*1024);
1648                 total_size -= buf_size;
1649
1650                 wrb = wrb_from_mccq(adapter);
1651                 if (!wrb) {
1652                         status = -EBUSY;
1653                         goto err;
1654                 }
1655                 req = get_fat_cmd.va;
1656
1657                 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1658                 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1659                                 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb,
1660                                 &get_fat_cmd);
1661
1662                 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1663                 req->read_log_offset = cpu_to_le32(log_offset);
1664                 req->read_log_length = cpu_to_le32(buf_size);
1665                 req->data_buffer_size = cpu_to_le32(buf_size);
1666
1667                 status = be_mcc_notify_wait(adapter);
1668                 if (!status) {
1669                         struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1670                         memcpy(buf + offset,
1671                                 resp->data_buffer,
1672                                 le32_to_cpu(resp->read_log_length));
1673                 } else {
1674                         dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1675                         goto err;
1676                 }
1677                 offset += buf_size;
1678                 log_offset += buf_size;
1679         }
1680 err:
1681         pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1682                         get_fat_cmd.va,
1683                         get_fat_cmd.dma);
1684         spin_unlock_bh(&adapter->mcc_lock);
1685 }
1686
1687 /* Uses synchronous mcc */
1688 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1689                         char *fw_on_flash)
1690 {
1691         struct be_mcc_wrb *wrb;
1692         struct be_cmd_req_get_fw_version *req;
1693         int status;
1694
1695         spin_lock_bh(&adapter->mcc_lock);
1696
1697         wrb = wrb_from_mccq(adapter);
1698         if (!wrb) {
1699                 status = -EBUSY;
1700                 goto err;
1701         }
1702
1703         req = embedded_payload(wrb);
1704
1705         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1706                 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL);
1707         status = be_mcc_notify_wait(adapter);
1708         if (!status) {
1709                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1710                 strcpy(fw_ver, resp->firmware_version_string);
1711                 if (fw_on_flash)
1712                         strcpy(fw_on_flash, resp->fw_on_flash_version_string);
1713         }
1714 err:
1715         spin_unlock_bh(&adapter->mcc_lock);
1716         return status;
1717 }
1718
1719 /* set the EQ delay interval of an EQ to specified value
1720  * Uses async mcc
1721  */
1722 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1723 {
1724         struct be_mcc_wrb *wrb;
1725         struct be_cmd_req_modify_eq_delay *req;
1726         int status = 0;
1727
1728         spin_lock_bh(&adapter->mcc_lock);
1729
1730         wrb = wrb_from_mccq(adapter);
1731         if (!wrb) {
1732                 status = -EBUSY;
1733                 goto err;
1734         }
1735         req = embedded_payload(wrb);
1736
1737         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1738                 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL);
1739
1740         req->num_eq = cpu_to_le32(1);
1741         req->delay[0].eq_id = cpu_to_le32(eq_id);
1742         req->delay[0].phase = 0;
1743         req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1744
1745         be_mcc_notify(adapter);
1746
1747 err:
1748         spin_unlock_bh(&adapter->mcc_lock);
1749         return status;
1750 }
1751
1752 /* Uses sycnhronous mcc */
1753 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1754                         u32 num, bool untagged, bool promiscuous)
1755 {
1756         struct be_mcc_wrb *wrb;
1757         struct be_cmd_req_vlan_config *req;
1758         int status;
1759
1760         spin_lock_bh(&adapter->mcc_lock);
1761
1762         wrb = wrb_from_mccq(adapter);
1763         if (!wrb) {
1764                 status = -EBUSY;
1765                 goto err;
1766         }
1767         req = embedded_payload(wrb);
1768
1769         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1770                 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL);
1771
1772         req->interface_id = if_id;
1773         req->promiscuous = promiscuous;
1774         req->untagged = untagged;
1775         req->num_vlan = num;
1776         if (!promiscuous) {
1777                 memcpy(req->normal_vlan, vtag_array,
1778                         req->num_vlan * sizeof(vtag_array[0]));
1779         }
1780
1781         status = be_mcc_notify_wait(adapter);
1782
1783 err:
1784         spin_unlock_bh(&adapter->mcc_lock);
1785         return status;
1786 }
1787
1788 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1789 {
1790         struct be_mcc_wrb *wrb;
1791         struct be_dma_mem *mem = &adapter->rx_filter;
1792         struct be_cmd_req_rx_filter *req = mem->va;
1793         int status;
1794
1795         spin_lock_bh(&adapter->mcc_lock);
1796
1797         wrb = wrb_from_mccq(adapter);
1798         if (!wrb) {
1799                 status = -EBUSY;
1800                 goto err;
1801         }
1802         memset(req, 0, sizeof(*req));
1803         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1804                                 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1805                                 wrb, mem);
1806
1807         req->if_id = cpu_to_le32(adapter->if_handle);
1808         if (flags & IFF_PROMISC) {
1809                 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1810                                         BE_IF_FLAGS_VLAN_PROMISCUOUS |
1811                                         BE_IF_FLAGS_MCAST_PROMISCUOUS);
1812                 if (value == ON)
1813                         req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1814                                                 BE_IF_FLAGS_VLAN_PROMISCUOUS |
1815                                                 BE_IF_FLAGS_MCAST_PROMISCUOUS);
1816         } else if (flags & IFF_ALLMULTI) {
1817                 req->if_flags_mask = req->if_flags =
1818                                 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1819         } else if (flags & BE_FLAGS_VLAN_PROMISC) {
1820                 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_VLAN_PROMISCUOUS);
1821
1822                 if (value == ON)
1823                         req->if_flags =
1824                                 cpu_to_le32(BE_IF_FLAGS_VLAN_PROMISCUOUS);
1825         } else {
1826                 struct netdev_hw_addr *ha;
1827                 int i = 0;
1828
1829                 req->if_flags_mask = req->if_flags =
1830                                 cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1831
1832                 /* Reset mcast promisc mode if already set by setting mask
1833                  * and not setting flags field
1834                  */
1835                 req->if_flags_mask |=
1836                         cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
1837                                     be_if_cap_flags(adapter));
1838                 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
1839                 netdev_for_each_mc_addr(ha, adapter->netdev)
1840                         memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
1841         }
1842
1843         status = be_mcc_notify_wait(adapter);
1844 err:
1845         spin_unlock_bh(&adapter->mcc_lock);
1846         return status;
1847 }
1848
1849 /* Uses synchrounous mcc */
1850 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1851 {
1852         struct be_mcc_wrb *wrb;
1853         struct be_cmd_req_set_flow_control *req;
1854         int status;
1855
1856         if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
1857                             CMD_SUBSYSTEM_COMMON))
1858                 return -EPERM;
1859
1860         spin_lock_bh(&adapter->mcc_lock);
1861
1862         wrb = wrb_from_mccq(adapter);
1863         if (!wrb) {
1864                 status = -EBUSY;
1865                 goto err;
1866         }
1867         req = embedded_payload(wrb);
1868
1869         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1870                 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1871
1872         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1873         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1874
1875         status = be_mcc_notify_wait(adapter);
1876
1877 err:
1878         spin_unlock_bh(&adapter->mcc_lock);
1879         return status;
1880 }
1881
1882 /* Uses sycn mcc */
1883 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1884 {
1885         struct be_mcc_wrb *wrb;
1886         struct be_cmd_req_get_flow_control *req;
1887         int status;
1888
1889         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
1890                             CMD_SUBSYSTEM_COMMON))
1891                 return -EPERM;
1892
1893         spin_lock_bh(&adapter->mcc_lock);
1894
1895         wrb = wrb_from_mccq(adapter);
1896         if (!wrb) {
1897                 status = -EBUSY;
1898                 goto err;
1899         }
1900         req = embedded_payload(wrb);
1901
1902         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1903                 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1904
1905         status = be_mcc_notify_wait(adapter);
1906         if (!status) {
1907                 struct be_cmd_resp_get_flow_control *resp =
1908                                                 embedded_payload(wrb);
1909                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1910                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1911         }
1912
1913 err:
1914         spin_unlock_bh(&adapter->mcc_lock);
1915         return status;
1916 }
1917
1918 /* Uses mbox */
1919 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1920                         u32 *mode, u32 *caps, u16 *asic_rev)
1921 {
1922         struct be_mcc_wrb *wrb;
1923         struct be_cmd_req_query_fw_cfg *req;
1924         int status;
1925
1926         if (mutex_lock_interruptible(&adapter->mbox_lock))
1927                 return -1;
1928
1929         wrb = wrb_from_mbox(adapter);
1930         req = embedded_payload(wrb);
1931
1932         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1933                 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL);
1934
1935         status = be_mbox_notify_wait(adapter);
1936         if (!status) {
1937                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1938                 *port_num = le32_to_cpu(resp->phys_port);
1939                 *mode = le32_to_cpu(resp->function_mode);
1940                 *caps = le32_to_cpu(resp->function_caps);
1941                 *asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
1942         }
1943
1944         mutex_unlock(&adapter->mbox_lock);
1945         return status;
1946 }
1947
1948 /* Uses mbox */
1949 int be_cmd_reset_function(struct be_adapter *adapter)
1950 {
1951         struct be_mcc_wrb *wrb;
1952         struct be_cmd_req_hdr *req;
1953         int status;
1954
1955         if (lancer_chip(adapter)) {
1956                 status = lancer_wait_ready(adapter);
1957                 if (!status) {
1958                         iowrite32(SLI_PORT_CONTROL_IP_MASK,
1959                                   adapter->db + SLIPORT_CONTROL_OFFSET);
1960                         status = lancer_test_and_set_rdy_state(adapter);
1961                 }
1962                 if (status) {
1963                         dev_err(&adapter->pdev->dev,
1964                                 "Adapter in non recoverable error\n");
1965                 }
1966                 return status;
1967         }
1968
1969         if (mutex_lock_interruptible(&adapter->mbox_lock))
1970                 return -1;
1971
1972         wrb = wrb_from_mbox(adapter);
1973         req = embedded_payload(wrb);
1974
1975         be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1976                 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL);
1977
1978         status = be_mbox_notify_wait(adapter);
1979
1980         mutex_unlock(&adapter->mbox_lock);
1981         return status;
1982 }
1983
1984 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
1985                         u32 rss_hash_opts, u16 table_size)
1986 {
1987         struct be_mcc_wrb *wrb;
1988         struct be_cmd_req_rss_config *req;
1989         u32 myhash[10] = {0x15d43fa5, 0x2534685a, 0x5f87693a, 0x5668494e,
1990                         0x33cf6a53, 0x383334c6, 0x76ac4257, 0x59b242b2,
1991                         0x3ea83c02, 0x4a110304};
1992         int status;
1993
1994         if (mutex_lock_interruptible(&adapter->mbox_lock))
1995                 return -1;
1996
1997         wrb = wrb_from_mbox(adapter);
1998         req = embedded_payload(wrb);
1999
2000         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2001                 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
2002
2003         req->if_id = cpu_to_le32(adapter->if_handle);
2004         req->enable_rss = cpu_to_le16(rss_hash_opts);
2005         req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
2006
2007         if (lancer_chip(adapter) || skyhawk_chip(adapter))
2008                 req->hdr.version = 1;
2009
2010         memcpy(req->cpu_table, rsstable, table_size);
2011         memcpy(req->hash, myhash, sizeof(myhash));
2012         be_dws_cpu_to_le(req->hash, sizeof(req->hash));
2013
2014         status = be_mbox_notify_wait(adapter);
2015
2016         mutex_unlock(&adapter->mbox_lock);
2017         return status;
2018 }
2019
2020 /* Uses sync mcc */
2021 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
2022                         u8 bcn, u8 sts, u8 state)
2023 {
2024         struct be_mcc_wrb *wrb;
2025         struct be_cmd_req_enable_disable_beacon *req;
2026         int status;
2027
2028         spin_lock_bh(&adapter->mcc_lock);
2029
2030         wrb = wrb_from_mccq(adapter);
2031         if (!wrb) {
2032                 status = -EBUSY;
2033                 goto err;
2034         }
2035         req = embedded_payload(wrb);
2036
2037         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2038                 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL);
2039
2040         req->port_num = port_num;
2041         req->beacon_state = state;
2042         req->beacon_duration = bcn;
2043         req->status_duration = sts;
2044
2045         status = be_mcc_notify_wait(adapter);
2046
2047 err:
2048         spin_unlock_bh(&adapter->mcc_lock);
2049         return status;
2050 }
2051
2052 /* Uses sync mcc */
2053 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2054 {
2055         struct be_mcc_wrb *wrb;
2056         struct be_cmd_req_get_beacon_state *req;
2057         int status;
2058
2059         spin_lock_bh(&adapter->mcc_lock);
2060
2061         wrb = wrb_from_mccq(adapter);
2062         if (!wrb) {
2063                 status = -EBUSY;
2064                 goto err;
2065         }
2066         req = embedded_payload(wrb);
2067
2068         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2069                 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL);
2070
2071         req->port_num = port_num;
2072
2073         status = be_mcc_notify_wait(adapter);
2074         if (!status) {
2075                 struct be_cmd_resp_get_beacon_state *resp =
2076                                                 embedded_payload(wrb);
2077                 *state = resp->beacon_state;
2078         }
2079
2080 err:
2081         spin_unlock_bh(&adapter->mcc_lock);
2082         return status;
2083 }
2084
2085 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2086                             u32 data_size, u32 data_offset,
2087                             const char *obj_name, u32 *data_written,
2088                             u8 *change_status, u8 *addn_status)
2089 {
2090         struct be_mcc_wrb *wrb;
2091         struct lancer_cmd_req_write_object *req;
2092         struct lancer_cmd_resp_write_object *resp;
2093         void *ctxt = NULL;
2094         int status;
2095
2096         spin_lock_bh(&adapter->mcc_lock);
2097         adapter->flash_status = 0;
2098
2099         wrb = wrb_from_mccq(adapter);
2100         if (!wrb) {
2101                 status = -EBUSY;
2102                 goto err_unlock;
2103         }
2104
2105         req = embedded_payload(wrb);
2106
2107         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2108                                 OPCODE_COMMON_WRITE_OBJECT,
2109                                 sizeof(struct lancer_cmd_req_write_object), wrb,
2110                                 NULL);
2111
2112         ctxt = &req->context;
2113         AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2114                         write_length, ctxt, data_size);
2115
2116         if (data_size == 0)
2117                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2118                                 eof, ctxt, 1);
2119         else
2120                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2121                                 eof, ctxt, 0);
2122
2123         be_dws_cpu_to_le(ctxt, sizeof(req->context));
2124         req->write_offset = cpu_to_le32(data_offset);
2125         strcpy(req->object_name, obj_name);
2126         req->descriptor_count = cpu_to_le32(1);
2127         req->buf_len = cpu_to_le32(data_size);
2128         req->addr_low = cpu_to_le32((cmd->dma +
2129                                 sizeof(struct lancer_cmd_req_write_object))
2130                                 & 0xFFFFFFFF);
2131         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2132                                 sizeof(struct lancer_cmd_req_write_object)));
2133
2134         be_mcc_notify(adapter);
2135         spin_unlock_bh(&adapter->mcc_lock);
2136
2137         if (!wait_for_completion_timeout(&adapter->flash_compl,
2138                                          msecs_to_jiffies(60000)))
2139                 status = -1;
2140         else
2141                 status = adapter->flash_status;
2142
2143         resp = embedded_payload(wrb);
2144         if (!status) {
2145                 *data_written = le32_to_cpu(resp->actual_write_len);
2146                 *change_status = resp->change_status;
2147         } else {
2148                 *addn_status = resp->additional_status;
2149         }
2150
2151         return status;
2152
2153 err_unlock:
2154         spin_unlock_bh(&adapter->mcc_lock);
2155         return status;
2156 }
2157
2158 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2159                 u32 data_size, u32 data_offset, const char *obj_name,
2160                 u32 *data_read, u32 *eof, u8 *addn_status)
2161 {
2162         struct be_mcc_wrb *wrb;
2163         struct lancer_cmd_req_read_object *req;
2164         struct lancer_cmd_resp_read_object *resp;
2165         int status;
2166
2167         spin_lock_bh(&adapter->mcc_lock);
2168
2169         wrb = wrb_from_mccq(adapter);
2170         if (!wrb) {
2171                 status = -EBUSY;
2172                 goto err_unlock;
2173         }
2174
2175         req = embedded_payload(wrb);
2176
2177         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2178                         OPCODE_COMMON_READ_OBJECT,
2179                         sizeof(struct lancer_cmd_req_read_object), wrb,
2180                         NULL);
2181
2182         req->desired_read_len = cpu_to_le32(data_size);
2183         req->read_offset = cpu_to_le32(data_offset);
2184         strcpy(req->object_name, obj_name);
2185         req->descriptor_count = cpu_to_le32(1);
2186         req->buf_len = cpu_to_le32(data_size);
2187         req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2188         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2189
2190         status = be_mcc_notify_wait(adapter);
2191
2192         resp = embedded_payload(wrb);
2193         if (!status) {
2194                 *data_read = le32_to_cpu(resp->actual_read_len);
2195                 *eof = le32_to_cpu(resp->eof);
2196         } else {
2197                 *addn_status = resp->additional_status;
2198         }
2199
2200 err_unlock:
2201         spin_unlock_bh(&adapter->mcc_lock);
2202         return status;
2203 }
2204
2205 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
2206                         u32 flash_type, u32 flash_opcode, u32 buf_size)
2207 {
2208         struct be_mcc_wrb *wrb;
2209         struct be_cmd_write_flashrom *req;
2210         int status;
2211
2212         spin_lock_bh(&adapter->mcc_lock);
2213         adapter->flash_status = 0;
2214
2215         wrb = wrb_from_mccq(adapter);
2216         if (!wrb) {
2217                 status = -EBUSY;
2218                 goto err_unlock;
2219         }
2220         req = cmd->va;
2221
2222         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2223                 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd);
2224
2225         req->params.op_type = cpu_to_le32(flash_type);
2226         req->params.op_code = cpu_to_le32(flash_opcode);
2227         req->params.data_buf_size = cpu_to_le32(buf_size);
2228
2229         be_mcc_notify(adapter);
2230         spin_unlock_bh(&adapter->mcc_lock);
2231
2232         if (!wait_for_completion_timeout(&adapter->flash_compl,
2233                         msecs_to_jiffies(40000)))
2234                 status = -1;
2235         else
2236                 status = adapter->flash_status;
2237
2238         return status;
2239
2240 err_unlock:
2241         spin_unlock_bh(&adapter->mcc_lock);
2242         return status;
2243 }
2244
2245 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2246                          int offset)
2247 {
2248         struct be_mcc_wrb *wrb;
2249         struct be_cmd_read_flash_crc *req;
2250         int status;
2251
2252         spin_lock_bh(&adapter->mcc_lock);
2253
2254         wrb = wrb_from_mccq(adapter);
2255         if (!wrb) {
2256                 status = -EBUSY;
2257                 goto err;
2258         }
2259         req = embedded_payload(wrb);
2260
2261         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2262                                OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2263                                wrb, NULL);
2264
2265         req->params.op_type = cpu_to_le32(OPTYPE_REDBOOT);
2266         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2267         req->params.offset = cpu_to_le32(offset);
2268         req->params.data_buf_size = cpu_to_le32(0x4);
2269
2270         status = be_mcc_notify_wait(adapter);
2271         if (!status)
2272                 memcpy(flashed_crc, req->crc, 4);
2273
2274 err:
2275         spin_unlock_bh(&adapter->mcc_lock);
2276         return status;
2277 }
2278
2279 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2280                                 struct be_dma_mem *nonemb_cmd)
2281 {
2282         struct be_mcc_wrb *wrb;
2283         struct be_cmd_req_acpi_wol_magic_config *req;
2284         int status;
2285
2286         spin_lock_bh(&adapter->mcc_lock);
2287
2288         wrb = wrb_from_mccq(adapter);
2289         if (!wrb) {
2290                 status = -EBUSY;
2291                 goto err;
2292         }
2293         req = nonemb_cmd->va;
2294
2295         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2296                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb,
2297                 nonemb_cmd);
2298         memcpy(req->magic_mac, mac, ETH_ALEN);
2299
2300         status = be_mcc_notify_wait(adapter);
2301
2302 err:
2303         spin_unlock_bh(&adapter->mcc_lock);
2304         return status;
2305 }
2306
2307 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2308                         u8 loopback_type, u8 enable)
2309 {
2310         struct be_mcc_wrb *wrb;
2311         struct be_cmd_req_set_lmode *req;
2312         int status;
2313
2314         spin_lock_bh(&adapter->mcc_lock);
2315
2316         wrb = wrb_from_mccq(adapter);
2317         if (!wrb) {
2318                 status = -EBUSY;
2319                 goto err;
2320         }
2321
2322         req = embedded_payload(wrb);
2323
2324         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2325                         OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb,
2326                         NULL);
2327
2328         req->src_port = port_num;
2329         req->dest_port = port_num;
2330         req->loopback_type = loopback_type;
2331         req->loopback_state = enable;
2332
2333         status = be_mcc_notify_wait(adapter);
2334 err:
2335         spin_unlock_bh(&adapter->mcc_lock);
2336         return status;
2337 }
2338
2339 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2340                 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
2341 {
2342         struct be_mcc_wrb *wrb;
2343         struct be_cmd_req_loopback_test *req;
2344         int status;
2345
2346         spin_lock_bh(&adapter->mcc_lock);
2347
2348         wrb = wrb_from_mccq(adapter);
2349         if (!wrb) {
2350                 status = -EBUSY;
2351                 goto err;
2352         }
2353
2354         req = embedded_payload(wrb);
2355
2356         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2357                         OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL);
2358         req->hdr.timeout = cpu_to_le32(4);
2359
2360         req->pattern = cpu_to_le64(pattern);
2361         req->src_port = cpu_to_le32(port_num);
2362         req->dest_port = cpu_to_le32(port_num);
2363         req->pkt_size = cpu_to_le32(pkt_size);
2364         req->num_pkts = cpu_to_le32(num_pkts);
2365         req->loopback_type = cpu_to_le32(loopback_type);
2366
2367         status = be_mcc_notify_wait(adapter);
2368         if (!status) {
2369                 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
2370                 status = le32_to_cpu(resp->status);
2371         }
2372
2373 err:
2374         spin_unlock_bh(&adapter->mcc_lock);
2375         return status;
2376 }
2377
2378 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2379                                 u32 byte_cnt, struct be_dma_mem *cmd)
2380 {
2381         struct be_mcc_wrb *wrb;
2382         struct be_cmd_req_ddrdma_test *req;
2383         int status;
2384         int i, j = 0;
2385
2386         spin_lock_bh(&adapter->mcc_lock);
2387
2388         wrb = wrb_from_mccq(adapter);
2389         if (!wrb) {
2390                 status = -EBUSY;
2391                 goto err;
2392         }
2393         req = cmd->va;
2394         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2395                         OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd);
2396
2397         req->pattern = cpu_to_le64(pattern);
2398         req->byte_count = cpu_to_le32(byte_cnt);
2399         for (i = 0; i < byte_cnt; i++) {
2400                 req->snd_buff[i] = (u8)(pattern >> (j*8));
2401                 j++;
2402                 if (j > 7)
2403                         j = 0;
2404         }
2405
2406         status = be_mcc_notify_wait(adapter);
2407
2408         if (!status) {
2409                 struct be_cmd_resp_ddrdma_test *resp;
2410                 resp = cmd->va;
2411                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2412                                 resp->snd_err) {
2413                         status = -1;
2414                 }
2415         }
2416
2417 err:
2418         spin_unlock_bh(&adapter->mcc_lock);
2419         return status;
2420 }
2421
2422 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2423                                 struct be_dma_mem *nonemb_cmd)
2424 {
2425         struct be_mcc_wrb *wrb;
2426         struct be_cmd_req_seeprom_read *req;
2427         int status;
2428
2429         spin_lock_bh(&adapter->mcc_lock);
2430
2431         wrb = wrb_from_mccq(adapter);
2432         if (!wrb) {
2433                 status = -EBUSY;
2434                 goto err;
2435         }
2436         req = nonemb_cmd->va;
2437
2438         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2439                         OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2440                         nonemb_cmd);
2441
2442         status = be_mcc_notify_wait(adapter);
2443
2444 err:
2445         spin_unlock_bh(&adapter->mcc_lock);
2446         return status;
2447 }
2448
2449 int be_cmd_get_phy_info(struct be_adapter *adapter)
2450 {
2451         struct be_mcc_wrb *wrb;
2452         struct be_cmd_req_get_phy_info *req;
2453         struct be_dma_mem cmd;
2454         int status;
2455
2456         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
2457                             CMD_SUBSYSTEM_COMMON))
2458                 return -EPERM;
2459
2460         spin_lock_bh(&adapter->mcc_lock);
2461
2462         wrb = wrb_from_mccq(adapter);
2463         if (!wrb) {
2464                 status = -EBUSY;
2465                 goto err;
2466         }
2467         cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2468         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2469                                         &cmd.dma);
2470         if (!cmd.va) {
2471                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2472                 status = -ENOMEM;
2473                 goto err;
2474         }
2475
2476         req = cmd.va;
2477
2478         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2479                         OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2480                         wrb, &cmd);
2481
2482         status = be_mcc_notify_wait(adapter);
2483         if (!status) {
2484                 struct be_phy_info *resp_phy_info =
2485                                 cmd.va + sizeof(struct be_cmd_req_hdr);
2486                 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2487                 adapter->phy.interface_type =
2488                         le16_to_cpu(resp_phy_info->interface_type);
2489                 adapter->phy.auto_speeds_supported =
2490                         le16_to_cpu(resp_phy_info->auto_speeds_supported);
2491                 adapter->phy.fixed_speeds_supported =
2492                         le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2493                 adapter->phy.misc_params =
2494                         le32_to_cpu(resp_phy_info->misc_params);
2495
2496                 if (BE2_chip(adapter)) {
2497                         adapter->phy.fixed_speeds_supported =
2498                                 BE_SUPPORTED_SPEED_10GBPS |
2499                                 BE_SUPPORTED_SPEED_1GBPS;
2500                 }
2501         }
2502         pci_free_consistent(adapter->pdev, cmd.size,
2503                                 cmd.va, cmd.dma);
2504 err:
2505         spin_unlock_bh(&adapter->mcc_lock);
2506         return status;
2507 }
2508
2509 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2510 {
2511         struct be_mcc_wrb *wrb;
2512         struct be_cmd_req_set_qos *req;
2513         int status;
2514
2515         spin_lock_bh(&adapter->mcc_lock);
2516
2517         wrb = wrb_from_mccq(adapter);
2518         if (!wrb) {
2519                 status = -EBUSY;
2520                 goto err;
2521         }
2522
2523         req = embedded_payload(wrb);
2524
2525         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2526                         OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
2527
2528         req->hdr.domain = domain;
2529         req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2530         req->max_bps_nic = cpu_to_le32(bps);
2531
2532         status = be_mcc_notify_wait(adapter);
2533
2534 err:
2535         spin_unlock_bh(&adapter->mcc_lock);
2536         return status;
2537 }
2538
2539 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2540 {
2541         struct be_mcc_wrb *wrb;
2542         struct be_cmd_req_cntl_attribs *req;
2543         struct be_cmd_resp_cntl_attribs *resp;
2544         int status;
2545         int payload_len = max(sizeof(*req), sizeof(*resp));
2546         struct mgmt_controller_attrib *attribs;
2547         struct be_dma_mem attribs_cmd;
2548
2549         if (mutex_lock_interruptible(&adapter->mbox_lock))
2550                 return -1;
2551
2552         memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2553         attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2554         attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2555                                                 &attribs_cmd.dma);
2556         if (!attribs_cmd.va) {
2557                 dev_err(&adapter->pdev->dev,
2558                                 "Memory allocation failure\n");
2559                 status = -ENOMEM;
2560                 goto err;
2561         }
2562
2563         wrb = wrb_from_mbox(adapter);
2564         if (!wrb) {
2565                 status = -EBUSY;
2566                 goto err;
2567         }
2568         req = attribs_cmd.va;
2569
2570         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2571                          OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb,
2572                         &attribs_cmd);
2573
2574         status = be_mbox_notify_wait(adapter);
2575         if (!status) {
2576                 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
2577                 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2578         }
2579
2580 err:
2581         mutex_unlock(&adapter->mbox_lock);
2582         if (attribs_cmd.va)
2583                 pci_free_consistent(adapter->pdev, attribs_cmd.size,
2584                                     attribs_cmd.va, attribs_cmd.dma);
2585         return status;
2586 }
2587
2588 /* Uses mbox */
2589 int be_cmd_req_native_mode(struct be_adapter *adapter)
2590 {
2591         struct be_mcc_wrb *wrb;
2592         struct be_cmd_req_set_func_cap *req;
2593         int status;
2594
2595         if (mutex_lock_interruptible(&adapter->mbox_lock))
2596                 return -1;
2597
2598         wrb = wrb_from_mbox(adapter);
2599         if (!wrb) {
2600                 status = -EBUSY;
2601                 goto err;
2602         }
2603
2604         req = embedded_payload(wrb);
2605
2606         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2607                 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL);
2608
2609         req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2610                                 CAPABILITY_BE3_NATIVE_ERX_API);
2611         req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2612
2613         status = be_mbox_notify_wait(adapter);
2614         if (!status) {
2615                 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2616                 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2617                                         CAPABILITY_BE3_NATIVE_ERX_API;
2618                 if (!adapter->be3_native)
2619                         dev_warn(&adapter->pdev->dev,
2620                                  "adapter not in advanced mode\n");
2621         }
2622 err:
2623         mutex_unlock(&adapter->mbox_lock);
2624         return status;
2625 }
2626
2627 /* Get privilege(s) for a function */
2628 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2629                              u32 domain)
2630 {
2631         struct be_mcc_wrb *wrb;
2632         struct be_cmd_req_get_fn_privileges *req;
2633         int status;
2634
2635         spin_lock_bh(&adapter->mcc_lock);
2636
2637         wrb = wrb_from_mccq(adapter);
2638         if (!wrb) {
2639                 status = -EBUSY;
2640                 goto err;
2641         }
2642
2643         req = embedded_payload(wrb);
2644
2645         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2646                                OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
2647                                wrb, NULL);
2648
2649         req->hdr.domain = domain;
2650
2651         status = be_mcc_notify_wait(adapter);
2652         if (!status) {
2653                 struct be_cmd_resp_get_fn_privileges *resp =
2654                                                 embedded_payload(wrb);
2655                 *privilege = le32_to_cpu(resp->privilege_mask);
2656         }
2657
2658 err:
2659         spin_unlock_bh(&adapter->mcc_lock);
2660         return status;
2661 }
2662
2663 /* Set privilege(s) for a function */
2664 int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
2665                              u32 domain)
2666 {
2667         struct be_mcc_wrb *wrb;
2668         struct be_cmd_req_set_fn_privileges *req;
2669         int status;
2670
2671         spin_lock_bh(&adapter->mcc_lock);
2672
2673         wrb = wrb_from_mccq(adapter);
2674         if (!wrb) {
2675                 status = -EBUSY;
2676                 goto err;
2677         }
2678
2679         req = embedded_payload(wrb);
2680         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2681                                OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
2682                                wrb, NULL);
2683         req->hdr.domain = domain;
2684         if (lancer_chip(adapter))
2685                 req->privileges_lancer = cpu_to_le32(privileges);
2686         else
2687                 req->privileges = cpu_to_le32(privileges);
2688
2689         status = be_mcc_notify_wait(adapter);
2690 err:
2691         spin_unlock_bh(&adapter->mcc_lock);
2692         return status;
2693 }
2694
2695 /* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
2696  * pmac_id_valid: false => pmac_id or MAC address is requested.
2697  *                If pmac_id is returned, pmac_id_valid is returned as true
2698  */
2699 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
2700                              bool *pmac_id_valid, u32 *pmac_id, u8 domain)
2701 {
2702         struct be_mcc_wrb *wrb;
2703         struct be_cmd_req_get_mac_list *req;
2704         int status;
2705         int mac_count;
2706         struct be_dma_mem get_mac_list_cmd;
2707         int i;
2708
2709         memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
2710         get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
2711         get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev,
2712                         get_mac_list_cmd.size,
2713                         &get_mac_list_cmd.dma);
2714
2715         if (!get_mac_list_cmd.va) {
2716                 dev_err(&adapter->pdev->dev,
2717                                 "Memory allocation failure during GET_MAC_LIST\n");
2718                 return -ENOMEM;
2719         }
2720
2721         spin_lock_bh(&adapter->mcc_lock);
2722
2723         wrb = wrb_from_mccq(adapter);
2724         if (!wrb) {
2725                 status = -EBUSY;
2726                 goto out;
2727         }
2728
2729         req = get_mac_list_cmd.va;
2730
2731         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2732                                OPCODE_COMMON_GET_MAC_LIST,
2733                                get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
2734         req->hdr.domain = domain;
2735         req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
2736         if (*pmac_id_valid) {
2737                 req->mac_id = cpu_to_le32(*pmac_id);
2738                 req->iface_id = cpu_to_le16(adapter->if_handle);
2739                 req->perm_override = 0;
2740         } else {
2741                 req->perm_override = 1;
2742         }
2743
2744         status = be_mcc_notify_wait(adapter);
2745         if (!status) {
2746                 struct be_cmd_resp_get_mac_list *resp =
2747                                                 get_mac_list_cmd.va;
2748
2749                 if (*pmac_id_valid) {
2750                         memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
2751                                ETH_ALEN);
2752                         goto out;
2753                 }
2754
2755                 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
2756                 /* Mac list returned could contain one or more active mac_ids
2757                  * or one or more true or pseudo permanant mac addresses.
2758                  * If an active mac_id is present, return first active mac_id
2759                  * found.
2760                  */
2761                 for (i = 0; i < mac_count; i++) {
2762                         struct get_list_macaddr *mac_entry;
2763                         u16 mac_addr_size;
2764                         u32 mac_id;
2765
2766                         mac_entry = &resp->macaddr_list[i];
2767                         mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
2768                         /* mac_id is a 32 bit value and mac_addr size
2769                          * is 6 bytes
2770                          */
2771                         if (mac_addr_size == sizeof(u32)) {
2772                                 *pmac_id_valid = true;
2773                                 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
2774                                 *pmac_id = le32_to_cpu(mac_id);
2775                                 goto out;
2776                         }
2777                 }
2778                 /* If no active mac_id found, return first mac addr */
2779                 *pmac_id_valid = false;
2780                 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
2781                                                                 ETH_ALEN);
2782         }
2783
2784 out:
2785         spin_unlock_bh(&adapter->mcc_lock);
2786         pci_free_consistent(adapter->pdev, get_mac_list_cmd.size,
2787                         get_mac_list_cmd.va, get_mac_list_cmd.dma);
2788         return status;
2789 }
2790
2791 int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id, u8 *mac)
2792 {
2793         bool active = true;
2794
2795         if (BEx_chip(adapter))
2796                 return be_cmd_mac_addr_query(adapter, mac, false,
2797                                              adapter->if_handle, curr_pmac_id);
2798         else
2799                 /* Fetch the MAC address using pmac_id */
2800                 return be_cmd_get_mac_from_list(adapter, mac, &active,
2801                                                 &curr_pmac_id, 0);
2802 }
2803
2804 int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
2805 {
2806         int status;
2807         bool pmac_valid = false;
2808
2809         memset(mac, 0, ETH_ALEN);
2810
2811         if (BEx_chip(adapter)) {
2812                 if (be_physfn(adapter))
2813                         status = be_cmd_mac_addr_query(adapter, mac, true, 0,
2814                                                        0);
2815                 else
2816                         status = be_cmd_mac_addr_query(adapter, mac, false,
2817                                                        adapter->if_handle, 0);
2818         } else {
2819                 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
2820                                                   NULL, 0);
2821         }
2822
2823         return status;
2824 }
2825
2826 /* Uses synchronous MCCQ */
2827 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
2828                         u8 mac_count, u32 domain)
2829 {
2830         struct be_mcc_wrb *wrb;
2831         struct be_cmd_req_set_mac_list *req;
2832         int status;
2833         struct be_dma_mem cmd;
2834
2835         memset(&cmd, 0, sizeof(struct be_dma_mem));
2836         cmd.size = sizeof(struct be_cmd_req_set_mac_list);
2837         cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
2838                         &cmd.dma, GFP_KERNEL);
2839         if (!cmd.va)
2840                 return -ENOMEM;
2841
2842         spin_lock_bh(&adapter->mcc_lock);
2843
2844         wrb = wrb_from_mccq(adapter);
2845         if (!wrb) {
2846                 status = -EBUSY;
2847                 goto err;
2848         }
2849
2850         req = cmd.va;
2851         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2852                                 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
2853                                 wrb, &cmd);
2854
2855         req->hdr.domain = domain;
2856         req->mac_count = mac_count;
2857         if (mac_count)
2858                 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
2859
2860         status = be_mcc_notify_wait(adapter);
2861
2862 err:
2863         dma_free_coherent(&adapter->pdev->dev, cmd.size,
2864                                 cmd.va, cmd.dma);
2865         spin_unlock_bh(&adapter->mcc_lock);
2866         return status;
2867 }
2868
2869 /* Wrapper to delete any active MACs and provision the new mac.
2870  * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
2871  * current list are active.
2872  */
2873 int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
2874 {
2875         bool active_mac = false;
2876         u8 old_mac[ETH_ALEN];
2877         u32 pmac_id;
2878         int status;
2879
2880         status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
2881                                           &pmac_id, dom);
2882         if (!status && active_mac)
2883                 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
2884
2885         return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
2886 }
2887
2888 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
2889                           u32 domain, u16 intf_id, u16 hsw_mode)
2890 {
2891         struct be_mcc_wrb *wrb;
2892         struct be_cmd_req_set_hsw_config *req;
2893         void *ctxt;
2894         int status;
2895
2896         spin_lock_bh(&adapter->mcc_lock);
2897
2898         wrb = wrb_from_mccq(adapter);
2899         if (!wrb) {
2900                 status = -EBUSY;
2901                 goto err;
2902         }
2903
2904         req = embedded_payload(wrb);
2905         ctxt = &req->context;
2906
2907         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2908                         OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2909
2910         req->hdr.domain = domain;
2911         AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
2912         if (pvid) {
2913                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
2914                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
2915         }
2916         if (!BEx_chip(adapter) && hsw_mode) {
2917                 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id,
2918                               ctxt, adapter->hba_port_num);
2919                 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1);
2920                 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type,
2921                               ctxt, hsw_mode);
2922         }
2923
2924         be_dws_cpu_to_le(req->context, sizeof(req->context));
2925         status = be_mcc_notify_wait(adapter);
2926
2927 err:
2928         spin_unlock_bh(&adapter->mcc_lock);
2929         return status;
2930 }
2931
2932 /* Get Hyper switch config */
2933 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
2934                           u32 domain, u16 intf_id, u8 *mode)
2935 {
2936         struct be_mcc_wrb *wrb;
2937         struct be_cmd_req_get_hsw_config *req;
2938         void *ctxt;
2939         int status;
2940         u16 vid;
2941
2942         spin_lock_bh(&adapter->mcc_lock);
2943
2944         wrb = wrb_from_mccq(adapter);
2945         if (!wrb) {
2946                 status = -EBUSY;
2947                 goto err;
2948         }
2949
2950         req = embedded_payload(wrb);
2951         ctxt = &req->context;
2952
2953         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2954                         OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2955
2956         req->hdr.domain = domain;
2957         AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
2958                       ctxt, intf_id);
2959         AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
2960
2961         if (!BEx_chip(adapter)) {
2962                 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
2963                               ctxt, adapter->hba_port_num);
2964                 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1);
2965         }
2966         be_dws_cpu_to_le(req->context, sizeof(req->context));
2967
2968         status = be_mcc_notify_wait(adapter);
2969         if (!status) {
2970                 struct be_cmd_resp_get_hsw_config *resp =
2971                                                 embedded_payload(wrb);
2972                 be_dws_le_to_cpu(&resp->context,
2973                                                 sizeof(resp->context));
2974                 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
2975                                                         pvid, &resp->context);
2976                 if (pvid)
2977                         *pvid = le16_to_cpu(vid);
2978                 if (mode)
2979                         *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
2980                                               port_fwd_type, &resp->context);
2981         }
2982
2983 err:
2984         spin_unlock_bh(&adapter->mcc_lock);
2985         return status;
2986 }
2987
2988 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
2989 {
2990         struct be_mcc_wrb *wrb;
2991         struct be_cmd_req_acpi_wol_magic_config_v1 *req;
2992         int status;
2993         int payload_len = sizeof(*req);
2994         struct be_dma_mem cmd;
2995
2996         if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
2997                             CMD_SUBSYSTEM_ETH))
2998                 return -EPERM;
2999
3000         if (mutex_lock_interruptible(&adapter->mbox_lock))
3001                 return -1;
3002
3003         memset(&cmd, 0, sizeof(struct be_dma_mem));
3004         cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
3005         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
3006                                                &cmd.dma);
3007         if (!cmd.va) {
3008                 dev_err(&adapter->pdev->dev,
3009                                 "Memory allocation failure\n");
3010                 status = -ENOMEM;
3011                 goto err;
3012         }
3013
3014         wrb = wrb_from_mbox(adapter);
3015         if (!wrb) {
3016                 status = -EBUSY;
3017                 goto err;
3018         }
3019
3020         req = cmd.va;
3021
3022         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
3023                                OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3024                                payload_len, wrb, &cmd);
3025
3026         req->hdr.version = 1;
3027         req->query_options = BE_GET_WOL_CAP;
3028
3029         status = be_mbox_notify_wait(adapter);
3030         if (!status) {
3031                 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
3032                 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *) cmd.va;
3033
3034                 /* the command could succeed misleadingly on old f/w
3035                  * which is not aware of the V1 version. fake an error. */
3036                 if (resp->hdr.response_length < payload_len) {
3037                         status = -1;
3038                         goto err;
3039                 }
3040                 adapter->wol_cap = resp->wol_settings;
3041         }
3042 err:
3043         mutex_unlock(&adapter->mbox_lock);
3044         if (cmd.va)
3045                 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
3046         return status;
3047
3048 }
3049 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
3050                                    struct be_dma_mem *cmd)
3051 {
3052         struct be_mcc_wrb *wrb;
3053         struct be_cmd_req_get_ext_fat_caps *req;
3054         int status;
3055
3056         if (mutex_lock_interruptible(&adapter->mbox_lock))
3057                 return -1;
3058
3059         wrb = wrb_from_mbox(adapter);
3060         if (!wrb) {
3061                 status = -EBUSY;
3062                 goto err;
3063         }
3064
3065         req = cmd->va;
3066         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3067                                OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
3068                                cmd->size, wrb, cmd);
3069         req->parameter_type = cpu_to_le32(1);
3070
3071         status = be_mbox_notify_wait(adapter);
3072 err:
3073         mutex_unlock(&adapter->mbox_lock);
3074         return status;
3075 }
3076
3077 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
3078                                    struct be_dma_mem *cmd,
3079                                    struct be_fat_conf_params *configs)
3080 {
3081         struct be_mcc_wrb *wrb;
3082         struct be_cmd_req_set_ext_fat_caps *req;
3083         int status;
3084
3085         spin_lock_bh(&adapter->mcc_lock);
3086
3087         wrb = wrb_from_mccq(adapter);
3088         if (!wrb) {
3089                 status = -EBUSY;
3090                 goto err;
3091         }
3092
3093         req = cmd->va;
3094         memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
3095         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3096                                OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
3097                                cmd->size, wrb, cmd);
3098
3099         status = be_mcc_notify_wait(adapter);
3100 err:
3101         spin_unlock_bh(&adapter->mcc_lock);
3102         return status;
3103 }
3104
3105 int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name)
3106 {
3107         struct be_mcc_wrb *wrb;
3108         struct be_cmd_req_get_port_name *req;
3109         int status;
3110
3111         if (!lancer_chip(adapter)) {
3112                 *port_name = adapter->hba_port_num + '0';
3113                 return 0;
3114         }
3115
3116         spin_lock_bh(&adapter->mcc_lock);
3117
3118         wrb = wrb_from_mccq(adapter);
3119         if (!wrb) {
3120                 status = -EBUSY;
3121                 goto err;
3122         }
3123
3124         req = embedded_payload(wrb);
3125
3126         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3127                                OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
3128                                NULL);
3129         req->hdr.version = 1;
3130
3131         status = be_mcc_notify_wait(adapter);
3132         if (!status) {
3133                 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
3134                 *port_name = resp->port_name[adapter->hba_port_num];
3135         } else {
3136                 *port_name = adapter->hba_port_num + '0';
3137         }
3138 err:
3139         spin_unlock_bh(&adapter->mcc_lock);
3140         return status;
3141 }
3142
3143 static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count)
3144 {
3145         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3146         int i;
3147
3148         for (i = 0; i < desc_count; i++) {
3149                 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
3150                     hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1)
3151                         return (struct be_nic_res_desc *)hdr;
3152
3153                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3154                 hdr = (void *)hdr + hdr->desc_len;
3155         }
3156         return NULL;
3157 }
3158
3159 static struct be_pcie_res_desc *be_get_pcie_desc(u8 devfn, u8 *buf,
3160                                                  u32 desc_count)
3161 {
3162         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3163         struct be_pcie_res_desc *pcie;
3164         int i;
3165
3166         for (i = 0; i < desc_count; i++) {
3167                 if ((hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
3168                      hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1)) {
3169                         pcie = (struct be_pcie_res_desc *)hdr;
3170                         if (pcie->pf_num == devfn)
3171                                 return pcie;
3172                 }
3173
3174                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3175                 hdr = (void *)hdr + hdr->desc_len;
3176         }
3177         return NULL;
3178 }
3179
3180 static void be_copy_nic_desc(struct be_resources *res,
3181                              struct be_nic_res_desc *desc)
3182 {
3183         res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count);
3184         res->max_vlans = le16_to_cpu(desc->vlan_count);
3185         res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
3186         res->max_tx_qs = le16_to_cpu(desc->txq_count);
3187         res->max_rss_qs = le16_to_cpu(desc->rssq_count);
3188         res->max_rx_qs = le16_to_cpu(desc->rq_count);
3189         res->max_evt_qs = le16_to_cpu(desc->eq_count);
3190         /* Clear flags that driver is not interested in */
3191         res->if_cap_flags = le32_to_cpu(desc->cap_flags) &
3192                                 BE_IF_CAP_FLAGS_WANT;
3193         /* Need 1 RXQ as the default RXQ */
3194         if (res->max_rss_qs && res->max_rss_qs == res->max_rx_qs)
3195                 res->max_rss_qs -= 1;
3196 }
3197
3198 /* Uses Mbox */
3199 int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res)
3200 {
3201         struct be_mcc_wrb *wrb;
3202         struct be_cmd_req_get_func_config *req;
3203         int status;
3204         struct be_dma_mem cmd;
3205
3206         if (mutex_lock_interruptible(&adapter->mbox_lock))
3207                 return -1;
3208
3209         memset(&cmd, 0, sizeof(struct be_dma_mem));
3210         cmd.size = sizeof(struct be_cmd_resp_get_func_config);
3211         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
3212                                       &cmd.dma);
3213         if (!cmd.va) {
3214                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3215                 status = -ENOMEM;
3216                 goto err;
3217         }
3218
3219         wrb = wrb_from_mbox(adapter);
3220         if (!wrb) {
3221                 status = -EBUSY;
3222                 goto err;
3223         }
3224
3225         req = cmd.va;
3226
3227         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3228                                OPCODE_COMMON_GET_FUNC_CONFIG,
3229                                cmd.size, wrb, &cmd);
3230
3231         if (skyhawk_chip(adapter))
3232                 req->hdr.version = 1;
3233
3234         status = be_mbox_notify_wait(adapter);
3235         if (!status) {
3236                 struct be_cmd_resp_get_func_config *resp = cmd.va;
3237                 u32 desc_count = le32_to_cpu(resp->desc_count);
3238                 struct be_nic_res_desc *desc;
3239
3240                 desc = be_get_nic_desc(resp->func_param, desc_count);
3241                 if (!desc) {
3242                         status = -EINVAL;
3243                         goto err;
3244                 }
3245
3246                 adapter->pf_number = desc->pf_num;
3247                 be_copy_nic_desc(res, desc);
3248         }
3249 err:
3250         mutex_unlock(&adapter->mbox_lock);
3251         if (cmd.va)
3252                 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
3253         return status;
3254 }
3255
3256 /* Uses mbox */
3257 static int be_cmd_get_profile_config_mbox(struct be_adapter *adapter,
3258                                         u8 domain, struct be_dma_mem *cmd)
3259 {
3260         struct be_mcc_wrb *wrb;
3261         struct be_cmd_req_get_profile_config *req;
3262         int status;
3263
3264         if (mutex_lock_interruptible(&adapter->mbox_lock))
3265                 return -1;
3266         wrb = wrb_from_mbox(adapter);
3267
3268         req = cmd->va;
3269         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3270                                OPCODE_COMMON_GET_PROFILE_CONFIG,
3271                                cmd->size, wrb, cmd);
3272
3273         req->type = ACTIVE_PROFILE_TYPE;
3274         req->hdr.domain = domain;
3275         if (!lancer_chip(adapter))
3276                 req->hdr.version = 1;
3277
3278         status = be_mbox_notify_wait(adapter);
3279
3280         mutex_unlock(&adapter->mbox_lock);
3281         return status;
3282 }
3283
3284 /* Uses sync mcc */
3285 static int be_cmd_get_profile_config_mccq(struct be_adapter *adapter,
3286                                         u8 domain, struct be_dma_mem *cmd)
3287 {
3288         struct be_mcc_wrb *wrb;
3289         struct be_cmd_req_get_profile_config *req;
3290         int status;
3291
3292         spin_lock_bh(&adapter->mcc_lock);
3293
3294         wrb = wrb_from_mccq(adapter);
3295         if (!wrb) {
3296                 status = -EBUSY;
3297                 goto err;
3298         }
3299
3300         req = cmd->va;
3301         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3302                                OPCODE_COMMON_GET_PROFILE_CONFIG,
3303                                cmd->size, wrb, cmd);
3304
3305         req->type = ACTIVE_PROFILE_TYPE;
3306         req->hdr.domain = domain;
3307         if (!lancer_chip(adapter))
3308                 req->hdr.version = 1;
3309
3310         status = be_mcc_notify_wait(adapter);
3311
3312 err:
3313         spin_unlock_bh(&adapter->mcc_lock);
3314         return status;
3315 }
3316
3317 /* Uses sync mcc, if MCCQ is already created otherwise mbox */
3318 int be_cmd_get_profile_config(struct be_adapter *adapter,
3319                               struct be_resources *res, u8 domain)
3320 {
3321         struct be_cmd_resp_get_profile_config *resp;
3322         struct be_pcie_res_desc *pcie;
3323         struct be_nic_res_desc *nic;
3324         struct be_queue_info *mccq = &adapter->mcc_obj.q;
3325         struct be_dma_mem cmd;
3326         u32 desc_count;
3327         int status;
3328
3329         memset(&cmd, 0, sizeof(struct be_dma_mem));
3330         cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
3331         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
3332         if (!cmd.va)
3333                 return -ENOMEM;
3334
3335         if (!mccq->created)
3336                 status = be_cmd_get_profile_config_mbox(adapter, domain, &cmd);
3337         else
3338                 status = be_cmd_get_profile_config_mccq(adapter, domain, &cmd);
3339         if (status)
3340                 goto err;
3341
3342         resp = cmd.va;
3343         desc_count = le32_to_cpu(resp->desc_count);
3344
3345         pcie =  be_get_pcie_desc(adapter->pdev->devfn, resp->func_param,
3346                                  desc_count);
3347         if (pcie)
3348                 res->max_vfs = le16_to_cpu(pcie->num_vfs);
3349
3350         nic = be_get_nic_desc(resp->func_param, desc_count);
3351         if (nic)
3352                 be_copy_nic_desc(res, nic);
3353
3354 err:
3355         if (cmd.va)
3356                 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
3357         return status;
3358 }
3359
3360 /* Currently only Lancer uses this command and it supports version 0 only
3361  * Uses sync mcc
3362  */
3363 int be_cmd_set_profile_config(struct be_adapter *adapter, u32 bps,
3364                               u8 domain)
3365 {
3366         struct be_mcc_wrb *wrb;
3367         struct be_cmd_req_set_profile_config *req;
3368         int status;
3369
3370         spin_lock_bh(&adapter->mcc_lock);
3371
3372         wrb = wrb_from_mccq(adapter);
3373         if (!wrb) {
3374                 status = -EBUSY;
3375                 goto err;
3376         }
3377
3378         req = embedded_payload(wrb);
3379
3380         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3381                                OPCODE_COMMON_SET_PROFILE_CONFIG, sizeof(*req),
3382                                wrb, NULL);
3383         req->hdr.domain = domain;
3384         req->desc_count = cpu_to_le32(1);
3385         req->nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
3386         req->nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
3387         req->nic_desc.flags = (1 << QUN) | (1 << IMM) | (1 << NOSV);
3388         req->nic_desc.pf_num = adapter->pf_number;
3389         req->nic_desc.vf_num = domain;
3390
3391         /* Mark fields invalid */
3392         req->nic_desc.unicast_mac_count = 0xFFFF;
3393         req->nic_desc.mcc_count = 0xFFFF;
3394         req->nic_desc.vlan_count = 0xFFFF;
3395         req->nic_desc.mcast_mac_count = 0xFFFF;
3396         req->nic_desc.txq_count = 0xFFFF;
3397         req->nic_desc.rq_count = 0xFFFF;
3398         req->nic_desc.rssq_count = 0xFFFF;
3399         req->nic_desc.lro_count = 0xFFFF;
3400         req->nic_desc.cq_count = 0xFFFF;
3401         req->nic_desc.toe_conn_count = 0xFFFF;
3402         req->nic_desc.eq_count = 0xFFFF;
3403         req->nic_desc.link_param = 0xFF;
3404         req->nic_desc.bw_min = 0xFFFFFFFF;
3405         req->nic_desc.acpi_params = 0xFF;
3406         req->nic_desc.wol_param = 0x0F;
3407
3408         /* Change BW */
3409         req->nic_desc.bw_min = cpu_to_le32(bps);
3410         req->nic_desc.bw_max = cpu_to_le32(bps);
3411         status = be_mcc_notify_wait(adapter);
3412 err:
3413         spin_unlock_bh(&adapter->mcc_lock);
3414         return status;
3415 }
3416
3417 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
3418                      int vf_num)
3419 {
3420         struct be_mcc_wrb *wrb;
3421         struct be_cmd_req_get_iface_list *req;
3422         struct be_cmd_resp_get_iface_list *resp;
3423         int status;
3424
3425         spin_lock_bh(&adapter->mcc_lock);
3426
3427         wrb = wrb_from_mccq(adapter);
3428         if (!wrb) {
3429                 status = -EBUSY;
3430                 goto err;
3431         }
3432         req = embedded_payload(wrb);
3433
3434         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3435                                OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
3436                                wrb, NULL);
3437         req->hdr.domain = vf_num + 1;
3438
3439         status = be_mcc_notify_wait(adapter);
3440         if (!status) {
3441                 resp = (struct be_cmd_resp_get_iface_list *)req;
3442                 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
3443         }
3444
3445 err:
3446         spin_unlock_bh(&adapter->mcc_lock);
3447         return status;
3448 }
3449
3450 static int lancer_wait_idle(struct be_adapter *adapter)
3451 {
3452 #define SLIPORT_IDLE_TIMEOUT 30
3453         u32 reg_val;
3454         int status = 0, i;
3455
3456         for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
3457                 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
3458                 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
3459                         break;
3460
3461                 ssleep(1);
3462         }
3463
3464         if (i == SLIPORT_IDLE_TIMEOUT)
3465                 status = -1;
3466
3467         return status;
3468 }
3469
3470 int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
3471 {
3472         int status = 0;
3473
3474         status = lancer_wait_idle(adapter);
3475         if (status)
3476                 return status;
3477
3478         iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
3479
3480         return status;
3481 }
3482
3483 /* Routine to check whether dump image is present or not */
3484 bool dump_present(struct be_adapter *adapter)
3485 {
3486         u32 sliport_status = 0;
3487
3488         sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
3489         return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
3490 }
3491
3492 int lancer_initiate_dump(struct be_adapter *adapter)
3493 {
3494         int status;
3495
3496         /* give firmware reset and diagnostic dump */
3497         status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
3498                                      PHYSDEV_CONTROL_DD_MASK);
3499         if (status < 0) {
3500                 dev_err(&adapter->pdev->dev, "Firmware reset failed\n");
3501                 return status;
3502         }
3503
3504         status = lancer_wait_idle(adapter);
3505         if (status)
3506                 return status;
3507
3508         if (!dump_present(adapter)) {
3509                 dev_err(&adapter->pdev->dev, "Dump image not present\n");
3510                 return -1;
3511         }
3512
3513         return 0;
3514 }
3515
3516 /* Uses sync mcc */
3517 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
3518 {
3519         struct be_mcc_wrb *wrb;
3520         struct be_cmd_enable_disable_vf *req;
3521         int status;
3522
3523         if (!lancer_chip(adapter))
3524                 return 0;
3525
3526         spin_lock_bh(&adapter->mcc_lock);
3527
3528         wrb = wrb_from_mccq(adapter);
3529         if (!wrb) {
3530                 status = -EBUSY;
3531                 goto err;
3532         }
3533
3534         req = embedded_payload(wrb);
3535
3536         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3537                                OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
3538                                wrb, NULL);
3539
3540         req->hdr.domain = domain;
3541         req->enable = 1;
3542         status = be_mcc_notify_wait(adapter);
3543 err:
3544         spin_unlock_bh(&adapter->mcc_lock);
3545         return status;
3546 }
3547
3548 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
3549 {
3550         struct be_mcc_wrb *wrb;
3551         struct be_cmd_req_intr_set *req;
3552         int status;
3553
3554         if (mutex_lock_interruptible(&adapter->mbox_lock))
3555                 return -1;
3556
3557         wrb = wrb_from_mbox(adapter);
3558
3559         req = embedded_payload(wrb);
3560
3561         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3562                                OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
3563                                wrb, NULL);
3564
3565         req->intr_enabled = intr_enable;
3566
3567         status = be_mbox_notify_wait(adapter);
3568
3569         mutex_unlock(&adapter->mbox_lock);
3570         return status;
3571 }
3572
3573 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
3574                         int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
3575 {
3576         struct be_adapter *adapter = netdev_priv(netdev_handle);
3577         struct be_mcc_wrb *wrb;
3578         struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *) wrb_payload;
3579         struct be_cmd_req_hdr *req;
3580         struct be_cmd_resp_hdr *resp;
3581         int status;
3582
3583         spin_lock_bh(&adapter->mcc_lock);
3584
3585         wrb = wrb_from_mccq(adapter);
3586         if (!wrb) {
3587                 status = -EBUSY;
3588                 goto err;
3589         }
3590         req = embedded_payload(wrb);
3591         resp = embedded_payload(wrb);
3592
3593         be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
3594                                hdr->opcode, wrb_payload_size, wrb, NULL);
3595         memcpy(req, wrb_payload, wrb_payload_size);
3596         be_dws_cpu_to_le(req, wrb_payload_size);
3597
3598         status = be_mcc_notify_wait(adapter);
3599         if (cmd_status)
3600                 *cmd_status = (status & 0xffff);
3601         if (ext_status)
3602                 *ext_status = 0;
3603         memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
3604         be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
3605 err:
3606         spin_unlock_bh(&adapter->mcc_lock);
3607         return status;
3608 }
3609 EXPORT_SYMBOL(be_roce_mcc_cmd);