drivers/net/ethernet/emulex/benet/be_cmds.c

   1 /*
   2  * Copyright (C) 2005 - 2015 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 #include <linux/module.h>
  19 #include "be.h"
  20 #include "be_cmds.h"
  21
  22 static char *be_port_misconfig_evt_desc[] = {
  23         "A valid SFP module detected",
  24         "Optics faulted/ incorrectly installed/ not installed.",
  25         "Optics of two types installed.",
  26         "Incompatible optics.",
  27         "Unknown port SFP status"
  28 };
  29
  30 static char *be_port_misconfig_remedy_desc[] = {
  31         "",
  32         "Reseat optics. If issue not resolved, replace",
  33         "Remove one optic or install matching pair of optics",
  34         "Replace with compatible optics for card to function",
  35         ""
  36 };
  37
  38 static struct be_cmd_priv_map cmd_priv_map[] = {
  39         {
  40                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
  41                 CMD_SUBSYSTEM_ETH,
  42                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  43                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  44         },
  45         {
  46                 OPCODE_COMMON_GET_FLOW_CONTROL,
  47                 CMD_SUBSYSTEM_COMMON,
  48                 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
  49                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  50         },
  51         {
  52                 OPCODE_COMMON_SET_FLOW_CONTROL,
  53                 CMD_SUBSYSTEM_COMMON,
  54                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  55                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  56         },
  57         {
  58                 OPCODE_ETH_GET_PPORT_STATS,
  59                 CMD_SUBSYSTEM_ETH,
  60                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  61                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  62         },
  63         {
  64                 OPCODE_COMMON_GET_PHY_DETAILS,
  65                 CMD_SUBSYSTEM_COMMON,
  66                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  67                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  68         }
  69 };
  70
  71 static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, u8 subsystem)
  72 {
  73         int i;
  74         int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
  75         u32 cmd_privileges = adapter->cmd_privileges;
  76
  77         for (i = 0; i < num_entries; i++)
  78                 if (opcode == cmd_priv_map[i].opcode &&
  79                     subsystem == cmd_priv_map[i].subsystem)
  80                         if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
  81                                 return false;
  82
  83         return true;
  84 }
  85
  86 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
  87 {
  88         return wrb->payload.embedded_payload;
  89 }
  90
  91 static int be_mcc_notify(struct be_adapter *adapter)
  92 {
  93         struct be_queue_info *mccq = &adapter->mcc_obj.q;
  94         u32 val = 0;
  95
  96         if (be_check_error(adapter, BE_ERROR_ANY))
  97                 return -EIO;
  98
  99         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
 100         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
 101
 102         wmb();
 103         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
 104
 105         return 0;
 106 }
 107
 108 /* To check if valid bit is set, check the entire word as we don't know
 109  * the endianness of the data (old entry is host endian while a new entry is
 110  * little endian) */
 111 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
 112 {
 113         u32 flags;
 114
 115         if (compl->flags != 0) {
 116                 flags = le32_to_cpu(compl->flags);
 117                 if (flags & CQE_FLAGS_VALID_MASK) {
 118                         compl->flags = flags;
 119                         return true;
 120                 }
 121         }
 122         return false;
 123 }
 124
 125 /* Need to reset the entire word that houses the valid bit */
 126 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
 127 {
 128         compl->flags = 0;
 129 }
 130
 131 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
 132 {
 133         unsigned long addr;
 134
 135         addr = tag1;
 136         addr = ((addr << 16) << 16) | tag0;
 137         return (void *)addr;
 138 }
 139
 140 static bool be_skip_err_log(u8 opcode, u16 base_status, u16 addl_status)
 141 {
 142         if (base_status == MCC_STATUS_NOT_SUPPORTED ||
 143             base_status == MCC_STATUS_ILLEGAL_REQUEST ||
 144             addl_status == MCC_ADDL_STATUS_TOO_MANY_INTERFACES ||
 145             addl_status == MCC_ADDL_STATUS_INSUFFICIENT_VLANS ||
 146             (opcode == OPCODE_COMMON_WRITE_FLASHROM &&
 147             (base_status == MCC_STATUS_ILLEGAL_FIELD ||
 148              addl_status == MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH)))
 149                 return true;
 150         else
 151                 return false;
 152 }
 153
 154 /* Place holder for all the async MCC cmds wherein the caller is not in a busy
 155  * loop (has not issued be_mcc_notify_wait())
 156  */
 157 static void be_async_cmd_process(struct be_adapter *adapter,
 158                                  struct be_mcc_compl *compl,
 159                                  struct be_cmd_resp_hdr *resp_hdr)
 160 {
 161         enum mcc_base_status base_status = base_status(compl->status);
 162         u8 opcode = 0, subsystem = 0;
 163
 164         if (resp_hdr) {
 165                 opcode = resp_hdr->opcode;
 166                 subsystem = resp_hdr->subsystem;
 167         }
 168
 169         if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST &&
 170             subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
 171                 complete(&adapter->et_cmd_compl);
 172                 return;
 173         }
 174
 175         if (opcode == OPCODE_LOWLEVEL_SET_LOOPBACK_MODE &&
 176             subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
 177                 complete(&adapter->et_cmd_compl);
 178                 return;
 179         }
 180
 181         if ((opcode == OPCODE_COMMON_WRITE_FLASHROM ||
 182              opcode == OPCODE_COMMON_WRITE_OBJECT) &&
 183             subsystem == CMD_SUBSYSTEM_COMMON) {
 184                 adapter->flash_status = compl->status;
 185                 complete(&adapter->et_cmd_compl);
 186                 return;
 187         }
 188
 189         if ((opcode == OPCODE_ETH_GET_STATISTICS ||
 190              opcode == OPCODE_ETH_GET_PPORT_STATS) &&
 191             subsystem == CMD_SUBSYSTEM_ETH &&
 192             base_status == MCC_STATUS_SUCCESS) {
 193                 be_parse_stats(adapter);
 194                 adapter->stats_cmd_sent = false;
 195                 return;
 196         }
 197
 198         if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
 199             subsystem == CMD_SUBSYSTEM_COMMON) {
 200                 if (base_status == MCC_STATUS_SUCCESS) {
 201                         struct be_cmd_resp_get_cntl_addnl_attribs *resp =
 202                                                         (void *)resp_hdr;
 203                         adapter->hwmon_info.be_on_die_temp =
 204                                                 resp->on_die_temperature;
 205                 } else {
 206                         adapter->be_get_temp_freq = 0;
 207                         adapter->hwmon_info.be_on_die_temp =
 208                                                 BE_INVALID_DIE_TEMP;
 209                 }
 210                 return;
 211         }
 212 }
 213
 214 static int be_mcc_compl_process(struct be_adapter *adapter,
 215                                 struct be_mcc_compl *compl)
 216 {
 217         enum mcc_base_status base_status;
 218         enum mcc_addl_status addl_status;
 219         struct be_cmd_resp_hdr *resp_hdr;
 220         u8 opcode = 0, subsystem = 0;
 221
 222         /* Just swap the status to host endian; mcc tag is opaquely copied
 223          * from mcc_wrb */
 224         be_dws_le_to_cpu(compl, 4);
 225
 226         base_status = base_status(compl->status);
 227         addl_status = addl_status(compl->status);
 228
 229         resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
 230         if (resp_hdr) {
 231                 opcode = resp_hdr->opcode;
 232                 subsystem = resp_hdr->subsystem;
 233         }
 234
 235         be_async_cmd_process(adapter, compl, resp_hdr);
 236
 237         if (base_status != MCC_STATUS_SUCCESS &&
 238             !be_skip_err_log(opcode, base_status, addl_status)) {
 239                 if (base_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
 240                         dev_warn(&adapter->pdev->dev,
 241                                  "VF is not privileged to issue opcode %d-%d\n",
 242                                  opcode, subsystem);
 243                 } else {
 244                         dev_err(&adapter->pdev->dev,
 245                                 "opcode %d-%d failed:status %d-%d\n",
 246                                 opcode, subsystem, base_status, addl_status);
 247                 }
 248         }
 249         return compl->status;
 250 }
 251
 252 /* Link state evt is a string of bytes; no need for endian swapping */
 253 static void be_async_link_state_process(struct be_adapter *adapter,
 254                                         struct be_mcc_compl *compl)
 255 {
 256         struct be_async_event_link_state *evt =
 257                         (struct be_async_event_link_state *)compl;
 258
 259         /* When link status changes, link speed must be re-queried from FW */
 260         adapter->phy.link_speed = -1;
 261
 262         /* On BEx the FW does not send a separate link status
 263          * notification for physical and logical link.
 264          * On other chips just process the logical link
 265          * status notification
 266          */
 267         if (!BEx_chip(adapter) &&
 268             !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
 269                 return;
 270
 271         /* For the initial link status do not rely on the ASYNC event as
 272          * it may not be received in some cases.
 273          */
 274         if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
 275                 be_link_status_update(adapter,
 276                                       evt->port_link_status & LINK_STATUS_MASK);
 277 }
 278
 279 static void be_async_port_misconfig_event_process(struct be_adapter *adapter,
 280                                                   struct be_mcc_compl *compl)
 281 {
 282         struct be_async_event_misconfig_port *evt =
 283                         (struct be_async_event_misconfig_port *)compl;
 284         u32 sfp_mismatch_evt = le32_to_cpu(evt->event_data_word1);
 285         struct device *dev = &adapter->pdev->dev;
 286         u8 port_misconfig_evt;
 287
 288         port_misconfig_evt =
 289                 ((sfp_mismatch_evt >> (adapter->hba_port_num * 8)) & 0xff);
 290
 291         /* Log an error message that would allow a user to determine
 292          * whether the SFPs have an issue
 293          */
 294         dev_info(dev, "Port %c: %s %s", adapter->port_name,
 295                  be_port_misconfig_evt_desc[port_misconfig_evt],
 296                  be_port_misconfig_remedy_desc[port_misconfig_evt]);
 297
 298         if (port_misconfig_evt == INCOMPATIBLE_SFP)
 299                 adapter->flags |= BE_FLAGS_EVT_INCOMPATIBLE_SFP;
 300 }
 301
 302 /* Grp5 CoS Priority evt */
 303 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
 304                                                struct be_mcc_compl *compl)
 305 {
 306         struct be_async_event_grp5_cos_priority *evt =
 307                         (struct be_async_event_grp5_cos_priority *)compl;
 308
 309         if (evt->valid) {
 310                 adapter->vlan_prio_bmap = evt->available_priority_bmap;
 311                 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
 312                 adapter->recommended_prio =
 313                         evt->reco_default_priority << VLAN_PRIO_SHIFT;
 314         }
 315 }
 316
 317 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
 318 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
 319                                             struct be_mcc_compl *compl)
 320 {
 321         struct be_async_event_grp5_qos_link_speed *evt =
 322                         (struct be_async_event_grp5_qos_link_speed *)compl;
 323
 324         if (adapter->phy.link_speed >= 0 &&
 325             evt->physical_port == adapter->port_num)
 326                 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
 327 }
 328
 329 /*Grp5 PVID evt*/
 330 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
 331                                              struct be_mcc_compl *compl)
 332 {
 333         struct be_async_event_grp5_pvid_state *evt =
 334                         (struct be_async_event_grp5_pvid_state *)compl;
 335
 336         if (evt->enabled) {
 337                 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
 338                 dev_info(&adapter->pdev->dev, "LPVID: %d\n", adapter->pvid);
 339         } else {
 340                 adapter->pvid = 0;
 341         }
 342 }
 343
 344 #define MGMT_ENABLE_MASK        0x4
 345 static void be_async_grp5_fw_control_process(struct be_adapter *adapter,
 346                                              struct be_mcc_compl *compl)
 347 {
 348         struct be_async_fw_control *evt = (struct be_async_fw_control *)compl;
 349         u32 evt_dw1 = le32_to_cpu(evt->event_data_word1);
 350
 351         if (evt_dw1 & MGMT_ENABLE_MASK) {
 352                 adapter->flags |= BE_FLAGS_OS2BMC;
 353                 adapter->bmc_filt_mask = le32_to_cpu(evt->event_data_word2);
 354         } else {
 355                 adapter->flags &= ~BE_FLAGS_OS2BMC;
 356         }
 357 }
 358
 359 static void be_async_grp5_evt_process(struct be_adapter *adapter,
 360                                       struct be_mcc_compl *compl)
 361 {
 362         u8 event_type = (compl->flags >> ASYNC_EVENT_TYPE_SHIFT) &
 363                                 ASYNC_EVENT_TYPE_MASK;
 364
 365         switch (event_type) {
 366         case ASYNC_EVENT_COS_PRIORITY:
 367                 be_async_grp5_cos_priority_process(adapter, compl);
 368                 break;
 369         case ASYNC_EVENT_QOS_SPEED:
 370                 be_async_grp5_qos_speed_process(adapter, compl);
 371                 break;
 372         case ASYNC_EVENT_PVID_STATE:
 373                 be_async_grp5_pvid_state_process(adapter, compl);
 374                 break;
 375         /* Async event to disable/enable os2bmc and/or mac-learning */
 376         case ASYNC_EVENT_FW_CONTROL:
 377                 be_async_grp5_fw_control_process(adapter, compl);
 378                 break;
 379         default:
 380                 break;
 381         }
 382 }
 383
 384 static void be_async_dbg_evt_process(struct be_adapter *adapter,
 385                                      struct be_mcc_compl *cmp)
 386 {
 387         u8 event_type = 0;
 388         struct be_async_event_qnq *evt = (struct be_async_event_qnq *)cmp;
 389
 390         event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
 391                         ASYNC_EVENT_TYPE_MASK;
 392
 393         switch (event_type) {
 394         case ASYNC_DEBUG_EVENT_TYPE_QNQ:
 395                 if (evt->valid)
 396                         adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
 397                 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
 398         break;
 399         default:
 400                 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
 401                          event_type);
 402         break;
 403         }
 404 }
 405
 406 static void be_async_sliport_evt_process(struct be_adapter *adapter,
 407                                          struct be_mcc_compl *cmp)
 408 {
 409         u8 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
 410                         ASYNC_EVENT_TYPE_MASK;
 411
 412         if (event_type == ASYNC_EVENT_PORT_MISCONFIG)
 413                 be_async_port_misconfig_event_process(adapter, cmp);
 414 }
 415
 416 static inline bool is_link_state_evt(u32 flags)
 417 {
 418         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 419                         ASYNC_EVENT_CODE_LINK_STATE;
 420 }
 421
 422 static inline bool is_grp5_evt(u32 flags)
 423 {
 424         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 425                         ASYNC_EVENT_CODE_GRP_5;
 426 }
 427
 428 static inline bool is_dbg_evt(u32 flags)
 429 {
 430         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 431                         ASYNC_EVENT_CODE_QNQ;
 432 }
 433
 434 static inline bool is_sliport_evt(u32 flags)
 435 {
 436         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 437                 ASYNC_EVENT_CODE_SLIPORT;
 438 }
 439
 440 static void be_mcc_event_process(struct be_adapter *adapter,
 441                                  struct be_mcc_compl *compl)
 442 {
 443         if (is_link_state_evt(compl->flags))
 444                 be_async_link_state_process(adapter, compl);
 445         else if (is_grp5_evt(compl->flags))
 446                 be_async_grp5_evt_process(adapter, compl);
 447         else if (is_dbg_evt(compl->flags))
 448                 be_async_dbg_evt_process(adapter, compl);
 449         else if (is_sliport_evt(compl->flags))
 450                 be_async_sliport_evt_process(adapter, compl);
 451 }
 452
 453 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
 454 {
 455         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
 456         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
 457
 458         if (be_mcc_compl_is_new(compl)) {
 459                 queue_tail_inc(mcc_cq);
 460                 return compl;
 461         }
 462         return NULL;
 463 }
 464
 465 void be_async_mcc_enable(struct be_adapter *adapter)
 466 {
 467         spin_lock_bh(&adapter->mcc_cq_lock);
 468
 469         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
 470         adapter->mcc_obj.rearm_cq = true;
 471
 472         spin_unlock_bh(&adapter->mcc_cq_lock);
 473 }
 474
 475 void be_async_mcc_disable(struct be_adapter *adapter)
 476 {
 477         spin_lock_bh(&adapter->mcc_cq_lock);
 478
 479         adapter->mcc_obj.rearm_cq = false;
 480         be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
 481
 482         spin_unlock_bh(&adapter->mcc_cq_lock);
 483 }
 484
 485 int be_process_mcc(struct be_adapter *adapter)
 486 {
 487         struct be_mcc_compl *compl;
 488         int num = 0, status = 0;
 489         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 490
 491         spin_lock(&adapter->mcc_cq_lock);
 492
 493         while ((compl = be_mcc_compl_get(adapter))) {
 494                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 495                         be_mcc_event_process(adapter, compl);
 496                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
 497                         status = be_mcc_compl_process(adapter, compl);
 498                         atomic_dec(&mcc_obj->q.used);
 499                 }
 500                 be_mcc_compl_use(compl);
 501                 num++;
 502         }
 503
 504         if (num)
 505                 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
 506
 507         spin_unlock(&adapter->mcc_cq_lock);
 508         return status;
 509 }
 510
 511 /* Wait till no more pending mcc requests are present */
 512 static int be_mcc_wait_compl(struct be_adapter *adapter)
 513 {
 514 #define mcc_timeout             120000 /* 12s timeout */
 515         int i, status = 0;
 516         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 517
 518         for (i = 0; i < mcc_timeout; i++) {
 519                 if (be_check_error(adapter, BE_ERROR_ANY))
 520                         return -EIO;
 521
 522                 local_bh_disable();
 523                 status = be_process_mcc(adapter);
 524                 local_bh_enable();
 525
 526                 if (atomic_read(&mcc_obj->q.used) == 0)
 527                         break;
 528                 udelay(100);
 529         }
 530         if (i == mcc_timeout) {
 531                 dev_err(&adapter->pdev->dev, "FW not responding\n");
 532                 be_set_error(adapter, BE_ERROR_FW);
 533                 return -EIO;
 534         }
 535         return status;
 536 }
 537
 538 /* Notify MCC requests and wait for completion */
 539 static int be_mcc_notify_wait(struct be_adapter *adapter)
 540 {
 541         int status;
 542         struct be_mcc_wrb *wrb;
 543         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 544         u16 index = mcc_obj->q.head;
 545         struct be_cmd_resp_hdr *resp;
 546
 547         index_dec(&index, mcc_obj->q.len);
 548         wrb = queue_index_node(&mcc_obj->q, index);
 549
 550         resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
 551
 552         status = be_mcc_notify(adapter);
 553         if (status)
 554                 goto out;
 555
 556         status = be_mcc_wait_compl(adapter);
 557         if (status == -EIO)
 558                 goto out;
 559
 560         status = (resp->base_status |
 561                   ((resp->addl_status & CQE_ADDL_STATUS_MASK) <<
 562                    CQE_ADDL_STATUS_SHIFT));
 563 out:
 564         return status;
 565 }
 566
 567 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 568 {
 569         int msecs = 0;
 570         u32 ready;
 571
 572         do {
 573                 if (be_check_error(adapter, BE_ERROR_ANY))
 574                         return -EIO;
 575
 576                 ready = ioread32(db);
 577                 if (ready == 0xffffffff)
 578                         return -1;
 579
 580                 ready &= MPU_MAILBOX_DB_RDY_MASK;
 581                 if (ready)
 582                         break;
 583
 584                 if (msecs > 4000) {
 585                         dev_err(&adapter->pdev->dev, "FW not responding\n");
 586                         be_set_error(adapter, BE_ERROR_FW);
 587                         be_detect_error(adapter);
 588                         return -1;
 589                 }
 590
 591                 msleep(1);
 592                 msecs++;
 593         } while (true);
 594
 595         return 0;
 596 }
 597
 598 /*
 599  * Insert the mailbox address into the doorbell in two steps
 600  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 601  */
 602 static int be_mbox_notify_wait(struct be_adapter *adapter)
 603 {
 604         int status;
 605         u32 val = 0;
 606         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 607         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 608         struct be_mcc_mailbox *mbox = mbox_mem->va;
 609         struct be_mcc_compl *compl = &mbox->compl;
 610
 611         /* wait for ready to be set */
 612         status = be_mbox_db_ready_wait(adapter, db);
 613         if (status != 0)
 614                 return status;
 615
 616         val |= MPU_MAILBOX_DB_HI_MASK;
 617         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 618         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 619         iowrite32(val, db);
 620
 621         /* wait for ready to be set */
 622         status = be_mbox_db_ready_wait(adapter, db);
 623         if (status != 0)
 624                 return status;
 625
 626         val = 0;
 627         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 628         val |= (u32)(mbox_mem->dma >> 4) << 2;
 629         iowrite32(val, db);
 630
 631         status = be_mbox_db_ready_wait(adapter, db);
 632         if (status != 0)
 633                 return status;
 634
 635         /* A cq entry has been made now */
 636         if (be_mcc_compl_is_new(compl)) {
 637                 status = be_mcc_compl_process(adapter, &mbox->compl);
 638                 be_mcc_compl_use(compl);
 639                 if (status)
 640                         return status;
 641         } else {
 642                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 643                 return -1;
 644         }
 645         return 0;
 646 }
 647
 648 static u16 be_POST_stage_get(struct be_adapter *adapter)
 649 {
 650         u32 sem;
 651
 652         if (BEx_chip(adapter))
 653                 sem  = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
 654         else
 655                 pci_read_config_dword(adapter->pdev,
 656                                       SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
 657
 658         return sem & POST_STAGE_MASK;
 659 }
 660
 661 static int lancer_wait_ready(struct be_adapter *adapter)
 662 {
 663 #define SLIPORT_READY_TIMEOUT 30
 664         u32 sliport_status;
 665         int i;
 666
 667         for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
 668                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 669                 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
 670                         return 0;
 671
 672                 if (sliport_status & SLIPORT_STATUS_ERR_MASK &&
 673                     !(sliport_status & SLIPORT_STATUS_RN_MASK))
 674                         return -EIO;
 675
 676                 msleep(1000);
 677         }
 678
 679         return sliport_status ? : -1;
 680 }
 681
 682 int be_fw_wait_ready(struct be_adapter *adapter)
 683 {
 684         u16 stage;
 685         int status, timeout = 0;
 686         struct device *dev = &adapter->pdev->dev;
 687
 688         if (lancer_chip(adapter)) {
 689                 status = lancer_wait_ready(adapter);
 690                 if (status) {
 691                         stage = status;
 692                         goto err;
 693                 }
 694                 return 0;
 695         }
 696
 697         do {
 698                 /* There's no means to poll POST state on BE2/3 VFs */
 699                 if (BEx_chip(adapter) && be_virtfn(adapter))
 700                         return 0;
 701
 702                 stage = be_POST_stage_get(adapter);
 703                 if (stage == POST_STAGE_ARMFW_RDY)
 704                         return 0;
 705
 706                 dev_info(dev, "Waiting for POST, %ds elapsed\n", timeout);
 707                 if (msleep_interruptible(2000)) {
 708                         dev_err(dev, "Waiting for POST aborted\n");
 709                         return -EINTR;
 710                 }
 711                 timeout += 2;
 712         } while (timeout < 60);
 713
 714 err:
 715         dev_err(dev, "POST timeout; stage=%#x\n", stage);
 716         return -ETIMEDOUT;
 717 }
 718
 719 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 720 {
 721         return &wrb->payload.sgl[0];
 722 }
 723
 724 static inline void fill_wrb_tags(struct be_mcc_wrb *wrb, unsigned long addr)
 725 {
 726         wrb->tag0 = addr & 0xFFFFFFFF;
 727         wrb->tag1 = upper_32_bits(addr);
 728 }
 729
 730 /* Don't touch the hdr after it's prepared */
 731 /* mem will be NULL for embedded commands */
 732 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 733                                    u8 subsystem, u8 opcode, int cmd_len,
 734                                    struct be_mcc_wrb *wrb,
 735                                    struct be_dma_mem *mem)
 736 {
 737         struct be_sge *sge;
 738
 739         req_hdr->opcode = opcode;
 740         req_hdr->subsystem = subsystem;
 741         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 742         req_hdr->version = 0;
 743         fill_wrb_tags(wrb, (ulong) req_hdr);
 744         wrb->payload_length = cmd_len;
 745         if (mem) {
 746                 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
 747                         MCC_WRB_SGE_CNT_SHIFT;
 748                 sge = nonembedded_sgl(wrb);
 749                 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
 750                 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
 751                 sge->len = cpu_to_le32(mem->size);
 752         } else
 753                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 754         be_dws_cpu_to_le(wrb, 8);
 755 }
 756
 757 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 758                                       struct be_dma_mem *mem)
 759 {
 760         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 761         u64 dma = (u64)mem->dma;
 762
 763         for (i = 0; i < buf_pages; i++) {
 764                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 765                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 766                 dma += PAGE_SIZE_4K;
 767         }
 768 }
 769
 770 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
 771 {
 772         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 773         struct be_mcc_wrb *wrb
 774                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 775         memset(wrb, 0, sizeof(*wrb));
 776         return wrb;
 777 }
 778
 779 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
 780 {
 781         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 782         struct be_mcc_wrb *wrb;
 783
 784         if (!mccq->created)
 785                 return NULL;
 786
 787         if (atomic_read(&mccq->used) >= mccq->len)
 788                 return NULL;
 789
 790         wrb = queue_head_node(mccq);
 791         queue_head_inc(mccq);
 792         atomic_inc(&mccq->used);
 793         memset(wrb, 0, sizeof(*wrb));
 794         return wrb;
 795 }
 796
 797 static bool use_mcc(struct be_adapter *adapter)
 798 {
 799         return adapter->mcc_obj.q.created;
 800 }
 801
 802 /* Must be used only in process context */
 803 static int be_cmd_lock(struct be_adapter *adapter)
 804 {
 805         if (use_mcc(adapter)) {
 806                 spin_lock_bh(&adapter->mcc_lock);
 807                 return 0;
 808         } else {
 809                 return mutex_lock_interruptible(&adapter->mbox_lock);
 810         }
 811 }
 812
 813 /* Must be used only in process context */
 814 static void be_cmd_unlock(struct be_adapter *adapter)
 815 {
 816         if (use_mcc(adapter))
 817                 spin_unlock_bh(&adapter->mcc_lock);
 818         else
 819                 return mutex_unlock(&adapter->mbox_lock);
 820 }
 821
 822 static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter,
 823                                       struct be_mcc_wrb *wrb)
 824 {
 825         struct be_mcc_wrb *dest_wrb;
 826
 827         if (use_mcc(adapter)) {
 828                 dest_wrb = wrb_from_mccq(adapter);
 829                 if (!dest_wrb)
 830                         return NULL;
 831         } else {
 832                 dest_wrb = wrb_from_mbox(adapter);
 833         }
 834
 835         memcpy(dest_wrb, wrb, sizeof(*wrb));
 836         if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK))
 837                 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb));
 838
 839         return dest_wrb;
 840 }
 841
 842 /* Must be used only in process context */
 843 static int be_cmd_notify_wait(struct be_adapter *adapter,
 844                               struct be_mcc_wrb *wrb)
 845 {
 846         struct be_mcc_wrb *dest_wrb;
 847         int status;
 848
 849         status = be_cmd_lock(adapter);
 850         if (status)
 851                 return status;
 852
 853         dest_wrb = be_cmd_copy(adapter, wrb);
 854         if (!dest_wrb) {
 855                 status = -EBUSY;
 856                 goto unlock;
 857         }
 858
 859         if (use_mcc(adapter))
 860                 status = be_mcc_notify_wait(adapter);
 861         else
 862                 status = be_mbox_notify_wait(adapter);
 863
 864         if (!status)
 865                 memcpy(wrb, dest_wrb, sizeof(*wrb));
 866
 867 unlock:
 868         be_cmd_unlock(adapter);
 869         return status;
 870 }
 871
 872 /* Tell fw we're about to start firing cmds by writing a
 873  * special pattern across the wrb hdr; uses mbox
 874  */
 875 int be_cmd_fw_init(struct be_adapter *adapter)
 876 {
 877         u8 *wrb;
 878         int status;
 879
 880         if (lancer_chip(adapter))
 881                 return 0;
 882
 883         if (mutex_lock_interruptible(&adapter->mbox_lock))
 884                 return -1;
 885
 886         wrb = (u8 *)wrb_from_mbox(adapter);
 887         *wrb++ = 0xFF;
 888         *wrb++ = 0x12;
 889         *wrb++ = 0x34;
 890         *wrb++ = 0xFF;
 891         *wrb++ = 0xFF;
 892         *wrb++ = 0x56;
 893         *wrb++ = 0x78;
 894         *wrb = 0xFF;
 895
 896         status = be_mbox_notify_wait(adapter);
 897
 898         mutex_unlock(&adapter->mbox_lock);
 899         return status;
 900 }
 901
 902 /* Tell fw we're done with firing cmds by writing a
 903  * special pattern across the wrb hdr; uses mbox
 904  */
 905 int be_cmd_fw_clean(struct be_adapter *adapter)
 906 {
 907         u8 *wrb;
 908         int status;
 909
 910         if (lancer_chip(adapter))
 911                 return 0;
 912
 913         if (mutex_lock_interruptible(&adapter->mbox_lock))
 914                 return -1;
 915
 916         wrb = (u8 *)wrb_from_mbox(adapter);
 917         *wrb++ = 0xFF;
 918         *wrb++ = 0xAA;
 919         *wrb++ = 0xBB;
 920         *wrb++ = 0xFF;
 921         *wrb++ = 0xFF;
 922         *wrb++ = 0xCC;
 923         *wrb++ = 0xDD;
 924         *wrb = 0xFF;
 925
 926         status = be_mbox_notify_wait(adapter);
 927
 928         mutex_unlock(&adapter->mbox_lock);
 929         return status;
 930 }
 931
 932 int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
 933 {
 934         struct be_mcc_wrb *wrb;
 935         struct be_cmd_req_eq_create *req;
 936         struct be_dma_mem *q_mem = &eqo->q.dma_mem;
 937         int status, ver = 0;
 938
 939         if (mutex_lock_interruptible(&adapter->mbox_lock))
 940                 return -1;
 941
 942         wrb = wrb_from_mbox(adapter);
 943         req = embedded_payload(wrb);
 944
 945         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 946                                OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb,
 947                                NULL);
 948
 949         /* Support for EQ_CREATEv2 available only SH-R onwards */
 950         if (!(BEx_chip(adapter) || lancer_chip(adapter)))
 951                 ver = 2;
 952
 953         req->hdr.version = ver;
 954         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 955
 956         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
 957         /* 4byte eqe*/
 958         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
 959         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
 960                       __ilog2_u32(eqo->q.len / 256));
 961         be_dws_cpu_to_le(req->context, sizeof(req->context));
 962
 963         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 964
 965         status = be_mbox_notify_wait(adapter);
 966         if (!status) {
 967                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
 968
 969                 eqo->q.id = le16_to_cpu(resp->eq_id);
 970                 eqo->msix_idx =
 971                         (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx;
 972                 eqo->q.created = true;
 973         }
 974
 975         mutex_unlock(&adapter->mbox_lock);
 976         return status;
 977 }
 978
 979 /* Use MCC */
 980 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 981                           bool permanent, u32 if_handle, u32 pmac_id)
 982 {
 983         struct be_mcc_wrb *wrb;
 984         struct be_cmd_req_mac_query *req;
 985         int status;
 986
 987         spin_lock_bh(&adapter->mcc_lock);
 988
 989         wrb = wrb_from_mccq(adapter);
 990         if (!wrb) {
 991                 status = -EBUSY;
 992                 goto err;
 993         }
 994         req = embedded_payload(wrb);
 995
 996         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 997                                OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb,
 998                                NULL);
 999         req->type = MAC_ADDRESS_TYPE_NETWORK;
1000         if (permanent) {
1001                 req->permanent = 1;
1002         } else {
1003                 req->if_id = cpu_to_le16((u16)if_handle);
1004                 req->pmac_id = cpu_to_le32(pmac_id);
1005                 req->permanent = 0;
1006         }
1007
1008         status = be_mcc_notify_wait(adapter);
1009         if (!status) {
1010                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
1011
1012                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
1013         }
1014
1015 err:
1016         spin_unlock_bh(&adapter->mcc_lock);
1017         return status;
1018 }
1019
1020 /* Uses synchronous MCCQ */
1021 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
1022                     u32 if_id, u32 *pmac_id, u32 domain)
1023 {
1024         struct be_mcc_wrb *wrb;
1025         struct be_cmd_req_pmac_add *req;
1026         int status;
1027
1028         spin_lock_bh(&adapter->mcc_lock);
1029
1030         wrb = wrb_from_mccq(adapter);
1031         if (!wrb) {
1032                 status = -EBUSY;
1033                 goto err;
1034         }
1035         req = embedded_payload(wrb);
1036
1037         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1038                                OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb,
1039                                NULL);
1040
1041         req->hdr.domain = domain;
1042         req->if_id = cpu_to_le32(if_id);
1043         memcpy(req->mac_address, mac_addr, ETH_ALEN);
1044
1045         status = be_mcc_notify_wait(adapter);
1046         if (!status) {
1047                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
1048
1049                 *pmac_id = le32_to_cpu(resp->pmac_id);
1050         }
1051
1052 err:
1053         spin_unlock_bh(&adapter->mcc_lock);
1054
1055          if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
1056                 status = -EPERM;
1057
1058         return status;
1059 }
1060
1061 /* Uses synchronous MCCQ */
1062 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
1063 {
1064         struct be_mcc_wrb *wrb;
1065         struct be_cmd_req_pmac_del *req;
1066         int status;
1067
1068         if (pmac_id == -1)
1069                 return 0;
1070
1071         spin_lock_bh(&adapter->mcc_lock);
1072
1073         wrb = wrb_from_mccq(adapter);
1074         if (!wrb) {
1075                 status = -EBUSY;
1076                 goto err;
1077         }
1078         req = embedded_payload(wrb);
1079
1080         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1081                                OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req),
1082                                wrb, NULL);
1083
1084         req->hdr.domain = dom;
1085         req->if_id = cpu_to_le32(if_id);
1086         req->pmac_id = cpu_to_le32(pmac_id);
1087
1088         status = be_mcc_notify_wait(adapter);
1089
1090 err:
1091         spin_unlock_bh(&adapter->mcc_lock);
1092         return status;
1093 }
1094
1095 /* Uses Mbox */
1096 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
1097                      struct be_queue_info *eq, bool no_delay, int coalesce_wm)
1098 {
1099         struct be_mcc_wrb *wrb;
1100         struct be_cmd_req_cq_create *req;
1101         struct be_dma_mem *q_mem = &cq->dma_mem;
1102         void *ctxt;
1103         int status;
1104
1105         if (mutex_lock_interruptible(&adapter->mbox_lock))
1106                 return -1;
1107
1108         wrb = wrb_from_mbox(adapter);
1109         req = embedded_payload(wrb);
1110         ctxt = &req->context;
1111
1112         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1113                                OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb,
1114                                NULL);
1115
1116         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1117
1118         if (BEx_chip(adapter)) {
1119                 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
1120                               coalesce_wm);
1121                 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
1122                               ctxt, no_delay);
1123                 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
1124                               __ilog2_u32(cq->len / 256));
1125                 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
1126                 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
1127                 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
1128         } else {
1129                 req->hdr.version = 2;
1130                 req->page_size = 1; /* 1 for 4K */
1131
1132                 /* coalesce-wm field in this cmd is not relevant to Lancer.
1133                  * Lancer uses COMMON_MODIFY_CQ to set this field
1134                  */
1135                 if (!lancer_chip(adapter))
1136                         AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
1137                                       ctxt, coalesce_wm);
1138                 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
1139                               no_delay);
1140                 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
1141                               __ilog2_u32(cq->len / 256));
1142                 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
1143                 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
1144                 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
1145         }
1146
1147         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1148
1149         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1150
1151         status = be_mbox_notify_wait(adapter);
1152         if (!status) {
1153                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
1154
1155                 cq->id = le16_to_cpu(resp->cq_id);
1156                 cq->created = true;
1157         }
1158
1159         mutex_unlock(&adapter->mbox_lock);
1160
1161         return status;
1162 }
1163
1164 static u32 be_encoded_q_len(int q_len)
1165 {
1166         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
1167
1168         if (len_encoded == 16)
1169                 len_encoded = 0;
1170         return len_encoded;
1171 }
1172
1173 static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
1174                                   struct be_queue_info *mccq,
1175                                   struct be_queue_info *cq)
1176 {
1177         struct be_mcc_wrb *wrb;
1178         struct be_cmd_req_mcc_ext_create *req;
1179         struct be_dma_mem *q_mem = &mccq->dma_mem;
1180         void *ctxt;
1181         int status;
1182
1183         if (mutex_lock_interruptible(&adapter->mbox_lock))
1184                 return -1;
1185
1186         wrb = wrb_from_mbox(adapter);
1187         req = embedded_payload(wrb);
1188         ctxt = &req->context;
1189
1190         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1191                                OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb,
1192                                NULL);
1193
1194         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1195         if (BEx_chip(adapter)) {
1196                 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1197                 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1198                               be_encoded_q_len(mccq->len));
1199                 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1200         } else {
1201                 req->hdr.version = 1;
1202                 req->cq_id = cpu_to_le16(cq->id);
1203
1204                 AMAP_SET_BITS(struct amap_mcc_context_v1, ring_size, ctxt,
1205                               be_encoded_q_len(mccq->len));
1206                 AMAP_SET_BITS(struct amap_mcc_context_v1, valid, ctxt, 1);
1207                 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_id,
1208                               ctxt, cq->id);
1209                 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_valid,
1210                               ctxt, 1);
1211         }
1212
1213         /* Subscribe to Link State, Sliport Event and Group 5 Events
1214          * (bits 1, 5 and 17 set)
1215          */
1216         req->async_event_bitmap[0] =
1217                         cpu_to_le32(BIT(ASYNC_EVENT_CODE_LINK_STATE) |
1218                                     BIT(ASYNC_EVENT_CODE_GRP_5) |
1219                                     BIT(ASYNC_EVENT_CODE_QNQ) |
1220                                     BIT(ASYNC_EVENT_CODE_SLIPORT));
1221
1222         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1223
1224         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1225
1226         status = be_mbox_notify_wait(adapter);
1227         if (!status) {
1228                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1229
1230                 mccq->id = le16_to_cpu(resp->id);
1231                 mccq->created = true;
1232         }
1233         mutex_unlock(&adapter->mbox_lock);
1234
1235         return status;
1236 }
1237
1238 static int be_cmd_mccq_org_create(struct be_adapter *adapter,
1239                                   struct be_queue_info *mccq,
1240                                   struct be_queue_info *cq)
1241 {
1242         struct be_mcc_wrb *wrb;
1243         struct be_cmd_req_mcc_create *req;
1244         struct be_dma_mem *q_mem = &mccq->dma_mem;
1245         void *ctxt;
1246         int status;
1247
1248         if (mutex_lock_interruptible(&adapter->mbox_lock))
1249                 return -1;
1250
1251         wrb = wrb_from_mbox(adapter);
1252         req = embedded_payload(wrb);
1253         ctxt = &req->context;
1254
1255         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1256                                OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb,
1257                                NULL);
1258
1259         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1260
1261         AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1262         AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1263                       be_encoded_q_len(mccq->len));
1264         AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1265
1266         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1267
1268         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1269
1270         status = be_mbox_notify_wait(adapter);
1271         if (!status) {
1272                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1273
1274                 mccq->id = le16_to_cpu(resp->id);
1275                 mccq->created = true;
1276         }
1277
1278         mutex_unlock(&adapter->mbox_lock);
1279         return status;
1280 }
1281
1282 int be_cmd_mccq_create(struct be_adapter *adapter,
1283                        struct be_queue_info *mccq, struct be_queue_info *cq)
1284 {
1285         int status;
1286
1287         status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1288         if (status && BEx_chip(adapter)) {
1289                 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1290                         "or newer to avoid conflicting priorities between NIC "
1291                         "and FCoE traffic");
1292                 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1293         }
1294         return status;
1295 }
1296
1297 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
1298 {
1299         struct be_mcc_wrb wrb = {0};
1300         struct be_cmd_req_eth_tx_create *req;
1301         struct be_queue_info *txq = &txo->q;
1302         struct be_queue_info *cq = &txo->cq;
1303         struct be_dma_mem *q_mem = &txq->dma_mem;
1304         int status, ver = 0;
1305
1306         req = embedded_payload(&wrb);
1307         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1308                                OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL);
1309
1310         if (lancer_chip(adapter)) {
1311                 req->hdr.version = 1;
1312         } else if (BEx_chip(adapter)) {
1313                 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1314                         req->hdr.version = 2;
1315         } else { /* For SH */
1316                 req->hdr.version = 2;
1317         }
1318
1319         if (req->hdr.version > 0)
1320                 req->if_id = cpu_to_le16(adapter->if_handle);
1321         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1322         req->ulp_num = BE_ULP1_NUM;
1323         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1324         req->cq_id = cpu_to_le16(cq->id);
1325         req->queue_size = be_encoded_q_len(txq->len);
1326         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1327         ver = req->hdr.version;
1328
1329         status = be_cmd_notify_wait(adapter, &wrb);
1330         if (!status) {
1331                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb);
1332
1333                 txq->id = le16_to_cpu(resp->cid);
1334                 if (ver == 2)
1335                         txo->db_offset = le32_to_cpu(resp->db_offset);
1336                 else
1337                         txo->db_offset = DB_TXULP1_OFFSET;
1338                 txq->created = true;
1339         }
1340
1341         return status;
1342 }
1343
1344 /* Uses MCC */
1345 int be_cmd_rxq_create(struct be_adapter *adapter,
1346                       struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1347                       u32 if_id, u32 rss, u8 *rss_id)
1348 {
1349         struct be_mcc_wrb *wrb;
1350         struct be_cmd_req_eth_rx_create *req;
1351         struct be_dma_mem *q_mem = &rxq->dma_mem;
1352         int status;
1353
1354         spin_lock_bh(&adapter->mcc_lock);
1355
1356         wrb = wrb_from_mccq(adapter);
1357         if (!wrb) {
1358                 status = -EBUSY;
1359                 goto err;
1360         }
1361         req = embedded_payload(wrb);
1362
1363         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1364                                OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1365
1366         req->cq_id = cpu_to_le16(cq_id);
1367         req->frag_size = fls(frag_size) - 1;
1368         req->num_pages = 2;
1369         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1370         req->interface_id = cpu_to_le32(if_id);
1371         req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
1372         req->rss_queue = cpu_to_le32(rss);
1373
1374         status = be_mcc_notify_wait(adapter);
1375         if (!status) {
1376                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1377
1378                 rxq->id = le16_to_cpu(resp->id);
1379                 rxq->created = true;
1380                 *rss_id = resp->rss_id;
1381         }
1382
1383 err:
1384         spin_unlock_bh(&adapter->mcc_lock);
1385         return status;
1386 }
1387
1388 /* Generic destroyer function for all types of queues
1389  * Uses Mbox
1390  */
1391 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1392                      int queue_type)
1393 {
1394         struct be_mcc_wrb *wrb;
1395         struct be_cmd_req_q_destroy *req;
1396         u8 subsys = 0, opcode = 0;
1397         int status;
1398
1399         if (mutex_lock_interruptible(&adapter->mbox_lock))
1400                 return -1;
1401
1402         wrb = wrb_from_mbox(adapter);
1403         req = embedded_payload(wrb);
1404
1405         switch (queue_type) {
1406         case QTYPE_EQ:
1407                 subsys = CMD_SUBSYSTEM_COMMON;
1408                 opcode = OPCODE_COMMON_EQ_DESTROY;
1409                 break;
1410         case QTYPE_CQ:
1411                 subsys = CMD_SUBSYSTEM_COMMON;
1412                 opcode = OPCODE_COMMON_CQ_DESTROY;
1413                 break;
1414         case QTYPE_TXQ:
1415                 subsys = CMD_SUBSYSTEM_ETH;
1416                 opcode = OPCODE_ETH_TX_DESTROY;
1417                 break;
1418         case QTYPE_RXQ:
1419                 subsys = CMD_SUBSYSTEM_ETH;
1420                 opcode = OPCODE_ETH_RX_DESTROY;
1421                 break;
1422         case QTYPE_MCCQ:
1423                 subsys = CMD_SUBSYSTEM_COMMON;
1424                 opcode = OPCODE_COMMON_MCC_DESTROY;
1425                 break;
1426         default:
1427                 BUG();
1428         }
1429
1430         be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1431                                NULL);
1432         req->id = cpu_to_le16(q->id);
1433
1434         status = be_mbox_notify_wait(adapter);
1435         q->created = false;
1436
1437         mutex_unlock(&adapter->mbox_lock);
1438         return status;
1439 }
1440
1441 /* Uses MCC */
1442 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1443 {
1444         struct be_mcc_wrb *wrb;
1445         struct be_cmd_req_q_destroy *req;
1446         int status;
1447
1448         spin_lock_bh(&adapter->mcc_lock);
1449
1450         wrb = wrb_from_mccq(adapter);
1451         if (!wrb) {
1452                 status = -EBUSY;
1453                 goto err;
1454         }
1455         req = embedded_payload(wrb);
1456
1457         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1458                                OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1459         req->id = cpu_to_le16(q->id);
1460
1461         status = be_mcc_notify_wait(adapter);
1462         q->created = false;
1463
1464 err:
1465         spin_unlock_bh(&adapter->mcc_lock);
1466         return status;
1467 }
1468
1469 /* Create an rx filtering policy configuration on an i/f
1470  * Will use MBOX only if MCCQ has not been created.
1471  */
1472 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1473                      u32 *if_handle, u32 domain)
1474 {
1475         struct be_mcc_wrb wrb = {0};
1476         struct be_cmd_req_if_create *req;
1477         int status;
1478
1479         req = embedded_payload(&wrb);
1480         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1481                                OPCODE_COMMON_NTWK_INTERFACE_CREATE,
1482                                sizeof(*req), &wrb, NULL);
1483         req->hdr.domain = domain;
1484         req->capability_flags = cpu_to_le32(cap_flags);
1485         req->enable_flags = cpu_to_le32(en_flags);
1486         req->pmac_invalid = true;
1487
1488         status = be_cmd_notify_wait(adapter, &wrb);
1489         if (!status) {
1490                 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb);
1491
1492                 *if_handle = le32_to_cpu(resp->interface_id);
1493
1494                 /* Hack to retrieve VF's pmac-id on BE3 */
1495                 if (BE3_chip(adapter) && be_virtfn(adapter))
1496                         adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
1497         }
1498         return status;
1499 }
1500
1501 /* Uses MCCQ */
1502 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1503 {
1504         struct be_mcc_wrb *wrb;
1505         struct be_cmd_req_if_destroy *req;
1506         int status;
1507
1508         if (interface_id == -1)
1509                 return 0;
1510
1511         spin_lock_bh(&adapter->mcc_lock);
1512
1513         wrb = wrb_from_mccq(adapter);
1514         if (!wrb) {
1515                 status = -EBUSY;
1516                 goto err;
1517         }
1518         req = embedded_payload(wrb);
1519
1520         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1521                                OPCODE_COMMON_NTWK_INTERFACE_DESTROY,
1522                                sizeof(*req), wrb, NULL);
1523         req->hdr.domain = domain;
1524         req->interface_id = cpu_to_le32(interface_id);
1525
1526         status = be_mcc_notify_wait(adapter);
1527 err:
1528         spin_unlock_bh(&adapter->mcc_lock);
1529         return status;
1530 }
1531
1532 /* Get stats is a non embedded command: the request is not embedded inside
1533  * WRB but is a separate dma memory block
1534  * Uses asynchronous MCC
1535  */
1536 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1537 {
1538         struct be_mcc_wrb *wrb;
1539         struct be_cmd_req_hdr *hdr;
1540         int status = 0;
1541
1542         spin_lock_bh(&adapter->mcc_lock);
1543
1544         wrb = wrb_from_mccq(adapter);
1545         if (!wrb) {
1546                 status = -EBUSY;
1547                 goto err;
1548         }
1549         hdr = nonemb_cmd->va;
1550
1551         be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1552                                OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb,
1553                                nonemb_cmd);
1554
1555         /* version 1 of the cmd is not supported only by BE2 */
1556         if (BE2_chip(adapter))
1557                 hdr->version = 0;
1558         if (BE3_chip(adapter) || lancer_chip(adapter))
1559                 hdr->version = 1;
1560         else
1561                 hdr->version = 2;
1562
1563         status = be_mcc_notify(adapter);
1564         if (status)
1565                 goto err;
1566
1567         adapter->stats_cmd_sent = true;
1568
1569 err:
1570         spin_unlock_bh(&adapter->mcc_lock);
1571         return status;
1572 }
1573
1574 /* Lancer Stats */
1575 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1576                                struct be_dma_mem *nonemb_cmd)
1577 {
1578         struct be_mcc_wrb *wrb;
1579         struct lancer_cmd_req_pport_stats *req;
1580         int status = 0;
1581
1582         if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1583                             CMD_SUBSYSTEM_ETH))
1584                 return -EPERM;
1585
1586         spin_lock_bh(&adapter->mcc_lock);
1587
1588         wrb = wrb_from_mccq(adapter);
1589         if (!wrb) {
1590                 status = -EBUSY;
1591                 goto err;
1592         }
1593         req = nonemb_cmd->va;
1594
1595         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1596                                OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size,
1597                                wrb, nonemb_cmd);
1598
1599         req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1600         req->cmd_params.params.reset_stats = 0;
1601
1602         status = be_mcc_notify(adapter);
1603         if (status)
1604                 goto err;
1605
1606         adapter->stats_cmd_sent = true;
1607
1608 err:
1609         spin_unlock_bh(&adapter->mcc_lock);
1610         return status;
1611 }
1612
1613 static int be_mac_to_link_speed(int mac_speed)
1614 {
1615         switch (mac_speed) {
1616         case PHY_LINK_SPEED_ZERO:
1617                 return 0;
1618         case PHY_LINK_SPEED_10MBPS:
1619                 return 10;
1620         case PHY_LINK_SPEED_100MBPS:
1621                 return 100;
1622         case PHY_LINK_SPEED_1GBPS:
1623                 return 1000;
1624         case PHY_LINK_SPEED_10GBPS:
1625                 return 10000;
1626         case PHY_LINK_SPEED_20GBPS:
1627                 return 20000;
1628         case PHY_LINK_SPEED_25GBPS:
1629                 return 25000;
1630         case PHY_LINK_SPEED_40GBPS:
1631                 return 40000;
1632         }
1633         return 0;
1634 }
1635
1636 /* Uses synchronous mcc
1637  * Returns link_speed in Mbps
1638  */
1639 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1640                              u8 *link_status, u32 dom)
1641 {
1642         struct be_mcc_wrb *wrb;
1643         struct be_cmd_req_link_status *req;
1644         int status;
1645
1646         spin_lock_bh(&adapter->mcc_lock);
1647
1648         if (link_status)
1649                 *link_status = LINK_DOWN;
1650
1651         wrb = wrb_from_mccq(adapter);
1652         if (!wrb) {
1653                 status = -EBUSY;
1654                 goto err;
1655         }
1656         req = embedded_payload(wrb);
1657
1658         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1659                                OPCODE_COMMON_NTWK_LINK_STATUS_QUERY,
1660                                sizeof(*req), wrb, NULL);
1661
1662         /* version 1 of the cmd is not supported only by BE2 */
1663         if (!BE2_chip(adapter))
1664                 req->hdr.version = 1;
1665
1666         req->hdr.domain = dom;
1667
1668         status = be_mcc_notify_wait(adapter);
1669         if (!status) {
1670                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1671
1672                 if (link_speed) {
1673                         *link_speed = resp->link_speed ?
1674                                       le16_to_cpu(resp->link_speed) * 10 :
1675                                       be_mac_to_link_speed(resp->mac_speed);
1676
1677                         if (!resp->logical_link_status)
1678                                 *link_speed = 0;
1679                 }
1680                 if (link_status)
1681                         *link_status = resp->logical_link_status;
1682         }
1683
1684 err:
1685         spin_unlock_bh(&adapter->mcc_lock);
1686         return status;
1687 }
1688
1689 /* Uses synchronous mcc */
1690 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1691 {
1692         struct be_mcc_wrb *wrb;
1693         struct be_cmd_req_get_cntl_addnl_attribs *req;
1694         int status = 0;
1695
1696         spin_lock_bh(&adapter->mcc_lock);
1697
1698         wrb = wrb_from_mccq(adapter);
1699         if (!wrb) {
1700                 status = -EBUSY;
1701                 goto err;
1702         }
1703         req = embedded_payload(wrb);
1704
1705         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1706                                OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES,
1707                                sizeof(*req), wrb, NULL);
1708
1709         status = be_mcc_notify(adapter);
1710 err:
1711         spin_unlock_bh(&adapter->mcc_lock);
1712         return status;
1713 }
1714
1715 /* Uses synchronous mcc */
1716 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1717 {
1718         struct be_mcc_wrb *wrb;
1719         struct be_cmd_req_get_fat *req;
1720         int status;
1721
1722         spin_lock_bh(&adapter->mcc_lock);
1723
1724         wrb = wrb_from_mccq(adapter);
1725         if (!wrb) {
1726                 status = -EBUSY;
1727                 goto err;
1728         }
1729         req = embedded_payload(wrb);
1730
1731         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1732                                OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb,
1733                                NULL);
1734         req->fat_operation = cpu_to_le32(QUERY_FAT);
1735         status = be_mcc_notify_wait(adapter);
1736         if (!status) {
1737                 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1738
1739                 if (log_size && resp->log_size)
1740                         *log_size = le32_to_cpu(resp->log_size) -
1741                                         sizeof(u32);
1742         }
1743 err:
1744         spin_unlock_bh(&adapter->mcc_lock);
1745         return status;
1746 }
1747
1748 int be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1749 {
1750         struct be_dma_mem get_fat_cmd;
1751         struct be_mcc_wrb *wrb;
1752         struct be_cmd_req_get_fat *req;
1753         u32 offset = 0, total_size, buf_size,
1754                                 log_offset = sizeof(u32), payload_len;
1755         int status = 0;
1756
1757         if (buf_len == 0)
1758                 return -EIO;
1759
1760         total_size = buf_len;
1761
1762         get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1763         get_fat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
1764                                              get_fat_cmd.size,
1765                                              &get_fat_cmd.dma, GFP_ATOMIC);
1766         if (!get_fat_cmd.va) {
1767                 dev_err(&adapter->pdev->dev,
1768                         "Memory allocation failure while reading FAT data\n");
1769                 return -ENOMEM;
1770         }
1771
1772         spin_lock_bh(&adapter->mcc_lock);
1773
1774         while (total_size) {
1775                 buf_size = min(total_size, (u32)60*1024);
1776                 total_size -= buf_size;
1777
1778                 wrb = wrb_from_mccq(adapter);
1779                 if (!wrb) {
1780                         status = -EBUSY;
1781                         goto err;
1782                 }
1783                 req = get_fat_cmd.va;
1784
1785                 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1786                 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1787                                        OPCODE_COMMON_MANAGE_FAT, payload_len,
1788                                        wrb, &get_fat_cmd);
1789
1790                 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1791                 req->read_log_offset = cpu_to_le32(log_offset);
1792                 req->read_log_length = cpu_to_le32(buf_size);
1793                 req->data_buffer_size = cpu_to_le32(buf_size);
1794
1795                 status = be_mcc_notify_wait(adapter);
1796                 if (!status) {
1797                         struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1798
1799                         memcpy(buf + offset,
1800                                resp->data_buffer,
1801                                le32_to_cpu(resp->read_log_length));
1802                 } else {
1803                         dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1804                         goto err;
1805                 }
1806                 offset += buf_size;
1807                 log_offset += buf_size;
1808         }
1809 err:
1810         dma_free_coherent(&adapter->pdev->dev, get_fat_cmd.size,
1811                           get_fat_cmd.va, get_fat_cmd.dma);
1812         spin_unlock_bh(&adapter->mcc_lock);
1813         return status;
1814 }
1815
1816 /* Uses synchronous mcc */
1817 int be_cmd_get_fw_ver(struct be_adapter *adapter)
1818 {
1819         struct be_mcc_wrb *wrb;
1820         struct be_cmd_req_get_fw_version *req;
1821         int status;
1822
1823         spin_lock_bh(&adapter->mcc_lock);
1824
1825         wrb = wrb_from_mccq(adapter);
1826         if (!wrb) {
1827                 status = -EBUSY;
1828                 goto err;
1829         }
1830
1831         req = embedded_payload(wrb);
1832
1833         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1834                                OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb,
1835                                NULL);
1836         status = be_mcc_notify_wait(adapter);
1837         if (!status) {
1838                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1839
1840                 strlcpy(adapter->fw_ver, resp->firmware_version_string,
1841                         sizeof(adapter->fw_ver));
1842                 strlcpy(adapter->fw_on_flash, resp->fw_on_flash_version_string,
1843                         sizeof(adapter->fw_on_flash));
1844         }
1845 err:
1846         spin_unlock_bh(&adapter->mcc_lock);
1847         return status;
1848 }
1849
1850 /* set the EQ delay interval of an EQ to specified value
1851  * Uses async mcc
1852  */
1853 static int __be_cmd_modify_eqd(struct be_adapter *adapter,
1854                                struct be_set_eqd *set_eqd, int num)
1855 {
1856         struct be_mcc_wrb *wrb;
1857         struct be_cmd_req_modify_eq_delay *req;
1858         int status = 0, i;
1859
1860         spin_lock_bh(&adapter->mcc_lock);
1861
1862         wrb = wrb_from_mccq(adapter);
1863         if (!wrb) {
1864                 status = -EBUSY;
1865                 goto err;
1866         }
1867         req = embedded_payload(wrb);
1868
1869         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1870                                OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb,
1871                                NULL);
1872
1873         req->num_eq = cpu_to_le32(num);
1874         for (i = 0; i < num; i++) {
1875                 req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id);
1876                 req->set_eqd[i].phase = 0;
1877                 req->set_eqd[i].delay_multiplier =
1878                                 cpu_to_le32(set_eqd[i].delay_multiplier);
1879         }
1880
1881         status = be_mcc_notify(adapter);
1882 err:
1883         spin_unlock_bh(&adapter->mcc_lock);
1884         return status;
1885 }
1886
1887 int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd,
1888                       int num)
1889 {
1890         int num_eqs, i = 0;
1891
1892         while (num) {
1893                 num_eqs = min(num, 8);
1894                 __be_cmd_modify_eqd(adapter, &set_eqd[i], num_eqs);
1895                 i += num_eqs;
1896                 num -= num_eqs;
1897         }
1898
1899         return 0;
1900 }
1901
1902 /* Uses sycnhronous mcc */
1903 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1904                        u32 num, u32 domain)
1905 {
1906         struct be_mcc_wrb *wrb;
1907         struct be_cmd_req_vlan_config *req;
1908         int status;
1909
1910         spin_lock_bh(&adapter->mcc_lock);
1911
1912         wrb = wrb_from_mccq(adapter);
1913         if (!wrb) {
1914                 status = -EBUSY;
1915                 goto err;
1916         }
1917         req = embedded_payload(wrb);
1918
1919         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1920                                OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req),
1921                                wrb, NULL);
1922         req->hdr.domain = domain;
1923
1924         req->interface_id = if_id;
1925         req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0;
1926         req->num_vlan = num;
1927         memcpy(req->normal_vlan, vtag_array,
1928                req->num_vlan * sizeof(vtag_array[0]));
1929
1930         status = be_mcc_notify_wait(adapter);
1931 err:
1932         spin_unlock_bh(&adapter->mcc_lock);
1933         return status;
1934 }
1935
1936 static int __be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1937 {
1938         struct be_mcc_wrb *wrb;
1939         struct be_dma_mem *mem = &adapter->rx_filter;
1940         struct be_cmd_req_rx_filter *req = mem->va;
1941         int status;
1942
1943         spin_lock_bh(&adapter->mcc_lock);
1944
1945         wrb = wrb_from_mccq(adapter);
1946         if (!wrb) {
1947                 status = -EBUSY;
1948                 goto err;
1949         }
1950         memset(req, 0, sizeof(*req));
1951         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1952                                OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1953                                wrb, mem);
1954
1955         req->if_id = cpu_to_le32(adapter->if_handle);
1956         req->if_flags_mask = cpu_to_le32(flags);
1957         req->if_flags = (value == ON) ? req->if_flags_mask : 0;
1958
1959         if (flags & BE_IF_FLAGS_MULTICAST) {
1960                 struct netdev_hw_addr *ha;
1961                 int i = 0;
1962
1963                 /* Reset mcast promisc mode if already set by setting mask
1964                  * and not setting flags field
1965                  */
1966                 req->if_flags_mask |=
1967                         cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
1968                                     be_if_cap_flags(adapter));
1969                 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
1970                 netdev_for_each_mc_addr(ha, adapter->netdev)
1971                         memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
1972         }
1973
1974         status = be_mcc_notify_wait(adapter);
1975 err:
1976         spin_unlock_bh(&adapter->mcc_lock);
1977         return status;
1978 }
1979
1980 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1981 {
1982         struct device *dev = &adapter->pdev->dev;
1983
1984         if ((flags & be_if_cap_flags(adapter)) != flags) {
1985                 dev_warn(dev, "Cannot set rx filter flags 0x%x\n", flags);
1986                 dev_warn(dev, "Interface is capable of 0x%x flags only\n",
1987                          be_if_cap_flags(adapter));
1988         }
1989         flags &= be_if_cap_flags(adapter);
1990         if (!flags)
1991                 return -ENOTSUPP;
1992
1993         return __be_cmd_rx_filter(adapter, flags, value);
1994 }
1995
1996 /* Uses synchrounous mcc */
1997 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1998 {
1999         struct be_mcc_wrb *wrb;
2000         struct be_cmd_req_set_flow_control *req;
2001         int status;
2002
2003         if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
2004                             CMD_SUBSYSTEM_COMMON))
2005                 return -EPERM;
2006
2007         spin_lock_bh(&adapter->mcc_lock);
2008
2009         wrb = wrb_from_mccq(adapter);
2010         if (!wrb) {
2011                 status = -EBUSY;
2012                 goto err;
2013         }
2014         req = embedded_payload(wrb);
2015
2016         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2017                                OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req),
2018                                wrb, NULL);
2019
2020         req->hdr.version = 1;
2021         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
2022         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
2023
2024         status = be_mcc_notify_wait(adapter);
2025
2026 err:
2027         spin_unlock_bh(&adapter->mcc_lock);
2028
2029         if (base_status(status) == MCC_STATUS_FEATURE_NOT_SUPPORTED)
2030                 return  -EOPNOTSUPP;
2031
2032         return status;
2033 }
2034
2035 /* Uses sycn mcc */
2036 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
2037 {
2038         struct be_mcc_wrb *wrb;
2039         struct be_cmd_req_get_flow_control *req;
2040         int status;
2041
2042         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
2043                             CMD_SUBSYSTEM_COMMON))
2044                 return -EPERM;
2045
2046         spin_lock_bh(&adapter->mcc_lock);
2047
2048         wrb = wrb_from_mccq(adapter);
2049         if (!wrb) {
2050                 status = -EBUSY;
2051                 goto err;
2052         }
2053         req = embedded_payload(wrb);
2054
2055         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2056                                OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req),
2057                                wrb, NULL);
2058
2059         status = be_mcc_notify_wait(adapter);
2060         if (!status) {
2061                 struct be_cmd_resp_get_flow_control *resp =
2062                                                 embedded_payload(wrb);
2063
2064                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
2065                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
2066         }
2067
2068 err:
2069         spin_unlock_bh(&adapter->mcc_lock);
2070         return status;
2071 }
2072
2073 /* Uses mbox */
2074 int be_cmd_query_fw_cfg(struct be_adapter *adapter)
2075 {
2076         struct be_mcc_wrb *wrb;
2077         struct be_cmd_req_query_fw_cfg *req;
2078         int status;
2079
2080         if (mutex_lock_interruptible(&adapter->mbox_lock))
2081                 return -1;
2082
2083         wrb = wrb_from_mbox(adapter);
2084         req = embedded_payload(wrb);
2085
2086         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2087                                OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
2088                                sizeof(*req), wrb, NULL);
2089
2090         status = be_mbox_notify_wait(adapter);
2091         if (!status) {
2092                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
2093
2094                 adapter->port_num = le32_to_cpu(resp->phys_port);
2095                 adapter->function_mode = le32_to_cpu(resp->function_mode);
2096                 adapter->function_caps = le32_to_cpu(resp->function_caps);
2097                 adapter->asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
2098                 dev_info(&adapter->pdev->dev,
2099                          "FW config: function_mode=0x%x, function_caps=0x%x\n",
2100                          adapter->function_mode, adapter->function_caps);
2101         }
2102
2103         mutex_unlock(&adapter->mbox_lock);
2104         return status;
2105 }
2106
2107 /* Uses mbox */
2108 int be_cmd_reset_function(struct be_adapter *adapter)
2109 {
2110         struct be_mcc_wrb *wrb;
2111         struct be_cmd_req_hdr *req;
2112         int status;
2113
2114         if (lancer_chip(adapter)) {
2115                 iowrite32(SLI_PORT_CONTROL_IP_MASK,
2116                           adapter->db + SLIPORT_CONTROL_OFFSET);
2117                 status = lancer_wait_ready(adapter);
2118                 if (status)
2119                         dev_err(&adapter->pdev->dev,
2120                                 "Adapter in non recoverable error\n");
2121                 return status;
2122         }
2123
2124         if (mutex_lock_interruptible(&adapter->mbox_lock))
2125                 return -1;
2126
2127         wrb = wrb_from_mbox(adapter);
2128         req = embedded_payload(wrb);
2129
2130         be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
2131                                OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb,
2132                                NULL);
2133
2134         status = be_mbox_notify_wait(adapter);
2135
2136         mutex_unlock(&adapter->mbox_lock);
2137         return status;
2138 }
2139
2140 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
2141                       u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey)
2142 {
2143         struct be_mcc_wrb *wrb;
2144         struct be_cmd_req_rss_config *req;
2145         int status;
2146
2147         if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS))
2148                 return 0;
2149
2150         spin_lock_bh(&adapter->mcc_lock);
2151
2152         wrb = wrb_from_mccq(adapter);
2153         if (!wrb) {
2154                 status = -EBUSY;
2155                 goto err;
2156         }
2157         req = embedded_payload(wrb);
2158
2159         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2160                                OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
2161
2162         req->if_id = cpu_to_le32(adapter->if_handle);
2163         req->enable_rss = cpu_to_le16(rss_hash_opts);
2164         req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
2165
2166         if (!BEx_chip(adapter))
2167                 req->hdr.version = 1;
2168
2169         memcpy(req->cpu_table, rsstable, table_size);
2170         memcpy(req->hash, rss_hkey, RSS_HASH_KEY_LEN);
2171         be_dws_cpu_to_le(req->hash, sizeof(req->hash));
2172
2173         status = be_mcc_notify_wait(adapter);
2174 err:
2175         spin_unlock_bh(&adapter->mcc_lock);
2176         return status;
2177 }
2178
2179 /* Uses sync mcc */
2180 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
2181                             u8 bcn, u8 sts, u8 state)
2182 {
2183         struct be_mcc_wrb *wrb;
2184         struct be_cmd_req_enable_disable_beacon *req;
2185         int status;
2186
2187         spin_lock_bh(&adapter->mcc_lock);
2188
2189         wrb = wrb_from_mccq(adapter);
2190         if (!wrb) {
2191                 status = -EBUSY;
2192                 goto err;
2193         }
2194         req = embedded_payload(wrb);
2195
2196         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2197                                OPCODE_COMMON_ENABLE_DISABLE_BEACON,
2198                                sizeof(*req), wrb, NULL);
2199
2200         req->port_num = port_num;
2201         req->beacon_state = state;
2202         req->beacon_duration = bcn;
2203         req->status_duration = sts;
2204
2205         status = be_mcc_notify_wait(adapter);
2206
2207 err:
2208         spin_unlock_bh(&adapter->mcc_lock);
2209         return status;
2210 }
2211
2212 /* Uses sync mcc */
2213 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2214 {
2215         struct be_mcc_wrb *wrb;
2216         struct be_cmd_req_get_beacon_state *req;
2217         int status;
2218
2219         spin_lock_bh(&adapter->mcc_lock);
2220
2221         wrb = wrb_from_mccq(adapter);
2222         if (!wrb) {
2223                 status = -EBUSY;
2224                 goto err;
2225         }
2226         req = embedded_payload(wrb);
2227
2228         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2229                                OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req),
2230                                wrb, NULL);
2231
2232         req->port_num = port_num;
2233
2234         status = be_mcc_notify_wait(adapter);
2235         if (!status) {
2236                 struct be_cmd_resp_get_beacon_state *resp =
2237                                                 embedded_payload(wrb);
2238
2239                 *state = resp->beacon_state;
2240         }
2241
2242 err:
2243         spin_unlock_bh(&adapter->mcc_lock);
2244         return status;
2245 }
2246
2247 /* Uses sync mcc */
2248 int be_cmd_read_port_transceiver_data(struct be_adapter *adapter,
2249                                       u8 page_num, u8 *data)
2250 {
2251         struct be_dma_mem cmd;
2252         struct be_mcc_wrb *wrb;
2253         struct be_cmd_req_port_type *req;
2254         int status;
2255
2256         if (page_num > TR_PAGE_A2)
2257                 return -EINVAL;
2258
2259         cmd.size = sizeof(struct be_cmd_resp_port_type);
2260         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
2261                                      GFP_ATOMIC);
2262         if (!cmd.va) {
2263                 dev_err(&adapter->pdev->dev, "Memory allocation failed\n");
2264                 return -ENOMEM;
2265         }
2266
2267         spin_lock_bh(&adapter->mcc_lock);
2268
2269         wrb = wrb_from_mccq(adapter);
2270         if (!wrb) {
2271                 status = -EBUSY;
2272                 goto err;
2273         }
2274         req = cmd.va;
2275
2276         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2277                                OPCODE_COMMON_READ_TRANSRECV_DATA,
2278                                cmd.size, wrb, &cmd);
2279
2280         req->port = cpu_to_le32(adapter->hba_port_num);
2281         req->page_num = cpu_to_le32(page_num);
2282         status = be_mcc_notify_wait(adapter);
2283         if (!status) {
2284                 struct be_cmd_resp_port_type *resp = cmd.va;
2285
2286                 memcpy(data, resp->page_data, PAGE_DATA_LEN);
2287         }
2288 err:
2289         spin_unlock_bh(&adapter->mcc_lock);
2290         dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
2291         return status;
2292 }
2293
2294 static int lancer_cmd_write_object(struct be_adapter *adapter,
2295                                    struct be_dma_mem *cmd, u32 data_size,
2296                                    u32 data_offset, const char *obj_name,
2297                                    u32 *data_written, u8 *change_status,
2298                                    u8 *addn_status)
2299 {
2300         struct be_mcc_wrb *wrb;
2301         struct lancer_cmd_req_write_object *req;
2302         struct lancer_cmd_resp_write_object *resp;
2303         void *ctxt = NULL;
2304         int status;
2305
2306         spin_lock_bh(&adapter->mcc_lock);
2307         adapter->flash_status = 0;
2308
2309         wrb = wrb_from_mccq(adapter);
2310         if (!wrb) {
2311                 status = -EBUSY;
2312                 goto err_unlock;
2313         }
2314
2315         req = embedded_payload(wrb);
2316
2317         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2318                                OPCODE_COMMON_WRITE_OBJECT,
2319                                sizeof(struct lancer_cmd_req_write_object), wrb,
2320                                NULL);
2321
2322         ctxt = &req->context;
2323         AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2324                       write_length, ctxt, data_size);
2325
2326         if (data_size == 0)
2327                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2328                               eof, ctxt, 1);
2329         else
2330                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2331                               eof, ctxt, 0);
2332
2333         be_dws_cpu_to_le(ctxt, sizeof(req->context));
2334         req->write_offset = cpu_to_le32(data_offset);
2335         strlcpy(req->object_name, obj_name, sizeof(req->object_name));
2336         req->descriptor_count = cpu_to_le32(1);
2337         req->buf_len = cpu_to_le32(data_size);
2338         req->addr_low = cpu_to_le32((cmd->dma +
2339                                      sizeof(struct lancer_cmd_req_write_object))
2340                                     & 0xFFFFFFFF);
2341         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2342                                 sizeof(struct lancer_cmd_req_write_object)));
2343
2344         status = be_mcc_notify(adapter);
2345         if (status)
2346                 goto err_unlock;
2347
2348         spin_unlock_bh(&adapter->mcc_lock);
2349
2350         if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2351                                          msecs_to_jiffies(60000)))
2352                 status = -ETIMEDOUT;
2353         else
2354                 status = adapter->flash_status;
2355
2356         resp = embedded_payload(wrb);
2357         if (!status) {
2358                 *data_written = le32_to_cpu(resp->actual_write_len);
2359                 *change_status = resp->change_status;
2360         } else {
2361                 *addn_status = resp->additional_status;
2362         }
2363
2364         return status;
2365
2366 err_unlock:
2367         spin_unlock_bh(&adapter->mcc_lock);
2368         return status;
2369 }
2370
2371 int be_cmd_query_cable_type(struct be_adapter *adapter)
2372 {
2373         u8 page_data[PAGE_DATA_LEN];
2374         int status;
2375
2376         status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2377                                                    page_data);
2378         if (!status) {
2379                 switch (adapter->phy.interface_type) {
2380                 case PHY_TYPE_QSFP:
2381                         adapter->phy.cable_type =
2382                                 page_data[QSFP_PLUS_CABLE_TYPE_OFFSET];
2383                         break;
2384                 case PHY_TYPE_SFP_PLUS_10GB:
2385                         adapter->phy.cable_type =
2386                                 page_data[SFP_PLUS_CABLE_TYPE_OFFSET];
2387                         break;
2388                 default:
2389                         adapter->phy.cable_type = 0;
2390                         break;
2391                 }
2392         }
2393         return status;
2394 }
2395
2396 int be_cmd_query_sfp_info(struct be_adapter *adapter)
2397 {
2398         u8 page_data[PAGE_DATA_LEN];
2399         int status;
2400
2401         status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2402                                                    page_data);
2403         if (!status) {
2404                 strlcpy(adapter->phy.vendor_name, page_data +
2405                         SFP_VENDOR_NAME_OFFSET, SFP_VENDOR_NAME_LEN - 1);
2406                 strlcpy(adapter->phy.vendor_pn,
2407                         page_data + SFP_VENDOR_PN_OFFSET,
2408                         SFP_VENDOR_NAME_LEN - 1);
2409         }
2410
2411         return status;
2412 }
2413
2414 static int lancer_cmd_delete_object(struct be_adapter *adapter,
2415                                     const char *obj_name)
2416 {
2417         struct lancer_cmd_req_delete_object *req;
2418         struct be_mcc_wrb *wrb;
2419         int status;
2420
2421         spin_lock_bh(&adapter->mcc_lock);
2422
2423         wrb = wrb_from_mccq(adapter);
2424         if (!wrb) {
2425                 status = -EBUSY;
2426                 goto err;
2427         }
2428
2429         req = embedded_payload(wrb);
2430
2431         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2432                                OPCODE_COMMON_DELETE_OBJECT,
2433                                sizeof(*req), wrb, NULL);
2434
2435         strlcpy(req->object_name, obj_name, sizeof(req->object_name));
2436
2437         status = be_mcc_notify_wait(adapter);
2438 err:
2439         spin_unlock_bh(&adapter->mcc_lock);
2440         return status;
2441 }
2442
2443 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2444                            u32 data_size, u32 data_offset, const char *obj_name,
2445                            u32 *data_read, u32 *eof, u8 *addn_status)
2446 {
2447         struct be_mcc_wrb *wrb;
2448         struct lancer_cmd_req_read_object *req;
2449         struct lancer_cmd_resp_read_object *resp;
2450         int status;
2451
2452         spin_lock_bh(&adapter->mcc_lock);
2453
2454         wrb = wrb_from_mccq(adapter);
2455         if (!wrb) {
2456                 status = -EBUSY;
2457                 goto err_unlock;
2458         }
2459
2460         req = embedded_payload(wrb);
2461
2462         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2463                                OPCODE_COMMON_READ_OBJECT,
2464                                sizeof(struct lancer_cmd_req_read_object), wrb,
2465                                NULL);
2466
2467         req->desired_read_len = cpu_to_le32(data_size);
2468         req->read_offset = cpu_to_le32(data_offset);
2469         strcpy(req->object_name, obj_name);
2470         req->descriptor_count = cpu_to_le32(1);
2471         req->buf_len = cpu_to_le32(data_size);
2472         req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2473         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2474
2475         status = be_mcc_notify_wait(adapter);
2476
2477         resp = embedded_payload(wrb);
2478         if (!status) {
2479                 *data_read = le32_to_cpu(resp->actual_read_len);
2480                 *eof = le32_to_cpu(resp->eof);
2481         } else {
2482                 *addn_status = resp->additional_status;
2483         }
2484
2485 err_unlock:
2486         spin_unlock_bh(&adapter->mcc_lock);
2487         return status;
2488 }
2489
2490 static int be_cmd_write_flashrom(struct be_adapter *adapter,
2491                                  struct be_dma_mem *cmd, u32 flash_type,
2492                                  u32 flash_opcode, u32 img_offset, u32 buf_size)
2493 {
2494         struct be_mcc_wrb *wrb;
2495         struct be_cmd_write_flashrom *req;
2496         int status;
2497
2498         spin_lock_bh(&adapter->mcc_lock);
2499         adapter->flash_status = 0;
2500
2501         wrb = wrb_from_mccq(adapter);
2502         if (!wrb) {
2503                 status = -EBUSY;
2504                 goto err_unlock;
2505         }
2506         req = cmd->va;
2507
2508         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2509                                OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb,
2510                                cmd);
2511
2512         req->params.op_type = cpu_to_le32(flash_type);
2513         if (flash_type == OPTYPE_OFFSET_SPECIFIED)
2514                 req->params.offset = cpu_to_le32(img_offset);
2515
2516         req->params.op_code = cpu_to_le32(flash_opcode);
2517         req->params.data_buf_size = cpu_to_le32(buf_size);
2518
2519         status = be_mcc_notify(adapter);
2520         if (status)
2521                 goto err_unlock;
2522
2523         spin_unlock_bh(&adapter->mcc_lock);
2524
2525         if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2526                                          msecs_to_jiffies(40000)))
2527                 status = -ETIMEDOUT;
2528         else
2529                 status = adapter->flash_status;
2530
2531         return status;
2532
2533 err_unlock:
2534         spin_unlock_bh(&adapter->mcc_lock);
2535         return status;
2536 }
2537
2538 static int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2539                                 u16 img_optype, u32 img_offset, u32 crc_offset)
2540 {
2541         struct be_cmd_read_flash_crc *req;
2542         struct be_mcc_wrb *wrb;
2543         int status;
2544
2545         spin_lock_bh(&adapter->mcc_lock);
2546
2547         wrb = wrb_from_mccq(adapter);
2548         if (!wrb) {
2549                 status = -EBUSY;
2550                 goto err;
2551         }
2552         req = embedded_payload(wrb);
2553
2554         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2555                                OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2556                                wrb, NULL);
2557
2558         req->params.op_type = cpu_to_le32(img_optype);
2559         if (img_optype == OPTYPE_OFFSET_SPECIFIED)
2560                 req->params.offset = cpu_to_le32(img_offset + crc_offset);
2561         else
2562                 req->params.offset = cpu_to_le32(crc_offset);
2563
2564         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2565         req->params.data_buf_size = cpu_to_le32(0x4);
2566
2567         status = be_mcc_notify_wait(adapter);
2568         if (!status)
2569                 memcpy(flashed_crc, req->crc, 4);
2570
2571 err:
2572         spin_unlock_bh(&adapter->mcc_lock);
2573         return status;
2574 }
2575
2576 static char flash_cookie[2][16] = {"*** SE FLAS", "H DIRECTORY *** "};
2577
2578 static bool phy_flashing_required(struct be_adapter *adapter)
2579 {
2580         return (adapter->phy.phy_type == PHY_TYPE_TN_8022 &&
2581                 adapter->phy.interface_type == PHY_TYPE_BASET_10GB);
2582 }
2583
2584 static bool is_comp_in_ufi(struct be_adapter *adapter,
2585                            struct flash_section_info *fsec, int type)
2586 {
2587         int i = 0, img_type = 0;
2588         struct flash_section_info_g2 *fsec_g2 = NULL;
2589
2590         if (BE2_chip(adapter))
2591                 fsec_g2 = (struct flash_section_info_g2 *)fsec;
2592
2593         for (i = 0; i < MAX_FLASH_COMP; i++) {
2594                 if (fsec_g2)
2595                         img_type = le32_to_cpu(fsec_g2->fsec_entry[i].type);
2596                 else
2597                         img_type = le32_to_cpu(fsec->fsec_entry[i].type);
2598
2599                 if (img_type == type)
2600                         return true;
2601         }
2602         return false;
2603 }
2604
2605 static struct flash_section_info *get_fsec_info(struct be_adapter *adapter,
2606                                                 int header_size,
2607                                                 const struct firmware *fw)
2608 {
2609         struct flash_section_info *fsec = NULL;
2610         const u8 *p = fw->data;
2611
2612         p += header_size;
2613         while (p < (fw->data + fw->size)) {
2614                 fsec = (struct flash_section_info *)p;
2615                 if (!memcmp(flash_cookie, fsec->cookie, sizeof(flash_cookie)))
2616                         return fsec;
2617                 p += 32;
2618         }
2619         return NULL;
2620 }
2621
2622 static int be_check_flash_crc(struct be_adapter *adapter, const u8 *p,
2623                               u32 img_offset, u32 img_size, int hdr_size,
2624                               u16 img_optype, bool *crc_match)
2625 {
2626         u32 crc_offset;
2627         int status;
2628         u8 crc[4];
2629
2630         status = be_cmd_get_flash_crc(adapter, crc, img_optype, img_offset,
2631                                       img_size - 4);
2632         if (status)
2633                 return status;
2634
2635         crc_offset = hdr_size + img_offset + img_size - 4;
2636
2637         /* Skip flashing, if crc of flashed region matches */
2638         if (!memcmp(crc, p + crc_offset, 4))
2639                 *crc_match = true;
2640         else
2641                 *crc_match = false;
2642
2643         return status;
2644 }
2645
2646 static int be_flash(struct be_adapter *adapter, const u8 *img,
2647                     struct be_dma_mem *flash_cmd, int optype, int img_size,
2648                     u32 img_offset)
2649 {
2650         u32 flash_op, num_bytes, total_bytes = img_size, bytes_sent = 0;
2651         struct be_cmd_write_flashrom *req = flash_cmd->va;
2652         int status;
2653
2654         while (total_bytes) {
2655                 num_bytes = min_t(u32, 32 * 1024, total_bytes);
2656
2657                 total_bytes -= num_bytes;
2658
2659                 if (!total_bytes) {
2660                         if (optype == OPTYPE_PHY_FW)
2661                                 flash_op = FLASHROM_OPER_PHY_FLASH;
2662                         else
2663                                 flash_op = FLASHROM_OPER_FLASH;
2664                 } else {
2665                         if (optype == OPTYPE_PHY_FW)
2666                                 flash_op = FLASHROM_OPER_PHY_SAVE;
2667                         else
2668                                 flash_op = FLASHROM_OPER_SAVE;
2669                 }
2670
2671                 memcpy(req->data_buf, img, num_bytes);
2672                 img += num_bytes;
2673                 status = be_cmd_write_flashrom(adapter, flash_cmd, optype,
2674                                                flash_op, img_offset +
2675                                                bytes_sent, num_bytes);
2676                 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST &&
2677                     optype == OPTYPE_PHY_FW)
2678                         break;
2679                 else if (status)
2680                         return status;
2681
2682                 bytes_sent += num_bytes;
2683         }
2684         return 0;
2685 }
2686
2687 /* For BE2, BE3 and BE3-R */
2688 static int be_flash_BEx(struct be_adapter *adapter,
2689                         const struct firmware *fw,
2690                         struct be_dma_mem *flash_cmd, int num_of_images)
2691 {
2692         int img_hdrs_size = (num_of_images * sizeof(struct image_hdr));
2693         struct device *dev = &adapter->pdev->dev;
2694         struct flash_section_info *fsec = NULL;
2695         int status, i, filehdr_size, num_comp;
2696         const struct flash_comp *pflashcomp;
2697         bool crc_match;
2698         const u8 *p;
2699
2700         struct flash_comp gen3_flash_types[] = {
2701                 { BE3_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE,
2702                         BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI},
2703                 { BE3_REDBOOT_START, OPTYPE_REDBOOT,
2704                         BE3_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE},
2705                 { BE3_ISCSI_BIOS_START, OPTYPE_BIOS,
2706                         BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI},
2707                 { BE3_PXE_BIOS_START, OPTYPE_PXE_BIOS,
2708                         BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE},
2709                 { BE3_FCOE_BIOS_START, OPTYPE_FCOE_BIOS,
2710                         BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE},
2711                 { BE3_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP,
2712                         BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI},
2713                 { BE3_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE,
2714                         BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE},
2715                 { BE3_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP,
2716                         BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE},
2717                 { BE3_NCSI_START, OPTYPE_NCSI_FW,
2718                         BE3_NCSI_COMP_MAX_SIZE, IMAGE_NCSI},
2719                 { BE3_PHY_FW_START, OPTYPE_PHY_FW,
2720                         BE3_PHY_FW_COMP_MAX_SIZE, IMAGE_FIRMWARE_PHY}
2721         };
2722
2723         struct flash_comp gen2_flash_types[] = {
2724                 { BE2_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE,
2725                         BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI},
2726                 { BE2_REDBOOT_START, OPTYPE_REDBOOT,
2727                         BE2_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE},
2728                 { BE2_ISCSI_BIOS_START, OPTYPE_BIOS,
2729                         BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI},
2730                 { BE2_PXE_BIOS_START, OPTYPE_PXE_BIOS,
2731                         BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE},
2732                 { BE2_FCOE_BIOS_START, OPTYPE_FCOE_BIOS,
2733                         BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE},
2734                 { BE2_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP,
2735                         BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI},
2736                 { BE2_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE,
2737                         BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE},
2738                 { BE2_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP,
2739                          BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE}
2740         };
2741
2742         if (BE3_chip(adapter)) {
2743                 pflashcomp = gen3_flash_types;
2744                 filehdr_size = sizeof(struct flash_file_hdr_g3);
2745                 num_comp = ARRAY_SIZE(gen3_flash_types);
2746         } else {
2747                 pflashcomp = gen2_flash_types;
2748                 filehdr_size = sizeof(struct flash_file_hdr_g2);
2749                 num_comp = ARRAY_SIZE(gen2_flash_types);
2750                 img_hdrs_size = 0;
2751         }
2752
2753         /* Get flash section info*/
2754         fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw);
2755         if (!fsec) {
2756                 dev_err(dev, "Invalid Cookie. FW image may be corrupted\n");
2757                 return -1;
2758         }
2759         for (i = 0; i < num_comp; i++) {
2760                 if (!is_comp_in_ufi(adapter, fsec, pflashcomp[i].img_type))
2761                         continue;
2762
2763                 if ((pflashcomp[i].optype == OPTYPE_NCSI_FW) &&
2764                     memcmp(adapter->fw_ver, "3.102.148.0", 11) < 0)
2765                         continue;
2766
2767                 if (pflashcomp[i].optype == OPTYPE_PHY_FW  &&
2768                     !phy_flashing_required(adapter))
2769                         continue;
2770
2771                 if (pflashcomp[i].optype == OPTYPE_REDBOOT) {
2772                         status = be_check_flash_crc(adapter, fw->data,
2773                                                     pflashcomp[i].offset,
2774                                                     pflashcomp[i].size,
2775                                                     filehdr_size +
2776                                                     img_hdrs_size,
2777                                                     OPTYPE_REDBOOT, &crc_match);
2778                         if (status) {
2779                                 dev_err(dev,
2780                                         "Could not get CRC for 0x%x region\n",
2781                                         pflashcomp[i].optype);
2782                                 continue;
2783                         }
2784
2785                         if (crc_match)
2786                                 continue;
2787                 }
2788
2789                 p = fw->data + filehdr_size + pflashcomp[i].offset +
2790                         img_hdrs_size;
2791                 if (p + pflashcomp[i].size > fw->data + fw->size)
2792                         return -1;
2793
2794                 status = be_flash(adapter, p, flash_cmd, pflashcomp[i].optype,
2795                                   pflashcomp[i].size, 0);
2796                 if (status) {
2797                         dev_err(dev, "Flashing section type 0x%x failed\n",
2798                                 pflashcomp[i].img_type);
2799                         return status;
2800                 }
2801         }
2802         return 0;
2803 }
2804
2805 static u16 be_get_img_optype(struct flash_section_entry fsec_entry)
2806 {
2807         u32 img_type = le32_to_cpu(fsec_entry.type);
2808         u16 img_optype = le16_to_cpu(fsec_entry.optype);
2809
2810         if (img_optype != 0xFFFF)
2811                 return img_optype;
2812
2813         switch (img_type) {
2814         case IMAGE_FIRMWARE_ISCSI:
2815                 img_optype = OPTYPE_ISCSI_ACTIVE;
2816                 break;
2817         case IMAGE_BOOT_CODE:
2818                 img_optype = OPTYPE_REDBOOT;
2819                 break;
2820         case IMAGE_OPTION_ROM_ISCSI:
2821                 img_optype = OPTYPE_BIOS;
2822                 break;
2823         case IMAGE_OPTION_ROM_PXE:
2824                 img_optype = OPTYPE_PXE_BIOS;
2825                 break;
2826         case IMAGE_OPTION_ROM_FCOE:
2827                 img_optype = OPTYPE_FCOE_BIOS;
2828                 break;
2829         case IMAGE_FIRMWARE_BACKUP_ISCSI:
2830                 img_optype = OPTYPE_ISCSI_BACKUP;
2831                 break;
2832         case IMAGE_NCSI:
2833                 img_optype = OPTYPE_NCSI_FW;
2834                 break;
2835         case IMAGE_FLASHISM_JUMPVECTOR:
2836                 img_optype = OPTYPE_FLASHISM_JUMPVECTOR;
2837                 break;
2838         case IMAGE_FIRMWARE_PHY:
2839                 img_optype = OPTYPE_SH_PHY_FW;
2840                 break;
2841         case IMAGE_REDBOOT_DIR:
2842                 img_optype = OPTYPE_REDBOOT_DIR;
2843                 break;
2844         case IMAGE_REDBOOT_CONFIG:
2845                 img_optype = OPTYPE_REDBOOT_CONFIG;
2846                 break;
2847         case IMAGE_UFI_DIR:
2848                 img_optype = OPTYPE_UFI_DIR;
2849                 break;
2850         default:
2851                 break;
2852         }
2853
2854         return img_optype;
2855 }
2856
2857 static int be_flash_skyhawk(struct be_adapter *adapter,
2858                             const struct firmware *fw,
2859                             struct be_dma_mem *flash_cmd, int num_of_images)
2860 {
2861         int img_hdrs_size = num_of_images * sizeof(struct image_hdr);
2862         bool crc_match, old_fw_img, flash_offset_support = true;
2863         struct device *dev = &adapter->pdev->dev;
2864         struct flash_section_info *fsec = NULL;
2865         u32 img_offset, img_size, img_type;
2866         u16 img_optype, flash_optype;
2867         int status, i, filehdr_size;
2868         const u8 *p;
2869
2870         filehdr_size = sizeof(struct flash_file_hdr_g3);
2871         fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw);
2872         if (!fsec) {
2873                 dev_err(dev, "Invalid Cookie. FW image may be corrupted\n");
2874                 return -EINVAL;
2875         }
2876
2877 retry_flash:
2878         for (i = 0; i < le32_to_cpu(fsec->fsec_hdr.num_images); i++) {
2879                 img_offset = le32_to_cpu(fsec->fsec_entry[i].offset);
2880                 img_size   = le32_to_cpu(fsec->fsec_entry[i].pad_size);
2881                 img_type   = le32_to_cpu(fsec->fsec_entry[i].type);
2882                 img_optype = be_get_img_optype(fsec->fsec_entry[i]);
2883                 old_fw_img = fsec->fsec_entry[i].optype == 0xFFFF;
2884
2885                 if (img_optype == 0xFFFF)
2886                         continue;
2887
2888                 if (flash_offset_support)
2889                         flash_optype = OPTYPE_OFFSET_SPECIFIED;
2890                 else
2891                         flash_optype = img_optype;
2892
2893                 /* Don't bother verifying CRC if an old FW image is being
2894                  * flashed
2895                  */
2896                 if (old_fw_img)
2897                         goto flash;
2898
2899                 status = be_check_flash_crc(adapter, fw->data, img_offset,
2900                                             img_size, filehdr_size +
2901                                             img_hdrs_size, flash_optype,
2902                                             &crc_match);
2903                 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST ||
2904                     base_status(status) == MCC_STATUS_ILLEGAL_FIELD) {
2905                         /* The current FW image on the card does not support
2906                          * OFFSET based flashing. Retry using older mechanism
2907                          * of OPTYPE based flashing
2908                          */
2909                         if (flash_optype == OPTYPE_OFFSET_SPECIFIED) {
2910                                 flash_offset_support = false;
2911                                 goto retry_flash;
2912                         }
2913
2914                         /* The current FW image on the card does not recognize
2915                          * the new FLASH op_type. The FW download is partially
2916                          * complete. Reboot the server now to enable FW image
2917                          * to recognize the new FLASH op_type. To complete the
2918                          * remaining process, download the same FW again after
2919                          * the reboot.
2920                          */
2921                         dev_err(dev, "Flash incomplete. Reset the server\n");
2922                         dev_err(dev, "Download FW image again after reset\n");
2923                         return -EAGAIN;
2924                 } else if (status) {
2925                         dev_err(dev, "Could not get CRC for 0x%x region\n",
2926                                 img_optype);
2927                         return -EFAULT;
2928                 }
2929
2930                 if (crc_match)
2931                         continue;
2932
2933 flash:
2934                 p = fw->data + filehdr_size + img_offset + img_hdrs_size;
2935                 if (p + img_size > fw->data + fw->size)
2936                         return -1;
2937
2938                 status = be_flash(adapter, p, flash_cmd, flash_optype, img_size,
2939                                   img_offset);
2940
2941                 /* The current FW image on the card does not support OFFSET
2942                  * based flashing. Retry using older mechanism of OPTYPE based
2943                  * flashing
2944                  */
2945                 if (base_status(status) == MCC_STATUS_ILLEGAL_FIELD &&
2946                     flash_optype == OPTYPE_OFFSET_SPECIFIED) {
2947                         flash_offset_support = false;
2948                         goto retry_flash;
2949                 }
2950
2951                 /* For old FW images ignore ILLEGAL_FIELD error or errors on
2952                  * UFI_DIR region
2953                  */
2954                 if (old_fw_img &&
2955                     (base_status(status) == MCC_STATUS_ILLEGAL_FIELD ||
2956                      (img_optype == OPTYPE_UFI_DIR &&
2957                       base_status(status) == MCC_STATUS_FAILED))) {
2958                         continue;
2959                 } else if (status) {
2960                         dev_err(dev, "Flashing section type 0x%x failed\n",
2961                                 img_type);
2962                         return -EFAULT;
2963                 }
2964         }
2965         return 0;
2966 }
2967
2968 int lancer_fw_download(struct be_adapter *adapter,
2969                        const struct firmware *fw)
2970 {
2971         struct device *dev = &adapter->pdev->dev;
2972         struct be_dma_mem flash_cmd;
2973         const u8 *data_ptr = NULL;
2974         u8 *dest_image_ptr = NULL;
2975         size_t image_size = 0;
2976         u32 chunk_size = 0;
2977         u32 data_written = 0;
2978         u32 offset = 0;
2979         int status = 0;
2980         u8 add_status = 0;
2981         u8 change_status;
2982
2983         if (!IS_ALIGNED(fw->size, sizeof(u32))) {
2984                 dev_err(dev, "FW image size should be multiple of 4\n");
2985                 return -EINVAL;
2986         }
2987
2988         flash_cmd.size = sizeof(struct lancer_cmd_req_write_object)
2989                                 + LANCER_FW_DOWNLOAD_CHUNK;
2990         flash_cmd.va = dma_zalloc_coherent(dev, flash_cmd.size,
2991                                            &flash_cmd.dma, GFP_KERNEL);
2992         if (!flash_cmd.va)
2993                 return -ENOMEM;
2994
2995         dest_image_ptr = flash_cmd.va +
2996                                 sizeof(struct lancer_cmd_req_write_object);
2997         image_size = fw->size;
2998         data_ptr = fw->data;
2999
3000         while (image_size) {
3001                 chunk_size = min_t(u32, image_size, LANCER_FW_DOWNLOAD_CHUNK);
3002
3003                 /* Copy the image chunk content. */
3004                 memcpy(dest_image_ptr, data_ptr, chunk_size);
3005
3006                 status = lancer_cmd_write_object(adapter, &flash_cmd,
3007                                                  chunk_size, offset,
3008                                                  LANCER_FW_DOWNLOAD_LOCATION,
3009                                                  &data_written, &change_status,
3010                                                  &add_status);
3011                 if (status)
3012                         break;
3013
3014                 offset += data_written;
3015                 data_ptr += data_written;
3016                 image_size -= data_written;
3017         }
3018
3019         if (!status) {
3020                 /* Commit the FW written */
3021                 status = lancer_cmd_write_object(adapter, &flash_cmd,
3022                                                  0, offset,
3023                                                  LANCER_FW_DOWNLOAD_LOCATION,
3024                                                  &data_written, &change_status,
3025                                                  &add_status);
3026         }
3027
3028         dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma);
3029         if (status) {
3030                 dev_err(dev, "Firmware load error\n");
3031                 return be_cmd_status(status);
3032         }
3033
3034         dev_info(dev, "Firmware flashed successfully\n");
3035
3036         if (change_status == LANCER_FW_RESET_NEEDED) {
3037                 dev_info(dev, "Resetting adapter to activate new FW\n");
3038                 status = lancer_physdev_ctrl(adapter,
3039                                              PHYSDEV_CONTROL_FW_RESET_MASK);
3040                 if (status) {
3041                         dev_err(dev, "Adapter busy, could not reset FW\n");
3042                         dev_err(dev, "Reboot server to activate new FW\n");
3043                 }
3044         } else if (change_status != LANCER_NO_RESET_NEEDED) {
3045                 dev_info(dev, "Reboot server to activate new FW\n");
3046         }
3047
3048         return 0;
3049 }
3050
3051 /* Check if the flash image file is compatible with the adapter that
3052  * is being flashed.
3053  */
3054 static bool be_check_ufi_compatibility(struct be_adapter *adapter,
3055                                        struct flash_file_hdr_g3 *fhdr)
3056 {
3057         if (!fhdr) {
3058                 dev_err(&adapter->pdev->dev, "Invalid FW UFI file");
3059                 return false;
3060         }
3061
3062         /* First letter of the build version is used to identify
3063          * which chip this image file is meant for.
3064          */
3065         switch (fhdr->build[0]) {
3066         case BLD_STR_UFI_TYPE_SH:
3067                 if (!skyhawk_chip(adapter))
3068                         return false;
3069                 break;
3070         case BLD_STR_UFI_TYPE_BE3:
3071                 if (!BE3_chip(adapter))
3072                         return false;
3073                 break;
3074         case BLD_STR_UFI_TYPE_BE2:
3075                 if (!BE2_chip(adapter))
3076                         return false;
3077                 break;
3078         default:
3079                 return false;
3080         }
3081
3082         /* In BE3 FW images the "asic_type_rev" field doesn't track the
3083          * asic_rev of the chips it is compatible with.
3084          * When asic_type_rev is 0 the image is compatible only with
3085          * pre-BE3-R chips (asic_rev < 0x10)
3086          */
3087         if (BEx_chip(adapter) && fhdr->asic_type_rev == 0)
3088                 return adapter->asic_rev < 0x10;
3089         else
3090                 return (fhdr->asic_type_rev >= adapter->asic_rev);
3091 }
3092
3093 int be_fw_download(struct be_adapter *adapter, const struct firmware *fw)
3094 {
3095         struct device *dev = &adapter->pdev->dev;
3096         struct flash_file_hdr_g3 *fhdr3;
3097         struct image_hdr *img_hdr_ptr;
3098         int status = 0, i, num_imgs;
3099         struct be_dma_mem flash_cmd;
3100
3101         fhdr3 = (struct flash_file_hdr_g3 *)fw->data;
3102         if (!be_check_ufi_compatibility(adapter, fhdr3)) {
3103                 dev_err(dev, "Flash image is not compatible with adapter\n");
3104                 return -EINVAL;
3105         }
3106
3107         flash_cmd.size = sizeof(struct be_cmd_write_flashrom);
3108         flash_cmd.va = dma_zalloc_coherent(dev, flash_cmd.size, &flash_cmd.dma,
3109                                            GFP_KERNEL);
3110         if (!flash_cmd.va)
3111                 return -ENOMEM;
3112
3113         num_imgs = le32_to_cpu(fhdr3->num_imgs);
3114         for (i = 0; i < num_imgs; i++) {
3115                 img_hdr_ptr = (struct image_hdr *)(fw->data +
3116                                 (sizeof(struct flash_file_hdr_g3) +
3117                                  i * sizeof(struct image_hdr)));
3118                 if (!BE2_chip(adapter) &&
3119                     le32_to_cpu(img_hdr_ptr->imageid) != 1)
3120                         continue;
3121
3122                 if (skyhawk_chip(adapter))
3123                         status = be_flash_skyhawk(adapter, fw, &flash_cmd,
3124                                                   num_imgs);
3125                 else
3126                         status = be_flash_BEx(adapter, fw, &flash_cmd,
3127                                               num_imgs);
3128         }
3129
3130         dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma);
3131         if (!status)
3132                 dev_info(dev, "Firmware flashed successfully\n");
3133
3134         return status;
3135 }
3136
3137 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
3138                             struct be_dma_mem *nonemb_cmd)
3139 {
3140         struct be_mcc_wrb *wrb;
3141         struct be_cmd_req_acpi_wol_magic_config *req;
3142         int status;
3143
3144         spin_lock_bh(&adapter->mcc_lock);
3145
3146         wrb = wrb_from_mccq(adapter);
3147         if (!wrb) {
3148                 status = -EBUSY;
3149                 goto err;
3150         }
3151         req = nonemb_cmd->va;
3152
3153         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
3154                                OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req),
3155                                wrb, nonemb_cmd);
3156         memcpy(req->magic_mac, mac, ETH_ALEN);
3157
3158         status = be_mcc_notify_wait(adapter);
3159
3160 err:
3161         spin_unlock_bh(&adapter->mcc_lock);
3162         return status;
3163 }
3164
3165 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
3166                         u8 loopback_type, u8 enable)
3167 {
3168         struct be_mcc_wrb *wrb;
3169         struct be_cmd_req_set_lmode *req;
3170         int status;
3171
3172         spin_lock_bh(&adapter->mcc_lock);
3173
3174         wrb = wrb_from_mccq(adapter);
3175         if (!wrb) {
3176                 status = -EBUSY;
3177                 goto err_unlock;
3178         }
3179
3180         req = embedded_payload(wrb);
3181
3182         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
3183                                OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req),
3184                                wrb, NULL);
3185
3186         req->src_port = port_num;
3187         req->dest_port = port_num;
3188         req->loopback_type = loopback_type;
3189         req->loopback_state = enable;
3190
3191         status = be_mcc_notify(adapter);
3192         if (status)
3193                 goto err_unlock;
3194
3195         spin_unlock_bh(&adapter->mcc_lock);
3196
3197         if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
3198                                          msecs_to_jiffies(SET_LB_MODE_TIMEOUT)))
3199                 status = -ETIMEDOUT;
3200
3201         return status;
3202
3203 err_unlock:
3204         spin_unlock_bh(&adapter->mcc_lock);
3205         return status;
3206 }
3207
3208 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
3209                          u32 loopback_type, u32 pkt_size, u32 num_pkts,
3210                          u64 pattern)
3211 {
3212         struct be_mcc_wrb *wrb;
3213         struct be_cmd_req_loopback_test *req;
3214         struct be_cmd_resp_loopback_test *resp;
3215         int status;
3216
3217         spin_lock_bh(&adapter->mcc_lock);
3218
3219         wrb = wrb_from_mccq(adapter);
3220         if (!wrb) {
3221                 status = -EBUSY;
3222                 goto err;
3223         }
3224
3225         req = embedded_payload(wrb);
3226
3227         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
3228                                OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb,
3229                                NULL);
3230
3231         req->hdr.timeout = cpu_to_le32(15);
3232         req->pattern = cpu_to_le64(pattern);
3233         req->src_port = cpu_to_le32(port_num);
3234         req->dest_port = cpu_to_le32(port_num);
3235         req->pkt_size = cpu_to_le32(pkt_size);
3236         req->num_pkts = cpu_to_le32(num_pkts);
3237         req->loopback_type = cpu_to_le32(loopback_type);
3238
3239         status = be_mcc_notify(adapter);
3240         if (status)
3241                 goto err;
3242
3243         spin_unlock_bh(&adapter->mcc_lock);
3244
3245         wait_for_completion(&adapter->et_cmd_compl);
3246         resp = embedded_payload(wrb);
3247         status = le32_to_cpu(resp->status);
3248
3249         return status;
3250 err:
3251         spin_unlock_bh(&adapter->mcc_lock);
3252         return status;
3253 }
3254
3255 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
3256                         u32 byte_cnt, struct be_dma_mem *cmd)
3257 {
3258         struct be_mcc_wrb *wrb;
3259         struct be_cmd_req_ddrdma_test *req;
3260         int status;
3261         int i, j = 0;
3262
3263         spin_lock_bh(&adapter->mcc_lock);
3264
3265         wrb = wrb_from_mccq(adapter);
3266         if (!wrb) {
3267                 status = -EBUSY;
3268                 goto err;
3269         }
3270         req = cmd->va;
3271         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
3272                                OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb,
3273                                cmd);
3274
3275         req->pattern = cpu_to_le64(pattern);
3276         req->byte_count = cpu_to_le32(byte_cnt);
3277         for (i = 0; i < byte_cnt; i++) {
3278                 req->snd_buff[i] = (u8)(pattern >> (j*8));
3279                 j++;
3280                 if (j > 7)
3281                         j = 0;
3282         }
3283
3284         status = be_mcc_notify_wait(adapter);
3285
3286         if (!status) {
3287                 struct be_cmd_resp_ddrdma_test *resp;
3288
3289                 resp = cmd->va;
3290                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
3291                     resp->snd_err) {
3292                         status = -1;
3293                 }
3294         }
3295
3296 err:
3297         spin_unlock_bh(&adapter->mcc_lock);
3298         return status;
3299 }
3300
3301 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
3302                             struct be_dma_mem *nonemb_cmd)
3303 {
3304         struct be_mcc_wrb *wrb;
3305         struct be_cmd_req_seeprom_read *req;
3306         int status;
3307
3308         spin_lock_bh(&adapter->mcc_lock);
3309
3310         wrb = wrb_from_mccq(adapter);
3311         if (!wrb) {
3312                 status = -EBUSY;
3313                 goto err;
3314         }
3315         req = nonemb_cmd->va;
3316
3317         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3318                                OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
3319                                nonemb_cmd);
3320
3321         status = be_mcc_notify_wait(adapter);
3322
3323 err:
3324         spin_unlock_bh(&adapter->mcc_lock);
3325         return status;
3326 }
3327
3328 int be_cmd_get_phy_info(struct be_adapter *adapter)
3329 {
3330         struct be_mcc_wrb *wrb;
3331         struct be_cmd_req_get_phy_info *req;
3332         struct be_dma_mem cmd;
3333         int status;
3334
3335         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
3336                             CMD_SUBSYSTEM_COMMON))
3337                 return -EPERM;
3338
3339         spin_lock_bh(&adapter->mcc_lock);
3340
3341         wrb = wrb_from_mccq(adapter);
3342         if (!wrb) {
3343                 status = -EBUSY;
3344                 goto err;
3345         }
3346         cmd.size = sizeof(struct be_cmd_req_get_phy_info);
3347         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3348                                      GFP_ATOMIC);
3349         if (!cmd.va) {
3350                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3351                 status = -ENOMEM;
3352                 goto err;
3353         }
3354
3355         req = cmd.va;
3356
3357         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3358                                OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
3359                                wrb, &cmd);
3360
3361         status = be_mcc_notify_wait(adapter);
3362         if (!status) {
3363                 struct be_phy_info *resp_phy_info =
3364                                 cmd.va + sizeof(struct be_cmd_req_hdr);
3365
3366                 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
3367                 adapter->phy.interface_type =
3368                         le16_to_cpu(resp_phy_info->interface_type);
3369                 adapter->phy.auto_speeds_supported =
3370                         le16_to_cpu(resp_phy_info->auto_speeds_supported);
3371                 adapter->phy.fixed_speeds_supported =
3372                         le16_to_cpu(resp_phy_info->fixed_speeds_supported);
3373                 adapter->phy.misc_params =
3374                         le32_to_cpu(resp_phy_info->misc_params);
3375
3376                 if (BE2_chip(adapter)) {
3377                         adapter->phy.fixed_speeds_supported =
3378                                 BE_SUPPORTED_SPEED_10GBPS |
3379                                 BE_SUPPORTED_SPEED_1GBPS;
3380                 }
3381         }
3382         dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
3383 err:
3384         spin_unlock_bh(&adapter->mcc_lock);
3385         return status;
3386 }
3387
3388 static int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
3389 {
3390         struct be_mcc_wrb *wrb;
3391         struct be_cmd_req_set_qos *req;
3392         int status;
3393
3394         spin_lock_bh(&adapter->mcc_lock);
3395
3396         wrb = wrb_from_mccq(adapter);
3397         if (!wrb) {
3398                 status = -EBUSY;
3399                 goto err;
3400         }
3401
3402         req = embedded_payload(wrb);
3403
3404         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3405                                OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
3406
3407         req->hdr.domain = domain;
3408         req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
3409         req->max_bps_nic = cpu_to_le32(bps);
3410
3411         status = be_mcc_notify_wait(adapter);
3412
3413 err:
3414         spin_unlock_bh(&adapter->mcc_lock);
3415         return status;
3416 }
3417
3418 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
3419 {
3420         struct be_mcc_wrb *wrb;
3421         struct be_cmd_req_cntl_attribs *req;
3422         struct be_cmd_resp_cntl_attribs *resp;
3423         int status, i;
3424         int payload_len = max(sizeof(*req), sizeof(*resp));
3425         struct mgmt_controller_attrib *attribs;
3426         struct be_dma_mem attribs_cmd;
3427         u32 *serial_num;
3428
3429         if (mutex_lock_interruptible(&adapter->mbox_lock))
3430                 return -1;
3431
3432         memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
3433         attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
3434         attribs_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3435                                              attribs_cmd.size,
3436                                              &attribs_cmd.dma, GFP_ATOMIC);
3437         if (!attribs_cmd.va) {
3438                 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
3439                 status = -ENOMEM;
3440                 goto err;
3441         }
3442
3443         wrb = wrb_from_mbox(adapter);
3444         if (!wrb) {
3445                 status = -EBUSY;
3446                 goto err;
3447         }
3448         req = attribs_cmd.va;
3449
3450         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3451                                OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len,
3452                                wrb, &attribs_cmd);
3453
3454         status = be_mbox_notify_wait(adapter);
3455         if (!status) {
3456                 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
3457                 adapter->hba_port_num = attribs->hba_attribs.phy_port;
3458                 adapter->pci_func_num = attribs->pci_func_num;
3459                 serial_num = attribs->hba_attribs.controller_serial_number;
3460                 for (i = 0; i < CNTL_SERIAL_NUM_WORDS; i++)
3461                         adapter->serial_num[i] = le32_to_cpu(serial_num[i]) &
3462                                 (BIT_MASK(16) - 1);
3463         }
3464
3465 err:
3466         mutex_unlock(&adapter->mbox_lock);
3467         if (attribs_cmd.va)
3468                 dma_free_coherent(&adapter->pdev->dev, attribs_cmd.size,
3469                                   attribs_cmd.va, attribs_cmd.dma);
3470         return status;
3471 }
3472
3473 /* Uses mbox */
3474 int be_cmd_req_native_mode(struct be_adapter *adapter)
3475 {
3476         struct be_mcc_wrb *wrb;
3477         struct be_cmd_req_set_func_cap *req;
3478         int status;
3479
3480         if (mutex_lock_interruptible(&adapter->mbox_lock))
3481                 return -1;
3482
3483         wrb = wrb_from_mbox(adapter);
3484         if (!wrb) {
3485                 status = -EBUSY;
3486                 goto err;
3487         }
3488
3489         req = embedded_payload(wrb);
3490
3491         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3492                                OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP,
3493                                sizeof(*req), wrb, NULL);
3494
3495         req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
3496                                 CAPABILITY_BE3_NATIVE_ERX_API);
3497         req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
3498
3499         status = be_mbox_notify_wait(adapter);
3500         if (!status) {
3501                 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
3502
3503                 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
3504                                         CAPABILITY_BE3_NATIVE_ERX_API;
3505                 if (!adapter->be3_native)
3506                         dev_warn(&adapter->pdev->dev,
3507                                  "adapter not in advanced mode\n");
3508         }
3509 err:
3510         mutex_unlock(&adapter->mbox_lock);
3511         return status;
3512 }
3513
3514 /* Get privilege(s) for a function */
3515 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
3516                              u32 domain)
3517 {
3518         struct be_mcc_wrb *wrb;
3519         struct be_cmd_req_get_fn_privileges *req;
3520         int status;
3521
3522         spin_lock_bh(&adapter->mcc_lock);
3523
3524         wrb = wrb_from_mccq(adapter);
3525         if (!wrb) {
3526                 status = -EBUSY;
3527                 goto err;
3528         }
3529
3530         req = embedded_payload(wrb);
3531
3532         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3533                                OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
3534                                wrb, NULL);
3535
3536         req->hdr.domain = domain;
3537
3538         status = be_mcc_notify_wait(adapter);
3539         if (!status) {
3540                 struct be_cmd_resp_get_fn_privileges *resp =
3541                                                 embedded_payload(wrb);
3542
3543                 *privilege = le32_to_cpu(resp->privilege_mask);
3544
3545                 /* In UMC mode FW does not return right privileges.
3546                  * Override with correct privilege equivalent to PF.
3547                  */
3548                 if (BEx_chip(adapter) && be_is_mc(adapter) &&
3549                     be_physfn(adapter))
3550                         *privilege = MAX_PRIVILEGES;
3551         }
3552
3553 err:
3554         spin_unlock_bh(&adapter->mcc_lock);
3555         return status;
3556 }
3557
3558 /* Set privilege(s) for a function */
3559 int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
3560                              u32 domain)
3561 {
3562         struct be_mcc_wrb *wrb;
3563         struct be_cmd_req_set_fn_privileges *req;
3564         int status;
3565
3566         spin_lock_bh(&adapter->mcc_lock);
3567
3568         wrb = wrb_from_mccq(adapter);
3569         if (!wrb) {
3570                 status = -EBUSY;
3571                 goto err;
3572         }
3573
3574         req = embedded_payload(wrb);
3575         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3576                                OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
3577                                wrb, NULL);
3578         req->hdr.domain = domain;
3579         if (lancer_chip(adapter))
3580                 req->privileges_lancer = cpu_to_le32(privileges);
3581         else
3582                 req->privileges = cpu_to_le32(privileges);
3583
3584         status = be_mcc_notify_wait(adapter);
3585 err:
3586         spin_unlock_bh(&adapter->mcc_lock);
3587         return status;
3588 }
3589
3590 /* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
3591  * pmac_id_valid: false => pmac_id or MAC address is requested.
3592  *                If pmac_id is returned, pmac_id_valid is returned as true
3593  */
3594 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
3595                              bool *pmac_id_valid, u32 *pmac_id, u32 if_handle,
3596                              u8 domain)
3597 {
3598         struct be_mcc_wrb *wrb;
3599         struct be_cmd_req_get_mac_list *req;
3600         int status;
3601         int mac_count;
3602         struct be_dma_mem get_mac_list_cmd;
3603         int i;
3604
3605         memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
3606         get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
3607         get_mac_list_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3608                                                   get_mac_list_cmd.size,
3609                                                   &get_mac_list_cmd.dma,
3610                                                   GFP_ATOMIC);
3611
3612         if (!get_mac_list_cmd.va) {
3613                 dev_err(&adapter->pdev->dev,
3614                         "Memory allocation failure during GET_MAC_LIST\n");
3615                 return -ENOMEM;
3616         }
3617
3618         spin_lock_bh(&adapter->mcc_lock);
3619
3620         wrb = wrb_from_mccq(adapter);
3621         if (!wrb) {
3622                 status = -EBUSY;
3623                 goto out;
3624         }
3625
3626         req = get_mac_list_cmd.va;
3627
3628         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3629                                OPCODE_COMMON_GET_MAC_LIST,
3630                                get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
3631         req->hdr.domain = domain;
3632         req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
3633         if (*pmac_id_valid) {
3634                 req->mac_id = cpu_to_le32(*pmac_id);
3635                 req->iface_id = cpu_to_le16(if_handle);
3636                 req->perm_override = 0;
3637         } else {
3638                 req->perm_override = 1;
3639         }
3640
3641         status = be_mcc_notify_wait(adapter);
3642         if (!status) {
3643                 struct be_cmd_resp_get_mac_list *resp =
3644                                                 get_mac_list_cmd.va;
3645
3646                 if (*pmac_id_valid) {
3647                         memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
3648                                ETH_ALEN);
3649                         goto out;
3650                 }
3651
3652                 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
3653                 /* Mac list returned could contain one or more active mac_ids
3654                  * or one or more true or pseudo permanent mac addresses.
3655                  * If an active mac_id is present, return first active mac_id
3656                  * found.
3657                  */
3658                 for (i = 0; i < mac_count; i++) {
3659                         struct get_list_macaddr *mac_entry;
3660                         u16 mac_addr_size;
3661                         u32 mac_id;
3662
3663                         mac_entry = &resp->macaddr_list[i];
3664                         mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
3665                         /* mac_id is a 32 bit value and mac_addr size
3666                          * is 6 bytes
3667                          */
3668                         if (mac_addr_size == sizeof(u32)) {
3669                                 *pmac_id_valid = true;
3670                                 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
3671                                 *pmac_id = le32_to_cpu(mac_id);
3672                                 goto out;
3673                         }
3674                 }
3675                 /* If no active mac_id found, return first mac addr */
3676                 *pmac_id_valid = false;
3677                 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
3678                        ETH_ALEN);
3679         }
3680
3681 out:
3682         spin_unlock_bh(&adapter->mcc_lock);
3683         dma_free_coherent(&adapter->pdev->dev, get_mac_list_cmd.size,
3684                           get_mac_list_cmd.va, get_mac_list_cmd.dma);
3685         return status;
3686 }
3687
3688 int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id,
3689                           u8 *mac, u32 if_handle, bool active, u32 domain)
3690 {
3691         if (!active)
3692                 be_cmd_get_mac_from_list(adapter, mac, &active, &curr_pmac_id,
3693                                          if_handle, domain);
3694         if (BEx_chip(adapter))
3695                 return be_cmd_mac_addr_query(adapter, mac, false,
3696                                              if_handle, curr_pmac_id);
3697         else
3698                 /* Fetch the MAC address using pmac_id */
3699                 return be_cmd_get_mac_from_list(adapter, mac, &active,
3700                                                 &curr_pmac_id,
3701                                                 if_handle, domain);
3702 }
3703
3704 int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
3705 {
3706         int status;
3707         bool pmac_valid = false;
3708
3709         eth_zero_addr(mac);
3710
3711         if (BEx_chip(adapter)) {
3712                 if (be_physfn(adapter))
3713                         status = be_cmd_mac_addr_query(adapter, mac, true, 0,
3714                                                        0);
3715                 else
3716                         status = be_cmd_mac_addr_query(adapter, mac, false,
3717                                                        adapter->if_handle, 0);
3718         } else {
3719                 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
3720                                                   NULL, adapter->if_handle, 0);
3721         }
3722
3723         return status;
3724 }
3725
3726 /* Uses synchronous MCCQ */
3727 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
3728                         u8 mac_count, u32 domain)
3729 {
3730         struct be_mcc_wrb *wrb;
3731         struct be_cmd_req_set_mac_list *req;
3732         int status;
3733         struct be_dma_mem cmd;
3734
3735         memset(&cmd, 0, sizeof(struct be_dma_mem));
3736         cmd.size = sizeof(struct be_cmd_req_set_mac_list);
3737         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3738                                      GFP_KERNEL);
3739         if (!cmd.va)
3740                 return -ENOMEM;
3741
3742         spin_lock_bh(&adapter->mcc_lock);
3743
3744         wrb = wrb_from_mccq(adapter);
3745         if (!wrb) {
3746                 status = -EBUSY;
3747                 goto err;
3748         }
3749
3750         req = cmd.va;
3751         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3752                                OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
3753                                wrb, &cmd);
3754
3755         req->hdr.domain = domain;
3756         req->mac_count = mac_count;
3757         if (mac_count)
3758                 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
3759
3760         status = be_mcc_notify_wait(adapter);
3761
3762 err:
3763         dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
3764         spin_unlock_bh(&adapter->mcc_lock);
3765         return status;
3766 }
3767
3768 /* Wrapper to delete any active MACs and provision the new mac.
3769  * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
3770  * current list are active.
3771  */
3772 int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
3773 {
3774         bool active_mac = false;
3775         u8 old_mac[ETH_ALEN];
3776         u32 pmac_id;
3777         int status;
3778
3779         status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
3780                                           &pmac_id, if_id, dom);
3781
3782         if (!status && active_mac)
3783                 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
3784
3785         return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
3786 }
3787
3788 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
3789                           u32 domain, u16 intf_id, u16 hsw_mode, u8 spoofchk)
3790 {
3791         struct be_mcc_wrb *wrb;
3792         struct be_cmd_req_set_hsw_config *req;
3793         void *ctxt;
3794         int status;
3795
3796         spin_lock_bh(&adapter->mcc_lock);
3797
3798         wrb = wrb_from_mccq(adapter);
3799         if (!wrb) {
3800                 status = -EBUSY;
3801                 goto err;
3802         }
3803
3804         req = embedded_payload(wrb);
3805         ctxt = &req->context;
3806
3807         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3808                                OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb,
3809                                NULL);
3810
3811         req->hdr.domain = domain;
3812         AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
3813         if (pvid) {
3814                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
3815                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
3816         }
3817         if (!BEx_chip(adapter) && hsw_mode) {
3818                 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id,
3819                               ctxt, adapter->hba_port_num);
3820                 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1);
3821                 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type,
3822                               ctxt, hsw_mode);
3823         }
3824
3825         /* Enable/disable both mac and vlan spoof checking */
3826         if (!BEx_chip(adapter) && spoofchk) {
3827                 AMAP_SET_BITS(struct amap_set_hsw_context, mac_spoofchk,
3828                               ctxt, spoofchk);
3829                 AMAP_SET_BITS(struct amap_set_hsw_context, vlan_spoofchk,
3830                               ctxt, spoofchk);
3831         }
3832
3833         be_dws_cpu_to_le(req->context, sizeof(req->context));
3834         status = be_mcc_notify_wait(adapter);
3835
3836 err:
3837         spin_unlock_bh(&adapter->mcc_lock);
3838         return status;
3839 }
3840
3841 /* Get Hyper switch config */
3842 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
3843                           u32 domain, u16 intf_id, u8 *mode, bool *spoofchk)
3844 {
3845         struct be_mcc_wrb *wrb;
3846         struct be_cmd_req_get_hsw_config *req;
3847         void *ctxt;
3848         int status;
3849         u16 vid;
3850
3851         spin_lock_bh(&adapter->mcc_lock);
3852
3853         wrb = wrb_from_mccq(adapter);
3854         if (!wrb) {
3855                 status = -EBUSY;
3856                 goto err;
3857         }
3858
3859         req = embedded_payload(wrb);
3860         ctxt = &req->context;
3861
3862         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3863                                OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb,
3864                                NULL);
3865
3866         req->hdr.domain = domain;
3867         AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3868                       ctxt, intf_id);
3869         AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
3870
3871         if (!BEx_chip(adapter) && mode) {
3872                 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3873                               ctxt, adapter->hba_port_num);
3874                 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1);
3875         }
3876         be_dws_cpu_to_le(req->context, sizeof(req->context));
3877
3878         status = be_mcc_notify_wait(adapter);
3879         if (!status) {
3880                 struct be_cmd_resp_get_hsw_config *resp =
3881                                                 embedded_payload(wrb);
3882
3883                 be_dws_le_to_cpu(&resp->context, sizeof(resp->context));
3884                 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3885                                     pvid, &resp->context);
3886                 if (pvid)
3887                         *pvid = le16_to_cpu(vid);
3888                 if (mode)
3889                         *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3890                                               port_fwd_type, &resp->context);
3891                 if (spoofchk)
3892                         *spoofchk =
3893                                 AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3894                                               spoofchk, &resp->context);
3895         }
3896
3897 err:
3898         spin_unlock_bh(&adapter->mcc_lock);
3899         return status;
3900 }
3901
3902 static bool be_is_wol_excluded(struct be_adapter *adapter)
3903 {
3904         struct pci_dev *pdev = adapter->pdev;
3905
3906         if (be_virtfn(adapter))
3907                 return true;
3908
3909         switch (pdev->subsystem_device) {
3910         case OC_SUBSYS_DEVICE_ID1:
3911         case OC_SUBSYS_DEVICE_ID2:
3912         case OC_SUBSYS_DEVICE_ID3:
3913         case OC_SUBSYS_DEVICE_ID4:
3914                 return true;
3915         default:
3916                 return false;
3917         }
3918 }
3919
3920 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
3921 {
3922         struct be_mcc_wrb *wrb;
3923         struct be_cmd_req_acpi_wol_magic_config_v1 *req;
3924         int status = 0;
3925         struct be_dma_mem cmd;
3926
3927         if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3928                             CMD_SUBSYSTEM_ETH))
3929                 return -EPERM;
3930
3931         if (be_is_wol_excluded(adapter))
3932                 return status;
3933
3934         if (mutex_lock_interruptible(&adapter->mbox_lock))
3935                 return -1;
3936
3937         memset(&cmd, 0, sizeof(struct be_dma_mem));
3938         cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
3939         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3940                                      GFP_ATOMIC);
3941         if (!cmd.va) {
3942                 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
3943                 status = -ENOMEM;
3944                 goto err;
3945         }
3946
3947         wrb = wrb_from_mbox(adapter);
3948         if (!wrb) {
3949                 status = -EBUSY;
3950                 goto err;
3951         }
3952
3953         req = cmd.va;
3954
3955         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
3956                                OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3957                                sizeof(*req), wrb, &cmd);
3958
3959         req->hdr.version = 1;
3960         req->query_options = BE_GET_WOL_CAP;
3961
3962         status = be_mbox_notify_wait(adapter);
3963         if (!status) {
3964                 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
3965
3966                 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *)cmd.va;
3967
3968                 adapter->wol_cap = resp->wol_settings;
3969                 if (adapter->wol_cap & BE_WOL_CAP)
3970                         adapter->wol_en = true;
3971         }
3972 err:
3973         mutex_unlock(&adapter->mbox_lock);
3974         if (cmd.va)
3975                 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
3976                                   cmd.dma);
3977         return status;
3978
3979 }
3980
3981 int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level)
3982 {
3983         struct be_dma_mem extfat_cmd;
3984         struct be_fat_conf_params *cfgs;
3985         int status;
3986         int i, j;
3987
3988         memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
3989         extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
3990         extfat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3991                                             extfat_cmd.size, &extfat_cmd.dma,
3992                                             GFP_ATOMIC);
3993         if (!extfat_cmd.va)
3994                 return -ENOMEM;
3995
3996         status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
3997         if (status)
3998                 goto err;
3999
4000         cfgs = (struct be_fat_conf_params *)
4001                         (extfat_cmd.va + sizeof(struct be_cmd_resp_hdr));
4002         for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) {
4003                 u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes);
4004
4005                 for (j = 0; j < num_modes; j++) {
4006                         if (cfgs->module[i].trace_lvl[j].mode == MODE_UART)
4007                                 cfgs->module[i].trace_lvl[j].dbg_lvl =
4008                                                         cpu_to_le32(level);
4009                 }
4010         }
4011
4012         status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd, cfgs);
4013 err:
4014         dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
4015                           extfat_cmd.dma);
4016         return status;
4017 }
4018
4019 int be_cmd_get_fw_log_level(struct be_adapter *adapter)
4020 {
4021         struct be_dma_mem extfat_cmd;
4022         struct be_fat_conf_params *cfgs;
4023         int status, j;
4024         int level = 0;
4025
4026         memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
4027         extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
4028         extfat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
4029                                             extfat_cmd.size, &extfat_cmd.dma,
4030                                             GFP_ATOMIC);
4031
4032         if (!extfat_cmd.va) {
4033                 dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
4034                         __func__);
4035                 goto err;
4036         }
4037
4038         status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
4039         if (!status) {
4040                 cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
4041                                                 sizeof(struct be_cmd_resp_hdr));
4042
4043                 for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) {
4044                         if (cfgs->module[0].trace_lvl[j].mode == MODE_UART)
4045                                 level = cfgs->module[0].trace_lvl[j].dbg_lvl;
4046                 }
4047         }
4048         dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
4049                           extfat_cmd.dma);
4050 err:
4051         return level;
4052 }
4053
4054 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
4055                                    struct be_dma_mem *cmd)
4056 {
4057         struct be_mcc_wrb *wrb;
4058         struct be_cmd_req_get_ext_fat_caps *req;
4059         int status;
4060
4061         if (mutex_lock_interruptible(&adapter->mbox_lock))
4062                 return -1;
4063
4064         wrb = wrb_from_mbox(adapter);
4065         if (!wrb) {
4066                 status = -EBUSY;
4067                 goto err;
4068         }
4069
4070         req = cmd->va;
4071         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4072                                OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
4073                                cmd->size, wrb, cmd);
4074         req->parameter_type = cpu_to_le32(1);
4075
4076         status = be_mbox_notify_wait(adapter);
4077 err:
4078         mutex_unlock(&adapter->mbox_lock);
4079         return status;
4080 }
4081
4082 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
4083                                    struct be_dma_mem *cmd,
4084                                    struct be_fat_conf_params *configs)
4085 {
4086         struct be_mcc_wrb *wrb;
4087         struct be_cmd_req_set_ext_fat_caps *req;
4088         int status;
4089
4090         spin_lock_bh(&adapter->mcc_lock);
4091
4092         wrb = wrb_from_mccq(adapter);
4093         if (!wrb) {
4094                 status = -EBUSY;
4095                 goto err;
4096         }
4097
4098         req = cmd->va;
4099         memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
4100         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4101                                OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
4102                                cmd->size, wrb, cmd);
4103
4104         status = be_mcc_notify_wait(adapter);
4105 err:
4106         spin_unlock_bh(&adapter->mcc_lock);
4107         return status;
4108 }
4109
4110 int be_cmd_query_port_name(struct be_adapter *adapter)
4111 {
4112         struct be_cmd_req_get_port_name *req;
4113         struct be_mcc_wrb *wrb;
4114         int status;
4115
4116         if (mutex_lock_interruptible(&adapter->mbox_lock))
4117                 return -1;
4118
4119         wrb = wrb_from_mbox(adapter);
4120         req = embedded_payload(wrb);
4121
4122         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4123                                OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
4124                                NULL);
4125         if (!BEx_chip(adapter))
4126                 req->hdr.version = 1;
4127
4128         status = be_mbox_notify_wait(adapter);
4129         if (!status) {
4130                 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
4131
4132                 adapter->port_name = resp->port_name[adapter->hba_port_num];
4133         } else {
4134                 adapter->port_name = adapter->hba_port_num + '0';
4135         }
4136
4137         mutex_unlock(&adapter->mbox_lock);
4138         return status;
4139 }
4140
4141 /* Descriptor type */
4142 enum {
4143         FUNC_DESC = 1,
4144         VFT_DESC = 2
4145 };
4146
4147 static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
4148                                                int desc_type)
4149 {
4150         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4151         struct be_nic_res_desc *nic;
4152         int i;
4153
4154         for (i = 0; i < desc_count; i++) {
4155                 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
4156                     hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1) {
4157                         nic = (struct be_nic_res_desc *)hdr;
4158                         if (desc_type == FUNC_DESC ||
4159                             (desc_type == VFT_DESC &&
4160                              nic->flags & (1 << VFT_SHIFT)))
4161                                 return nic;
4162                 }
4163
4164                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4165                 hdr = (void *)hdr + hdr->desc_len;
4166         }
4167         return NULL;
4168 }
4169
4170 static struct be_nic_res_desc *be_get_vft_desc(u8 *buf, u32 desc_count)
4171 {
4172         return be_get_nic_desc(buf, desc_count, VFT_DESC);
4173 }
4174
4175 static struct be_nic_res_desc *be_get_func_nic_desc(u8 *buf, u32 desc_count)
4176 {
4177         return be_get_nic_desc(buf, desc_count, FUNC_DESC);
4178 }
4179
4180 static struct be_pcie_res_desc *be_get_pcie_desc(u8 devfn, u8 *buf,
4181                                                  u32 desc_count)
4182 {
4183         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4184         struct be_pcie_res_desc *pcie;
4185         int i;
4186
4187         for (i = 0; i < desc_count; i++) {
4188                 if ((hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
4189                      hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1)) {
4190                         pcie = (struct be_pcie_res_desc *)hdr;
4191                         if (pcie->pf_num == devfn)
4192                                 return pcie;
4193                 }
4194
4195                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4196                 hdr = (void *)hdr + hdr->desc_len;
4197         }
4198         return NULL;
4199 }
4200
4201 static struct be_port_res_desc *be_get_port_desc(u8 *buf, u32 desc_count)
4202 {
4203         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4204         int i;
4205
4206         for (i = 0; i < desc_count; i++) {
4207                 if (hdr->desc_type == PORT_RESOURCE_DESC_TYPE_V1)
4208                         return (struct be_port_res_desc *)hdr;
4209
4210                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4211                 hdr = (void *)hdr + hdr->desc_len;
4212         }
4213         return NULL;
4214 }
4215
4216 static void be_copy_nic_desc(struct be_resources *res,
4217                              struct be_nic_res_desc *desc)
4218 {
4219         res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count);
4220         res->max_vlans = le16_to_cpu(desc->vlan_count);
4221         res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
4222         res->max_tx_qs = le16_to_cpu(desc->txq_count);
4223         res->max_rss_qs = le16_to_cpu(desc->rssq_count);
4224         res->max_rx_qs = le16_to_cpu(desc->rq_count);
4225         res->max_evt_qs = le16_to_cpu(desc->eq_count);
4226         res->max_cq_count = le16_to_cpu(desc->cq_count);
4227         res->max_iface_count = le16_to_cpu(desc->iface_count);
4228         res->max_mcc_count = le16_to_cpu(desc->mcc_count);
4229         /* Clear flags that driver is not interested in */
4230         res->if_cap_flags = le32_to_cpu(desc->cap_flags) &
4231                                 BE_IF_CAP_FLAGS_WANT;
4232 }
4233
4234 /* Uses Mbox */
4235 int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res)
4236 {
4237         struct be_mcc_wrb *wrb;
4238         struct be_cmd_req_get_func_config *req;
4239         int status;
4240         struct be_dma_mem cmd;
4241
4242         if (mutex_lock_interruptible(&adapter->mbox_lock))
4243                 return -1;
4244
4245         memset(&cmd, 0, sizeof(struct be_dma_mem));
4246         cmd.size = sizeof(struct be_cmd_resp_get_func_config);
4247         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4248                                      GFP_ATOMIC);
4249         if (!cmd.va) {
4250                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
4251                 status = -ENOMEM;
4252                 goto err;
4253         }
4254
4255         wrb = wrb_from_mbox(adapter);
4256         if (!wrb) {
4257                 status = -EBUSY;
4258                 goto err;
4259         }
4260
4261         req = cmd.va;
4262
4263         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4264                                OPCODE_COMMON_GET_FUNC_CONFIG,
4265                                cmd.size, wrb, &cmd);
4266
4267         if (skyhawk_chip(adapter))
4268                 req->hdr.version = 1;
4269
4270         status = be_mbox_notify_wait(adapter);
4271         if (!status) {
4272                 struct be_cmd_resp_get_func_config *resp = cmd.va;
4273                 u32 desc_count = le32_to_cpu(resp->desc_count);
4274                 struct be_nic_res_desc *desc;
4275
4276                 desc = be_get_func_nic_desc(resp->func_param, desc_count);
4277                 if (!desc) {
4278                         status = -EINVAL;
4279                         goto err;
4280                 }
4281                 adapter->pf_number = desc->pf_num;
4282                 be_copy_nic_desc(res, desc);
4283         }
4284 err:
4285         mutex_unlock(&adapter->mbox_lock);
4286         if (cmd.va)
4287                 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4288                                   cmd.dma);
4289         return status;
4290 }
4291
4292 /* Will use MBOX only if MCCQ has not been created
4293  * non-zero domain => a PF is querying this on behalf of a VF
4294  * zero domain => a PF or a VF is querying this for itself
4295  */
4296 int be_cmd_get_profile_config(struct be_adapter *adapter,
4297                               struct be_resources *res, u8 query, u8 domain)
4298 {
4299         struct be_cmd_resp_get_profile_config *resp;
4300         struct be_cmd_req_get_profile_config *req;
4301         struct be_nic_res_desc *vf_res;
4302         struct be_pcie_res_desc *pcie;
4303         struct be_port_res_desc *port;
4304         struct be_nic_res_desc *nic;
4305         struct be_mcc_wrb wrb = {0};
4306         struct be_dma_mem cmd;
4307         u16 desc_count;
4308         int status;
4309
4310         memset(&cmd, 0, sizeof(struct be_dma_mem));
4311         cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
4312         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4313                                      GFP_ATOMIC);
4314         if (!cmd.va)
4315                 return -ENOMEM;
4316
4317         req = cmd.va;
4318         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4319                                OPCODE_COMMON_GET_PROFILE_CONFIG,
4320                                cmd.size, &wrb, &cmd);
4321
4322         if (!lancer_chip(adapter))
4323                 req->hdr.version = 1;
4324         req->type = ACTIVE_PROFILE_TYPE;
4325         /* When a function is querying profile information relating to
4326          * itself hdr.pf_number must be set to it's pci_func_num + 1
4327          */
4328         req->hdr.domain = domain;
4329         if (domain == 0)
4330                 req->hdr.pf_num = adapter->pci_func_num + 1;
4331
4332         /* When QUERY_MODIFIABLE_FIELDS_TYPE bit is set, cmd returns the
4333          * descriptors with all bits set to "1" for the fields which can be
4334          * modified using SET_PROFILE_CONFIG cmd.
4335          */
4336         if (query == RESOURCE_MODIFIABLE)
4337                 req->type |= QUERY_MODIFIABLE_FIELDS_TYPE;
4338
4339         status = be_cmd_notify_wait(adapter, &wrb);
4340         if (status)
4341                 goto err;
4342
4343         resp = cmd.va;
4344         desc_count = le16_to_cpu(resp->desc_count);
4345
4346         pcie = be_get_pcie_desc(adapter->pdev->devfn, resp->func_param,
4347                                 desc_count);
4348         if (pcie)
4349                 res->max_vfs = le16_to_cpu(pcie->num_vfs);
4350
4351         port = be_get_port_desc(resp->func_param, desc_count);
4352         if (port)
4353                 adapter->mc_type = port->mc_type;
4354
4355         nic = be_get_func_nic_desc(resp->func_param, desc_count);
4356         if (nic)
4357                 be_copy_nic_desc(res, nic);
4358
4359         vf_res = be_get_vft_desc(resp->func_param, desc_count);
4360         if (vf_res)
4361                 res->vf_if_cap_flags = vf_res->cap_flags;
4362 err:
4363         if (cmd.va)
4364                 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4365                                   cmd.dma);
4366         return status;
4367 }
4368
4369 /* Will use MBOX only if MCCQ has not been created */
4370 static int be_cmd_set_profile_config(struct be_adapter *adapter, void *desc,
4371                                      int size, int count, u8 version, u8 domain)
4372 {
4373         struct be_cmd_req_set_profile_config *req;
4374         struct be_mcc_wrb wrb = {0};
4375         struct be_dma_mem cmd;
4376         int status;
4377
4378         memset(&cmd, 0, sizeof(struct be_dma_mem));
4379         cmd.size = sizeof(struct be_cmd_req_set_profile_config);
4380         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4381                                      GFP_ATOMIC);
4382         if (!cmd.va)
4383                 return -ENOMEM;
4384
4385         req = cmd.va;
4386         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4387                                OPCODE_COMMON_SET_PROFILE_CONFIG, cmd.size,
4388                                &wrb, &cmd);
4389         req->hdr.version = version;
4390         req->hdr.domain = domain;
4391         req->desc_count = cpu_to_le32(count);
4392         memcpy(req->desc, desc, size);
4393
4394         status = be_cmd_notify_wait(adapter, &wrb);
4395
4396         if (cmd.va)
4397                 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4398                                   cmd.dma);
4399         return status;
4400 }
4401
4402 /* Mark all fields invalid */
4403 static void be_reset_nic_desc(struct be_nic_res_desc *nic)
4404 {
4405         memset(nic, 0, sizeof(*nic));
4406         nic->unicast_mac_count = 0xFFFF;
4407         nic->mcc_count = 0xFFFF;
4408         nic->vlan_count = 0xFFFF;
4409         nic->mcast_mac_count = 0xFFFF;
4410         nic->txq_count = 0xFFFF;
4411         nic->rq_count = 0xFFFF;
4412         nic->rssq_count = 0xFFFF;
4413         nic->lro_count = 0xFFFF;
4414         nic->cq_count = 0xFFFF;
4415         nic->toe_conn_count = 0xFFFF;
4416         nic->eq_count = 0xFFFF;
4417         nic->iface_count = 0xFFFF;
4418         nic->link_param = 0xFF;
4419         nic->channel_id_param = cpu_to_le16(0xF000);
4420         nic->acpi_params = 0xFF;
4421         nic->wol_param = 0x0F;
4422         nic->tunnel_iface_count = 0xFFFF;
4423         nic->direct_tenant_iface_count = 0xFFFF;
4424         nic->bw_min = 0xFFFFFFFF;
4425         nic->bw_max = 0xFFFFFFFF;
4426 }
4427
4428 /* Mark all fields invalid */
4429 static void be_reset_pcie_desc(struct be_pcie_res_desc *pcie)
4430 {
4431         memset(pcie, 0, sizeof(*pcie));
4432         pcie->sriov_state = 0xFF;
4433         pcie->pf_state = 0xFF;
4434         pcie->pf_type = 0xFF;
4435         pcie->num_vfs = 0xFFFF;
4436 }
4437
4438 int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, u16 link_speed,
4439                       u8 domain)
4440 {
4441         struct be_nic_res_desc nic_desc;
4442         u32 bw_percent;
4443         u16 version = 0;
4444
4445         if (BE3_chip(adapter))
4446                 return be_cmd_set_qos(adapter, max_rate / 10, domain);
4447
4448         be_reset_nic_desc(&nic_desc);
4449         nic_desc.pf_num = adapter->pf_number;
4450         nic_desc.vf_num = domain;
4451         nic_desc.bw_min = 0;
4452         if (lancer_chip(adapter)) {
4453                 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
4454                 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
4455                 nic_desc.flags = (1 << QUN_SHIFT) | (1 << IMM_SHIFT) |
4456                                         (1 << NOSV_SHIFT);
4457                 nic_desc.bw_max = cpu_to_le32(max_rate / 10);
4458         } else {
4459                 version = 1;
4460                 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
4461                 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4462                 nic_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
4463                 bw_percent = max_rate ? (max_rate * 100) / link_speed : 100;
4464                 nic_desc.bw_max = cpu_to_le32(bw_percent);
4465         }
4466
4467         return be_cmd_set_profile_config(adapter, &nic_desc,
4468                                          nic_desc.hdr.desc_len,
4469                                          1, version, domain);
4470 }
4471
4472 static void be_fill_vf_res_template(struct be_adapter *adapter,
4473                                     struct be_resources pool_res,
4474                                     u16 num_vfs, u16 num_vf_qs,
4475                                     struct be_nic_res_desc *nic_vft)
4476 {
4477         u32 vf_if_cap_flags = pool_res.vf_if_cap_flags;
4478         struct be_resources res_mod = {0};
4479
4480         /* Resource with fields set to all '1's by GET_PROFILE_CONFIG cmd,
4481          * which are modifiable using SET_PROFILE_CONFIG cmd.
4482          */
4483         be_cmd_get_profile_config(adapter, &res_mod, RESOURCE_MODIFIABLE, 0);
4484
4485         /* If RSS IFACE capability flags are modifiable for a VF, set the
4486          * capability flag as valid and set RSS and DEFQ_RSS IFACE flags if
4487          * more than 1 RSSQ is available for a VF.
4488          * Otherwise, provision only 1 queue pair for VF.
4489          */
4490         if (res_mod.vf_if_cap_flags & BE_IF_FLAGS_RSS) {
4491                 nic_vft->flags |= BIT(IF_CAPS_FLAGS_VALID_SHIFT);
4492                 if (num_vf_qs > 1) {
4493                         vf_if_cap_flags |= BE_IF_FLAGS_RSS;
4494                         if (pool_res.if_cap_flags & BE_IF_FLAGS_DEFQ_RSS)
4495                                 vf_if_cap_flags |= BE_IF_FLAGS_DEFQ_RSS;
4496                 } else {
4497                         vf_if_cap_flags &= ~(BE_IF_FLAGS_RSS |
4498                                              BE_IF_FLAGS_DEFQ_RSS);
4499                 }
4500         } else {
4501                 num_vf_qs = 1;
4502         }
4503
4504         if (res_mod.vf_if_cap_flags & BE_IF_FLAGS_VLAN_PROMISCUOUS) {
4505                 nic_vft->flags |= BIT(IF_CAPS_FLAGS_VALID_SHIFT);
4506                 vf_if_cap_flags &= ~BE_IF_FLAGS_VLAN_PROMISCUOUS;
4507         }
4508
4509         nic_vft->cap_flags = cpu_to_le32(vf_if_cap_flags);
4510         nic_vft->rq_count = cpu_to_le16(num_vf_qs);
4511         nic_vft->txq_count = cpu_to_le16(num_vf_qs);
4512         nic_vft->rssq_count = cpu_to_le16(num_vf_qs);
4513         nic_vft->cq_count = cpu_to_le16(pool_res.max_cq_count /
4514                                         (num_vfs + 1));
4515
4516         /* Distribute unicast MACs, VLANs, IFACE count and MCCQ count equally
4517          * among the PF and it's VFs, if the fields are changeable
4518          */
4519         if (res_mod.max_uc_mac == FIELD_MODIFIABLE)
4520                 nic_vft->unicast_mac_count = cpu_to_le16(pool_res.max_uc_mac /
4521                                                          (num_vfs + 1));
4522
4523         if (res_mod.max_vlans == FIELD_MODIFIABLE)
4524                 nic_vft->vlan_count = cpu_to_le16(pool_res.max_vlans /
4525                                                   (num_vfs + 1));
4526
4527         if (res_mod.max_iface_count == FIELD_MODIFIABLE)
4528                 nic_vft->iface_count = cpu_to_le16(pool_res.max_iface_count /
4529                                                    (num_vfs + 1));
4530
4531         if (res_mod.max_mcc_count == FIELD_MODIFIABLE)
4532                 nic_vft->mcc_count = cpu_to_le16(pool_res.max_mcc_count /
4533                                                  (num_vfs + 1));
4534 }
4535
4536 int be_cmd_set_sriov_config(struct be_adapter *adapter,
4537                             struct be_resources pool_res, u16 num_vfs,
4538                             u16 num_vf_qs)
4539 {
4540         struct {
4541                 struct be_pcie_res_desc pcie;
4542                 struct be_nic_res_desc nic_vft;
4543         } __packed desc;
4544
4545         /* PF PCIE descriptor */
4546         be_reset_pcie_desc(&desc.pcie);
4547         desc.pcie.hdr.desc_type = PCIE_RESOURCE_DESC_TYPE_V1;
4548         desc.pcie.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4549         desc.pcie.flags = BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
4550         desc.pcie.pf_num = adapter->pdev->devfn;
4551         desc.pcie.sriov_state = num_vfs ? 1 : 0;
4552         desc.pcie.num_vfs = cpu_to_le16(num_vfs);
4553
4554         /* VF NIC Template descriptor */
4555         be_reset_nic_desc(&desc.nic_vft);
4556         desc.nic_vft.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
4557         desc.nic_vft.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4558         desc.nic_vft.flags = BIT(VFT_SHIFT) | BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
4559         desc.nic_vft.pf_num = adapter->pdev->devfn;
4560         desc.nic_vft.vf_num = 0;
4561
4562         be_fill_vf_res_template(adapter, pool_res, num_vfs, num_vf_qs,
4563                                 &desc.nic_vft);
4564
4565         return be_cmd_set_profile_config(adapter, &desc,
4566                                          2 * RESOURCE_DESC_SIZE_V1, 2, 1, 0);
4567 }
4568
4569 int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op)
4570 {
4571         struct be_mcc_wrb *wrb;
4572         struct be_cmd_req_manage_iface_filters *req;
4573         int status;
4574
4575         if (iface == 0xFFFFFFFF)
4576                 return -1;
4577
4578         spin_lock_bh(&adapter->mcc_lock);
4579
4580         wrb = wrb_from_mccq(adapter);
4581         if (!wrb) {
4582                 status = -EBUSY;
4583                 goto err;
4584         }
4585         req = embedded_payload(wrb);
4586
4587         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4588                                OPCODE_COMMON_MANAGE_IFACE_FILTERS, sizeof(*req),
4589                                wrb, NULL);
4590         req->op = op;
4591         req->target_iface_id = cpu_to_le32(iface);
4592
4593         status = be_mcc_notify_wait(adapter);
4594 err:
4595         spin_unlock_bh(&adapter->mcc_lock);
4596         return status;
4597 }
4598
4599 int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port)
4600 {
4601         struct be_port_res_desc port_desc;
4602
4603         memset(&port_desc, 0, sizeof(port_desc));
4604         port_desc.hdr.desc_type = PORT_RESOURCE_DESC_TYPE_V1;
4605         port_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4606         port_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
4607         port_desc.link_num = adapter->hba_port_num;
4608         if (port) {
4609                 port_desc.nv_flags = NV_TYPE_VXLAN | (1 << SOCVID_SHIFT) |
4610                                         (1 << RCVID_SHIFT);
4611                 port_desc.nv_port = swab16(port);
4612         } else {
4613                 port_desc.nv_flags = NV_TYPE_DISABLED;
4614                 port_desc.nv_port = 0;
4615         }
4616
4617         return be_cmd_set_profile_config(adapter, &port_desc,
4618                                          RESOURCE_DESC_SIZE_V1, 1, 1, 0);
4619 }
4620
4621 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
4622                      int vf_num)
4623 {
4624         struct be_mcc_wrb *wrb;
4625         struct be_cmd_req_get_iface_list *req;
4626         struct be_cmd_resp_get_iface_list *resp;
4627         int status;
4628
4629         spin_lock_bh(&adapter->mcc_lock);
4630
4631         wrb = wrb_from_mccq(adapter);
4632         if (!wrb) {
4633                 status = -EBUSY;
4634                 goto err;
4635         }
4636         req = embedded_payload(wrb);
4637
4638         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4639                                OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
4640                                wrb, NULL);
4641         req->hdr.domain = vf_num + 1;
4642
4643         status = be_mcc_notify_wait(adapter);
4644         if (!status) {
4645                 resp = (struct be_cmd_resp_get_iface_list *)req;
4646                 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
4647         }
4648
4649 err:
4650         spin_unlock_bh(&adapter->mcc_lock);
4651         return status;
4652 }
4653
4654 static int lancer_wait_idle(struct be_adapter *adapter)
4655 {
4656 #define SLIPORT_IDLE_TIMEOUT 30
4657         u32 reg_val;
4658         int status = 0, i;
4659
4660         for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
4661                 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
4662                 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
4663                         break;
4664
4665                 ssleep(1);
4666         }
4667
4668         if (i == SLIPORT_IDLE_TIMEOUT)
4669                 status = -1;
4670
4671         return status;
4672 }
4673
4674 int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
4675 {
4676         int status = 0;
4677
4678         status = lancer_wait_idle(adapter);
4679         if (status)
4680                 return status;
4681
4682         iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
4683
4684         return status;
4685 }
4686
4687 /* Routine to check whether dump image is present or not */
4688 bool dump_present(struct be_adapter *adapter)
4689 {
4690         u32 sliport_status = 0;
4691
4692         sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
4693         return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
4694 }
4695
4696 int lancer_initiate_dump(struct be_adapter *adapter)
4697 {
4698         struct device *dev = &adapter->pdev->dev;
4699         int status;
4700
4701         if (dump_present(adapter)) {
4702                 dev_info(dev, "Previous dump not cleared, not forcing dump\n");
4703                 return -EEXIST;
4704         }
4705
4706         /* give firmware reset and diagnostic dump */
4707         status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
4708                                      PHYSDEV_CONTROL_DD_MASK);
4709         if (status < 0) {
4710                 dev_err(dev, "FW reset failed\n");
4711                 return status;
4712         }
4713
4714         status = lancer_wait_idle(adapter);
4715         if (status)
4716                 return status;
4717
4718         if (!dump_present(adapter)) {
4719                 dev_err(dev, "FW dump not generated\n");
4720                 return -EIO;
4721         }
4722
4723         return 0;
4724 }
4725
4726 int lancer_delete_dump(struct be_adapter *adapter)
4727 {
4728         int status;
4729
4730         status = lancer_cmd_delete_object(adapter, LANCER_FW_DUMP_FILE);
4731         return be_cmd_status(status);
4732 }
4733
4734 /* Uses sync mcc */
4735 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
4736 {
4737         struct be_mcc_wrb *wrb;
4738         struct be_cmd_enable_disable_vf *req;
4739         int status;
4740
4741         if (BEx_chip(adapter))
4742                 return 0;
4743
4744         spin_lock_bh(&adapter->mcc_lock);
4745
4746         wrb = wrb_from_mccq(adapter);
4747         if (!wrb) {
4748                 status = -EBUSY;
4749                 goto err;
4750         }
4751
4752         req = embedded_payload(wrb);
4753
4754         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4755                                OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
4756                                wrb, NULL);
4757
4758         req->hdr.domain = domain;
4759         req->enable = 1;
4760         status = be_mcc_notify_wait(adapter);
4761 err:
4762         spin_unlock_bh(&adapter->mcc_lock);
4763         return status;
4764 }
4765
4766 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
4767 {
4768         struct be_mcc_wrb *wrb;
4769         struct be_cmd_req_intr_set *req;
4770         int status;
4771
4772         if (mutex_lock_interruptible(&adapter->mbox_lock))
4773                 return -1;
4774
4775         wrb = wrb_from_mbox(adapter);
4776
4777         req = embedded_payload(wrb);
4778
4779         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4780                                OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
4781                                wrb, NULL);
4782
4783         req->intr_enabled = intr_enable;
4784
4785         status = be_mbox_notify_wait(adapter);
4786
4787         mutex_unlock(&adapter->mbox_lock);
4788         return status;
4789 }
4790
4791 /* Uses MBOX */
4792 int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile_id)
4793 {
4794         struct be_cmd_req_get_active_profile *req;
4795         struct be_mcc_wrb *wrb;
4796         int status;
4797
4798         if (mutex_lock_interruptible(&adapter->mbox_lock))
4799                 return -1;
4800
4801         wrb = wrb_from_mbox(adapter);
4802         if (!wrb) {
4803                 status = -EBUSY;
4804                 goto err;
4805         }
4806
4807         req = embedded_payload(wrb);
4808
4809         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4810                                OPCODE_COMMON_GET_ACTIVE_PROFILE, sizeof(*req),
4811                                wrb, NULL);
4812
4813         status = be_mbox_notify_wait(adapter);
4814         if (!status) {
4815                 struct be_cmd_resp_get_active_profile *resp =
4816                                                         embedded_payload(wrb);
4817
4818                 *profile_id = le16_to_cpu(resp->active_profile_id);
4819         }
4820
4821 err:
4822         mutex_unlock(&adapter->mbox_lock);
4823         return status;
4824 }
4825
4826 int __be_cmd_set_logical_link_config(struct be_adapter *adapter,
4827                                      int link_state, int version, u8 domain)
4828 {
4829         struct be_mcc_wrb *wrb;
4830         struct be_cmd_req_set_ll_link *req;
4831         int status;
4832
4833         spin_lock_bh(&adapter->mcc_lock);
4834
4835         wrb = wrb_from_mccq(adapter);
4836         if (!wrb) {
4837                 status = -EBUSY;
4838                 goto err;
4839         }
4840
4841         req = embedded_payload(wrb);
4842
4843         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4844                                OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG,
4845                                sizeof(*req), wrb, NULL);
4846
4847         req->hdr.version = version;
4848         req->hdr.domain = domain;
4849
4850         if (link_state == IFLA_VF_LINK_STATE_ENABLE ||
4851             link_state == IFLA_VF_LINK_STATE_AUTO)
4852                 req->link_config |= PLINK_ENABLE;
4853
4854         if (link_state == IFLA_VF_LINK_STATE_AUTO)
4855                 req->link_config |= PLINK_TRACK;
4856
4857         status = be_mcc_notify_wait(adapter);
4858 err:
4859         spin_unlock_bh(&adapter->mcc_lock);
4860         return status;
4861 }
4862
4863 int be_cmd_set_logical_link_config(struct be_adapter *adapter,
4864                                    int link_state, u8 domain)
4865 {
4866         int status;
4867
4868         if (BEx_chip(adapter))
4869                 return -EOPNOTSUPP;
4870
4871         status = __be_cmd_set_logical_link_config(adapter, link_state,
4872                                                   2, domain);
4873
4874         /* Version 2 of the command will not be recognized by older FW.
4875          * On such a failure issue version 1 of the command.
4876          */
4877         if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST)
4878                 status = __be_cmd_set_logical_link_config(adapter, link_state,
4879                                                           1, domain);
4880         return status;
4881 }
4882 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
4883                     int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
4884 {
4885         struct be_adapter *adapter = netdev_priv(netdev_handle);
4886         struct be_mcc_wrb *wrb;
4887         struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *)wrb_payload;
4888         struct be_cmd_req_hdr *req;
4889         struct be_cmd_resp_hdr *resp;
4890         int status;
4891
4892         spin_lock_bh(&adapter->mcc_lock);
4893
4894         wrb = wrb_from_mccq(adapter);
4895         if (!wrb) {
4896                 status = -EBUSY;
4897                 goto err;
4898         }
4899         req = embedded_payload(wrb);
4900         resp = embedded_payload(wrb);
4901
4902         be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
4903                                hdr->opcode, wrb_payload_size, wrb, NULL);
4904         memcpy(req, wrb_payload, wrb_payload_size);
4905         be_dws_cpu_to_le(req, wrb_payload_size);
4906
4907         status = be_mcc_notify_wait(adapter);
4908         if (cmd_status)
4909                 *cmd_status = (status & 0xffff);
4910         if (ext_status)
4911                 *ext_status = 0;
4912         memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
4913         be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
4914 err:
4915         spin_unlock_bh(&adapter->mcc_lock);
4916         return status;
4917 }
4918 EXPORT_SYMBOL(be_roce_mcc_cmd);