drivers/net/ethernet/emulex/benet/be_cmds.c

   1 /*
   2  * Copyright (C) 2005 - 2016 Broadcom
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 #include <linux/module.h>
  19 #include "be.h"
  20 #include "be_cmds.h"
  21
  22 char *be_misconfig_evt_port_state[] = {
  23         "Physical Link is functional",
  24         "Optics faulted/incorrectly installed/not installed - Reseat optics. If issue not resolved, replace.",
  25         "Optics of two types installed – Remove one optic or install matching pair of optics.",
  26         "Incompatible optics – Replace with compatible optics for card to function.",
  27         "Unqualified optics – Replace with Avago optics for Warranty and Technical Support.",
  28         "Uncertified optics – Replace with Avago-certified optics to enable link operation."
  29 };
  30
  31 static char *be_port_misconfig_evt_severity[] = {
  32         "KERN_WARN",
  33         "KERN_INFO",
  34         "KERN_ERR",
  35         "KERN_WARN"
  36 };
  37
  38 static char *phy_state_oper_desc[] = {
  39         "Link is non-operational",
  40         "Link is operational",
  41         ""
  42 };
  43
  44 static struct be_cmd_priv_map cmd_priv_map[] = {
  45         {
  46                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
  47                 CMD_SUBSYSTEM_ETH,
  48                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  49                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  50         },
  51         {
  52                 OPCODE_COMMON_GET_FLOW_CONTROL,
  53                 CMD_SUBSYSTEM_COMMON,
  54                 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
  55                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  56         },
  57         {
  58                 OPCODE_COMMON_SET_FLOW_CONTROL,
  59                 CMD_SUBSYSTEM_COMMON,
  60                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  61                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  62         },
  63         {
  64                 OPCODE_ETH_GET_PPORT_STATS,
  65                 CMD_SUBSYSTEM_ETH,
  66                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  67                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  68         },
  69         {
  70                 OPCODE_COMMON_GET_PHY_DETAILS,
  71                 CMD_SUBSYSTEM_COMMON,
  72                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  73                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  74         },
  75         {
  76                 OPCODE_LOWLEVEL_HOST_DDR_DMA,
  77                 CMD_SUBSYSTEM_LOWLEVEL,
  78                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  79         },
  80         {
  81                 OPCODE_LOWLEVEL_LOOPBACK_TEST,
  82                 CMD_SUBSYSTEM_LOWLEVEL,
  83                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  84         },
  85         {
  86                 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
  87                 CMD_SUBSYSTEM_LOWLEVEL,
  88                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  89         },
  90         {
  91                 OPCODE_COMMON_SET_HSW_CONFIG,
  92                 CMD_SUBSYSTEM_COMMON,
  93                 BE_PRIV_DEVCFG | BE_PRIV_VHADM
  94         },
  95 };
  96
  97 static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, u8 subsystem)
  98 {
  99         int i;
 100         int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
 101         u32 cmd_privileges = adapter->cmd_privileges;
 102
 103         for (i = 0; i < num_entries; i++)
 104                 if (opcode == cmd_priv_map[i].opcode &&
 105                     subsystem == cmd_priv_map[i].subsystem)
 106                         if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
 107                                 return false;
 108
 109         return true;
 110 }
 111
 112 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
 113 {
 114         return wrb->payload.embedded_payload;
 115 }
 116
 117 static int be_mcc_notify(struct be_adapter *adapter)
 118 {
 119         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 120         u32 val = 0;
 121
 122         if (be_check_error(adapter, BE_ERROR_ANY))
 123                 return -EIO;
 124
 125         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
 126         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
 127
 128         wmb();
 129         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
 130
 131         return 0;
 132 }
 133
 134 /* To check if valid bit is set, check the entire word as we don't know
 135  * the endianness of the data (old entry is host endian while a new entry is
 136  * little endian) */
 137 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
 138 {
 139         u32 flags;
 140
 141         if (compl->flags != 0) {
 142                 flags = le32_to_cpu(compl->flags);
 143                 if (flags & CQE_FLAGS_VALID_MASK) {
 144                         compl->flags = flags;
 145                         return true;
 146                 }
 147         }
 148         return false;
 149 }
 150
 151 /* Need to reset the entire word that houses the valid bit */
 152 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
 153 {
 154         compl->flags = 0;
 155 }
 156
 157 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
 158 {
 159         unsigned long addr;
 160
 161         addr = tag1;
 162         addr = ((addr << 16) << 16) | tag0;
 163         return (void *)addr;
 164 }
 165
 166 static bool be_skip_err_log(u8 opcode, u16 base_status, u16 addl_status)
 167 {
 168         if (base_status == MCC_STATUS_NOT_SUPPORTED ||
 169             base_status == MCC_STATUS_ILLEGAL_REQUEST ||
 170             addl_status == MCC_ADDL_STATUS_TOO_MANY_INTERFACES ||
 171             addl_status == MCC_ADDL_STATUS_INSUFFICIENT_VLANS ||
 172             (opcode == OPCODE_COMMON_WRITE_FLASHROM &&
 173             (base_status == MCC_STATUS_ILLEGAL_FIELD ||
 174              addl_status == MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH)))
 175                 return true;
 176         else
 177                 return false;
 178 }
 179
 180 /* Place holder for all the async MCC cmds wherein the caller is not in a busy
 181  * loop (has not issued be_mcc_notify_wait())
 182  */
 183 static void be_async_cmd_process(struct be_adapter *adapter,
 184                                  struct be_mcc_compl *compl,
 185                                  struct be_cmd_resp_hdr *resp_hdr)
 186 {
 187         enum mcc_base_status base_status = base_status(compl->status);
 188         u8 opcode = 0, subsystem = 0;
 189
 190         if (resp_hdr) {
 191                 opcode = resp_hdr->opcode;
 192                 subsystem = resp_hdr->subsystem;
 193         }
 194
 195         if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST &&
 196             subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
 197                 complete(&adapter->et_cmd_compl);
 198                 return;
 199         }
 200
 201         if (opcode == OPCODE_LOWLEVEL_SET_LOOPBACK_MODE &&
 202             subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
 203                 complete(&adapter->et_cmd_compl);
 204                 return;
 205         }
 206
 207         if ((opcode == OPCODE_COMMON_WRITE_FLASHROM ||
 208              opcode == OPCODE_COMMON_WRITE_OBJECT) &&
 209             subsystem == CMD_SUBSYSTEM_COMMON) {
 210                 adapter->flash_status = compl->status;
 211                 complete(&adapter->et_cmd_compl);
 212                 return;
 213         }
 214
 215         if ((opcode == OPCODE_ETH_GET_STATISTICS ||
 216              opcode == OPCODE_ETH_GET_PPORT_STATS) &&
 217             subsystem == CMD_SUBSYSTEM_ETH &&
 218             base_status == MCC_STATUS_SUCCESS) {
 219                 be_parse_stats(adapter);
 220                 adapter->stats_cmd_sent = false;
 221                 return;
 222         }
 223
 224         if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
 225             subsystem == CMD_SUBSYSTEM_COMMON) {
 226                 if (base_status == MCC_STATUS_SUCCESS) {
 227                         struct be_cmd_resp_get_cntl_addnl_attribs *resp =
 228                                                         (void *)resp_hdr;
 229                         adapter->hwmon_info.be_on_die_temp =
 230                                                 resp->on_die_temperature;
 231                 } else {
 232                         adapter->be_get_temp_freq = 0;
 233                         adapter->hwmon_info.be_on_die_temp =
 234                                                 BE_INVALID_DIE_TEMP;
 235                 }
 236                 return;
 237         }
 238 }
 239
 240 static int be_mcc_compl_process(struct be_adapter *adapter,
 241                                 struct be_mcc_compl *compl)
 242 {
 243         enum mcc_base_status base_status;
 244         enum mcc_addl_status addl_status;
 245         struct be_cmd_resp_hdr *resp_hdr;
 246         u8 opcode = 0, subsystem = 0;
 247
 248         /* Just swap the status to host endian; mcc tag is opaquely copied
 249          * from mcc_wrb */
 250         be_dws_le_to_cpu(compl, 4);
 251
 252         base_status = base_status(compl->status);
 253         addl_status = addl_status(compl->status);
 254
 255         resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
 256         if (resp_hdr) {
 257                 opcode = resp_hdr->opcode;
 258                 subsystem = resp_hdr->subsystem;
 259         }
 260
 261         be_async_cmd_process(adapter, compl, resp_hdr);
 262
 263         if (base_status != MCC_STATUS_SUCCESS &&
 264             !be_skip_err_log(opcode, base_status, addl_status)) {
 265                 if (base_status == MCC_STATUS_UNAUTHORIZED_REQUEST ||
 266                     addl_status == MCC_ADDL_STATUS_INSUFFICIENT_PRIVILEGES) {
 267                         dev_warn(&adapter->pdev->dev,
 268                                  "VF is not privileged to issue opcode %d-%d\n",
 269                                  opcode, subsystem);
 270                 } else {
 271                         dev_err(&adapter->pdev->dev,
 272                                 "opcode %d-%d failed:status %d-%d\n",
 273                                 opcode, subsystem, base_status, addl_status);
 274                 }
 275         }
 276         return compl->status;
 277 }
 278
 279 /* Link state evt is a string of bytes; no need for endian swapping */
 280 static void be_async_link_state_process(struct be_adapter *adapter,
 281                                         struct be_mcc_compl *compl)
 282 {
 283         struct be_async_event_link_state *evt =
 284                         (struct be_async_event_link_state *)compl;
 285
 286         /* When link status changes, link speed must be re-queried from FW */
 287         adapter->phy.link_speed = -1;
 288
 289         /* On BEx the FW does not send a separate link status
 290          * notification for physical and logical link.
 291          * On other chips just process the logical link
 292          * status notification
 293          */
 294         if (!BEx_chip(adapter) &&
 295             !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
 296                 return;
 297
 298         /* For the initial link status do not rely on the ASYNC event as
 299          * it may not be received in some cases.
 300          */
 301         if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
 302                 be_link_status_update(adapter,
 303                                       evt->port_link_status & LINK_STATUS_MASK);
 304 }
 305
 306 static void be_async_port_misconfig_event_process(struct be_adapter *adapter,
 307                                                   struct be_mcc_compl *compl)
 308 {
 309         struct be_async_event_misconfig_port *evt =
 310                         (struct be_async_event_misconfig_port *)compl;
 311         u32 sfp_misconfig_evt_word1 = le32_to_cpu(evt->event_data_word1);
 312         u32 sfp_misconfig_evt_word2 = le32_to_cpu(evt->event_data_word2);
 313         u8 phy_oper_state = PHY_STATE_OPER_MSG_NONE;
 314         struct device *dev = &adapter->pdev->dev;
 315         u8 msg_severity = DEFAULT_MSG_SEVERITY;
 316         u8 phy_state_info;
 317         u8 new_phy_state;
 318
 319         new_phy_state =
 320                 (sfp_misconfig_evt_word1 >> (adapter->hba_port_num * 8)) & 0xff;
 321
 322         if (new_phy_state == adapter->phy_state)
 323                 return;
 324
 325         adapter->phy_state = new_phy_state;
 326
 327         /* for older fw that doesn't populate link effect data */
 328         if (!sfp_misconfig_evt_word2)
 329                 goto log_message;
 330
 331         phy_state_info =
 332                 (sfp_misconfig_evt_word2 >> (adapter->hba_port_num * 8)) & 0xff;
 333
 334         if (phy_state_info & PHY_STATE_INFO_VALID) {
 335                 msg_severity = (phy_state_info & PHY_STATE_MSG_SEVERITY) >> 1;
 336
 337                 if (be_phy_unqualified(new_phy_state))
 338                         phy_oper_state = (phy_state_info & PHY_STATE_OPER);
 339         }
 340
 341 log_message:
 342         /* Log an error message that would allow a user to determine
 343          * whether the SFPs have an issue
 344          */
 345         if (be_phy_state_unknown(new_phy_state))
 346                 dev_printk(be_port_misconfig_evt_severity[msg_severity], dev,
 347                            "Port %c: Unrecognized Optics state: 0x%x. %s",
 348                            adapter->port_name,
 349                            new_phy_state,
 350                            phy_state_oper_desc[phy_oper_state]);
 351         else
 352                 dev_printk(be_port_misconfig_evt_severity[msg_severity], dev,
 353                            "Port %c: %s %s",
 354                            adapter->port_name,
 355                            be_misconfig_evt_port_state[new_phy_state],
 356                            phy_state_oper_desc[phy_oper_state]);
 357
 358         /* Log Vendor name and part no. if a misconfigured SFP is detected */
 359         if (be_phy_misconfigured(new_phy_state))
 360                 adapter->flags |= BE_FLAGS_PHY_MISCONFIGURED;
 361 }
 362
 363 /* Grp5 CoS Priority evt */
 364 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
 365                                                struct be_mcc_compl *compl)
 366 {
 367         struct be_async_event_grp5_cos_priority *evt =
 368                         (struct be_async_event_grp5_cos_priority *)compl;
 369
 370         if (evt->valid) {
 371                 adapter->vlan_prio_bmap = evt->available_priority_bmap;
 372                 adapter->recommended_prio_bits =
 373                         evt->reco_default_priority << VLAN_PRIO_SHIFT;
 374         }
 375 }
 376
 377 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
 378 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
 379                                             struct be_mcc_compl *compl)
 380 {
 381         struct be_async_event_grp5_qos_link_speed *evt =
 382                         (struct be_async_event_grp5_qos_link_speed *)compl;
 383
 384         if (adapter->phy.link_speed >= 0 &&
 385             evt->physical_port == adapter->port_num)
 386                 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
 387 }
 388
 389 /*Grp5 PVID evt*/
 390 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
 391                                              struct be_mcc_compl *compl)
 392 {
 393         struct be_async_event_grp5_pvid_state *evt =
 394                         (struct be_async_event_grp5_pvid_state *)compl;
 395
 396         if (evt->enabled) {
 397                 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
 398                 dev_info(&adapter->pdev->dev, "LPVID: %d\n", adapter->pvid);
 399         } else {
 400                 adapter->pvid = 0;
 401         }
 402 }
 403
 404 #define MGMT_ENABLE_MASK        0x4
 405 static void be_async_grp5_fw_control_process(struct be_adapter *adapter,
 406                                              struct be_mcc_compl *compl)
 407 {
 408         struct be_async_fw_control *evt = (struct be_async_fw_control *)compl;
 409         u32 evt_dw1 = le32_to_cpu(evt->event_data_word1);
 410
 411         if (evt_dw1 & MGMT_ENABLE_MASK) {
 412                 adapter->flags |= BE_FLAGS_OS2BMC;
 413                 adapter->bmc_filt_mask = le32_to_cpu(evt->event_data_word2);
 414         } else {
 415                 adapter->flags &= ~BE_FLAGS_OS2BMC;
 416         }
 417 }
 418
 419 static void be_async_grp5_evt_process(struct be_adapter *adapter,
 420                                       struct be_mcc_compl *compl)
 421 {
 422         u8 event_type = (compl->flags >> ASYNC_EVENT_TYPE_SHIFT) &
 423                                 ASYNC_EVENT_TYPE_MASK;
 424
 425         switch (event_type) {
 426         case ASYNC_EVENT_COS_PRIORITY:
 427                 be_async_grp5_cos_priority_process(adapter, compl);
 428                 break;
 429         case ASYNC_EVENT_QOS_SPEED:
 430                 be_async_grp5_qos_speed_process(adapter, compl);
 431                 break;
 432         case ASYNC_EVENT_PVID_STATE:
 433                 be_async_grp5_pvid_state_process(adapter, compl);
 434                 break;
 435         /* Async event to disable/enable os2bmc and/or mac-learning */
 436         case ASYNC_EVENT_FW_CONTROL:
 437                 be_async_grp5_fw_control_process(adapter, compl);
 438                 break;
 439         default:
 440                 break;
 441         }
 442 }
 443
 444 static void be_async_dbg_evt_process(struct be_adapter *adapter,
 445                                      struct be_mcc_compl *cmp)
 446 {
 447         u8 event_type = 0;
 448         struct be_async_event_qnq *evt = (struct be_async_event_qnq *)cmp;
 449
 450         event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
 451                         ASYNC_EVENT_TYPE_MASK;
 452
 453         switch (event_type) {
 454         case ASYNC_DEBUG_EVENT_TYPE_QNQ:
 455                 if (evt->valid)
 456                         adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
 457                 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
 458         break;
 459         default:
 460                 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
 461                          event_type);
 462         break;
 463         }
 464 }
 465
 466 static void be_async_sliport_evt_process(struct be_adapter *adapter,
 467                                          struct be_mcc_compl *cmp)
 468 {
 469         u8 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
 470                         ASYNC_EVENT_TYPE_MASK;
 471
 472         if (event_type == ASYNC_EVENT_PORT_MISCONFIG)
 473                 be_async_port_misconfig_event_process(adapter, cmp);
 474 }
 475
 476 static inline bool is_link_state_evt(u32 flags)
 477 {
 478         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 479                         ASYNC_EVENT_CODE_LINK_STATE;
 480 }
 481
 482 static inline bool is_grp5_evt(u32 flags)
 483 {
 484         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 485                         ASYNC_EVENT_CODE_GRP_5;
 486 }
 487
 488 static inline bool is_dbg_evt(u32 flags)
 489 {
 490         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 491                         ASYNC_EVENT_CODE_QNQ;
 492 }
 493
 494 static inline bool is_sliport_evt(u32 flags)
 495 {
 496         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 497                 ASYNC_EVENT_CODE_SLIPORT;
 498 }
 499
 500 static void be_mcc_event_process(struct be_adapter *adapter,
 501                                  struct be_mcc_compl *compl)
 502 {
 503         if (is_link_state_evt(compl->flags))
 504                 be_async_link_state_process(adapter, compl);
 505         else if (is_grp5_evt(compl->flags))
 506                 be_async_grp5_evt_process(adapter, compl);
 507         else if (is_dbg_evt(compl->flags))
 508                 be_async_dbg_evt_process(adapter, compl);
 509         else if (is_sliport_evt(compl->flags))
 510                 be_async_sliport_evt_process(adapter, compl);
 511 }
 512
 513 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
 514 {
 515         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
 516         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
 517
 518         if (be_mcc_compl_is_new(compl)) {
 519                 queue_tail_inc(mcc_cq);
 520                 return compl;
 521         }
 522         return NULL;
 523 }
 524
 525 void be_async_mcc_enable(struct be_adapter *adapter)
 526 {
 527         spin_lock_bh(&adapter->mcc_cq_lock);
 528
 529         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
 530         adapter->mcc_obj.rearm_cq = true;
 531
 532         spin_unlock_bh(&adapter->mcc_cq_lock);
 533 }
 534
 535 void be_async_mcc_disable(struct be_adapter *adapter)
 536 {
 537         spin_lock_bh(&adapter->mcc_cq_lock);
 538
 539         adapter->mcc_obj.rearm_cq = false;
 540         be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
 541
 542         spin_unlock_bh(&adapter->mcc_cq_lock);
 543 }
 544
 545 int be_process_mcc(struct be_adapter *adapter)
 546 {
 547         struct be_mcc_compl *compl;
 548         int num = 0, status = 0;
 549         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 550
 551         spin_lock(&adapter->mcc_cq_lock);
 552
 553         while ((compl = be_mcc_compl_get(adapter))) {
 554                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 555                         be_mcc_event_process(adapter, compl);
 556                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
 557                         status = be_mcc_compl_process(adapter, compl);
 558                         atomic_dec(&mcc_obj->q.used);
 559                 }
 560                 be_mcc_compl_use(compl);
 561                 num++;
 562         }
 563
 564         if (num)
 565                 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
 566
 567         spin_unlock(&adapter->mcc_cq_lock);
 568         return status;
 569 }
 570
 571 /* Wait till no more pending mcc requests are present */
 572 static int be_mcc_wait_compl(struct be_adapter *adapter)
 573 {
 574 #define mcc_timeout             120000 /* 12s timeout */
 575         int i, status = 0;
 576         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 577
 578         for (i = 0; i < mcc_timeout; i++) {
 579                 if (be_check_error(adapter, BE_ERROR_ANY))
 580                         return -EIO;
 581
 582                 local_bh_disable();
 583                 status = be_process_mcc(adapter);
 584                 local_bh_enable();
 585
 586                 if (atomic_read(&mcc_obj->q.used) == 0)
 587                         break;
 588                 udelay(100);
 589         }
 590         if (i == mcc_timeout) {
 591                 dev_err(&adapter->pdev->dev, "FW not responding\n");
 592                 be_set_error(adapter, BE_ERROR_FW);
 593                 return -EIO;
 594         }
 595         return status;
 596 }
 597
 598 /* Notify MCC requests and wait for completion */
 599 static int be_mcc_notify_wait(struct be_adapter *adapter)
 600 {
 601         int status;
 602         struct be_mcc_wrb *wrb;
 603         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 604         u32 index = mcc_obj->q.head;
 605         struct be_cmd_resp_hdr *resp;
 606
 607         index_dec(&index, mcc_obj->q.len);
 608         wrb = queue_index_node(&mcc_obj->q, index);
 609
 610         resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
 611
 612         status = be_mcc_notify(adapter);
 613         if (status)
 614                 goto out;
 615
 616         status = be_mcc_wait_compl(adapter);
 617         if (status == -EIO)
 618                 goto out;
 619
 620         status = (resp->base_status |
 621                   ((resp->addl_status & CQE_ADDL_STATUS_MASK) <<
 622                    CQE_ADDL_STATUS_SHIFT));
 623 out:
 624         return status;
 625 }
 626
 627 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 628 {
 629         int msecs = 0;
 630         u32 ready;
 631
 632         do {
 633                 if (be_check_error(adapter, BE_ERROR_ANY))
 634                         return -EIO;
 635
 636                 ready = ioread32(db);
 637                 if (ready == 0xffffffff)
 638                         return -1;
 639
 640                 ready &= MPU_MAILBOX_DB_RDY_MASK;
 641                 if (ready)
 642                         break;
 643
 644                 if (msecs > 4000) {
 645                         dev_err(&adapter->pdev->dev, "FW not responding\n");
 646                         be_set_error(adapter, BE_ERROR_FW);
 647                         be_detect_error(adapter);
 648                         return -1;
 649                 }
 650
 651                 msleep(1);
 652                 msecs++;
 653         } while (true);
 654
 655         return 0;
 656 }
 657
 658 /*
 659  * Insert the mailbox address into the doorbell in two steps
 660  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 661  */
 662 static int be_mbox_notify_wait(struct be_adapter *adapter)
 663 {
 664         int status;
 665         u32 val = 0;
 666         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 667         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 668         struct be_mcc_mailbox *mbox = mbox_mem->va;
 669         struct be_mcc_compl *compl = &mbox->compl;
 670
 671         /* wait for ready to be set */
 672         status = be_mbox_db_ready_wait(adapter, db);
 673         if (status != 0)
 674                 return status;
 675
 676         val |= MPU_MAILBOX_DB_HI_MASK;
 677         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 678         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 679         iowrite32(val, db);
 680
 681         /* wait for ready to be set */
 682         status = be_mbox_db_ready_wait(adapter, db);
 683         if (status != 0)
 684                 return status;
 685
 686         val = 0;
 687         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 688         val |= (u32)(mbox_mem->dma >> 4) << 2;
 689         iowrite32(val, db);
 690
 691         status = be_mbox_db_ready_wait(adapter, db);
 692         if (status != 0)
 693                 return status;
 694
 695         /* A cq entry has been made now */
 696         if (be_mcc_compl_is_new(compl)) {
 697                 status = be_mcc_compl_process(adapter, &mbox->compl);
 698                 be_mcc_compl_use(compl);
 699                 if (status)
 700                         return status;
 701         } else {
 702                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 703                 return -1;
 704         }
 705         return 0;
 706 }
 707
 708 static u16 be_POST_stage_get(struct be_adapter *adapter)
 709 {
 710         u32 sem;
 711
 712         if (BEx_chip(adapter))
 713                 sem  = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
 714         else
 715                 pci_read_config_dword(adapter->pdev,
 716                                       SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
 717
 718         return sem & POST_STAGE_MASK;
 719 }
 720
 721 static int lancer_wait_ready(struct be_adapter *adapter)
 722 {
 723 #define SLIPORT_READY_TIMEOUT 30
 724         u32 sliport_status;
 725         int i;
 726
 727         for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
 728                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 729                 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
 730                         return 0;
 731
 732                 if (sliport_status & SLIPORT_STATUS_ERR_MASK &&
 733                     !(sliport_status & SLIPORT_STATUS_RN_MASK))
 734                         return -EIO;
 735
 736                 msleep(1000);
 737         }
 738
 739         return sliport_status ? : -1;
 740 }
 741
 742 int be_fw_wait_ready(struct be_adapter *adapter)
 743 {
 744         u16 stage;
 745         int status, timeout = 0;
 746         struct device *dev = &adapter->pdev->dev;
 747
 748         if (lancer_chip(adapter)) {
 749                 status = lancer_wait_ready(adapter);
 750                 if (status) {
 751                         stage = status;
 752                         goto err;
 753                 }
 754                 return 0;
 755         }
 756
 757         do {
 758                 /* There's no means to poll POST state on BE2/3 VFs */
 759                 if (BEx_chip(adapter) && be_virtfn(adapter))
 760                         return 0;
 761
 762                 stage = be_POST_stage_get(adapter);
 763                 if (stage == POST_STAGE_ARMFW_RDY)
 764                         return 0;
 765
 766                 dev_info(dev, "Waiting for POST, %ds elapsed\n", timeout);
 767                 if (msleep_interruptible(2000)) {
 768                         dev_err(dev, "Waiting for POST aborted\n");
 769                         return -EINTR;
 770                 }
 771                 timeout += 2;
 772         } while (timeout < 60);
 773
 774 err:
 775         dev_err(dev, "POST timeout; stage=%#x\n", stage);
 776         return -ETIMEDOUT;
 777 }
 778
 779 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 780 {
 781         return &wrb->payload.sgl[0];
 782 }
 783
 784 static inline void fill_wrb_tags(struct be_mcc_wrb *wrb, unsigned long addr)
 785 {
 786         wrb->tag0 = addr & 0xFFFFFFFF;
 787         wrb->tag1 = upper_32_bits(addr);
 788 }
 789
 790 /* Don't touch the hdr after it's prepared */
 791 /* mem will be NULL for embedded commands */
 792 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 793                                    u8 subsystem, u8 opcode, int cmd_len,
 794                                    struct be_mcc_wrb *wrb,
 795                                    struct be_dma_mem *mem)
 796 {
 797         struct be_sge *sge;
 798
 799         req_hdr->opcode = opcode;
 800         req_hdr->subsystem = subsystem;
 801         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 802         req_hdr->version = 0;
 803         fill_wrb_tags(wrb, (ulong) req_hdr);
 804         wrb->payload_length = cmd_len;
 805         if (mem) {
 806                 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
 807                         MCC_WRB_SGE_CNT_SHIFT;
 808                 sge = nonembedded_sgl(wrb);
 809                 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
 810                 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
 811                 sge->len = cpu_to_le32(mem->size);
 812         } else
 813                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 814         be_dws_cpu_to_le(wrb, 8);
 815 }
 816
 817 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 818                                       struct be_dma_mem *mem)
 819 {
 820         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 821         u64 dma = (u64)mem->dma;
 822
 823         for (i = 0; i < buf_pages; i++) {
 824                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 825                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 826                 dma += PAGE_SIZE_4K;
 827         }
 828 }
 829
 830 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
 831 {
 832         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 833         struct be_mcc_wrb *wrb
 834                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 835         memset(wrb, 0, sizeof(*wrb));
 836         return wrb;
 837 }
 838
 839 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
 840 {
 841         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 842         struct be_mcc_wrb *wrb;
 843
 844         if (!mccq->created)
 845                 return NULL;
 846
 847         if (atomic_read(&mccq->used) >= mccq->len)
 848                 return NULL;
 849
 850         wrb = queue_head_node(mccq);
 851         queue_head_inc(mccq);
 852         atomic_inc(&mccq->used);
 853         memset(wrb, 0, sizeof(*wrb));
 854         return wrb;
 855 }
 856
 857 static bool use_mcc(struct be_adapter *adapter)
 858 {
 859         return adapter->mcc_obj.q.created;
 860 }
 861
 862 /* Must be used only in process context */
 863 static int be_cmd_lock(struct be_adapter *adapter)
 864 {
 865         if (use_mcc(adapter)) {
 866                 spin_lock_bh(&adapter->mcc_lock);
 867                 return 0;
 868         } else {
 869                 return mutex_lock_interruptible(&adapter->mbox_lock);
 870         }
 871 }
 872
 873 /* Must be used only in process context */
 874 static void be_cmd_unlock(struct be_adapter *adapter)
 875 {
 876         if (use_mcc(adapter))
 877                 spin_unlock_bh(&adapter->mcc_lock);
 878         else
 879                 return mutex_unlock(&adapter->mbox_lock);
 880 }
 881
 882 static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter,
 883                                       struct be_mcc_wrb *wrb)
 884 {
 885         struct be_mcc_wrb *dest_wrb;
 886
 887         if (use_mcc(adapter)) {
 888                 dest_wrb = wrb_from_mccq(adapter);
 889                 if (!dest_wrb)
 890                         return NULL;
 891         } else {
 892                 dest_wrb = wrb_from_mbox(adapter);
 893         }
 894
 895         memcpy(dest_wrb, wrb, sizeof(*wrb));
 896         if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK))
 897                 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb));
 898
 899         return dest_wrb;
 900 }
 901
 902 /* Must be used only in process context */
 903 static int be_cmd_notify_wait(struct be_adapter *adapter,
 904                               struct be_mcc_wrb *wrb)
 905 {
 906         struct be_mcc_wrb *dest_wrb;
 907         int status;
 908
 909         status = be_cmd_lock(adapter);
 910         if (status)
 911                 return status;
 912
 913         dest_wrb = be_cmd_copy(adapter, wrb);
 914         if (!dest_wrb) {
 915                 status = -EBUSY;
 916                 goto unlock;
 917         }
 918
 919         if (use_mcc(adapter))
 920                 status = be_mcc_notify_wait(adapter);
 921         else
 922                 status = be_mbox_notify_wait(adapter);
 923
 924         if (!status)
 925                 memcpy(wrb, dest_wrb, sizeof(*wrb));
 926
 927 unlock:
 928         be_cmd_unlock(adapter);
 929         return status;
 930 }
 931
 932 /* Tell fw we're about to start firing cmds by writing a
 933  * special pattern across the wrb hdr; uses mbox
 934  */
 935 int be_cmd_fw_init(struct be_adapter *adapter)
 936 {
 937         u8 *wrb;
 938         int status;
 939
 940         if (lancer_chip(adapter))
 941                 return 0;
 942
 943         if (mutex_lock_interruptible(&adapter->mbox_lock))
 944                 return -1;
 945
 946         wrb = (u8 *)wrb_from_mbox(adapter);
 947         *wrb++ = 0xFF;
 948         *wrb++ = 0x12;
 949         *wrb++ = 0x34;
 950         *wrb++ = 0xFF;
 951         *wrb++ = 0xFF;
 952         *wrb++ = 0x56;
 953         *wrb++ = 0x78;
 954         *wrb = 0xFF;
 955
 956         status = be_mbox_notify_wait(adapter);
 957
 958         mutex_unlock(&adapter->mbox_lock);
 959         return status;
 960 }
 961
 962 /* Tell fw we're done with firing cmds by writing a
 963  * special pattern across the wrb hdr; uses mbox
 964  */
 965 int be_cmd_fw_clean(struct be_adapter *adapter)
 966 {
 967         u8 *wrb;
 968         int status;
 969
 970         if (lancer_chip(adapter))
 971                 return 0;
 972
 973         if (mutex_lock_interruptible(&adapter->mbox_lock))
 974                 return -1;
 975
 976         wrb = (u8 *)wrb_from_mbox(adapter);
 977         *wrb++ = 0xFF;
 978         *wrb++ = 0xAA;
 979         *wrb++ = 0xBB;
 980         *wrb++ = 0xFF;
 981         *wrb++ = 0xFF;
 982         *wrb++ = 0xCC;
 983         *wrb++ = 0xDD;
 984         *wrb = 0xFF;
 985
 986         status = be_mbox_notify_wait(adapter);
 987
 988         mutex_unlock(&adapter->mbox_lock);
 989         return status;
 990 }
 991
 992 int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
 993 {
 994         struct be_mcc_wrb *wrb;
 995         struct be_cmd_req_eq_create *req;
 996         struct be_dma_mem *q_mem = &eqo->q.dma_mem;
 997         int status, ver = 0;
 998
 999         if (mutex_lock_interruptible(&adapter->mbox_lock))
1000                 return -1;
1001
1002         wrb = wrb_from_mbox(adapter);
1003         req = embedded_payload(wrb);
1004
1005         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1006                                OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb,
1007                                NULL);
1008
1009         /* Support for EQ_CREATEv2 available only SH-R onwards */
1010         if (!(BEx_chip(adapter) || lancer_chip(adapter)))
1011                 ver = 2;
1012
1013         req->hdr.version = ver;
1014         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1015
1016         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
1017         /* 4byte eqe*/
1018         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
1019         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
1020                       __ilog2_u32(eqo->q.len / 256));
1021         be_dws_cpu_to_le(req->context, sizeof(req->context));
1022
1023         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1024
1025         status = be_mbox_notify_wait(adapter);
1026         if (!status) {
1027                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
1028
1029                 eqo->q.id = le16_to_cpu(resp->eq_id);
1030                 eqo->msix_idx =
1031                         (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx;
1032                 eqo->q.created = true;
1033         }
1034
1035         mutex_unlock(&adapter->mbox_lock);
1036         return status;
1037 }
1038
1039 /* Use MCC */
1040 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
1041                           bool permanent, u32 if_handle, u32 pmac_id)
1042 {
1043         struct be_mcc_wrb *wrb;
1044         struct be_cmd_req_mac_query *req;
1045         int status;
1046
1047         spin_lock_bh(&adapter->mcc_lock);
1048
1049         wrb = wrb_from_mccq(adapter);
1050         if (!wrb) {
1051                 status = -EBUSY;
1052                 goto err;
1053         }
1054         req = embedded_payload(wrb);
1055
1056         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1057                                OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb,
1058                                NULL);
1059         req->type = MAC_ADDRESS_TYPE_NETWORK;
1060         if (permanent) {
1061                 req->permanent = 1;
1062         } else {
1063                 req->if_id = cpu_to_le16((u16)if_handle);
1064                 req->pmac_id = cpu_to_le32(pmac_id);
1065                 req->permanent = 0;
1066         }
1067
1068         status = be_mcc_notify_wait(adapter);
1069         if (!status) {
1070                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
1071
1072                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
1073         }
1074
1075 err:
1076         spin_unlock_bh(&adapter->mcc_lock);
1077         return status;
1078 }
1079
1080 /* Uses synchronous MCCQ */
1081 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
1082                     u32 if_id, u32 *pmac_id, u32 domain)
1083 {
1084         struct be_mcc_wrb *wrb;
1085         struct be_cmd_req_pmac_add *req;
1086         int status;
1087
1088         spin_lock_bh(&adapter->mcc_lock);
1089
1090         wrb = wrb_from_mccq(adapter);
1091         if (!wrb) {
1092                 status = -EBUSY;
1093                 goto err;
1094         }
1095         req = embedded_payload(wrb);
1096
1097         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1098                                OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb,
1099                                NULL);
1100
1101         req->hdr.domain = domain;
1102         req->if_id = cpu_to_le32(if_id);
1103         memcpy(req->mac_address, mac_addr, ETH_ALEN);
1104
1105         status = be_mcc_notify_wait(adapter);
1106         if (!status) {
1107                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
1108
1109                 *pmac_id = le32_to_cpu(resp->pmac_id);
1110         }
1111
1112 err:
1113         spin_unlock_bh(&adapter->mcc_lock);
1114
1115          if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
1116                 status = -EPERM;
1117
1118         return status;
1119 }
1120
1121 /* Uses synchronous MCCQ */
1122 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
1123 {
1124         struct be_mcc_wrb *wrb;
1125         struct be_cmd_req_pmac_del *req;
1126         int status;
1127
1128         if (pmac_id == -1)
1129                 return 0;
1130
1131         spin_lock_bh(&adapter->mcc_lock);
1132
1133         wrb = wrb_from_mccq(adapter);
1134         if (!wrb) {
1135                 status = -EBUSY;
1136                 goto err;
1137         }
1138         req = embedded_payload(wrb);
1139
1140         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1141                                OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req),
1142                                wrb, NULL);
1143
1144         req->hdr.domain = dom;
1145         req->if_id = cpu_to_le32(if_id);
1146         req->pmac_id = cpu_to_le32(pmac_id);
1147
1148         status = be_mcc_notify_wait(adapter);
1149
1150 err:
1151         spin_unlock_bh(&adapter->mcc_lock);
1152         return status;
1153 }
1154
1155 /* Uses Mbox */
1156 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
1157                      struct be_queue_info *eq, bool no_delay, int coalesce_wm)
1158 {
1159         struct be_mcc_wrb *wrb;
1160         struct be_cmd_req_cq_create *req;
1161         struct be_dma_mem *q_mem = &cq->dma_mem;
1162         void *ctxt;
1163         int status;
1164
1165         if (mutex_lock_interruptible(&adapter->mbox_lock))
1166                 return -1;
1167
1168         wrb = wrb_from_mbox(adapter);
1169         req = embedded_payload(wrb);
1170         ctxt = &req->context;
1171
1172         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1173                                OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb,
1174                                NULL);
1175
1176         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1177
1178         if (BEx_chip(adapter)) {
1179                 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
1180                               coalesce_wm);
1181                 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
1182                               ctxt, no_delay);
1183                 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
1184                               __ilog2_u32(cq->len / 256));
1185                 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
1186                 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
1187                 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
1188         } else {
1189                 req->hdr.version = 2;
1190                 req->page_size = 1; /* 1 for 4K */
1191
1192                 /* coalesce-wm field in this cmd is not relevant to Lancer.
1193                  * Lancer uses COMMON_MODIFY_CQ to set this field
1194                  */
1195                 if (!lancer_chip(adapter))
1196                         AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
1197                                       ctxt, coalesce_wm);
1198                 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
1199                               no_delay);
1200                 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
1201                               __ilog2_u32(cq->len / 256));
1202                 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
1203                 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
1204                 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
1205         }
1206
1207         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1208
1209         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1210
1211         status = be_mbox_notify_wait(adapter);
1212         if (!status) {
1213                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
1214
1215                 cq->id = le16_to_cpu(resp->cq_id);
1216                 cq->created = true;
1217         }
1218
1219         mutex_unlock(&adapter->mbox_lock);
1220
1221         return status;
1222 }
1223
1224 static u32 be_encoded_q_len(int q_len)
1225 {
1226         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
1227
1228         if (len_encoded == 16)
1229                 len_encoded = 0;
1230         return len_encoded;
1231 }
1232
1233 static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
1234                                   struct be_queue_info *mccq,
1235                                   struct be_queue_info *cq)
1236 {
1237         struct be_mcc_wrb *wrb;
1238         struct be_cmd_req_mcc_ext_create *req;
1239         struct be_dma_mem *q_mem = &mccq->dma_mem;
1240         void *ctxt;
1241         int status;
1242
1243         if (mutex_lock_interruptible(&adapter->mbox_lock))
1244                 return -1;
1245
1246         wrb = wrb_from_mbox(adapter);
1247         req = embedded_payload(wrb);
1248         ctxt = &req->context;
1249
1250         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1251                                OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb,
1252                                NULL);
1253
1254         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1255         if (BEx_chip(adapter)) {
1256                 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1257                 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1258                               be_encoded_q_len(mccq->len));
1259                 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1260         } else {
1261                 req->hdr.version = 1;
1262                 req->cq_id = cpu_to_le16(cq->id);
1263
1264                 AMAP_SET_BITS(struct amap_mcc_context_v1, ring_size, ctxt,
1265                               be_encoded_q_len(mccq->len));
1266                 AMAP_SET_BITS(struct amap_mcc_context_v1, valid, ctxt, 1);
1267                 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_id,
1268                               ctxt, cq->id);
1269                 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_valid,
1270                               ctxt, 1);
1271         }
1272
1273         /* Subscribe to Link State, Sliport Event and Group 5 Events
1274          * (bits 1, 5 and 17 set)
1275          */
1276         req->async_event_bitmap[0] =
1277                         cpu_to_le32(BIT(ASYNC_EVENT_CODE_LINK_STATE) |
1278                                     BIT(ASYNC_EVENT_CODE_GRP_5) |
1279                                     BIT(ASYNC_EVENT_CODE_QNQ) |
1280                                     BIT(ASYNC_EVENT_CODE_SLIPORT));
1281
1282         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1283
1284         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1285
1286         status = be_mbox_notify_wait(adapter);
1287         if (!status) {
1288                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1289
1290                 mccq->id = le16_to_cpu(resp->id);
1291                 mccq->created = true;
1292         }
1293         mutex_unlock(&adapter->mbox_lock);
1294
1295         return status;
1296 }
1297
1298 static int be_cmd_mccq_org_create(struct be_adapter *adapter,
1299                                   struct be_queue_info *mccq,
1300                                   struct be_queue_info *cq)
1301 {
1302         struct be_mcc_wrb *wrb;
1303         struct be_cmd_req_mcc_create *req;
1304         struct be_dma_mem *q_mem = &mccq->dma_mem;
1305         void *ctxt;
1306         int status;
1307
1308         if (mutex_lock_interruptible(&adapter->mbox_lock))
1309                 return -1;
1310
1311         wrb = wrb_from_mbox(adapter);
1312         req = embedded_payload(wrb);
1313         ctxt = &req->context;
1314
1315         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1316                                OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb,
1317                                NULL);
1318
1319         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1320
1321         AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1322         AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1323                       be_encoded_q_len(mccq->len));
1324         AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1325
1326         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1327
1328         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1329
1330         status = be_mbox_notify_wait(adapter);
1331         if (!status) {
1332                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1333
1334                 mccq->id = le16_to_cpu(resp->id);
1335                 mccq->created = true;
1336         }
1337
1338         mutex_unlock(&adapter->mbox_lock);
1339         return status;
1340 }
1341
1342 int be_cmd_mccq_create(struct be_adapter *adapter,
1343                        struct be_queue_info *mccq, struct be_queue_info *cq)
1344 {
1345         int status;
1346
1347         status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1348         if (status && BEx_chip(adapter)) {
1349                 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1350                         "or newer to avoid conflicting priorities between NIC "
1351                         "and FCoE traffic");
1352                 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1353         }
1354         return status;
1355 }
1356
1357 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
1358 {
1359         struct be_mcc_wrb wrb = {0};
1360         struct be_cmd_req_eth_tx_create *req;
1361         struct be_queue_info *txq = &txo->q;
1362         struct be_queue_info *cq = &txo->cq;
1363         struct be_dma_mem *q_mem = &txq->dma_mem;
1364         int status, ver = 0;
1365
1366         req = embedded_payload(&wrb);
1367         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1368                                OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL);
1369
1370         if (lancer_chip(adapter)) {
1371                 req->hdr.version = 1;
1372         } else if (BEx_chip(adapter)) {
1373                 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1374                         req->hdr.version = 2;
1375         } else { /* For SH */
1376                 req->hdr.version = 2;
1377         }
1378
1379         if (req->hdr.version > 0)
1380                 req->if_id = cpu_to_le16(adapter->if_handle);
1381         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1382         req->ulp_num = BE_ULP1_NUM;
1383         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1384         req->cq_id = cpu_to_le16(cq->id);
1385         req->queue_size = be_encoded_q_len(txq->len);
1386         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1387         ver = req->hdr.version;
1388
1389         status = be_cmd_notify_wait(adapter, &wrb);
1390         if (!status) {
1391                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb);
1392
1393                 txq->id = le16_to_cpu(resp->cid);
1394                 if (ver == 2)
1395                         txo->db_offset = le32_to_cpu(resp->db_offset);
1396                 else
1397                         txo->db_offset = DB_TXULP1_OFFSET;
1398                 txq->created = true;
1399         }
1400
1401         return status;
1402 }
1403
1404 /* Uses MCC */
1405 int be_cmd_rxq_create(struct be_adapter *adapter,
1406                       struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1407                       u32 if_id, u32 rss, u8 *rss_id)
1408 {
1409         struct be_mcc_wrb *wrb;
1410         struct be_cmd_req_eth_rx_create *req;
1411         struct be_dma_mem *q_mem = &rxq->dma_mem;
1412         int status;
1413
1414         spin_lock_bh(&adapter->mcc_lock);
1415
1416         wrb = wrb_from_mccq(adapter);
1417         if (!wrb) {
1418                 status = -EBUSY;
1419                 goto err;
1420         }
1421         req = embedded_payload(wrb);
1422
1423         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1424                                OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1425
1426         req->cq_id = cpu_to_le16(cq_id);
1427         req->frag_size = fls(frag_size) - 1;
1428         req->num_pages = 2;
1429         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1430         req->interface_id = cpu_to_le32(if_id);
1431         req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
1432         req->rss_queue = cpu_to_le32(rss);
1433
1434         status = be_mcc_notify_wait(adapter);
1435         if (!status) {
1436                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1437
1438                 rxq->id = le16_to_cpu(resp->id);
1439                 rxq->created = true;
1440                 *rss_id = resp->rss_id;
1441         }
1442
1443 err:
1444         spin_unlock_bh(&adapter->mcc_lock);
1445         return status;
1446 }
1447
1448 /* Generic destroyer function for all types of queues
1449  * Uses Mbox
1450  */
1451 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1452                      int queue_type)
1453 {
1454         struct be_mcc_wrb *wrb;
1455         struct be_cmd_req_q_destroy *req;
1456         u8 subsys = 0, opcode = 0;
1457         int status;
1458
1459         if (mutex_lock_interruptible(&adapter->mbox_lock))
1460                 return -1;
1461
1462         wrb = wrb_from_mbox(adapter);
1463         req = embedded_payload(wrb);
1464
1465         switch (queue_type) {
1466         case QTYPE_EQ:
1467                 subsys = CMD_SUBSYSTEM_COMMON;
1468                 opcode = OPCODE_COMMON_EQ_DESTROY;
1469                 break;
1470         case QTYPE_CQ:
1471                 subsys = CMD_SUBSYSTEM_COMMON;
1472                 opcode = OPCODE_COMMON_CQ_DESTROY;
1473                 break;
1474         case QTYPE_TXQ:
1475                 subsys = CMD_SUBSYSTEM_ETH;
1476                 opcode = OPCODE_ETH_TX_DESTROY;
1477                 break;
1478         case QTYPE_RXQ:
1479                 subsys = CMD_SUBSYSTEM_ETH;
1480                 opcode = OPCODE_ETH_RX_DESTROY;
1481                 break;
1482         case QTYPE_MCCQ:
1483                 subsys = CMD_SUBSYSTEM_COMMON;
1484                 opcode = OPCODE_COMMON_MCC_DESTROY;
1485                 break;
1486         default:
1487                 BUG();
1488         }
1489
1490         be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1491                                NULL);
1492         req->id = cpu_to_le16(q->id);
1493
1494         status = be_mbox_notify_wait(adapter);
1495         q->created = false;
1496
1497         mutex_unlock(&adapter->mbox_lock);
1498         return status;
1499 }
1500
1501 /* Uses MCC */
1502 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1503 {
1504         struct be_mcc_wrb *wrb;
1505         struct be_cmd_req_q_destroy *req;
1506         int status;
1507
1508         spin_lock_bh(&adapter->mcc_lock);
1509
1510         wrb = wrb_from_mccq(adapter);
1511         if (!wrb) {
1512                 status = -EBUSY;
1513                 goto err;
1514         }
1515         req = embedded_payload(wrb);
1516
1517         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1518                                OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1519         req->id = cpu_to_le16(q->id);
1520
1521         status = be_mcc_notify_wait(adapter);
1522         q->created = false;
1523
1524 err:
1525         spin_unlock_bh(&adapter->mcc_lock);
1526         return status;
1527 }
1528
1529 /* Create an rx filtering policy configuration on an i/f
1530  * Will use MBOX only if MCCQ has not been created.
1531  */
1532 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1533                      u32 *if_handle, u32 domain)
1534 {
1535         struct be_mcc_wrb wrb = {0};
1536         struct be_cmd_req_if_create *req;
1537         int status;
1538
1539         req = embedded_payload(&wrb);
1540         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1541                                OPCODE_COMMON_NTWK_INTERFACE_CREATE,
1542                                sizeof(*req), &wrb, NULL);
1543         req->hdr.domain = domain;
1544         req->capability_flags = cpu_to_le32(cap_flags);
1545         req->enable_flags = cpu_to_le32(en_flags);
1546         req->pmac_invalid = true;
1547
1548         status = be_cmd_notify_wait(adapter, &wrb);
1549         if (!status) {
1550                 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb);
1551
1552                 *if_handle = le32_to_cpu(resp->interface_id);
1553
1554                 /* Hack to retrieve VF's pmac-id on BE3 */
1555                 if (BE3_chip(adapter) && be_virtfn(adapter))
1556                         adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
1557         }
1558         return status;
1559 }
1560
1561 /* Uses MCCQ if available else MBOX */
1562 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1563 {
1564         struct be_mcc_wrb wrb = {0};
1565         struct be_cmd_req_if_destroy *req;
1566         int status;
1567
1568         if (interface_id == -1)
1569                 return 0;
1570
1571         req = embedded_payload(&wrb);
1572
1573         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1574                                OPCODE_COMMON_NTWK_INTERFACE_DESTROY,
1575                                sizeof(*req), &wrb, NULL);
1576         req->hdr.domain = domain;
1577         req->interface_id = cpu_to_le32(interface_id);
1578
1579         status = be_cmd_notify_wait(adapter, &wrb);
1580         return status;
1581 }
1582
1583 /* Get stats is a non embedded command: the request is not embedded inside
1584  * WRB but is a separate dma memory block
1585  * Uses asynchronous MCC
1586  */
1587 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1588 {
1589         struct be_mcc_wrb *wrb;
1590         struct be_cmd_req_hdr *hdr;
1591         int status = 0;
1592
1593         spin_lock_bh(&adapter->mcc_lock);
1594
1595         wrb = wrb_from_mccq(adapter);
1596         if (!wrb) {
1597                 status = -EBUSY;
1598                 goto err;
1599         }
1600         hdr = nonemb_cmd->va;
1601
1602         be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1603                                OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb,
1604                                nonemb_cmd);
1605
1606         /* version 1 of the cmd is not supported only by BE2 */
1607         if (BE2_chip(adapter))
1608                 hdr->version = 0;
1609         if (BE3_chip(adapter) || lancer_chip(adapter))
1610                 hdr->version = 1;
1611         else
1612                 hdr->version = 2;
1613
1614         status = be_mcc_notify(adapter);
1615         if (status)
1616                 goto err;
1617
1618         adapter->stats_cmd_sent = true;
1619
1620 err:
1621         spin_unlock_bh(&adapter->mcc_lock);
1622         return status;
1623 }
1624
1625 /* Lancer Stats */
1626 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1627                                struct be_dma_mem *nonemb_cmd)
1628 {
1629         struct be_mcc_wrb *wrb;
1630         struct lancer_cmd_req_pport_stats *req;
1631         int status = 0;
1632
1633         if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1634                             CMD_SUBSYSTEM_ETH))
1635                 return -EPERM;
1636
1637         spin_lock_bh(&adapter->mcc_lock);
1638
1639         wrb = wrb_from_mccq(adapter);
1640         if (!wrb) {
1641                 status = -EBUSY;
1642                 goto err;
1643         }
1644         req = nonemb_cmd->va;
1645
1646         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1647                                OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size,
1648                                wrb, nonemb_cmd);
1649
1650         req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1651         req->cmd_params.params.reset_stats = 0;
1652
1653         status = be_mcc_notify(adapter);
1654         if (status)
1655                 goto err;
1656
1657         adapter->stats_cmd_sent = true;
1658
1659 err:
1660         spin_unlock_bh(&adapter->mcc_lock);
1661         return status;
1662 }
1663
1664 static int be_mac_to_link_speed(int mac_speed)
1665 {
1666         switch (mac_speed) {
1667         case PHY_LINK_SPEED_ZERO:
1668                 return 0;
1669         case PHY_LINK_SPEED_10MBPS:
1670                 return 10;
1671         case PHY_LINK_SPEED_100MBPS:
1672                 return 100;
1673         case PHY_LINK_SPEED_1GBPS:
1674                 return 1000;
1675         case PHY_LINK_SPEED_10GBPS:
1676                 return 10000;
1677         case PHY_LINK_SPEED_20GBPS:
1678                 return 20000;
1679         case PHY_LINK_SPEED_25GBPS:
1680                 return 25000;
1681         case PHY_LINK_SPEED_40GBPS:
1682                 return 40000;
1683         }
1684         return 0;
1685 }
1686
1687 /* Uses synchronous mcc
1688  * Returns link_speed in Mbps
1689  */
1690 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1691                              u8 *link_status, u32 dom)
1692 {
1693         struct be_mcc_wrb *wrb;
1694         struct be_cmd_req_link_status *req;
1695         int status;
1696
1697         spin_lock_bh(&adapter->mcc_lock);
1698
1699         if (link_status)
1700                 *link_status = LINK_DOWN;
1701
1702         wrb = wrb_from_mccq(adapter);
1703         if (!wrb) {
1704                 status = -EBUSY;
1705                 goto err;
1706         }
1707         req = embedded_payload(wrb);
1708
1709         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1710                                OPCODE_COMMON_NTWK_LINK_STATUS_QUERY,
1711                                sizeof(*req), wrb, NULL);
1712
1713         /* version 1 of the cmd is not supported only by BE2 */
1714         if (!BE2_chip(adapter))
1715                 req->hdr.version = 1;
1716
1717         req->hdr.domain = dom;
1718
1719         status = be_mcc_notify_wait(adapter);
1720         if (!status) {
1721                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1722
1723                 if (link_speed) {
1724                         *link_speed = resp->link_speed ?
1725                                       le16_to_cpu(resp->link_speed) * 10 :
1726                                       be_mac_to_link_speed(resp->mac_speed);
1727
1728                         if (!resp->logical_link_status)
1729                                 *link_speed = 0;
1730                 }
1731                 if (link_status)
1732                         *link_status = resp->logical_link_status;
1733         }
1734
1735 err:
1736         spin_unlock_bh(&adapter->mcc_lock);
1737         return status;
1738 }
1739
1740 /* Uses synchronous mcc */
1741 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1742 {
1743         struct be_mcc_wrb *wrb;
1744         struct be_cmd_req_get_cntl_addnl_attribs *req;
1745         int status = 0;
1746
1747         spin_lock_bh(&adapter->mcc_lock);
1748
1749         wrb = wrb_from_mccq(adapter);
1750         if (!wrb) {
1751                 status = -EBUSY;
1752                 goto err;
1753         }
1754         req = embedded_payload(wrb);
1755
1756         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1757                                OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES,
1758                                sizeof(*req), wrb, NULL);
1759
1760         status = be_mcc_notify(adapter);
1761 err:
1762         spin_unlock_bh(&adapter->mcc_lock);
1763         return status;
1764 }
1765
1766 /* Uses synchronous mcc */
1767 int be_cmd_get_fat_dump_len(struct be_adapter *adapter, u32 *dump_size)
1768 {
1769         struct be_mcc_wrb wrb = {0};
1770         struct be_cmd_req_get_fat *req;
1771         int status;
1772
1773         req = embedded_payload(&wrb);
1774
1775         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1776                                OPCODE_COMMON_MANAGE_FAT, sizeof(*req),
1777                                &wrb, NULL);
1778         req->fat_operation = cpu_to_le32(QUERY_FAT);
1779         status = be_cmd_notify_wait(adapter, &wrb);
1780         if (!status) {
1781                 struct be_cmd_resp_get_fat *resp = embedded_payload(&wrb);
1782
1783                 if (dump_size && resp->log_size)
1784                         *dump_size = le32_to_cpu(resp->log_size) -
1785                                         sizeof(u32);
1786         }
1787         return status;
1788 }
1789
1790 int be_cmd_get_fat_dump(struct be_adapter *adapter, u32 buf_len, void *buf)
1791 {
1792         struct be_dma_mem get_fat_cmd;
1793         struct be_mcc_wrb *wrb;
1794         struct be_cmd_req_get_fat *req;
1795         u32 offset = 0, total_size, buf_size,
1796                                 log_offset = sizeof(u32), payload_len;
1797         int status;
1798
1799         if (buf_len == 0)
1800                 return 0;
1801
1802         total_size = buf_len;
1803
1804         get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1805         get_fat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
1806                                              get_fat_cmd.size,
1807                                              &get_fat_cmd.dma, GFP_ATOMIC);
1808         if (!get_fat_cmd.va)
1809                 return -ENOMEM;
1810
1811         spin_lock_bh(&adapter->mcc_lock);
1812
1813         while (total_size) {
1814                 buf_size = min(total_size, (u32)60*1024);
1815                 total_size -= buf_size;
1816
1817                 wrb = wrb_from_mccq(adapter);
1818                 if (!wrb) {
1819                         status = -EBUSY;
1820                         goto err;
1821                 }
1822                 req = get_fat_cmd.va;
1823
1824                 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1825                 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1826                                        OPCODE_COMMON_MANAGE_FAT, payload_len,
1827                                        wrb, &get_fat_cmd);
1828
1829                 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1830                 req->read_log_offset = cpu_to_le32(log_offset);
1831                 req->read_log_length = cpu_to_le32(buf_size);
1832                 req->data_buffer_size = cpu_to_le32(buf_size);
1833
1834                 status = be_mcc_notify_wait(adapter);
1835                 if (!status) {
1836                         struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1837
1838                         memcpy(buf + offset,
1839                                resp->data_buffer,
1840                                le32_to_cpu(resp->read_log_length));
1841                 } else {
1842                         dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1843                         goto err;
1844                 }
1845                 offset += buf_size;
1846                 log_offset += buf_size;
1847         }
1848 err:
1849         dma_free_coherent(&adapter->pdev->dev, get_fat_cmd.size,
1850                           get_fat_cmd.va, get_fat_cmd.dma);
1851         spin_unlock_bh(&adapter->mcc_lock);
1852         return status;
1853 }
1854
1855 /* Uses synchronous mcc */
1856 int be_cmd_get_fw_ver(struct be_adapter *adapter)
1857 {
1858         struct be_mcc_wrb *wrb;
1859         struct be_cmd_req_get_fw_version *req;
1860         int status;
1861
1862         spin_lock_bh(&adapter->mcc_lock);
1863
1864         wrb = wrb_from_mccq(adapter);
1865         if (!wrb) {
1866                 status = -EBUSY;
1867                 goto err;
1868         }
1869
1870         req = embedded_payload(wrb);
1871
1872         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1873                                OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb,
1874                                NULL);
1875         status = be_mcc_notify_wait(adapter);
1876         if (!status) {
1877                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1878
1879                 strlcpy(adapter->fw_ver, resp->firmware_version_string,
1880                         sizeof(adapter->fw_ver));
1881                 strlcpy(adapter->fw_on_flash, resp->fw_on_flash_version_string,
1882                         sizeof(adapter->fw_on_flash));
1883         }
1884 err:
1885         spin_unlock_bh(&adapter->mcc_lock);
1886         return status;
1887 }
1888
1889 /* set the EQ delay interval of an EQ to specified value
1890  * Uses async mcc
1891  */
1892 static int __be_cmd_modify_eqd(struct be_adapter *adapter,
1893                                struct be_set_eqd *set_eqd, int num)
1894 {
1895         struct be_mcc_wrb *wrb;
1896         struct be_cmd_req_modify_eq_delay *req;
1897         int status = 0, i;
1898
1899         spin_lock_bh(&adapter->mcc_lock);
1900
1901         wrb = wrb_from_mccq(adapter);
1902         if (!wrb) {
1903                 status = -EBUSY;
1904                 goto err;
1905         }
1906         req = embedded_payload(wrb);
1907
1908         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1909                                OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb,
1910                                NULL);
1911
1912         req->num_eq = cpu_to_le32(num);
1913         for (i = 0; i < num; i++) {
1914                 req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id);
1915                 req->set_eqd[i].phase = 0;
1916                 req->set_eqd[i].delay_multiplier =
1917                                 cpu_to_le32(set_eqd[i].delay_multiplier);
1918         }
1919
1920         status = be_mcc_notify(adapter);
1921 err:
1922         spin_unlock_bh(&adapter->mcc_lock);
1923         return status;
1924 }
1925
1926 int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd,
1927                       int num)
1928 {
1929         int num_eqs, i = 0;
1930
1931         while (num) {
1932                 num_eqs = min(num, 8);
1933                 __be_cmd_modify_eqd(adapter, &set_eqd[i], num_eqs);
1934                 i += num_eqs;
1935                 num -= num_eqs;
1936         }
1937
1938         return 0;
1939 }
1940
1941 /* Uses sycnhronous mcc */
1942 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1943                        u32 num, u32 domain)
1944 {
1945         struct be_mcc_wrb *wrb;
1946         struct be_cmd_req_vlan_config *req;
1947         int status;
1948
1949         spin_lock_bh(&adapter->mcc_lock);
1950
1951         wrb = wrb_from_mccq(adapter);
1952         if (!wrb) {
1953                 status = -EBUSY;
1954                 goto err;
1955         }
1956         req = embedded_payload(wrb);
1957
1958         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1959                                OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req),
1960                                wrb, NULL);
1961         req->hdr.domain = domain;
1962
1963         req->interface_id = if_id;
1964         req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0;
1965         req->num_vlan = num;
1966         memcpy(req->normal_vlan, vtag_array,
1967                req->num_vlan * sizeof(vtag_array[0]));
1968
1969         status = be_mcc_notify_wait(adapter);
1970 err:
1971         spin_unlock_bh(&adapter->mcc_lock);
1972         return status;
1973 }
1974
1975 static int __be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1976 {
1977         struct be_mcc_wrb *wrb;
1978         struct be_dma_mem *mem = &adapter->rx_filter;
1979         struct be_cmd_req_rx_filter *req = mem->va;
1980         int status;
1981
1982         spin_lock_bh(&adapter->mcc_lock);
1983
1984         wrb = wrb_from_mccq(adapter);
1985         if (!wrb) {
1986                 status = -EBUSY;
1987                 goto err;
1988         }
1989         memset(req, 0, sizeof(*req));
1990         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1991                                OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1992                                wrb, mem);
1993
1994         req->if_id = cpu_to_le32(adapter->if_handle);
1995         req->if_flags_mask = cpu_to_le32(flags);
1996         req->if_flags = (value == ON) ? req->if_flags_mask : 0;
1997
1998         if (flags & BE_IF_FLAGS_MULTICAST) {
1999                 struct netdev_hw_addr *ha;
2000                 int i = 0;
2001
2002                 /* Reset mcast promisc mode if already set by setting mask
2003                  * and not setting flags field
2004                  */
2005                 req->if_flags_mask |=
2006                         cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
2007                                     be_if_cap_flags(adapter));
2008                 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
2009                 netdev_for_each_mc_addr(ha, adapter->netdev)
2010                         memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
2011         }
2012
2013         status = be_mcc_notify_wait(adapter);
2014 err:
2015         spin_unlock_bh(&adapter->mcc_lock);
2016         return status;
2017 }
2018
2019 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
2020 {
2021         struct device *dev = &adapter->pdev->dev;
2022
2023         if ((flags & be_if_cap_flags(adapter)) != flags) {
2024                 dev_warn(dev, "Cannot set rx filter flags 0x%x\n", flags);
2025                 dev_warn(dev, "Interface is capable of 0x%x flags only\n",
2026                          be_if_cap_flags(adapter));
2027         }
2028         flags &= be_if_cap_flags(adapter);
2029         if (!flags)
2030                 return -ENOTSUPP;
2031
2032         return __be_cmd_rx_filter(adapter, flags, value);
2033 }
2034
2035 /* Uses synchrounous mcc */
2036 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
2037 {
2038         struct be_mcc_wrb *wrb;
2039         struct be_cmd_req_set_flow_control *req;
2040         int status;
2041
2042         if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
2043                             CMD_SUBSYSTEM_COMMON))
2044                 return -EPERM;
2045
2046         spin_lock_bh(&adapter->mcc_lock);
2047
2048         wrb = wrb_from_mccq(adapter);
2049         if (!wrb) {
2050                 status = -EBUSY;
2051                 goto err;
2052         }
2053         req = embedded_payload(wrb);
2054
2055         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2056                                OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req),
2057                                wrb, NULL);
2058
2059         req->hdr.version = 1;
2060         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
2061         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
2062
2063         status = be_mcc_notify_wait(adapter);
2064
2065 err:
2066         spin_unlock_bh(&adapter->mcc_lock);
2067
2068         if (base_status(status) == MCC_STATUS_FEATURE_NOT_SUPPORTED)
2069                 return  -EOPNOTSUPP;
2070
2071         return status;
2072 }
2073
2074 /* Uses sycn mcc */
2075 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
2076 {
2077         struct be_mcc_wrb *wrb;
2078         struct be_cmd_req_get_flow_control *req;
2079         int status;
2080
2081         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
2082                             CMD_SUBSYSTEM_COMMON))
2083                 return -EPERM;
2084
2085         spin_lock_bh(&adapter->mcc_lock);
2086
2087         wrb = wrb_from_mccq(adapter);
2088         if (!wrb) {
2089                 status = -EBUSY;
2090                 goto err;
2091         }
2092         req = embedded_payload(wrb);
2093
2094         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2095                                OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req),
2096                                wrb, NULL);
2097
2098         status = be_mcc_notify_wait(adapter);
2099         if (!status) {
2100                 struct be_cmd_resp_get_flow_control *resp =
2101                                                 embedded_payload(wrb);
2102
2103                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
2104                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
2105         }
2106
2107 err:
2108         spin_unlock_bh(&adapter->mcc_lock);
2109         return status;
2110 }
2111
2112 /* Uses mbox */
2113 int be_cmd_query_fw_cfg(struct be_adapter *adapter)
2114 {
2115         struct be_mcc_wrb *wrb;
2116         struct be_cmd_req_query_fw_cfg *req;
2117         int status;
2118
2119         if (mutex_lock_interruptible(&adapter->mbox_lock))
2120                 return -1;
2121
2122         wrb = wrb_from_mbox(adapter);
2123         req = embedded_payload(wrb);
2124
2125         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2126                                OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
2127                                sizeof(*req), wrb, NULL);
2128
2129         status = be_mbox_notify_wait(adapter);
2130         if (!status) {
2131                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
2132
2133                 adapter->port_num = le32_to_cpu(resp->phys_port);
2134                 adapter->function_mode = le32_to_cpu(resp->function_mode);
2135                 adapter->function_caps = le32_to_cpu(resp->function_caps);
2136                 adapter->asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
2137                 dev_info(&adapter->pdev->dev,
2138                          "FW config: function_mode=0x%x, function_caps=0x%x\n",
2139                          adapter->function_mode, adapter->function_caps);
2140         }
2141
2142         mutex_unlock(&adapter->mbox_lock);
2143         return status;
2144 }
2145
2146 /* Uses mbox */
2147 int be_cmd_reset_function(struct be_adapter *adapter)
2148 {
2149         struct be_mcc_wrb *wrb;
2150         struct be_cmd_req_hdr *req;
2151         int status;
2152
2153         if (lancer_chip(adapter)) {
2154                 iowrite32(SLI_PORT_CONTROL_IP_MASK,
2155                           adapter->db + SLIPORT_CONTROL_OFFSET);
2156                 status = lancer_wait_ready(adapter);
2157                 if (status)
2158                         dev_err(&adapter->pdev->dev,
2159                                 "Adapter in non recoverable error\n");
2160                 return status;
2161         }
2162
2163         if (mutex_lock_interruptible(&adapter->mbox_lock))
2164                 return -1;
2165
2166         wrb = wrb_from_mbox(adapter);
2167         req = embedded_payload(wrb);
2168
2169         be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
2170                                OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb,
2171                                NULL);
2172
2173         status = be_mbox_notify_wait(adapter);
2174
2175         mutex_unlock(&adapter->mbox_lock);
2176         return status;
2177 }
2178
2179 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
2180                       u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey)
2181 {
2182         struct be_mcc_wrb *wrb;
2183         struct be_cmd_req_rss_config *req;
2184         int status;
2185
2186         if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS))
2187                 return 0;
2188
2189         spin_lock_bh(&adapter->mcc_lock);
2190
2191         wrb = wrb_from_mccq(adapter);
2192         if (!wrb) {
2193                 status = -EBUSY;
2194                 goto err;
2195         }
2196         req = embedded_payload(wrb);
2197
2198         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2199                                OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
2200
2201         req->if_id = cpu_to_le32(adapter->if_handle);
2202         req->enable_rss = cpu_to_le16(rss_hash_opts);
2203         req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
2204
2205         if (!BEx_chip(adapter))
2206                 req->hdr.version = 1;
2207
2208         memcpy(req->cpu_table, rsstable, table_size);
2209         memcpy(req->hash, rss_hkey, RSS_HASH_KEY_LEN);
2210         be_dws_cpu_to_le(req->hash, sizeof(req->hash));
2211
2212         status = be_mcc_notify_wait(adapter);
2213 err:
2214         spin_unlock_bh(&adapter->mcc_lock);
2215         return status;
2216 }
2217
2218 /* Uses sync mcc */
2219 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
2220                             u8 bcn, u8 sts, u8 state)
2221 {
2222         struct be_mcc_wrb *wrb;
2223         struct be_cmd_req_enable_disable_beacon *req;
2224         int status;
2225
2226         spin_lock_bh(&adapter->mcc_lock);
2227
2228         wrb = wrb_from_mccq(adapter);
2229         if (!wrb) {
2230                 status = -EBUSY;
2231                 goto err;
2232         }
2233         req = embedded_payload(wrb);
2234
2235         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2236                                OPCODE_COMMON_ENABLE_DISABLE_BEACON,
2237                                sizeof(*req), wrb, NULL);
2238
2239         req->port_num = port_num;
2240         req->beacon_state = state;
2241         req->beacon_duration = bcn;
2242         req->status_duration = sts;
2243
2244         status = be_mcc_notify_wait(adapter);
2245
2246 err:
2247         spin_unlock_bh(&adapter->mcc_lock);
2248         return status;
2249 }
2250
2251 /* Uses sync mcc */
2252 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2253 {
2254         struct be_mcc_wrb *wrb;
2255         struct be_cmd_req_get_beacon_state *req;
2256         int status;
2257
2258         spin_lock_bh(&adapter->mcc_lock);
2259
2260         wrb = wrb_from_mccq(adapter);
2261         if (!wrb) {
2262                 status = -EBUSY;
2263                 goto err;
2264         }
2265         req = embedded_payload(wrb);
2266
2267         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2268                                OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req),
2269                                wrb, NULL);
2270
2271         req->port_num = port_num;
2272
2273         status = be_mcc_notify_wait(adapter);
2274         if (!status) {
2275                 struct be_cmd_resp_get_beacon_state *resp =
2276                                                 embedded_payload(wrb);
2277
2278                 *state = resp->beacon_state;
2279         }
2280
2281 err:
2282         spin_unlock_bh(&adapter->mcc_lock);
2283         return status;
2284 }
2285
2286 /* Uses sync mcc */
2287 int be_cmd_read_port_transceiver_data(struct be_adapter *adapter,
2288                                       u8 page_num, u8 *data)
2289 {
2290         struct be_dma_mem cmd;
2291         struct be_mcc_wrb *wrb;
2292         struct be_cmd_req_port_type *req;
2293         int status;
2294
2295         if (page_num > TR_PAGE_A2)
2296                 return -EINVAL;
2297
2298         cmd.size = sizeof(struct be_cmd_resp_port_type);
2299         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
2300                                      GFP_ATOMIC);
2301         if (!cmd.va) {
2302                 dev_err(&adapter->pdev->dev, "Memory allocation failed\n");
2303                 return -ENOMEM;
2304         }
2305
2306         spin_lock_bh(&adapter->mcc_lock);
2307
2308         wrb = wrb_from_mccq(adapter);
2309         if (!wrb) {
2310                 status = -EBUSY;
2311                 goto err;
2312         }
2313         req = cmd.va;
2314
2315         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2316                                OPCODE_COMMON_READ_TRANSRECV_DATA,
2317                                cmd.size, wrb, &cmd);
2318
2319         req->port = cpu_to_le32(adapter->hba_port_num);
2320         req->page_num = cpu_to_le32(page_num);
2321         status = be_mcc_notify_wait(adapter);
2322         if (!status) {
2323                 struct be_cmd_resp_port_type *resp = cmd.va;
2324
2325                 memcpy(data, resp->page_data, PAGE_DATA_LEN);
2326         }
2327 err:
2328         spin_unlock_bh(&adapter->mcc_lock);
2329         dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
2330         return status;
2331 }
2332
2333 static int lancer_cmd_write_object(struct be_adapter *adapter,
2334                                    struct be_dma_mem *cmd, u32 data_size,
2335                                    u32 data_offset, const char *obj_name,
2336                                    u32 *data_written, u8 *change_status,
2337                                    u8 *addn_status)
2338 {
2339         struct be_mcc_wrb *wrb;
2340         struct lancer_cmd_req_write_object *req;
2341         struct lancer_cmd_resp_write_object *resp;
2342         void *ctxt = NULL;
2343         int status;
2344
2345         spin_lock_bh(&adapter->mcc_lock);
2346         adapter->flash_status = 0;
2347
2348         wrb = wrb_from_mccq(adapter);
2349         if (!wrb) {
2350                 status = -EBUSY;
2351                 goto err_unlock;
2352         }
2353
2354         req = embedded_payload(wrb);
2355
2356         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2357                                OPCODE_COMMON_WRITE_OBJECT,
2358                                sizeof(struct lancer_cmd_req_write_object), wrb,
2359                                NULL);
2360
2361         ctxt = &req->context;
2362         AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2363                       write_length, ctxt, data_size);
2364
2365         if (data_size == 0)
2366                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2367                               eof, ctxt, 1);
2368         else
2369                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2370                               eof, ctxt, 0);
2371
2372         be_dws_cpu_to_le(ctxt, sizeof(req->context));
2373         req->write_offset = cpu_to_le32(data_offset);
2374         strlcpy(req->object_name, obj_name, sizeof(req->object_name));
2375         req->descriptor_count = cpu_to_le32(1);
2376         req->buf_len = cpu_to_le32(data_size);
2377         req->addr_low = cpu_to_le32((cmd->dma +
2378                                      sizeof(struct lancer_cmd_req_write_object))
2379                                     & 0xFFFFFFFF);
2380         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2381                                 sizeof(struct lancer_cmd_req_write_object)));
2382
2383         status = be_mcc_notify(adapter);
2384         if (status)
2385                 goto err_unlock;
2386
2387         spin_unlock_bh(&adapter->mcc_lock);
2388
2389         if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2390                                          msecs_to_jiffies(60000)))
2391                 status = -ETIMEDOUT;
2392         else
2393                 status = adapter->flash_status;
2394
2395         resp = embedded_payload(wrb);
2396         if (!status) {
2397                 *data_written = le32_to_cpu(resp->actual_write_len);
2398                 *change_status = resp->change_status;
2399         } else {
2400                 *addn_status = resp->additional_status;
2401         }
2402
2403         return status;
2404
2405 err_unlock:
2406         spin_unlock_bh(&adapter->mcc_lock);
2407         return status;
2408 }
2409
2410 int be_cmd_query_cable_type(struct be_adapter *adapter)
2411 {
2412         u8 page_data[PAGE_DATA_LEN];
2413         int status;
2414
2415         status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2416                                                    page_data);
2417         if (!status) {
2418                 switch (adapter->phy.interface_type) {
2419                 case PHY_TYPE_QSFP:
2420                         adapter->phy.cable_type =
2421                                 page_data[QSFP_PLUS_CABLE_TYPE_OFFSET];
2422                         break;
2423                 case PHY_TYPE_SFP_PLUS_10GB:
2424                         adapter->phy.cable_type =
2425                                 page_data[SFP_PLUS_CABLE_TYPE_OFFSET];
2426                         break;
2427                 default:
2428                         adapter->phy.cable_type = 0;
2429                         break;
2430                 }
2431         }
2432         return status;
2433 }
2434
2435 int be_cmd_query_sfp_info(struct be_adapter *adapter)
2436 {
2437         u8 page_data[PAGE_DATA_LEN];
2438         int status;
2439
2440         status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2441                                                    page_data);
2442         if (!status) {
2443                 strlcpy(adapter->phy.vendor_name, page_data +
2444                         SFP_VENDOR_NAME_OFFSET, SFP_VENDOR_NAME_LEN - 1);
2445                 strlcpy(adapter->phy.vendor_pn,
2446                         page_data + SFP_VENDOR_PN_OFFSET,
2447                         SFP_VENDOR_NAME_LEN - 1);
2448         }
2449
2450         return status;
2451 }
2452
2453 static int lancer_cmd_delete_object(struct be_adapter *adapter,
2454                                     const char *obj_name)
2455 {
2456         struct lancer_cmd_req_delete_object *req;
2457         struct be_mcc_wrb *wrb;
2458         int status;
2459
2460         spin_lock_bh(&adapter->mcc_lock);
2461
2462         wrb = wrb_from_mccq(adapter);
2463         if (!wrb) {
2464                 status = -EBUSY;
2465                 goto err;
2466         }
2467
2468         req = embedded_payload(wrb);
2469
2470         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2471                                OPCODE_COMMON_DELETE_OBJECT,
2472                                sizeof(*req), wrb, NULL);
2473
2474         strlcpy(req->object_name, obj_name, sizeof(req->object_name));
2475
2476         status = be_mcc_notify_wait(adapter);
2477 err:
2478         spin_unlock_bh(&adapter->mcc_lock);
2479         return status;
2480 }
2481
2482 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2483                            u32 data_size, u32 data_offset, const char *obj_name,
2484                            u32 *data_read, u32 *eof, u8 *addn_status)
2485 {
2486         struct be_mcc_wrb *wrb;
2487         struct lancer_cmd_req_read_object *req;
2488         struct lancer_cmd_resp_read_object *resp;
2489         int status;
2490
2491         spin_lock_bh(&adapter->mcc_lock);
2492
2493         wrb = wrb_from_mccq(adapter);
2494         if (!wrb) {
2495                 status = -EBUSY;
2496                 goto err_unlock;
2497         }
2498
2499         req = embedded_payload(wrb);
2500
2501         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2502                                OPCODE_COMMON_READ_OBJECT,
2503                                sizeof(struct lancer_cmd_req_read_object), wrb,
2504                                NULL);
2505
2506         req->desired_read_len = cpu_to_le32(data_size);
2507         req->read_offset = cpu_to_le32(data_offset);
2508         strcpy(req->object_name, obj_name);
2509         req->descriptor_count = cpu_to_le32(1);
2510         req->buf_len = cpu_to_le32(data_size);
2511         req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2512         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2513
2514         status = be_mcc_notify_wait(adapter);
2515
2516         resp = embedded_payload(wrb);
2517         if (!status) {
2518                 *data_read = le32_to_cpu(resp->actual_read_len);
2519                 *eof = le32_to_cpu(resp->eof);
2520         } else {
2521                 *addn_status = resp->additional_status;
2522         }
2523
2524 err_unlock:
2525         spin_unlock_bh(&adapter->mcc_lock);
2526         return status;
2527 }
2528
2529 static int be_cmd_write_flashrom(struct be_adapter *adapter,
2530                                  struct be_dma_mem *cmd, u32 flash_type,
2531                                  u32 flash_opcode, u32 img_offset, u32 buf_size)
2532 {
2533         struct be_mcc_wrb *wrb;
2534         struct be_cmd_write_flashrom *req;
2535         int status;
2536
2537         spin_lock_bh(&adapter->mcc_lock);
2538         adapter->flash_status = 0;
2539
2540         wrb = wrb_from_mccq(adapter);
2541         if (!wrb) {
2542                 status = -EBUSY;
2543                 goto err_unlock;
2544         }
2545         req = cmd->va;
2546
2547         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2548                                OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb,
2549                                cmd);
2550
2551         req->params.op_type = cpu_to_le32(flash_type);
2552         if (flash_type == OPTYPE_OFFSET_SPECIFIED)
2553                 req->params.offset = cpu_to_le32(img_offset);
2554
2555         req->params.op_code = cpu_to_le32(flash_opcode);
2556         req->params.data_buf_size = cpu_to_le32(buf_size);
2557
2558         status = be_mcc_notify(adapter);
2559         if (status)
2560                 goto err_unlock;
2561
2562         spin_unlock_bh(&adapter->mcc_lock);
2563
2564         if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2565                                          msecs_to_jiffies(40000)))
2566                 status = -ETIMEDOUT;
2567         else
2568                 status = adapter->flash_status;
2569
2570         return status;
2571
2572 err_unlock:
2573         spin_unlock_bh(&adapter->mcc_lock);
2574         return status;
2575 }
2576
2577 static int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2578                                 u16 img_optype, u32 img_offset, u32 crc_offset)
2579 {
2580         struct be_cmd_read_flash_crc *req;
2581         struct be_mcc_wrb *wrb;
2582         int status;
2583
2584         spin_lock_bh(&adapter->mcc_lock);
2585
2586         wrb = wrb_from_mccq(adapter);
2587         if (!wrb) {
2588                 status = -EBUSY;
2589                 goto err;
2590         }
2591         req = embedded_payload(wrb);
2592
2593         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2594                                OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2595                                wrb, NULL);
2596
2597         req->params.op_type = cpu_to_le32(img_optype);
2598         if (img_optype == OPTYPE_OFFSET_SPECIFIED)
2599                 req->params.offset = cpu_to_le32(img_offset + crc_offset);
2600         else
2601                 req->params.offset = cpu_to_le32(crc_offset);
2602
2603         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2604         req->params.data_buf_size = cpu_to_le32(0x4);
2605
2606         status = be_mcc_notify_wait(adapter);
2607         if (!status)
2608                 memcpy(flashed_crc, req->crc, 4);
2609
2610 err:
2611         spin_unlock_bh(&adapter->mcc_lock);
2612         return status;
2613 }
2614
2615 static char flash_cookie[2][16] = {"*** SE FLAS", "H DIRECTORY *** "};
2616
2617 static bool phy_flashing_required(struct be_adapter *adapter)
2618 {
2619         return (adapter->phy.phy_type == PHY_TYPE_TN_8022 &&
2620                 adapter->phy.interface_type == PHY_TYPE_BASET_10GB);
2621 }
2622
2623 static bool is_comp_in_ufi(struct be_adapter *adapter,
2624                            struct flash_section_info *fsec, int type)
2625 {
2626         int i = 0, img_type = 0;
2627         struct flash_section_info_g2 *fsec_g2 = NULL;
2628
2629         if (BE2_chip(adapter))
2630                 fsec_g2 = (struct flash_section_info_g2 *)fsec;
2631
2632         for (i = 0; i < MAX_FLASH_COMP; i++) {
2633                 if (fsec_g2)
2634                         img_type = le32_to_cpu(fsec_g2->fsec_entry[i].type);
2635                 else
2636                         img_type = le32_to_cpu(fsec->fsec_entry[i].type);
2637
2638                 if (img_type == type)
2639                         return true;
2640         }
2641         return false;
2642 }
2643
2644 static struct flash_section_info *get_fsec_info(struct be_adapter *adapter,
2645                                                 int header_size,
2646                                                 const struct firmware *fw)
2647 {
2648         struct flash_section_info *fsec = NULL;
2649         const u8 *p = fw->data;
2650
2651         p += header_size;
2652         while (p < (fw->data + fw->size)) {
2653                 fsec = (struct flash_section_info *)p;
2654                 if (!memcmp(flash_cookie, fsec->cookie, sizeof(flash_cookie)))
2655                         return fsec;
2656                 p += 32;
2657         }
2658         return NULL;
2659 }
2660
2661 static int be_check_flash_crc(struct be_adapter *adapter, const u8 *p,
2662                               u32 img_offset, u32 img_size, int hdr_size,
2663                               u16 img_optype, bool *crc_match)
2664 {
2665         u32 crc_offset;
2666         int status;
2667         u8 crc[4];
2668
2669         status = be_cmd_get_flash_crc(adapter, crc, img_optype, img_offset,
2670                                       img_size - 4);
2671         if (status)
2672                 return status;
2673
2674         crc_offset = hdr_size + img_offset + img_size - 4;
2675
2676         /* Skip flashing, if crc of flashed region matches */
2677         if (!memcmp(crc, p + crc_offset, 4))
2678                 *crc_match = true;
2679         else
2680                 *crc_match = false;
2681
2682         return status;
2683 }
2684
2685 static int be_flash(struct be_adapter *adapter, const u8 *img,
2686                     struct be_dma_mem *flash_cmd, int optype, int img_size,
2687                     u32 img_offset)
2688 {
2689         u32 flash_op, num_bytes, total_bytes = img_size, bytes_sent = 0;
2690         struct be_cmd_write_flashrom *req = flash_cmd->va;
2691         int status;
2692
2693         while (total_bytes) {
2694                 num_bytes = min_t(u32, 32 * 1024, total_bytes);
2695
2696                 total_bytes -= num_bytes;
2697
2698                 if (!total_bytes) {
2699                         if (optype == OPTYPE_PHY_FW)
2700                                 flash_op = FLASHROM_OPER_PHY_FLASH;
2701                         else
2702                                 flash_op = FLASHROM_OPER_FLASH;
2703                 } else {
2704                         if (optype == OPTYPE_PHY_FW)
2705                                 flash_op = FLASHROM_OPER_PHY_SAVE;
2706                         else
2707                                 flash_op = FLASHROM_OPER_SAVE;
2708                 }
2709
2710                 memcpy(req->data_buf, img, num_bytes);
2711                 img += num_bytes;
2712                 status = be_cmd_write_flashrom(adapter, flash_cmd, optype,
2713                                                flash_op, img_offset +
2714                                                bytes_sent, num_bytes);
2715                 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST &&
2716                     optype == OPTYPE_PHY_FW)
2717                         break;
2718                 else if (status)
2719                         return status;
2720
2721                 bytes_sent += num_bytes;
2722         }
2723         return 0;
2724 }
2725
2726 /* For BE2, BE3 and BE3-R */
2727 static int be_flash_BEx(struct be_adapter *adapter,
2728                         const struct firmware *fw,
2729                         struct be_dma_mem *flash_cmd, int num_of_images)
2730 {
2731         int img_hdrs_size = (num_of_images * sizeof(struct image_hdr));
2732         struct device *dev = &adapter->pdev->dev;
2733         struct flash_section_info *fsec = NULL;
2734         int status, i, filehdr_size, num_comp;
2735         const struct flash_comp *pflashcomp;
2736         bool crc_match;
2737         const u8 *p;
2738
2739         struct flash_comp gen3_flash_types[] = {
2740                 { BE3_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE,
2741                         BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI},
2742                 { BE3_REDBOOT_START, OPTYPE_REDBOOT,
2743                         BE3_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE},
2744                 { BE3_ISCSI_BIOS_START, OPTYPE_BIOS,
2745                         BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI},
2746                 { BE3_PXE_BIOS_START, OPTYPE_PXE_BIOS,
2747                         BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE},
2748                 { BE3_FCOE_BIOS_START, OPTYPE_FCOE_BIOS,
2749                         BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE},
2750                 { BE3_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP,
2751                         BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI},
2752                 { BE3_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE,
2753                         BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE},
2754                 { BE3_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP,
2755                         BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE},
2756                 { BE3_NCSI_START, OPTYPE_NCSI_FW,
2757                         BE3_NCSI_COMP_MAX_SIZE, IMAGE_NCSI},
2758                 { BE3_PHY_FW_START, OPTYPE_PHY_FW,
2759                         BE3_PHY_FW_COMP_MAX_SIZE, IMAGE_FIRMWARE_PHY}
2760         };
2761
2762         struct flash_comp gen2_flash_types[] = {
2763                 { BE2_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE,
2764                         BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI},
2765                 { BE2_REDBOOT_START, OPTYPE_REDBOOT,
2766                         BE2_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE},
2767                 { BE2_ISCSI_BIOS_START, OPTYPE_BIOS,
2768                         BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI},
2769                 { BE2_PXE_BIOS_START, OPTYPE_PXE_BIOS,
2770                         BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE},
2771                 { BE2_FCOE_BIOS_START, OPTYPE_FCOE_BIOS,
2772                         BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE},
2773                 { BE2_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP,
2774                         BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI},
2775                 { BE2_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE,
2776                         BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE},
2777                 { BE2_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP,
2778                          BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE}
2779         };
2780
2781         if (BE3_chip(adapter)) {
2782                 pflashcomp = gen3_flash_types;
2783                 filehdr_size = sizeof(struct flash_file_hdr_g3);
2784                 num_comp = ARRAY_SIZE(gen3_flash_types);
2785         } else {
2786                 pflashcomp = gen2_flash_types;
2787                 filehdr_size = sizeof(struct flash_file_hdr_g2);
2788                 num_comp = ARRAY_SIZE(gen2_flash_types);
2789                 img_hdrs_size = 0;
2790         }
2791
2792         /* Get flash section info*/
2793         fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw);
2794         if (!fsec) {
2795                 dev_err(dev, "Invalid Cookie. FW image may be corrupted\n");
2796                 return -1;
2797         }
2798         for (i = 0; i < num_comp; i++) {
2799                 if (!is_comp_in_ufi(adapter, fsec, pflashcomp[i].img_type))
2800                         continue;
2801
2802                 if ((pflashcomp[i].optype == OPTYPE_NCSI_FW) &&
2803                     memcmp(adapter->fw_ver, "3.102.148.0", 11) < 0)
2804                         continue;
2805
2806                 if (pflashcomp[i].optype == OPTYPE_PHY_FW  &&
2807                     !phy_flashing_required(adapter))
2808                         continue;
2809
2810                 if (pflashcomp[i].optype == OPTYPE_REDBOOT) {
2811                         status = be_check_flash_crc(adapter, fw->data,
2812                                                     pflashcomp[i].offset,
2813                                                     pflashcomp[i].size,
2814                                                     filehdr_size +
2815                                                     img_hdrs_size,
2816                                                     OPTYPE_REDBOOT, &crc_match);
2817                         if (status) {
2818                                 dev_err(dev,
2819                                         "Could not get CRC for 0x%x region\n",
2820                                         pflashcomp[i].optype);
2821                                 continue;
2822                         }
2823
2824                         if (crc_match)
2825                                 continue;
2826                 }
2827
2828                 p = fw->data + filehdr_size + pflashcomp[i].offset +
2829                         img_hdrs_size;
2830                 if (p + pflashcomp[i].size > fw->data + fw->size)
2831                         return -1;
2832
2833                 status = be_flash(adapter, p, flash_cmd, pflashcomp[i].optype,
2834                                   pflashcomp[i].size, 0);
2835                 if (status) {
2836                         dev_err(dev, "Flashing section type 0x%x failed\n",
2837                                 pflashcomp[i].img_type);
2838                         return status;
2839                 }
2840         }
2841         return 0;
2842 }
2843
2844 static u16 be_get_img_optype(struct flash_section_entry fsec_entry)
2845 {
2846         u32 img_type = le32_to_cpu(fsec_entry.type);
2847         u16 img_optype = le16_to_cpu(fsec_entry.optype);
2848
2849         if (img_optype != 0xFFFF)
2850                 return img_optype;
2851
2852         switch (img_type) {
2853         case IMAGE_FIRMWARE_ISCSI:
2854                 img_optype = OPTYPE_ISCSI_ACTIVE;
2855                 break;
2856         case IMAGE_BOOT_CODE:
2857                 img_optype = OPTYPE_REDBOOT;
2858                 break;
2859         case IMAGE_OPTION_ROM_ISCSI:
2860                 img_optype = OPTYPE_BIOS;
2861                 break;
2862         case IMAGE_OPTION_ROM_PXE:
2863                 img_optype = OPTYPE_PXE_BIOS;
2864                 break;
2865         case IMAGE_OPTION_ROM_FCOE:
2866                 img_optype = OPTYPE_FCOE_BIOS;
2867                 break;
2868         case IMAGE_FIRMWARE_BACKUP_ISCSI:
2869                 img_optype = OPTYPE_ISCSI_BACKUP;
2870                 break;
2871         case IMAGE_NCSI:
2872                 img_optype = OPTYPE_NCSI_FW;
2873                 break;
2874         case IMAGE_FLASHISM_JUMPVECTOR:
2875                 img_optype = OPTYPE_FLASHISM_JUMPVECTOR;
2876                 break;
2877         case IMAGE_FIRMWARE_PHY:
2878                 img_optype = OPTYPE_SH_PHY_FW;
2879                 break;
2880         case IMAGE_REDBOOT_DIR:
2881                 img_optype = OPTYPE_REDBOOT_DIR;
2882                 break;
2883         case IMAGE_REDBOOT_CONFIG:
2884                 img_optype = OPTYPE_REDBOOT_CONFIG;
2885                 break;
2886         case IMAGE_UFI_DIR:
2887                 img_optype = OPTYPE_UFI_DIR;
2888                 break;
2889         default:
2890                 break;
2891         }
2892
2893         return img_optype;
2894 }
2895
2896 static int be_flash_skyhawk(struct be_adapter *adapter,
2897                             const struct firmware *fw,
2898                             struct be_dma_mem *flash_cmd, int num_of_images)
2899 {
2900         int img_hdrs_size = num_of_images * sizeof(struct image_hdr);
2901         bool crc_match, old_fw_img, flash_offset_support = true;
2902         struct device *dev = &adapter->pdev->dev;
2903         struct flash_section_info *fsec = NULL;
2904         u32 img_offset, img_size, img_type;
2905         u16 img_optype, flash_optype;
2906         int status, i, filehdr_size;
2907         const u8 *p;
2908
2909         filehdr_size = sizeof(struct flash_file_hdr_g3);
2910         fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw);
2911         if (!fsec) {
2912                 dev_err(dev, "Invalid Cookie. FW image may be corrupted\n");
2913                 return -EINVAL;
2914         }
2915
2916 retry_flash:
2917         for (i = 0; i < le32_to_cpu(fsec->fsec_hdr.num_images); i++) {
2918                 img_offset = le32_to_cpu(fsec->fsec_entry[i].offset);
2919                 img_size   = le32_to_cpu(fsec->fsec_entry[i].pad_size);
2920                 img_type   = le32_to_cpu(fsec->fsec_entry[i].type);
2921                 img_optype = be_get_img_optype(fsec->fsec_entry[i]);
2922                 old_fw_img = fsec->fsec_entry[i].optype == 0xFFFF;
2923
2924                 if (img_optype == 0xFFFF)
2925                         continue;
2926
2927                 if (flash_offset_support)
2928                         flash_optype = OPTYPE_OFFSET_SPECIFIED;
2929                 else
2930                         flash_optype = img_optype;
2931
2932                 /* Don't bother verifying CRC if an old FW image is being
2933                  * flashed
2934                  */
2935                 if (old_fw_img)
2936                         goto flash;
2937
2938                 status = be_check_flash_crc(adapter, fw->data, img_offset,
2939                                             img_size, filehdr_size +
2940                                             img_hdrs_size, flash_optype,
2941                                             &crc_match);
2942                 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST ||
2943                     base_status(status) == MCC_STATUS_ILLEGAL_FIELD) {
2944                         /* The current FW image on the card does not support
2945                          * OFFSET based flashing. Retry using older mechanism
2946                          * of OPTYPE based flashing
2947                          */
2948                         if (flash_optype == OPTYPE_OFFSET_SPECIFIED) {
2949                                 flash_offset_support = false;
2950                                 goto retry_flash;
2951                         }
2952
2953                         /* The current FW image on the card does not recognize
2954                          * the new FLASH op_type. The FW download is partially
2955                          * complete. Reboot the server now to enable FW image
2956                          * to recognize the new FLASH op_type. To complete the
2957                          * remaining process, download the same FW again after
2958                          * the reboot.
2959                          */
2960                         dev_err(dev, "Flash incomplete. Reset the server\n");
2961                         dev_err(dev, "Download FW image again after reset\n");
2962                         return -EAGAIN;
2963                 } else if (status) {
2964                         dev_err(dev, "Could not get CRC for 0x%x region\n",
2965                                 img_optype);
2966                         return -EFAULT;
2967                 }
2968
2969                 if (crc_match)
2970                         continue;
2971
2972 flash:
2973                 p = fw->data + filehdr_size + img_offset + img_hdrs_size;
2974                 if (p + img_size > fw->data + fw->size)
2975                         return -1;
2976
2977                 status = be_flash(adapter, p, flash_cmd, flash_optype, img_size,
2978                                   img_offset);
2979
2980                 /* The current FW image on the card does not support OFFSET
2981                  * based flashing. Retry using older mechanism of OPTYPE based
2982                  * flashing
2983                  */
2984                 if (base_status(status) == MCC_STATUS_ILLEGAL_FIELD &&
2985                     flash_optype == OPTYPE_OFFSET_SPECIFIED) {
2986                         flash_offset_support = false;
2987                         goto retry_flash;
2988                 }
2989
2990                 /* For old FW images ignore ILLEGAL_FIELD error or errors on
2991                  * UFI_DIR region
2992                  */
2993                 if (old_fw_img &&
2994                     (base_status(status) == MCC_STATUS_ILLEGAL_FIELD ||
2995                      (img_optype == OPTYPE_UFI_DIR &&
2996                       base_status(status) == MCC_STATUS_FAILED))) {
2997                         continue;
2998                 } else if (status) {
2999                         dev_err(dev, "Flashing section type 0x%x failed\n",
3000                                 img_type);
3001
3002                         switch (addl_status(status)) {
3003                         case MCC_ADDL_STATUS_MISSING_SIGNATURE:
3004                                 dev_err(dev,
3005                                         "Digital signature missing in FW\n");
3006                                 return -EINVAL;
3007                         case MCC_ADDL_STATUS_INVALID_SIGNATURE:
3008                                 dev_err(dev,
3009                                         "Invalid digital signature in FW\n");
3010                                 return -EINVAL;
3011                         default:
3012                                 return -EFAULT;
3013                         }
3014                 }
3015         }
3016         return 0;
3017 }
3018
3019 int lancer_fw_download(struct be_adapter *adapter,
3020                        const struct firmware *fw)
3021 {
3022         struct device *dev = &adapter->pdev->dev;
3023         struct be_dma_mem flash_cmd;
3024         const u8 *data_ptr = NULL;
3025         u8 *dest_image_ptr = NULL;
3026         size_t image_size = 0;
3027         u32 chunk_size = 0;
3028         u32 data_written = 0;
3029         u32 offset = 0;
3030         int status = 0;
3031         u8 add_status = 0;
3032         u8 change_status;
3033
3034         if (!IS_ALIGNED(fw->size, sizeof(u32))) {
3035                 dev_err(dev, "FW image size should be multiple of 4\n");
3036                 return -EINVAL;
3037         }
3038
3039         flash_cmd.size = sizeof(struct lancer_cmd_req_write_object)
3040                                 + LANCER_FW_DOWNLOAD_CHUNK;
3041         flash_cmd.va = dma_zalloc_coherent(dev, flash_cmd.size,
3042                                            &flash_cmd.dma, GFP_KERNEL);
3043         if (!flash_cmd.va)
3044                 return -ENOMEM;
3045
3046         dest_image_ptr = flash_cmd.va +
3047                                 sizeof(struct lancer_cmd_req_write_object);
3048         image_size = fw->size;
3049         data_ptr = fw->data;
3050
3051         while (image_size) {
3052                 chunk_size = min_t(u32, image_size, LANCER_FW_DOWNLOAD_CHUNK);
3053
3054                 /* Copy the image chunk content. */
3055                 memcpy(dest_image_ptr, data_ptr, chunk_size);
3056
3057                 status = lancer_cmd_write_object(adapter, &flash_cmd,
3058                                                  chunk_size, offset,
3059                                                  LANCER_FW_DOWNLOAD_LOCATION,
3060                                                  &data_written, &change_status,
3061                                                  &add_status);
3062                 if (status)
3063                         break;
3064
3065                 offset += data_written;
3066                 data_ptr += data_written;
3067                 image_size -= data_written;
3068         }
3069
3070         if (!status) {
3071                 /* Commit the FW written */
3072                 status = lancer_cmd_write_object(adapter, &flash_cmd,
3073                                                  0, offset,
3074                                                  LANCER_FW_DOWNLOAD_LOCATION,
3075                                                  &data_written, &change_status,
3076                                                  &add_status);
3077         }
3078
3079         dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma);
3080         if (status) {
3081                 dev_err(dev, "Firmware load error\n");
3082                 return be_cmd_status(status);
3083         }
3084
3085         dev_info(dev, "Firmware flashed successfully\n");
3086
3087         if (change_status == LANCER_FW_RESET_NEEDED) {
3088                 dev_info(dev, "Resetting adapter to activate new FW\n");
3089                 status = lancer_physdev_ctrl(adapter,
3090                                              PHYSDEV_CONTROL_FW_RESET_MASK);
3091                 if (status) {
3092                         dev_err(dev, "Adapter busy, could not reset FW\n");
3093                         dev_err(dev, "Reboot server to activate new FW\n");
3094                 }
3095         } else if (change_status != LANCER_NO_RESET_NEEDED) {
3096                 dev_info(dev, "Reboot server to activate new FW\n");
3097         }
3098
3099         return 0;
3100 }
3101
3102 /* Check if the flash image file is compatible with the adapter that
3103  * is being flashed.
3104  */
3105 static bool be_check_ufi_compatibility(struct be_adapter *adapter,
3106                                        struct flash_file_hdr_g3 *fhdr)
3107 {
3108         if (!fhdr) {
3109                 dev_err(&adapter->pdev->dev, "Invalid FW UFI file");
3110                 return false;
3111         }
3112
3113         /* First letter of the build version is used to identify
3114          * which chip this image file is meant for.
3115          */
3116         switch (fhdr->build[0]) {
3117         case BLD_STR_UFI_TYPE_SH:
3118                 if (!skyhawk_chip(adapter))
3119                         return false;
3120                 break;
3121         case BLD_STR_UFI_TYPE_BE3:
3122                 if (!BE3_chip(adapter))
3123                         return false;
3124                 break;
3125         case BLD_STR_UFI_TYPE_BE2:
3126                 if (!BE2_chip(adapter))
3127                         return false;
3128                 break;
3129         default:
3130                 return false;
3131         }
3132
3133         /* In BE3 FW images the "asic_type_rev" field doesn't track the
3134          * asic_rev of the chips it is compatible with.
3135          * When asic_type_rev is 0 the image is compatible only with
3136          * pre-BE3-R chips (asic_rev < 0x10)
3137          */
3138         if (BEx_chip(adapter) && fhdr->asic_type_rev == 0)
3139                 return adapter->asic_rev < 0x10;
3140         else
3141                 return (fhdr->asic_type_rev >= adapter->asic_rev);
3142 }
3143
3144 int be_fw_download(struct be_adapter *adapter, const struct firmware *fw)
3145 {
3146         struct device *dev = &adapter->pdev->dev;
3147         struct flash_file_hdr_g3 *fhdr3;
3148         struct image_hdr *img_hdr_ptr;
3149         int status = 0, i, num_imgs;
3150         struct be_dma_mem flash_cmd;
3151
3152         fhdr3 = (struct flash_file_hdr_g3 *)fw->data;
3153         if (!be_check_ufi_compatibility(adapter, fhdr3)) {
3154                 dev_err(dev, "Flash image is not compatible with adapter\n");
3155                 return -EINVAL;
3156         }
3157
3158         flash_cmd.size = sizeof(struct be_cmd_write_flashrom);
3159         flash_cmd.va = dma_zalloc_coherent(dev, flash_cmd.size, &flash_cmd.dma,
3160                                            GFP_KERNEL);
3161         if (!flash_cmd.va)
3162                 return -ENOMEM;
3163
3164         num_imgs = le32_to_cpu(fhdr3->num_imgs);
3165         for (i = 0; i < num_imgs; i++) {
3166                 img_hdr_ptr = (struct image_hdr *)(fw->data +
3167                                 (sizeof(struct flash_file_hdr_g3) +
3168                                  i * sizeof(struct image_hdr)));
3169                 if (!BE2_chip(adapter) &&
3170                     le32_to_cpu(img_hdr_ptr->imageid) != 1)
3171                         continue;
3172
3173                 if (skyhawk_chip(adapter))
3174                         status = be_flash_skyhawk(adapter, fw, &flash_cmd,
3175                                                   num_imgs);
3176                 else
3177                         status = be_flash_BEx(adapter, fw, &flash_cmd,
3178                                               num_imgs);
3179         }
3180
3181         dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma);
3182         if (!status)
3183                 dev_info(dev, "Firmware flashed successfully\n");
3184
3185         return status;
3186 }
3187
3188 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
3189                             struct be_dma_mem *nonemb_cmd)
3190 {
3191         struct be_mcc_wrb *wrb;
3192         struct be_cmd_req_acpi_wol_magic_config *req;
3193         int status;
3194
3195         spin_lock_bh(&adapter->mcc_lock);
3196
3197         wrb = wrb_from_mccq(adapter);
3198         if (!wrb) {
3199                 status = -EBUSY;
3200                 goto err;
3201         }
3202         req = nonemb_cmd->va;
3203
3204         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
3205                                OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req),
3206                                wrb, nonemb_cmd);
3207         memcpy(req->magic_mac, mac, ETH_ALEN);
3208
3209         status = be_mcc_notify_wait(adapter);
3210
3211 err:
3212         spin_unlock_bh(&adapter->mcc_lock);
3213         return status;
3214 }
3215
3216 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
3217                         u8 loopback_type, u8 enable)
3218 {
3219         struct be_mcc_wrb *wrb;
3220         struct be_cmd_req_set_lmode *req;
3221         int status;
3222
3223         if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
3224                             CMD_SUBSYSTEM_LOWLEVEL))
3225                 return -EPERM;
3226
3227         spin_lock_bh(&adapter->mcc_lock);
3228
3229         wrb = wrb_from_mccq(adapter);
3230         if (!wrb) {
3231                 status = -EBUSY;
3232                 goto err_unlock;
3233         }
3234
3235         req = embedded_payload(wrb);
3236
3237         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
3238                                OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req),
3239                                wrb, NULL);
3240
3241         req->src_port = port_num;
3242         req->dest_port = port_num;
3243         req->loopback_type = loopback_type;
3244         req->loopback_state = enable;
3245
3246         status = be_mcc_notify(adapter);
3247         if (status)
3248                 goto err_unlock;
3249
3250         spin_unlock_bh(&adapter->mcc_lock);
3251
3252         if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
3253                                          msecs_to_jiffies(SET_LB_MODE_TIMEOUT)))
3254                 status = -ETIMEDOUT;
3255
3256         return status;
3257
3258 err_unlock:
3259         spin_unlock_bh(&adapter->mcc_lock);
3260         return status;
3261 }
3262
3263 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
3264                          u32 loopback_type, u32 pkt_size, u32 num_pkts,
3265                          u64 pattern)
3266 {
3267         struct be_mcc_wrb *wrb;
3268         struct be_cmd_req_loopback_test *req;
3269         struct be_cmd_resp_loopback_test *resp;
3270         int status;
3271
3272         if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_LOOPBACK_TEST,
3273                             CMD_SUBSYSTEM_LOWLEVEL))
3274                 return -EPERM;
3275
3276         spin_lock_bh(&adapter->mcc_lock);
3277
3278         wrb = wrb_from_mccq(adapter);
3279         if (!wrb) {
3280                 status = -EBUSY;
3281                 goto err;
3282         }
3283
3284         req = embedded_payload(wrb);
3285
3286         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
3287                                OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb,
3288                                NULL);
3289
3290         req->hdr.timeout = cpu_to_le32(15);
3291         req->pattern = cpu_to_le64(pattern);
3292         req->src_port = cpu_to_le32(port_num);
3293         req->dest_port = cpu_to_le32(port_num);
3294         req->pkt_size = cpu_to_le32(pkt_size);
3295         req->num_pkts = cpu_to_le32(num_pkts);
3296         req->loopback_type = cpu_to_le32(loopback_type);
3297
3298         status = be_mcc_notify(adapter);
3299         if (status)
3300                 goto err;
3301
3302         spin_unlock_bh(&adapter->mcc_lock);
3303
3304         wait_for_completion(&adapter->et_cmd_compl);
3305         resp = embedded_payload(wrb);
3306         status = le32_to_cpu(resp->status);
3307
3308         return status;
3309 err:
3310         spin_unlock_bh(&adapter->mcc_lock);
3311         return status;
3312 }
3313
3314 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
3315                         u32 byte_cnt, struct be_dma_mem *cmd)
3316 {
3317         struct be_mcc_wrb *wrb;
3318         struct be_cmd_req_ddrdma_test *req;
3319         int status;
3320         int i, j = 0;
3321
3322         if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_HOST_DDR_DMA,
3323                             CMD_SUBSYSTEM_LOWLEVEL))
3324                 return -EPERM;
3325
3326         spin_lock_bh(&adapter->mcc_lock);
3327
3328         wrb = wrb_from_mccq(adapter);
3329         if (!wrb) {
3330                 status = -EBUSY;
3331                 goto err;
3332         }
3333         req = cmd->va;
3334         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
3335                                OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb,
3336                                cmd);
3337
3338         req->pattern = cpu_to_le64(pattern);
3339         req->byte_count = cpu_to_le32(byte_cnt);
3340         for (i = 0; i < byte_cnt; i++) {
3341                 req->snd_buff[i] = (u8)(pattern >> (j*8));
3342                 j++;
3343                 if (j > 7)
3344                         j = 0;
3345         }
3346
3347         status = be_mcc_notify_wait(adapter);
3348
3349         if (!status) {
3350                 struct be_cmd_resp_ddrdma_test *resp;
3351
3352                 resp = cmd->va;
3353                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
3354                     resp->snd_err) {
3355                         status = -1;
3356                 }
3357         }
3358
3359 err:
3360         spin_unlock_bh(&adapter->mcc_lock);
3361         return status;
3362 }
3363
3364 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
3365                             struct be_dma_mem *nonemb_cmd)
3366 {
3367         struct be_mcc_wrb *wrb;
3368         struct be_cmd_req_seeprom_read *req;
3369         int status;
3370
3371         spin_lock_bh(&adapter->mcc_lock);
3372
3373         wrb = wrb_from_mccq(adapter);
3374         if (!wrb) {
3375                 status = -EBUSY;
3376                 goto err;
3377         }
3378         req = nonemb_cmd->va;
3379
3380         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3381                                OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
3382                                nonemb_cmd);
3383
3384         status = be_mcc_notify_wait(adapter);
3385
3386 err:
3387         spin_unlock_bh(&adapter->mcc_lock);
3388         return status;
3389 }
3390
3391 int be_cmd_get_phy_info(struct be_adapter *adapter)
3392 {
3393         struct be_mcc_wrb *wrb;
3394         struct be_cmd_req_get_phy_info *req;
3395         struct be_dma_mem cmd;
3396         int status;
3397
3398         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
3399                             CMD_SUBSYSTEM_COMMON))
3400                 return -EPERM;
3401
3402         spin_lock_bh(&adapter->mcc_lock);
3403
3404         wrb = wrb_from_mccq(adapter);
3405         if (!wrb) {
3406                 status = -EBUSY;
3407                 goto err;
3408         }
3409         cmd.size = sizeof(struct be_cmd_req_get_phy_info);
3410         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3411                                      GFP_ATOMIC);
3412         if (!cmd.va) {
3413                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3414                 status = -ENOMEM;
3415                 goto err;
3416         }
3417
3418         req = cmd.va;
3419
3420         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3421                                OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
3422                                wrb, &cmd);
3423
3424         status = be_mcc_notify_wait(adapter);
3425         if (!status) {
3426                 struct be_phy_info *resp_phy_info =
3427                                 cmd.va + sizeof(struct be_cmd_req_hdr);
3428
3429                 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
3430                 adapter->phy.interface_type =
3431                         le16_to_cpu(resp_phy_info->interface_type);
3432                 adapter->phy.auto_speeds_supported =
3433                         le16_to_cpu(resp_phy_info->auto_speeds_supported);
3434                 adapter->phy.fixed_speeds_supported =
3435                         le16_to_cpu(resp_phy_info->fixed_speeds_supported);
3436                 adapter->phy.misc_params =
3437                         le32_to_cpu(resp_phy_info->misc_params);
3438
3439                 if (BE2_chip(adapter)) {
3440                         adapter->phy.fixed_speeds_supported =
3441                                 BE_SUPPORTED_SPEED_10GBPS |
3442                                 BE_SUPPORTED_SPEED_1GBPS;
3443                 }
3444         }
3445         dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
3446 err:
3447         spin_unlock_bh(&adapter->mcc_lock);
3448         return status;
3449 }
3450
3451 static int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
3452 {
3453         struct be_mcc_wrb *wrb;
3454         struct be_cmd_req_set_qos *req;
3455         int status;
3456
3457         spin_lock_bh(&adapter->mcc_lock);
3458
3459         wrb = wrb_from_mccq(adapter);
3460         if (!wrb) {
3461                 status = -EBUSY;
3462                 goto err;
3463         }
3464
3465         req = embedded_payload(wrb);
3466
3467         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3468                                OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
3469
3470         req->hdr.domain = domain;
3471         req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
3472         req->max_bps_nic = cpu_to_le32(bps);
3473
3474         status = be_mcc_notify_wait(adapter);
3475
3476 err:
3477         spin_unlock_bh(&adapter->mcc_lock);
3478         return status;
3479 }
3480
3481 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
3482 {
3483         struct be_mcc_wrb *wrb;
3484         struct be_cmd_req_cntl_attribs *req;
3485         struct be_cmd_resp_cntl_attribs *resp;
3486         int status, i;
3487         int payload_len = max(sizeof(*req), sizeof(*resp));
3488         struct mgmt_controller_attrib *attribs;
3489         struct be_dma_mem attribs_cmd;
3490         u32 *serial_num;
3491
3492         if (mutex_lock_interruptible(&adapter->mbox_lock))
3493                 return -1;
3494
3495         memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
3496         attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
3497         attribs_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3498                                              attribs_cmd.size,
3499                                              &attribs_cmd.dma, GFP_ATOMIC);
3500         if (!attribs_cmd.va) {
3501                 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
3502                 status = -ENOMEM;
3503                 goto err;
3504         }
3505
3506         wrb = wrb_from_mbox(adapter);
3507         if (!wrb) {
3508                 status = -EBUSY;
3509                 goto err;
3510         }
3511         req = attribs_cmd.va;
3512
3513         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3514                                OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len,
3515                                wrb, &attribs_cmd);
3516
3517         status = be_mbox_notify_wait(adapter);
3518         if (!status) {
3519                 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
3520                 adapter->hba_port_num = attribs->hba_attribs.phy_port;
3521                 serial_num = attribs->hba_attribs.controller_serial_number;
3522                 for (i = 0; i < CNTL_SERIAL_NUM_WORDS; i++)
3523                         adapter->serial_num[i] = le32_to_cpu(serial_num[i]) &
3524                                 (BIT_MASK(16) - 1);
3525         }
3526
3527 err:
3528         mutex_unlock(&adapter->mbox_lock);
3529         if (attribs_cmd.va)
3530                 dma_free_coherent(&adapter->pdev->dev, attribs_cmd.size,
3531                                   attribs_cmd.va, attribs_cmd.dma);
3532         return status;
3533 }
3534
3535 /* Uses mbox */
3536 int be_cmd_req_native_mode(struct be_adapter *adapter)
3537 {
3538         struct be_mcc_wrb *wrb;
3539         struct be_cmd_req_set_func_cap *req;
3540         int status;
3541
3542         if (mutex_lock_interruptible(&adapter->mbox_lock))
3543                 return -1;
3544
3545         wrb = wrb_from_mbox(adapter);
3546         if (!wrb) {
3547                 status = -EBUSY;
3548                 goto err;
3549         }
3550
3551         req = embedded_payload(wrb);
3552
3553         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3554                                OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP,
3555                                sizeof(*req), wrb, NULL);
3556
3557         req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
3558                                 CAPABILITY_BE3_NATIVE_ERX_API);
3559         req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
3560
3561         status = be_mbox_notify_wait(adapter);
3562         if (!status) {
3563                 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
3564
3565                 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
3566                                         CAPABILITY_BE3_NATIVE_ERX_API;
3567                 if (!adapter->be3_native)
3568                         dev_warn(&adapter->pdev->dev,
3569                                  "adapter not in advanced mode\n");
3570         }
3571 err:
3572         mutex_unlock(&adapter->mbox_lock);
3573         return status;
3574 }
3575
3576 /* Get privilege(s) for a function */
3577 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
3578                              u32 domain)
3579 {
3580         struct be_mcc_wrb *wrb;
3581         struct be_cmd_req_get_fn_privileges *req;
3582         int status;
3583
3584         spin_lock_bh(&adapter->mcc_lock);
3585
3586         wrb = wrb_from_mccq(adapter);
3587         if (!wrb) {
3588                 status = -EBUSY;
3589                 goto err;
3590         }
3591
3592         req = embedded_payload(wrb);
3593
3594         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3595                                OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
3596                                wrb, NULL);
3597
3598         req->hdr.domain = domain;
3599
3600         status = be_mcc_notify_wait(adapter);
3601         if (!status) {
3602                 struct be_cmd_resp_get_fn_privileges *resp =
3603                                                 embedded_payload(wrb);
3604
3605                 *privilege = le32_to_cpu(resp->privilege_mask);
3606
3607                 /* In UMC mode FW does not return right privileges.
3608                  * Override with correct privilege equivalent to PF.
3609                  */
3610                 if (BEx_chip(adapter) && be_is_mc(adapter) &&
3611                     be_physfn(adapter))
3612                         *privilege = MAX_PRIVILEGES;
3613         }
3614
3615 err:
3616         spin_unlock_bh(&adapter->mcc_lock);
3617         return status;
3618 }
3619
3620 /* Set privilege(s) for a function */
3621 int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
3622                              u32 domain)
3623 {
3624         struct be_mcc_wrb *wrb;
3625         struct be_cmd_req_set_fn_privileges *req;
3626         int status;
3627
3628         spin_lock_bh(&adapter->mcc_lock);
3629
3630         wrb = wrb_from_mccq(adapter);
3631         if (!wrb) {
3632                 status = -EBUSY;
3633                 goto err;
3634         }
3635
3636         req = embedded_payload(wrb);
3637         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3638                                OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
3639                                wrb, NULL);
3640         req->hdr.domain = domain;
3641         if (lancer_chip(adapter))
3642                 req->privileges_lancer = cpu_to_le32(privileges);
3643         else
3644                 req->privileges = cpu_to_le32(privileges);
3645
3646         status = be_mcc_notify_wait(adapter);
3647 err:
3648         spin_unlock_bh(&adapter->mcc_lock);
3649         return status;
3650 }
3651
3652 /* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
3653  * pmac_id_valid: false => pmac_id or MAC address is requested.
3654  *                If pmac_id is returned, pmac_id_valid is returned as true
3655  */
3656 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
3657                              bool *pmac_id_valid, u32 *pmac_id, u32 if_handle,
3658                              u8 domain)
3659 {
3660         struct be_mcc_wrb *wrb;
3661         struct be_cmd_req_get_mac_list *req;
3662         int status;
3663         int mac_count;
3664         struct be_dma_mem get_mac_list_cmd;
3665         int i;
3666
3667         memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
3668         get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
3669         get_mac_list_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3670                                                   get_mac_list_cmd.size,
3671                                                   &get_mac_list_cmd.dma,
3672                                                   GFP_ATOMIC);
3673
3674         if (!get_mac_list_cmd.va) {
3675                 dev_err(&adapter->pdev->dev,
3676                         "Memory allocation failure during GET_MAC_LIST\n");
3677                 return -ENOMEM;
3678         }
3679
3680         spin_lock_bh(&adapter->mcc_lock);
3681
3682         wrb = wrb_from_mccq(adapter);
3683         if (!wrb) {
3684                 status = -EBUSY;
3685                 goto out;
3686         }
3687
3688         req = get_mac_list_cmd.va;
3689
3690         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3691                                OPCODE_COMMON_GET_MAC_LIST,
3692                                get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
3693         req->hdr.domain = domain;
3694         req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
3695         if (*pmac_id_valid) {
3696                 req->mac_id = cpu_to_le32(*pmac_id);
3697                 req->iface_id = cpu_to_le16(if_handle);
3698                 req->perm_override = 0;
3699         } else {
3700                 req->perm_override = 1;
3701         }
3702
3703         status = be_mcc_notify_wait(adapter);
3704         if (!status) {
3705                 struct be_cmd_resp_get_mac_list *resp =
3706                                                 get_mac_list_cmd.va;
3707
3708                 if (*pmac_id_valid) {
3709                         memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
3710                                ETH_ALEN);
3711                         goto out;
3712                 }
3713
3714                 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
3715                 /* Mac list returned could contain one or more active mac_ids
3716                  * or one or more true or pseudo permanent mac addresses.
3717                  * If an active mac_id is present, return first active mac_id
3718                  * found.
3719                  */
3720                 for (i = 0; i < mac_count; i++) {
3721                         struct get_list_macaddr *mac_entry;
3722                         u16 mac_addr_size;
3723                         u32 mac_id;
3724
3725                         mac_entry = &resp->macaddr_list[i];
3726                         mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
3727                         /* mac_id is a 32 bit value and mac_addr size
3728                          * is 6 bytes
3729                          */
3730                         if (mac_addr_size == sizeof(u32)) {
3731                                 *pmac_id_valid = true;
3732                                 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
3733                                 *pmac_id = le32_to_cpu(mac_id);
3734                                 goto out;
3735                         }
3736                 }
3737                 /* If no active mac_id found, return first mac addr */
3738                 *pmac_id_valid = false;
3739                 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
3740                        ETH_ALEN);
3741         }
3742
3743 out:
3744         spin_unlock_bh(&adapter->mcc_lock);
3745         dma_free_coherent(&adapter->pdev->dev, get_mac_list_cmd.size,
3746                           get_mac_list_cmd.va, get_mac_list_cmd.dma);
3747         return status;
3748 }
3749
3750 int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id,
3751                           u8 *mac, u32 if_handle, bool active, u32 domain)
3752 {
3753         if (!active)
3754                 be_cmd_get_mac_from_list(adapter, mac, &active, &curr_pmac_id,
3755                                          if_handle, domain);
3756         if (BEx_chip(adapter))
3757                 return be_cmd_mac_addr_query(adapter, mac, false,
3758                                              if_handle, curr_pmac_id);
3759         else
3760                 /* Fetch the MAC address using pmac_id */
3761                 return be_cmd_get_mac_from_list(adapter, mac, &active,
3762                                                 &curr_pmac_id,
3763                                                 if_handle, domain);
3764 }
3765
3766 int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
3767 {
3768         int status;
3769         bool pmac_valid = false;
3770
3771         eth_zero_addr(mac);
3772
3773         if (BEx_chip(adapter)) {
3774                 if (be_physfn(adapter))
3775                         status = be_cmd_mac_addr_query(adapter, mac, true, 0,
3776                                                        0);
3777                 else
3778                         status = be_cmd_mac_addr_query(adapter, mac, false,
3779                                                        adapter->if_handle, 0);
3780         } else {
3781                 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
3782                                                   NULL, adapter->if_handle, 0);
3783         }
3784
3785         return status;
3786 }
3787
3788 /* Uses synchronous MCCQ */
3789 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
3790                         u8 mac_count, u32 domain)
3791 {
3792         struct be_mcc_wrb *wrb;
3793         struct be_cmd_req_set_mac_list *req;
3794         int status;
3795         struct be_dma_mem cmd;
3796
3797         memset(&cmd, 0, sizeof(struct be_dma_mem));
3798         cmd.size = sizeof(struct be_cmd_req_set_mac_list);
3799         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3800                                      GFP_KERNEL);
3801         if (!cmd.va)
3802                 return -ENOMEM;
3803
3804         spin_lock_bh(&adapter->mcc_lock);
3805
3806         wrb = wrb_from_mccq(adapter);
3807         if (!wrb) {
3808                 status = -EBUSY;
3809                 goto err;
3810         }
3811
3812         req = cmd.va;
3813         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3814                                OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
3815                                wrb, &cmd);
3816
3817         req->hdr.domain = domain;
3818         req->mac_count = mac_count;
3819         if (mac_count)
3820                 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
3821
3822         status = be_mcc_notify_wait(adapter);
3823
3824 err:
3825         dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
3826         spin_unlock_bh(&adapter->mcc_lock);
3827         return status;
3828 }
3829
3830 /* Wrapper to delete any active MACs and provision the new mac.
3831  * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
3832  * current list are active.
3833  */
3834 int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
3835 {
3836         bool active_mac = false;
3837         u8 old_mac[ETH_ALEN];
3838         u32 pmac_id;
3839         int status;
3840
3841         status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
3842                                           &pmac_id, if_id, dom);
3843
3844         if (!status && active_mac)
3845                 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
3846
3847         return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
3848 }
3849
3850 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
3851                           u32 domain, u16 intf_id, u16 hsw_mode, u8 spoofchk)
3852 {
3853         struct be_mcc_wrb *wrb;
3854         struct be_cmd_req_set_hsw_config *req;
3855         void *ctxt;
3856         int status;
3857
3858         if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_HSW_CONFIG,
3859                             CMD_SUBSYSTEM_COMMON))
3860                 return -EPERM;
3861
3862         spin_lock_bh(&adapter->mcc_lock);
3863
3864         wrb = wrb_from_mccq(adapter);
3865         if (!wrb) {
3866                 status = -EBUSY;
3867                 goto err;
3868         }
3869
3870         req = embedded_payload(wrb);
3871         ctxt = &req->context;
3872
3873         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3874                                OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb,
3875                                NULL);
3876
3877         req->hdr.domain = domain;
3878         AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
3879         if (pvid) {
3880                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
3881                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
3882         }
3883         if (hsw_mode) {
3884                 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id,
3885                               ctxt, adapter->hba_port_num);
3886                 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1);
3887                 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type,
3888                               ctxt, hsw_mode);
3889         }
3890
3891         /* Enable/disable both mac and vlan spoof checking */
3892         if (!BEx_chip(adapter) && spoofchk) {
3893                 AMAP_SET_BITS(struct amap_set_hsw_context, mac_spoofchk,
3894                               ctxt, spoofchk);
3895                 AMAP_SET_BITS(struct amap_set_hsw_context, vlan_spoofchk,
3896                               ctxt, spoofchk);
3897         }
3898
3899         be_dws_cpu_to_le(req->context, sizeof(req->context));
3900         status = be_mcc_notify_wait(adapter);
3901
3902 err:
3903         spin_unlock_bh(&adapter->mcc_lock);
3904         return status;
3905 }
3906
3907 /* Get Hyper switch config */
3908 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
3909                           u32 domain, u16 intf_id, u8 *mode, bool *spoofchk)
3910 {
3911         struct be_mcc_wrb *wrb;
3912         struct be_cmd_req_get_hsw_config *req;
3913         void *ctxt;
3914         int status;
3915         u16 vid;
3916
3917         spin_lock_bh(&adapter->mcc_lock);
3918
3919         wrb = wrb_from_mccq(adapter);
3920         if (!wrb) {
3921                 status = -EBUSY;
3922                 goto err;
3923         }
3924
3925         req = embedded_payload(wrb);
3926         ctxt = &req->context;
3927
3928         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3929                                OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb,
3930                                NULL);
3931
3932         req->hdr.domain = domain;
3933         AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3934                       ctxt, intf_id);
3935         AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
3936
3937         if (!BEx_chip(adapter) && mode) {
3938                 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3939                               ctxt, adapter->hba_port_num);
3940                 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1);
3941         }
3942         be_dws_cpu_to_le(req->context, sizeof(req->context));
3943
3944         status = be_mcc_notify_wait(adapter);
3945         if (!status) {
3946                 struct be_cmd_resp_get_hsw_config *resp =
3947                                                 embedded_payload(wrb);
3948
3949                 be_dws_le_to_cpu(&resp->context, sizeof(resp->context));
3950                 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3951                                     pvid, &resp->context);
3952                 if (pvid)
3953                         *pvid = le16_to_cpu(vid);
3954                 if (mode)
3955                         *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3956                                               port_fwd_type, &resp->context);
3957                 if (spoofchk)
3958                         *spoofchk =
3959                                 AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3960                                               spoofchk, &resp->context);
3961         }
3962
3963 err:
3964         spin_unlock_bh(&adapter->mcc_lock);
3965         return status;
3966 }
3967
3968 static bool be_is_wol_excluded(struct be_adapter *adapter)
3969 {
3970         struct pci_dev *pdev = adapter->pdev;
3971
3972         if (be_virtfn(adapter))
3973                 return true;
3974
3975         switch (pdev->subsystem_device) {
3976         case OC_SUBSYS_DEVICE_ID1:
3977         case OC_SUBSYS_DEVICE_ID2:
3978         case OC_SUBSYS_DEVICE_ID3:
3979         case OC_SUBSYS_DEVICE_ID4:
3980                 return true;
3981         default:
3982                 return false;
3983         }
3984 }
3985
3986 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
3987 {
3988         struct be_mcc_wrb *wrb;
3989         struct be_cmd_req_acpi_wol_magic_config_v1 *req;
3990         int status = 0;
3991         struct be_dma_mem cmd;
3992
3993         if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3994                             CMD_SUBSYSTEM_ETH))
3995                 return -EPERM;
3996
3997         if (be_is_wol_excluded(adapter))
3998                 return status;
3999
4000         if (mutex_lock_interruptible(&adapter->mbox_lock))
4001                 return -1;
4002
4003         memset(&cmd, 0, sizeof(struct be_dma_mem));
4004         cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
4005         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4006                                      GFP_ATOMIC);
4007         if (!cmd.va) {
4008                 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
4009                 status = -ENOMEM;
4010                 goto err;
4011         }
4012
4013         wrb = wrb_from_mbox(adapter);
4014         if (!wrb) {
4015                 status = -EBUSY;
4016                 goto err;
4017         }
4018
4019         req = cmd.va;
4020
4021         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
4022                                OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
4023                                sizeof(*req), wrb, &cmd);
4024
4025         req->hdr.version = 1;
4026         req->query_options = BE_GET_WOL_CAP;
4027
4028         status = be_mbox_notify_wait(adapter);
4029         if (!status) {
4030                 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
4031
4032                 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *)cmd.va;
4033
4034                 adapter->wol_cap = resp->wol_settings;
4035
4036                 /* Non-zero macaddr indicates WOL is enabled */
4037                 if (adapter->wol_cap & BE_WOL_CAP &&
4038                     !is_zero_ether_addr(resp->magic_mac))
4039                         adapter->wol_en = true;
4040         }
4041 err:
4042         mutex_unlock(&adapter->mbox_lock);
4043         if (cmd.va)
4044                 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4045                                   cmd.dma);
4046         return status;
4047
4048 }
4049
4050 int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level)
4051 {
4052         struct be_dma_mem extfat_cmd;
4053         struct be_fat_conf_params *cfgs;
4054         int status;
4055         int i, j;
4056
4057         memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
4058         extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
4059         extfat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
4060                                             extfat_cmd.size, &extfat_cmd.dma,
4061                                             GFP_ATOMIC);
4062         if (!extfat_cmd.va)
4063                 return -ENOMEM;
4064
4065         status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
4066         if (status)
4067                 goto err;
4068
4069         cfgs = (struct be_fat_conf_params *)
4070                         (extfat_cmd.va + sizeof(struct be_cmd_resp_hdr));
4071         for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) {
4072                 u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes);
4073
4074                 for (j = 0; j < num_modes; j++) {
4075                         if (cfgs->module[i].trace_lvl[j].mode == MODE_UART)
4076                                 cfgs->module[i].trace_lvl[j].dbg_lvl =
4077                                                         cpu_to_le32(level);
4078                 }
4079         }
4080
4081         status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd, cfgs);
4082 err:
4083         dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
4084                           extfat_cmd.dma);
4085         return status;
4086 }
4087
4088 int be_cmd_get_fw_log_level(struct be_adapter *adapter)
4089 {
4090         struct be_dma_mem extfat_cmd;
4091         struct be_fat_conf_params *cfgs;
4092         int status, j;
4093         int level = 0;
4094
4095         memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
4096         extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
4097         extfat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
4098                                             extfat_cmd.size, &extfat_cmd.dma,
4099                                             GFP_ATOMIC);
4100
4101         if (!extfat_cmd.va) {
4102                 dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
4103                         __func__);
4104                 goto err;
4105         }
4106
4107         status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
4108         if (!status) {
4109                 cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
4110                                                 sizeof(struct be_cmd_resp_hdr));
4111
4112                 for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) {
4113                         if (cfgs->module[0].trace_lvl[j].mode == MODE_UART)
4114                                 level = cfgs->module[0].trace_lvl[j].dbg_lvl;
4115                 }
4116         }
4117         dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
4118                           extfat_cmd.dma);
4119 err:
4120         return level;
4121 }
4122
4123 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
4124                                    struct be_dma_mem *cmd)
4125 {
4126         struct be_mcc_wrb *wrb;
4127         struct be_cmd_req_get_ext_fat_caps *req;
4128         int status;
4129
4130         if (mutex_lock_interruptible(&adapter->mbox_lock))
4131                 return -1;
4132
4133         wrb = wrb_from_mbox(adapter);
4134         if (!wrb) {
4135                 status = -EBUSY;
4136                 goto err;
4137         }
4138
4139         req = cmd->va;
4140         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4141                                OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
4142                                cmd->size, wrb, cmd);
4143         req->parameter_type = cpu_to_le32(1);
4144
4145         status = be_mbox_notify_wait(adapter);
4146 err:
4147         mutex_unlock(&adapter->mbox_lock);
4148         return status;
4149 }
4150
4151 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
4152                                    struct be_dma_mem *cmd,
4153                                    struct be_fat_conf_params *configs)
4154 {
4155         struct be_mcc_wrb *wrb;
4156         struct be_cmd_req_set_ext_fat_caps *req;
4157         int status;
4158
4159         spin_lock_bh(&adapter->mcc_lock);
4160
4161         wrb = wrb_from_mccq(adapter);
4162         if (!wrb) {
4163                 status = -EBUSY;
4164                 goto err;
4165         }
4166
4167         req = cmd->va;
4168         memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
4169         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4170                                OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
4171                                cmd->size, wrb, cmd);
4172
4173         status = be_mcc_notify_wait(adapter);
4174 err:
4175         spin_unlock_bh(&adapter->mcc_lock);
4176         return status;
4177 }
4178
4179 int be_cmd_query_port_name(struct be_adapter *adapter)
4180 {
4181         struct be_cmd_req_get_port_name *req;
4182         struct be_mcc_wrb *wrb;
4183         int status;
4184
4185         if (mutex_lock_interruptible(&adapter->mbox_lock))
4186                 return -1;
4187
4188         wrb = wrb_from_mbox(adapter);
4189         req = embedded_payload(wrb);
4190
4191         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4192                                OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
4193                                NULL);
4194         if (!BEx_chip(adapter))
4195                 req->hdr.version = 1;
4196
4197         status = be_mbox_notify_wait(adapter);
4198         if (!status) {
4199                 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
4200
4201                 adapter->port_name = resp->port_name[adapter->hba_port_num];
4202         } else {
4203                 adapter->port_name = adapter->hba_port_num + '0';
4204         }
4205
4206         mutex_unlock(&adapter->mbox_lock);
4207         return status;
4208 }
4209
4210 /* When more than 1 NIC descriptor is present in the descriptor list,
4211  * the caller must specify the pf_num to obtain the NIC descriptor
4212  * corresponding to its pci function.
4213  * get_vft must be true when the caller wants the VF-template desc of the
4214  * PF-pool.
4215  * The pf_num should be set to PF_NUM_IGNORE when the caller knows
4216  * that only it's NIC descriptor is present in the descriptor list.
4217  */
4218 static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
4219                                                bool get_vft, u8 pf_num)
4220 {
4221         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4222         struct be_nic_res_desc *nic;
4223         int i;
4224
4225         for (i = 0; i < desc_count; i++) {
4226                 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
4227                     hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1) {
4228                         nic = (struct be_nic_res_desc *)hdr;
4229
4230                         if ((pf_num == PF_NUM_IGNORE ||
4231                              nic->pf_num == pf_num) &&
4232                             (!get_vft || nic->flags & BIT(VFT_SHIFT)))
4233                                 return nic;
4234                 }
4235                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4236                 hdr = (void *)hdr + hdr->desc_len;
4237         }
4238         return NULL;
4239 }
4240
4241 static struct be_nic_res_desc *be_get_vft_desc(u8 *buf, u32 desc_count,
4242                                                u8 pf_num)
4243 {
4244         return be_get_nic_desc(buf, desc_count, true, pf_num);
4245 }
4246
4247 static struct be_nic_res_desc *be_get_func_nic_desc(u8 *buf, u32 desc_count,
4248                                                     u8 pf_num)
4249 {
4250         return be_get_nic_desc(buf, desc_count, false, pf_num);
4251 }
4252
4253 static struct be_pcie_res_desc *be_get_pcie_desc(u8 *buf, u32 desc_count,
4254                                                  u8 pf_num)
4255 {
4256         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4257         struct be_pcie_res_desc *pcie;
4258         int i;
4259
4260         for (i = 0; i < desc_count; i++) {
4261                 if (hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
4262                     hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1) {
4263                         pcie = (struct be_pcie_res_desc *)hdr;
4264                         if (pcie->pf_num == pf_num)
4265                                 return pcie;
4266                 }
4267
4268                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4269                 hdr = (void *)hdr + hdr->desc_len;
4270         }
4271         return NULL;
4272 }
4273
4274 static struct be_port_res_desc *be_get_port_desc(u8 *buf, u32 desc_count)
4275 {
4276         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4277         int i;
4278
4279         for (i = 0; i < desc_count; i++) {
4280                 if (hdr->desc_type == PORT_RESOURCE_DESC_TYPE_V1)
4281                         return (struct be_port_res_desc *)hdr;
4282
4283                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4284                 hdr = (void *)hdr + hdr->desc_len;
4285         }
4286         return NULL;
4287 }
4288
4289 static void be_copy_nic_desc(struct be_resources *res,
4290                              struct be_nic_res_desc *desc)
4291 {
4292         res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count);
4293         res->max_vlans = le16_to_cpu(desc->vlan_count);
4294         res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
4295         res->max_tx_qs = le16_to_cpu(desc->txq_count);
4296         res->max_rss_qs = le16_to_cpu(desc->rssq_count);
4297         res->max_rx_qs = le16_to_cpu(desc->rq_count);
4298         res->max_evt_qs = le16_to_cpu(desc->eq_count);
4299         res->max_cq_count = le16_to_cpu(desc->cq_count);
4300         res->max_iface_count = le16_to_cpu(desc->iface_count);
4301         res->max_mcc_count = le16_to_cpu(desc->mcc_count);
4302         /* Clear flags that driver is not interested in */
4303         res->if_cap_flags = le32_to_cpu(desc->cap_flags) &
4304                                 BE_IF_CAP_FLAGS_WANT;
4305 }
4306
4307 /* Uses Mbox */
4308 int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res)
4309 {
4310         struct be_mcc_wrb *wrb;
4311         struct be_cmd_req_get_func_config *req;
4312         int status;
4313         struct be_dma_mem cmd;
4314
4315         if (mutex_lock_interruptible(&adapter->mbox_lock))
4316                 return -1;
4317
4318         memset(&cmd, 0, sizeof(struct be_dma_mem));
4319         cmd.size = sizeof(struct be_cmd_resp_get_func_config);
4320         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4321                                      GFP_ATOMIC);
4322         if (!cmd.va) {
4323                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
4324                 status = -ENOMEM;
4325                 goto err;
4326         }
4327
4328         wrb = wrb_from_mbox(adapter);
4329         if (!wrb) {
4330                 status = -EBUSY;
4331                 goto err;
4332         }
4333
4334         req = cmd.va;
4335
4336         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4337                                OPCODE_COMMON_GET_FUNC_CONFIG,
4338                                cmd.size, wrb, &cmd);
4339
4340         if (skyhawk_chip(adapter))
4341                 req->hdr.version = 1;
4342
4343         status = be_mbox_notify_wait(adapter);
4344         if (!status) {
4345                 struct be_cmd_resp_get_func_config *resp = cmd.va;
4346                 u32 desc_count = le32_to_cpu(resp->desc_count);
4347                 struct be_nic_res_desc *desc;
4348
4349                 /* GET_FUNC_CONFIG returns resource descriptors of the
4350                  * current function only. So, pf_num should be set to
4351                  * PF_NUM_IGNORE.
4352                  */
4353                 desc = be_get_func_nic_desc(resp->func_param, desc_count,
4354                                             PF_NUM_IGNORE);
4355                 if (!desc) {
4356                         status = -EINVAL;
4357                         goto err;
4358                 }
4359
4360                 /* Store pf_num & vf_num for later use in GET_PROFILE_CONFIG */
4361                 adapter->pf_num = desc->pf_num;
4362                 adapter->vf_num = desc->vf_num;
4363
4364                 if (res)
4365                         be_copy_nic_desc(res, desc);
4366         }
4367 err:
4368         mutex_unlock(&adapter->mbox_lock);
4369         if (cmd.va)
4370                 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4371                                   cmd.dma);
4372         return status;
4373 }
4374
4375 /* This routine returns a list of all the NIC PF_nums in the adapter */
4376 u16 be_get_nic_pf_num_list(u8 *buf, u32 desc_count, u16 *nic_pf_nums)
4377 {
4378         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4379         struct be_pcie_res_desc *pcie = NULL;
4380         int i;
4381         u16 nic_pf_count = 0;
4382
4383         for (i = 0; i < desc_count; i++) {
4384                 if (hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
4385                     hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1) {
4386                         pcie = (struct be_pcie_res_desc *)hdr;
4387                         if (pcie->pf_state && (pcie->pf_type == MISSION_NIC ||
4388                                                pcie->pf_type == MISSION_RDMA)) {
4389                                 nic_pf_nums[nic_pf_count++] = pcie->pf_num;
4390                         }
4391                 }
4392
4393                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4394                 hdr = (void *)hdr + hdr->desc_len;
4395         }
4396         return nic_pf_count;
4397 }
4398
4399 /* Will use MBOX only if MCCQ has not been created */
4400 int be_cmd_get_profile_config(struct be_adapter *adapter,
4401                               struct be_resources *res,
4402                               struct be_port_resources *port_res,
4403                               u8 profile_type, u8 query, u8 domain)
4404 {
4405         struct be_cmd_resp_get_profile_config *resp;
4406         struct be_cmd_req_get_profile_config *req;
4407         struct be_nic_res_desc *vf_res;
4408         struct be_pcie_res_desc *pcie;
4409         struct be_port_res_desc *port;
4410         struct be_nic_res_desc *nic;
4411         struct be_mcc_wrb wrb = {0};
4412         struct be_dma_mem cmd;
4413         u16 desc_count;
4414         int status;
4415
4416         memset(&cmd, 0, sizeof(struct be_dma_mem));
4417         cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
4418         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4419                                      GFP_ATOMIC);
4420         if (!cmd.va)
4421                 return -ENOMEM;
4422
4423         req = cmd.va;
4424         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4425                                OPCODE_COMMON_GET_PROFILE_CONFIG,
4426                                cmd.size, &wrb, &cmd);
4427
4428         if (!lancer_chip(adapter))
4429                 req->hdr.version = 1;
4430         req->type = profile_type;
4431         req->hdr.domain = domain;
4432
4433         /* When QUERY_MODIFIABLE_FIELDS_TYPE bit is set, cmd returns the
4434          * descriptors with all bits set to "1" for the fields which can be
4435          * modified using SET_PROFILE_CONFIG cmd.
4436          */
4437         if (query == RESOURCE_MODIFIABLE)
4438                 req->type |= QUERY_MODIFIABLE_FIELDS_TYPE;
4439
4440         status = be_cmd_notify_wait(adapter, &wrb);
4441         if (status)
4442                 goto err;
4443
4444         resp = cmd.va;
4445         desc_count = le16_to_cpu(resp->desc_count);
4446
4447         if (port_res) {
4448                 u16 nic_pf_cnt = 0, i;
4449                 u16 nic_pf_num_list[MAX_NIC_FUNCS];
4450
4451                 nic_pf_cnt = be_get_nic_pf_num_list(resp->func_param,
4452                                                     desc_count,
4453                                                     nic_pf_num_list);
4454
4455                 for (i = 0; i < nic_pf_cnt; i++) {
4456                         nic = be_get_func_nic_desc(resp->func_param, desc_count,
4457                                                    nic_pf_num_list[i]);
4458                         if (nic->link_param == adapter->port_num) {
4459                                 port_res->nic_pfs++;
4460                                 pcie = be_get_pcie_desc(resp->func_param,
4461                                                         desc_count,
4462                                                         nic_pf_num_list[i]);
4463                                 port_res->max_vfs += le16_to_cpu(pcie->num_vfs);
4464                         }
4465                 }
4466                 return status;
4467         }
4468
4469         pcie = be_get_pcie_desc(resp->func_param, desc_count,
4470                                 adapter->pf_num);
4471         if (pcie)
4472                 res->max_vfs = le16_to_cpu(pcie->num_vfs);
4473
4474         port = be_get_port_desc(resp->func_param, desc_count);
4475         if (port)
4476                 adapter->mc_type = port->mc_type;
4477
4478         nic = be_get_func_nic_desc(resp->func_param, desc_count,
4479                                    adapter->pf_num);
4480         if (nic)
4481                 be_copy_nic_desc(res, nic);
4482
4483         vf_res = be_get_vft_desc(resp->func_param, desc_count,
4484                                  adapter->pf_num);
4485         if (vf_res)
4486                 res->vf_if_cap_flags = vf_res->cap_flags;
4487 err:
4488         if (cmd.va)
4489                 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4490                                   cmd.dma);
4491         return status;
4492 }
4493
4494 /* Will use MBOX only if MCCQ has not been created */
4495 static int be_cmd_set_profile_config(struct be_adapter *adapter, void *desc,
4496                                      int size, int count, u8 version, u8 domain)
4497 {
4498         struct be_cmd_req_set_profile_config *req;
4499         struct be_mcc_wrb wrb = {0};
4500         struct be_dma_mem cmd;
4501         int status;
4502
4503         memset(&cmd, 0, sizeof(struct be_dma_mem));
4504         cmd.size = sizeof(struct be_cmd_req_set_profile_config);
4505         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4506                                      GFP_ATOMIC);
4507         if (!cmd.va)
4508                 return -ENOMEM;
4509
4510         req = cmd.va;
4511         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4512                                OPCODE_COMMON_SET_PROFILE_CONFIG, cmd.size,
4513                                &wrb, &cmd);
4514         req->hdr.version = version;
4515         req->hdr.domain = domain;
4516         req->desc_count = cpu_to_le32(count);
4517         memcpy(req->desc, desc, size);
4518
4519         status = be_cmd_notify_wait(adapter, &wrb);
4520
4521         if (cmd.va)
4522                 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4523                                   cmd.dma);
4524         return status;
4525 }
4526
4527 /* Mark all fields invalid */
4528 void be_reset_nic_desc(struct be_nic_res_desc *nic)
4529 {
4530         memset(nic, 0, sizeof(*nic));
4531         nic->unicast_mac_count = 0xFFFF;
4532         nic->mcc_count = 0xFFFF;
4533         nic->vlan_count = 0xFFFF;
4534         nic->mcast_mac_count = 0xFFFF;
4535         nic->txq_count = 0xFFFF;
4536         nic->rq_count = 0xFFFF;
4537         nic->rssq_count = 0xFFFF;
4538         nic->lro_count = 0xFFFF;
4539         nic->cq_count = 0xFFFF;
4540         nic->toe_conn_count = 0xFFFF;
4541         nic->eq_count = 0xFFFF;
4542         nic->iface_count = 0xFFFF;
4543         nic->link_param = 0xFF;
4544         nic->channel_id_param = cpu_to_le16(0xF000);
4545         nic->acpi_params = 0xFF;
4546         nic->wol_param = 0x0F;
4547         nic->tunnel_iface_count = 0xFFFF;
4548         nic->direct_tenant_iface_count = 0xFFFF;
4549         nic->bw_min = 0xFFFFFFFF;
4550         nic->bw_max = 0xFFFFFFFF;
4551 }
4552
4553 /* Mark all fields invalid */
4554 static void be_reset_pcie_desc(struct be_pcie_res_desc *pcie)
4555 {
4556         memset(pcie, 0, sizeof(*pcie));
4557         pcie->sriov_state = 0xFF;
4558         pcie->pf_state = 0xFF;
4559         pcie->pf_type = 0xFF;
4560         pcie->num_vfs = 0xFFFF;
4561 }
4562
4563 int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, u16 link_speed,
4564                       u8 domain)
4565 {
4566         struct be_nic_res_desc nic_desc;
4567         u32 bw_percent;
4568         u16 version = 0;
4569
4570         if (BE3_chip(adapter))
4571                 return be_cmd_set_qos(adapter, max_rate / 10, domain);
4572
4573         be_reset_nic_desc(&nic_desc);
4574         nic_desc.pf_num = adapter->pf_num;
4575         nic_desc.vf_num = domain;
4576         nic_desc.bw_min = 0;
4577         if (lancer_chip(adapter)) {
4578                 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
4579                 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
4580                 nic_desc.flags = (1 << QUN_SHIFT) | (1 << IMM_SHIFT) |
4581                                         (1 << NOSV_SHIFT);
4582                 nic_desc.bw_max = cpu_to_le32(max_rate / 10);
4583         } else {
4584                 version = 1;
4585                 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
4586                 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4587                 nic_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
4588                 bw_percent = max_rate ? (max_rate * 100) / link_speed : 100;
4589                 nic_desc.bw_max = cpu_to_le32(bw_percent);
4590         }
4591
4592         return be_cmd_set_profile_config(adapter, &nic_desc,
4593                                          nic_desc.hdr.desc_len,
4594                                          1, version, domain);
4595 }
4596
4597 int be_cmd_set_sriov_config(struct be_adapter *adapter,
4598                             struct be_resources pool_res, u16 num_vfs,
4599                             struct be_resources *vft_res)
4600 {
4601         struct {
4602                 struct be_pcie_res_desc pcie;
4603                 struct be_nic_res_desc nic_vft;
4604         } __packed desc;
4605
4606         /* PF PCIE descriptor */
4607         be_reset_pcie_desc(&desc.pcie);
4608         desc.pcie.hdr.desc_type = PCIE_RESOURCE_DESC_TYPE_V1;
4609         desc.pcie.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4610         desc.pcie.flags = BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
4611         desc.pcie.pf_num = adapter->pdev->devfn;
4612         desc.pcie.sriov_state = num_vfs ? 1 : 0;
4613         desc.pcie.num_vfs = cpu_to_le16(num_vfs);
4614
4615         /* VF NIC Template descriptor */
4616         be_reset_nic_desc(&desc.nic_vft);
4617         desc.nic_vft.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
4618         desc.nic_vft.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4619         desc.nic_vft.flags = vft_res->flags | BIT(VFT_SHIFT) |
4620                              BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
4621         desc.nic_vft.pf_num = adapter->pdev->devfn;
4622         desc.nic_vft.vf_num = 0;
4623         desc.nic_vft.cap_flags = cpu_to_le32(vft_res->vf_if_cap_flags);
4624         desc.nic_vft.rq_count = cpu_to_le16(vft_res->max_rx_qs);
4625         desc.nic_vft.txq_count = cpu_to_le16(vft_res->max_tx_qs);
4626         desc.nic_vft.rssq_count = cpu_to_le16(vft_res->max_rss_qs);
4627         desc.nic_vft.cq_count = cpu_to_le16(vft_res->max_cq_count);
4628
4629         if (vft_res->max_uc_mac)
4630                 desc.nic_vft.unicast_mac_count =
4631                                         cpu_to_le16(vft_res->max_uc_mac);
4632         if (vft_res->max_vlans)
4633                 desc.nic_vft.vlan_count = cpu_to_le16(vft_res->max_vlans);
4634         if (vft_res->max_iface_count)
4635                 desc.nic_vft.iface_count =
4636                                 cpu_to_le16(vft_res->max_iface_count);
4637         if (vft_res->max_mcc_count)
4638                 desc.nic_vft.mcc_count = cpu_to_le16(vft_res->max_mcc_count);
4639
4640         return be_cmd_set_profile_config(adapter, &desc,
4641                                          2 * RESOURCE_DESC_SIZE_V1, 2, 1, 0);
4642 }
4643
4644 int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op)
4645 {
4646         struct be_mcc_wrb *wrb;
4647         struct be_cmd_req_manage_iface_filters *req;
4648         int status;
4649
4650         if (iface == 0xFFFFFFFF)
4651                 return -1;
4652
4653         spin_lock_bh(&adapter->mcc_lock);
4654
4655         wrb = wrb_from_mccq(adapter);
4656         if (!wrb) {
4657                 status = -EBUSY;
4658                 goto err;
4659         }
4660         req = embedded_payload(wrb);
4661
4662         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4663                                OPCODE_COMMON_MANAGE_IFACE_FILTERS, sizeof(*req),
4664                                wrb, NULL);
4665         req->op = op;
4666         req->target_iface_id = cpu_to_le32(iface);
4667
4668         status = be_mcc_notify_wait(adapter);
4669 err:
4670         spin_unlock_bh(&adapter->mcc_lock);
4671         return status;
4672 }
4673
4674 int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port)
4675 {
4676         struct be_port_res_desc port_desc;
4677
4678         memset(&port_desc, 0, sizeof(port_desc));
4679         port_desc.hdr.desc_type = PORT_RESOURCE_DESC_TYPE_V1;
4680         port_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4681         port_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
4682         port_desc.link_num = adapter->hba_port_num;
4683         if (port) {
4684                 port_desc.nv_flags = NV_TYPE_VXLAN | (1 << SOCVID_SHIFT) |
4685                                         (1 << RCVID_SHIFT);
4686                 port_desc.nv_port = swab16(port);
4687         } else {
4688                 port_desc.nv_flags = NV_TYPE_DISABLED;
4689                 port_desc.nv_port = 0;
4690         }
4691
4692         return be_cmd_set_profile_config(adapter, &port_desc,
4693                                          RESOURCE_DESC_SIZE_V1, 1, 1, 0);
4694 }
4695
4696 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
4697                      int vf_num)
4698 {
4699         struct be_mcc_wrb *wrb;
4700         struct be_cmd_req_get_iface_list *req;
4701         struct be_cmd_resp_get_iface_list *resp;
4702         int status;
4703
4704         spin_lock_bh(&adapter->mcc_lock);
4705
4706         wrb = wrb_from_mccq(adapter);
4707         if (!wrb) {
4708                 status = -EBUSY;
4709                 goto err;
4710         }
4711         req = embedded_payload(wrb);
4712
4713         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4714                                OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
4715                                wrb, NULL);
4716         req->hdr.domain = vf_num + 1;
4717
4718         status = be_mcc_notify_wait(adapter);
4719         if (!status) {
4720                 resp = (struct be_cmd_resp_get_iface_list *)req;
4721                 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
4722         }
4723
4724 err:
4725         spin_unlock_bh(&adapter->mcc_lock);
4726         return status;
4727 }
4728
4729 static int lancer_wait_idle(struct be_adapter *adapter)
4730 {
4731 #define SLIPORT_IDLE_TIMEOUT 30
4732         u32 reg_val;
4733         int status = 0, i;
4734
4735         for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
4736                 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
4737                 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
4738                         break;
4739
4740                 ssleep(1);
4741         }
4742
4743         if (i == SLIPORT_IDLE_TIMEOUT)
4744                 status = -1;
4745
4746         return status;
4747 }
4748
4749 int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
4750 {
4751         int status = 0;
4752
4753         status = lancer_wait_idle(adapter);
4754         if (status)
4755                 return status;
4756
4757         iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
4758
4759         return status;
4760 }
4761
4762 /* Routine to check whether dump image is present or not */
4763 bool dump_present(struct be_adapter *adapter)
4764 {
4765         u32 sliport_status = 0;
4766
4767         sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
4768         return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
4769 }
4770
4771 int lancer_initiate_dump(struct be_adapter *adapter)
4772 {
4773         struct device *dev = &adapter->pdev->dev;
4774         int status;
4775
4776         if (dump_present(adapter)) {
4777                 dev_info(dev, "Previous dump not cleared, not forcing dump\n");
4778                 return -EEXIST;
4779         }
4780
4781         /* give firmware reset and diagnostic dump */
4782         status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
4783                                      PHYSDEV_CONTROL_DD_MASK);
4784         if (status < 0) {
4785                 dev_err(dev, "FW reset failed\n");
4786                 return status;
4787         }
4788
4789         status = lancer_wait_idle(adapter);
4790         if (status)
4791                 return status;
4792
4793         if (!dump_present(adapter)) {
4794                 dev_err(dev, "FW dump not generated\n");
4795                 return -EIO;
4796         }
4797
4798         return 0;
4799 }
4800
4801 int lancer_delete_dump(struct be_adapter *adapter)
4802 {
4803         int status;
4804
4805         status = lancer_cmd_delete_object(adapter, LANCER_FW_DUMP_FILE);
4806         return be_cmd_status(status);
4807 }
4808
4809 /* Uses sync mcc */
4810 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
4811 {
4812         struct be_mcc_wrb *wrb;
4813         struct be_cmd_enable_disable_vf *req;
4814         int status;
4815
4816         if (BEx_chip(adapter))
4817                 return 0;
4818
4819         spin_lock_bh(&adapter->mcc_lock);
4820
4821         wrb = wrb_from_mccq(adapter);
4822         if (!wrb) {
4823                 status = -EBUSY;
4824                 goto err;
4825         }
4826
4827         req = embedded_payload(wrb);
4828
4829         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4830                                OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
4831                                wrb, NULL);
4832
4833         req->hdr.domain = domain;
4834         req->enable = 1;
4835         status = be_mcc_notify_wait(adapter);
4836 err:
4837         spin_unlock_bh(&adapter->mcc_lock);
4838         return status;
4839 }
4840
4841 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
4842 {
4843         struct be_mcc_wrb *wrb;
4844         struct be_cmd_req_intr_set *req;
4845         int status;
4846
4847         if (mutex_lock_interruptible(&adapter->mbox_lock))
4848                 return -1;
4849
4850         wrb = wrb_from_mbox(adapter);
4851
4852         req = embedded_payload(wrb);
4853
4854         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4855                                OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
4856                                wrb, NULL);
4857
4858         req->intr_enabled = intr_enable;
4859
4860         status = be_mbox_notify_wait(adapter);
4861
4862         mutex_unlock(&adapter->mbox_lock);
4863         return status;
4864 }
4865
4866 /* Uses MBOX */
4867 int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile_id)
4868 {
4869         struct be_cmd_req_get_active_profile *req;
4870         struct be_mcc_wrb *wrb;
4871         int status;
4872
4873         if (mutex_lock_interruptible(&adapter->mbox_lock))
4874                 return -1;
4875
4876         wrb = wrb_from_mbox(adapter);
4877         if (!wrb) {
4878                 status = -EBUSY;
4879                 goto err;
4880         }
4881
4882         req = embedded_payload(wrb);
4883
4884         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4885                                OPCODE_COMMON_GET_ACTIVE_PROFILE, sizeof(*req),
4886                                wrb, NULL);
4887
4888         status = be_mbox_notify_wait(adapter);
4889         if (!status) {
4890                 struct be_cmd_resp_get_active_profile *resp =
4891                                                         embedded_payload(wrb);
4892
4893                 *profile_id = le16_to_cpu(resp->active_profile_id);
4894         }
4895
4896 err:
4897         mutex_unlock(&adapter->mbox_lock);
4898         return status;
4899 }
4900
4901 int __be_cmd_set_logical_link_config(struct be_adapter *adapter,
4902                                      int link_state, int version, u8 domain)
4903 {
4904         struct be_mcc_wrb *wrb;
4905         struct be_cmd_req_set_ll_link *req;
4906         int status;
4907
4908         spin_lock_bh(&adapter->mcc_lock);
4909
4910         wrb = wrb_from_mccq(adapter);
4911         if (!wrb) {
4912                 status = -EBUSY;
4913                 goto err;
4914         }
4915
4916         req = embedded_payload(wrb);
4917
4918         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4919                                OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG,
4920                                sizeof(*req), wrb, NULL);
4921
4922         req->hdr.version = version;
4923         req->hdr.domain = domain;
4924
4925         if (link_state == IFLA_VF_LINK_STATE_ENABLE ||
4926             link_state == IFLA_VF_LINK_STATE_AUTO)
4927                 req->link_config |= PLINK_ENABLE;
4928
4929         if (link_state == IFLA_VF_LINK_STATE_AUTO)
4930                 req->link_config |= PLINK_TRACK;
4931
4932         status = be_mcc_notify_wait(adapter);
4933 err:
4934         spin_unlock_bh(&adapter->mcc_lock);
4935         return status;
4936 }
4937
4938 int be_cmd_set_logical_link_config(struct be_adapter *adapter,
4939                                    int link_state, u8 domain)
4940 {
4941         int status;
4942
4943         if (BEx_chip(adapter))
4944                 return -EOPNOTSUPP;
4945
4946         status = __be_cmd_set_logical_link_config(adapter, link_state,
4947                                                   2, domain);
4948
4949         /* Version 2 of the command will not be recognized by older FW.
4950          * On such a failure issue version 1 of the command.
4951          */
4952         if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST)
4953                 status = __be_cmd_set_logical_link_config(adapter, link_state,
4954                                                           1, domain);
4955         return status;
4956 }
4957 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
4958                     int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
4959 {
4960         struct be_adapter *adapter = netdev_priv(netdev_handle);
4961         struct be_mcc_wrb *wrb;
4962         struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *)wrb_payload;
4963         struct be_cmd_req_hdr *req;
4964         struct be_cmd_resp_hdr *resp;
4965         int status;
4966
4967         spin_lock_bh(&adapter->mcc_lock);
4968
4969         wrb = wrb_from_mccq(adapter);
4970         if (!wrb) {
4971                 status = -EBUSY;
4972                 goto err;
4973         }
4974         req = embedded_payload(wrb);
4975         resp = embedded_payload(wrb);
4976
4977         be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
4978                                hdr->opcode, wrb_payload_size, wrb, NULL);
4979         memcpy(req, wrb_payload, wrb_payload_size);
4980         be_dws_cpu_to_le(req, wrb_payload_size);
4981
4982         status = be_mcc_notify_wait(adapter);
4983         if (cmd_status)
4984                 *cmd_status = (status & 0xffff);
4985         if (ext_status)
4986                 *ext_status = 0;
4987         memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
4988         be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
4989 err:
4990         spin_unlock_bh(&adapter->mcc_lock);
4991         return status;
4992 }
4993 EXPORT_SYMBOL(be_roce_mcc_cmd);